On 16.09.2008 00:04, Rudolf Marek wrote:
Attached patch fixes at least one issue ;) During the PCI BAR sizing must be the D1F0 bridge without activated I/O and MEM resources, otherwise it will hang whole PCI bus.
U-boot is also disabling the IO/MEM decode when sizing the BARs, dont know why does we not.
Second small change just changes a bit which controls the PSTATECTL logic.
Third change deals with the integrated VGA, which needs to be enabled early, so the VGA_EN is set along the bridges, and PCI K8 resource maps are set correctly. Finally the CPU accessible framebuffer is now disabled as it is not needed.
Signed-off-by: Rudolf Marek r.marek@assembler.cz
The old code had some obvious problems and the new code looks better.
Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
One question about the following snippet, though:
- /* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */
- tmp = pci_read_config8(dev, PCI_COMMAND);
- tmp &= ~0x3;
- pci_write_config8(dev, PCI_COMMAND, tmp);
AFAICS that's a workaround for a hardware bug (more explanations in code comments welcome). Do you reenable I/O and memory decode after BAR sizing?
Regards, Carl-Daniel