Hi all,
As Jordan noted, some device context must be restored. It won't fit in CMOS. Some chipset have additional NVRAM for this S3 resume process.
You have basically two options:
1) Follow the way I did, re-run coreboot and jump later to OS waking vector. Check the patches and the other threads.
2) Save memory config in CMOS, restore memory config, restore memory, re-init the chipset registers (not the leafs) and jump to OS vector. This means that the rest of device state is saved in reserved RAM. To be sure to save actual context you will need also SMM (system management mode trap) and trap the SLP register write, do the backup of all important registers and then go off.
I think easier is 1) Only problem is about memory overwrites. Check the Jason's thread. He is facing similar issues. Maybe put whole coreboot to TOPMEM-something and put low memory trampolines and stack to some place where it don't hurt. You may also save/restore the region during resume.
Rudolf