Dear coreboot readers!
This is the automatic build system of coreboot.
The developer "ruik" checked in revision 6381 to the coreboot repository. This caused the following changes:
Change Log: It adds support for automatic PSS object generation for AMD pre fam Fh CPU. Those CPUs require a hardcoded table, which I managed to rewrite during one particularly boring flight. Too pity it is only for Opteron CPUs. Someone needs to finish the second PDF for All others Athlons and Semprons.
Also it enables the FID/VID changes in SB. Jakllsch had some troubles with that too but on am2 CPU. Those bits are only documented in SB600. They arent in RRG RPR and BDG.
Signed-off-by: Rudolf Marek r.marek@asssembler.cz Acked-by: Stefan Reinauer stefan.reinauer@coreboot.org
Build Log: Compilation of asi:mb_5blgp has been fixed
If something broke during this checkin please be a pain in ruik's neck until the issue is fixed.
If this issue is not fixed within 24h the revision should be backed out.
Best regards, coreboot automatic build system