Zeh, Werner wrote:
there are cases where the calculated and reported timing can be suitable for a given speed in coreboot and a speed switch to HIGH in OS ... will lead to a different timing, worse case not matching the hardware circumstances and therefore ending up in violating the I2C spec.
I think this is an important point, if the OS driver does not calculate different parameters, but relies on what coreboot prepares.
In that case, coreboot should make an effort to prepare correctly for all speeds, possibly by pushing this responsibility onto whoever adds a new mainboard and/or informing the OS driver about which speeds have actually been correctly prepared by coreboot.
coreboot should indeed not prepare for only some of the possible cases at runtime and then stick its head in the sand yolo style.
Does the coreboot code communicate something to the OS driver already?
//Peter