On 01/10/2014 05:05 PM, Gabe Black wrote:
It really depends on how that blob built into the SOC works. On the Tegra chips and on the SOC in the Beaglebone, the amount that's loaded depends on a data structure bundled in with the firmware. On the Beaglebone I told it to load enough of CBFS that it could get the ROM stage out of SRAM without having to talk to the boot media again. Anything beyond that, though, would require talking to the media. On Exynos the blob on the SOC loads another fixed size Samsung provided blob from the boot media which then loads the actual firmware. There it depends on how that blob works. Sometimes the blob loads a fixed size chunk, and sometimes it loads a variably sized blob which is described in a small header. I think the blobs we have in the coreboot repository are one of each, fixed size for the 5250 and variably sized for the 5420.
Gabe, that's the perfect example. We have a different way for each chip because "it really depends on how that blob built into the SOC works". Is that really the case? Every time there's a new ARM SoC we have to reinvent CBFS loading. That sounds wrong. Ron was talking about a unified approach. I think it's time we start doing that now, before it gets messy.
Re Exynos, the SPI code imposes an alignment of 4 bytes. It's cleverly hidden, but that is a little block device logic nonetheless.
Alex