Author: uwe Date: Wed Oct 13 10:21:44 2010 New Revision: 5949 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5949
Log: Convert all Intel i810 boards to CAR.
- Drop "select ROMCC" from the boards, as well as early_mtrr stuff.
- Add "select CACHE_AS_RAM" to socket_PGA370/Kconfig, as well as the usual DCACHE_RAM_BASE and DCACHE_RAM_SIZE variables.
- In socket_PGA370/Makefile.inc add: cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
- Other smaller related fixes.
Abuild-tested and boot-tested on MSI MS-6178.
Signed-off-by: Uwe Hermann uwe@hermann-uwe.de Acked-by: Peter Stuge peter@stuge.se
Modified: trunk/src/cpu/intel/socket_PGA370/Kconfig trunk/src/cpu/intel/socket_PGA370/Makefile.inc trunk/src/cpu/intel/socket_PGA370/socket_PGA370.c trunk/src/mainboard/asus/mew-am/Kconfig trunk/src/mainboard/asus/mew-am/romstage.c trunk/src/mainboard/asus/mew-vm/Kconfig trunk/src/mainboard/asus/mew-vm/romstage.c trunk/src/mainboard/ecs/p6iwp-fe/Kconfig trunk/src/mainboard/ecs/p6iwp-fe/romstage.c trunk/src/mainboard/hp/e_vectra_p2706t/Kconfig trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c trunk/src/mainboard/intel/d810e2cb/romstage.c trunk/src/mainboard/mitac/6513wu/Kconfig trunk/src/mainboard/mitac/6513wu/romstage.c trunk/src/mainboard/msi/ms6178/Kconfig trunk/src/mainboard/msi/ms6178/romstage.c trunk/src/mainboard/nec/powermate2000/Kconfig trunk/src/mainboard/nec/powermate2000/romstage.c trunk/src/northbridge/intel/i82810/debug.c trunk/src/northbridge/intel/i82810/raminit.c
Modified: trunk/src/cpu/intel/socket_PGA370/Kconfig ============================================================================== --- trunk/src/cpu/intel/socket_PGA370/Kconfig Wed Oct 13 08:23:02 2010 (r5948) +++ trunk/src/cpu/intel/socket_PGA370/Kconfig Wed Oct 13 10:21:44 2010 (r5949) @@ -21,10 +21,22 @@ bool select MMX select UDELAY_TSC + select CACHE_AS_RAM + +if CPU_INTEL_SOCKET_PGA370
# Not all CPUs for Socket 370 can do SSE2 config SSE2 bool default n - depends on CPU_INTEL_SOCKET_PGA370 + +config DCACHE_RAM_BASE + hex + default 0xc0000 + +config DCACHE_RAM_SIZE + hex + default 0x01000 + +endif
Modified: trunk/src/cpu/intel/socket_PGA370/Makefile.inc ============================================================================== --- trunk/src/cpu/intel/socket_PGA370/Makefile.inc Wed Oct 13 08:23:02 2010 (r5948) +++ trunk/src/cpu/intel/socket_PGA370/Makefile.inc Wed Oct 13 10:21:44 2010 (r5949) @@ -27,3 +27,5 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode
+cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc +
Modified: trunk/src/cpu/intel/socket_PGA370/socket_PGA370.c ============================================================================== --- trunk/src/cpu/intel/socket_PGA370/socket_PGA370.c Wed Oct 13 08:23:02 2010 (r5948) +++ trunk/src/cpu/intel/socket_PGA370/socket_PGA370.c Wed Oct 13 10:21:44 2010 (r5949) @@ -1,7 +1,6 @@ #include <device/device.h> #include "chip.h"
- struct chip_operations cpu_intel_socket_PGA370_ops = { CHIP_NAME("Socket PGA370 CPU") };
Modified: trunk/src/mainboard/asus/mew-am/Kconfig ============================================================================== --- trunk/src/mainboard/asus/mew-am/Kconfig Wed Oct 13 08:23:02 2010 (r5948) +++ trunk/src/mainboard/asus/mew-am/Kconfig Wed Oct 13 10:21:44 2010 (r5949) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_SMSC_SMSCSUPERIO - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512
Modified: trunk/src/mainboard/asus/mew-am/romstage.c ============================================================================== --- trunk/src/mainboard/asus/mew-am/romstage.c Wed Oct 13 08:23:02 2010 (r5948) +++ trunk/src/mainboard/asus/mew-am/romstage.c Wed Oct 13 10:21:44 2010 (r5949) @@ -26,31 +26,21 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" - -#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) - -static inline int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - #include "northbridge/intel/i82810/raminit.c" /* #include "northbridge/intel/i82810/debug.c" */ +#include <lib.h>
-static void main(unsigned long bist) -{ - if (bist == 0) - early_mtrr_init(); +#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
+void main(unsigned long bist) +{ smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -60,6 +50,4 @@ sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } -
Modified: trunk/src/mainboard/asus/mew-vm/Kconfig ============================================================================== --- trunk/src/mainboard/asus/mew-vm/Kconfig Wed Oct 13 08:23:02 2010 (r5948) +++ trunk/src/mainboard/asus/mew-vm/Kconfig Wed Oct 13 10:21:44 2010 (r5949) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_SMSC_LPC47B272 - select ROMCC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select UDELAY_TSC
Modified: trunk/src/mainboard/asus/mew-vm/romstage.c ============================================================================== --- trunk/src/mainboard/asus/mew-vm/romstage.c Wed Oct 13 08:23:02 2010 (r5948) +++ trunk/src/mainboard/asus/mew-vm/romstage.c Wed Oct 13 10:21:44 2010 (r5949) @@ -26,42 +26,28 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "superio/smsc/lpc47b272/lpc47b272_early_serial.c" #include "northbridge/intel/i82810/raminit.h" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" - -#define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1) - #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "northbridge/intel/i82810/raminit.c" #include "northbridge/intel/i82810/debug.c" +#include <lib.h>
-static void main(unsigned long bist) -{ - if (bist == 0) - early_mtrr_init(); +#define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1)
+void main(unsigned long bist) +{ lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); - enable_smbus(); - - /* Halt if there was a built in self test failure. */ report_bist_failure(bist); - - /* dump_spd_registers(); */ - + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - - /* Check RAM. */ - /* ram_check(0, 640 * 1024); */ } -
Modified: trunk/src/mainboard/ecs/p6iwp-fe/Kconfig ============================================================================== --- trunk/src/mainboard/ecs/p6iwp-fe/Kconfig Wed Oct 13 08:23:02 2010 (r5948) +++ trunk/src/mainboard/ecs/p6iwp-fe/Kconfig Wed Oct 13 10:21:44 2010 (r5949) @@ -26,7 +26,6 @@ select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_ITE_IT8712F - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512
Modified: trunk/src/mainboard/ecs/p6iwp-fe/romstage.c ============================================================================== --- trunk/src/mainboard/ecs/p6iwp-fe/romstage.c Wed Oct 13 08:23:02 2010 (r5948) +++ trunk/src/mainboard/ecs/p6iwp-fe/romstage.c Wed Oct 13 10:21:44 2010 (r5949) @@ -27,37 +27,21 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/ite/it8712f/it8712f_early_serial.c" - -static inline int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - #include "northbridge/intel/i82810/raminit.c" #include "northbridge/intel/i82810/debug.c" +#include <lib.h>
-/* Early mainboard specific GPIO setup. */ -static void mb_gpio_init(void) +void main(unsigned long bist) { -} - -static void main(unsigned long bist) -{ - if (bist == 0) - early_mtrr_init(); - it8712f_24mhz_clkin(); it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter - mb_gpio_init(); uart_init(); console_init(); report_bist_failure(bist); @@ -67,6 +51,4 @@ sdram_set_spd_registers(); sdram_enable(); dump_spd_registers(); - /* ram_check(0, 640 * 1024); */ } -
Modified: trunk/src/mainboard/hp/e_vectra_p2706t/Kconfig ============================================================================== --- trunk/src/mainboard/hp/e_vectra_p2706t/Kconfig Wed Oct 13 08:23:02 2010 (r5948) +++ trunk/src/mainboard/hp/e_vectra_p2706t/Kconfig Wed Oct 13 10:21:44 2010 (r5949) @@ -29,7 +29,6 @@ select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_NSC_PC87360 - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512
Modified: trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c ============================================================================== --- trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c Wed Oct 13 08:23:02 2010 (r5948) +++ trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c Wed Oct 13 10:21:44 2010 (r5949) @@ -26,40 +26,30 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" /* TODO: It's a PC87364 actually! */ #include "superio/nsc/pc87360/pc87360_early_serial.c" /* TODO: It's i810E actually! */ #include "northbridge/intel/i82810/raminit.h" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "pc80/udelay_io.c" #include "lib/debug.c" #include "northbridge/intel/i82810/raminit.c" +#include <lib.h>
/* TODO: It's a PC87364 actually! */ #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
-static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - /* TODO: It's a PC87364 actually! */ pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - uart_init(); console_init(); - enable_smbus(); - report_bist_failure(bist); - /* dump_spd_registers(); */ sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } -
Modified: trunk/src/mainboard/intel/d810e2cb/romstage.c ============================================================================== --- trunk/src/mainboard/intel/d810e2cb/romstage.c Wed Oct 13 08:23:02 2010 (r5948) +++ trunk/src/mainboard/intel/d810e2cb/romstage.c Wed Oct 13 10:21:44 2010 (r5949) @@ -35,21 +35,15 @@ #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "gpio.c" +#include "northbridge/intel/i82810/raminit.c" +/* #include "northbridge/intel/i82810/debug.c" */ #include <lib.h>
#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
-static inline int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/i82810/raminit.c" -/* #include "northbridge/intel/i82810/debug.c" */ - void main(unsigned long bist) { - /* Set southbridge and superio gpios */ + /* Set southbridge and Super I/O GPIOs. */ mb_gpio_init();
smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -62,6 +56,4 @@ sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } -
Modified: trunk/src/mainboard/mitac/6513wu/Kconfig ============================================================================== --- trunk/src/mainboard/mitac/6513wu/Kconfig Wed Oct 13 08:23:02 2010 (r5948) +++ trunk/src/mainboard/mitac/6513wu/Kconfig Wed Oct 13 10:21:44 2010 (r5949) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_SMSC_SMSCSUPERIO - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512
Modified: trunk/src/mainboard/mitac/6513wu/romstage.c ============================================================================== --- trunk/src/mainboard/mitac/6513wu/romstage.c Wed Oct 13 08:23:02 2010 (r5948) +++ trunk/src/mainboard/mitac/6513wu/romstage.c Wed Oct 13 10:21:44 2010 (r5949) @@ -26,31 +26,21 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" - -#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) - -static inline int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - #include "northbridge/intel/i82810/raminit.c" /* #include "northbridge/intel/i82810/debug.c" */ +#include <lib.h>
-static void main(unsigned long bist) -{ - if (bist == 0) - early_mtrr_init(); +#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
+void main(unsigned long bist) +{ smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -61,6 +51,4 @@ sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } -
Modified: trunk/src/mainboard/msi/ms6178/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms6178/Kconfig Wed Oct 13 08:23:02 2010 (r5948) +++ trunk/src/mainboard/msi/ms6178/Kconfig Wed Oct 13 10:21:44 2010 (r5949) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_WINBOND_W83627HF - select ROMCC select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_512 select HAVE_MAINBOARD_RESOURCES
Modified: trunk/src/mainboard/msi/ms6178/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6178/romstage.c Wed Oct 13 08:23:02 2010 (r5948) +++ trunk/src/mainboard/msi/ms6178/romstage.c Wed Oct 13 10:21:44 2010 (r5949) @@ -26,23 +26,19 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/intel/i82810/raminit.h" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "pc80/udelay_io.c" #include "lib/debug.c" #include "northbridge/intel/i82810/raminit.c" +#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - /* FIXME */ outb(0x87, 0x2e); outb(0x87, 0x2e); @@ -61,6 +57,4 @@ sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } -
Modified: trunk/src/mainboard/nec/powermate2000/Kconfig ============================================================================== --- trunk/src/mainboard/nec/powermate2000/Kconfig Wed Oct 13 08:23:02 2010 (r5948) +++ trunk/src/mainboard/nec/powermate2000/Kconfig Wed Oct 13 10:21:44 2010 (r5949) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_SMSC_SMSCSUPERIO - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512
Modified: trunk/src/mainboard/nec/powermate2000/romstage.c ============================================================================== --- trunk/src/mainboard/nec/powermate2000/romstage.c Wed Oct 13 08:23:02 2010 (r5948) +++ trunk/src/mainboard/nec/powermate2000/romstage.c Wed Oct 13 10:21:44 2010 (r5949) @@ -26,34 +26,25 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82810/raminit.h" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "pc80/udelay_io.c" #include "northbridge/intel/i82810/raminit.c" +#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
-static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); - enable_smbus(); - report_bist_failure(bist); - /* dump_spd_registers(); */ sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } -
Modified: trunk/src/northbridge/intel/i82810/debug.c ============================================================================== --- trunk/src/northbridge/intel/i82810/debug.c Wed Oct 13 08:23:02 2010 (r5948) +++ trunk/src/northbridge/intel/i82810/debug.c Wed Oct 13 10:21:44 2010 (r5949) @@ -1,6 +1,6 @@ - static void dump_spd_registers(void) { +#if CONFIG_DEBUG_RAM_SETUP int i; print_debug("\n"); for(i = 0; i < DIMM_SOCKETS; i++) { @@ -32,4 +32,5 @@ print_debug("\n"); } } +#endif }
Modified: trunk/src/northbridge/intel/i82810/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i82810/raminit.c Wed Oct 13 08:23:02 2010 (r5948) +++ trunk/src/northbridge/intel/i82810/raminit.c Wed Oct 13 10:21:44 2010 (r5949) @@ -137,6 +137,11 @@ SDRAM configuration functions. -----------------------------------------------------------------------------*/
+static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + /** * Send the specified RAM command to all DIMMs. *