Ühel kenal päeval, K, 2008-05-07 kell 02:42, kirjutas Carl-Daniel Hailfinger:
See below for my take at this.
Move CS5536 IDE configuration into a separate dts and its own PCI device.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Build-tested on db800, norwich, dbe62, alix.1c, alix.2c3. Breaks build for dbe61.
I think it's fine that it breaks build for dbe61 and I think that dbe61 code should be brought up to mostly the state that dbe62 is in anyway.
Index: LinuxBIOSv3-hierarchical_dts/southbridge/amd/cs5536/dts
--- LinuxBIOSv3-hierarchical_dts/southbridge/amd/cs5536/dts (revision 676) +++ LinuxBIOSv3-hierarchical_dts/southbridge/amd/cs5536/dts (working copy) @@ -36,9 +36,6 @@ /* 0:IDE 1:FLASH, if you are using NAND flash instead of IDE drive. */ enable_ide_nand_flash = "0";
- /* IDE: enable CS5536 IDE. There may be a different IDE controller on board */
- enable_ide = "0";
- /* Enable USB Port 4 (0:host 1:device). */ enable_USBP4_device = "0";
...
Index: LinuxBIOSv3-hierarchical_dts/mainboard/artecgroup/dbe62/dts
--- LinuxBIOSv3-hierarchical_dts/mainboard/artecgroup/dbe62/dts (revision 676) +++ LinuxBIOSv3-hierarchical_dts/mainboard/artecgroup/dbe62/dts (working copy) @@ -34,7 +34,6 @@ }; pci@15,0 { /config/("southbridge/amd/cs5536/dts");
enable_ide = "1"; /* Interrupt enables for LPC bus. * Each bit is an IRQ 0-15. */ lpc_serirq_enable = "0x00001002";@@ -54,5 +53,9 @@ /* Set com2 IRQ to be what is usually COM1 */ com2_irq = "4"; };
pci@15,2 {/config/("southbridge/amd/cs5536/ide");enable_ide = "1";};};
Just removing enable_ide as in southbridge/cs5536 would be better in my opinion. DBE62 uses NAND not any IDE, so I was actually intending to send a patch that sets enable_ide to 0, but now I saw this.
Those things said, not qualified for acking
Mart Raudsepp Artec Design LLC