On 29.03.19 19:08, Rafael Send wrote:
Hi Nico- Can you clarify what you mean by coreboot on x86 is special?
on x86, there are two ways to access a SPI flash chip: 1. you can ask the SPI controller via a register based interface to access the flash chip. 2. by default, the flash chip contents of the BIOS region* of the flash chip is memory mapped (i.e. you can read from it just like you read from RAM).
1. may support >16MiB chips/regions.
2. is usually limited to 8MiB or 16MiB depending on the chipset. I would guess 16MiB in your case, but I can't promise.
2. is used by coreboot. However, with some additional code you can also use 1.
*Intel shares the flash chip with other chipset components, e.g. ME firmware.
Does that mean even if 3-byte addresses are supported (which would allow addressing more than 128Mb / 16MiB of memory), it specifically doesn't work on x86?
No. The x86 thing is just a current software limitation that can be lifted. But still, there may be chips (e.g. EC) between the flash and the Intel chipset that may have their own limits.
I'm looking at the coreboot port that was done for the Thinkpad X210, which is a Chinese custom motherboard that updates the X201 form factor with an i7-8650U / i7-8550u / i5-8250U CPU, and just for the hell of it I'm wondering what the largest piece of BIOS memory is I can get on there. Hardware-wise, I can get up to 512Mb / 64MiB into the chip form factor. If we can address it, that opens up interesting possibilities for embedding full OS distributions there (such as my previous question about TinyCore).
The chipset supports up to two chips of 64MiB each. But I don't know if the flash is directly connected.
In case of a full OS in flash, I would suggest a SPI driver in the OS kernel, anyway. Otherwise, you'd have to let coreboot load a lot of data from flash at once and that would slow it down (but that doesn't have to be a concern).
Nico