Author: myles Date: 2009-11-06 17:02:51 +0000 (Fri, 06 Nov 2009) New Revision: 4921
Removed: trunk/src/drivers/pci/ Modified: trunk/src/arch/i386/include/arch/cpu.h trunk/src/arch/i386/include/arch/hlt.h trunk/src/arch/i386/include/arch/io.h trunk/src/arch/i386/lib/console_print.c trunk/src/cpu/amd/dualcore/dualcore_id.c trunk/src/cpu/amd/microcode/microcode.c trunk/src/cpu/amd/model_10xxx/apic_timer.c trunk/src/cpu/amd/model_10xxx/update_microcode.c trunk/src/cpu/amd/quadcore/quadcore_id.c trunk/src/cpu/x86/smm/smmrelocate.S trunk/src/include/assert.h trunk/src/include/cpu/amd/dualcore.h trunk/src/include/cpu/amd/model_fxx_rev.h trunk/src/include/cpu/amd/mtrr.h trunk/src/include/cpu/amd/quadcore.h trunk/src/include/cpu/x86/cache.h trunk/src/include/cpu/x86/lapic.h trunk/src/include/cpu/x86/msr.h trunk/src/include/cpu/x86/mtrr.h trunk/src/include/cpu/x86/tsc.h trunk/src/include/stdlib.h trunk/src/include/string.h trunk/src/lib/cbmem.c trunk/src/lib/usbdebug_direct.c trunk/src/mainboard/amd/dbm690t/cache_as_ram_auto.c trunk/src/mainboard/amd/pistachio/cache_as_ram_auto.c trunk/src/mainboard/amd/serengeti_cheetah/apc_auto.c trunk/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c trunk/src/mainboard/arima/hdama/cache_as_ram_auto.c trunk/src/mainboard/asus/a8n_e/cache_as_ram_auto.c trunk/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c trunk/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c trunk/src/mainboard/broadcom/blast/cache_as_ram_auto.c trunk/src/mainboard/dell/s1850/reset.c trunk/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c trunk/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c trunk/src/mainboard/gigabyte/m57sli/apc_auto.c trunk/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c trunk/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c trunk/src/mainboard/ibm/e325/cache_as_ram_auto.c trunk/src/mainboard/ibm/e326/cache_as_ram_auto.c trunk/src/mainboard/intel/d945gclf/auto.c trunk/src/mainboard/intel/eagleheights/auto.c trunk/src/mainboard/intel/eagleheights/reset.c trunk/src/mainboard/intel/jarrell/reset.c trunk/src/mainboard/intel/xe7501devkit/auto.c trunk/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c trunk/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c trunk/src/mainboard/iwill/dk8x/cache_as_ram_auto.c trunk/src/mainboard/kontron/986lcd-m/auto.c trunk/src/mainboard/kontron/kt690/cache_as_ram_auto.c trunk/src/mainboard/msi/ms7135/cache_as_ram_auto.c trunk/src/mainboard/msi/ms7260/apc_auto.c trunk/src/mainboard/msi/ms7260/cache_as_ram_auto.c trunk/src/mainboard/msi/ms9185/cache_as_ram_auto.c trunk/src/mainboard/msi/ms9282/cache_as_ram_auto.c trunk/src/mainboard/newisys/khepri/cache_as_ram_auto.c trunk/src/mainboard/nvidia/l1_2pvv/apc_auto.c trunk/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c trunk/src/mainboard/sunw/ultra40/cache_as_ram_auto.c trunk/src/mainboard/supermicro/h8dme/apc_auto.c trunk/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c trunk/src/mainboard/supermicro/h8dmr/apc_auto.c trunk/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c trunk/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c trunk/src/mainboard/supermicro/h8dmr_fam10/cache_as_ram_auto.c trunk/src/mainboard/supermicro/x6dai_g/reset.c trunk/src/mainboard/supermicro/x6dhe_g/reset.c trunk/src/mainboard/supermicro/x6dhe_g2/reset.c trunk/src/mainboard/supermicro/x6dhr_ig/reset.c trunk/src/mainboard/supermicro/x6dhr_ig2/reset.c trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c trunk/src/mainboard/technexion/tim8690/cache_as_ram_auto.c trunk/src/mainboard/tyan/s2735/cache_as_ram_auto.c trunk/src/mainboard/tyan/s2850/cache_as_ram_auto.c trunk/src/mainboard/tyan/s2875/cache_as_ram_auto.c trunk/src/mainboard/tyan/s2880/cache_as_ram_auto.c trunk/src/mainboard/tyan/s2881/cache_as_ram_auto.c trunk/src/mainboard/tyan/s2882/cache_as_ram_auto.c trunk/src/mainboard/tyan/s2885/cache_as_ram_auto.c trunk/src/mainboard/tyan/s2891/cache_as_ram_auto.c trunk/src/mainboard/tyan/s2892/cache_as_ram_auto.c trunk/src/mainboard/tyan/s2895/cache_as_ram_auto.c trunk/src/mainboard/tyan/s2895/failover.c trunk/src/mainboard/tyan/s2912/apc_auto.c trunk/src/mainboard/tyan/s2912/cache_as_ram_auto.c trunk/src/mainboard/tyan/s2912_fam10/apc_auto.c trunk/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c trunk/src/mainboard/tyan/s4880/cache_as_ram_auto.c trunk/src/mainboard/tyan/s4882/cache_as_ram_auto.c trunk/src/mainboard/via/epia-m700/cache_as_ram_auto.c trunk/src/northbridge/amd/amdfam10/amdfam10.h trunk/src/northbridge/amd/amdfam10/amdfam10_conf.c trunk/src/northbridge/amd/amdk8/amdk8_f.h trunk/src/northbridge/via/cn700/cn700.h trunk/src/northbridge/via/vx800/examples/cache_as_ram_auto.c trunk/src/southbridge/amd/cs5530/cs5530.h trunk/src/southbridge/intel/i82371eb/i82371eb.h trunk/src/southbridge/intel/i82801ca/i82801ca.h trunk/src/southbridge/intel/i82801gx/i82801gx.h trunk/src/southbridge/intel/i82801xx/i82801xx.h Log: Split the two usages of __ROMCC__: __ROMCC__ now means "Don't use prototypes, since romcc doesn't support them." __PRE_RAM__ means "Use simpler versions of functions, and no device tree."
There are probably some places where both are tested, but only one is needed.
Signed-off-by: Myles Watson mylesgw@gmail.com Acked-by: Peter Stuge peter@stuge.se
Modified: trunk/src/arch/i386/include/arch/cpu.h =================================================================== --- trunk/src/arch/i386/include/arch/cpu.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/arch/i386/include/arch/cpu.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -104,7 +104,7 @@ #define X86_VENDOR_SIS 10 #define X86_VENDOR_UNKNOWN 0xff
-#if !defined( __ROMCC__ ) && defined( __GNUC__) +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) && defined( __GNUC__) #include <device/device.h>
Modified: trunk/src/arch/i386/include/arch/hlt.h =================================================================== --- trunk/src/arch/i386/include/arch/hlt.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/arch/i386/include/arch/hlt.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,7 +1,7 @@ #ifndef ARCH_HLT_H #define ARCH_HLT_H
-#if defined( __ROMCC__) && !defined(__GNUC__) +#if defined( __ROMCC__) && !defined(__PRE_RAM__) && !defined(__GNUC__) static void hlt(void) { __builtin_hlt();
Modified: trunk/src/arch/i386/include/arch/io.h =================================================================== --- trunk/src/arch/i386/include/arch/io.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/arch/i386/include/arch/io.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -9,7 +9,7 @@ * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" * versions of the single-IO instructions (inb_p/inw_p/..). */ -#if defined( __ROMCC__ ) && !defined (__GNUC__) +#if defined( __ROMCC__ ) && !defined (__GNUC__) static inline void outb(uint8_t value, uint16_t port) { __builtin_outb(value, port);
Modified: trunk/src/arch/i386/lib/console_print.c =================================================================== --- trunk/src/arch/i386/lib/console_print.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/arch/i386/lib/console_print.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -66,7 +66,7 @@ * set in some auto.c files to trigger the simple device_t version to be used. * So __GNUCC__ does the right thing here. */ -#if defined (__GNUCC__) +#if defined (__ROMCC__) #define STATIC #else #define STATIC static
Modified: trunk/src/cpu/amd/dualcore/dualcore_id.c =================================================================== --- trunk/src/cpu/amd/dualcore/dualcore_id.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/cpu/amd/dualcore/dualcore_id.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -2,7 +2,7 @@
#include <arch/cpu.h> #include <cpu/amd/dualcore.h> -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ #include <cpu/amd/model_fxx_msr.h> #endif
Modified: trunk/src/cpu/amd/microcode/microcode.c =================================================================== --- trunk/src/cpu/amd/microcode/microcode.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/cpu/amd/microcode/microcode.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#ifndef __ROMCC__ +#ifndef __PRE_RAM__
#include <stdint.h> #include <console/console.h>
Modified: trunk/src/cpu/amd/model_10xxx/apic_timer.c =================================================================== --- trunk/src/cpu/amd/model_10xxx/apic_timer.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/cpu/amd/model_10xxx/apic_timer.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -23,8 +23,8 @@ #include <cpu/x86/lapic.h>
/* NOTE: We use the APIC TIMER register is to hold flags for AP init during - * pre-memory init (ROMCC). Don't use init_timer() and udelay is redirected - * to udelay_tsc(). + * pre-memory init (__PRE_RAM__). Don't use init_timer() and udelay is + * redirected to udelay_tsc(). */
Modified: trunk/src/cpu/amd/model_10xxx/update_microcode.c =================================================================== --- trunk/src/cpu/amd/model_10xxx/update_microcode.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/cpu/amd/model_10xxx/update_microcode.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -18,7 +18,7 @@ */
-#ifndef __ROMCC__ +#ifndef __PRE_RAM__ #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -29,7 +29,7 @@
static const u8 microcode_updates[] __attribute__ ((aligned(16))) = {
-#ifdef __ROMCC__ +#ifdef __PRE_RAM__
/* From the Revision Guide : * Equivalent Processor Table for AMD Family 10h Processors
Modified: trunk/src/cpu/amd/quadcore/quadcore_id.c =================================================================== --- trunk/src/cpu/amd/quadcore/quadcore_id.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/cpu/amd/quadcore/quadcore_id.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@
#include <arch/cpu.h> #include <cpu/amd/quadcore.h> -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ #include <cpu/amd/model_10xxx_msr.h> #endif
Modified: trunk/src/cpu/x86/smm/smmrelocate.S =================================================================== --- trunk/src/cpu/x86/smm/smmrelocate.S 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/cpu/x86/smm/smmrelocate.S 2009-11-06 17:02:51 UTC (rev 4921) @@ -22,7 +22,7 @@ #include <arch/asm.h>
// Make sure no stage 2 code is included: -#define __ROMCC__ +#define __PRE_RAM__
// FIXME: Is this piece of code southbridge specific, or // can it be cleaned up so this include is not required?
Modified: trunk/src/include/assert.h =================================================================== --- trunk/src/include/assert.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/include/assert.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -24,7 +24,7 @@ // ROMCC doesn't support __FILE__ or __LINE__ :^{
#if CONFIG_DEBUG -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ #define ASSERT(x) { if (!(x)) die("ASSERT failure!\r\n"); } #else #define ASSERT(x) { \ @@ -39,7 +39,7 @@ #define ASSERT(x) { } #endif
-#ifdef __ROMCC__ +#ifdef __PRE_RAM__ #define BUG() { die("BUG encountered: system halted\r\n"); } #else #define BUG() { \
Modified: trunk/src/include/cpu/amd/dualcore.h =================================================================== --- trunk/src/include/cpu/amd/dualcore.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/include/cpu/amd/dualcore.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -15,7 +15,7 @@ struct node_core_id get_node_core_id(unsigned int nb_cfg_54); #endif
-#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) struct device; unsigned get_apicid_base(unsigned ioapic_num); void amd_sibling_init(struct device *cpu);
Modified: trunk/src/include/cpu/amd/model_fxx_rev.h =================================================================== --- trunk/src/include/cpu/amd/model_fxx_rev.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/include/cpu/amd/model_fxx_rev.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -49,7 +49,7 @@ }
-#ifdef __ROMCC__ +#ifdef __PRE_RAM__ static int is_e0_later_in_bsp(int nodeid) { uint32_t val; @@ -96,7 +96,7 @@ return (cpuid_eax(1) & 0xfff0f) < 0x40f02; }
-#ifdef __ROMCC__ +#ifdef __PRE_RAM__ //AMD_F0_SUPPORT static int is_cpu_f0_in_bsp(int nodeid) {
Modified: trunk/src/include/cpu/amd/mtrr.h =================================================================== --- trunk/src/include/cpu/amd/mtrr.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/include/cpu/amd/mtrr.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -31,7 +31,7 @@ #define TOP_MEM_MASK 0x007fffff #define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10)
-#if !defined( __ROMCC__ ) && !defined (ASSEMBLY) +#if !defined( __ROMCC__ ) && !defined (ASSEMBLY) && !defined(__PRE_RAM__) void amd_setup_mtrrs(void); #endif /* __ROMCC__ */
Modified: trunk/src/include/cpu/amd/quadcore.h =================================================================== --- trunk/src/include/cpu/amd/quadcore.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/include/cpu/amd/quadcore.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -34,7 +34,7 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54); #endif
-#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) struct device; u32 get_apicid_base(u32 ioapic_num); void amd_sibling_init(struct device *cpu);
Modified: trunk/src/include/cpu/x86/cache.h =================================================================== --- trunk/src/include/cpu/x86/cache.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/include/cpu/x86/cache.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -41,7 +41,7 @@ wbinvd(); }
-#if !defined( __ROMCC__) && defined (__GNUC__) +#if !defined( __ROMCC__) && !defined(__PRE_RAM__) && defined (__GNUC__) void x86_enable_cache(void); #endif /* !__ROMCC__ */
Modified: trunk/src/include/cpu/x86/lapic.h =================================================================== --- trunk/src/include/cpu/x86/lapic.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/include/cpu/x86/lapic.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -68,7 +68,7 @@ } #endif
-#if ! defined (__ROMCC__) +#if ! defined (__ROMCC__) && !defined(__PRE_RAM__)
#define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
@@ -157,6 +157,6 @@ #endif /* CONFIG_SMP */
-#endif /* !__ROMCC__ */ +#endif /* !__ROMCC__ && !__PRE_RAM__ */
#endif /* CPU_X86_LAPIC_H */
Modified: trunk/src/include/cpu/x86/msr.h =================================================================== --- trunk/src/include/cpu/x86/msr.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/include/cpu/x86/msr.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,7 +1,7 @@ #ifndef CPU_X86_MSR_H #define CPU_X86_MSR_H
-#if defined( __ROMCC__) && !defined (__GNUC__) +#if defined( __ROMCC__)
typedef __builtin_msr_t msr_t;
@@ -43,7 +43,7 @@ ); }
-#endif /* ROMCC__ && !__GNUC__ */ +#endif /* __ROMCC__ */
#endif /* CPU_X86_MSR_H */
Modified: trunk/src/include/cpu/x86/mtrr.h =================================================================== --- trunk/src/include/cpu/x86/mtrr.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/include/cpu/x86/mtrr.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -32,7 +32,7 @@ #define MTRRfix4K_F8000_MSR 0x26f
-#if !defined(__ROMCC__) && !defined (ASSEMBLY) +#if !defined(__ROMCC__) && !defined (ASSEMBLY) && !defined(__PRE_RAM__)
#include <device/device.h>
Modified: trunk/src/include/cpu/x86/tsc.h =================================================================== --- trunk/src/include/cpu/x86/tsc.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/include/cpu/x86/tsc.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -17,7 +17,7 @@ return res; }
-#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined (__PRE_RAM__) static inline unsigned long long rdtscll(void) { unsigned long long val;
Modified: trunk/src/include/stdlib.h =================================================================== --- trunk/src/include/stdlib.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/include/stdlib.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -11,7 +11,7 @@ #define MIN(a,b) ((a) < (b) ? (a) : (b)) #define MAX(a,b) ((a) > (b) ? (a) : (b))
-#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) void *malloc(size_t size); void free(void *ptr); #endif
Modified: trunk/src/include/string.h =================================================================== --- trunk/src/include/string.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/include/string.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -8,7 +8,7 @@ void *memmove(void *dest, const void *src, size_t n); void *memset(void *s, int c, size_t n); int memcmp(const void *s1, const void *s2, size_t n); -#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) int sprintf(char * buf, const char *fmt, ...); #endif
@@ -41,7 +41,7 @@ return 0; }
-#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) static inline char *strdup(const char *s) { size_t sz = strlen(s) + 1;
Modified: trunk/src/lib/cbmem.c =================================================================== --- trunk/src/lib/cbmem.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/lib/cbmem.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -45,7 +45,7 @@ u64 size; } __attribute__((packed));
-#ifndef __ROMCC__ +#ifndef __PRE_RAM__ struct cbmem_entry *bss_cbmem_toc; #endif
@@ -64,7 +64,7 @@ struct cbmem_entry *cbmem_toc; cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr;
-#ifndef __ROMCC__ +#ifndef __PRE_RAM__ bss_cbmem_toc = cbmem_toc; #endif @@ -91,7 +91,7 @@ cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr;
debug("Re-Initializing CBMEM area to 0x%lx\n", (unsigned long)baseaddr); -#ifndef __ROMCC__ +#ifndef __PRE_RAM__ bss_cbmem_toc = cbmem_toc; #endif
@@ -102,7 +102,7 @@ { struct cbmem_entry *cbmem_toc; int i; -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ cbmem_toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); #else cbmem_toc = bss_cbmem_toc; @@ -158,7 +158,7 @@ { struct cbmem_entry *cbmem_toc; int i; -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ cbmem_toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); #else cbmem_toc = bss_cbmem_toc; @@ -175,7 +175,7 @@ return (void *)NULL; }
-#ifndef __ROMCC__ +#ifndef __PRE_RAM__ #if CONFIG_HAVE_ACPI_RESUME extern u8 acpi_slp_type; #endif @@ -199,12 +199,12 @@ cbmem_arch_init(); }
-#ifndef __ROMCC__ +#ifndef __PRE_RAM__ void cbmem_list(void) { struct cbmem_entry *cbmem_toc; int i; -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ cbmem_toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); #else cbmem_toc = bss_cbmem_toc;
Modified: trunk/src/lib/usbdebug_direct.c =================================================================== --- trunk/src/lib/usbdebug_direct.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/lib/usbdebug_direct.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -19,7 +19,7 @@ /* * 2006.12.10 yhlu moved it to corbeoot and use struct instead */ -#ifndef __ROMCC__ +#if !defined(__ROMCC__) #include <console/console.h> #else #if CONFIG_USE_PRINTK_IN_CAR==0
Modified: trunk/src/mainboard/amd/dbm690t/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/amd/dbm690t/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/amd/dbm690t/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -18,7 +18,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1 #define K8_SET_FIDVID 1
Modified: trunk/src/mainboard/amd/pistachio/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/amd/pistachio/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/amd/pistachio/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -18,7 +18,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1 #define K8_SET_FIDVID 1
Modified: trunk/src/mainboard/amd/serengeti_cheetah/apc_auto.c =================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/apc_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/amd/serengeti_cheetah/apc_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
Modified: trunk/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c =================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -18,7 +18,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -19,7 +19,7 @@
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define SYSTEM_TYPE 0 /* SERVER */ //#define SYSTEM_TYPE 1 /* DESKTOP */
Modified: trunk/src/mainboard/arima/hdama/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/arima/hdama/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/arima/hdama/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#include <stdint.h> #include <device/pci_def.h>
Modified: trunk/src/mainboard/asus/a8n_e/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/asus/a8n_e/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/asus/a8n_e/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -22,7 +22,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
/* Used by it8712f_enable_serial(). */ #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
Modified: trunk/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -23,7 +23,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
Modified: trunk/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -23,7 +23,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
Modified: trunk/src/mainboard/broadcom/blast/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/broadcom/blast/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/broadcom/blast/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define QRANK_DIMM_SUPPORT 1
Modified: trunk/src/mainboard/dell/s1850/reset.c =================================================================== --- trunk/src/mainboard/dell/s1850/reset.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/dell/s1850/reset.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -2,7 +2,7 @@
#include <device/pci_def.h> #include <device/pci_ids.h> -#ifndef __ROMCC__ +#if !defined (__ROMCC__) && !defined (__PRE_RAM__) #include <device/pci.h> #define PCI_ID(VENDOR_ID, DEVICE_ID) \ ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c =================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -22,7 +22,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -22,7 +22,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
Modified: trunk/src/mainboard/gigabyte/m57sli/apc_auto.c =================================================================== --- trunk/src/mainboard/gigabyte/m57sli/apc_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/gigabyte/m57sli/apc_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
Modified: trunk/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
Modified: trunk/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -26,7 +26,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
Modified: trunk/src/mainboard/ibm/e325/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/ibm/e325/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/ibm/e325/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#include <stdint.h> #include <string.h>
Modified: trunk/src/mainboard/ibm/e326/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/ibm/e326/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/ibm/e326/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#include <stdint.h> #include <string.h>
Modified: trunk/src/mainboard/intel/d945gclf/auto.c =================================================================== --- trunk/src/mainboard/intel/d945gclf/auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/intel/d945gclf/auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-// __ROMCC__ means: use "unsigned" for device, not a struct. -#define __ROMCC__ +// __PRE_RAM__ means: use "unsigned" for device, not a struct. +#define __PRE_RAM__
#include <stdint.h> #include <string.h> @@ -220,10 +220,10 @@ #include <cbmem.h>
// Now, this needs to be included because it relies on the symbol -// __ROMCC_ being set during CAR stage (in order to compile the +// __PRE_RAM__ being set during CAR stage (in order to compile the // BSS free versions of the functions). Either rewrite the code // to be always BSS free, or invent a flag that's better suited than -// __ROMCC__ to determine whether we're in ram init stage (stage 1) +// __PRE_RAM__ to determine whether we're in ram init stage (stage 1) // #include "lib/cbmem.c"
Modified: trunk/src/mainboard/intel/eagleheights/auto.c =================================================================== --- trunk/src/mainboard/intel/eagleheights/auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/intel/eagleheights/auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ * MA 02110-1301 USA */
-#define __ROMCC__ +#define __PRE_RAM__
#include <delay.h>
Modified: trunk/src/mainboard/intel/eagleheights/reset.c =================================================================== --- trunk/src/mainboard/intel/eagleheights/reset.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/intel/eagleheights/reset.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -22,7 +22,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#ifndef __ROMCC__ +#if !defined (__ROMCC__) && !defined (__PRE_RAM__) #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h>
Modified: trunk/src/mainboard/intel/jarrell/reset.c =================================================================== --- trunk/src/mainboard/intel/jarrell/reset.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/intel/jarrell/reset.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,7 +1,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#ifndef __ROMCC__ +#if !defined (__ROMCC__) && !defined (__PRE_RAM__) #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h>
Modified: trunk/src/mainboard/intel/xe7501devkit/auto.c =================================================================== --- trunk/src/mainboard/intel/xe7501devkit/auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/intel/xe7501devkit/auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,4 +1,5 @@ #define ASSEMBLY 1 +#define __PRE_RAM__
#include <stdint.h> #include <device/pci_def.h>
Modified: trunk/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
Modified: trunk/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
Modified: trunk/src/mainboard/iwill/dk8x/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/iwill/dk8x/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/iwill/dk8x/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
Modified: trunk/src/mainboard/kontron/986lcd-m/auto.c =================================================================== --- trunk/src/mainboard/kontron/986lcd-m/auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/kontron/986lcd-m/auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -19,8 +19,8 @@ * MA 02110-1301 USA */
-// __ROMCC__ means: use "unsigned" for device, not a struct. -#define __ROMCC__ +// __PRE_RAM__ means: use "unsigned" for device, not a struct. +#define __PRE_RAM__
#include <stdint.h> #include <string.h> @@ -359,10 +359,10 @@ #include <cbmem.h>
// Now, this needs to be included because it relies on the symbol -// __ROMCC_ being set during CAR stage (in order to compile the +// __PRE_RAM__ being set during CAR stage (in order to compile the // BSS free versions of the functions). Either rewrite the code // to be always BSS free, or invent a flag that's better suited than -// __ROMCC__ to determine whether we're in ram init stage (stage 1) +// __PRE_RAM__ to determine whether we're in ram init stage (stage 1) // #include "lib/cbmem.c"
Modified: trunk/src/mainboard/kontron/kt690/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/kontron/kt690/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/kontron/kt690/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -19,7 +19,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1 #define K8_SET_FIDVID 1
Modified: trunk/src/mainboard/msi/ms7135/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/msi/ms7135/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/msi/ms7135/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -23,7 +23,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define SERIAL_DEV PNP_DEV(0x4e, W83627HF_SP1)
Modified: trunk/src/mainboard/msi/ms7260/apc_auto.c =================================================================== --- trunk/src/mainboard/msi/ms7260/apc_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/msi/ms7260/apc_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -21,7 +21,7 @@
#define ASSEMBLY 1
-#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
Modified: trunk/src/mainboard/msi/ms7260/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/msi/ms7260/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/msi/ms7260/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -21,7 +21,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
// #define CACHE_AS_RAM_ADDRESS_DEBUG 1 // #define DEBUG_SMBUS 1
Modified: trunk/src/mainboard/msi/ms9185/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/msi/ms9185/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/msi/ms9185/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -24,7 +24,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
Modified: trunk/src/mainboard/msi/ms9282/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/msi/ms9282/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/msi/ms9282/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -23,7 +23,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
Modified: trunk/src/mainboard/newisys/khepri/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/newisys/khepri/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/newisys/khepri/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -4,7 +4,7 @@ * Additional (C) 2007 coresystems GmbH */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#include <stdint.h> #include <string.h>
Modified: trunk/src/mainboard/nvidia/l1_2pvv/apc_auto.c =================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/apc_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/nvidia/l1_2pvv/apc_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
Modified: trunk/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
Modified: trunk/src/mainboard/sunw/ultra40/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/sunw/ultra40/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/sunw/ultra40/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define K8_ALLOCATE_IO_RANGE 1
Modified: trunk/src/mainboard/supermicro/h8dme/apc_auto.c =================================================================== --- trunk/src/mainboard/supermicro/h8dme/apc_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/supermicro/h8dme/apc_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
Modified: trunk/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -17,7 +17,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
Modified: trunk/src/mainboard/supermicro/h8dmr/apc_auto.c =================================================================== --- trunk/src/mainboard/supermicro/h8dmr/apc_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/supermicro/h8dmr/apc_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
Modified: trunk/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c =================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
Modified: trunk/src/mainboard/supermicro/x6dai_g/reset.c =================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/reset.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/supermicro/x6dai_g/reset.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,7 +1,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#ifndef __ROMCC__ +#if !defined (__ROMCC__) && !defined (__PRE_RAM__) #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h>
Modified: trunk/src/mainboard/supermicro/x6dhe_g/reset.c =================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/reset.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/supermicro/x6dhe_g/reset.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,7 +1,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#ifndef __ROMCC__ +#if !defined (__ROMCC__) && !defined (__PRE_RAM__) #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h>
Modified: trunk/src/mainboard/supermicro/x6dhe_g2/reset.c =================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/reset.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/supermicro/x6dhe_g2/reset.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,7 +1,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#ifndef __ROMCC__ +#if !defined (__ROMCC__) && !defined (__PRE_RAM__) #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h>
Modified: trunk/src/mainboard/supermicro/x6dhr_ig/reset.c =================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/reset.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/supermicro/x6dhr_ig/reset.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,7 +1,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#ifndef __ROMCC__ +#if !defined (__ROMCC__) && !defined (__PRE_RAM__) #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h>
Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/reset.c =================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/reset.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/reset.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,7 +1,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#ifndef __ROMCC__ +#if !defined (__ROMCC__) && !defined (__PRE_RAM__) #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h>
Modified: trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -18,7 +18,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1 #define K8_SET_FIDVID 1
Modified: trunk/src/mainboard/technexion/tim8690/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/technexion/tim8690/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/technexion/tim8690/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -18,7 +18,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1 #define K8_SET_FIDVID 1
Modified: trunk/src/mainboard/tyan/s2735/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/tyan/s2735/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2735/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#include <stdint.h> #include <string.h>
Modified: trunk/src/mainboard/tyan/s2850/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/tyan/s2850/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2850/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#include <stdint.h> #include <string.h>
Modified: trunk/src/mainboard/tyan/s2875/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/tyan/s2875/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2875/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#include <stdint.h> #include <string.h>
Modified: trunk/src/mainboard/tyan/s2880/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/tyan/s2880/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2880/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#include <stdint.h> #include <string.h>
Modified: trunk/src/mainboard/tyan/s2881/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/tyan/s2881/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2881/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define QRANK_DIMM_SUPPORT 1
Modified: trunk/src/mainboard/tyan/s2882/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/tyan/s2882/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2882/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#include <stdint.h> #include <string.h>
Modified: trunk/src/mainboard/tyan/s2885/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/tyan/s2885/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2885/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#include <stdint.h> #include <string.h>
Modified: trunk/src/mainboard/tyan/s2891/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/tyan/s2891/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2891/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
//used by raminit #define QRANK_DIMM_SUPPORT 1
Modified: trunk/src/mainboard/tyan/s2892/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/tyan/s2892/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2892/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define QRANK_DIMM_SUPPORT 1
Modified: trunk/src/mainboard/tyan/s2895/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/tyan/s2895/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2895/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define K8_ALLOCATE_IO_RANGE 1
Modified: trunk/src/mainboard/tyan/s2895/failover.c =================================================================== --- trunk/src/mainboard/tyan/s2895/failover.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2895/failover.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#include <stdint.h> #include <string.h>
Modified: trunk/src/mainboard/tyan/s2912/apc_auto.c =================================================================== --- trunk/src/mainboard/tyan/s2912/apc_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2912/apc_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
Modified: trunk/src/mainboard/tyan/s2912/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/tyan/s2912/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2912/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
Modified: trunk/src/mainboard/tyan/s2912_fam10/apc_auto.c =================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/apc_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2912_fam10/apc_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
Modified: trunk/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#define RAMINIT_SYSINFO 1
Modified: trunk/src/mainboard/tyan/s4880/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/tyan/s4880/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s4880/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#include <stdint.h> #include <string.h>
Modified: trunk/src/mainboard/tyan/s4882/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/tyan/s4882/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s4882/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__
#include <stdint.h> #include <string.h>
Modified: trunk/src/mainboard/via/epia-m700/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/via/epia-m700/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/via/epia-m700/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -23,7 +23,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
Modified: trunk/src/northbridge/amd/amdfam10/amdfam10.h =================================================================== --- trunk/src/northbridge/amd/amdfam10/amdfam10.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/northbridge/amd/amdfam10/amdfam10.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -956,7 +956,7 @@
#include "amdfam10_nums.h"
-#ifdef __ROMCC__ +#ifdef __PRE_RAM__ #if NODE_NUMS==64 #define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) #else @@ -1086,7 +1086,7 @@
#if CONFIG_AMDMCT == 0
-#ifdef __ROMCC__ +#ifdef __PRE_RAM__ static void soft_reset(void); #endif static void wait_all_core0_mem_trained(struct sys_info *sysinfo) @@ -1131,7 +1131,7 @@ }
for(i=0; i<sysinfo->nodes; i++) { -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n"); #else printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); @@ -1148,7 +1148,7 @@ } } if(needs_reset) { -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ print_debug("mem trained failed\n"); soft_reset(); #else
Modified: trunk/src/northbridge/amd/amdfam10/amdfam10_conf.c =================================================================== --- trunk/src/northbridge/amd/amdfam10/amdfam10_conf.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/northbridge/amd/amdfam10/amdfam10_conf.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#if defined(__ROMCC__) +#if defined(__PRE_RAM__) typedef struct sys_info sys_info_conf_t; #else typedef struct amdfam10_sysconf_t sys_info_conf_t; @@ -32,7 +32,7 @@ { device_t dev; struct dram_base_mask_t d; -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1); #else dev = __f1_dev[0]; @@ -88,7 +88,7 @@ #endif
for(i=0;i<nodes;i++) { -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(i, 1); #else dev = __f1_dev[i]; @@ -108,7 +108,7 @@ #endif }
-#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(nodeid, 1); #else dev = __f1_dev[nodeid]; @@ -122,7 +122,7 @@ static void set_DctSelBaseAddr(u32 i, u32 sel_m) { device_t dev; -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(i, 2); #else dev = __f2_dev[i]; @@ -139,7 +139,7 @@ static u32 get_DctSelBaseAddr(u32 i) { device_t dev; -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(i, 2); #else dev = __f2_dev[i]; @@ -156,7 +156,7 @@ static void set_DctSelHiEn(u32 i, u32 val) { device_t dev; -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(i, 2); #else dev = __f2_dev[i]; @@ -172,7 +172,7 @@ static u32 get_DctSelHiEn(u32 i) { device_t dev; -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(i, 2); #else dev = __f2_dev[i]; @@ -187,7 +187,7 @@ static void set_DctSelBaseOffset(u32 i, u32 sel_off_m) { device_t dev; -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(i, 2); #else dev = __f2_dev[i]; @@ -203,7 +203,7 @@ static u32 get_DctSelBaseOffset(u32 i) { device_t dev; -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(i, 2); #else dev = __f2_dev[i]; @@ -264,7 +264,7 @@ d = get_dram_base_mask(i); d.mask += (carry_over>>9); set_dram_base_mask(i,d, nodes); -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(i, 1); #else dev = __f1_dev[i]; @@ -330,7 +330,7 @@ index_max = busn_max>>2; dest_max = busn_max - (index_max<<2);
// three case: index_min==index_max, index_min+1=index_max; index_min+1<index_max -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(nodeid, 1); #else dev = __f1_dev[nodeid]; @@ -393,7 +393,7 @@ #endif tempreg = 3 | ((nodeid&0xf)<<4) | ((nodeid & 0x30)<<(12-4))|(linkn<<8)|((busn_min & 0xff)<<16)|((busn_max&0xff)<<24); for(i=0; i<nodes; i++) { - #if defined(__ROMCC__) + #if defined(__PRE_RAM__) dev = NODE_PCI(i, 1); #else dev = __f1_dev[i]; @@ -433,7 +433,7 @@ if(ht_c_index<4) { #endif for(i=0; i<nodes; i++) { - #if defined(__ROMCC__) + #if defined(__PRE_RAM__) dev = NODE_PCI(i, 1); #else dev = __f1_dev[i]; @@ -480,7 +480,7 @@ } #endif
-#if defined(__ROMCC__) +#if defined(__PRE_RAM__) static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 io_min, u32 io_max, u32 nodes) { @@ -494,7 +494,7 @@ /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit for(i=0; i<nodes; i++) { - #if defined(__ROMCC__) + #if defined(__PRE_RAM__) dev = NODE_PCI(i, 1); #else dev = __f1_dev[i]; @@ -503,7 +503,7 @@ } tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? for(i=0; i<nodes; i++){ - #if defined(__ROMCC__) + #if defined(__PRE_RAM__) dev = NODE_PCI(i, 1); #else dev = __f1_dev[i]; @@ -546,7 +546,7 @@ #endif /* io range allocation */ for(i=0; i<nodes; i++) { - #if defined(__ROMCC__) + #if defined(__PRE_RAM__) dev = NODE_PCI(i, 1); #else dev = __f1_dev[i]; @@ -584,7 +584,7 @@ for(ht_c_index=1;ht_c_index<4; ht_c_index++) { u32 i; for(i=0; i<nodes; i++) { - #if defined(__ROMCC__) + #if defined(__PRE_RAM__) dev = NODE_PCI(i, 1); #else dev = __f1_dev[i]; @@ -664,7 +664,7 @@ u32 dword; device_t dev;
-#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(node, 0); #else dev = __f0_dev[node]; @@ -677,7 +677,7 @@ #endif }
-#if !defined(__ROMCC__) +#if !defined(__PRE_RAM__) static u32 get_io_addr_index(u32 nodeid, u32 linkn) { u32 index;
Modified: trunk/src/northbridge/amd/amdk8/amdk8_f.h =================================================================== --- trunk/src/northbridge/amd/amdk8/amdk8_f.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/northbridge/amd/amdk8/amdk8_f.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -518,7 +518,7 @@ uint32_t sbbusn; } __attribute__((packed));
-#ifdef __ROMCC__ +#ifdef __PRE_RAM__ static void soft_reset(void); #else void hard_reset(void); @@ -562,7 +562,7 @@ }
for(i=0; i<sysinfo->nodes; i++) { -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\r\n"); #else printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); @@ -579,7 +579,7 @@ } } if(needs_reset) { -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ print_debug("mem trained failed\r\n"); soft_reset(); #else
Modified: trunk/src/northbridge/via/cn700/cn700.h =================================================================== --- trunk/src/northbridge/via/cn700/cn700.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/northbridge/via/cn700/cn700.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#ifndef __ROMCC__ +#if !defined (__ROMCC__) && !defined (__PRE_RAM__) static void cn700_noop() { }
Modified: trunk/src/northbridge/via/vx800/examples/cache_as_ram_auto.c =================================================================== --- trunk/src/northbridge/via/vx800/examples/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/northbridge/via/vx800/examples/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -19,7 +19,7 @@ */
#define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
Modified: trunk/src/southbridge/amd/cs5530/cs5530.h =================================================================== --- trunk/src/southbridge/amd/cs5530/cs5530.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/southbridge/amd/cs5530/cs5530.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -21,7 +21,7 @@ #ifndef SOUTHBRIDGE_AMD_CS5530_CS5530_H #define SOUTHBRIDGE_AMD_CS5530_CS5530_H
-#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) #include "chip.h" void cs5530_enable(device_t dev); #endif
Modified: trunk/src/southbridge/intel/i82371eb/i82371eb.h =================================================================== --- trunk/src/southbridge/intel/i82371eb/i82371eb.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/southbridge/intel/i82371eb/i82371eb.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -21,7 +21,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H #define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
-#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) #include "chip.h" void i82371eb_enable(device_t dev); void i82371eb_hard_reset(void);
Modified: trunk/src/southbridge/intel/i82801ca/i82801ca.h =================================================================== --- trunk/src/southbridge/intel/i82801ca/i82801ca.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/southbridge/intel/i82801ca/i82801ca.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,7 +1,7 @@ #ifndef I82801CA_H #define I82801CA_H
-#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) #include "chip.h" extern void i82801ca_enable(device_t dev); #endif
Modified: trunk/src/southbridge/intel/i82801gx/i82801gx.h =================================================================== --- trunk/src/southbridge/intel/i82801gx/i82801gx.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/southbridge/intel/i82801gx/i82801gx.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -41,7 +41,7 @@ /* __ROMCC__ is set by auto.c to make sure * none of the stage2 data structures are included. */ -#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) #include "chip.h" extern void i82801gx_enable(device_t dev); #endif
Modified: trunk/src/southbridge/intel/i82801xx/i82801xx.h =================================================================== --- trunk/src/southbridge/intel/i82801xx/i82801xx.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/southbridge/intel/i82801xx/i82801xx.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -21,7 +21,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H #define SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H
-#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) #include "chip.h" extern void i82801xx_enable(device_t dev); #endif