Re: [coreboot] flashrom issues??

[Carl-Daniel Hailfinger]

On 01.03.2008 14:04, [e-mail] wrote:
> Quoting Carl-Daniel Hailfinger :
> > On 29.02.2008 20:21, Stefan Reinauer wrote:
> > > Carl-Daniel Hailfinger  [080229
> > >
> > > 20:13]:
> > > > > > > Yes, it means the actual flash write mechanism is protected, 
> > > > > > > though the
> > > > > > > ID command gets through. I had the same thing on another ICH4M 
> > > > > > > board.
> > > > > > > Might be SMM protection, some GPIO or some other mapping/locking
> > > > > > > mechanism.
> >
> > "Might be SMM...", so this is not certain.
> > > > > > Do you remember what you did to fix this on the ICH4-M?
> > > > >
> > > > > The issue remained unfixed, I used a Galep5 to burn the flash chips.
> > > >
> > > > In theory, this should be debuggable with DOS ports of the ICH  
> > > > GPIO dumper and superiotool.
> > >
> > > SMM based bios lock down? How so? It does not seem to be a GPIO 
> > > issue in
> > > case.
> >
> > If the lockdown is indeed SMM based, we can find out with superiotool
> > and the GPIO dumper (they will show no changes in GPIO configuration).
> > Then again, if you can ID the chip, it means you can write to it and
> > the only thing missing is setting the TBL# and WP# pins of the flash
> > chip high. Both pins are probably connected to some GPIOs, so unless
> > SMM protects access to the GPIO settings, flashing should be possible.
> > If the problem appears under coreboot as well, we can rule out SMM
> > protection, but not SMM flash enabling.
>
> To check this with superiotool I have to be able to dump the "Runtime 
> Registers", this is where the GPIO's are (See the SMSC lpc47m192 
> datasheet for more info). Currently superiotool does not dump these 
> registers so modifications will be required.

I was relying on the new extended superiotool dumping functionality. 
That doesn't exist yet for your superio, so I should have written 
"...can find out with superiotool (once that has GPIO dumping support 
for your superio) and...". Thanks for correcting me.
> Little confused about SMM? In the nothbridge datasheet it talks about 
> SMM (System Management Space), I do not have any of these registers 
> set, just defaults.

I only know SMM as "System Management Mode" and I hope very much we do 
not have to mess with SMM code arbitrating access to any superio/chipset 
GPIOs.
> In the southbridge datasheet it talks about SMM (special mask mode), I 
> do not have any of these registers set eithor, just defaults. Are 
> these related, or two different things? Do I need to set these 
> registers up?

I had no idea about this meaning of SMM, so I can't answer here.

Regards,
Carl-Daniel