Author: myles Date: 2008-10-28 18:29:07 +0100 (Tue, 28 Oct 2008) New Revision: 958
Modified: coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c coreboot-v3/mainboard/amd/dbm690t/initram.c coreboot-v3/mainboard/amd/serengeti/initram.c coreboot-v3/northbridge/amd/geodelx/raminit.c coreboot-v3/northbridge/amd/k8/coherent_ht.c coreboot-v3/northbridge/amd/k8/cpu.c coreboot-v3/southbridge/amd/amd8111/stage1_smbus.c coreboot-v3/southbridge/amd/sb600/stage1.c coreboot-v3/southbridge/nvidia/mcp55/stage1.c coreboot-v3/southbridge/nvidia/mcp55/stage1_smbus.c coreboot-v3/superio/ite/it8716f/superio.c coreboot-v3/superio/winbond/w83627hf/superio.c Log: Trivial fixes of printk \r\n and white space.
Signed-off-by: Myles Watson mylesgw@gmail.com Acked-by: Myles Watson mylesgw@gmail.com
Modified: coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c =================================================================== --- coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c 2008-10-28 16:06:28 UTC (rev 957) +++ coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c 2008-10-28 17:29:07 UTC (rev 958) @@ -40,10 +40,10 @@ */ /** * for_each_ap - * iterate over all APs and have them run a function. + * iterate over all APs and have them run a function. * The behaviour is modified by the core_range parameter * @param bsp_apicid The BSP APIC ID number - * @param core_range modifier for the range of cores to run on: + * @param core_range modifier for the range of cores to run on: * core_range = 0 : all cores * core range = 1 : core 0 only * core range = 2 : cores other than core0 @@ -54,7 +54,7 @@ process_ap_t process_ap, void *gp) { /* Assume the OS will not change our APIC ID. Why does this matter? Because some of the setup - * we do for other cores may depend on it not being changed. + * we do for other cores may depend on it not being changed. */ unsigned int ap_apicid;
@@ -69,12 +69,12 @@ nodes = get_nodes();
/* if the get_option fails siblings remain disabled. */ - // This sound not be a config option. disable_siblings = !CONFIG_LOGICAL_CPUS; + // This sound not be a config option. disable_siblings = !CONFIG_LOGICAL_CPUS; //get_option(&disable_siblings, "dual_core");
- /* There is an interesting problem in different steppings. See page 373. The interpretation of the + /* There is an interesting problem in different steppings. See page 373. The interpretation of the * APIC ID bits is different. To determine which order is used, check bit 54 of the programmers' guide - * here we assume that all nodes are the same stepping. + * here we assume that all nodes are the same stepping. * If not, "otherwise we can use use nb_cfg_54 from bsp for all nodes" */ nb_cfg_54 = read_nb_cfg_54(); @@ -88,7 +88,7 @@ NORTHBRIDGE_CAP) >> NBCAP_CmpCap_SHIFT) & NBCAP_CmpCap_MASK); if (nb_cfg_54) { - if (j == 0) // if it is single core, we need to increase siblings for apic calculation + if (j == 0) // if it is single core, we need to increase siblings for apic calculation j = 1; } siblings = j; @@ -133,18 +133,18 @@
/** * lapic remote read - * lapics are more than just an interrupt steering system. They are a key part of inter-processor communication. - * They can be used to start, control, and interrupt other CPUs from the BSP. It is not possible to bring up - * an SMP system without somehow using the APIC. - * CPUs and their attached IOAPICs all have an ID. For convenience, these IDs are unique. - * The communications is packet-based, using (in coreboot) a polling-based strategy. As with most APIC ops, - * the ID is the APIC ID. Even more fun, code can read registers in remote APICs, and this in turn can - * provide us with remote CPU status. - * This function does a remote read given an apic id. It returns the value or an error. It can time out. + * lapics are more than just an interrupt steering system. They are a key part of inter-processor communication. + * They can be used to start, control, and interrupt other CPUs from the BSP. It is not possible to bring up + * an SMP system without somehow using the APIC. + * CPUs and their attached IOAPICs all have an ID. For convenience, these IDs are unique. + * The communications is packet-based, using (in coreboot) a polling-based strategy. As with most APIC ops, + * the ID is the APIC ID. Even more fun, code can read registers in remote APICs, and this in turn can + * provide us with remote CPU status. + * This function does a remote read given an apic id. It returns the value or an error. It can time out. * @param apicid Remote APIC id * @param reg The register number to read * @param pvalue pointer to int for return value - * @returns 0 on success, -1 on error + * @returns 0 on success, -1 on error */ int lapic_remote_read(int apicid, int reg, unsigned int *pvalue) { @@ -153,8 +153,8 @@ int result; /* Wait for the idle state. Could we enter this with the APIC busy? It's possible. */ lapic_wait_icr_idle(); - /* The APIC Interrupt Control Registers define the operations and destinations. - * In this case, we set ICR2 to the dest, set the op to REMOTE READ, and set the + /* The APIC Interrupt Control Registers define the operations and destinations. + * In this case, we set ICR2 to the dest, set the op to REMOTE READ, and set the * reg (which is 16-bit aligned, it seems, hence the >> 4 */ lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); @@ -167,7 +167,7 @@ /* note here the ICR is command and status. */ /* Why don't we use the lapic_wait_icr_idle() above? */ /* That said, it's a bad idea to mess with this code too much. - * APICs (and their code) are quite fragile. + * APICs (and their code) are quite fragile. */ status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; } while (status == LAPIC_ICR_BUSY && timeout++ < 1000); @@ -195,16 +195,16 @@ const char *str) { printk(BIOS_DEBUG, "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n", - str, apicid, id.nodeid, id.coreid); + str, apicid, id.nodeid, id.coreid); }
/** * Using the APIC remote read code, wait for the CPU to enter a given state - * This function can time out. + * This function can time out. * @param apicid The apicid of the remote CPU * @param state The state we are waiting for - * @return 0 on success, readback value on error + * @return 0 on success, readback value on error */ unsigned int wait_cpu_state(unsigned apicid, unsigned state) { @@ -229,8 +229,8 @@ return timeout; }
-/** - * Wait for an AP to start. +/** + * Wait for an AP to start. * @param ap_apicid the apic id of the CPu * @param gp arbitrary parameter */ @@ -246,30 +246,30 @@ } }
-/** - * disable cache as ram on a BSP. - * For reasons not totally known we are saving ecx and edx. - * That will work on k8 as we copy the stack and return in the same stack frame. +/** + * disable cache as ram on a BSP. + * For reasons not totally known we are saving ecx and edx. + * That will work on k8 as we copy the stack and return in the same stack frame. */ void disable_cache_as_ram_bsp(void) { __asm__ volatile ( // "pushl %eax\n\t" - "pushl %edx\n\t" - "pushl %ecx\n\t" + "pushl %edx\n\t" + "pushl %ecx\n\t" );
disable_cache_as_ram(); - __asm__ volatile ( - "popl %ecx\n\t" - "popl %edx\n\t" -// "popl %eax\n\t" - ); + __asm__ volatile ( + "popl %ecx\n\t" + "popl %edx\n\t" +// "popl %eax\n\t" + ); }
/** - * wait for all apics to start. Make sure we don't wait on ourself. + * wait for all apics to start. Make sure we don't wait on ourself. * @param bsp_apicid The BSP APIC ID */ void wait_all_aps_started(unsigned bsp_apicid) @@ -278,14 +278,14 @@ }
/** - * Wait on all other cores to start. This includes cores on bsp, we think. + * Wait on all other cores to start. This includes cores on bsp, we think. * @param bsp_apicid The BSP APIC ID */ void wait_all_other_cores_started(unsigned bsp_apicid) // all aps other than core0 { printk(BIOS_DEBUG, "started ap apicid: "); for_each_ap(bsp_apicid, 2, wait_ap_started, (void *) 0); - printk(BIOS_DEBUG, "\r\n"); + printk(BIOS_DEBUG, "\n"); }
void STOP_CAR_AND_CPU(void) @@ -301,49 +301,49 @@
#if MEM_TRAIN_SEQ == 1 void train_ram_on_node(unsigned nodeid, unsigned coreid, - struct sys_info *sysinfo, - void * retcall); + struct sys_info *sysinfo, + void * retcall); #endif
/** - * Init all the CPUs. Part of the process involves setting APIC IDs for all cores on all sockets. - * The code that is run - * is for the most part the same on all cpus and cores of cpus. + * Init all the CPUs. Part of the process involves setting APIC IDs for all cores on all sockets. + * The code that is run + * is for the most part the same on all cpus and cores of cpus. * Since we only support F2 and later Opteron CPUs our job is considerably simplified - * as compared to v2. The basic process it to set up the cpu 0 core 0, then the other cpus, one by one. - * Complications: BSP, a.k.a. cpu 0, comes up with APIC id 0, the others all come up with APIC id 7, - * including other cpu 0 cores. Why? Because the BSP brings them up one by one and assigns their APIC ID. - * There is also the question of the need to "lift" the BSP APIC id. - * For some setups, we want the BSP APIC id to be 0; for others, - * a non-zero value is preferred. This means that we have to change the BSP APIC ID on the fly. - * - * So here we have it, some of the slickest code you'll ever read. Which cores run this function? - * All of them. + * as compared to v2. The basic process it to set up the cpu 0 core 0, then the other cpus, one by one. + * Complications: BSP, a.k.a. cpu 0, comes up with APIC id 0, the others all come up with APIC id 7, + * including other cpu 0 cores. Why? Because the BSP brings them up one by one and assigns their APIC ID. + * There is also the question of the need to "lift" the BSP APIC id. + * For some setups, we want the BSP APIC id to be 0; for others, + * a non-zero value is preferred. This means that we have to change the BSP APIC ID on the fly. + * + * So here we have it, some of the slickest code you'll ever read. Which cores run this function? + * All of them. * Do they communicate through APIC Interrupts or memory? Yes. Both. APICs before - * memory is ready, memory afterword. What is the state of the cores at the end of this function? - * They are all ready to go, just waiting to be started up. What is the state of memory on all sockets? - * It's all working. - * Except that it's not quite that simple. We'll try to comment this well enough to make sense. + * memory is ready, memory afterword. What is the state of the cores at the end of this function? + * They are all ready to go, just waiting to be started up. What is the state of memory on all sockets? + * It's all working. + * Except that it's not quite that simple. We'll try to comment this well enough to make sense. * But rest assured, it's complicated! - * @param cpu_init_detectedx has this cpu been init'ed before? - * @param sysinfo The sys_info pointer + * @param cpu_init_detectedx has this cpu been init'ed before? + * @param sysinfo The sys_info pointer * @returns the BSP APIC ID */ unsigned int init_cpus(unsigned cpu_init_detectedx, - struct sys_info *sysinfo) + struct sys_info *sysinfo) { unsigned bsp_apicid = 0; unsigned apicid; struct node_core_id id; - /* this is a bit weird but soft_reset can be defined in many places, - * so finding a common + /* this is a bit weird but soft_reset can be defined in many places, + * so finding a common * include file to use is a little daunting. */ void soft_reset(void);
#warning ignore init_detectedx cpu_init_detectedx = 0; - /* + /* * MTRR must be set by this point. */
@@ -352,19 +352,19 @@ id = get_node_core_id(); printk(BIOS_DEBUG, "init_cpus: node %d core %d\n", id.nodeid, id.coreid);
- /* The NB_CFG MSR is shared between cores on a given node. - * Here is an interesting parallel processing bug: if you were to start the + /* The NB_CFG MSR is shared between cores on a given node. + * Here is an interesting parallel processing bug: if you were to start the * other cores and THEN make this setting, different cores might read * a different value! Since ALL cores run this code, it is very important to have * core0 initialize this setting before any others. - * So do this setting very early in the function to make sure the bit has a - * consistent value on all cores. + * So do this setting very early in the function to make sure the bit has a + * consistent value on all cores. */ if (id.coreid == 0) { set_apicid_cpuid_lo(); /* only set it on core0 */ - /* Should we enable extended APIC IDs? This feature is used on a number of mainboards. - * It is required when the board requires more than 4 bits of ID. - * the question is, why not use it on all of them? Would it do harm to always enable it? + /* Should we enable extended APIC IDs? This feature is used on a number of mainboards. + * It is required when the board requires more than 4 bits of ID. + * the question is, why not use it on all of them? Would it do harm to always enable it? */ #if ENABLE_APIC_EXT_ID == 1 enable_apic_ext_id(id.nodeid); @@ -373,18 +373,18 @@
/* enable the local APIC, which we need to do message passing between sockets. */ enable_lapic(); -// init_timer(); // We need TMICT to pass msg for FID/VID change +// init_timer(); // We need TMICT to pass msg for FID/VID change
#if (ENABLE_APIC_EXT_ID == 1) /* we wish to enable extended APIC IDs. We have an APIC ID already which we can - * use as a "base" for the extended ID. + * use as a "base" for the extended ID. */ unsigned initial_apicid = get_initial_apicid(); - /* We don't always need to lift the BSP APIC ID. - * Again, is there harm if we do it anyway? + /* We don't always need to lift the BSP APIC ID. + * Again, is there harm if we do it anyway? */ #if LIFT_BSP_APIC_ID == 0 - if (initial_apicid != 0) // This CPU is not the BSP so lift it. + if (initial_apicid != 0) // This CPU is not the BSP so lift it. #endif { /* Use the CPUs initial 4-bit APIC id as the basis for the extended ID */ @@ -395,7 +395,7 @@
lapic_write(LAPIC_ID, dword); } - /* Again, the bsp_apicid is a special case and if we changed it + /* Again, the bsp_apicid is a special case and if we changed it * we need to remember that change. */ #if LIFT_BSP_APIC_ID == 1 @@ -422,26 +422,26 @@
if (cpu_init_detectedx) { print_apicid_nodeid_coreid(apicid, id, - "\r\n\r\n\r\nINIT detected from "); - printk(BIOS_DEBUG, "\r\nIssuing SOFT_RESET...\r\n"); + "\n\n\nINIT detected from "); + printk(BIOS_DEBUG, "\nIssuing SOFT_RESET...\n"); soft_reset(); }
if (id.coreid == 0) { /* not known what this is yet. */ distinguish_cpu_resets(id.nodeid); - // start_other_core(id.nodeid); // start second core in first cpu, only allowed for nb_cfg_54 is not set +// start_other_core(id.nodeid); // start second core in first cpu, only allowed for nb_cfg_54 is not set } - //Indicate to other CPUs that our CPU is running. + //Indicate to other CPUs that our CPU is running. /* and, again, recall that this is running on all sockets at some point, although it runs at - * different times. + * different times. */ lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x33);
/* non-BSP CPUs are now set up and need to halt. There are a few possibilities here. * BSP may train memory * AP may train memory - * In v2, both are possible. + * In v2, both are possible. */ if (apicid != bsp_apicid) { unsigned timeout = 1; @@ -454,13 +454,13 @@ #endif
// We need to stop the CACHE as RAM for this CPU, really? - /* Yes we do. What happens here is really interesting. To this point - * we have used APICs to communicate. We're going to use the sysinfo - * struct. But to do that we have to use real memory. So we have to - * disable car, and do it in a way that lets us continue in this function. - * The way we do it for non-node 0 is to never return from this function, - * but to do the work in this function to train RAM. - * Note that serengeti, the SimNow target, does not do this; it lets BSP train AP memory. + /* Yes we do. What happens here is really interesting. To this point + * we have used APICs to communicate. We're going to use the sysinfo + * struct. But to do that we have to use real memory. So we have to + * disable car, and do it in a way that lets us continue in this function. + * The way we do it for non-node 0 is to never return from this function, + * but to do the work in this function to train RAM. + * Note that serengeti, the SimNow target, does not do this; it lets BSP train AP memory. */ /* Wait for the bsp to enter state 44. */ while (timeout && (loop-- > 0)) { @@ -468,10 +468,10 @@ } if (timeout) { printk(BIOS_DEBUG, "while waiting for BSP signal to STOP, timeout in ap 0x%08x\n", - apicid); + apicid); } /* indicate that we are in state 44 as well. We are catching up to the BSP. */ - // old comment follows -- not sure what this means yet. + // old comment follows -- not sure what this means yet. // bsp can not check it before stop_this_cpu lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x44); /* Now set up so we can use RAM. This will be low memory, i.e. BSP memory, already working. */ @@ -490,7 +490,7 @@
/** - * Given a node, find out if core0 is started. + * Given a node, find out if core0 is started. * @param nodeid the node ID * @returns non-zero if node is started */ @@ -505,7 +505,7 @@ }
/** - * Wait for all core 0s on all CPUs to start up. + * Wait for all core 0s on all CPUs to start up. */ void wait_all_core0_started(void) { @@ -523,6 +523,6 @@ } printk(BIOS_DEBUG, "%s%02x", " ", i); } - printk(BIOS_DEBUG, "\r\n"); + printk(BIOS_DEBUG, "\n");
}
Modified: coreboot-v3/mainboard/amd/dbm690t/initram.c =================================================================== --- coreboot-v3/mainboard/amd/dbm690t/initram.c 2008-10-28 16:06:28 UTC (rev 957) +++ coreboot-v3/mainboard/amd/dbm690t/initram.c 2008-10-28 17:29:07 UTC (rev 958) @@ -43,15 +43,15 @@ #define DIMM1 0x51
/* this code is very mainboard dependent, sadly. */ -/** +/** * no op at present */ static void memreset_setup(void) { }
-/** - * this is a no op on this platform. +/** + * this is a no op on this platform. */ void memreset(int controllers, const struct mem_controller *ctrl) { @@ -62,10 +62,10 @@ }
/** - * read a byte from spd. + * read a byte from spd. * @param device device to read from * @param address address in the spd ROM - * @return the value of the byte at that address. + * @return the value of the byte at that address. */ u8 spd_read_byte(u16 device, u8 address) { @@ -73,25 +73,25 @@ return do_smbus_read_byte(device, address); }
-/** +/** * main for initram for the AMD DBM690T * @param init_detected Used to indicate that we have been started via init * @returns 0 on success - * The purpose of this code is to not only get ram going, but get any other cpus/cores going. + * The purpose of this code is to not only get ram going, but get any other cpus/cores going. * The two activities are very tightly connected and not really seperable. - * + * */ -/* - * init_detected is used to determine if we did a soft reset as required by a reprogramming of the - * hypertransport links. If we did this kind of reset, bit 11 will be set in the MTRRdefType_MSR MSR. - * That may seem crazy, but there are not lots of places to hide a bit when the CPU does a reset. - * This value is picked up in assembly, or it should be. +/* + * init_detected is used to determine if we did a soft reset as required by a reprogramming of the + * hypertransport links. If we did this kind of reset, bit 11 will be set in the MTRRdefType_MSR MSR. + * That may seem crazy, but there are not lots of places to hide a bit when the CPU does a reset. + * This value is picked up in assembly, or it should be. */ int main(void) { - /* sure, we could put this in a .h. It's called precisely once, from this one - * place. And it only relates to the initram stage. I think I'll leave it here. - * That way we can see the definition without grepping the source tree. + /* sure, we could put this in a .h. It's called precisely once, from this one + * place. And it only relates to the initram stage. I think I'll leave it here. + * That way we can see the definition without grepping the source tree. */ // void do_enable_smbus(void); void enable_fid_change_on_sb(u16 sbbusn, u16 sbdn); @@ -122,12 +122,12 @@ sysinfo = &(global_vars()->sys_info); init_detected = cpu_init_detected(me.nodeid); printk(BIOS_DEBUG, "init_detected: %d\n", init_detected); - /* well, here we are. For starters, we need to know if this is cpu0 core0. - * cpu0 core 0 will do all the DRAM setup. + /* well, here we are. For starters, we need to know if this is cpu0 core0. + * cpu0 core 0 will do all the DRAM setup. */ bsp_apicid = init_cpus(init_detected, sysinfo);
-// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE); +// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
#if 0 dump_pci_device(PCI_DEV(0, 0x18, 0)); @@ -141,9 +141,9 @@ wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched - /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, + /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) + * (there may be apic id conflicts in that case) */ start_all_cores(); wait_all_other_cores_started(bsp_apicid); @@ -176,7 +176,7 @@
// fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - printk(BIOS_INFO, "ht reset -\r\n"); + printk(BIOS_INFO, "ht reset -\n"); // soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); soft_reset(); } @@ -192,7 +192,7 @@
//do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synconize FID/VID +// init_timer(); // Need to use TMICT to synconize FID/VID
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
@@ -201,7 +201,7 @@ #endif
#if 0 -// dump_pci_devices(); +// dump_pci_devices(); dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); #endif
Modified: coreboot-v3/mainboard/amd/serengeti/initram.c =================================================================== --- coreboot-v3/mainboard/amd/serengeti/initram.c 2008-10-28 16:06:28 UTC (rev 957) +++ coreboot-v3/mainboard/amd/serengeti/initram.c 2008-10-28 17:29:07 UTC (rev 958) @@ -52,19 +52,19 @@ #define DIMM7 0x57
/* this code is very mainboard dependent, sadly. */ -/** - * call the amd 8111 memreset_setup_amd8111 function to jam the GPIOs to reset memory. +/** + * call the amd 8111 memreset_setup_amd8111 function to jam the GPIOs to reset memory. */ static void memreset_setup(void) { void memreset_setup_amd8111(u8 data, u16 offset); //GPIO on amd8111 to enable MEMRST ???? - memreset_setup_amd8111((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), 0xc0 + 16); //REVC_MEMRST_EN=1 - memreset_setup_amd8111((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), 0xc0 + 17); + memreset_setup_amd8111((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), 0xc0 + 16); //REVC_MEMRST_EN=1 + memreset_setup_amd8111((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), 0xc0 + 17); }
-/** - * this is a no op on this platform. +/** + * this is a no op on this platform. */ void memreset(int controllers, const struct mem_controller *ctrl) { @@ -86,10 +86,10 @@ }
/** - * read a byte from spd. + * read a byte from spd. * @param device device to read from * @param address address in the spd ROM - * @return the value of the byte at that address. + * @return the value of the byte at that address. */ u8 spd_read_byte(u16 device, u8 address) { @@ -97,30 +97,30 @@ return smbus_read_byte(device, address); }
-/** +/** * main for initram for the AMD Serengeti * init_detected Used to indicate that we have been started via init - * The purpose of this code is to not only get ram going, but get any other cpus/cores going. - * The two activities are very tightly connected and not really seperable. + * The purpose of this code is to not only get ram going, but get any other cpus/cores going. + * The two activities are very tightly connected and not really seperable. * The BSP (boot strap processor) Core 0 (BSC) is responsible for all training or all sockets. Note that * this need not be socket 0; one great strength of coreboot, as opposed to other BIOSes, is that it could * always boot with with a CPU in any socket, and even with empty sockets (as opposed to, e.g., the BIOS * that came installed on the Sun Ultra 40, which would freeze if one CPU were not installed). * The bringup proceeds in several sections. The cool part is that this code is run by all CPUs, and - * control flow is managed by seeing which CPU we are -- BSP or AP? - * - * init_detected is used to determine if we did a soft reset as required by a reprogramming of the - * hypertransport links. If we did this kind of reset, bit 11 will be set in the MTRRdefType_MSR MSR. - * That may seem crazy, but there are not lots of places to hide a bit when the CPU does a reset. - * This value is picked up in assembly, or it should be. + * control flow is managed by seeing which CPU we are -- BSP or AP? * + * init_detected is used to determine if we did a soft reset as required by a reprogramming of the + * hypertransport links. If we did this kind of reset, bit 11 will be set in the MTRRdefType_MSR MSR. + * That may seem crazy, but there are not lots of places to hide a bit when the CPU does a reset. + * This value is picked up in assembly, or it should be. + * * @return 0 on success */ int main(void) { - /* sure, we could put this in a .h. It's called precisely once, from this one - * place. And it only relates to the initram stage. I think I'll leave it here. - * That way we can see the definition without grepping the source tree. + /* sure, we could put this in a .h. It's called precisely once, from this one + * place. And it only relates to the initram stage. I think I'll leave it here. + * That way we can see the definition without grepping the source tree. */ void enable_smbus(void); void enable_fid_change_on_sb(u16 sbbusn, u16 sbdn); @@ -161,12 +161,12 @@
init_detected = cpu_init_detected(me.nodeid); printk(BIOS_DEBUG, "init_detected: %d\n", init_detected); - /* well, here we are. For starters, we need to know if this is cpu0 core0. - * cpu0 core 0 will do all the DRAM setup. + /* well, here we are. For starters, we need to know if this is cpu0 core0. + * cpu0 core 0 will do all the DRAM setup. */ bsp_apicid = init_cpus(init_detected, sysinfo);
-// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE); +// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
#if 0 dump_pci_device(PCI_DEV(0, 0x18, 0)); @@ -176,16 +176,16 @@ printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
#if MEM_TRAIN_SEQ == 1 - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched - /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, + /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) + * (there may be apic id conflicts in that case) */ start_all_cores(); wait_all_other_cores_started(bsp_apicid); @@ -195,7 +195,7 @@ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if 0 - //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. + //if your CPU min fid is 1G, you can change HT to 1G and FID to max one time. needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); #endif @@ -220,7 +220,7 @@
// fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - printk(BIOS_INFO, "ht reset -\r\n"); + printk(BIOS_INFO, "ht reset -\n"); soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); } #endif @@ -235,7 +235,7 @@
//do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synconize FID/VID +// init_timer(); // Need to use TMICT to synconize FID/VID
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
@@ -244,7 +244,7 @@ #endif
#if 0 -// dump_pci_devices(); +// dump_pci_devices(); dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); #endif
Modified: coreboot-v3/northbridge/amd/geodelx/raminit.c =================================================================== --- coreboot-v3/northbridge/amd/geodelx/raminit.c 2008-10-28 16:06:28 UTC (rev 957) +++ coreboot-v3/northbridge/amd/geodelx/raminit.c 2008-10-28 17:29:07 UTC (rev 958) @@ -84,7 +84,7 @@ */ void hcf(void) { - printk(BIOS_EMERG, "DIE\r\n"); + printk(BIOS_EMERG, "DIE\n");
/* This guarantees we flush the UART FIFOs (if any) and also ensures * that things, in general, keep going so no debug output is lost.
Modified: coreboot-v3/northbridge/amd/k8/coherent_ht.c =================================================================== --- coreboot-v3/northbridge/amd/k8/coherent_ht.c 2008-10-28 16:06:28 UTC (rev 957) +++ coreboot-v3/northbridge/amd/k8/coherent_ht.c 2008-10-28 17:29:07 UTC (rev 958) @@ -1,5 +1,5 @@ /* - * coherent hypertransport initialization for AMD64 + * coherent hypertransport initialization for AMD64 * This file is part of the coreboot project. * * written by Stefan Reinauer stepan@openbios.org @@ -29,51 +29,51 @@ * nodes : 1 2 4 6 8 * org. : 1x1 2x1 2x2 2x3 2x4 Ladder: - CPU7-------------CPU6 - | | + CPU7-------------CPU6 | | - | | - | | - | | - | | - CPU5-------------CPU4 - | | - | | - | | - | | - | | - | | - CPU3-------------CPU2 - | | - | | | | | | - | | - | | - CPU1-------------CPU0 + | | + | | + | | + CPU5-------------CPU4 + | | + | | + | | + | | + | | + | | + CPU3-------------CPU2 + | | + | | + | | + | | + | | + | | + CPU1-------------CPU0 CONFIG_CROSS_BAR_47_56: - CPU7-------------CPU6 - | ____ ___/ | + CPU7-------------CPU6 + | ____ ___/ | | \ / | - | / | - | /\ | - | / \ | - | ____/ ___ | - CPU5 CPU4 - | | - | | - | | - | | - | | - | | - CPU3-------------CPU2 - | | - | | + | / | + | /\ | + | / \ | + | ____/ ___ | + CPU5 CPU4 | | | | - | | - | | - CPU1-------------CPU0 + | | + | | + | | + | | + CPU3-------------CPU2 + | | + | | + | | + | | + | | + | | + CPU1-------------CPU0 */
#include <mainboard.h> @@ -116,13 +116,13 @@ #endif
#ifndef ENABLE_APIC_EXT_ID - #define ENABLE_APIC_EXT_ID 0 + #define ENABLE_APIC_EXT_ID 0 #endif
-inline void print_linkn (const char *strval, u8 byteval) +inline void print_linkn (const char *strval, u8 byteval) { - printk(BIOS_DEBUG, "%s%02x\n", strval, byteval); + printk(BIOS_DEBUG, "%s%02x\n", strval, byteval); }
void disable_probes(void) @@ -131,7 +131,7 @@ * they don't make sense if only one cpu is available */
- /* Hypertransport Transaction Control Register + /* Hypertransport Transaction Control Register * F0:0x68 * [ 0: 0] Disable read byte probe * 0 = Probes issues @@ -156,7 +156,7 @@
val=pci_conf1_read_config32(NODE_HT(0), HT_TRANSACTION_CONTROL); val |= HTTC_DIS_FILL_P | HTTC_DIS_RMT_MEM_C | HTTC_DIS_P_MEM_C | - HTTC_DIS_MTS | HTTC_DIS_WR_DW_P | HTTC_DIS_WR_B_P | + HTTC_DIS_MTS | HTTC_DIS_WR_DW_P | HTTC_DIS_WR_B_P | HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P; pci_conf1_write_config32(NODE_HT(0), HT_TRANSACTION_CONTROL, val);
@@ -164,16 +164,16 @@
}
-void enable_apic_ext_id(u8 node) +void enable_apic_ext_id(u8 node) { #if ENABLE_APIC_EXT_ID==1 #warning "FIXME Is the right place to enable apic ext id here?"
u32 val;
- val = pci_conf1_read_config32(NODE_HT(node), 0x68); - val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST); - pci_conf1_write_config32(NODE_HT(node), 0x68, val); + val = pci_conf1_read_config32(NODE_HT(node), 0x68); + val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST); + pci_conf1_write_config32(NODE_HT(node), 0x68, val); #endif }
@@ -210,7 +210,7 @@ val &= ~((1<<1)|(1<<0)); pci_conf1_write_config32(NODE_HT(node), 0x6c, val);
- printk(BIOS_SPEW, " done.\r\n"); + printk(BIOS_SPEW, " done.\n"); }
void fill_row(u8 node, u8 row, u32 value) @@ -232,7 +232,7 @@ if (ldt&0x08) return 0x40; if (ldt&0x04) return 0x20; if (ldt&0x02) return 0x00; - + /* we should never get here */ printk(BIOS_SPEW, "Unknown Link\n"); return 0; @@ -256,7 +256,7 @@
val=pci_conf1_read_config32(NODE_HT(7), 0x60); val &= (~7); /* clear low bits. */ - val |= node; /* new node */ + val |= node; /* new node */ pci_conf1_write_config32(NODE_HT(7), 0x60, val);
printk(BIOS_SPEW, " done.\n"); @@ -266,12 +266,12 @@ { /* See if we have a valid connection to dest */ u32 val; - + /* Verify that the coherent hypertransport link is * established and actually working by reading the * remode node's vendor/device id */ - val = pci_conf1_read_config32(NODE_HT(dest),0); + val = pci_conf1_read_config32(NODE_HT(dest),0); if(val != 0x11001022) return 0;
@@ -299,7 +299,7 @@ if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) { freq_cap &= ~(1 << HT_FREQ_1000Mhz); } - + return freq_cap; }
@@ -354,10 +354,10 @@ ln_width1 = ln_width2; } width |= pow2_to_link_width[ln_width1] << 4; - + /* See if I am changing node1's width */ old_width = pci_conf1_read_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH + 1); - old_width &= 0x77; + old_width &= 0x77; needs_reset |= old_width != width;
/* Set node1's widths */ @@ -379,27 +379,27 @@
u8 get_linkn_first(u8 byte) { - if(byte & 0x02) { byte = 0; } - else if(byte & 0x04) { byte = 1; } - else if(byte & 0x08) { byte = 2; } - return byte; + if(byte & 0x02) { byte = 0; } + else if(byte & 0x04) { byte = 1; } + else if(byte & 0x08) { byte = 2; } + return byte; }
u8 get_linkn_last(u8 byte) { - if(byte & 0x02) { byte &= 0x0f; byte |= 0x00; } - if(byte & 0x04) { byte &= 0x0f; byte |= 0x10; } - if(byte & 0x08) { byte &= 0x0f; byte |= 0x20; } - return byte>>4; + if(byte & 0x02) { byte &= 0x0f; byte |= 0x00; } + if(byte & 0x04) { byte &= 0x0f; byte |= 0x10; } + if(byte & 0x08) { byte &= 0x0f; byte |= 0x20; } + return byte>>4; }
u8 get_linkn_last_count(u8 byte) { - byte &= 0x0f; - if(byte & 0x02) { byte &= 0xcf; byte |= 0x00; byte+=0x40; } - if(byte & 0x04) { byte &= 0xcf; byte |= 0x10; byte+=0x40; } - if(byte & 0x08) { byte &= 0xcf; byte |= 0x20; byte+=0x40; } - return byte>>4; + byte &= 0x0f; + if(byte & 0x02) { byte &= 0xcf; byte |= 0x00; byte+=0x40; } + if(byte & 0x04) { byte &= 0xcf; byte |= 0x10; byte+=0x40; } + if(byte & 0x08) { byte &= 0xcf; byte |= 0x20; byte+=0x40; } + return byte>>4; }
void setup_row_local(u8 source, u8 row) /* source will be 7 when it is for temp use*/ @@ -407,13 +407,13 @@ u8 linkn; u32 val; val = 1; - for(linkn = 0; linkn<3; linkn++) { - u8 regpos; + for(linkn = 0; linkn<3; linkn++) { + u8 regpos; u32 reg; regpos = 0x98 + 0x20 * linkn; reg = pci_conf1_read_config32(NODE_HT(source), regpos); if ((reg & 0x17) != 3) continue; /* it is not conherent or not connected*/ - val |= 1<<(linkn+1); + val |= 1<<(linkn+1); } val <<= 16; val |= 0x0101; @@ -427,17 +427,17 @@ val = 1<<(linkn+1); val |= 1<<(linkn+1+8); /*for direct connect response route should equal to request table*/
- if(((source &1)!=(dest &1)) + if(((source &1)!=(dest &1)) #if CONFIG_CROSS_BAR_47_56 && ( (source<4)||(source>5) ) //(6,7) (7,6) should still be here - //(6,5) (7,4) should be here + //(6,5) (7,4) should be here #endif ){ val |= (1<<16); } else { /*for CONFIG_CROSS_BAR_47_56 47, 56, should be here too - and for 47, 56, 57, 75, 46, 64 we need to substract another link to - 6, 7, 6, 6, 7, 7 + and for 47, 56, 57, 75, 46, 64 we need to substract another link to + 6, 7, 6, 6, 7, 7 */ val_s = get_row(temp, source); val |= ((val_s>>16) - (1<<(linkn+1)))<<16; @@ -455,26 +455,26 @@ }
void opt_broadcast_rt_group(const u8 *conn, int num) { - int i; + int i;
- for(i=0; i<num; i+=3) { - opt_broadcast_rt(conn[i], conn[i+1],conn[i+2]); - } + for(i=0; i<num; i+=3) { + opt_broadcast_rt(conn[i], conn[i+1],conn[i+2]); + } } void opt_broadcast_rt_plus(u8 source, u8 dest, u8 kickout) { - u32 val; - val = get_row(source, dest); - val += link_connection(source, kickout)<<16; - fill_row(source, dest, val); -} - + u32 val; + val = get_row(source, dest); + val += link_connection(source, kickout)<<16; + fill_row(source, dest, val); +} + void opt_broadcast_rt_plus_group(const u8 *conn, int num) { - int i; - - for(i=0; i<num; i+=3) { - opt_broadcast_rt_plus(conn[i], conn[i+1],conn[i+2]); - } -} + int i; + + for(i=0; i<num; i+=3) { + opt_broadcast_rt_plus(conn[i], conn[i+1],conn[i+2]); + } +} #endif
void setup_row_direct(u8 source, u8 dest, u8 linkn){ @@ -498,8 +498,8 @@
void setup_remote_node(u8 node) { - static const u8 pci_reg[] = { - 0x44, 0x4c, 0x54, 0x5c, 0x64, 0x6c, 0x74, 0x7c, + static const u8 pci_reg[] = { + 0x44, 0x4c, 0x54, 0x5c, 0x64, 0x6c, 0x74, 0x7c, 0x40, 0x48, 0x50, 0x58, 0x60, 0x68, 0x70, 0x78, 0x84, 0x8c, 0x94, 0x9c, 0xa4, 0xac, 0xb4, 0xbc, 0x80, 0x88, 0x90, 0x98, 0xa0, 0xa8, 0xb0, 0xb8, @@ -520,7 +520,7 @@ pci_conf1_write_config32(NODE_MP(7), reg, value);
} - printk(BIOS_SPEW, "done\r\n"); + printk(BIOS_SPEW, "done\n"); }
#endif /* CONFIG_MAX_PHYSICAL_CPUS > 1*/ @@ -536,7 +536,7 @@ /*for indirect connection, we need to compute the val from val_s(source, source), and val_g(source, gateway) */ u32 val_s; u32 val; -#if !CONFIG_CROSS_BAR_47_56 +#if !CONFIG_CROSS_BAR_47_56 u8 gateway; u8 diff; if(source<dest) { @@ -547,11 +547,11 @@ #endif val_s = get_row(temp, source); val = get_row(temp, gateway); - + val &= 0xffff; val_s >>= 16; val_s &= 0xfe; - + #if !CONFIG_CROSS_BAR_47_56 diff = ((source&1)!=(dest &1)); #endif @@ -569,32 +569,32 @@ if(source<dest) { val_s-=link_connection(temp, source-2); /* -down*/ } else { -#if CONFIG_CROSS_BAR_47_56 - #if 0 +#if CONFIG_CROSS_BAR_47_56 + #if 0 if(source==7) { val_s-=link_connection(temp, 6); // for 7,2 via 5 } else if (source==6){ val_s-=link_connection(temp, 7); // for 6,3 via 4 - } else + } else #endif if (source < gateway) { // for 5, 4 via 7 - val_s-=link_connection(temp, source-2); + val_s-=link_connection(temp, source-2); } else -#endif +#endif val_s-=link_connection(temp, source+2); /* -up*/ } } #endif val &= 0xff; val |= (val_s<<8); - } + }
if(diff) { /* cross rung?*/ val |= (1<<16); } else { val_s = get_row(temp, source); - val |= ((val_s>>16) - link_connection(temp, gateway))<<16; + val |= ((val_s>>16) - link_connection(temp, gateway))<<16; }
fill_row(temp, dest, val); @@ -603,15 +603,15 @@
#if !CONFIG_CROSS_BAR_47_56 void setup_row_indirect(u8 source, u8 dest) -{ +{ setup_row_indirect_x(source, source, dest); } -#else +#else void setup_row_indirect(u8 source, u8 dest, u8 gateway, u8 diff) { setup_row_indirect_x(source, source, dest, gateway, diff); } -#endif +#endif
void setup_row_indirect_group(const u8 *conn, int num) { @@ -659,7 +659,7 @@
void setup_uniprocessor(void) { - printk(BIOS_SPEW, "Enabling UP settings\r\n"); + printk(BIOS_SPEW, "Enabling UP settings\n"); #if CONFIG_LOGICAL_CPUS==1 unsigned tmp = (pci_conf1_read_config32(NODE_MC(0), 0xe8) >> 12) & 3; if (tmp>0) return; @@ -675,9 +675,9 @@ needs_reset = optimize_connection( NODE_HT(opt_conn[i]), 0x80 + link_to_register(link_connection(opt_conn[i],opt_conn[i+1])), NODE_HT(opt_conn[i+1]), 0x80 + link_to_register(link_connection(opt_conn[i+1],opt_conn[i])) ); - } + } return needs_reset; -} +} #endif
#if CONFIG_MAX_PHYSICAL_CPUS > 1 @@ -689,7 +689,7 @@ nodes = 2;
setup_row_local(0, 0); /* it will update the broadcast RT*/ - + val = get_row(0,0); byte = (val>>16) & 0xfe; if(byte<0x2) { /* no coherent connection so get out.*/ @@ -706,7 +706,7 @@ print_linkn("(0,1) link=", byte); setup_row_direct(0,1, byte); setup_temp_row(0, 1); - + verify_connection(7);
/* We found 2 nodes so far */ @@ -716,7 +716,7 @@ setup_row_local(7,1); setup_remote_row_direct(1, 0, byte);
-#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1) +#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1) val = get_row(7,1); byte = (val>>16) & 0xfe; byte = get_linkn_last_count(byte); @@ -731,18 +731,18 @@ print_linkn("\t-->(0,1) link=", byte); setup_row_direct(0,1, byte); setup_temp_row(0, 1); - + verify_connection(7); - + /* We found 2 nodes so far */ val = pci_conf1_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on node7 to node0*/ - print_linkn("\t-->(1,0) link=", byte); + print_linkn("\t-->(1,0) link=", byte); setup_row_local(7,1); setup_remote_row_direct(1, 0, byte); } #endif - + setup_remote_node(1); /* Setup the regs on the remote node */ rename_temp_node(1); /* Rename Node 7 to Node 1 */ enable_routing(1); /* Enable routing on Node 1 */ @@ -776,7 +776,7 @@ }
byte &= 3; /* bit [3,2] is count-1*/ - print_linkn("(0,2) link=", byte); + print_linkn("(0,2) link=", byte); setup_row_direct(0, 2, byte); /*(0,2) direct link done*/
/* We found 3 nodes so far. Now setup a temporary @@ -787,7 +787,7 @@ val = get_row(1,1); byte = ((val>>16) & 0xfe) - link_connection(1,0); byte = get_linkn_first(byte); - print_linkn("(1,3) link=", byte); + print_linkn("(1,3) link=", byte); setup_row_direct(1,3,byte); /* (1, 3) direct link done*/
/* We found 4 nodes so far. Now setup all nodes for 4p */ @@ -796,7 +796,7 @@ static const u8 conn4_1[] = { 0,3, 1,2, - }; + }; #else static const u8 conn4_1[] = { 0,3,2,1, @@ -810,7 +810,7 @@ verify_connection(7); val = pci_conf1_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on 7 to 0*/ - print_linkn("(2,0) link=", byte); + print_linkn("(2,0) link=", byte);
setup_row_local(7,2); setup_remote_row_direct(2, 0, byte); /* node 2 to node 0 direct link done */ @@ -825,7 +825,7 @@
val = pci_conf1_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on 7 to 1*/ - print_linkn("(3,1) link=", byte); + print_linkn("(3,1) link=", byte);
setup_row_local(7,3); setup_remote_row_direct(3, 1, byte); /* node 3 to node 1 direct link done */ @@ -836,7 +836,7 @@ byte = ((val>>16) & 0xfe) - link_connection(2,0); byte = get_linkn_last_count(byte); print_linkn("(2,3) link=", byte & 3); - + setup_row_direct(2,3, byte & 0x3); setup_temp_row(0,2); setup_temp_row(2,3); @@ -850,68 +850,68 @@ val = get_row(2,2); byte = ((val>>16) & 0xfe) - link_connection(2,0); byte = get_linkn_first(byte); - print_linkn("\t-->(2,3) link=", byte); + print_linkn("\t-->(2,3) link=", byte); setup_row_direct(2,3,byte); setup_temp_row(2,3); verify_connection(7); /* to 3*/ } - } + } #endif
val = pci_conf1_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on 7 to 2*/ - print_linkn("(3,2) link=", byte); + print_linkn("(3,2) link=", byte); setup_remote_row_direct(3,2, byte);
#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1) /* set link from 3 to 5 before enable it*/ - val = get_row(7,3); - byte = ((val>>16) & 0xfe) - link_connection(7,2) - link_connection(7,1); - byte = get_linkn_last_count(byte); - if((byte>>2)==1) { /* We should have three coherent links on node 3 for 6p and above*/ - byte &= 3; /*bit [3,2] is count-2*/ - print_linkn("(3,5) link=", byte); - setup_remote_row_direct(3, 5, byte); + val = get_row(7,3); + byte = ((val>>16) & 0xfe) - link_connection(7,2) - link_connection(7,1); + byte = get_linkn_last_count(byte); + if((byte>>2)==1) { /* We should have three coherent links on node 3 for 6p and above*/ + byte &= 3; /*bit [3,2] is count-2*/ + print_linkn("(3,5) link=", byte); + setup_remote_row_direct(3, 5, byte); } - - val = get_row(2,2); - byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0); - byte = get_linkn_last_count(byte);
- if((byte>>2)==1) { /* We should have three coherent link on node 2 for 6p and above*/ - byte &= 3; /* bit [3,2] is count-2*/ - print_linkn("(2,4) link=", byte); - setup_row_direct(2, 4, byte); - } + val = get_row(2,2); + byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0); + byte = get_linkn_last_count(byte); + + if((byte>>2)==1) { /* We should have three coherent link on node 2 for 6p and above*/ + byte &= 3; /* bit [3,2] is count-2*/ + print_linkn("(2,4) link=", byte); + setup_row_direct(2, 4, byte); + } #endif
//Beside 3, 1 is set, We need to make sure 3, 5 is set already in case has three link in 3 #if !CONFIG_CROSS_BAR_47_56 - static const u8 conn4_3[] = { - 3,0, - }; + static const u8 conn4_3[] = { + 3,0, + }; #else - static const u8 conn4_3[] = { - 3,0,1,1, - }; + static const u8 conn4_3[] = { + 3,0,1,1, + }; #endif - setup_remote_row_indirect_group(conn4_3, ARRAY_SIZE(conn4_3)); + setup_remote_row_indirect_group(conn4_3, ARRAY_SIZE(conn4_3));
/* ready to enable RT for Node 3 */ rename_temp_node(3); enable_routing(3); /* enable routing on node 3 (temp.) */
// beside 2, 0 is set, We need to make sure 2, 4 link is set already in case has three link in 2 -#if !CONFIG_CROSS_BAR_47_56 - static const u8 conn4_2[] = { - 2,1, - }; -#else - static const u8 conn4_2[] = { - 2,1,0,1, - }; -#endif - setup_row_indirect_group(conn4_2, ARRAY_SIZE(conn4_2)); +#if !CONFIG_CROSS_BAR_47_56 + static const u8 conn4_2[] = { + 2,1, + }; +#else + static const u8 conn4_2[] = { + 2,1,0,1, + }; +#endif + setup_row_indirect_group(conn4_2, ARRAY_SIZE(conn4_2));
#if 0 /*We need to do sth to reverse work for setup_temp_row (0,1) (1,3) */ @@ -937,27 +937,27 @@ nodes=6;
/* Setup and check temporary connection from Node 0 to Node 4 through 2*/ - val = get_row(2,2); - byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0); - byte = get_linkn_last_count(byte); + val = get_row(2,2); + byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0); + byte = get_linkn_last_count(byte);
- if((byte>>2)==0) { /* We should have three coherent link on node 2 for 6p and above*/ - nodes = 4; - return nodes; - } + if((byte>>2)==0) { /* We should have three coherent link on node 2 for 6p and above*/ + nodes = 4; + return nodes; + }
/* Setup and check temporary connection from Node 0 to Node 5 through 1, 3*/ - /* set link from 3 to 5 before enable it*/ - val = get_row(3,3); - byte = ((val>>16) & 0xfe) - link_connection(3,2) - link_connection(3,1); - byte = get_linkn_last_count(byte); - if((byte>>2)==0) { /* We should have three coherent links on node 3 for 6p and above*/ - nodes = 4; - return nodes; - } - + /* set link from 3 to 5 before enable it*/ + val = get_row(3,3); + byte = ((val>>16) & 0xfe) - link_connection(3,2) - link_connection(3,1); + byte = get_linkn_last_count(byte); + if((byte>>2)==0) { /* We should have three coherent links on node 3 for 6p and above*/ + nodes = 4; + return nodes; + } + /* We found 6 nodes so far. Now setup all nodes for 6p */ -#warning "FIXME we need to find out the correct gateway for 6p" +#warning "FIXME we need to find out the correct gateway for 6p" static const u8 conn6_1[] = { #if !CONFIG_CROSS_BAR_47_56 0, 4, @@ -974,22 +974,22 @@ 2, 5, 3, 0, 3, 4, 2, 0, #endif - }; + };
setup_row_indirect_group(conn6_1, ARRAY_SIZE(conn6_1)); - + for(byte=0; byte<4; byte+=2) { setup_temp_row(byte,byte+2); } verify_connection(7); val = pci_conf1_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /*get default link on 7 to 2*/ - print_linkn("(4,2) link=", byte); - + print_linkn("(4,2) link=", byte); + setup_row_local(7,4); setup_remote_row_direct(4, 2, byte); setup_remote_node(4); /* Setup the regs on the remote node */ - + /* Set indirect connection to 0, to 3 */ //we only need to set 4,0 here static const u8 conn6_2[] = { @@ -998,10 +998,10 @@ #else 4, 0, 2, 0, #endif - }; - + }; + setup_remote_row_indirect_group(conn6_2, ARRAY_SIZE(conn6_2)); - + rename_temp_node(4); enable_routing(4);
@@ -1013,18 +1013,18 @@
val = pci_conf1_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on 7 to 3*/ - print_linkn("(5,3) link=", byte); + print_linkn("(5,3) link=", byte); setup_row_local(7,5); setup_remote_row_direct(5, 3, byte); setup_remote_node(5); /* Setup the regs on the remote node */ - + #if !CONFIG_CROSS_BAR_47_56 /* We need to init link between 4, and 5 direct link */ val = get_row(4,4); byte = ((val>>16) & 0xfe) - link_connection(4,2); byte = get_linkn_last_count(byte); print_linkn("(4,5) link=", byte & 3); - + setup_row_direct(4,5, byte & 0x3); setup_temp_row(0,2); setup_temp_row(2,4); @@ -1033,7 +1033,7 @@
#if CONFIG_MAX_PHYSICAL_CPUS > 6 /* We need to find out which link is to node5 */ - + if((byte>>2)==2) { /* one to node5, one to node2, one to node6*/ val = get_row(7,5); if((val>>16) == 1) { /* that link is to node6, because via node 3 node 5 has been set*/ @@ -1045,37 +1045,37 @@ setup_temp_row(4,5); verify_connection(7); /* to 5*/ } - } + } #endif
val = pci_conf1_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on 7 to 4*/ - print_linkn("(5,4) link=", byte); + print_linkn("(5,4) link=", byte); setup_remote_row_direct(5,4, byte); - + //init 5, 7 here - val = get_row(7,5); - byte = ((val>>16) & 0xfe) - link_connection(7,4) - link_connection(7,3); - byte = get_linkn_last_count(byte); - if((byte>>2)==1) { /* We should have three coherent links on node 5 for 6p and above*/ - byte &= 3; /*bit [3,2] is count-2*/ - print_linkn("(5,7) link=", byte); - setup_remote_row_direct(5, 7, byte); + val = get_row(7,5); + byte = ((val>>16) & 0xfe) - link_connection(7,4) - link_connection(7,3); + byte = get_linkn_last_count(byte); + if((byte>>2)==1) { /* We should have three coherent links on node 5 for 6p and above*/ + byte &= 3; /*bit [3,2] is count-2*/ + print_linkn("(5,7) link=", byte); + setup_remote_row_direct(5, 7, byte); } - + //init 4,6 here - val = get_row(4,4); - byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2); - byte = get_linkn_last_count(byte); + val = get_row(4,4); + byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2); + byte = get_linkn_last_count(byte);
- if((byte>>2)==1) { /* We should have three coherent link on node 4 for 6p and above*/ - byte &= 3; /* bit [3,2] is count-2*/ - print_linkn("(4,6) link=", byte); - setup_row_direct(4, 6, byte); - } - -#endif - + if((byte>>2)==1) { /* We should have three coherent link on node 4 for 6p and above*/ + byte &= 3; /* bit [3,2] is count-2*/ + print_linkn("(4,6) link=", byte); + setup_row_direct(4, 6, byte); + } + +#endif + //We need to set 5,0 here only, We need to set up 5, 7 to make 5,0 /* Set indirect connection to 0, to 3 for indirect we will use clockwise routing */ static const u8 conn6_3[] = { @@ -1084,8 +1084,8 @@ #else 5, 0, 3, 0, #endif - }; - + }; + setup_remote_row_indirect_group(conn6_3, ARRAY_SIZE(conn6_3));
/* ready to enable RT for 5 */ @@ -1096,27 +1096,27 @@ #if !CONFIG_CROSS_BAR_47_56 4, 1, 4, 3, - + 5, 2, 5, 1, - + #else 4, 1, 2, 0, 4, 3, 2, 0, 4, 5, 2, 0, - + 5, 2, 3, 0, 5, 1, 3, 0, 5, 4, 3, 0, - + #endif - }; - + }; + setup_row_indirect_group(conn6_4, ARRAY_SIZE(conn6_4));
#if 0 /* We need to do sth about reverse about setup_temp_row (0,1), (2,4), (1, 3), (3,5) - * It will be done by clear_dead_links + * It will be done by clear_dead_links */ for(byte=0; byte<4; byte++) { clear_temp_row(byte); @@ -1141,18 +1141,18 @@
/* Setup and check temporary connection from Node 0 to Node 6 via 2 and 4 to 7 */ val = get_row(4,4); -#if CONFIG_CROSS_BAR_47_56 +#if CONFIG_CROSS_BAR_47_56 byte = ((val>>16) & 0xfe) - link_connection(4,2); #else byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2); - byte = get_linkn_last_count(byte); /* Max link to 6*/ - if((byte>>2)==0) { /* We should have two or three coherent links on node 4 for 8p*/ - nodes = 6; - return nodes; - } + byte = get_linkn_last_count(byte); /* Max link to 6*/ + if((byte>>2)==0) { /* We should have two or three coherent links on node 4 for 8p*/ + nodes = 6; + return nodes; + } #endif
-#if CONFIG_CROSS_BAR_47_56 +#if CONFIG_CROSS_BAR_47_56 byte = get_linkn_last_count(byte); /* Max link to 6*/ if((byte>>2)<2) { /* We should have two or three coherent links on node 4 for 8p*/ nodes = 6; @@ -1170,13 +1170,13 @@
#if !CONFIG_CROSS_BAR_47_56 /* Setup and check temporary connection from Node 0 to Node 7 through 1, 3, 5*/ - val = get_row(5,5); - byte = ((val>>16) & 0xfe) - link_connection(5,4) - link_connection(5,3); - byte = get_linkn_last_count(byte); - if((byte>>2)==0) { /* We should have three coherent links on node 5 for 6p and above*/ - nodes = 6; - return nodes; - } + val = get_row(5,5); + byte = ((val>>16) & 0xfe) - link_connection(5,4) - link_connection(5,3); + byte = get_linkn_last_count(byte); + if((byte>>2)==0) { /* We should have three coherent links on node 5 for 6p and above*/ + nodes = 6; + return nodes; + } #endif
/* We found 8 nodes so far. Now setup all nodes for 8p */ @@ -1213,12 +1213,12 @@ val = pci_conf1_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on 7 to 4*/ print_linkn("(6,4) link=", byte); - + setup_row_local(7,6); setup_remote_row_direct(6, 4, byte); setup_remote_node(6); /* Setup the regs on the remote node */ /* Set indirect connection to 0, to 3 */ -#warning "FIXME we need to find out the correct gateway for 8p" +#warning "FIXME we need to find out the correct gateway for 8p" static const u8 conn8_2[] = { #if !CONFIG_CROSS_BAR_47_56 6, 0, @@ -1231,55 +1231,55 @@
#if CONFIG_CROSS_BAR_47_56 //init 5, 6 here - /* here init 5, 6 */ - /* Setup and check temporary connection from Node 0 to Node 5 through 1, 3, 5*/ - val = get_row(5,5); - byte = ((val>>16) & 0xfe) - link_connection(5,3); + /* here init 5, 6 */ + /* Setup and check temporary connection from Node 0 to Node 5 through 1, 3, 5*/ + val = get_row(5,5); + byte = ((val>>16) & 0xfe) - link_connection(5,3); #if TRY_HIGH_FIRST == 1 byte = get_linkn_first(byte); #else - byte = get_linkn_last(byte); + byte = get_linkn_last(byte); #endif - print_linkn("(5,6) link=", byte); - setup_row_direct(5, 6, byte); + print_linkn("(5,6) link=", byte); + setup_row_direct(5, 6, byte);
- setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ - for(byte=0; byte<4; byte+=2) { - setup_temp_row(byte+1,byte+3); - } + setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ + for(byte=0; byte<4; byte+=2) { + setup_temp_row(byte+1,byte+3); + } setup_temp_row(5,6);
- verify_connection(7); + verify_connection(7);
val = get_row(7,6); // to chect it if it is node6 before renaming if( (val>>16) == 1) { // it is real node 7 so swap it - /* We need to recompute link to 6 */ - val = get_row(5,5); - byte = ((val>>16) & 0xfe) - link_connection(5,3); + /* We need to recompute link to 6 */ + val = get_row(5,5); + byte = ((val>>16) & 0xfe) - link_connection(5,3); #if TRY_HIGH_FIRST == 1 - byte = get_linkn_first(byte); + byte = get_linkn_first(byte); #else - byte = get_linkn_last(byte); + byte = get_linkn_last(byte); #endif - print_linkn("\t-->(5,6) link=", byte); - setup_row_direct(5, 6, byte); + print_linkn("\t-->(5,6) link=", byte); + setup_row_direct(5, 6, byte); #if 0 - setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ - for(byte=0; byte<4; byte+=2) { - setup_temp_row(byte+1,byte+3); - } + setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ + for(byte=0; byte<4; byte+=2) { + setup_temp_row(byte+1,byte+3); + } #endif setup_temp_row(5,6);
- verify_connection(7); + verify_connection(7); } - val = pci_conf1_read_config32(NODE_HT(7), 0x6c); - byte = (val>>2) & 0x3; /* get default link on 7 to 5*/ - print_linkn("(6,5) link=", byte); - setup_remote_row_direct(6, 5, byte); - /*Till now 56, 65 done */ + val = pci_conf1_read_config32(NODE_HT(7), 0x6c); + byte = (val>>2) & 0x3; /* get default link on 7 to 5*/ + print_linkn("(6,5) link=", byte); + setup_remote_row_direct(6, 5, byte); + /*Till now 56, 65 done */ #endif - + rename_temp_node(6); enable_routing(6);
@@ -1293,27 +1293,27 @@
val = pci_conf1_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on 7 to 5*/ - print_linkn("(7,5) link=", byte); + print_linkn("(7,5) link=", byte); setup_row_local(7,7); setup_remote_row_direct(7, 5, byte);
#else - val = get_row(4,4); - byte = ((val>>16) & 0xfe) - link_connection(4,2) - link_connection(4,6); - byte = get_linkn_first(byte); - print_linkn("(4,7) link=", byte); - setup_row_direct(4, 7, byte); + val = get_row(4,4); + byte = ((val>>16) & 0xfe) - link_connection(4,2) - link_connection(4,6); + byte = get_linkn_first(byte); + print_linkn("(4,7) link=", byte); + setup_row_direct(4, 7, byte);
- /* Setup and check temporary connection from Node 0 to Node 7 through 2, and 4*/ + /* Setup and check temporary connection from Node 0 to Node 7 through 2, and 4*/ for(byte=0; byte<4; byte+=2) { setup_temp_row(byte,byte+2); }
- verify_connection(7); + verify_connection(7);
val = pci_conf1_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on 7 to 4*/ - print_linkn("(7,4) link=", byte); + print_linkn("(7,4) link=", byte); setup_row_local(7,7); setup_remote_row_direct(7, 4, byte); /* till now 4-7, 7-4 done. */ @@ -1326,12 +1326,12 @@ val = get_row(5,5); byte = ((val>>16) & 0xfe) - link_connection(5,3) - link_connection(5,6); byte = get_linkn_first(byte); - print_linkn("(5,7) link=", byte); + print_linkn("(5,7) link=", byte); setup_row_direct(5, 7, byte); - + setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ for(byte=0; byte<4; byte+=2) { - setup_temp_row(byte+1,byte+3); + setup_temp_row(byte+1,byte+3); }
verify_connection(7); @@ -1341,7 +1341,7 @@ print_linkn("(7,5) link=", byte); setup_remote_row_direct(7, 5, byte); /*Till now 57, 75 done */ - + #endif
/* We need to init link between 6, and 7 direct link */ @@ -1373,12 +1373,12 @@ 2, 7, 3, 7, 4, 7, - + 6, 1, 6, 2, 6, 3, 6, 5, - + 7, 0, 7, 1, 7, 2, @@ -1386,68 +1386,68 @@ 7, 4, #else
- - 4, 5, 6, 1, - 5, 4, 7, 1,
- 6, 1, 5, 0, // or 4, 1 - 6, 2, 4, 0, - 6, 3, 5, 0, // or 4, 1 + 4, 5, 6, 1, + 5, 4, 7, 1,
- 7, 0, 4, 0, // or 5, 1 - 7, 1, 5, 0, - 7, 2, 4, 0, // or 5, 1 - 7, 3, 5, 0, + 6, 1, 5, 0, // or 4, 1 + 6, 2, 4, 0, + 6, 3, 5, 0, // or 4, 1
+ 7, 0, 4, 0, // or 5, 1 + 7, 1, 5, 0, + 7, 2, 4, 0, // or 5, 1 + 7, 3, 5, 0, + 0, 7, 2, 0, /* restore it*/ 1, 7, 3, 0, 2, 7, 4, 1, 3, 7, 5, 0,
- 2, 5, 4, 1, /* reset it */ - 3, 4, 5, 1, + 2, 5, 4, 1, /* reset it */ + 3, 4, 5, 1,
4, 1, 2, 1, /* reset it */ 4, 3, 2, 1,
5, 2, 3, 1, /* reset it */ 5, 0, 3, 1, - + #endif };
setup_row_indirect_group(conn8_3, ARRAY_SIZE(conn8_3));
#if CONFIG_CROSS_BAR_47_56 - /* for 47, 56, 57, 75, 46, 64 we need to substract another link to - 6, 7, 6, 6, 7, 7 */ - static const u8 conn8_4[] = { + /* for 47, 56, 57, 75, 46, 64 we need to substract another link to + 6, 7, 6, 6, 7, 7 */ + static const u8 conn8_4[] = { //direct - 4, 7, 6, - 5, 6, 7, - 5, 7, 6, - 7, 5, 6, - 4, 6, 7, - 6, 4, 7, + 4, 7, 6, + 5, 6, 7, + 5, 7, 6, + 7, 5, 6, + 4, 6, 7, + 6, 4, 7,
//in direct - 0, 6, 1, - 0, 7, 1, - - 1, 6, 0, - 1, 7, 0, + 0, 6, 1, + 0, 7, 1,
- 2, 6, 3, + 1, 6, 0, + 1, 7, 0, + + 2, 6, 3, // 2, 7, 3, + - + // 3, 6, 1, + 3, 7, 2, - + 6, 0, 7, 6, 1, 7, // needed for via 5 6, 1, 4, // ??? 6, 2, 7, - 6, 3, 7, // needed for via 5 + 6, 3, 7, // needed for via 5 6, 3, 4, //??? 7, 0, 6, // needed for via 4 7, 0, 5, //??? @@ -1455,21 +1455,21 @@ 7, 2, 6, // needed for via 4 7, 2, 5, //??? 7, 3, 6, - }; + };
- opt_broadcast_rt_group(conn8_4, ARRAY_SIZE(conn8_4)); + opt_broadcast_rt_group(conn8_4, ARRAY_SIZE(conn8_4));
- static const u8 conn8_5[] = { - 2, 7, 0, + static const u8 conn8_5[] = { + 2, 7, 0,
- 3, 6, 1, - }; - - opt_broadcast_rt_plus_group(conn8_5, ARRAY_SIZE(conn8_5)); + 3, 6, 1, + }; + + opt_broadcast_rt_plus_group(conn8_5, ARRAY_SIZE(conn8_5)); #endif
- + /* ready to enable RT for Node 7 */ enable_routing(7); /* enable routing on node 7 (temp.) */
@@ -1485,56 +1485,56 @@ { unsigned nodes;
- printk(BIOS_SPEW, "Enabling SMP settings\r\n"); - + printk(BIOS_SPEW, "Enabling SMP settings\n"); + nodes = setup_smp2(); #if CONFIG_MAX_PHYSICAL_CPUS > 2 - if(nodes == 2) + if(nodes == 2) nodes = setup_smp4(); #endif - + #if CONFIG_MAX_PHYSICAL_CPUS > 4 if(nodes == 4) nodes = setup_smp6(); #endif
#if CONFIG_MAX_PHYSICAL_CPUS > 6 - if(nodes == 6) + if(nodes == 6) nodes = setup_smp8(); #endif
- printk(BIOS_DEBUG,"%02x nodes initialized.\r\n", nodes); - + printk(BIOS_DEBUG,"%02x nodes initialized.\n", nodes); + return nodes; }
unsigned verify_mp_capabilities(unsigned nodes) { unsigned node, mask; - + mask = 0x06; /* BigMPCap */
for (node=0; node<nodes; node++) { mask &= pci_conf1_read_config32(NODE_MC(node), 0xe8); } - + switch(mask) { #if CONFIG_MAX_PHYSICAL_CPUS > 2 case 0x02: /* MPCap */ if(nodes > 2) { - print_err("Going back to DP\r\n"); + print_err("Going back to DP\n"); return 2; } break; #endif case 0x00: /* Non SMP */ if(nodes >1 ) { - print_err("Going back to UP\r\n"); + print_err("Going back to UP\n"); return 1; } break; } - + return nodes;
} @@ -1556,14 +1556,14 @@ fill_row(node, row, DEFAULT); } } - + /* Update the local row */ for( node=0; node<nodes; node++) { u32 val = 0; for(row =0; row<nodes; row++) { val |= get_row(node, row); } - fill_row(node, node, (((val & 0xff) | ((val >> 8) & 0xff)) << 16) | 0x0101); + fill_row(node, node, (((val & 0xff) | ((val >> 8) & 0xff)) << 16) | 0x0101); } } #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */ @@ -1580,7 +1580,7 @@ }
return totalcpus; - + } #endif
@@ -1599,14 +1599,14 @@ total_cpus = nodes; } #endif - + /* set up cpu count and node count and enable Limit * Config Space Range for all available CPUs. * Also clear non coherent hypertransport bus range * registers on Hammer A0 revision. */
- printk(BIOS_SPEW, "coherent_ht_finalize\r\n"); + printk(BIOS_SPEW, "coherent_ht_finalize\n"); for (node = 0; node < nodes; node++) { u32 dev; u32 val; @@ -1623,13 +1623,13 @@ pci_conf1_write_config32(dev, 0x60, val);
/* Only respond to real cpu pci configuration cycles - * and optimize the HT settings + * and optimize the HT settings */ val=pci_conf1_read_config32(dev, HT_TRANSACTION_CONTROL); val &= ~((HTTC_BUF_REL_PRI_MASK << HTTC_BUF_REL_PRI_SHIFT) | (HTTC_MED_PRI_BYP_CNT_MASK << HTTC_MED_PRI_BYP_CNT_SHIFT) | (HTTC_HI_PRI_BYP_CNT_MASK << HTTC_HI_PRI_BYP_CNT_SHIFT)); - val |= HTTC_LIMIT_CLDT_CFG | + val |= HTTC_LIMIT_CLDT_CFG | (HTTC_BUF_REL_PRI_8 << HTTC_BUF_REL_PRI_SHIFT) | (3 << HTTC_MED_PRI_BYP_CNT_SHIFT) | (3 << HTTC_HI_PRI_BYP_CNT_SHIFT); @@ -1637,7 +1637,7 @@
}
- printk(BIOS_SPEW, "done\r\n"); + printk(BIOS_SPEW, "done\n"); }
int apply_cpu_errata_fixes(unsigned int nodes) @@ -1669,8 +1669,8 @@ reg = 0x98 + (link * 0x20); link_type = pci_conf1_read_config32(f0_dev, reg); /* Only handle coherent links */ - if ((link_type & (LinkConnected | InitComplete|NonCoherent)) == - (LinkConnected|InitComplete)) + if ((link_type & (LinkConnected | InitComplete|NonCoherent)) == + (LinkConnected|InitComplete)) { cmd &= ~(0xff << (link *8)); cmd |= 0x25 << (link *8); @@ -1686,65 +1686,65 @@
int optimize_link_coherent_ht(void) { - int needs_reset = 0; + int needs_reset = 0;
- unsigned nodes; + unsigned nodes;
- nodes = get_nodes(); + nodes = get_nodes();
#if CONFIG_MAX_PHYSICAL_CPUS > 1 - if(nodes>1) { - needs_reset |= optimize_connection( - NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)), - NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) ); - } + if(nodes>1) { + needs_reset |= optimize_connection( + NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)), + NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) ); + }
#if CONFIG_MAX_PHYSICAL_CPUS > 2 - if(nodes>2) { - /* optimize physical connections - by LYH */ - static const u8 opt_conn4[] = { - 0,2, - 1,3, - 2,3, - }; - needs_reset |= optimize_connection_group(opt_conn4, ARRAY_SIZE(opt_conn4)); - } + if(nodes>2) { + /* optimize physical connections - by LYH */ + static const u8 opt_conn4[] = { + 0,2, + 1,3, + 2,3, + }; + needs_reset |= optimize_connection_group(opt_conn4, ARRAY_SIZE(opt_conn4)); + } #endif
#if CONFIG_MAX_PHYSICAL_CPUS > 4 - if(nodes>4) { - static const u8 opt_conn6[] ={ - 2, 4, - 3, 5, - #if !CONFIG_CROSS_BAR_47_56 - 4, 5, - #endif - }; - needs_reset |= optimize_connection_group(opt_conn6, ARRAY_SIZE(opt_conn6)); - } + if(nodes>4) { + static const u8 opt_conn6[] ={ + 2, 4, + 3, 5, + #if !CONFIG_CROSS_BAR_47_56 + 4, 5, + #endif + }; + needs_reset |= optimize_connection_group(opt_conn6, ARRAY_SIZE(opt_conn6)); + } #endif
#if CONFIG_MAX_PHYSICAL_CPUS > 6 - if(nodes>6) { - static const u8 opt_conn8[] ={ - 4, 6, - #if CONFIG_CROSS_BAR_47_56 - 4, 7, - 5, 6, - #endif - 5, 7, - 6, 7, - }; - needs_reset |= optimize_connection_group(opt_conn8, ARRAY_SIZE(opt_conn8)); - } + if(nodes>6) { + static const u8 opt_conn8[] ={ + 4, 6, + #if CONFIG_CROSS_BAR_47_56 + 4, 7, + 5, 6, + #endif + 5, 7, + 6, 7, + }; + needs_reset |= optimize_connection_group(opt_conn8, ARRAY_SIZE(opt_conn8)); + } #endif
#endif
- needs_reset |= apply_cpu_errata_fixes(nodes); - needs_reset |= optimize_link_read_pointers(nodes); + needs_reset |= apply_cpu_errata_fixes(nodes); + needs_reset |= optimize_link_read_pointers(nodes);
- return needs_reset; + return needs_reset; }
void setup_coherent_ht_domain(void) @@ -1755,9 +1755,9 @@ enable_bsp_routing();
#if CONFIG_MAX_PHYSICAL_CPUS > 1 - nodes = setup_smp(); - nodes = verify_mp_capabilities(nodes); - clear_dead_routes(nodes); + nodes = setup_smp(); + nodes = verify_mp_capabilities(nodes); + clear_dead_routes(nodes); #endif
if (nodes == 1) {
Modified: coreboot-v3/northbridge/amd/k8/cpu.c =================================================================== --- coreboot-v3/northbridge/amd/k8/cpu.c 2008-10-28 16:06:28 UTC (rev 957) +++ coreboot-v3/northbridge/amd/k8/cpu.c 2008-10-28 17:29:07 UTC (rev 958) @@ -148,7 +148,7 @@ e0_later_single_core = 0; } if(e0_later_single_core) { - printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\r\n"); + printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\n");
j=1; }
Modified: coreboot-v3/southbridge/amd/amd8111/stage1_smbus.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/stage1_smbus.c 2008-10-28 16:06:28 UTC (rev 957) +++ coreboot-v3/southbridge/amd/amd8111/stage1_smbus.c 2008-10-28 17:29:07 UTC (rev 958) @@ -42,7 +42,7 @@
/* Yes, the ACPI device controls the SMBUS. */ if (!pci_conf1_find_on_bus(0, PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ACPI, &dev)){ - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); }
pci_conf1_write_config32(dev, 0x58, SMBUS_IO_BASE | 1); @@ -56,7 +56,7 @@
/* clear any lingering errors, so the transaction will run */ outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS); - printk(BIOS_SPEW, "SMBus controller enabled\r\n"); + printk(BIOS_SPEW, "SMBus controller enabled\n"); }
int smbus_wait_until_ready(u16 smbus_io_base) @@ -71,7 +71,7 @@ break; } if(loops == (SMBUS_TIMEOUT / 2)) { - outw(inw(smbus_io_base + SMBGSTATUS), + outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS); } } while(--loops); @@ -85,7 +85,7 @@ do { u16 val; smbus_delay(); - + val = inw(smbus_io_base + SMBGSTATUS); if (((val & 0x8) == 0) | ((val & 0x0037) != 0)) { break; @@ -102,7 +102,7 @@ if (smbus_wait_until_ready(smbus_io_base) < 0) { return SMBUS_WAIT_UNTIL_READY_TIMEOUT; } - + /* setup transaction */ /* disable interrupts */ outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL); @@ -147,7 +147,7 @@ if (smbus_wait_until_ready(smbus_io_base) < 0) { return SMBUS_WAIT_UNTIL_READY_TIMEOUT; } - + /* setup transaction */ /* disable interrupts */ outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL); @@ -190,7 +190,7 @@ if (smbus_wait_until_ready(smbus_io_base) < 0) { return SMBUS_WAIT_UNTIL_READY_TIMEOUT; } - + /* setup transaction */ /* disable interrupts */ outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL); @@ -302,18 +302,18 @@ */ u8 spd_read_byte(u16 device, u8 address) { - return smbus_read_byte(device, address); + return smbus_read_byte(device, address); }
/** * memreset_setup_amd8111 - * This function is part of a complex dance played between the mainboard and - * the southbridge. We don't want to export SMBUS_IO_BASE, but neither can the - * amd8111 know about what GPIOs connect to what reset lines. So + * This function is part of a complex dance played between the mainboard and + * the southbridge. We don't want to export SMBUS_IO_BASE, but neither can the + * amd8111 know about what GPIOs connect to what reset lines. So * we split the difference. The mainboard must call this function with bytes * to be output to accomplish reset, as well as the offset from IOBASE; - * amd8111 will output those bytes to SMBIOS_IOBASE. - * The caller of this function must have called spd_init for it to work correctly. + * amd8111 will output those bytes to SMBIOS_IOBASE. + * The caller of this function must have called spd_init for it to work correctly. */ void memreset_setup_amd8111(u8 data, u16 offset) {
Modified: coreboot-v3/southbridge/amd/sb600/stage1.c =================================================================== --- coreboot-v3/southbridge/amd/sb600/stage1.c 2008-10-28 16:06:28 UTC (rev 957) +++ coreboot-v3/southbridge/amd/sb600/stage1.c 2008-10-28 17:29:07 UTC (rev 958) @@ -69,7 +69,7 @@ { u32 dev; if (!pci_conf1_find_device(PCI_VENDOR_ID_ATI, 0x4385, &dev)){ - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); } return pci_conf1_read_config8(dev, 0x08); } @@ -277,10 +277,10 @@ /* SMBus Device, BDF:0-20-0 */ printk(BIOS_INFO, "sb600_devices_por_init(): SMBus Device, BDF:0-20-0\n"); if (!pci_conf1_find_device(PCI_VENDOR_ID_ATI, 0x4385, &dev)){ - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); } - printk(BIOS_INFO, "SMBus controller enabled, sb revision is 0x%x\r\n", - get_sb600_revision()); + printk(BIOS_INFO, "SMBus controller enabled, sb revision is 0x%x\n", + get_sb600_revision());
/* sbPorAtStartOfTblCfg */ /* Set A-Link bridge access address. This address is set at device 14h, function 0, register 0xf0. @@ -392,7 +392,7 @@ byte |= ((1 << 1) + (1 << 6)); /*0x42, save the configuraion for port 0x80. */ pci_conf1_write_config8(dev, 0x4A, byte);
- /* Set LPC ROM size, it has been done in sb600_lpc_init(). + /* Set LPC ROM size, it has been done in sb600_lpc_init(). * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB; * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB * pci_conf1_write_config16(dev, 0x68, 0x000e) @@ -401,8 +401,8 @@ /* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */ pci_conf1_write_config8(dev, 0x7C, 0x05);
- /* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM, - * TODO: I don't know what are their mean? */ + /* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM, + * TODO: I don't know what these mean? */ printk(BIOS_INFO, "sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n"); pci_conf1_find_device(PCI_VENDOR_ID_ATI, 0x4384, &dev); /* I don't know why CIM tried to write into a read-only reg! */ @@ -416,7 +416,7 @@
pci_conf1_write_config8(dev, 0x40, 0x26);
- /* I don't know why CIM set reg0x1c as 0x11. + /* I don't know why CIM set reg0x1c as 0x11. * System will block at sdram_initialize() if I set it before call sdram_initialize(). * If it is necessary to set reg0x1c as 0x11, please call this function after sdram_initialize(). * pci_conf1_write_config8(dev, 0x1c, 0x11); @@ -569,7 +569,7 @@ byte |= (1 << 3); pci_conf1_write_config8(dev, 0x41, byte);
- /* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles) + /* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles) * generated PCIRST#. */ byte = pm_ioread(0x65); byte |= (1 << 4);
Modified: coreboot-v3/southbridge/nvidia/mcp55/stage1.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/stage1.c 2008-10-28 16:06:28 UTC (rev 957) +++ coreboot-v3/southbridge/nvidia/mcp55/stage1.c 2008-10-28 17:29:07 UTC (rev 958) @@ -436,7 +436,7 @@ */ u32 bdf; if (!pci_conf1_find_device(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP55_HT, &bdf)) { - die("PCI_DEVICE_ID_NVIDIA_MCP55_HT not found\r\n"); + die("PCI_DEVICE_ID_NVIDIA_MCP55_HT not found\n"); }
return (bdf>>15) & 0x1f;
Modified: coreboot-v3/southbridge/nvidia/mcp55/stage1_smbus.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/stage1_smbus.c 2008-10-28 16:06:28 UTC (rev 957) +++ coreboot-v3/southbridge/nvidia/mcp55/stage1_smbus.c 2008-10-28 17:29:07 UTC (rev 958) @@ -192,7 +192,7 @@ { u32 bdf; if (!pci_conf1_find_device(0x10de, 0x0368, &bdf)) { - die("SMBUS controller not found\r\n"); + die("SMBUS controller not found\n"); }
printk(BIOS_DEBUG, "SMBus controller enabled\n"); @@ -261,6 +261,6 @@ */ u8 spd_read_byte(u16 device, u8 address) { - return smbus_read_byte(device, address); + return smbus_read_byte(device, address); }
Modified: coreboot-v3/superio/ite/it8716f/superio.c =================================================================== --- coreboot-v3/superio/ite/it8716f/superio.c 2008-10-28 16:06:28 UTC (rev 957) +++ coreboot-v3/superio/ite/it8716f/superio.c 2008-10-28 17:29:07 UTC (rev 958) @@ -74,14 +74,14 @@
/* Read out current value of FAN_CTL control register (0x14). */ value = pnp_read_index(base, 0x14); - printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, read value = 0x%02x\r\n", - base + 0x14, value); + printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, read value = 0x%02x\n", + base + 0x14, value);
/* Set FAN_CTL control register (0x14) polarity to high, and - activate fans 1, 2 and 3. */ + * activate fans 1, 2 and 3. */ pnp_write_index(base, 0x14, value | 0x87); - printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, writing value = 0x%02x\r\n", - base + 0x14, value | 0x87); + printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, writing value = 0x%02x\n", + base + 0x14, value | 0x87); } #endif
Modified: coreboot-v3/superio/winbond/w83627hf/superio.c =================================================================== --- coreboot-v3/superio/winbond/w83627hf/superio.c 2008-10-28 16:06:28 UTC (rev 957) +++ coreboot-v3/superio/winbond/w83627hf/superio.c 2008-10-28 17:29:07 UTC (rev 958) @@ -34,28 +34,28 @@ #include <statictree.h> #include "w83627hf.h"
-static void pnp_enter_ext_func_mode(struct device * dev) +static void pnp_enter_ext_func_mode(struct device * dev) { - outb(0x87, dev->path.pnp.port); - outb(0x87, dev->path.pnp.port); + outb(0x87, dev->path.pnp.port); + outb(0x87, dev->path.pnp.port); }
-static void pnp_exit_ext_func_mode(struct device * dev) +static void pnp_exit_ext_func_mode(struct device * dev) { - outb(0xaa, dev->path.pnp.port); + outb(0xaa, dev->path.pnp.port); }
static void pnp_write_index(u16 port_base, u8 reg, u8 value) { - outb(reg, port_base); - outb(value, port_base + 1); + outb(reg, port_base); + outb(value, port_base + 1); }
static u8 pnp_read_index(u16 port_base, u8 reg) { - outb(reg, port_base); - return inb(port_base + 1); -} + outb(reg, port_base); + return inb(port_base + 1); +}
static void enable_hwm_smbus(struct device * dev) { /* set the pin 91,92 as I2C bus */ @@ -73,14 +73,14 @@ #warning Fix CMOS handling // get_option(&power_on, "power_on_after_fail"); pnp_enter_ext_func_mode(dev); - pnp_write_index(dev->path.pnp.port,7,0x0a); + pnp_write_index(dev->path.pnp.port,7,0x0a); value = pnp_read_config(dev, 0xE4); value &= ~(3<<5); if(power_on) { value |= (1<<5); } pnp_write_config(dev, 0xE4, value); - pnp_exit_ext_func_mode(dev); + pnp_exit_ext_func_mode(dev); }
static void init_hwm(u16 base) @@ -90,24 +90,24 @@
unsigned hwm_reg_values[] = { /* reg, mask, data */ - 0x40, 0xff, 0x81, /* start HWM */ - 0x48, 0xaa, 0x2a, /* set SMBus base to 0x54>>1 */ - 0x4a, 0x21, 0x21, /* set T2 SMBus base to 0x92>>1 and T3 SMBus base to 0x94>>1 */ - 0x4e, 0x80, 0x00, - 0x43, 0x00, 0xff, - 0x44, 0x00, 0x3f, - 0x4c, 0xbf, 0x18, - 0x4d, 0xff, 0x80 /* turn off beep */ - + 0x40, 0xff, 0x81, /* start HWM */ + 0x48, 0xaa, 0x2a, /* set SMBus base to 0x54>>1 */ + 0x4a, 0x21, 0x21, /* set T2 SMBus base to 0x92>>1 and T3 SMBus base to 0x94>>1 */ + 0x4e, 0x80, 0x00, + 0x43, 0x00, 0xff, + 0x44, 0x00, 0x3f, + 0x4c, 0xbf, 0x18, + 0x4d, 0xff, 0x80 /* turn off beep */ + };
- for (i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) { - reg = hwm_reg_values[i]; - value = pnp_read_index(base, reg); + for (i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) { + reg = hwm_reg_values[i]; + value = pnp_read_index(base, reg); value &= 0xff & hwm_reg_values[i+1]; value |= 0xff & hwm_reg_values[i+2];
- printk(BIOS_SPEW, "base = 0x%04x, reg = 0x%02x, value = 0x%02x\r\n", base, reg,value); + printk(BIOS_SPEW, "base = 0x%04x, reg = 0x%02x, value = 0x%02x\n", base, reg,value);
pnp_write_index(base, reg, value); } @@ -129,7 +129,7 @@
conf = dev->device_configuration; switch(dev->path.pnp.device) { - case W83627HF_SP1: + case W83627HF_SP1: res0 = find_resource(dev, PNP_IDX_IO0); #warning init_uart8250 //init_uart8250(res0->base, &conf->com1); @@ -144,55 +144,55 @@ res1 = find_resource(dev, PNP_IDX_IO1); init_pc_keyboard(res0->base, res1->base, &keyboard); break; - case W83627HF_HWM: - res0 = find_resource(dev, PNP_IDX_IO0); + case W83627HF_HWM: + res0 = find_resource(dev, PNP_IDX_IO0); #define HWM_INDEX_PORT 5 - init_hwm(res0->base + HWM_INDEX_PORT); - break; - case W83627HF_ACPI: - init_acpi(dev); - break; + init_hwm(res0->base + HWM_INDEX_PORT); + break; + case W83627HF_ACPI: + init_acpi(dev); + break; } }
void w83627hf_pnp_set_resources(struct device * dev) { - pnp_enter_ext_func_mode(dev); + pnp_enter_ext_func_mode(dev); pnp_set_resources(dev); - pnp_exit_ext_func_mode(dev); - -} - + pnp_exit_ext_func_mode(dev); + +} + void w83627hf_pnp_enable_resources(struct device * dev) -{ - pnp_enter_ext_func_mode(dev); - pnp_enable_resources(dev); - switch(dev->path.pnp.device) { +{ + pnp_enter_ext_func_mode(dev); + pnp_enable_resources(dev); + switch(dev->path.pnp.device) { case W83627HF_HWM: printk(BIOS_DEBUG, "w83627hf hwm smbus enabled\n"); enable_hwm_smbus(dev); break; } - pnp_exit_ext_func_mode(dev); + pnp_exit_ext_func_mode(dev);
}
void w83627hf_pnp_enable(struct device * dev) {
- if (!dev->enabled) { - pnp_enter_ext_func_mode(dev); + if (!dev->enabled) { + pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0);
- pnp_exit_ext_func_mode(dev); - } + pnp_exit_ext_func_mode(dev); + } } static void phase3_chip_setup_dev(struct device *dev); struct device_operations w83627hf_ops = { - .phase3_chip_setup_dev = phase3_chip_setup_dev, - .phase3_enable = w83627hf_pnp_enable_resources, + .phase3_chip_setup_dev = phase3_chip_setup_dev, + .phase3_enable = w83627hf_pnp_enable_resources, .phase4_read_resources = pnp_read_resources, .phase4_set_resources = w83627hf_pnp_set_resources, .phase5_enable_resources = w83627hf_pnp_enable, @@ -200,18 +200,18 @@ };
static struct pnp_info pnp_dev_info[] = { - { &w83627hf_ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &w83627hf_ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &w83627hf_ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &w83627hf_ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - // No 4 { 0,}, - { &w83627hf_ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, - { &w83627hf_ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &w83627hf_ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, }, - { &w83627hf_ops, W83627HF_GPIO2, }, - { &w83627hf_ops, W83627HF_GPIO3, }, - { &w83627hf_ops, W83627HF_ACPI, }, - { &w83627hf_ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, }, + { &w83627hf_ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &w83627hf_ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &w83627hf_ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &w83627hf_ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + // No 4 { 0,}, + { &w83627hf_ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, + { &w83627hf_ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &w83627hf_ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, }, + { &w83627hf_ops, W83627HF_GPIO2, }, + { &w83627hf_ops, W83627HF_GPIO3, }, + { &w83627hf_ops, W83627HF_ACPI, }, + { &w83627hf_ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, }, };