the following patch was just integrated into master: commit 265da9b2659d2e18bb59e6a99792492fac71bdc8 Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Tue Feb 28 00:24:15 2012 +0200
Intel cpus: cache actual size of the Flash ROM device
Cache was enabled for the last 4 MB below 4 GB when ramstage is loaded. This does not cover the case of a 8 MB Flash and could overlap with some system device placed at high memory.
Use the actual device size for the cache region. Mainboard may override this with Kconfig CACHE_ROM_SIZE if necessary.
Change-Id: I622223b1e2af0b3c1831f3570b74eacfde7189dc Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com
Reviewed-By: Patrick Georgi patrick@georgi-clan.de at Sat Mar 31 11:54:01 2012, giving +2 See http://review.coreboot.org/641 for details.
-gerrit