Author: mjones Date: Mon Feb 28 00:53:11 2011 New Revision: 6391 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6391
Log: Prepare for next patches (Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode).
No change of behaviour intended.
Refactor FAM10 fidvid . prep_fid_change was already long and it'd get longer with forthcoming patches. We now take apart F3x[84:80], ACPI Power State Control Registers, to its own function.
Signed-off-by: Xavi Drudis Ferran xdrudis@tinet.cat Acked-by: Marc Jones marcj303@gmail.com
Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c
Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 00:50:30 2011 (r6390) +++ trunk/src/cpu/amd/model_10xxx/fidvid.c Mon Feb 28 00:53:11 2011 (r6391) @@ -257,7 +257,6 @@ pci_write_config32(dev, 0xD8, dword); } } -
static void config_nb_syn_ptr_adj(device_t dev) { /* Note the following settings are additional from the ported @@ -269,6 +268,14 @@
}
+static void config_acpi_pwr_state_ctrl_regs(device_t dev) { + /* Rev B settings - FIXME: support other revs. */ + u32 dword = 0xA0E641E6; + pci_write_config32(dev, 0x84, dword); + dword = 0xE600A681; + pci_write_config32(dev, 0x80, dword); +} + static void prep_fid_change(void) { u32 dword; @@ -295,12 +302,7 @@
config_nb_syn_ptr_adj(dev);
- /* Rev B settings - FIXME: support other revs. */ - dword = 0xA0E641E6; - pci_write_config32(dev, 0x84, dword); - - dword = 0xE600A681; - pci_write_config32(dev, 0x80, dword); + config_acpi_pwr_state_ctrl_regs(dev);
dword = pci_read_config32(dev, 0x80); printk(BIOS_DEBUG, " F3x80: %08x \n", dword);