Author: uwe Date: 2008-09-07 19:18:10 +0200 (Sun, 07 Sep 2008) New Revision: 861
Modified: coreboot-v3/include/spd.h Log: Port some of the recent SPD DDR2 #defines from v2 to v3 (trivial).
Signed-off-by: Uwe Hermann uwe@hermann-uwe.de Acked-by: Uwe Hermann uwe@hermann-uwe.de
Modified: coreboot-v3/include/spd.h =================================================================== --- coreboot-v3/include/spd.h 2008-09-06 20:39:25 UTC (rev 860) +++ coreboot-v3/include/spd.h 2008-09-07 17:18:10 UTC (rev 861) @@ -75,6 +75,17 @@ #define SPD_CMD_SIGNAL_INPUT_HOLD_TIME 33 /* Command and address signal input hold time */ #define SPD_DATA_SIGNAL_INPUT_SETUP_TIME 34 /* Data signal input setup time */ #define SPD_DATA_SIGNAL_INPUT_HOLD_TIME 35 /* Data signal input hold time */ +#define SPD_WRITE_RECOVERY_TIME 36 /* Write recovery time (tWR) */ +#define SPD_INT_WRITE_TO_READ_DELAY 37 /* Internal write to read command delay (tWTR) */ +#define SPD_INT_READ_TO_PRECHARGE_DELAY 38 /* Internal read to precharge command delay (tRTP) */ +#define SPD_MEM_ANALYSIS_PROBE_PARAMS 39 /* Memory analysis probe characteristics */ +#define SPD_BYTE_41_42_EXTENSION 40 /* Extension of byte 41 (tRC) and byte 42 (tRFC) */ +#define SPD_MIN_ACT_TO_ACT_AUTO_REFRESH 41 /* Minimum active to active auto refresh (tRCmin) */ +#define SPD_MIN_AUTO_REFRESH_TO_ACT 42 /* Minimum auto refresh to active/auto refresh (tRFC) */ +#define SPD_MAX_DEVICE_CYCLE_TIME 43 /* Maximum device cycle time (tCKmax) */ +#define SPD_MAX_DQS_DQ_SKEW 44 /* Maximum skew between DQS and DQ (tDQSQ) */ +#define SPD_MAX_READ_DATAHOLD_SKEW 45 /* Maximum read data-hold skew factor (tQHS) */ +#define SPD_PLL_RELOCK_TIME 46 /* PLL relock time */ #define SPD_SPD_DATA_REVISION_CODE 62 /* SPD data revision code */ #define SPD_CHECKSUM_FOR_BYTES_0_TO_62 63 /* Checksum for bytes 0-62 */ #define SPD_MANUFACTURER_JEDEC_ID_CODE 64 /* Manufacturer's JEDEC ID code, per EIA/JEP106 (bytes 64-71) */ @@ -107,6 +118,7 @@ #define SPD_MEMORY_TYPE_SGRAM_DDR 6 #define SPD_MEMORY_TYPE_SDRAM_DDR 7 #define SPD_MEMORY_TYPE_SDRAM_DDR2 8 +#define SPD_MEMORY_TYPE_SDRAM_DDR3 0xb
/* SPD_MODULE_VOLTAGE values. */ #define SPD_VOLTAGE_TTL 0 /* 5.0 Volt/TTL */ @@ -130,6 +142,11 @@ #define SPD_CAS_LATENCY_3_5 0x20 #define SPD_CAS_LATENCY_4_0 0x40
+#define SPD_CAS_LATENCY_DDR2_3 (1 << 3) +#define SPD_CAS_LATENCY_DDR2_4 (1 << 4) +#define SPD_CAS_LATENCY_DDR2_5 (1 << 5) +#define SPD_CAS_LATENCY_DDR2_6 (1 << 6) + /* SPD_SUPPORTED_BURST_LENGTHS values. */ #define SPD_BURST_LENGTH_1 1 #define SPD_BURST_LENGTH_2 2 @@ -145,4 +162,3 @@ u8 spd_read_byte(u16 device, u8 address);
#endif /* _SPD_H_ */ -