Hello to all! Need quick help! I am poorly versed in the question so detailed answers are welcome :) !
As a result of the motherboard developers laziness the hard straps for ASPEED AST2510 chip were not properly prescribed. Now I need to write register 0x1e6e2070 with necessary bits [5][15] to '1' at an early stage of coreboot booting. Motherboard based on Intel Atom SOC Processor C3758 (DENVERTON_NS). The AST2510 chip is always located on (B3:D0:F0) [0x1a03:0x2000] after aspeed bridge (B2:D0:F0) [1a03/1150]:
PCI: 00:09.0 scanning... do_pci_scan_bridge for PCI: 00:09.0 PCI: pci_scan_bus for bus 02 PCI: 02:00.0 subordinate PCI PCI: 02:00.0 [1a03/1150] enabled PCI: 02:00.0 scanning... do_pci_scan_bridge for PCI: 02:00.0 PCI: pci_scan_bus for bus 03 PCI: 03:00.0 [1a03/2000] ops PCI: 03:00.0 [1a03/2000] enabled
The code below located in romstage.c file successfully finds the device:
pci_devfn_t dev; /* ASPEED AST2510 Graphics (B3:D0:F0). */ dev = PCI_DEV(3, 0, 0); uint32_t id = pci_read_config32(dev, 0); // id = (0x1a03<<16) | 0x2000 => Aspeed graphics!
What to do next, I do not quite understand. Based on the Aspeed driver from /src/driver/aspeed/common/ast_main.c (int ast_driver_load) I compiled the code, but I need to somehow get the filled "struct device* dev".
1. Please tell me how get the filled "struct device" in my case? Something like this could be: pcidev_path_on_root(PCI_DEV(3, 0, 0)); ? 2. Do I need to make the device "enable" before access at its registers? Maybe I something else forgot?
3. Is it necessary to somehow release the resources allocated? Release the assigned base addresses maybe?
Estimated Code:
#define AST_IO_MM_OFFSET (0x380)
struct device *dev; struct resource *res;
void __iomem *regs; void __iomem *ioregs; bool io_space_uses_mmap;
/* PCI BAR 1 */ res = find_resource(dev, 0x14); regs = res2mmio(res, 0, 0); /* PCI BAR 2 */ io_space_uses_mmap = false; res = find_resource(dev, 0x18); /* If we don't have IO space at all, use MMIO now and assume the chip has MMIO enabled by default (rev 0x20 and higher).*/
if (!(res->flags & IORESOURCE_IO)) { printk("platform has no IO space, trying MMIO\n"); ioregs = regs + AST_IO_MM_OFFSET; io_space_uses_mmap = true; }
/* "map" IO regs if the above hasn't done so already */ if (!ioregs) { ioregs = res2mmio(res, 0, 0); if (!ioregs) { ret = -EIO; goto out_free; } /* Adjust the I/O space location to match expectations (the code expects offset 0x0 to be I/O location 0x380) */ ioregs = (void *)AST_IO_MM_OFFSET; }
iowrite32(0x1e6e0000, regs + 0xf004); // Re-mapping Base address register iowrite32(0x1, regs + 0xf000); // Enable P-Bus to AHB bridge iowrite32(0x1688a8a8, regs + 0x12000); // Unprotect SCU Registers, if read 0x1 - Unprotected! iowrite32(0xf900d2e6, 0x12070); // Write ASPEED SCU70 (0x1e6e2070) register with new straps bits.