Marshall Buschman (mbuschman@lucidmachines.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/32
-gerrit
commit a405a454515236058ca9c6b93c6051af0fafc070 Author: Marshall Buschman mbuschman@lucidmachines.com Date: Mon Jun 20 21:23:36 2011 -0500
Move SB800 clock init earlier
Committing Scott's e350m1 changes (svn r6585): Move SB800 clock init earlier, Fixes problem where initial serial port output is garbled.
Change-Id: If05aa37726b962e8994ee69bf1882fcfae56aa19 Signed-off-by: Scott Duplichan scott@notabs.org Signed-off-by: Marshall Buschman mbuschman@lucidmachines.com --- src/mainboard/asrock/e350m1/romstage.c | 26 +++++++++++++++----------- 1 files changed, 15 insertions(+), 11 deletions(-)
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 61de9f6..e822899 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -55,6 +55,21 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time __writemsr(0xc0010062, 0);
+ if (boot_cpu()) { + u8 reg8; + // SB800: program AcpiMmioEn to enable MMIO access to MiscCntrl register + outb(0x24, 0xCD6); + reg8 = inb(0xCD7); + reg8 |= 1; + reg8 &= ~(1 << 1); + outb(0x24, 0xCD6); + outb(reg8, 0xCD7); + + // program SB800 MiscCntrl + *(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ + *(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) |= 1 << 1; /* 48Mhz */ + } + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_poweron_init(); @@ -63,17 +78,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } - //reg8 = pmio_read(0x24); - outb(0x24, 0xCD6); - reg8 = inb(0xCD7); - reg8 |= 1; - reg8 &= ~(1 << 1); - //pmio_write(0x24, reg8); - outb(0x24, 0xCD6); - outb(reg8, 0xCD7); - - *(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ - *(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) |= 1 << 1; /* 48Mhz */
/* Halt if there was a built in self test failure */ post_code(0x34);