Re: [LinuxBIOS] [LinuxBIOSv2] WIP Support for RCA RM4100 - i82830 Complete

Quoting Uwe Hermann :
> I'd like to wait with committing until (a) a few issues are resolved,
> and (b) the board boots up to a Linux login prompt, if possible.

Ok but the problem now is related to the Southbridge i82801DB not  
anything I have written.
> > Index: src/mainboard/rca/rm4100/Config.lb
>
> RCA RM4100 is the name of the box as a whole, correct? Can you look at
> the mainboard and search for a vendor and mainboard name/ID?
> If there is one (printed on the PCB), we should use that as the
> target name in LinuxBIOS (as we did with other embedded stuff).

Well, it was originally made by Thomson Electronics Model: IP1000 but
RCA now manufactures the device and board as Model: RM4100
> Very good, you're using the generic 'smscsuperio' code. Once this boots
> to a Linux prompt, please let me know how well the code works for this
> Super I/O. There are still some TODOs in the 'smscsuperio' code.
>
> Which Super I/O model is on your board?

I have the SMSC LPC47M192-NC
> > 			device pnp 2e.0 off # Floppy
> > 				io 0x60 = 0x3f0
> > 				irq 0x70 = 6
> > 				drq 0x74 = 2
> > 			end
> > 			device pnp 2e.3 off # Parallel Port
> > 				io 0x60 = 0x378
> > 				irq 0x70 = 7
> > 			end
> > 			device pnp 2e.4 on # Com1
> > 				io 0x60 = 0x3f8
> > 				irq 0x70 = 4
> > 			end
> > 			device pnp 2e.5 off # Com2 / IR
> > 				io 0x60 = 0x2f8
> > 				irq 0x70 = 3
> > 			end
> > 			device pnp 2e.7 on # Keyboard
> > 				io 0x60 = 0x60
> > 				io 0x62 = 0x64
> > 				irq 0x70 = 1 # Keyboard interrupt
> > 				irq 0x72 = 12 # Mouse interrupt
> > 			end
> > 			device pnp 2e.9 off end # Game Port
> > 			device pnp 2e.a off end # PME
> > 			device pnp 2e.b off end # MPU-401
>
> Did you check whether the above values are all correct?

Yes, these are all the devices according to the datasheet.
> > chip cpu/intel/socket_PGA370
>
> Is this a Socket 370 board?

It is a Low Voltage Intel® Celeron® processor (Micro-FC-BGA) 733MHz  
but socket_PGA370 seems to work ok.
> Is this copied from another target, or written manually, or based on
> getpir output?

I used getpir output to create this.
> Once the board boots, please check if it's correct, i.e. if all devices
> work as expected.
> > +/* The onboard 128MB PC133 memory does not have a SPD eeprom so the
> > values have to be set manually,
> > the onboard memory is located in socket1 (0x51).
> >
> > +*/
> > +static inline int spd_read_byte(unsigned device, unsigned address)
> > +{
> > int i;
> > if (device == 0x50){
> > return smbus_read_byte(device, address);
>
> If 0x51 is RAM, what is 0x50 then?

0x50 is a so-dimm socket, 0x51 is onboard memory
> > } else if (device == 0x51){
> > for (i=0; i < (sizeof spd_table/sizeof spd_table[0]); i++){
> > 	if (spd_table[i].address == address){
> > 		return spd_table[i].data;
> > 	}
> > }
> > return 0xFF; /* This line returns 0xFF when address not found */
> > } else {
> > return 0xFF; /* returns 0xFF on any failures */
> > }
> >
> > +}
> >
> > +static void ac97_io_enable(void)
> > +{
> > device_t dev;
> > /* Set the ac97 audio device staticly. */
> > dev = PCI_DEV(0x0, 0x1f, 0x5);
> > /* Enable access to the IO space. */
> > pci_write_config8(dev, 0x41, 0x01);
>
> Is this really needed? The lines in Config.lb should instruct LinuxBIOS
> to properly enable the device, no?

If I don't do this when booting the ac97 memory resuources become read only.
> > Index: src/northbridge/intel/i82830/i82830.h
>
> [...]
> > +#define VID 0X00     /* Vendor Identification Register - Default   
> > Value 0X8086 - 16 bits Read Only */
> > +#define DID 0X02     /* Device Identification Register - Default   
> > Value 0X3575 - 16 bits Read Only */
> > +#define RID 0X08     /* Revision Identification Register - Default  
> >  Value 0X04 - 8 bits Read Only */
> > +#define SUBC 0X0A     /* SUB-Class Code Register - Default Value   
> > 0X00 - 8 bits Read Only */
> > +#define BCC 0X0B     /* Base Class Code Register - Default Value   
> > 0X06 - 8 bits Read Only */
> > +#define MLT 0X0D     /* Master Latency Timer Register - Default   
> > Value 0X00 - 8 bits Read Only */
> > +#define HDR 0X0E     /* Header Type Register - Default Value 0X00
> > 8 bits Read Only */
> >
> > +#define CAPPTR 0X34     /* Capablities Pointer - Default Value   
> > 0X40 - 8 bits Read Only */
> >
> > +#define PCICMD0 0X04  /* PCI Command Register - Default Value   
> > 0X0006 - 16 bits */
> > +#define PCISTS 0X06  /* PCI Status Register - Default Value 0X0010
> > 16 bits */
>
> I think you can drop all of the above (and maybe also SVID/SID), they're
> generic PCI registers, not i82830 specific at all.

These are mostly here just for reference.
> Not _too_ different to i815, it seems. Any chance this code could be
> merged into the i815 code, with some i830 specifics special-cased?
> If that's possible I'd really prefer it over creating another
> near-duplicate code base.

Actually the i830 is more like the i845 chipset, but it is adaptable,  
I'm sure.
> Did you enable the ram_check() function and did you verify
> that the RAM init actually works?

Yes.
> After the above fixes, the code is in good shape IMO, so we should be
> able to commit it as soon as a Linux boot works.
>
> You can split out the northbridge code in an extra patch if you want,
> I think we can commit that even before your board works, so that others
> who have i830 boards can work with it.

Will Do.
> But please consider merging the i830 code into the i815 code, if at all
> possible.
>
> Uwe.

Like I said the i830 is more like the i845 chipset, but it is  
adaptable, I'm sure.

Thanks - Joe