I think you guys are going in circles :-)
Here is my chance to help :-)
For the last gazillion years the IO ports on the intel parts have been about the same. You could probably even reference an old PIIX document to see how they are programmed. (you'd be surprised how much all the new stuff looks like a PIIX ...)
You could also take the basic code from superio probe and modify it to work on southbridge parts -- I looked at this, it looked doable, I ran out of time and need for it.
And, yes, who knows why, but on all of the ICH parts (you pronounce this "ICK!") I know of the GPIO IOBASE is not a config space register. BLEAH!
So you do something like this: 1. id the vendor/dev id (use libpci -- see flashrom for example) 2. From that, call a chip-specific function that returns the GPIO IOBASE set. Plan to make it an arbitrary sized array or a struct that has the info (use the code from flashrom) 3. With that data from (2), write chip-specific functions that display: - enable info - direction info - value of the gpio port info (Some of the code from the superio tool might be very useful here --it's all inx/outx bit mask/extract bits at this point, nothing special)
Anyway, this is a bit more work, but ... if you do it, we'll have a tool we can extend the same way as the superiotool, and your grandchildren will thank you.
btw, this type of tool is incredibly useful, as you doubtless know. We found the FLASH write enable on the K8N in about 10 minutes with superiotool, and it only took 10 mins as we had to write a little support code for the superio ... would have taken 30 seconds otherwise. I feel so safe now that I know how well the write line on FLASH is protected :-)
ron