[coreboot] Re: BIOS chip address range?

[Peter Stuge]

Rafael Send wrote:
> If I theoretically had a flash chip that was larger than 128Mb, it
> requires 3-4 byte addressing.

The de facto standard commands all use 3 byte addresses.
> Does / could coreboot support such large memory, or would the
> limitation live somewhere else in the system?

coreboot doesn't need to know about SPI. (It does, e.g. to enable block
locks for some chips, but that's unrelated to booting.)

The platform hardware exposes the SPI flash mapped at top of 4 GByte of
physical address space.

The platform hardware would have to know to use 4 byte address commands.

I don't know if any platforms do - I guess that they don't.

//Peter