Re: [coreboot] FSPInitiNot Returning

[Jin, Huang]

Hi David,

May I know which FSP version are you using? If it is not difficult, enabling early serial output in coreboot before calling FSP will be helpful for trouble shooting your problem, and your development in the long run.

Thanks,
Huang

From: David Crammer [mailto:[e-mail]]
Sent: Wednesday, December 09, 2015 11:05 AM
To: Jin, Huang
Cc: [e-mail]
Subject: Re: [coreboot] FSPInitiNot Returning

Yes. This is a broadwell platform.  I removed the UPD settings and left them default (passed NULL for that pointer in the parameters to FspInit).  It seems to get past that point now.  I did notice that the SMBus addresses for the DIMMs were being set to different values than what is listed in the binary configuration tool.  This and the PMBASE settings were really the only things changed in the coreboot source.  Maybe this is the cause?
I don't really have any logs as I'm only debugging with port 0x80 values.

On Wed, Dec 9, 2015 at 11:19 AM, Jin, Huang <[e-mail]> wrote:
Hi David,

I am assuming you are using a Broadwell platform and Broadwell FSP. Could you please share some logs? I might be able to help you.

Thanks,
Huang

From: coreboot [mailto:[e-mail]] On Behalf Of David Crammer
Sent: Wednesday, December 09, 2015 8:19 AM
To: [e-mail]
Subject: [coreboot] FSPInitiNot Returning

Hello All,
    I’m running into a rather strange error and I’m hoping someone has had experience with this or may know about what I’m seeing.

I’m working with an Intel I5 5350U on an ADLINK platform.  I’m getting to the part of the boot sequence where FspInit is called but it never returns to the specified return function.  The system resets 3 times with a post code (codes inserted before and in return function) indicating that it got to the FspInit call and reset.  After the third time, it settles on a post code of 0xBE.  I can’t find reference to the post code anywhere.

Any help would be greatly appreciated.  In case anyone is interested, I’ll reply with any updates.

--David Crammer