cbmem log after cold boot (power off) and hibernate (success resume). Did MRC cache present (and used) in case of IvyBridge CPU and native memory init without FSP?
11.06.2019, 08:29, "Kyösti Mälkki" kyosti.malkki@gmail.com:
On Mon, Jun 10, 2019 at 11:22 PM Andrew A. I. aidron@yandex.ru wrote:
Hello, Kyösti! cbmem log in attachment. I am rebooting and/or powering off after upgrading corboot firmware for verify. It doesn't help, as I remember.
Logs from both a cold boot and hibernation resume would be needed for comparison.
But this pretty much sounds like the case of entering ACPI S4 from a boot that did memory training and wrote MRC CACHE in SPI. This is the known failing case described earlier.
Kyösti _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org