On Tue, Oct 27, 2009 at 2:04 PM, Gregg Levine gregg.drwho8@gmail.comwrote:
On Tue, Oct 27, 2009 at 4:51 PM, David Hendricks dhendrix@google.com wrote:
On Tue, Oct 27, 2009 at 6:06 AM, Darmawan Salihun darmawan.salihun@gmail.com wrote:
What is the BIOS RAM in AMD SB7XX used for?
Looks like scratchpad memory to me. From the public doc:
3.3 BIOS RAM The SB700 has 256 bytes of BIOS RAM. Data in this RAM is preserved until RSMRST# or S5 is asserted, or until power is lost. This RAM is accessed using index and data registers at CD4h/CD5h.
Might it be enough to act as a very, very small cache-as-RAM substitute until CAR can be set up?
On Tue, Oct 27, 2009 at 6:06 AM, Darmawan Salihun darmawan.salihun@gmail.com wrote:
Is it to buffer the BIOS contents from SPI flash chip prior to execution of the very first instruction? I recall that it's impossible to execute code directly in an SPI chip.
That's correct, afaik.
David Hendricks (dhendrix) Systems Software Engineer, Google Inc.
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Hello! This is well and good David. Thank you! And as it happens Google Mail goofed on its spam scanning, and even mistook this one for a phishing scheme. According to other folk at Google they themselves obviously use the Google Mail service internally, so I do not see why this would have happened.
Weird! Maybe it's because of the external website link in my post. Thanks for catching that, Gregg.
For reference, the public doc I referenced is available from AMD's main developer manual site: http://developer.amd.com/DOCUMENTATION/GUIDES/Pages/default.aspx
The doc I referred to is here: http://developer.amd.com/assets/43366_sb7xx_bdg_pub_1.00.pdf . It's pretty vague, though. The register reference guide ( http://developer.amd.com/assets/43009_sb7xx_rrg_pub_1.00.pdf ) has some additional information on how to enable and utilize the BIOS RAM area for those curious.