Hi,
as preparation for the kconfig merge, here are some changes from the kconfig tree that are unrelated to kconfig itself.
20090805-1-ttys0-rename Takes care of the different CONFIG_* names of the variable containing the serial I/O port
20090805-2-config-prefixes Some more CONFIG_* prefixes that were missing
20090805-3-empty-files These changes exist mostly to make diff happy, which ignores empty files (or rather: Make Patrick happy when he's using diff). Maybe the right way would be to delete those files.
Signed-off-by: Patrick Georgi patrick.georgi@coresystems.de
Index: coreboot-v2/src/arch/i386/lib/printk_init.c =================================================================== --- coreboot-v2.orig/src/arch/i386/lib/printk_init.c +++ coreboot-v2/src/arch/i386/lib/printk_init.c @@ -8,6 +8,10 @@ #include <stdarg.h> #include <console/loglevel.h>
+#if !defined(CONFIG_TTYS0_BASE) +#define CONFIG_TTYS0_BASE CONFIG_SERIAL_IOBASE +#endif + /* printk's without a loglevel use this.. */ #define DEFAULT_MESSAGE_LOGLEVEL 4 /* BIOS_WARNING */
Index: coreboot-v2/src/include/uart8250.h =================================================================== --- coreboot-v2.orig/src/include/uart8250.h +++ coreboot-v2/src/include/uart8250.h @@ -1,6 +1,10 @@ #ifndef UART8250_H #define UART8250_H
+#if !defined(CONFIG_TTYS0_BASE) +#define CONFIG_TTYS0_BASE CONFIG_SERIAL_IOBASE +#endif + struct uart8250 { unsigned int baud; /* Do I need an lcs parameter here? */
Index: coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c =================================================================== --- coreboot-v2.orig/src/southbridge/intel/i82801gx/i82801gx_lpc.c +++ coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c @@ -273,7 +273,7 @@ static void i82801gx_power_options(devic /* Set up power management block and determine sleep mode */ pmbase = pci_read_config16(dev, 0x40) & 0xfffe; reg32 = inl(pmbase + 0x04); // PM1_CNT -#if HAVE_ACPI_RESUME +#if CONFIG_HAVE_ACPI_RESUME acpi_slp_type = (((reg32 >> 10) & 7) == 5) ? 3 : 0; printk_debug("PM1_CNT: 0x%08x --> acpi_sleep_type: %x\n", reg32, acpi_slp_type); Index: coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_power.h =================================================================== --- coreboot-v2.orig/src/southbridge/intel/i82801gx/i82801gx_power.h +++ coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_power.h @@ -23,7 +23,7 @@ #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2
-#ifndef MAINBOARD_POWER_ON_AFTER_FAIL -#define MAINBOARD_POWER_ON_AFTER_FAIL MAINBOARD_POWER_ON +#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif
Index: coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smihandler.c =================================================================== --- coreboot-v2.orig/src/southbridge/intel/i82801gx/i82801gx_smihandler.c +++ coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smihandler.c @@ -300,7 +300,7 @@ static void southbridge_smi_sleep(unsign * CMOS or even better from GNVS. Right now it's hard * coded at compile time. */ - u8 s5pwr = MAINBOARD_POWER_ON_AFTER_FAIL; + u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
/* First, disable further SMIs */ reg8 = inb(pmbase + SMI_EN);
Index: coreboot-v2/src/cpu/x86/32bit/entry32.lds =================================================================== --- /dev/null +++ coreboot-v2/src/cpu/x86/32bit/entry32.lds @@ -0,0 +1 @@ +# Index: coreboot-v2/src/cpu/x86/fpu/Config.lb =================================================================== --- /dev/null +++ coreboot-v2/src/cpu/x86/fpu/Config.lb @@ -0,0 +1 @@ +# Index: coreboot-v2/src/cpu/x86/mmx/Config.lb =================================================================== --- /dev/null +++ coreboot-v2/src/cpu/x86/mmx/Config.lb @@ -0,0 +1 @@ +# Index: coreboot-v2/src/cpu/x86/sse/Config.lb =================================================================== --- /dev/null +++ coreboot-v2/src/cpu/x86/sse/Config.lb @@ -0,0 +1 @@ +# Index: coreboot-v2/src/drivers/generic/generic/Config.lb =================================================================== --- /dev/null +++ coreboot-v2/src/drivers/generic/generic/Config.lb @@ -0,0 +1 @@ +# Index: coreboot-v2/src/northbridge/intel/i855pm/i855pm.h =================================================================== --- /dev/null +++ coreboot-v2/src/northbridge/intel/i855pm/i855pm.h @@ -0,0 +1 @@ +#