Hello,
I was looking at the Local APIC code in coreboot and was wondering about `lapic_write_atomic` in src/include/cpu/x86/lapic.h. This uses an atomic XCHG to write to Local APIC registers. I would like to understand why this would be necessary, because none of the OSes I've seen or worked on do anything similar. ALso the Intel SDM discourages acceses that are not plain loads/stores.
In the coreboot code, this function seems to exist for a really long time. I've found this from 2004:
#ifdef CONFIG_X86_GOOD_APIC # define FORCE_READ_AROUND_WRITE 0 # define lapic_read_around(x) lapic_read(x) # define lapic_write_around(x,y) lapic_write((x),(y)) #else # define FORCE_READ_AROUND_WRITE 1 # define lapic_read_around(x) lapic_read(x) # define lapic_write_around(x,y) lapic_write_atomic((x),(y)) #endif
This seems to indicate that using atomic writes was a workaround of some kind. Does anyone know more?
Thanks! Julian