[coreboot] [commit] r5919 - in trunk/src/southbridge/amd: rs690 rs780

[repository service]

Author: ruik
Date: Thu Oct  7 20:25:04 2010
New Revision: 5919
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5919

Log:
RS780 function ProgK8TempMmioBase is setting a reserved
bit in the AMD processor 'MMIO Limit Address Register'.
I suspect it is because of a typo where 0x80 was entered
as 0x8. If 0x80 is used, then the strap configuration
register accesses become non-posted, which is how the
Shiner reference BIOS does it.

Signed-off-by: Scott Duplichan 
Acked-by: Rudolf Marek

Modified:
   trunk/src/southbridge/amd/rs690/rs690_cmn.c
   trunk/src/southbridge/amd/rs780/rs780_cmn.c

Modified: trunk/src/southbridge/amd/rs690/rs690_cmn.c
==============================================================================
--- trunk/src/southbridge/amd/rs690/rs690_cmn.c	Thu Oct  7 18:24:28 2010	(r5918)
+++ trunk/src/southbridge/amd/rs690/rs690_cmn.c	Thu Oct  7 20:25:04 2010	(r5919)
@@ -206,7 +206,7 @@
    if (in_out) {
    	pci_write_config32(k8_f1, 0xbc,
    			   (((pcie_base_add + 0x10000000 -
-				     1) >> 8) & 0xffffff00) | 0x8);
+				     1) >> 8) & 0xffffff00) | 0x80);
    	pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3);
    	pci_write_config32(k8_f1, 0xb4,
    			   ((mmio_base_add + 0x10000000 -

Modified: trunk/src/southbridge/amd/rs780/rs780_cmn.c
==============================================================================
--- trunk/src/southbridge/amd/rs780/rs780_cmn.c	Thu Oct  7 18:24:28 2010	(r5918)
+++ trunk/src/southbridge/amd/rs780/rs780_cmn.c	Thu Oct  7 20:25:04 2010	(r5919)
@@ -204,7 +204,7 @@
    if (in_out) {
    	pci_write_config32(k8_f1, 0xbc,
    			   (((pcie_base_add + 0x10000000 -
-				     1) >> 8) & 0xffffff00) | 0x8);
+				     1) >> 8) & 0xffffff00) | 0x80);
    	pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3);
    	pci_write_config32(k8_f1, 0xb4,
    			   ((mmio_base_add + 0x10000000 -