On 29.03.2019 18:03, Nico Huber wrote:
Hi Michal,
Hi Nico,
On 29.03.19 16:49, Michal Zygowski wrote:
I am wondering what is the format of CPU-DRAM DQ byte map for FSP-M configuration. Typically there are 64 DQ lanes per non-ECC SODIMM/DIMM (correct me if I'm wrong) for DDR4 for example. But the DQ map is an 2x12 array, so I assume 12 bytes for each channel (why not 8 bytes?). My questions are:
- Why there are more bytes in array than DQ lanes?
it's actually not an array but a rather complex structure. You can find some clues in the Skylake FSP Integration Guide [1] and also in coreboot header files [2]. I have no idea why the documentation was removed from future guides.
I have read the KabyLake FSP Integration guide, but there is only an information about the values' existence in FSP UPD. Definitely will look at those files too.
- How should I define the DQ map? Does 0xFF or 0x00 mean 1 to 1 mapping?
If you have DDR4 (SO)DIMMs, you probably shouldn't. [2] mentions that it's for memory-down configurations with LPDDR3 only. And, AFAIR, an investigation into the deep of the KBL FSP source didn't find any relation to DDR4.
Good to know I will not have to bother with it.
I know about 3 Rcomp resistors of the chipset and what they are for, but what RcompTarget is? In the code I can see function `mainboard_fill_rcomp_strength_data` and begin to wonder what rcomp strength is (not Rcomp Target?). How to correctly fill RcompTarget FSP-M configuration?
Please tell me if you find out ;) even Intel developers working on coreboot don't know. Some insider came back quoting identifiers from comments in the FSP header... identifiers nowhere to be found in source/documentation.
I have some clues about it actually. I have found some information after diving into network abyss. There is a motherboard manual[3] which gives a tiny bit of explanation of those RcompTarget values. Here is the fragment from BIOS settings, Memory Overclocking section, page 89:
RcompTarget[RdOdt] Enter a value for desired Rcomptarget[RdOdt]. The default is 60.
RcompTarget[WrDS] Enter a value for desired RcompTarget[WrDS]. The default is 26.
RcompTarget[WrDSCmd] Enter a value for desired RcompTarget[WrDSCmd]. The default is 20.
RcompTarget[WrDSCtl] Enter a value for desired RcompTarget[WrDSCtl]. The default is 20.
RcompTarget[WrDSClk] Enter a value for desired RcompTarget[WrDSClk]. The default is 26.
Interestingly also 5 byte values as defined in FSP UPD. The strings in square brackets seem to be some DDR standard terms. Maybe someone on the mailing list would know something about it.
My guess is that the targets are either computed or even measured by some very confidential tool.
Nico
[1] https://github.com/IntelFsp/FSP/raw/master/SkylakeFspBinPkg/Docs/SkylakeFspI... [2] https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/broadwell/i... _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Thank You Nico. Best regards,
[3] https://www.supermicro.com/manuals/motherboard/X299/MNL-2001.pdf