Zheng Bao (zheng.bao@amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1155
-gerrit
commit 8d1524b3d11ee5c9133909cb26863d5be03cc073 Author: zbao fishbaozi@gmail.com Date: Mon Jul 2 14:19:14 2012 +0800
AGESA F15tn: AMD family15 AGESA code for Trinity
AMD AGESA code for trinity.
Change-Id: I847a54b15e8ce03ad5dbc17b95ee6771a9da0592 Signed-off-by: Zheng Bao zheng.bao@amd.com Signed-off-by: zbao fishbaozi@gmail.com --- src/vendorcode/amd/agesa/Makefile.inc | 1 + src/vendorcode/amd/agesa/f15tn/AGESA.h | 3718 ++ src/vendorcode/amd/agesa/f15tn/AMD.h | 506 + src/vendorcode/amd/agesa/f15tn/Dispatcher.h | 78 + .../amd/agesa/f15tn/Include/AdvancedApi.h | 193 + .../amd/agesa/f15tn/Include/ComalInstall.h | 186 + .../amd/agesa/f15tn/Include/CommonReturns.h | 151 + src/vendorcode/amd/agesa/f15tn/Include/Filecode.h | 1113 + .../amd/agesa/f15tn/Include/GeneralServices.h | 228 + .../amd/agesa/f15tn/Include/GnbInterface.h | 138 + src/vendorcode/amd/agesa/f15tn/Include/GnbPage.h | 2020 + src/vendorcode/amd/agesa/f15tn/Include/Ids.h | 1365 + src/vendorcode/amd/agesa/f15tn/Include/IdsHt.h | 150 + .../amd/agesa/f15tn/Include/OptionApmInstall.h | 113 + .../amd/agesa/f15tn/Include/OptionC6Install.h | 205 + .../amd/agesa/f15tn/Include/OptionCpbInstall.h | 211 + .../Include/OptionCpuCacheFlushOnHaltInstall.h | 154 + .../f15tn/Include/OptionCpuCoreLevelingInstall.h | 149 + .../agesa/f15tn/Include/OptionCpuFamiliesInstall.h | 434 + .../agesa/f15tn/Include/OptionCpuFeaturesInstall.h | 108 + src/vendorcode/amd/agesa/f15tn/Include/OptionDmi.h | 116 + .../amd/agesa/f15tn/Include/OptionDmiInstall.h | 242 + .../agesa/f15tn/Include/OptionFamily15hInstall.h | 1206 + .../amd/agesa/f15tn/Include/OptionFchInstall.h | 1024 + .../amd/agesa/f15tn/Include/OptionGfxRecovery.h | 108 + .../agesa/f15tn/Include/OptionGfxRecoveryInstall.h | 80 + src/vendorcode/amd/agesa/f15tn/Include/OptionGnb.h | 149 + .../amd/agesa/f15tn/Include/OptionGnbInstall.h | 942 + .../amd/agesa/f15tn/Include/OptionHtInstall.h | 365 + .../amd/agesa/f15tn/Include/OptionHtcInstall.h | 113 + .../amd/agesa/f15tn/Include/OptionHwC1eInstall.h | 107 + .../amd/agesa/f15tn/Include/OptionIdsInstall.h | 666 + .../agesa/f15tn/Include/OptionIoCstateInstall.h | 171 + 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src/vendorcode/amd/agesa/f15tn/Proc/HT/htGraph.h | 170 + .../amd/agesa/f15tn/Proc/HT/htInterface.c | 289 + .../amd/agesa/f15tn/Proc/HT/htInterface.h | 516 + .../amd/agesa/f15tn/Proc/HT/htInterfaceCoherent.c | 290 + .../amd/agesa/f15tn/Proc/HT/htInterfaceCoherent.h | 141 + .../amd/agesa/f15tn/Proc/HT/htInterfaceGeneral.c | 565 + .../amd/agesa/f15tn/Proc/HT/htInterfaceGeneral.h | 188 + .../agesa/f15tn/Proc/HT/htInterfaceNonCoherent.c | 420 + .../agesa/f15tn/Proc/HT/htInterfaceNonCoherent.h | 164 + src/vendorcode/amd/agesa/f15tn/Proc/HT/htMain.c | 605 + src/vendorcode/amd/agesa/f15tn/Proc/HT/htNb.c | 274 + src/vendorcode/amd/agesa/f15tn/Proc/HT/htNb.h | 1160 + .../amd/agesa/f15tn/Proc/HT/htNbCommonHardware.h | 149 + src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.c | 696 + src/vendorcode/amd/agesa/f15tn/Proc/HT/htNotify.h | 324 + src/vendorcode/amd/agesa/f15tn/Proc/HT/htPage.h | 91 + .../amd/agesa/f15tn/Proc/HT/htTopologies.h | 98 + .../amd/agesa/f15tn/Proc/IDS/Control/IdsCtrl.c | 855 + .../amd/agesa/f15tn/Proc/IDS/Control/IdsLib32.asm | 362 + .../amd/agesa/f15tn/Proc/IDS/Control/IdsLib64.asm | 369 + .../amd/agesa/f15tn/Proc/IDS/Control/IdsNvToCmos.c | 442 + .../amd/agesa/f15tn/Proc/IDS/Control/IdsNvToCmos.h | 110 + .../amd/agesa/f15tn/Proc/IDS/Debug/IdsDebug.c | 229 + .../amd/agesa/f15tn/Proc/IDS/Debug/IdsDebugPrint.c | 678 + .../amd/agesa/f15tn/Proc/IDS/Debug/IdsDebugPrint.h | 105 + .../amd/agesa/f15tn/Proc/IDS/Debug/IdsDpHdtout.c | 778 + .../amd/agesa/f15tn/Proc/IDS/Debug/IdsDpHdtout.h | 146 + .../agesa/f15tn/Proc/IDS/Debug/IdsDpRedirectIo.c | 172 + .../amd/agesa/f15tn/Proc/IDS/Debug/IdsDpSerial.c | 211 + .../amd/agesa/f15tn/Proc/IDS/Debug/IdsIdtTable.c | 329 + .../f15tn/Proc/IDS/Family/0x15/IdsF15AllService.c | 79 + .../f15tn/Proc/IDS/Family/0x15/IdsF15AllService.h | 76 + .../Proc/IDS/Family/0x15/TN/IdsF15TnAllService.c | 420 + .../Proc/IDS/Family/0x15/TN/IdsF15TnAllService.h | 76 + .../f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnNvDef.h | 311 + src/vendorcode/amd/agesa/f15tn/Proc/IDS/IdsLib.h | 444 + src/vendorcode/amd/agesa/f15tn/Proc/IDS/IdsPage.h | 84 + .../amd/agesa/f15tn/Proc/IDS/Library/IdsLib.c | 959 + .../amd/agesa/f15tn/Proc/IDS/Library/IdsRegAcc.c | 316 + .../amd/agesa/f15tn/Proc/IDS/Library/IdsRegAcc.h | 180 + .../amd/agesa/f15tn/Proc/IDS/OptionsIds.h | 113 + .../amd/agesa/f15tn/Proc/IDS/Perf/IdsPerf.c | 248 + src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ardk/ma.c | 172 + .../amd/agesa/f15tn/Proc/Mem/Feat/CHINTLV/mfchi.c | 238 + .../amd/agesa/f15tn/Proc/Mem/Feat/CHINTLV/mfchi.h | 107 + .../amd/agesa/f15tn/Proc/Mem/Feat/CRAT/mfCrat.c | 412 + .../amd/agesa/f15tn/Proc/Mem/Feat/CRAT/mfCrat.h | 115 + .../amd/agesa/f15tn/Proc/Mem/Feat/CSINTLV/mfcsi.c | 382 + .../amd/agesa/f15tn/Proc/Mem/Feat/CSINTLV/mfcsi.h | 107 + .../amd/agesa/f15tn/Proc/Mem/Feat/DMI/mfDMI.c | 677 + .../amd/agesa/f15tn/Proc/Mem/Feat/ECC/mfecc.c | 316 + .../amd/agesa/f15tn/Proc/Mem/Feat/ECC/mfecc.h | 107 + .../amd/agesa/f15tn/Proc/Mem/Feat/ECC/mfemp.c | 204 + .../f15tn/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c | 233 + .../f15tn/Proc/Mem/Feat/IDENDIMM/mfidendimm.c | 575 + .../f15tn/Proc/Mem/Feat/IDENDIMM/mfidendimm.h | 134 + .../agesa/f15tn/Proc/Mem/Feat/INTLVRN/mfintlvrn.c | 190 + .../agesa/f15tn/Proc/Mem/Feat/INTLVRN/mfintlvrn.h | 107 + .../agesa/f15tn/Proc/Mem/Feat/LVDDR3/mflvddr3.c | 199 + .../agesa/f15tn/Proc/Mem/Feat/LVDDR3/mflvddr3.h | 105 + .../agesa/f15tn/Proc/Mem/Feat/MEMCLR/mfmemclr.c | 178 + .../f15tn/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c | 199 + .../f15tn/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h | 104 + .../Proc/Mem/Feat/PARTRN/mfParallelTraining.c | 315 + .../Proc/Mem/Feat/PARTRN/mfStandardTraining.c | 112 + .../amd/agesa/f15tn/Proc/Mem/Feat/S3/mfs3.c | 745 + .../amd/agesa/f15tn/Proc/Mem/Feat/TABLE/mftds.c | 362 + .../amd/agesa/f15tn/Proc/Mem/Main/TN/mmflowtn.c | 389 + .../amd/agesa/f15tn/Proc/Mem/Main/mdef.c | 173 + .../amd/agesa/f15tn/Proc/Mem/Main/merrhdl.c | 214 + .../amd/agesa/f15tn/Proc/Mem/Main/minit.c | 164 + src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mm.c | 279 + .../agesa/f15tn/Proc/Mem/Main/mmConditionalPso.c | 722 + .../amd/agesa/f15tn/Proc/Mem/Main/mmEcc.c | 162 + .../amd/agesa/f15tn/Proc/Mem/Main/mmExcludeDimm.c | 271 + .../amd/agesa/f15tn/Proc/Mem/Main/mmLvDdr3.c | 331 + .../amd/agesa/f15tn/Proc/Mem/Main/mmMemClr.c | 145 + .../amd/agesa/f15tn/Proc/Mem/Main/mmMemRestore.c | 698 + .../agesa/f15tn/Proc/Mem/Main/mmNodeInterleave.c | 173 + .../amd/agesa/f15tn/Proc/Mem/Main/mmOnlineSpare.c | 192 + .../agesa/f15tn/Proc/Mem/Main/mmParallelTraining.c | 315 + .../agesa/f15tn/Proc/Mem/Main/mmStandardTraining.c | 159 + .../amd/agesa/f15tn/Proc/Mem/Main/mmUmaAlloc.c | 272 + .../amd/agesa/f15tn/Proc/Mem/Main/mmflow.c | 421 + .../amd/agesa/f15tn/Proc/Mem/Main/mmlvddr3.h | 107 + .../amd/agesa/f15tn/Proc/Mem/Main/mu.asm | 523 + src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mu.c | 250 + src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/muc.c | 787 + .../amd/agesa/f15tn/Proc/Mem/NB/TN/mnS3tn.h | 111 + .../amd/agesa/f15tn/Proc/Mem/NB/TN/mndcttn.c | 906 + .../amd/agesa/f15tn/Proc/Mem/NB/TN/mnflowtn.c | 156 + .../amd/agesa/f15tn/Proc/Mem/NB/TN/mnidendimmtn.c | 172 + .../amd/agesa/f15tn/Proc/Mem/NB/TN/mnmcttn.c | 562 + .../amd/agesa/f15tn/Proc/Mem/NB/TN/mnottn.c | 348 + .../amd/agesa/f15tn/Proc/Mem/NB/TN/mnphytn.c | 742 + .../amd/agesa/f15tn/Proc/Mem/NB/TN/mnregtn.c | 856 + .../amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c | 1498 + .../amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c | 618 + .../amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.h | 341 + src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mn.c | 530 + src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnS3.c | 1493 + src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mndct.c | 3613 ++ .../amd/agesa/f15tn/Proc/Mem/NB/mnfeat.c | 1418 + .../amd/agesa/f15tn/Proc/Mem/NB/mnflow.c | 359 + src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnmct.c | 1313 + src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnphy.c | 2059 + src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/mnreg.c | 608 + .../amd/agesa/f15tn/Proc/Mem/NB/mntrain3.c | 269 + .../amd/agesa/f15tn/Proc/Mem/Ps/TN/FM2/mpUtnfm2.c | 153 + .../amd/agesa/f15tn/Proc/Mem/Ps/TN/FP2/mpStnfp2.c | 196 + .../amd/agesa/f15tn/Proc/Mem/Ps/TN/FS1/mpStnfs1.c | 142 + .../amd/agesa/f15tn/Proc/Mem/Ps/TN/mpStn3.c | 203 + .../amd/agesa/f15tn/Proc/Mem/Ps/TN/mpUtn3.c | 205 + .../amd/agesa/f15tn/Proc/Mem/Ps/TN/mptn3.c | 186 + src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mp.c | 1246 + .../amd/agesa/f15tn/Proc/Mem/Ps/mplribt.c | 226 + .../amd/agesa/f15tn/Proc/Mem/Ps/mplrnlr.c | 137 + .../amd/agesa/f15tn/Proc/Mem/Ps/mplrnpr.c | 137 + .../amd/agesa/f15tn/Proc/Mem/Ps/mpmaxfreq.c | 342 + src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpmr0.c | 222 + .../amd/agesa/f15tn/Proc/Mem/Ps/mpodtpat.c | 243 + .../amd/agesa/f15tn/Proc/Mem/Ps/mprc10opspd.c | 204 + .../amd/agesa/f15tn/Proc/Mem/Ps/mprc2ibt.c | 256 + src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mprtt.c | 307 + src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mpsao.c | 266 + .../amd/agesa/f15tn/Proc/Mem/Ps/mpseeds.c | 243 + .../amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mt3.c | 262 + .../amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mt3.h | 161 + .../amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtlrdimm3.c | 1474 + .../amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtlrdimm3.h | 159 + .../amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtot3.c | 194 + .../amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtot3.h | 117 + .../amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtrci3.c | 345 + .../amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtrci3.h | 114 + .../amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtsdi3.c | 530 + .../amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtsdi3.h | 123 + .../amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.c | 1221 + .../amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h | 203 + .../amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mttecc3.c | 190 + .../amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mttwl3.c | 742 + src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mt.c | 289 + .../amd/agesa/f15tn/Proc/Mem/Tech/mthdi.c | 151 + .../amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c | 933 + .../amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.h | 144 + .../amd/agesa/f15tn/Proc/Mem/Tech/mttdimbt.c | 1510 + .../amd/agesa/f15tn/Proc/Mem/Tech/mttecc.c | 252 + .../amd/agesa/f15tn/Proc/Mem/Tech/mtthrc.c | 337 + .../agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c | 649 + .../amd/agesa/f15tn/Proc/Mem/Tech/mttml.c | 285 + .../amd/agesa/f15tn/Proc/Mem/Tech/mttoptsrc.c | 452 + .../amd/agesa/f15tn/Proc/Mem/Tech/mttsrc.c | 372 + src/vendorcode/amd/agesa/f15tn/Proc/Mem/ma.h | 343 + src/vendorcode/amd/agesa/f15tn/Proc/Mem/memPage.h | 84 + src/vendorcode/amd/agesa/f15tn/Proc/Mem/merrhdl.h | 130 + .../amd/agesa/f15tn/Proc/Mem/mfParallelTraining.h | 140 + .../amd/agesa/f15tn/Proc/Mem/mfStandardTraining.h | 108 + src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfmemclr.h | 110 + src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfs3.h | 398 + src/vendorcode/amd/agesa/f15tn/Proc/Mem/mftds.h | 107 + src/vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h | 1378 + src/vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h | 1820 + src/vendorcode/amd/agesa/f15tn/Proc/Mem/mnreg.h | 356 + src/vendorcode/amd/agesa/f15tn/Proc/Mem/mp.h | 635 + src/vendorcode/amd/agesa/f15tn/Proc/Mem/mport.h | 97 + src/vendorcode/amd/agesa/f15tn/Proc/Mem/mt.h | 513 + src/vendorcode/amd/agesa/f15tn/Proc/Mem/mu.h | 290 + src/vendorcode/amd/agesa/f15tn/cpcar.inc | 1556 + src/vendorcode/amd/agesa/f15tn/cpcarmac.inc | 483 + src/vendorcode/amd/agesa/f15tn/gcccar.inc | 1936 + 750 files changed, 313689 insertions(+), 0 deletions(-)
diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc index b0e5ddf..824595d 100644 --- a/src/vendorcode/amd/agesa/Makefile.inc +++ b/src/vendorcode/amd/agesa/Makefile.inc @@ -2,3 +2,4 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += f10 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += f12 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += f14 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += f15 +subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += f15tn diff --git a/src/vendorcode/amd/agesa/f15tn/AGESA.h b/src/vendorcode/amd/agesa/f15tn/AGESA.h new file mode 100644 index 0000000..a9e7967 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/AGESA.h @@ -0,0 +1,3718 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Agesa structures and definitions + * + * Contains AMD AGESA core interface + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Include + * @e $Revision: 64574 $ @e $Date: 2012-01-25 01:01:51 -0600 (Wed, 25 Jan 2012) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + + +#ifndef _AGESA_H_ +#define _AGESA_H_ + +#include "Porting.h" +#include "AMD.h" + +// +// +// AGESA Types and Definitions +// +// + +// AGESA BASIC CALLOUTS +#define AGESA_MEM_RELEASE 0x00028000ul + +// AGESA ADVANCED CALLOUTS, Processor +#define AGESA_CHECK_UMA 0x00028100ul +#define AGESA_DO_RESET 0x00028101ul +#define AGESA_ALLOCATE_BUFFER 0x00028102ul +#define AGESA_DEALLOCATE_BUFFER 0x00028103ul +#define AGESA_LOCATE_BUFFER 0x00028104ul +#define AGESA_RUNFUNC_ONAP 0x00028105ul + +// AGESA ADVANCED CALLOUTS, HyperTransport + +// AGESA ADVANCED CALLOUTS, Memory +#define AGESA_READ_SPD 0x00028140ul +#define AGESA_HOOKBEFORE_DRAM_INIT 0x00028141ul +#define AGESA_HOOKBEFORE_DQS_TRAINING 0x00028142ul +#define AGESA_READ_SPD_RECOVERY 0x00028143ul +#define AGESA_HOOKBEFORE_EXIT_SELF_REF 0x00028144ul +#define AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY 0x00028145ul + +// AGESA IDS CALLOUTS +#define AGESA_GET_IDS_INIT_DATA 0x00028200ul + +// AGESA GNB CALLOUTS +#define AGESA_GNB_PCIE_SLOT_RESET 0x00028301ul +#define AGESA_GNB_GFX_GET_VBIOS_IMAGE 0x00028302ul + +// AGESA FCH CALLOUTS +#define AGESA_FCH_OEM_CALLOUT 0x00028401ul + +//------------------------------------------------------------------------ +// +// HyperTransport Interface + + + +//----------------------------------------------------------------------------- +// HT DEFINITIONS AND MACROS +// +//----------------------------------------------------------------------------- + + +// Width equates for call backs +#define HT_WIDTH_8_BITS 8 ///< Specifies 8 bit, or up to 8 bit widths. +#define HT_WIDTH_16_BITS 16 ///< Specifies 16 bit, or up to 16 bit widths. +#define HT_WIDTH_4_BITS 4 +#define HT_WIDTH_2_BITS 2 +#define HT_WIDTH_NO_LIMIT HT_WIDTH_16_BITS + +// Frequency Limit equates for call backs which take a frequency supported mask. +#define HT_FREQUENCY_LIMIT_200M 1 ///< Specifies a limit of no more than 200 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_400M 7 ///< Specifies a limit of no more than 400 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_600M 0x1F ///< Specifies a limit of no more than 600 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_800M 0x3F ///< Specifies a limit of no more than 800 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_1000M 0x7F ///< Specifies a limit of no more than 1000 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_HT1_ONLY 0x7F ///< Specifies a limit of no more than 1000 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_1200M 0xFF ///< Specifies a limit of no more than 1200 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_1400M 0x1FF ///< Specifies a limit of no more than 1400 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_1600M 0x3FF ///< Specifies a limit of no more than 1600 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_1800M 0x7FF ///< Specifies a limit of no more than 1800 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_2000M 0xFFF ///< Specifies a limit of no more than 2000 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_2200M 0x1FFF ///< Specifies a limit of no more than 2200 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_2400M 0x3FFF ///< Specifies a limit of no more than 2400 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_2600M 0x7FFF ///< Specifies a limit of no more than 2600 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_2800M 0x27FFFul ///< Specifies a limit of no more than 2800 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_3000M 0x67FFFul ///< Specifies a limit of no more than 3000 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_3200M 0xE7FFFul ///< Specifies a limit of no more than 3200 MHz HT frequency. +#define HT_FREQUENCY_LIMIT_3600M 0x1E7FFFul +#define HT_FREQUENCY_LIMIT_MAX HT_FREQUENCY_LIMIT_3600M +#define HT_FREQUENCY_NO_LIMIT 0xFFFFFFFFul ///< Specifies a no limit of HT frequency. + +// Unit ID Clumping special values +#define HT_CLUMPING_DISABLE 0x00000000ul +#define HT_CLUMPING_NO_LIMIT 0xFFFFFFFFul + +#define HT_LIST_TERMINAL 0xFF ///< End of list. +#define HT_LIST_MATCH_ANY 0xFE ///< Match Any value, used for Sockets, Links, IO Chain Depth. +#define HT_LIST_MATCH_INTERNAL_LINK 0xFD ///< Match all of the internal links. + +// Event Notify definitions + +// Event definitions. + +// Coherent subfunction events +#define HT_EVENT_COH_EVENTS 0x10001000ul +#define HT_EVENT_COH_NO_TOPOLOGY 0x10011000ul ///< See ::HT_EVENT_DATA_COH_NO_TOPOLOGY. +#define HT_EVENT_COH_OBSOLETE000 0x10021000ul // No longer used. +#define HT_EVENT_COH_PROCESSOR_TYPE_MIX 0x10031000ul ///< See ::HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX. +#define HT_EVENT_COH_NODE_DISCOVERED 0x10041000ul ///< See ::HT_EVENT_COH_NODE_DISCOVERED. +#define HT_EVENT_COH_MPCAP_MISMATCH 0x10051000ul ///< See ::HT_EVENT_COH_MPCAP_MISMATCH. + +// Non-coherent subfunction events +#define HT_EVENT_NCOH_EVENTS 0x10002000ul +#define HT_EVENT_NCOH_BUID_EXCEED 0x10012000ul ///< See ::HT_EVENT_DATA_NCOH_BUID_EXCEED +#define HT_EVENT_NCOH_OBSOLETE000 0x10022000ul // No longer used. +#define HT_EVENT_NCOH_BUS_MAX_EXCEED 0x10032000ul ///< See ::HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED. +#define HT_EVENT_NCOH_CFG_MAP_EXCEED 0x10042000ul ///< See ::HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED. +#define HT_EVENT_NCOH_DEVICE_FAILED 0x10052000ul ///< See ::HT_EVENT_DATA_NCOH_DEVICE_FAILED +#define HT_EVENT_NCOH_AUTO_DEPTH 0x10062000ul ///< See ::HT_EVENT_NCOH_AUTO_DEPTH + +// Optimization subfunction events +#define HT_EVENT_OPT_EVENTS 0x10003000ul +#define HT_EVENT_OPT_REQUIRED_CAP_RETRY 0x10013000ul ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP. +#define HT_EVENT_OPT_REQUIRED_CAP_GEN3 0x10023000ul ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP. +#define HT_EVENT_OPT_UNUSED_LINKS 0x10033000ul ///< See ::HT_EVENT_DATA_OPT_UNUSED_LINKS. +#define HT_EVENT_OPT_LINK_PAIR_EXCEED 0x10043000ul ///< See ::HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED. + +// HW Fault events +#define HT_EVENT_HW_EVENTS 0x10004000ul +#define HT_EVENT_HW_SYNCFLOOD 0x10014000ul ///< See ::HT_EVENT_DATA_HW_SYNCFLOOD. +#define HT_EVENT_HW_HTCRC 0x10024000ul ///< See ::HT_EVENT_DATA_HW_HT_CRC. + +// The Recovery HT component uses 0x10005000 for events. +// For consistency, we avoid that range here. + +#define HT_MAX_NC_BUIDS 32 +//---------------------------------------------------------------------------- +// HT TYPEDEFS, STRUCTURES, ENUMS +// +//---------------------------------------------------------------------------- + +/// Specify the state redundant links are to be left in after match. +/// +/// After matching a link for IGNORE_LINK or SKIP_REGANG, the link may be left alone, +/// or powered off. + +typedef enum { + MATCHED, ///< The link matches the requested customization. + ///< When used with IGNORE_LINK, + ///< this will generally require other software to initialize the link. + ///< When used with SKIP_REGANG, + ///< the two unganged links will be available for distribution. + + POWERED_OFF, ///< Power the link off. Support may vary based on processor model. + ///< Power Off is only supported for coherent links. + ///< Link power off may occur at a warm reset rather than immediately. + ///< When used with SKIP_REGANG, the paired sublink is powered off, not the matching link. + + UNMATCHED, ///< The link should be processed according to normal defaults. + ///< Effectively, the link does not match the requested customization. + ///< This can be used to exclude links from a following match any. + + MaxFinalLinkState ///< Not a final link state, use for limit checking. +} FINAL_LINK_STATE; + +/// Swap a device from its current id to a new one. + +typedef struct { + IN UINT8 FromId; ///< The device responding to FromId, + IN UINT8 ToId; ///< will be moved to ToId. +} BUID_SWAP_ITEM; + + +/// Each Non-coherent chain may have a list of device swaps. After performing the swaps, +/// the final in order list of device ids is provided. (There can be more swaps than devices.) +/// The unused entries in both are filled with 0xFF. + +typedef struct { + IN BUID_SWAP_ITEM Swaps[HT_MAX_NC_BUIDS]; ///< The BUID Swaps to perform + IN UINT8 FinalIds[HT_MAX_NC_BUIDS]; ///< The ordered final BUIDs, resulting from the swaps +} BUID_SWAP_LIST; + + +/// Control Manual Initialization of Non-Coherent Chains +/// +/// This interface is checked every time a non-coherent chain is +/// processed. BUID assignment may be controlled explicitly on a +/// non-coherent chain. Provide a swap list. Swaps controls the +/// BUID assignment and FinalIds provides the device to device +/// Linking. Device orientation can be detected automatically, or +/// explicitly. See interface documentation for more details. +/// +/// If a manual swap list is not supplied, +/// automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially +/// based on each device's unit count. + +typedef struct { + // Match fields + IN UINT8 Socket; ///< The Socket on which this chain is located + IN UINT8 Link; ///< The Link on the host for this chain + // Override fields + IN BUID_SWAP_LIST SwapList; ///< The swap list +} MANUAL_BUID_SWAP_LIST; + + +/// Override options for DEVICE_CAP_OVERRIDE. +/// +/// Specify which override actions should be performed. For Checks, 1 means to check the item +/// and 0 means to skip the check. For the override options, 1 means to apply the override and +/// 0 means to ignore the override. + +typedef struct { + IN UINT32 IsCheckDevVenId:1; ///< Check Match on Device/Vendor id + IN UINT32 IsCheckRevision:1; ///< Check Match on device Revision + IN UINT32 IsOverrideWidthIn:1; ///< Override Width In + IN UINT32 IsOverrideWidthOut:1; ///< Override Width Out + IN UINT32 IsOverrideFreq:1; ///< Override Frequency + IN UINT32 IsOverrideClumping:1; ///< Override Clumping + IN UINT32 IsDoCallout:1; ///< Make the optional callout +} DEVICE_CAP_OVERRIDE_OPTIONS; + +/// Override capabilities of a device. +/// +/// This interface is checked once for every Link on every IO device. +/// Provide the width and frequency capability if needed for this device. +/// This is used along with device capabilities, the limit interfaces, and northbridge +/// limits to compute the default settings. The components of the device's PCI config +/// address are provided, so its settings can be consulted if need be. +/// The optional callout is a catch all. + +typedef struct { + // Match fields + IN UINT8 HostSocket; ///< The Socket on which this chain is located. + IN UINT8 HostLink; ///< The Link on the host for this chain. + IN UINT8 Depth; ///< The Depth in the I/O chain from the Host. + IN UINT32 DevVenId; ///< The Device's PCI Vendor + Device ID (offset 0x00). + IN UINT8 Revision; ///< The Device's PCI Revision field (offset 0x08). + IN UINT8 Link; ///< The Device's Link number (0 or 1). + IN DEVICE_CAP_OVERRIDE_OPTIONS Options; ///< The options for this device override. + // Override fields + IN UINT8 LinkWidthIn; ///< modify to change the Link Width In. + IN UINT8 LinkWidthOut; ///< modify to change the Link Width Out. + IN UINT32 FreqCap; ///< modify to change the Link's frequency capability. + IN UINT32 Clumping; ///< modify to change Unit ID clumping support. + IN CALLOUT_ENTRY Callout; ///< optional call for really complex cases, or NULL. +} DEVICE_CAP_OVERRIDE; + +/// Callout param struct for override capabilities of a device. +/// +/// If the optional callout is implemented this param struct is passed to it. + +typedef struct { + IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + // Match fields + IN UINT8 HostSocket; ///< The Socket on which this chain is located. + IN UINT8 HostLink; ///< The Link on the host for this chain. + IN UINT8 Depth; ///< The Depth in the I/O chain from the Host. + IN UINT32 DevVenId; ///< The Device's PCI Vendor + Device ID (offset 0x00). + IN UINT8 Revision; ///< The Device's PCI Revision field (offset 0x08). + IN UINT8 Link; ///< The Device's Link number (0 or 1). + IN PCI_ADDR PciAddress; ///< The Device's PCI Address. + // Override fields + OUT UINT8 *LinkWidthIn; ///< modify to change the Link Width In. + OUT UINT8 *LinkWidthOut; ///< modify to change the Link Width Out. + OUT UINT32 *FreqCap; ///< modify to change the Link's frequency capability. + OUT UINT32 *Clumping; ///< modify to change Unit ID clumping support. +} DEVICE_CAP_CALLOUT_PARAMS; + +/// Limits for CPU to CPU Links. +/// +/// For each coherent connection this interface is checked once. +/// Provide the frequency and width if needed for this Link (usually based on board +/// restriction). This is used with CPU device capabilities and northbridge limits +/// to compute the default settings. + +typedef struct { + // Match fields + IN UINT8 SocketA; ///< One Socket on which this Link is located + IN UINT8 LinkA; ///< The Link on this Node + IN UINT8 SocketB; ///< The other Socket on which this Link is located + IN UINT8 LinkB; ///< The Link on that Node + // Limit fields + IN UINT8 ABLinkWidthLimit; ///< modify to change the Link Width A->B + IN UINT8 BALinkWidthLimit; ///< modify to change the Link Width B-<A + IN UINT32 PcbFreqCap; ///< modify to change the Link's frequency capability +} CPU_TO_CPU_PCB_LIMITS; + +/// Get limits for non-coherent Links. +/// +/// For each non-coherent connection this interface is checked once. +/// Provide the frequency and width if needed for this Link (usually based on board +/// restriction). This is used with device capabilities, device overrides, and northbridge limits +/// to compute the default settings. +/// +typedef struct { + // Match fields + IN UINT8 HostSocket; ///< The Socket on which this Link is located + IN UINT8 HostLink; ///< The Link about to be initialized + IN UINT8 Depth; ///< The Depth in the I/O chain from the Host + // Limit fields + IN UINT8 DownstreamLinkWidthLimit; ///< modify to change the Link Width going away from processor + IN UINT8 UpstreamLinkWidthLimit; ///< modify to change the Link Width moving toward processor + IN UINT32 PcbFreqCap; ///< modify to change the Link's frequency capability +} IO_PCB_LIMITS; + +/// Manually control bus number assignment. +/// +/// This interface is checked every time a non-coherent chain is processed. +/// If a system can not use the auto Bus numbering feature for non-coherent chain bus +/// assignments, this interface can provide explicit control. For each chain, provide +/// the bus number range to use. + +typedef struct { + // Match fields + IN UINT8 Socket; ///< The Socket on which this chain is located + IN UINT8 Link; ///< The Link on the host for this chain + // Override fields + IN UINT8 SecBus; ///< Secondary Bus number for this non-coherent chain + IN UINT8 SubBus; ///< Subordinate Bus number +} OVERRIDE_BUS_NUMBERS; + + +/// Ignore a Link. +/// +/// This interface is checked every time a coherent Link is found and then every +/// time a non-coherent Link from a CPU is found. +/// Any coherent or non-coherent Link from a CPU can be ignored and not used +/// for discovery or initialization. Useful for connection based systems. +/// (Note: not checked for IO device to IO Device Links.) +/// (Note: not usable for internal links (MCM processors).) + +typedef struct { + // Match fields + IN UINT8 Socket; ///< The Socket on which this Link is located + IN UINT8 Link; ///< The Link about to be initialized + // Customization fields + IN FINAL_LINK_STATE LinkState; ///< The link may be left unitialized, or powered off. +} IGNORE_LINK; + + +/// Skip reganging of subLinks. +/// +/// This interface is checked whenever two subLinks are both connected to the same CPUs. +/// Normally, unganged sublinks between the same two CPUs are reganged. +/// Provide a matching structure to leave the Links unganged. + +typedef struct { + // Match fields + IN UINT8 SocketA; ///< One Socket on which this Link is located + IN UINT8 LinkA; ///< The Link on this Node + IN UINT8 SocketB; ///< The other Socket on which this Link is located + IN UINT8 LinkB; ///< The Link on that Node + // Customization fields + IN FINAL_LINK_STATE LinkState; ///< The paired sublink may be active, or powered off. +} SKIP_REGANG; + +/// The System Socket layout, which sockets are physically connected. +/// +/// The hardware method for Socket naming is preferred. Use this software method only +/// if required. + +typedef struct { + IN UINT8 CurrentSocket; ///< The socket from which this connection originates. + IN UINT8 CurrentLink; ///< The Link from the source socket connects to another socket. + IN UINT8 TargetSocket; ///< The target socket which is connected on that link. +} SYSTEM_PHYSICAL_SOCKET_MAP; + +//---------------------------------------------------------------------------- +/// +/// This is the input structure for AmdHtInitialize. +/// +typedef struct { + // Basic level customization + IN UINT8 AutoBusStart; ///< For automatic bus number assignment, starting bus number - usually zero. + ///< @BldCfgItem{BLDCFG_STARTING_BUSNUM} + IN UINT8 AutoBusMax; ///< For automatic bus number assignment, do not assign above max. + ///< @BldCfgItem{BLDCFG_MAXIMUM_BUSNUM} + IN UINT8 AutoBusIncrement; ///< For automatic bus number assignment, each chain gets this many busses. + ///< @BldCfgItem{BLDCFG_ALLOCATED_BUSNUM} + + // Advanced Level Customization + IN MANUAL_BUID_SWAP_LIST *ManualBuidSwapList; ///< Provide Manual Swap List, if any. + ///< @BldCfgItem{BLDCFG_BUID_SWAP_LIST} + IN DEVICE_CAP_OVERRIDE *DeviceCapOverrideList; ///< Provide Device Overrides, if any. + ///< @BldCfgItem{BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST} + IN CPU_TO_CPU_PCB_LIMITS *CpuToCpuPcbLimitsList; ///< Provide CPU PCB Limits, if any. + ///< @BldCfgItem{BLDCFG_HTFABRIC_LIMITS_LIST}. + ///< @n @e Examples: See @ref FrequencyLimitExamples "Frequency Limit Examples". + IN IO_PCB_LIMITS *IoPcbLimitsList; ///< Provide IO PCB Limits, if any. + ///< @BldCfgItem{BLDCFG_HTCHAIN_LIMITS_LIST}. + ///< @n @e Examples: See @ref FrequencyLimitExamples "Frequency Limit Examples". + IN OVERRIDE_BUS_NUMBERS *OverrideBusNumbersList; ///< Provide manual Bus Number assignment, if any. + ///< Use either auto bus numbering or override bus + ///< numbers, not both. + ///< @BldCfgItem{BLDCFG_BUS_NUMBERS_LIST} + + IN IGNORE_LINK *IgnoreLinkList; ///< Provide links to ignore, if any. + ///< @BldCfgItem{BLDCFG_IGNORE_LINK_LIST} + IN SKIP_REGANG *SkipRegangList; ///< Provide links to remain unganged, if any. + ///< @BldCfgItem{BLDCFG_LINK_SKIP_REGANG_LIST} + ///< @n @e Examples: See @ref PerfPerWattHt "Performance-per-watt Optimization". + + // Expert Level Customization + IN UINT8 **Topolist; ///< Use this topology list in addition to the built in, if not NULL. + ///< @BldCfgItem{BLDCFG_ADDITIONAL_TOPOLOGIES_LIST} + IN SYSTEM_PHYSICAL_SOCKET_MAP *SystemPhysicalSocketMap; + ///< The hardware socket naming method is preferred, + ///< If it can't be used, this provides a software method. + ///< @BldCfgItem{BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP} +} AMD_HT_INTERFACE; + +//----------------------------------------------------------------------------- +// +// HT Recovery Interface +// + + +/*----------------------------------------------------------------------------- + * HT Recovery DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +// BBHT subfunction events +#define HT_EVENT_BB_EVENTS 0x10005000ul +#define HT_EVENT_BB_BUID_EXCEED 0x10015000ul +#define HT_EVENT_BB_DEVICE_FAILED 0x10055000ul +#define HT_EVENT_BB_AUTO_DEPTH 0x10065000ul + +/*---------------------------------------------------------------------------- + * HT Recovery TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + + +/// The Interface structure to Recovery HT. + +typedef struct { + IN MANUAL_BUID_SWAP_LIST *ManualBuidSwapList; ///< Option to manually control SB link init + ///< @BldCfgItem{BLDCFG_BUID_SWAP_LIST} + OUT UINT32 Depth; ///< If auto init was used this is set to the depth of the chain, + ///< else, for manual init unmodified. +} AMD_HT_RESET_INTERFACE; + + +//----------------------------------------------------------------------------- +// FCH DEFINITIONS AND MACROS +// +//----------------------------------------------------------------------------- + +/// Configuration values for SdConfig +typedef enum { + SdDisable = 0, ///< Disabled + SdAmda, ///< AMDA, set 24,18,16, default + SdDma, ///< DMA clear 24, 16, set 18 + SdPio ///< PIO clear 24,18,16 +} SD_MODE; + +/// Configuration values for SdClockControl +typedef enum { + Sd50MhzTraceCableLengthWithinSixInches = 4, ///< 50Mhz, default + Sd40MhzTraceCableLengthSix2ElevenInches = 6, ///< 40Mhz + Sd25MhzTraceCableLengthEleven2TwentyfourInches = 7, ///< 25Mhz +} SD_CLOCK_CONTROL; + +/// Configuration values for AzaliaController +typedef enum { + hdaconf0 = 0, ///< Auto - Detect Azalia controller automatically + hdaconf1 , ///< Diable - Disable Azalia controller + hdaconf2 ///< Enable - Enable Azalia controller +} HDA_CONFIG; + +/// Configuration values for IrConfig +typedef enum { + IrDisable = 0, ///< Disable + IrRxTx0 = 1, ///< Rx and Tx0 + IrRxTx1 = 2, ///< Rx and Tx1 + IrRxTx0Tx1 = 3 ///< Rx and both Tx0,Tx1 +} IR_CONFIG; + +/// Configuration values for SataClass +typedef enum { + SataNativeIde = 0, ///< Native IDE mode + SataRaid, ///< RAID mode + SataAhci, ///< AHCI mode + SataLegacyIde, ///< Legacy IDE mode + SataIde2Ahci, ///< IDE->AHCI mode + SataAhci7804, ///< AHCI mode as 7804 ID (AMD driver) + SataIde2Ahci7804 ///< IDE->AHCI mode as 7804 ID (AMD driver) +} SATA_CLASS; + +/// Configuration values for BLDCFG_FCH_GPP_LINK_CONFIG +typedef enum { + PortA4 = 0, ///< 4:0:0:0 + PortA2B2 = 2, ///< 2:2:0:0 + PortA2B1C1 = 3, ///< 2:1:1:0 + PortA1B1C1D1 = 4 ///< 1:1:1:1 +} GPP_LINKMODE; + +/// Configuration values for FchPowerFail +typedef enum { + AlwaysOff = 0, ///< Always power off after power resumes + AlwaysOn = 1, ///< Always power on after power resumes + UsePrevious = 3, ///< Resume to same setting when power fails +} POWER_FAIL; + + +/// Configuration values for SATA Link Speed +typedef enum { + Gen1 = 1, ///< SATA port GEN1 speed + Gen2 = 2, ///< SATA port GEN2 speed + Gen3 = 3, ///< SATA port GEN3 speed +} SATA_SPEED; + + +/// Configuration values for GPIO function +typedef enum { + Function0 = 0, ///< GPIO Function 1 + Function1 = 1, ///< GPIO Function 1 + Function2 = 2, ///< GPIO Function 2 + Function3 = 3, ///< GPIO Function 3 +} GPIO_FUN; + + +/// Configuration values for GPIO_CFG +typedef enum { + OwnedByEc = 1 << 0, ///< This bit can only be written by EC + OwnedByHost = 1 << 1, ///< This bit can only be written by host (BIOS) + Sticky = 1 << 2, ///< If set, [6:3] are sticky + PullUpB = 1 << 3, ///< 0: Pullup enable; 1: Pullup disabled + PullDown = 1 << 4, ///< 0: Pulldown disabled; 1: Pulldown enable + GpioOutEnB = 1 << 5, ///< 0: Output enable; 1: Output disable + GpioOut = 1 << 6, ///< Output state when GpioOutEnB is 0 + GpioIn = 1 << 7, ///< This bit is read only - current pin state +} CFG_BYTE; + +/// FCH GPIO CONTROL +typedef struct { + IN UINT8 GpioPin; ///< Gpio Pin, valid range: 0-67, 128-150, 160-228 + IN GPIO_FUN PinFunction; ///< Multi-function selection + IN CFG_BYTE CfgByte; ///< GPIO Register value +} GPIO_CONTROL; + +/// +/// FCH SCI MAP CONTROL +/// +typedef struct { + IN UINT8 InputPin; ///< Input Pin, valid range 0-63 + IN UINT8 GpeMap; ///< Gpe Map, valid range 0-31 +} SCI_MAP_CONTROL; + +/// +/// FCH SATA PHY CONTROL +/// +typedef struct { + IN BOOLEAN CommonPhy; ///< Common PHY or not + ///< @li <b>FALSE</b> - Only applied to specified port + ///< @li <b>TRUE</b> - Apply to all SATA ports + IN SATA_SPEED Gen; ///< SATA speed + IN UINT8 Port; ///< Port number, valid range: 0-7 + IN UINT32 PhyData; ///< SATA PHY data, valid range: 0-0xFFFFFFFF +} SATA_PHY_CONTROL; + +/// +/// FCH Component Data Structure in InitReset stage +/// +typedef struct { + IN BOOLEAN UmiGen2; ///< Enable Gen2 data rate of UMI + ///< @li <b>FALSE</b> - Disable Gen2 + ///< @li <b>TRUE</b> - Enable Gen2 + + IN BOOLEAN SataEnable; ///< SATA controller function + ///< @li <b>FALSE</b> - SATA controller is disabled + ///< @li <b>TRUE</b> - SATA controller is enabled + + IN BOOLEAN IdeEnable; ///< SATA IDE controller mode enabled/disabled + ///< @li <b>FALSE</b> - IDE controller is disabled + ///< @li <b>TRUE</b> - IDE controller is enabled + + IN BOOLEAN GppEnable; ///< Master switch of GPP function + ///< @li <b>FALSE</b> - GPP disabled + ///< @li <b>TRUE</b> - GPP enabled + + IN BOOLEAN Xhci0Enable; ///< XHCI0 controller function + ///< @li <b>FALSE</b> - XHCI0 controller disabled + ///< @li <b>TRUE</b> - XHCI0 controller enabled + + IN BOOLEAN Xhci1Enable; ///< XHCI1 controller function + ///< @li <b>FALSE</b> - XHCI1 controller disabled + ///< @li <b>TRUE</b> - XHCI1 controller enabled +} FCH_RESET_INTERFACE; + + +/// +/// FCH Component Data Structure from InitEnv stage +/// +typedef struct { + IN SD_MODE SdConfig; ///< Secure Digital (SD) controller mode + IN HDA_CONFIG AzaliaController; ///< Azalia HD Audio Controller + + IN IR_CONFIG IrConfig; ///< Infrared (IR) Configuration + IN BOOLEAN UmiGen2; ///< Enable Gen2 data rate of UMI + ///< @li <b>FALSE</b> - Disable Gen2 + ///< @li <b>TRUE</b> - Enable Gen2 + + IN SATA_CLASS SataClass; ///< SATA controller mode + IN BOOLEAN SataEnable; ///< SATA controller function + ///< @li <b>FALSE</b> - SATA controller is disabled + ///< @li <b>TRUE</b> - SATA controller is enabled + + IN BOOLEAN IdeEnable; ///< SATA IDE controller mode enabled/disabled + ///< @li <b>FALSE</b> - IDE controller is disabled + ///< @li <b>TRUE</b> - IDE controller is enabled + + IN BOOLEAN SataIdeMode; ///< Native mode of SATA IDE controller + ///< @li <b>FALSE</b> - Legacy IDE mode + ///< @li <b>TRUE</b> - Native IDE mode + + IN BOOLEAN Ohci1Enable; ///< OHCI controller #1 Function + ///< @li <b>FALSE</b> - OHCI1 is disabled + ///< @li <b>TRUE</b> - OHCI1 is enabled + + IN BOOLEAN Ohci2Enable; ///< OHCI controller #2 Function + ///< @li <b>FALSE</b> - OHCI2 is disabled + ///< @li <b>TRUE</b> - OHCI2 is enabled + + IN BOOLEAN Ohci3Enable; ///< OHCI controller #3 Function + ///< @li <b>FALSE</b> - OHCI3 is disabled + ///< @li <b>TRUE</b> - OHCI3 is enabled + + IN BOOLEAN Ohci4Enable; ///< OHCI controller #4 Function + ///< @li <b>FALSE</b> - OHCI4 is disabled + ///< @li <b>TRUE</b> - OHCI4 is enabled + + IN BOOLEAN XhciSwitch; ///< XHCI controller Function + ///< @li <b>FALSE</b> - XHCI is disabled + ///< @li <b>TRUE</b> - XHCI is enabled + + IN BOOLEAN GppEnable; ///< Master switch of GPP function + ///< @li <b>FALSE</b> - GPP disabled + ///< @li <b>TRUE</b> - GPP enabled + + IN POWER_FAIL FchPowerFail; ///< FCH power failure option +} FCH_INTERFACE; + + +/*---------------------------------------------------------------------------- + * CPU Feature related info + *---------------------------------------------------------------------------- + */ + +/// Build Configuration values for BLDCFG_PLATFORM_C1E_MODE +typedef enum { + C1eModeDisabled = 0, ///< Disabled + C1eModeAuto = 1, ///< Auto mode enables the best C1e method for the + ///< currently installed processor + C1eModeHardware = 2, ///< Hardware method + C1eModeMsgBased = 3, ///< Message-based method + C1eModeSoftwareDeprecated = 4, ///< Deprecated software SMI method. + ///< Refer to "Addendum\Examples\C1eSMMHandler.asm" for + ///< example host BIOS SMM Handler implementation + C1eModeHardwareSoftwareDeprecated = 5, ///< Hardware or deprecated software SMI method + MaxC1eMode = 6 ///< Not a valid value, used for verifying input +} PLATFORM_C1E_MODES; + +/// Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE +typedef enum { + CStateModeDisabled = 0, ///< Disabled + CStateModeC6 = 1, ///< C6 State + MaxCStateMode = 2 ///< Not a valid value, used for verifying input +} PLATFORM_CSTATE_MODES; + +/// Build Configuration values for BLDCFG_PLATFORM_CPB_MODE +typedef enum { + CpbModeAuto = 0, ///< Auto + CpbModeDisabled = 1, ///< Disabled + MaxCpbMode = 2 ///< Not a valid value, used for verifying input +} PLATFORM_CPB_MODES; + +/// Build Configuration values for BLDCFG_LOW_POWER_PSTATE_FOR_PROCHOT_MODE +typedef enum { + LOW_POWER_PSTATE_FOR_PROCHOT_AUTO = 0, ///< Auto + LOW_POWER_PSTATE_FOR_PROCHOT_DISABLE = 1, ///< Disabled + MAX_LOW_POWER_PSTATE_FOR_PROCHOT_MODE = 2 ///< Not a valid value, used for verifying input +} PLATFORM_LOW_POWER_PSTATE_MODES; + +/*---------------------------------------------------------------------------- + * GNB PCIe configuration info + *---------------------------------------------------------------------------- + */ + +// Event definitions + +#define GNB_EVENT_INVALID_CONFIGURATION 0x20010000ul // User configuration invalid +#define GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION 0x20010001ul // Requested lane allocation for PCIe port can not be supported +#define GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION 0x20010002ul // Requested incorrect PCIe port device address +#define GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION 0x20010003ul // Incorrect parameter in DDI link configuration +#define GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION 0x20010004ul // Invalid with for PCIe port or DDI link +#define GNB_EVENT_INVALID_LANES_CONFIGURATION 0x20010005ul // Lane double subscribe lanes +#define GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION 0x20010006ul // Requested lane allocation for DDI link(s) can not be supported +#define GNB_EVENT_LINK_TRAINING_FAIL 0x20020000ul // PCIe Link training fail +#define GNB_EVENT_BROKEN_LANE_RECOVERY 0x20030000ul // Broken lane workaround applied to recover link training +#define GNB_EVENT_GEN2_SUPPORT_RECOVERY 0x20040000ul // Scale back to GEN1 to recover link training + + +#define DESCRIPTOR_TERMINATE_LIST 0x80000000ull +#define DESCRIPTOR_IGNORE 0x40000000ull + +/// PCIe link initialization +typedef enum { + EndpointDetect = 0, ///< Detect endpoint presence + EndpointNotPresent ///< Endpoint not present (or connected). Used in case there is alternative way to determine + ///< if device present on board or in slot. For example GPIO can be used to determine device presence. +} PCIE_ENDPOINT_STATUS; + + +/// PCIe port misc extended controls +typedef struct { + IN UINT8 LinkComplianceMode :1; ///< Force port into compliance mode (device will not be trained, port output compliance pattern) + IN UINT8 LinkSafeMode :2; /**< Safe mode PCIe capability. (Parameter may limit PCIe speed requested through PCIe_PORT_DATA::LinkSpeedCapability) + * @li @b 0 - port can advertize muximum supported capability + * @li @b 1 - port limit advertized capability and speed to PCIe Gen1 + */ + IN UINT8 SbLink :1; /**< PCIe link type + * @li @b 0 - General purpose port + * @li @b 1 - Port connected to SB + */ + IN UINT8 ClkPmSupport :1; /**< Clock Power Management Support + * @li @b 0 - Clock Power Management not configured + * @li @b 1 - Clock Power Management configured according to PCIe device capability + */ +} PCIe_PORT_MISC_CONTROL; + +/// The IO APIC Interrupt Mapping Info +typedef struct { + IN UINT8 GroupMap; /**< Group mapping for slot or endpoint device (connected to PCIE port) interrupts . + * @li <b>0</b> - IGNORE THIS STRUCTURE AND USE RECOMMENDED SETTINGS + * @li <b>1</b> - mapped to Grp 0 (Interrupts 0..3 of IO APIC redirection table) + * @li <b>2</b> - mapped to Grp 1 (Interrupts 4..7 of IO APIC redirection table) + * @li ... + * @li <b>8</b> - mapped to Grp 7 (Interrupts 28..31 of IO APIC redirection table) + */ + IN UINT8 Swizzle; /**< Swizzle interrupt in the Group. + * @li <b>0</b> - ABCD + * @li <b>1</b> - BCDA + * @li <b>2</b> - CDAB + * @li <b>3</b> - DABC + */ + IN UINT8 BridgeInt; /**< IOAPIC redirection table entry for PCIE bridge interrupt + * @li <b>0</b> - Entry 0 of IO APIC redirection table + * @li <b>1</b> - Entry 1 of IO APIC redirection table + * @li ... + * @li <b>31</b> - Entry 31 of IO APIC redirection table + */ +} APIC_DEVICE_INFO; + +/// PCIe port configuration data +typedef struct { + IN UINT8 PortPresent; ///< Enable PCIe port for initialization. + IN UINT8 ChannelType; /**< Channel type. + * @li @b 0 - "lowLoss", + * @li @b 1 - "highLoss", + * @li @b 2 - "mob0db", + * @li @b 3 - "mob3db", + * @li @b 4 - "extnd6db" + * @li @b 5 - "extnd8db" + */ + IN UINT8 DeviceNumber; /**< PCI Device number for port. + * @li @b 0 - Native port device number + * @li @b N - Port device number (See available configurations @ref F12LaneConfigurations "Family 0x12", @ref F14ONLaneConfigurations "Family 0x14(ON)") + */ + IN UINT8 FunctionNumber; ///< Reserved for future use + IN UINT8 LinkSpeedCapability; /**< PCIe link speed/ + * @li @b 0 - Maximum supported by silicon + * @li @b 1 - Gen1 + * @li @b 2 - Gen2 + * @li @b 3 - Gen3 + */ + IN UINT8 LinkAspm; /**< ASPM control. (see AgesaPcieLinkAspm for additional option to control ASPM) + * @li @b 0 - Disabled + * @li @b 1 - L0s only + * @li @b 2 - L1 only + * @li @b 3 - L0s and L1 + */ + IN UINT8 LinkHotplug; /**< Hotplug control. + * @li @b 0 - Disabled + * @li @b 1 - Basic + * @li @b 2 - Server + * @li @b 3 - Enhanced + */ + IN UINT8 ResetId; /**< Arbitrary number greater than 0 assigned by platform firmware for GPIO + * identification which control reset for given port. + * Each port with unique GPIO should have unique ResetId assigned. + * All ports use same GPIO to control reset should have same ResetId assigned. + * see AgesaPcieSlotResetContol. + */ + IN PCIe_PORT_MISC_CONTROL MiscControls; ///< Misc extended controls + IN APIC_DEVICE_INFO ApicDeviceInfo; ///< IOAPIC device programming info + IN PCIE_ENDPOINT_STATUS EndpointStatus; ///< PCIe endpoint (device connected to PCIe port) status +} PCIe_PORT_DATA; + +/// DDI channel lane mapping +typedef struct { ///< Structure that discribe lane mapping + IN UINT8 Lane0 :2; /**< Lane 0 mapping + * @li @b 0 - Map to lane 0 + * @li @b 1 - Map to lane 1 + * @li @b 2 - Map to lane 2 + * @li @b 2 - Map to lane 3 + */ + IN UINT8 Lane1 :2; ///< Lane 1 mapping (see "Lane 0 mapping") + IN UINT8 Lane2 :2; ///< Lane 2 mapping (see "Lane 0 mapping") + IN UINT8 Lane3 :2; ///< Lane 3 mapping (see "Lane 0 mapping") +} CHANNEL_MAPPING; ///< Lane mapping + +/// Common Channel Mapping +typedef union { + IN UINT8 ChannelMappingValue; ///< Raw lane mapping + IN CHANNEL_MAPPING ChannelMapping; ///< Channel mapping +} CONN_CHANNEL_MAPPING; + +/// DDI Configuration data +typedef struct { + IN UINT8 ConnectorType; /**< Display Connector Type + * @li @b 0 - DP + * @li @b 1 - eDP + * @li @b 2 - Single Link DVI-D + * @li @b 3 - Dual Link DVI-D (see @ref F12DualLinkDviDescription "Family 0x12 Dual Link DVI connector description") + * @li @b 4 - HDMI + * @li @b 5 - Travis DP-to-VGA + * @li @b 6 - Travis DP-to-LVDS + * @li @b 7 - Hudson-2 NutMeg DP-to-VGA + * @li @b 8 - Single Link DVI-I + * @li @b 9 - Native CRT (Family 0x14) + * @li @b 10 - Native LVDS (Family 0x14) + * @li @b 11 - Auto detect LCD panel connector type. VBIOS is able to auto detect the LVDS connector type: native LVDS, eDP or Travis-LVDS + * The auto detection method only support panel with EDID. + */ + IN UINT8 AuxIndex; /**< Indicates which AUX or DDC Line is used + * @li @b 0 - AUX1 + * @li @b 1 - AUX2 + * @li @b 2 - AUX3 + * @li @b 3 - AUX4 + * @li @b 4 - AUX5 + * @li @b 5 - AUX6 + */ + IN UINT8 HdpIndex; /**< Indicates which HDP pin is used + * @li @b 0 - HDP1 + * @li @b 1 - HDP2 + * @li @b 2 - HDP3 + * @li @b 3 - HDP4 + * @li @b 4 - HDP5 + * @li @b 5 - HDP6 + */ + IN CONN_CHANNEL_MAPPING Mapping[2]; /**< Set specific mapping of lanes to connector pins + * @li Mapping[0] define mapping for group of 4 lanes starting at PCIe_ENGINE_DATA.StartLane + * @li Mapping[1] define mapping for group of 4 lanes ending at PCIe_ENGINE_DATA.EndLane (only applicable for Dual DDI link) + * if Mapping[x] set to 0 than default mapping assumed + */ + IN UINT8 LanePnInversionMask; /**< Specifies whether to invert the state of P and N for each lane. Each bit represents a PCIe lane on the DDI port. + * @li 0 - Do not invert (default) + * @li 1 - Invert P and N on this lane + */ + IN UINT8 Flags; /**< Capabilities flags + * @li Flags bit[0] DDI_DATA_FLAGS_DP1_1_ONLY Selects downgrade PHY link to DP1.1 + * @li Flags bit[7:1] Reserved + */ +} PCIe_DDI_DATA; + +/// Engine Configuration +typedef struct { + IN UINT8 EngineType; /**< Engine type + * @li @b 0 - Ignore engine configuration + * @li @b 1 - PCIe port + * @li @b 2 - DDI + */ + IN UINT16 StartLane; /**< Start Lane ID (in reversed configuration StartLane > EndLane) + * See lane description for @ref F12PcieLaneDescription "Family 0x12" + * @ref F14ONPcieLaneDescription "Family 0x14(ON)". + * See lane configurations for @ref F12LaneConfigurations "Family 0x12" + * @ref F14ONLaneConfigurations "Family 0x14(ON)". + */ + IN UINT16 EndLane; /**< End lane ID (in reversed configuration StartLane > EndLane) + * See lane description for @ref F12PcieLaneDescription "Family 0x12", + * @ref F14ONPcieLaneDescription "Family 0x14(ON)". + * See lane configurations for @ref F12LaneConfigurations "Family 0x12" + * @ref F14ONLaneConfigurations "Family 0x14(ON)". + */ + +} PCIe_ENGINE_DATA; + +/// PCIe port descriptor +typedef struct { + IN UINT32 Flags; /**< Descriptor flags + * @li @b Bit31 - last descriptor in complex + */ + IN PCIe_ENGINE_DATA EngineData; ///< Engine data + IN PCIe_PORT_DATA Port; ///< PCIe port specific configuration info +} PCIe_PORT_DESCRIPTOR; + +/// DDI descriptor +typedef struct { + IN UINT32 Flags; /**< Descriptor flags + * @li @b Bit31 - last descriptor in complex + */ + IN PCIe_ENGINE_DATA EngineData; ///< Engine data + IN PCIe_DDI_DATA Ddi; ///< DDI port specific configuration info +} PCIe_DDI_DESCRIPTOR; + +/// PCIe Complex descriptor +typedef struct { + IN UINT32 Flags; /**< Descriptor flags + * @li @b Bit31 - last descriptor in topology + */ + IN UINT32 SocketId; ///< Socket Id + IN PCIe_PORT_DESCRIPTOR *PciePortList; ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). + IN PCIe_DDI_DESCRIPTOR *DdiLinkList; ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). + IN VOID *Reserved; ///< Reserved for future use +} PCIe_COMPLEX_DESCRIPTOR; + +/// Action to control PCIe slot reset +typedef enum { + AssertSlotReset, ///< Assert slot reset + DeassertSlotReset ///< Deassert slot reset +} PCIE_RESET_CONTROL; + +///Slot Reset Info +typedef struct { + IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN UINT8 ResetId; ///< Slot reset ID as specified in PCIe_PORT_DESCRIPTOR + IN UINT8 ResetControl; ///< Reset control as in PCIE_RESET_CONTROL +} PCIe_SLOT_RESET_INFO; + +#define GFX_VBIOS_IMAGE_FLAG_SPECIAL_POST 0x1 + +///VBIOS image info +typedef struct { + IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + OUT VOID *ImagePtr; ///< Pointer to VBIOS image + IN PCI_ADDR GfxPciAddress; ///< PCI address of integrated graphics controller + IN UINT32 Flags; ///< BIT[0] - special repost requred +} GFX_VBIOS_IMAGE_INFO; + +/// Engine descriptor type +typedef enum { + PcieUnusedEngine = 0, ///< Unused descriptor + PciePortEngine = 1, ///< PCIe port + PcieDdiEngine = 2, ///< DDI + MaxPcieEngine ///< Max engine type for boundary check. +} PCIE_ENGINE_TYPE; + +/// PCIe link capability/speed +typedef enum { + PcieGenMaxSupported, ///< Maximum supported + PcieGen1 = 1, ///< Gen1 + PcieGen2, ///< Gen2 + PcieGen3, ///< Gen3 + MaxPcieGen ///< Max Gen for boundary check +} PCIE_LINK_SPEED_CAP; + +/// PCIe PSPP Power policy +typedef enum { + PsppDisabled, ///< PSPP disabled + PsppPerformance = 1, ///< Performance + PsppBalanceHigh, ///< Balance-High + PsppBalanceLow, ///< Balance-Low + PsppPowerSaving, ///< Power Saving + MaxPspp ///< Max Pspp for boundary check +} PCIE_PSPP_POLICY; + +/// DDI display connector type +typedef enum { + ConnectorTypeDP, ///< DP + ConnectorTypeEDP, ///< eDP + ConnectorTypeSingleLinkDVI, ///< Single Link DVI-D + ConnectorTypeDualLinkDVI, ///< Dual Link DVI-D + ConnectorTypeHDMI, ///< HDMI + ConnectorTypeTravisDpToVga, ///< Travis DP-to-VGA + ConnectorTypeTravisDpToLvds, ///< Travis DP-to-LVDS + ConnectorTypeNutmegDpToVga, ///< Hudson-2 NutMeg DP-to-VGA + ConnectorTypeSingleLinkDviI, ///< Single Link DVI-I + ConnectorTypeCrt, ///< CRT (VGA) + ConnectorTypeLvds, ///< LVDS + ConnectorTypeEDPToLvds, ///< 3rd party common eDP-to-LVDS translator chip without AMD SW init + ConnectorTypeEDPToRealtecLvds, ///< Realtek eDP-to-LVDS tansaltor which require AMD SW init + ConnectorTypeAutoDetect, ///< VBIOS auto detect connector type (native LVDS, eDP or Travis-LVDS) + MaxConnectorType ///< Not valid value, used to verify input +} PCIE_CONNECTOR_TYPE; + +/// PCIe link channel type +typedef enum { + ChannelTypeLowLoss, ///< Low Loss + ChannelTypeHighLoss, ///< High Loss + ChannelTypeMob0db, ///< Mobile 0dB + ChannelTypeMob3db, ///< Mobile 3dB + ChannelTypeExt6db, ///< Extended 6dB + ChannelTypeExt8db, ///< Extended 8dB + MaxChannelType ///< Not valid value, used to verify input +} PCIE_CHANNEL_TYPE; + +/// PCIe link ASPM +typedef enum { + AspmDisabled, ///< Disabled + AspmL0s, ///< PCIe L0s link state + AspmL1, ///< PCIe L1 link state + AspmL0sL1, ///< PCIe L0s & L1 link state + MaxAspm ///< Not valid value, used to verify input +} PCIE_ASPM_TYPE; + +/// PCIe link hotplug support +typedef enum { + HotplugDisabled, ///< Hotplug disable + HotplugBasic, ///< Basic Hotplug + HotplugServer, ///< Server Hotplug + HotplugEnhanced, ///< Enhanced + HotplugInboard, ///< Inboard + MaxHotplug ///< Not valid value, used to verify input +} PCIE_HOTPLUG_TYPE; + +/// PCIe link initialization +typedef enum { + PortDisabled, ///< Disable + PortEnabled ///< Enable +} PCIE_PORT_ENABLE; + +/// DDI Aux channel +typedef enum { + Aux1, ///< Aux1 + Aux2, ///< Aux2 + Aux3, ///< Aux3 + Aux4, ///< Aux4 + Aux5, ///< Aux5 + Aux6, ///< Aux6 + MaxAux ///< Not valid value, used to verify input +} PCIE_AUX_TYPE; + +/// DDI Hdp Index +typedef enum { + Hdp1, ///< Hdp1 + Hdp2, ///< Hdp2 + Hdp3, ///< Hdp3 + Hdp4, ///< Hdp4 + Hdp5, ///< Hdp5 + Hdp6, ///< Hdp6 + MaxHdp ///< Not valid value, used to verify input +} PCIE_HDP_TYPE; + +/// PCIe_DDI_DATA.Flags definitions +#define DDI_DATA_FLAGS_DP1_1_ONLY 0x01 ///< BIT[0] Selects downgrade PHY link to DP1.1 + + +// Macro for statically initialization of various structures +#define PCIE_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane) {mType, mStartLane, mEndLane} +#define PCIE_PORT_DATA_INITIALIZER(mPortPresent, mChannelType, mDevAddress, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId) \ +{mPortPresent, mChannelType, mDevAddress, 0, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap, 0, 0}, {0, 0, 0}, EndpointDetect} +#define PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \ +{mConnectorType, mAuxIndex, mHpdIndex, {{0}, {0}}, 0, 0} +#define PCIE_DDI_DATA_INITIALIZER_V1(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1, mPNInversion) \ +{mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}, mPNInversion, 0} +#define PCIE_DDI_DATA_INITIALIZER_V2(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1, mPNInversion, mFlags) \ +{mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}, mPNInversion, mFlags} + +///IOMMU requestor ID +typedef struct { + IN UINT16 Bus :8; ///< Bus + IN UINT16 Device :5; ///< Device + IN UINT16 Function :3; ///< Function +} IOMMU_REQUESTOR_ID; + +/// IVMD exclusion range descriptor +typedef struct { + IN UINT32 Flags; /**< Descriptor flags + * @li @b Flags[31] - Terminate descriptor array. + * @li @b Flags[30] - Ignore descriptor. + */ + IN IOMMU_REQUESTOR_ID RequestorIdStart; ///< Requestor ID start + IN IOMMU_REQUESTOR_ID RequestorIdEnd; ///< Requestor ID end (use same as start for single ID) + IN UINT64 RangeBaseAddress; ///< Phisical base address of exclusion range + IN UINT64 RangeLength; ///< Length of exclusion range in bytes +} IOMMU_EXCLUSION_RANGE_DESCRIPTOR; + +/*---------------------------------------------------------------------------- + * GNB configuration info + *---------------------------------------------------------------------------- + */ + +/// LVDS Misc Control Field +typedef struct { + IN UINT8 FpdiMode:1; ///< This item configures LVDS 888bit panel mode + ///< @li FALSE = LVDS 888 panel in LDI mode + ///< @li TRUE = LVDS 888 panel in FPDI mode + ///< @BldCfgItem{BLDCFG_LVDS_MISC_888_FPDI_MODE} + IN UINT8 DlChSwap:1; ///< This item configures LVDS panel lower and upper link mapping + ///< @li FALSE = Lower link and upper link not swap + ///< @li TRUE = Lower link and upper link are swapped + ///< @BldCfgItem{BLDCFG_LVDS_MISC_DL_CH_SWAP} + IN UINT8 VsyncActiveLow:1; ///< This item configures polarity of frame pulse encoded in lvds data stream + ///< @li FALSE = Active high Frame Pulse/Vsync + ///< @li TRUE = Active low Frame Pulse/Vsync + ///< @BldCfgItem{BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW} + IN UINT8 HsyncActiveLow:1; ///< This item configures polarity of line pulse encoded in lvds data + ///< @li FALSE = Active high Line Pulse + ///< @li TRUE = Active low Line Pulse / Hsync + ///< @BldCfgItem{BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW} + IN UINT8 BLONActiveLow:1; ///< This item configures polarity of signal sent to digital BLON output pin + ///< @li FALSE = Not inverted(active high) + ///< @li TRUE = Inverted (active low) + ///< @BldCfgItem{BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW} + IN UINT8 TravisLvdsVoltOverwriteEn:1; ///< This item configures polarity of Travis LVDS output voltage overwrite + ///< @li FALSE = Travis LVDS output voltage overwrite disable, use VBIOS default setting. + ///< @li TRUE = Use ucTravisLVDSVolAdjust value to program Travis register LVDS_CTRL_4 + ///< @BldCfgItem{BLDCFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE} + IN UINT8 Reserved:2; ///< Reserved +} LVDS_MISC_CONTROL_FIELD; + +/// LVDS Misc Control +typedef union _LVDS_MISC_CONTROL { + IN LVDS_MISC_CONTROL_FIELD Field; ///< LVDS_MISC_CONTROL_FIELD + IN UINT8 Value; ///< LVDS Misc Control Value +} LVDS_MISC_CONTROL; + +/// Display Misc Control Field +typedef struct { + IN UINT8 Reserved1:3; ///< Reserved + IN UINT8 VbiosFastBootEn:1; ///< This item configures VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open. + ///< @li FALSE = VBIOS fast boot is disable. + ///< @li TRUE = VBIOS fast boot is enable. + ///< @BldCfgItem{BLDCFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE} + IN UINT8 Reserved2:4; ///< Reserved +} DISPLAY_MISC_CONTROL_FIELD; + +/// LVDS Misc Control +typedef union _DISPLAY_MISC_CONTROL { + IN DISPLAY_MISC_CONTROL_FIELD Field; ///< DISPLAY_MISC_CONTROL_FIELD + IN UINT8 Value; ///< Display Misc Control Value +} DISPLAY_MISC_CONTROL; + +/// POST Configuration settings for GNB. +typedef struct { + IN UINT8 IgpuEnableDisablePolicy; ///< This item defines the iGPU Enable/Disable policy + ///< @li 0 = Auto - use existing default - + ///< @li 1 = Disable iGPU if any PCIe/PCI graphics card present + ///< @BldCfgItem{BLDCFG_IGPU_ENABLE_DISABLE_POLICY} +} GNB_POST_CONFIGURATION; + +/// iGPU Enable/Disable Policy values +#define IGPU_DISABLE_AUTO 0 ///< Auto setting - disable iGPU if ANY PCI graphics or non-AMD PCIe graphics +#define IGPU_DISABLE_ANY_PCIE 1 ///< Disable iGPU if any PCI or PCIE graphics card is present + +/// ENV Configuration settings for GNB. +typedef struct { + IN UINT8 Gnb3dStereoPinIndex; ///< 3D Stereo Pin ID. + ///< @li 0 = Stereo 3D is disabled (default). + ///< @li 1 = Use processor pin HPD1. + ///< @li 2 = Use processor pin HPD2 + ///< @li 3 = Use processor pin HPD3 + ///< @li 4 = Use processor pin HPD4 + ///< @li 5 = Use processor pin HPD5 + ///< @li 6 = Use processor pin HPD6 + ///< @BldCfgItem{BLDCFG_STEREO_3D_PINOUT} + IN BOOLEAN IommuSupport; ///< IOMMU support. + ///< @li FALSE = Disabled. Disable and hide IOMMU device. + ///< @li TRUE = Initialize IOMMU subsystem. Generate ACPI IVRS table. + ///< BldCfgItem{BLDCFG_IOMMU_SUPPORT} + IN UINT16 LvdsSpreadSpectrum; ///< Spread spectrum value in 0.01 % + ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM} + IN UINT16 LvdsSpreadSpectrumRate; ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz + ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE} + IN UINT8 LvdsPowerOnSeqDigonToDe; ///< This item configures panel initialization timing. + ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE} + IN UINT8 LvdsPowerOnSeqDeToVaryBl; ///< This item configures panel initialization timing. + ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL} + IN UINT8 LvdsPowerOnSeqDeToDigon; ///< This item configures panel initialization timing. + ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON} + IN UINT8 LvdsPowerOnSeqVaryBlToDe; ///< This item configures panel initialization timing. + ///< @BldCfgItem{BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE} + IN UINT8 LvdsPowerOnSeqOnToOffDelay; ///< This item configures panel initialization timing. + ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY} + IN UINT8 LvdsPowerOnSeqVaryBlToBlon; ///< This item configures panel initialization timing. + ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON} + IN UINT8 LvdsPowerOnSeqBlonToVaryBl; ///< This item configures panel initialization timing. + ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL} + IN UINT16 LvdsMaxPixelClockFreq; ///< This item configures the maximum pixel clock frequency supported. + ///< @BldCfgItem{BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ} + IN UINT32 LcdBitDepthControlValue; ///< This item configures the LCD bit depth control settings. + ///< @BldCfgItem{BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE} + IN UINT8 Lvds24bbpPanelMode; ///< This item configures the LVDS 24 BBP mode. + ///< @BldCfgItem{BLDCFG_LVDS_24BBP_PANEL_MODE} + IN LVDS_MISC_CONTROL LvdsMiscControl;///< This item configures LVDS swap/Hsync/Vsync/BLON + IN UINT16 PcieRefClkSpreadSpectrum; ///< Spread spectrum value in 0.01 % + ///< @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM} + IN BOOLEAN GnbRemoteDisplaySupport; ///< This item enables Wireless Display Support + ///< @li TRUE = Enable Wireless Display Support + ///< @li FALSE = Disable Wireless Display Support + ///< @BldCfgItem{BLDCFG_REMOTE_DISPLAY_SUPPORT} + IN UINT8 LvdsMiscVoltAdjustment; ///< Travis register LVDS_CTRL_4 to adjust LVDS output voltage + ///< @BldCfgItem{BLDCFG_LVDS_MISC_VOL_ADJUSTMENT} + IN DISPLAY_MISC_CONTROL DisplayMiscControl;///< This item configures display misc control +} GNB_ENV_CONFIGURATION; + +/// Configuration settings for GNB. +typedef struct { + IN UINT8 iGpuVgaMode; ///< VGA resourses decoding configuration for iGPU + ///< @li 0 = iGPU decode all VGA resourses (must be promary VGA adapter) + ///< @li 1 = iGPU will not decode any VGA resourses (must be secondary graphics adapter) +} GNB_MID_CONFIGURATION; + +/// GNB configuration info +typedef struct { + IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL. + * Last element of array must ne terminated with DESCRIPTOR_TERMINATE_LIST + * Example of topology definition for single socket system: + * @code + * PCIe_PORT_DESCRIPTOR PortList [] = { + * // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...) + * { + * 0, //Descriptor flags + * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15), + * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + * }, + * // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...) + * { + * 0, //Descriptor flags + * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19), + * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + * }, + * // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + * { + * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + * } + * }; + * PCIe_PORT_DESCRIPTOR DdiList [] = { + * // Initialize Ddi descriptor (DDI interface Lanes 24:27, Display Port Connector, ...) + * { + * 0, //Descriptor flags + * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0) + * }, + * // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...) + * { + * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0) + * } + * }; + * PCIe_COMPLEX_DESCRIPTOR PlatformTopology = { + * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate complexes list + * 0, //Socket ID + * &PortList[0], + * &DdiList[0], + * } + * @endcode + */ + IN UINT8 PsppPolicy; /**< PSPP (PCIe Speed Power Policy) + * @li @b 0 - Disabled + * @li @b 1 - Performance + * @li @b 2 - Balance-High + * @li @b 3 - Balance-Low + * @li @b 4 - Power Saving + */ + +} GNB_CONFIGURATION; +// +// MEMORY-SPECIFIC DATA STRUCTURES +// +// +// +// +// AGESA MAXIMIUM VALUES +// +// These Max values are used to define array sizes and associated loop +// counts in the code. They reflect the maximum values that AGESA +// currently supports and does not necessarily reflect the hardware +// capabilities of configuration. +// + +#define MAX_SOCKETS_SUPPORTED 8 ///< Max number of sockets in system +#define MAX_CHANNELS_PER_SOCKET 4 ///< Max Channels per sockets +#define MAX_DIMMS_PER_CHANNEL 4 ///< Max DIMMs on a memory channel (independent of platform) +#define NUMBER_OF_DELAY_TABLES 9 ///< Number of tables defined in CH_DEF_STRUCT. + ///< Eg: UINT16 *RcvEnDlys; + ///< UINT8 *WrDqsDlys; + ///< UINT8 *RdDqsDlys; + ///< UINT8 *WrDatDlys; + ///< UINT8 *RdDqsMinDlys; + ///< UINT8 *RdDqsMaxDlys; + ///< UINT8 *WrDatMinDlys; + ///< UINT8 *WrDatMaxDlys; +#define NUMBER_OF_FAILURE_MASK_TABLES 1 ///< Number of failure mask tables + +#define MAX_PLATFORM_TYPES 16 ///< Platform types per system + +#define MCT_TRNG_KEEPOUT_START 0x00004000ul ///< base [39:8] +#define MCT_TRNG_KEEPOUT_END 0x00007FFFul ///< base [39:8] + +#define UMA_ATTRIBUTE_INTERLEAVE 0x80000000ul ///< Uma Region is interleaved +#define UMA_ATTRIBUTE_ON_DCT0 0x40000000ul ///< UMA resides on memory that belongs to DCT0 +#define UMA_ATTRIBUTE_ON_DCT1 0x20000000ul ///< UMA resides on memory that belongs to DCT1 + +typedef UINT8 PSO_TABLE; ///< Platform Configuration Table + +// AGESA DEFINITIONS +// +// Many of these are derived from the platform and hardware specific definitions + +/// EccSymbolSize override value +#define ECCSYMBOLSIZE_USE_BKDG 0 ///< Use BKDG Recommended Value +#define ECCSYMBOLSIZE_FORCE_X4 4 ///< Force to x4 +#define ECCSYMBOLSIZE_FORCE_X8 8 ///< Force to x8 +/// CPU Package Type +#define PT_L1 0 ///< L1 Package type +#define PT_M2 1 ///< AM Package type +#define PT_S1 2 ///< S1 Package type + +/// Structures use to pass system Logical CPU-ID +typedef struct { + IN OUT UINT64 Family; ///< Indicates logical ID Family + IN OUT UINT64 Revision; ///< Indicates logical ID Family +} CPU_LOGICAL_ID; + +/// Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE +typedef enum { + AMD_PLATFORM_SERVER = 0x8000, ///< Server + AMD_PLATFORM_DESKTOP = 0x10000, ///< Desktop + AMD_PLATFORM_MOBILE = 0x20000, ///< Mobile +} AMD_PLATFORM_TYPE; + +/// Dram technology type +typedef enum { + DDR2_TECHNOLOGY, ///< DDR2 technology + DDR3_TECHNOLOGY ///< DDR3 technology +} TECHNOLOGY_TYPE; + +/// Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT +typedef enum { + DDR400_FREQUENCY = 200, ///< DDR 400 + DDR533_FREQUENCY = 266, ///< DDR 533 + DDR667_FREQUENCY = 333, ///< DDR 667 + DDR800_FREQUENCY = 400, ///< DDR 800 + DDR1066_FREQUENCY = 533, ///< DDR 1066 + DDR1333_FREQUENCY = 667, ///< DDR 1333 + DDR1600_FREQUENCY = 800, ///< DDR 1600 + DDR1866_FREQUENCY = 933, ///< DDR 1866 + DDR2100_FREQUENCY = 1050, ///< DDR 2100 + DDR2133_FREQUENCY = 1066, ///< DDR 2133 + DDR2400_FREQUENCY = 1200, ///< DDR 2400 + UNSUPPORTED_DDR_FREQUENCY ///< Highest limit of DDR frequency +} MEMORY_BUS_SPEED; + +/// Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE +typedef enum { + QUADRANK_REGISTERED, ///< Quadrank registered DIMM + QUADRANK_UNBUFFERED ///< Quadrank unbuffered DIMM +} QUANDRANK_TYPE; + +/// Build Configuration values for BLDCFG_TIMING_MODE_SELECT +typedef enum { + TIMING_MODE_AUTO, ///< Use best rate possible + TIMING_MODE_LIMITED, ///< Set user top limit + TIMING_MODE_SPECIFIC ///< Set user specified speed +} USER_MEMORY_TIMING_MODE; + +/// Build Configuration values for BLDCFG_POWER_DOWN_MODE +typedef enum { + POWER_DOWN_BY_CHANNEL, ///< Channel power down mode + POWER_DOWN_BY_CHIP_SELECT, ///< Chip select power down mode + POWER_DOWN_MODE_AUTO ///< AGESA to select power down mode +} POWER_DOWN_MODE; + +/// Low voltage support +typedef enum { + VOLT_INITIAL, ///< Initial value for VDDIO + VOLT1_5, ///< 1.5 Volt + VOLT1_35, ///< 1.35 Volt + VOLT1_25, ///< 1.25 Volt + VOLT_UNSUPPORTED = 0xFF ///< No common voltage found +} DIMM_VOLTAGE; + +/// UMA Mode +typedef enum { + UMA_NONE = 0, ///< UMA None + UMA_SPECIFIED = 1, ///< UMA Specified + UMA_AUTO = 2 ///< UMA Auto +} UMA_MODE; + +/// Force Training Mode +typedef enum { + FORCE_TRAIN_1D = 0, ///< 1D Training only + FORCE_ENUM1 = 1, + FORCE_TRAIN_AUTO = 2 +} FORCE_TRAIN_MODE; + +/// The possible DRAM prefetch mode settings. +typedef enum { + DRAM_PREFETCHER_AUTO, ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled. + DISABLE_DRAM_PREFETCH_FOR_IO, ///< Disable DRAM prefetching for I/O requests only. + DISABLE_DRAM_PREFETCH_FOR_CPU, ///< Disable DRAM prefetching for requests from processor cores only. + DISABLE_DRAM_PREFETCHER, ///< Disable DRAM prefetching. + MAX_DRAM_FREFETCH_MODE ///< Not a DRAM prefetch mode, use for limit checking. +} DRAM_PREFETCH_MODE; + +/// Build Configuration values for BLDCFG_UMA_ALIGNMENT +typedef enum { + NO_UMA_ALIGNED = 0x00FFFFFF, ///< NO UMA aligned + UMA_4MB_ALIGNED = 0x00FFFFC0, ///< UMA 4MB aligned + UMA_128MB_ALIGNED = 0x00FFF800, ///< UMA 128MB aligned + UMA_256MB_ALIGNED = 0x00FFF000, ///< UMA 256MB aligned + UMA_512MB_ALIGNED = 0x00FFE000, ///< UMA 512MB aligned +} UMA_ALIGNMENT; + +/// +/// Global MCT Configuration Status Word (GStatus) +/// +typedef enum { + GsbMTRRshort, ///< Ran out of MTRRs while mapping memory + GsbAllECCDimms, ///< All banks of all Nodes are ECC capable + GsbDramECCDis, ///< Dram ECC requested but not enabled. + GsbSoftHole, ///< A Node Base gap was created + GsbHWHole, ///< A HW dram remap was created + GsbNodeIntlv, ///< Node Memory interleaving was enabled + GsbSpIntRemapHole, ///< Special condition for Node Interleave and HW remapping + GsbEnDIMMSpareNW, ///< Indicates that DIMM Spare can be used without a warm reset + + GsbEOL ///< End of list +} GLOBAL_STATUS_FIELD; + +/// +/// Local Error Status (DIE_STRUCT.ErrStatus[31:0]) +/// +typedef enum { + EsbNoDimms, ///< No DIMMs + EsbSpdChkSum, ///< SPD Checksum fail + EsbDimmMismatchM, ///< dimm module type(buffer) mismatch + EsbDimmMismatchT, ///< dimm CL/T mismatch + EsbDimmMismatchO, ///< dimm organization mismatch (128-bit) + EsbNoTrcTrfc, ///< SPD missing Trc or Trfc info + EsbNoCycTime, ///< SPD missing byte 23 or 25 + EsbBkIntDis, ///< Bank interleave requested but not enabled + EsbDramECCDis, ///< Dram ECC requested but not enabled + EsbSpareDis, ///< Online spare requested but not enabled + EsbMinimumMode, ///< Running in Minimum Mode + EsbNoRcvrEn, ///< No DQS Receiver Enable pass window found + EsbSmallRcvr, ///< DQS Rcvr En pass window too small (far right of dynamic range) + EsbNoDqsPos, ///< No DQS-DQ passing positions + EsbSmallDqs, ///< DQS-DQ passing window too small + EsbDCBKScrubDis, ///< DCache scrub requested but not enabled + + EsbEMPNotSupported, ///< Processor is not capable for EMP. + EsbEMPConflict, ///< EMP requested but cannot be enabled since + ///< channel interleaving, bank interleaving, or bank swizzle is enabled. + EsbEMPDis, ///< EMP requested but cannot be enabled since + ///< memory size of each DCT is not a power of two. + + EsbEOL ///< End of list +} ERROR_STATUS_FIELD; + +/// +/// Local Configuration Status (DIE_STRUCT.Status[31:0]) +/// +typedef enum { + SbRegistered, ///< All DIMMs are Registered + SbEccDimms, ///< All banks ECC capable + SbParDimms, ///< All banks Addr/CMD Parity capable + SbDiagClks, ///< Jedec ALL slots clock enable diag mode + Sb128bitmode, ///< DCT in 128-bit mode operation + Sb64MuxedMode, ///< DCT in 64-bit mux'ed mode. + Sb2TMode, ///< 2T CMD timing mode is enabled. + SbSWNodeHole, ///< Remapping of Node Base on this Node to create a gap. + SbHWHole, ///< Memory Hole created on this Node using HW remapping. + SbOver400Mhz, ///< DCT freq greater than or equal to 400MHz flag + SbDQSPosPass2, ///< Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz + SbDQSRcvLimit, ///< Used for DQSRcvEnTrain to know we have reached the upper bound. + SbExtConfig, ///< Indicate the default setting for extended PCI configuration support + SbLrdimms, ///< All DIMMs are LRDIMMs + + SbEOL ///< End of list +} LOCAL_STATUS_FIELD; + + +///< CPU MSR Register definitions ------------------------------------------ +#define SYS_CFG 0xC0010010ul +#define TOP_MEM 0xC001001Aul +#define TOP_MEM2 0xC001001Dul +#define HWCR 0xC0010015ul +#define NB_CFG 0xC001001Ful + +#define FS_BASE 0xC0000100ul +#define IORR0_BASE 0xC0010016ul +#define IORR0_MASK 0xC0010017ul +#define BU_CFG 0xC0011023ul +#define BU_CFG2 0xC001102Aul +#define COFVID_STAT 0xC0010071ul +#define TSC 0x10 + +//----------------------------------------------------------------------------- +/// +/// SPD Data for each DIMM. +/// +typedef struct _SPD_DEF_STRUCT { + IN BOOLEAN DimmPresent; ///< Indicates that the DIMM is present and Data is valid + IN UINT8 Data[256]; ///< Buffer for 256 Bytes of SPD data from DIMM +} SPD_DEF_STRUCT; + +/// +/// Channel Definition Structure. +/// This data structure defines entries that are specific to the channel initialization +/// +typedef struct _CH_DEF_STRUCT { + OUT UINT8 ChannelID; ///< Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D) + OUT TECHNOLOGY_TYPE TechType; ///< Technology type of this channel + OUT UINT8 ChDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is present. + ///< DIMM# Select Signal + ///< 0 MA0_CS_L[0, 1] + ///< 1 MB0_CS_L[0, 1] + ///< 2 MA1_CS_L[0, 1] + ///< 3 MB1_CS_L[0, 1] + ///< 4 MA2_CS_L[0, 1] + ///< 5 MB2_CS_L[0, 1] + ///< 6 MA3_CS_L[0, 1] + ///< 7 MB3_CS_L[0, 1] + + OUT struct _DCT_STRUCT *DCTPtr; ///< Pointer to the DCT data of this channel. + OUT struct _DIE_STRUCT *MCTPtr; ///< Pointer to the node data of this channel. + OUT SPD_DEF_STRUCT *SpdPtr; ///< Pointer to the SPD data for this channel. (Setup by NB Constructor) + OUT SPD_DEF_STRUCT *DimmSpdPtr[MAX_DIMMS_PER_CHANNEL]; ///< Array of pointers to + ///< SPD Data for each Dimm. (Setup by Tech Block Constructor) + OUT UINT8 ChDimmValid; ///< For each bit n 0..3, 1 = DIMM n is valid and is/will be configured where 4..7 are reserved. + ///< + OUT UINT8 RegDimmPresent; ///< For each bit n 0..3, 1 = DIMM n is a registered DIMM where 4..7 are reserved. + OUT UINT8 LrDimmPresent; ///< For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved. + OUT UINT8 SODimmPresent; ///< For each bit n 0..3, 1 = DIMM n is a SO-DIMM, where 4..7 are reserved. + OUT UINT8 Loads; ///< Number of devices loading bus + OUT UINT8 Dimms; ///< Number of DIMMs loading Channel + OUT UINT8 Ranks; ///< Number of ranks loading Channel DATA + OUT BOOLEAN SlowMode; ///< 1T or 2T CMD mode (slow access mode) + ///< FALSE = 1T + ///< TRUE = 2T + ///< The following pointers will be pointed to dynamically allocated buffers. + ///< Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below. + ///< Example: If DIMM and Byte based training, then + ///< XX is a value in Hex + ///< BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE + ///< Row1 - Logical DIMM0 XX XX XX XX XX XX XX XX XX + ///< Row2 - Logical DIMM1 XX XX XX XX XX XX XX XX XX + OUT UINT16 *RcvEnDlys; ///< DQS Receiver Enable Delays + OUT UINT8 *WrDqsDlys; ///< Write DQS delays (only valid for DDR3) + OUT UINT8 *RdDqsDlys; ///< Read Dqs delays + OUT UINT8 *WrDatDlys; ///< Write Data delays + OUT UINT8 *RdDqs2dDlys; ///< 2d Read DQS data + OUT UINT8 *RdDqsMinDlys; ///< Minimum Window for Read DQS + OUT UINT8 *RdDqsMaxDlys; ///< Maximum Window for Read DQS + OUT UINT8 *WrDatMinDlys; ///< Minimum Window for Write data + OUT UINT8 *WrDatMaxDlys; ///< Maximum Window for Write data + OUT UINT16 *RcvEnDlysMemPs1; ///< DQS Receiver Enable Delays for Mem Pstate 1 + OUT UINT8 *WrDqsDlysMemPs1; ///< Write DQS delays (only valid for DDR3) for Mem Pstate 1 + OUT UINT8 *RdDqsDlysMemPs1; ///< Read Dqs delays for Memory Pstate 1 + OUT UINT8 *WrDatDlysMemPs1; ///< Write Data delays for Memory Pstate 1 + OUT UINT8 *RdDqs2dDlysMemPs1; ///< 2d Read DQS data for Memory Pstate 1 + OUT UINT8 *RdDqsMinDlysMemPs1; ///< Minimum Window for Read DQS for Memory Pstate 1 + OUT UINT8 *RdDqsMaxDlysMemPs1; ///< Maximum Window for Read DQS for Memory Pstate 1 + OUT UINT8 *WrDatMinDlysMemPs1; ///< Minimum Window for Write data for Memory Pstate 1 + OUT UINT8 *WrDatMaxDlysMemPs1; ///< Maximum Window for Write data for Memory Pstate 1 + OUT UINT8 RowCount; ///< Number of rows of the allocated buffer. + OUT UINT8 ColumnCount; ///< Number of columns of the allocated buffer. + OUT UINT8 *FailingBitMask; ///< Table of masks to Track Failing bits + OUT UINT8 *FailingBitMaskMemPs1; ///< Table of masks to Track Failing bits for Memory Pstate 1 + OUT UINT32 DctOdcCtl; ///< Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h) + OUT UINT32 DctAddrTmg; ///< Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h) + OUT UINT32 PhyRODTCSLow; ///< Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h) + OUT UINT32 PhyRODTCSHigh; ///< Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h) + OUT UINT32 PhyWODTCSLow; ///< Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h) + OUT UINT32 PhyWODTCSHigh; ///< Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183) + OUT UINT8 PhyWLODT[4]; ///< Write Levelization ODT Pattern for Dimm 0-3 or CS 0-7(see BKDG FN2:Offset 9Ch, index 0x8[11:8]) + OUT UINT16 DctEccDqsLike; ///< DCT DQS ECC UINT8 like... + OUT UINT8 DctEccDqsScale; ///< DCT DQS ECC UINT8 scale + OUT UINT16 PtrPatternBufA; ///< Ptr on stack to aligned DQS testing pattern + OUT UINT16 PtrPatternBufB; ///< Ptr on stack to aligned DQS testing pattern + OUT UINT8 ByteLane; ///< Current UINT8 Lane (0..7) + OUT UINT8 Direction; ///< Current DQS-DQ training write direction (0=read, 1=write) + OUT UINT8 Pattern; ///< Current pattern + OUT UINT8 DqsDelay; ///< Current DQS delay value + OUT UINT16 HostBiosSrvc1; ///< UINT16 sized general purpose field for use by host BIOS. Scratch space. + OUT UINT32 HostBiosSrvc2; ///< UINT32 sized general purpose field for use by host BIOS. Scratch space. + OUT UINT16 DctMaxRdLat[4]; ///< Max Read Latency (ns) for the DCT + ///< DctMaxRdLat [i] is for NBPstate i + OUT UINT8 DIMMValidCh; ///< DIMM# in CH + OUT UINT8 MaxCh; ///< Max number of CH in system + OUT UINT8 Dct; ///< Dct pointer + OUT UINT8 WrDatGrossH; ///< Write Data Gross delay high value + OUT UINT8 DqsRcvEnGrossL; ///< DQS Receive Enable Gross Delay low + + OUT UINT8 TrwtWB; ///< Non-SPD timing value for TrwtWB + OUT UINT8 CurrRcvrDctADelay; ///< for keep current RcvrEnDly + OUT UINT16 T1000; ///< get the T1000 figure (cycle time (ns) * 1K) + OUT UINT8 DqsRcvEnPass; ///< for TrainRcvrEn UINT8 lane pass flag + OUT UINT8 DqsRcvEnSaved; ///< for TrainRcvrEn UINT8 lane saved flag + OUT UINT8 SeedPass1Remainder; ///< for Phy assisted DQS receiver enable training + + OUT UINT8 ClToNbFlag; ///< is used to restore ClLinesToNbDis bit after memory + OUT UINT32 NodeSysBase; ///< for channel interleave usage + OUT UINT8 RefRawCard[MAX_DIMMS_PER_CHANNEL]; ///< Array of rawcards detected + OUT UINT8 CtrlWrd02[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 2 values per DIMM + OUT UINT8 CtrlWrd03[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 3 values per DIMM + OUT UINT8 CtrlWrd04[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 4 values per DIMM + OUT UINT8 CtrlWrd05[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 5 values per DIMM + OUT UINT8 CtrlWrd08[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 8 values per DIMM + + OUT UINT16 CsPresentDCT; ///< For each bit n 0..7, 1 = Chip-select n is present + OUT UINT8 DimmMirrorPresent; ///< For each bit n 0..3, 1 = DIMM n is OnDimmMirror capable where 4..7 are reserved. + OUT UINT8 DimmSpdCse; ///< For each bit n 0..3, 1 = DIMM n SPD checksum error where 4..7 are reserved. + OUT UINT8 DimmExclude; ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved. + OUT UINT8 DimmYr06; ///< Bitmap indicating which Dimms have a manufacturer's year code <= 2006 + OUT UINT8 DimmWk2406; ///< Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June) + OUT UINT8 DimmPlPresent; ///< Bitmap indicating that Planar (1) or Stacked (0) Dimms are present. + OUT UINT8 DimmQrPresent; ///< QuadRank DIMM present? + OUT UINT8 DimmDrPresent; ///< Bitmap indicating that Dual Rank Dimms are present + OUT UINT8 DimmSRPresent; ///< Bitmap indicating that Single Rank Dimms are present + OUT UINT8 Dimmx4Present; ///< For each bit n 0..3, 1 = DIMM n contains x4 data devices. where 4..7 are reserved. + OUT UINT8 Dimmx8Present; ///< For each bit n 0..3, 1 = DIMM n contains x8 data devices. where 4..7 are reserved. + OUT UINT8 Dimmx16Present; ///< For each bit n 0..3, 1 = DIMM n contains x16 data devices. where 4..7 are reserved. + OUT UINT8 LrdimmPhysicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of Physical Ranks for LRDIMMs + OUT UINT8 LrDimmLogicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of LRDIMM Logical ranks in this configuration + OUT UINT8 LrDimmRankMult[MAX_DIMMS_PER_CHANNEL];///< Rank Multipication factor per dimm. + OUT UINT8 DimmNibbleAccess; ///< For each bit n 0..3, 1 = DIMM n will use nibble signaling. Where 4..7 are reserved. + OUT UINT8 *MemClkDisMap; ///< This pointer will be set to point to an array that describes + ///< the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will + ///< base on this array to disable unused MemClk to save power. + ///< + ///< The array must have 8 entries. Each entry, which associates with + ///< one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to. + ///< Example: + ///< BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package + ///< is like below: + ///< Bit AM3/S1g3 pin name + ///< 0 M[B,A]_CLK_H/L[0] + ///< 1 M[B,A]_CLK_H/L[1] + ///< 2 M[B,A]_CLK_H/L[2] + ///< 3 M[B,A]_CLK_H/L[3] + ///< 4 M[B,A]_CLK_H/L[4] + ///< 5 M[B,A]_CLK_H/L[5] + ///< 6 M[B,A]_CLK_H/L[6] + ///< 7 M[B,A]_CLK_H/L[7] + ///< And platform has the following routing: + ///< CS0 M[B,A]_CLK_H/L[4] + ///< CS1 M[B,A]_CLK_H/L[2] + ///< CS2 M[B,A]_CLK_H/L[3] + ///< CS3 M[B,A]_CLK_H/L[5] + ///< Then MemClkDisMap should be pointed to the following array: + ///< CLK_2 CLK_3 CLK_4 CLK_5 + ///< 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00 + ///< Each entry of the array is the bitmask of 8 chip selects. + + OUT UINT8 *CKETriMap; ///< This pointer will be set to point to an array that describes + ///< the routing of CKE pins to the DIMMs' ranks. + ///< The array must have 2 entries. Each entry, which associates with + ///< one CKE pin, is a bitmap of 8 CS that that CKE is routed to. + ///< AGESA will base on this array to disable unused CKE pins to save power. + + OUT UINT8 *ODTTriMap; ///< This pointer will be set to point to an array that describes + ///< the routing of ODT pins to the DIMMs' ranks. + ///< The array must have 4 entries. Each entry, which associates with + ///< one ODT pin, is a bitmap of 8 CS that that ODT is routed to. + ///< AGESA will base on this array to disable unused ODT pins to save power. + + OUT UINT8 *ChipSelTriMap; ///< This pointer will be set to point to an array that describes + ///< the routing of chip select pins to the DIMMs' ranks. + ///< The array must have 8 entries. Each entry is a bitmap of 8 CS. + ///< AGESA will base on this array to disable unused Chip select pins to save power. + + OUT BOOLEAN ExtendTmp; ///< If extended temperature is supported on all dimms on a channel. + + OUT UINT8 MaxVref; ///< Maximum Vref Value for channel + + OUT UINT8 Reserved[100]; ///< Reserved +} CH_DEF_STRUCT; + +/// +/// DCT Channel Timing Parameters. +/// This data structure sets timings that are specific to the channel. +/// +typedef struct _CH_TIMING_STRUCT { + OUT UINT16 DctDimmValid; ///< For each bit n 0..3, 1=DIMM n is valid and is/will be configured where 4..7 are reserved. + OUT UINT16 DimmMirrorPresent; ///< For each bit n 0..3, 1=DIMM n is OnDimmMirror capable where 4..7 are reserved. + OUT UINT16 DimmSpdCse; ///< For each bit n 0..3, 1=DIMM n SPD checksum error where 4..7 are reserved. + OUT UINT16 DimmExclude; ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved. + OUT UINT16 CsPresent; ///< For each bit n 0..7, 1=Chip-select n is present + OUT UINT16 CsEnabled; ///< For each bit n 0..7, 1=Chip-select n is enabled + OUT UINT16 CsTestFail; ///< For each bit n 0..7, 1=Chip-select n is present but disabled + OUT UINT16 CsTrainFail; ///< Bitmap showing which chipselects failed training + OUT UINT16 DIMM1KPage; ///< For each bit n 0..3, 1=DIMM n contains 1K page devices. where 4..7 are reserved + OUT UINT16 DimmQrPresent; ///< QuadRank DIMM present? + OUT UINT16 DimmDrPresent; ///< Bitmap indicating that Dual Rank Dimms are present , where 4..7 are reserved + OUT UINT8 DimmSRPresent; ///< Bitmap indicating that Single Rank Dimms are present, where 4..7 are reserved + OUT UINT16 Dimmx4Present; ///< For each bit n 0..3, 1=DIMM n contains x4 data devices. where 4..7 are reserved + OUT UINT16 Dimmx8Present; ///< For each bit n 0..3, 1=DIMM n contains x8 data devices. where 4..7 are reserved + OUT UINT16 Dimmx16Present; ///< For each bit n 0..3, 1=DIMM n contains x16 data devices. where 4..7 are reserved + + OUT UINT16 DIMMTrcd; ///< Minimax Trcd*40 (ns) of DIMMs + OUT UINT16 DIMMTrp; ///< Minimax Trp*40 (ns) of DIMMs + OUT UINT16 DIMMTrtp; ///< Minimax Trtp*40 (ns) of DIMMs + OUT UINT16 DIMMTras; ///< Minimax Tras*40 (ns) of DIMMs + OUT UINT16 DIMMTrc; ///< Minimax Trc*40 (ns) of DIMMs + OUT UINT16 DIMMTwr; ///< Minimax Twr*40 (ns) of DIMMs + OUT UINT16 DIMMTrrd; ///< Minimax Trrd*40 (ns) of DIMMs + OUT UINT16 DIMMTwtr; ///< Minimax Twtr*40 (ns) of DIMMs + OUT UINT16 DIMMTfaw; ///< Minimax Tfaw*40 (ns) of DIMMs + OUT UINT16 TargetSpeed; ///< Target DRAM bus speed in MHz + OUT UINT16 Speed; ///< DRAM bus speed in MHz + ///< 400 (MHz) + ///< 533 (MHz) + ///< 667 (MHz) + ///< 800 (MHz) + ///< and so on... + OUT UINT8 CasL; ///< CAS latency DCT setting (busclocks) + OUT UINT8 Trcd; ///< DCT Trcd (busclocks) + OUT UINT8 Trp; ///< DCT Trp (busclocks) + OUT UINT8 Trtp; ///< DCT Trtp (busclocks) + OUT UINT8 Tras; ///< DCT Tras (busclocks) + OUT UINT8 Trc; ///< DCT Trc (busclocks) + OUT UINT8 Twr; ///< DCT Twr (busclocks) + OUT UINT8 Trrd; ///< DCT Trrd (busclocks) + OUT UINT8 Twtr; ///< DCT Twtr (busclocks) + OUT UINT8 Tfaw; ///< DCT Tfaw (busclocks) + OUT UINT8 Trfc0; ///< DCT Logical DIMM0 Trfc + ///< 0 = 75ns (for 256Mb devs) + ///< 1 = 105ns (for 512Mb devs) + ///< 2 = 127.5ns (for 1Gb devs) + ///< 3 = 195ns (for 2Gb devs) + ///< 4 = 327.5ns (for 4Gb devs) + OUT UINT8 Trfc1; ///< DCT Logical DIMM1 Trfc (see Trfc0 for format) + OUT UINT8 Trfc2; ///< DCT Logical DIMM2 Trfc (see Trfc0 for format) + OUT UINT8 Trfc3; ///< DCT Logical DIMM3 Trfc (see Trfc0 for format) + OUT UINT32 DctMemSize; ///< Base[47:16], total DRAM size controlled by this DCT. + ///< + OUT BOOLEAN SlowMode; ///< 1T or 2T CMD mode (slow access mode) + ///< FALSE = 1T + ///< TRUE = 2T + OUT UINT8 TrwtTO; ///< DCT TrwtTO (busclocks) + OUT UINT8 Twrrd; ///< DCT Twrrd (busclocks) + OUT UINT8 Twrwr; ///< DCT Twrwr (busclocks) + OUT UINT8 Trdrd; ///< DCT Trdrd (busclocks) + OUT UINT8 TrwtWB; ///< DCT TrwtWB (busclocks) + OUT UINT8 TrdrdSD; ///< DCT TrdrdSD (busclocks) + OUT UINT8 TwrwrSD; ///< DCT TwrwrSD (busclocks) + OUT UINT8 TwrrdSD; ///< DCT TwrrdSD (busclocks) + OUT UINT16 MaxRdLat; ///< Max Read Latency + OUT UINT8 WrDatGrossH; ///< Temporary variables must be removed + OUT UINT8 DqsRcvEnGrossL; ///< Temporary variables must be removed +} CH_TIMING_STRUCT; + +/// +/// Data for each DCT. +/// This data structure defines data used to configure each DRAM controller. +/// +typedef struct _DCT_STRUCT { + OUT UINT8 Dct; ///< Current Dct + OUT CH_TIMING_STRUCT Timings; ///< Channel Timing structure + OUT CH_TIMING_STRUCT *TimingsMemPs1; ///< Pointed to channel timing structure for memory Pstate 1 + OUT CH_DEF_STRUCT *ChData; ///< Pointed to a dynamically allocated array of Channel structures + OUT UINT8 ChannelCount; ///< Number of channel per this DCT + OUT BOOLEAN BkIntDis; ///< Bank interleave requested but not enabled on current DCT +} DCT_STRUCT; + + +/// +/// Data Structure defining each Die. +/// This data structure contains information that is used to configure each Die. +/// +typedef struct _DIE_STRUCT { + + /// Advanced: + + OUT UINT8 NodeId; ///< Node ID of current controller + OUT UINT8 SocketId; ///< Socket ID of this Die + OUT UINT8 DieId; ///< ID of this die relative to the socket + OUT PCI_ADDR PciAddr; ///< Pci bus and device number of this controller. + OUT AGESA_STATUS ErrCode; ///< Current error condition of Node + ///< 0x0 = AGESA_SUCCESS + ///< 0x1 = AGESA_UNSUPPORTED + ///< 0x2 = AGESA_BOUNDS_CHK + ///< 0x3 = AGESA_ALERT + ///< 0x4 = AGESA_WARNING + ///< 0x5 = AGESA_ERROR + ///< 0x6 = AGESA_CRITICAL + ///< 0x7 = AGESA_FATAL + ///< + OUT BOOLEAN ErrStatus[EsbEOL]; ///< Error Status bit Field + ///< + OUT BOOLEAN Status[SbEOL]; ///< Status bit Field + ///< + OUT UINT32 NodeMemSize; ///< Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node. + ///< + OUT UINT32 NodeSysBase; ///< Base[47:16] (system address) DRAM base address of this Node. + ///< + OUT UINT32 NodeHoleBase; ///< If not zero, Base[47:16] (system address) of dram hole for HW remapping. Dram hole exists on this Node + ///< + OUT UINT32 NodeSysLimit; ///< Base[47:16] (system address) DRAM limit address of this Node. + ///< + OUT UINT32 DimmPresent; ///< For each bit n 0..7, 1 = DIMM n is present. + ///< DIMM# Select Signal + ///< 0 MA0_CS_L[0, 1] + ///< 1 MB0_CS_L[0, 1] + ///< 2 MA1_CS_L[0, 1] + ///< 3 MB1_CS_L[0, 1] + ///< 4 MA2_CS_L[0, 1] + ///< 5 MB2_CS_L[0, 1] + ///< 6 MA3_CS_L[0, 1] + ///< 7 MB3_CS_L[0, 1] + ///< + OUT UINT32 DimmValid; ///< For each bit n 0..7, 1 = DIMM n is valid and is / will be configured + OUT UINT32 RegDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is registered DIMM + OUT UINT32 LrDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is Load Reduced DIMM + OUT UINT32 DimmEccPresent; ///< For each bit n 0..7, 1 = DIMM n is ECC capable. + OUT UINT32 DimmParPresent; ///< For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable. + ///< + OUT UINT16 DimmTrainFail; ///< Bitmap showing which dimms failed training + OUT UINT16 ChannelTrainFail; ///< Bitmap showing the channel information about failed Chip Selects + ///< 0 in any bit field indicates Channel 0 + ///< 1 in any bit field indicates Channel 1 + OUT UINT8 Dct; ///< Need to be removed + ///< DCT pointer + OUT BOOLEAN GangedMode; ///< Ganged mode + ///< 0 = disabled + ///< 1 = enabled + OUT CPU_LOGICAL_ID LogicalCpuid; ///< The logical CPUID of the node + ///< + OUT UINT16 HostBiosSrvc1; ///< UINT16 sized general purpose field for use by host BIOS. Scratch space. + ///< + OUT UINT32 HostBiosSrvc2; ///< UINT32 sized general purpose field for use by host BIOS. Scratch space. + ///< + OUT UINT8 MLoad; ///< Need to be removed + ///< Number of devices loading MAA bus + ///< + OUT UINT8 MaxAsyncLat; ///< Legacy wrapper + ///< + OUT UINT8 ChbD3Rcvrdly; ///< Legacy wrapper + ///< + OUT UINT16 ChaMaxRdLat; ///< Max Read Latency (ns) for DCT 0 + ///< + OUT UINT8 ChbD3BcRcvrdly; ///< CHB DIMM 3 Check UINT8 Receiver Enable Delay + + OUT DCT_STRUCT *DctData; ///< Pointed to a dynamically allocated array of DCT_STRUCTs + OUT UINT8 DctCount; ///< Number of DCTs per this Die + OUT UINT8 Reserved[16]; ///< Reserved +} DIE_STRUCT; + +/********************************************************************** + * S3 Support structure + **********************************************************************/ +/// AmdInitResume, AmdS3LateRestore, and AmdS3Save param structure +typedef struct { + OUT UINT32 Signature; ///< "ASTR" for AMD Suspend-To-RAM + OUT UINT16 Version; ///< S3 Params version number + IN OUT UINT32 Flags; ///< Indicates operation + IN OUT VOID *NvStorage; ///< Pointer to memory critical save state data + IN OUT UINT32 NvStorageSize; ///< Size in bytes of the NvStorage region + IN OUT VOID *VolatileStorage; ///< Pointer to remaining AMD save state data + IN OUT UINT32 VolatileStorageSize; ///< Size in bytes of the VolatileStorage region +} AMD_S3_PARAMS; + +///=============================================================================== +/// MEM_PARAMETER_STRUCT +/// This data structure is used to pass wrapper parameters to the memory configuration code +/// +typedef struct _MEM_PARAMETER_STRUCT { + + // Basic (Return parameters) + // (This section contains the outbound parameters from the memory init code) + + OUT BOOLEAN GStatus[GsbEOL]; ///< Global Status bitfield. + ///< + OUT UINT32 HoleBase; ///< If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping. + ///< + OUT UINT32 Sub4GCacheTop; ///< If not zero, the 32-bit top of cacheable memory. + ///< + OUT UINT32 Sub1THoleBase; ///< If not zero Base[47:16] (system address) of sub 1TB dram hole. + ///< + OUT UINT32 SysLimit; ///< Limit[47:16] (system address). + ///< + OUT DIMM_VOLTAGE DDR3Voltage; ///< Find support voltage and send back to platform BIOS. + ///< + OUT UINT8 ExternalVrefValue; ///< Target reference voltage for external Vref for 2D training + ///< + OUT struct _MEM_DATA_STRUCT *MemData; ///< Access to global memory init data. + + // Advanced (Optional parameters) + // Optional (all defaults values will be initialized by the + // 'AmdMemInitDataStructDef' based on AMD defaults. It is up + // to the IBV/OEM to change the defaults after initialization + // but prior to the main entry to the memory code): + + // Memory Map/Mgt. + + IN UINT16 BottomIo; ///< Bottom of 32-bit IO space (8-bits). + ///< NV_BOTTOM_IO[7:0]=Addr[31:24] + ///< + IN BOOLEAN MemHoleRemapping; ///< Memory Hole Remapping (1-bit). + ///< FALSE = disable + ///< TRUE = enable + ///< + IN BOOLEAN LimitMemoryToBelow1Tb;///< Limit memory address space to below 1 TB + ///< FALSE = disable + ///< TRUE = enable + ///< + ///< @BldCfgItem{BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB} + + + // Dram Timing + + IN USER_MEMORY_TIMING_MODE UserTimingMode; ///< User Memclock Mode. + ///< @BldCfgItem{BLDCFG_TIMING_MODE_SELECT} + + IN MEMORY_BUS_SPEED MemClockValue; ///< Memory Clock Value. + ///< @BldCfgItem{BLDCFG_MEMORY_CLOCK_SELECT} + + + // Dram Configuration + + IN BOOLEAN EnableBankIntlv; ///< Dram Bank (chip-select) Interleaving (1-bit). + ///< - FALSE =disable (default) + ///< - TRUE = enable + ///< + ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING} + + IN BOOLEAN EnableNodeIntlv; ///< Node Memory Interleaving (1-bit). + ///< - FALSE = disable (default) + ///< - TRUE = enable + ///< + ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING} + + IN BOOLEAN EnableChannelIntlv; ///< Channel Interleaving (1-bit). + ///< - FALSE = disable (default) + ///< - TRUE = enable + ///< + ///< @BldCfgItem{BLDCFG_MEMORY_CHANNEL_INTERLEAVING} + // ECC + + IN BOOLEAN EnableEccFeature; ///< enable ECC error to go into MCE. + ///< - FALSE = disable (default) + ///< - TRUE = enable + ///< + ///< @BldCfgItem{BLDCFG_ENABLE_ECC_FEATURE} + // Dram Power + + IN BOOLEAN EnablePowerDown; ///< CKE based power down mode (1-bit). + ///< - FALSE =disable (default) + ///< - TRUE =enable + ///< + ///< @BldCfgItem{BLDCFG_MEMORY_POWER_DOWN} + + // Online Spare + + IN BOOLEAN EnableOnLineSpareCtl; ///< Chip Select Spare Control bit 0. + ///< - FALSE = disable Spare (default) + ///< - TRUE = enable Spare + ///< + ///< @BldCfgItem{BLDCFG_ONLINE_SPARE} + + IN UINT8 *TableBasedAlterations; ///< Desired modifications to register settings. + + IN PSO_TABLE *PlatformMemoryConfiguration; + ///< A table that contains platform specific settings. + ///< For example, MemClk routing, the number of DIMM slots per channel, .... + ///< AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that + ///< contains default conservative settings. Platform BIOS can either tweak + ///< DefaultPlatformMemoryConfiguration or reassign this pointer to its own table. + ///< + IN BOOLEAN EnableParity; ///< Parity control. + ///< - TRUE = enable + ///< - FALSE = disable (default) + ///< + ///< @BldCfgItem{BLDCFG_MEMORY_PARITY_ENABLE} + + IN BOOLEAN EnableBankSwizzle; ///< BankSwizzle control. + ///< - FALSE = disable + ///< - TRUE = enable (default) + ///< + ///< @BldCfgItem{BLDCFG_BANK_SWIZZLE} + + ///< + + IN BOOLEAN EnableMemClr; ///< Memory Clear functionality control. + ///< - FALSE = disable + ///< - TRUE = enable (default) + ///< + + // Uma Configuration + + IN UMA_MODE UmaMode; ///< Uma Mode + ///< 0 = None + ///< 1 = Specified + ///< 2 = Auto + IN OUT UINT32 UmaSize; ///< The size of shared graphics dram (16-bits) + ///< NV_UMA_Size[31:0]=Addr[47:16] + ///< + OUT UINT32 UmaBase; ///< The allocated Uma base address (32-bits) + ///< NV_UMA_Base[31:0]=Addr[47:16] + ///< + + /// Memory Restore Feature + + IN BOOLEAN MemRestoreCtl; ///< Memory context restore control + ///< FALSE = perform memory init as normal (AMD default) + ///< TRUE = restore memory context and skip training. This requires + ///< MemContext is valid before AmdInitPost + ///< + IN BOOLEAN SaveMemContextCtl; ///< Control switch to save memory context at the end of MemAuto + ///< TRUE = AGESA will setup MemContext block before exit AmdInitPost + ///< FALSE = AGESA will not setup MemContext block. Platform is + ///< expected to call S3Save later in POST if it wants to + ///< use memory context restore feature. + ///< + IN OUT AMD_S3_PARAMS MemContext; ///< Memory context block describes the data that platform needs to + ///< save and restore for memory context restore feature to work. + ///< It uses the subset of S3Save block to save/restore. Hence platform + ///< may save only S3 block and uses it for both S3 resume and + ///< memory context restore. + ///< - If MemRestoreCtl is TRUE, platform needs to pass in MemContext + ///< before AmdInitPost. + ///< - If SaveMemContextCtl is TRUE, platform needs to save MemContext + ///< right after AmdInitPost. + ///< + IN BOOLEAN ExternalVrefCtl; ///< Control the use of external Vref + ///< TRUE = AGESA will use the function defined in "AGESA_EXTERNAL_VREF_CHANGE" in function list + ///< to change the vref + ///< FALSE = AGESA will will use the internal vref control. + ///< @BldCfgItem{BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE} + ///< + IN FORCE_TRAIN_MODE ForceTrainMode; ///< Training Mode + ///< 0 = Force 1D Training for all configurations + ///< 2 = Auto - AGESA will control 1D or 2D +} MEM_PARAMETER_STRUCT; + + +/// +/// Function definition. +/// This data structure passes function pointers to the memory configuration code. +/// The wrapper can use this structure with customized versions. +/// +typedef struct _MEM_FUNCTION_STRUCT { + + // PUBLIC required Internal functions + + IN OUT BOOLEAN (*amdMemGetPsCfgU) ( VOID *pMemData); ///< Proc for Unbuffered DIMMs, platform specific + IN OUT BOOLEAN (*amdMemGetPsCfgR) (VOID *pMemData); ///< Proc for Registered DIMMs, platform specific + + // PUBLIC optional functions + + IN OUT VOID (*amdMemEccInit) (VOID *pMemData); ///< NB proc for ECC feature + IN OUT VOID (*amdMemChipSelectInterleaveInit) (VOID *pMemData); ///< NB proc for CS interleave feature + IN OUT VOID (*amdMemDctInterleavingInit) (VOID *pMemData); ///< NB proc for Channel interleave feature + IN OUT VOID (*amdMemMctInterleavingInit) (VOID *pMemData); ///< NB proc for Node interleave feature + IN OUT VOID (*amdMemParallelTraining) (VOID *pMemData); ///< NB proc for parallel training feature + IN OUT VOID (*amdMemEarlySampleSupport) (VOID *pMemData); ///< NB code for early sample support feature + IN OUT VOID (*amdMemMultiPartInitSupport) (VOID *pMemData); ///< NB code for 'multi-part' + IN OUT VOID (*amdMemOnlineSpareSupport) (VOID *pMemData); ///< NB code for On-Line Spare feature + IN OUT VOID (*amdMemUDimmInit) (VOID *pMemData); ///< NB code for UDIMMs + IN OUT VOID (*amdMemRDimmInit) (VOID *pMemData); ///< NB code for RDIMMs + IN OUT VOID (*amdMemLrDimmInit) (VOID *pMemData); ///< NB code for LRDIMMs + IN OUT UINT32 Reserved[100]; ///< Reserved for later function definition +} MEM_FUNCTION_STRUCT; + +/// +/// Socket Structure +/// +/// +typedef struct _MEM_SOCKET_STRUCT { + OUT VOID *ChannelPtr[MAX_CHANNELS_PER_SOCKET]; ///< Pointers to each channels training data + + OUT VOID *TimingsPtr[MAX_CHANNELS_PER_SOCKET]; ///< Pointers to each channels timing data +} MEM_SOCKET_STRUCT; + +/// +/// Contains all data relevant to Memory Initialization. +/// +typedef struct _MEM_DATA_STRUCT { + IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + + IN MEM_PARAMETER_STRUCT *ParameterListPtr; ///< List of input Parameters + + OUT MEM_FUNCTION_STRUCT FunctionList; ///< List of function Pointers + + IN OUT AGESA_STATUS (*GetPlatformCfg[MAX_PLATFORM_TYPES]) (struct _MEM_DATA_STRUCT *MemData, UINT8 SocketID, CH_DEF_STRUCT *CurrentChannel); ///< look-up platform info + + IN OUT BOOLEAN (*ErrorHandling)(struct _DIE_STRUCT *MCTPtr, UINT8 DCT, UINT16 ChipSelMask, AMD_CONFIG_PARAMS *StdHeader); ///< Error Handling + + + OUT MEM_SOCKET_STRUCT SocketList[MAX_SOCKETS_SUPPORTED]; ///< Socket list for memory code. + ///< SocketList is a shortcut for IBVs to retrieve training + ///< and timing data for each channel indexed by socket/channel, + ///< eliminating their need to parse die/dct/channel etc. + ///< It contains pointers to the populated data structures for + ///< each channel and skips the channel structures that are + ///< unpopulated. In the case of channels sharing the same DCT, + ///< the pTimings pointers will point to the same DCT Timing data. + + OUT DIE_STRUCT *DiesPerSystem; ///< Pointed to an array of DIE_STRUCTs + OUT UINT8 DieCount; ///< Number of MCTs in the system. + + IN SPD_DEF_STRUCT *SpdDataStructure; ///< Pointer to SPD Data structure + + IN OUT struct _PLATFORM_CONFIGURATION *PlatFormConfig; ///< Platform profile/build option config structure + + IN OUT BOOLEAN IsFlowControlSupported; ///< Indicates if flow control is supported + + OUT UINT32 TscRate; ///< The rate at which the TSC increments in megahertz. + +} MEM_DATA_STRUCT; + +/// +/// Uma Structure +/// +/// +typedef struct _UMA_INFO { + OUT UINT64 UmaBase; ///< UmaBase[63:0] = Addr[63:0] + OUT UINT32 UmaSize; ///< UmaSize[31:0] = Addr[31:0] + OUT UINT32 UmaAttributes; ///< Indicate the attribute of Uma + OUT UINT8 UmaMode; ///< Indicate the mode of Uma + OUT UINT16 MemClock; ///< Indicate memory running speed in MHz + OUT UINT8 Reserved[3]; ///< Reserved for future usage +} UMA_INFO; + +/// Bitfield for ID +typedef struct { + OUT UINT16 SocketId:8; ///< Socket ID + OUT UINT16 ModuleId:8; ///< Module ID +} ID_FIELD; +/// +/// Union for ID of socket and module that will be passed out in call out +/// +typedef union { + OUT ID_FIELD IdField; ///< Bitfield for ID + OUT UINT16 IdInformation; ///< ID information for call out +} ID_INFO; + +// AGESA MEMORY ERRORS + +// AGESA_ALERT Memory Errors +#define MEM_ALERT_USER_TMG_MODE_OVERRULED 0x04010000ul ///< TIMING_MODE_SPECIFIC is requested but + ///< cannot be applied to current configurations. +#define MEM_ALERT_ORG_MISMATCH_DIMM 0x04010100ul ///< DIMM organization miss-match +#define MEM_ALERT_BK_INT_DIS 0x04010200ul ///< Bank interleaving disable for internal issue + +// AGESA_ERROR Memory Errors +#define MEM_ERROR_NO_DQS_POS_RD_WINDOW 0x04010300ul ///< No DQS Position window for RD DQS +#define MEM_ERROR_SMALL_DQS_POS_RD_WINDOW 0x04020300ul ///< Small DQS Position window for RD DQS +#define MEM_ERROR_NO_DQS_POS_WR_WINDOW 0x04030300ul ///< No DQS Position window for WR DQS +#define MEM_ERROR_SMALL_DQS_POS_WR_WINDOW 0x04040300ul ///< Small DQS Position window for WR DQS +#define MEM_ERROR_DIMM_SPARING_NOT_ENABLED 0x04010500ul ///< DIMM sparing has not been enabled for an internal issues +#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE 0x04050300ul ///< Receive Enable value is too large +#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW 0x04060300ul ///< There is no DQS receiver enable window +#define MEM_ERROR_DRAM_ENABLED_TIME_OUT 0x04010600ul ///< Time out when polling DramEnabled bit +#define MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT 0x04010700ul ///< Time out when polling DctAccessDone bit +#define MEM_ERROR_SEND_CTRL_WORD_TIME_OUT 0x04010800ul ///< Time out when polling SendCtrlWord bit +#define MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT 0x04010900ul ///< Time out when polling PrefDramTrainMode bit +#define MEM_ERROR_ENTER_SELF_REF_TIME_OUT 0x04010A00ul ///< Time out when polling EnterSelfRef bit +#define MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT 0x04010B00ul ///< Time out when polling FreqChgInProg bit +#define MEM_ERROR_EXIT_SELF_REF_TIME_OUT 0x04020A00ul ///< Time out when polling ExitSelfRef bit +#define MEM_ERROR_SEND_MRS_CMD_TIME_OUT 0x04010C00ul ///< Time out when polling SendMrsCmd bit +#define MEM_ERROR_SEND_ZQ_CMD_TIME_OUT 0x04010D00ul ///< Time out when polling SendZQCmd bit +#define MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT 0x04010E00ul ///< Time out when polling DctExtraAccessDone bit +#define MEM_ERROR_MEM_CLR_BUSY_TIME_OUT 0x04010F00ul ///< Time out when polling MemClrBusy bit +#define MEM_ERROR_MEM_CLEARED_TIME_OUT 0x04020F00ul ///< Time out when polling MemCleared bit +#define MEM_ERROR_FLUSH_WR_TIME_OUT 0x04011000ul ///< Time out when polling FlushWr bit +#define MEM_ERROR_NBPSTATE_TRANSITION_TIME_OUT 0x04012600ul ///< Time out when polling CurNBPstate bit +#define MEM_ERROR_MAX_LAT_NO_WINDOW 0x04070300ul ///< Fail to find pass during Max Rd Latency training +#define MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL 0x04080300ul ///< Fail to launch training code on an AP +#define MEM_ERROR_PARALLEL_TRAINING_TIME_OUT 0x04090300ul ///< Fail to finish parallel training +#define MEM_ERROR_NO_ADDRESS_MAPPING 0x04011100ul ///< No address mapping found for a dimm +#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT 0x040A0300ul ///< There is no DQS receiver enable window and the value is equal to the largest value +#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE 0x040B0300ul ///< Receive Enable value is too large and is 1 less than limit +#define MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR 0x04011200ul ///< SPD Checksum error for NV_SPDCHK_RESTRT +#define MEM_ERROR_NO_CHIPSELECT 0x04011300ul ///< No chipselects found +#define MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM 0x04011500ul ///< Unbuffered dimm is not supported at 333MHz +#define MEM_ERROR_WL_PRE_OUT_OF_RANGE 0x040C0300ul ///< Returned PRE value during write levelizzation was out of range +#define MEM_ERROR_LR_IBT_NOT_FOUND 0x04013500ul ///< No LR dimm IBT value is found +#define MEM_ERROR_MR0_NOT_FOUND 0x04023500ul ///< No MR0 value is found +#define MEM_ERROR_ODT_PATTERN_NOT_FOUND 0x04033500ul ///< No odt pattern value is found +#define MEM_ERROR_RC2_IBT_NOT_FOUND 0x04043500ul ///< No RC2 IBT value is found +#define MEM_ERROR_RC10_OP_SPEED_NOT_FOUND 0x04053500ul ///< No RC10 op speed is found +#define MEM_ERROR_RTT_NOT_FOUND 0x04063500ul ///< No RTT value is found +#define MEM_ERROR_P2D_NOT_FOUND 0x04073500ul ///< No 2D training config value is found +#define MEM_ERROR_SAO_NOT_FOUND 0x04083500ul ///< No slow access mode, Address timing and Output driver compensation value is found +#define MEM_ERROR_CLK_DIS_MAP_NOT_FOUND 0x04093500ul ///< No CLK disable map is found +#define MEM_ERROR_CKE_TRI_MAP_NOT_FOUND 0x040A3500ul ///< No CKE tristate map is found +#define MEM_ERROR_ODT_TRI_MAP_NOT_FOUND 0x040B3500ul ///< No ODT tristate map is found +#define MEM_ERROR_CS_TRI_MAP_NOT_FOUND 0x040C3500ul ///< No CS tristate map is found +#define MEM_ERROR_TRAINING_SEED_NOT_FOUND 0x040D3500ul ///< No training seed is found + +// AGESA_WARNING Memory Errors +#define MEM_WARNING_UNSUPPORTED_QRDIMM 0x04011600ul ///< QR DIMMs detected but not supported +#define MEM_WARNING_UNSUPPORTED_UDIMM 0x04021600ul ///< U DIMMs detected but not supported +#define MEM_WARNING_UNSUPPORTED_SODIMM 0x04031600ul ///< SO-DIMMs detected but not supported +#define MEM_WARNING_UNSUPPORTED_X4DIMM 0x04041600ul ///< x4 DIMMs detected but not supported +#define MEM_WARNING_UNSUPPORTED_RDIMM 0x04051600ul ///< R DIMMs detected but not supported +#define MEM_WARNING_UNSUPPORTED_LRDIMM 0x04061600ul ///< LR DIMMs detected but not supported +#define MEM_WARNING_EMP_NOT_SUPPORTED 0x04011700ul ///< Processor is not capable for EMP +#define MEM_WARNING_EMP_CONFLICT 0x04021700ul ///< EMP cannot be enabled if channel interleaving, +#define MEM_WARNING_EMP_NOT_ENABLED 0x04031700ul ///< Memory size is not power of two. +#define MEM_WARNING_ECC_DIS 0x04041700ul ///< ECC has been disabled as a result of an internal issue +#define MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED 0x04011800ul ///< Performance has been enabled, but battery life is preferred. + ///< bank interleaving, or bank swizzle is enabled. +#define MEM_WARNING_NO_SPDTRC_FOUND 0x04011900ul ///< No Trc timing value found in SPD of a dimm. +#define MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED 0x04012000ul ///< Node Interleaveing Requested, but could not be enabled +#define MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED 0x04012100ul ///< Channel Interleaveing Requested, but could not be enabled +#define MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED 0x04012200ul ///< Bank Interleaveing Requested, but could not be enabled +#define MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED 0x04012300ul ///< Voltage 1.35 determined, but could not be supported +#define MEM_WARNING_INITIAL_DDR3VOLT_NONZERO 0x04012400ul ///< DDR3 voltage initial value is not 0 +#define MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO 0x04012500ul ///< Cannot find a commonly supported VDDIO + +// AGESA_FATAL Memory Errors +#define MEM_ERROR_MINIMUM_MODE 0x04011A00ul ///< Running in minimum mode +#define MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM 0x04011B00ul ///< DIMM modules are miss-matched +#define MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM 0x04011C00ul ///< No DIMMs have been found +#define MEM_ERROR_MISMATCH_DIMM_CLOCKS 0x04011D00ul ///< DIMM clocks miss-matched +#define MEM_ERROR_NO_CYC_TIME 0x04011E00ul ///< No cycle time found +#define MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS 0x04011F00ul ///< Heap allocation error with dynamic storing of trained timings +#define MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs 0x04021F00ul ///< Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT +#define MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV 0x04031F00ul ///< Heap allocation error with REMOTE_TRAINING_ENV +#define MEM_ERROR_HEAP_ALLOCATE_FOR_SPD 0x04041F00ul ///< Heap allocation error for SPD data +#define MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA 0x04051F00ul ///< Heap allocation error for RECEIVED_DATA during parallel training +#define MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS 0x04061F00ul ///< Heap allocation error for S3 "SPECIAL_CASE_REGISTER" +#define MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA 0x04071F00ul ///< Heap allocation error for Training Data +#define MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK 0x04081F00ul ///< Heap allocation error for DIMM Identify "MEM_NB_BLOCK +#define MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM 0x04022300ul ///< No Constructor for DIMM Identify +#define MEM_ERROR_VDDIO_UNSUPPORTED 0x04022500ul ///< VDDIO of the dimms on the board is not supported +#define MEM_ERROR_HEAP_ALLOCATE_FOR_2D 0x040B1F00ul ///< Heap allocation error for 2D training data +#define MEM_ERROR_HEAP_DEALLOCATE_FOR_2D 0x040C1F00ul ///< Heap de-allocation error for 2D training data + +// AGESA_CRITICAL Memory Errors +#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3 0x04091F00ul ///< Heap allocation error for DMI table for DDR3 +#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2 0x040A1F00ul ///< Heap allocation error for DMI table for DDR2 +#define MEM_ERROR_UNSUPPORTED_DIMM_CONFIG 0x04011400ul ///< Dimm population is not supported +#define MEM_ERROR_HEAP_ALLOCATE_FOR_CRAT_MEM_AFFINITY 0x040D1F00ul ///< Heap allocation error for CRAT memory affinity info + + + +/*---------------------------------------------------------------------------- + * + * END OF MEMORY-SPECIFIC DATA STRUCTURES + * + *---------------------------------------------------------------------------- + */ + + + + +/*---------------------------------------------------------------------------- + * + * CPU RELATED DEFINITIONS + * + *---------------------------------------------------------------------------- + */ + +// CPU Event definitions. + +// Defines used to filter CPU events based on functional blocks +#define CPU_EVENT_PM_EVENT_MASK 0xFF00FF00ul +#define CPU_EVENT_PM_EVENT_CLASS 0x08000400ul + +//================================================================ +// CPU General events +// Heap allocation (AppFunction = 01h) +#define CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT 0x08000100ul +#define CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED 0x08010100ul +#define CPU_ERROR_HEAP_IS_FULL 0x08020100ul +#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED 0x08030100ul +#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT 0x08040100ul +// BrandId (AppFunction = 02h) +#define CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE 0x08000200ul +// Micro code patch (AppFunction = 03h) +#define CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED 0x08000300ul +// Power management (AppFunction = 04h) +#define CPU_EVENT_PM_PSTATE_OVERCURRENT 0x08000400ul +#define CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT 0x08010400ul +#define CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE 0x08020400ul +#define CPU_ERROR_PM_NB_PSTATE_MISMATCH 0x08030400ul +// Other CPU events (AppFunction = 05h) +#define CPU_EVENT_BIST_ERROR 0x08000500ul +#define CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY 0x08010500ul +#define CPU_EVENT_STACK_REENTRY 0x08020500ul +#define CPU_EVENT_CORE_NOT_IDENTIFIED 0x08030500ul + +//================================================================= +// CPU Feature events +// Execution cache (AppFunction = 21h) +// AGESA_CACHE_SIZE_REDUCED 2101 +// AGESA_CACHE_REGIONS_ACROSS_1MB 2102 +// AGESA_CACHE_REGIONS_ACROSS_4GB 2103 +// AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 2104 +// AGESA_CACHE_START_ADDRESS_LESS_D0000 2105 +// AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 2106 +// AGESA_DEALLOCATE_CACHE_REGIONS 2107 +#define CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR 0x08002100ul +// Core Leveling (AppFunction = 22h) +#define CPU_WARNING_ADJUSTED_LEVELING_MODE 0x08002200ul +// HT Assist (AppFunction = 23h) +#define CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG 0x08002300ul + +// CPU Build Configuration structures and definitions + +/// Build Configuration structure for BLDCFG_AP_MTRR_SETTINGS +typedef struct { + IN UINT32 MsrAddr; ///< Fixed-Sized MTRR address + IN UINT64 MsrData; ///< MTRR Settings +} AP_MTRR_SETTINGS; + +#define AMD_AP_MTRR_FIX64k_00000 0x00000250ul +#define AMD_AP_MTRR_FIX16k_80000 0x00000258ul +#define AMD_AP_MTRR_FIX16k_A0000 0x00000259ul +#define AMD_AP_MTRR_FIX4k_C0000 0x00000268ul +#define AMD_AP_MTRR_FIX4k_C8000 0x00000269ul +#define AMD_AP_MTRR_FIX4k_D0000 0x0000026Aul +#define AMD_AP_MTRR_FIX4k_D8000 0x0000026Bul +#define AMD_AP_MTRR_FIX4k_E0000 0x0000026Cul +#define AMD_AP_MTRR_FIX4k_E8000 0x0000026Dul +#define AMD_AP_MTRR_FIX4k_F0000 0x0000026Eul +#define AMD_AP_MTRR_FIX4k_F8000 0x0000026Ful +#define CPU_LIST_TERMINAL 0xFFFFFFFFul + +/// Data structure for the Mapping Item between Unified ID for IDS Setup Option +/// and the option value. +/// +typedef struct { + IN UINT16 IdsNvId; ///< Unified ID for IDS Setup Option. + OUT UINT16 IdsNvValue; ///< The value of IDS Setup Option. +} IDS_NV_ITEM; + +/// Data Structure for IDS CallOut Function +typedef struct { + IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN IDS_NV_ITEM *IdsNvPtr; ///< Memory Pointer of IDS NV Table + IN OUT UINTN Reserved; ///< reserved +} IDS_CALLOUT_STRUCT; + +/************************************************************************ + * + * AGESA interface Call-Out function parameter structures + * + ***********************************************************************/ + +/// Parameters structure for interface call-out AgesaAllocateBuffer +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN OUT UINT32 BufferLength; ///< Size of buffer to allocate + IN UINT32 BufferHandle; ///< Identifier or name for the buffer + OUT VOID *BufferPointer; ///< location of the created buffer +} AGESA_BUFFER_PARAMS; + +/// Parameters structure for interface call-out AgesaRunCodeOnAp +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN UINT32 FunctionNumber; ///< Index of the procedure to execute + IN VOID *RelatedDataBlock; ///< Location of data structure the procedure will use + IN UINT32 RelatedBlockLength; ///< Size of the related data block +} AP_EXE_PARAMS; + +/// Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN UINT8 SocketId; ///< Address of SPD - socket ID + IN UINT8 MemChannelId; ///< Address of SPD - memory channel ID + IN UINT8 DimmId; ///< Address of SPD - DIMM ID + IN OUT UINT8 *Buffer; ///< Location where to place the SPD content + IN OUT MEM_DATA_STRUCT *MemData; ///< Location of the MemData structure, for reference +} AGESA_READ_SPD_PARAMS; + +/// Buffer Handles +typedef enum { + AMD_DMI_INFO_BUFFER_HANDLE = 0x000D000, ///< Assign 0x000D000 buffer handle to DMI function + AMD_PSTATE_DATA_BUFFER_HANDLE, ///< Assign 0x000D001 buffer handle to Pstate data + AMD_PSTATE_ACPI_BUFFER_HANDLE, ///< Assign 0x000D002 buffer handle to Pstate table + AMD_BRAND_ID_BUFFER_HANDLE, ///< Assign 0x000D003 buffer handle to Brand ID + AMD_ACPI_SLIT_BUFFER_HANDLE, ///< Assign 0x000D004 buffer handle to SLIT function + AMD_SRAT_INFO_BUFFER_HANDLE, ///< Assign 0x000D005 buffer handle to SRAT function + AMD_WHEA_BUFFER_HANDLE, ///< Assign 0x000D006 buffer handle to WHEA function + AMD_S3_INFO_BUFFER_HANDLE, ///< Assign 0x000D007 buffer handle to S3 function + AMD_S3_NB_INFO_BUFFER_HANDLE, ///< Assign 0x000D008 buffer handle to S3 NB device info + AMD_ACPI_ALIB_BUFFER_HANDLE, ///< Assign 0x000D009 buffer handle to ALIB SSDT table + AMD_ACPI_IVRS_BUFFER_HANDLE, ///< Assign 0x000D00A buffer handle to IOMMU IVRS table + AMD_CRAT_INFO_BUFFER_HANDLE, ///< Assign 0x000D00B buffer handle to CRAT function + AMD_ACPI_CDIT_BUFFER_HANDLE ///< Assign 0x000D00C buffer handle to CDIT function +} AMD_BUFFER_HANDLE; + + +/************************************************************************ + * + * AGESA interface Call-Out function prototypes + * + ***********************************************************************/ + +VOID +AgesaDoReset ( + IN UINTN ResetType, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +AgesaAllocateBuffer ( + IN UINTN FcnData, + IN OUT AGESA_BUFFER_PARAMS *AllocParams + ); + +AGESA_STATUS +AgesaDeallocateBuffer ( + IN UINTN FcnData, + IN OUT AGESA_BUFFER_PARAMS *DeallocParams + ); + +AGESA_STATUS +AgesaLocateBuffer ( + IN UINTN FcnData, + IN OUT AGESA_BUFFER_PARAMS *LocateParams + ); + +AGESA_STATUS +AgesaReadSpd ( + IN UINTN FcnData, + IN OUT AGESA_READ_SPD_PARAMS *ReadSpd + ); + +AGESA_STATUS +AgesaReadSpdRecovery ( + IN UINTN FcnData, + IN OUT AGESA_READ_SPD_PARAMS *ReadSpd + ); + +AGESA_STATUS +AgesaHookBeforeDramInitRecovery ( + IN UINTN FcnData, + IN OUT MEM_DATA_STRUCT *MemData + ); + +AGESA_STATUS +AgesaRunFcnOnAp ( + IN UINTN ApicIdOfCore, + IN AP_EXE_PARAMS *LaunchApParams + ); + +AGESA_STATUS +AgesaHookBeforeDramInit ( + IN UINTN SocketIdModuleId, + IN OUT MEM_DATA_STRUCT *MemData + ); + +AGESA_STATUS +AgesaHookBeforeDQSTraining ( + IN UINTN SocketIdModuleId, + IN OUT MEM_DATA_STRUCT *MemData + ); + +AGESA_STATUS +AgesaHookBeforeExitSelfRefresh ( + IN UINTN FcnData, + IN OUT MEM_DATA_STRUCT *MemData + ); + +AGESA_STATUS +AgesaPcieSlotResetControl ( + IN UINTN FcnData, + IN PCIe_SLOT_RESET_INFO *ResetInfo + ); + +AGESA_STATUS +AgesaGetVbiosImage ( + IN UINTN FcnData, + IN OUT GFX_VBIOS_IMAGE_INFO *VbiosImageInfo + ); + +AGESA_STATUS +AgesaFchOemCallout ( + IN VOID *FchData + ); + +AGESA_STATUS +excel331 ( + IN UINTN SocketIdModuleId, + IN OUT MEM_DATA_STRUCT *MemData + ); + +AGESA_STATUS +AgesaGetIdsData ( + IN UINTN Data, + IN OUT IDS_CALLOUT_STRUCT *IdsCalloutData + ); +/************************************************************************ + * + * AGESA interface structure definition and function prototypes + * + ***********************************************************************/ + +/********************************************************************** + * Platform Configuration: The parameters in boot branch function + **********************************************************************/ + +/// The possible platform control flow settings. +typedef enum { + Nfcm, ///< Normal Flow Control Mode. + UmaDr, ///< UMA using Display Refresh flow control. + UmaIfcm, ///< UMA using Isochronous Flow Control. + Ifcm, ///< Isochronous Flow Control Mode (other than for UMA). + Iommu, ///< An IOMMU is in use in the system. + MaxControlFlow ///< Not a control flow mode, use for limit checking. +} PLATFORM_CONTROL_FLOW; + +/// Platform Deemphasis Levels. +/// +/// The deemphasis level is set for the receiver, based on link characterization. The DCV level is +/// set based on the level of the far transmitter. +typedef enum { + DeemphasisLevelNone, ///< No Deemphasis. + DeemphasisLevelMinus3, ///< Minus 3 db deemphasis. + DeemphasisLevelMinus6, ///< Minus 6 db deemphasis. + DeemphasisLevelMinus8, ///< Minus 8 db deemphasis. + DeemphasisLevelMinus11, ///< Minus 11 db deemphasis. + DeemphasisLevelMinus11pre8, ///< Minus 11, Minus 8 precursor db deemphasis. + DcvLevelNone = 16, ///< No DCV Deemphasis. + DcvLevelMinus2, ///< Minus 2 db DCV deemphasis. + DcvLevelMinus3, ///< Minus 3 db DCV deemphasis. + DcvLevelMinus5, ///< Minus 5 db DCV deemphasis. + DcvLevelMinus6, ///< Minus 6 db DCV deemphasis. + DcvLevelMinus7, ///< Minus 7 db DCV deemphasis. + DcvLevelMinus8, ///< Minus 8 db DCV deemphasis. + DcvLevelMinus9, ///< Minus 9 db DCV deemphasis. + DcvLevelMinus11, ///< Minus 11 db DCV deemphasis. + MaxPlatformDeemphasisLevel ///< Not a deemphasis level, use for limit checking. +} PLATFORM_DEEMPHASIS_LEVEL; + +/// Provide Deemphasis Levels for HT Links. +/// +/// For each CPU to CPU or CPU to IO device HT link, the list of Deemphasis Levels will +/// be checked for a match. The item matches for a Socket, Link if the link frequency is +/// is in the inclusive range HighFreq:LoFreq. +/// AGESA does not set deemphasis in IO devices, only in processors. + +typedef struct { + // Match fields + IN UINT8 Socket; ///< One Socket on which this Link is located + IN UINT8 Link; ///< The Link on this Processor. + IN UINT8 LoFreq; ///< If the link is set to this frequency or greater, apply these levels, and + IN UINT8 HighFreq; ///< If the link is set to this frequency or less, apply these levels. + // Value fields + IN PLATFORM_DEEMPHASIS_LEVEL ReceiverDeemphasis; ///< The deemphasis level for this link + IN PLATFORM_DEEMPHASIS_LEVEL DcvDeemphasis; ///< The DCV, or far transmitter deemphasis level. +} CPU_HT_DEEMPHASIS_LEVEL; + + +/// The possible hardware prefetch mode settings. +typedef enum { + HARDWARE_PREFETCHER_AUTO, ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled. + DISABLE_L1_PREFETCHER, ///< Use the recommended settings for the hardware prefetcher, but disable L1 prefetching. + DISABLE_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES, ///< Use the recommended setting for the hardware prefetcher, but disable training on software prefetches. + DISABLE_L1_PREFETCHER_AND_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES, ///< Use the recommended settings for the hardware prefetcher, but disable both the L1 prefetcher and training on software prefetches. + DISABLE_HARDWARE_PREFETCH, ///< Disable hardware prefetching. + MAX_HARDWARE_PREFETCH_MODE ///< Not a hardware prefetch mode, use for limit checking. +} HARDWARE_PREFETCH_MODE; + +/// The possible software prefetch mode settings. +typedef enum { + SOFTWARE_PREFETCHES_AUTO, ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled. + DISABLE_SOFTWARE_PREFETCHES, ///< Disable software prefetches (convert software prefetch instructions to NOP). + MAX_SOFTWARE_PREFETCH_MODE ///< Not a software prefetch mode, use for limit checking. +} SOFTWARE_PREFETCH_MODE; + +/// Advanced performance tunings, prefetchers. +/// These settings provide for performance tuning to optimize for specific workloads. +typedef struct { + IN HARDWARE_PREFETCH_MODE HardwarePrefetchMode; ///< This value provides for advanced performance tuning by controlling the hardware prefetcher setting. + IN SOFTWARE_PREFETCH_MODE SoftwarePrefetchMode; ///< This value provides for advanced performance tuning by controlling the software prefetch instructions. + IN DRAM_PREFETCH_MODE DramPrefetchMode; ///< This value provides for advanced performance tuning by controlling the DRAM prefetcher setting. +} ADVANCED_PERFORMANCE_PROFILE; + +/// The possible platform power policy settings. +typedef enum { + Performance, ///< Optimize for performance. + BatteryLife, ///< Optimize for battery life. + MaxPowerPolicy ///< Not a power policy mode, use for limit checking. +} PLATFORM_POWER_POLICY; + +/// Platform performance settings for optimized settings. +/// Several configuration settings for the processor depend upon other parts and +/// general designer choices for the system. The determination of these data points +/// is not standard for all platforms, so the host environment needs to provide these +/// to specify how the system is to be configured. +typedef struct { + IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode; ///< The platform's control flow mode for optimum platform performance. + ///< @BldCfgItem{BLDCFG_PLATFORM_CONTROL_FLOW_MODE} + IN BOOLEAN UseHtAssist; ///< HyperTransport link traffic optimization. + ///< @BldCfgItem{BLDCFG_USE_HT_ASSIST} + IN BOOLEAN UseAtmMode; ///< HyperTransport link traffic optimization. + ///< @BldCfgItem{BLDCFG_USE_ATM_MODE} + IN BOOLEAN Use32ByteRefresh; ///< Display Refresh traffic generates 32 byte requests. + ///< @BldCfgItem{BLDCFG_USE_32_BYTE_REFRESH} + IN BOOLEAN UseVariableMctIsocPriority; ///< The Memory controller will be set to Variable Isoc Priority. + ///< @BldCfgItem{BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY} + IN ADVANCED_PERFORMANCE_PROFILE AdvancedPerformanceProfile; ///< The advanced platform performance settings. + IN PLATFORM_POWER_POLICY PlatformPowerPolicy; ///< The platform's desired power policy + ///< @BldCfgItem{BLDCFG_PLATFORM_POWER_POLICY_MODE} +} PERFORMANCE_PROFILE; + +/// Platform settings that describe the voltage regulator modules of the system. +/// Many power management settings are dependent upon the characteristics of the +/// on-board voltage regulator module (VRM). The host environment needs to provide +/// these to specify how the system is to be configured. +typedef struct { + IN UINT32 CurrentLimit; ///< Vrm Current Limit. + ///< @BldCfgItem{BLDCFG_VRM_CURRENT_LIMIT} + ///< @BldCfgItem{BLDCFG_VRM_NB_CURRENT_LIMIT} + IN UINT32 LowPowerThreshold; ///< Vrm Low Power Threshold. + ///< @BldCfgItem{BLDCFG_VRM_LOW_POWER_THRESHOLD} + ///< @BldCfgItem{BLDCFG_VRM_NB_LOW_POWER_THRESHOLD} + IN UINT32 SlewRate; ///< Vrm Slew Rate. + ///< @BldCfgItem{BLDCFG_VRM_SLEW_RATE} + ///< @BldCfgItem{BLDCFG_VRM_NB_SLEW_RATE} + IN UINT32 AdditionalDelay; ///< Vrm Additional Delay. + ///< @BldCfgItem{BLDCFG_VRM_ADDITIONAL_DELAY} + ///< @BldCfgItem{BLDCFG_VRM_NB_ADDITIONAL_DELAY} + IN BOOLEAN HiSpeedEnable; ///< Select high speed VRM. + ///< @BldCfgItem{BLDCFG_VRM_HIGH_SPEED_ENABLE} + ///< @BldCfgItem{BLDCFG_VRM_NB_HIGH_SPEED_ENABLE} + IN UINT32 InrushCurrentLimit; ///< Vrm Inrush Current Limit. + ///< @BldCfgItem{BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT} + ///< @BldCfgItem{BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT} + IN UINT32 SviOcpLevel; ///< SVI OCP Level. + ///< @BldCfgItem{BLDCFG_VRM_SVI_OCP_LEVEL} + ///< @BldCfgItem{BLDCFG_VRM_NB_SVI_OCP_LEVEL} +} PLATFORM_VRM_CONFIGURATION; + +/// The VRM types to characterize. +typedef enum { + CoreVrm, ///< VDD plane. + NbVrm, ///< VDDNB plane. + MaxVrmType ///< Not a valid VRM type, use for limit checking. +} PLATFORM_VRM_TYPE; + + +/// FCH Platform Configuration Policy +typedef struct { + IN UINT16 CfgSmbus0BaseAddress; ///< SMBUS0 Controller Base Address + IN UINT16 CfgSmbus1BaseAddress; ///< SMBUS1 Controller Base Address + IN UINT16 CfgSioPmeBaseAddress; ///< I/O base address for LPC I/O target range + IN UINT16 CfgAcpiPm1EvtBlkAddr; ///< I/O base address of ACPI power management Event Block + IN UINT16 CfgAcpiPm1CntBlkAddr; ///< I/O base address of ACPI power management Control Block + IN UINT16 CfgAcpiPmTmrBlkAddr; ///< I/O base address of ACPI power management Timer Block + IN UINT16 CfgCpuControlBlkAddr; ///< I/O base address of ACPI power management CPU Control Block + IN UINT16 CfgAcpiGpe0BlkAddr; ///< I/O base address of ACPI power management General Purpose Event Block + IN UINT16 CfgSmiCmdPortAddr; ///< I/O base address of ACPI SMI Command Block + IN UINT16 CfgAcpiPmaCntBlkAddr; ///< I/O base address of ACPI power management additional control block + IN UINT32 CfgGecShadowRomBase; ///< 32-bit base address to the GEC shadow ROM + IN UINT32 CfgWatchDogTimerBase; ///< Watchdog Timer base address + IN UINT32 CfgSpiRomBaseAddress; ///< Base address for the SPI ROM controller + IN UINT32 CfgHpetBaseAddress; ///< HPET MMIO base address + IN UINT32 CfgAzaliaSsid; ///< Subsystem ID of HD Audio controller + IN UINT32 CfgSmbusSsid; ///< Subsystem ID of SMBUS controller + IN UINT32 CfgIdeSsid; ///< Subsystem ID of IDE controller + IN UINT32 CfgSataAhciSsid; ///< Subsystem ID of SATA controller in AHCI mode + IN UINT32 CfgSataIdeSsid; ///< Subsystem ID of SATA controller in IDE mode + IN UINT32 CfgSataRaid5Ssid; ///< Subsystem ID of SATA controller in RAID5 mode + IN UINT32 CfgSataRaidSsid; ///< Subsystem ID of SATA controller in RAID mode + IN UINT32 CfgEhciSsid; ///< Subsystem ID of EHCI + IN UINT32 CfgOhciSsid; ///< Subsystem ID of OHCI + IN UINT32 CfgLpcSsid; ///< Subsystem ID of LPC ISA Bridge + IN UINT32 CfgSdSsid; ///< Subsystem ID of SecureDigital controller + IN UINT32 CfgXhciSsid; ///< Subsystem ID of XHCI + IN BOOLEAN CfgFchPort80BehindPcib; ///< Is port80 cycle going to the PCI bridge + IN BOOLEAN CfgFchEnableAcpiSleepTrap; ///< ACPI sleep SMI enable/disable + IN GPP_LINKMODE CfgFchGppLinkConfig; ///< GPP link configuration + IN BOOLEAN CfgFchGppPort0Present; ///< Is FCH GPP port 0 present + IN BOOLEAN CfgFchGppPort1Present; ///< Is FCH GPP port 1 present + IN BOOLEAN CfgFchGppPort2Present; ///< Is FCH GPP port 2 present + IN BOOLEAN CfgFchGppPort3Present; ///< Is FCH GPP port 3 present + IN BOOLEAN CfgFchGppPort0HotPlug; ///< Is FCH GPP port 0 hotplug capable + IN BOOLEAN CfgFchGppPort1HotPlug; ///< Is FCH GPP port 1 hotplug capable + IN BOOLEAN CfgFchGppPort2HotPlug; ///< Is FCH GPP port 2 hotplug capable + IN BOOLEAN CfgFchGppPort3HotPlug; ///< Is FCH GPP port 3 hotplug capable + + IN UINT8 CfgFchEsataPortBitMap; ///< ESATA Port definition, eg: [0]=1, means port 0 is ESATA capable + IN UINT8 CfgFchIrPinControl; ///< Register bitfield describing Infrared Pin Control: + ///< [0] - IR Enable 0 + ///< [1] - IR Enable 1 + ///< [2] - IR Tx0 + ///< [3] - IR Tx1 + ///< [4] - IR Open Drain + ///< [5] - IR Enable LED + IN SD_CLOCK_CONTROL CfgFchSdClockControl; ///< FCH SD Clock Control + IN SCI_MAP_CONTROL *CfgFchSciMapControl; ///< FCH SCI Mapping Control + IN SATA_PHY_CONTROL *CfgFchSataPhyControl; ///< FCH SATA PHY Control + IN GPIO_CONTROL *CfgFchGpioControl; ///< FCH GPIO Control +} FCH_PLATFORM_POLICY; + + +/// Build Option/Configuration Boolean Structure. +typedef struct { + IN AMD_CODE_HEADER VersionString; ///< AMD embedded code version string + + //Build Option Area + IN BOOLEAN OptionUDimms; ///< @ref BLDOPT_REMOVE_UDIMMS_SUPPORT "BLDOPT_REMOVE_UDIMMS_SUPPORT" + IN BOOLEAN OptionRDimms; ///< @ref BLDOPT_REMOVE_RDIMMS_SUPPORT "BLDOPT_REMOVE_RDIMMS_SUPPORT" + IN BOOLEAN OptionLrDimms; ///< @ref BLDOPT_REMOVE_LRDIMMS_SUPPORT "BLDOPT_REMOVE_LRDIMMS_SUPPORT" + IN BOOLEAN OptionEcc; ///< @ref BLDOPT_REMOVE_ECC_SUPPORT "BLDOPT_REMOVE_ECC_SUPPORT" + IN BOOLEAN OptionBankInterleave; ///< @ref BLDOPT_REMOVE_BANK_INTERLEAVE "BLDOPT_REMOVE_BANK_INTERLEAVE" + IN BOOLEAN OptionDctInterleave; ///< @ref BLDOPT_REMOVE_DCT_INTERLEAVE "BLDOPT_REMOVE_DCT_INTERLEAVE" + IN BOOLEAN OptionNodeInterleave; ///< @ref BLDOPT_REMOVE_NODE_INTERLEAVE "BLDOPT_REMOVE_NODE_INTERLEAVE" + IN BOOLEAN OptionParallelTraining; ///< @ref BLDOPT_REMOVE_PARALLEL_TRAINING "BLDOPT_REMOVE_PARALLEL_TRAINING" + IN BOOLEAN OptionOnlineSpare; ///< @ref BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT "BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT" + IN BOOLEAN OptionMemRestore; ///< @ref BLDOPT_REMOVE_MEM_RESTORE_SUPPORT "BLDOPT_REMOVE_MEM_RESTORE_SUPPORT" + IN BOOLEAN OptionMultisocket; ///< @ref BLDOPT_REMOVE_MULTISOCKET_SUPPORT "BLDOPT_REMOVE_MULTISOCKET_SUPPORT" + IN BOOLEAN OptionAcpiPstates; ///< @ref BLDOPT_REMOVE_ACPI_PSTATES "BLDOPT_REMOVE_ACPI_PSTATES" + IN BOOLEAN OptionPStatesInHpcMode; ///< @ref BLDCFG_PSTATE_HPC_MODE "BLDCFG_PSTATE_HPC_MODE" + IN BOOLEAN OptionCrat; ///< @ref BLDOPT_REMOVE_CRAT "BLDOPT_REMOVE_CRAT" + IN BOOLEAN OptionCdit; ///< @ref BLDOPT_REMOVE_CDIT "BLDOPT_REMOVE_CDIT" + IN BOOLEAN OptionSrat; ///< @ref BLDOPT_REMOVE_SRAT "BLDOPT_REMOVE_SRAT" + IN BOOLEAN OptionSlit; ///< @ref BLDOPT_REMOVE_SLIT "BLDOPT_REMOVE_SLIT" + IN BOOLEAN OptionWhea; ///< @ref BLDOPT_REMOVE_WHEA "BLDOPT_REMOVE_WHEA" + IN BOOLEAN OptionDmi; ///< @ref BLDOPT_REMOVE_DMI "BLDOPT_REMOVE_DMI" + IN BOOLEAN OptionEarlySamples; ///< @ref BLDOPT_REMOVE_EARLY_SAMPLES "BLDOPT_REMOVE_EARLY_SAMPLES" + IN BOOLEAN OptionAddrToCsTranslator; ///< ADDR_TO_CS_TRANSLATOR + + //Build Configuration Area + IN UINT64 CfgPciMmioAddress; ///< Pci Mmio Base Address to use for PCI Config accesses. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_BASE} + IN UINT32 CfgPciMmioSize; ///< Pci Mmio region Size. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_SIZE} + IN PLATFORM_VRM_CONFIGURATION CfgPlatVrmCfg[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules. + IN UINT32 CfgPlatNumIoApics; ///< The number of IO APICS for the platform. + IN UINT32 CfgMemInitPstate; ///< Memory Init Pstate. + IN PLATFORM_C1E_MODES CfgPlatformC1eMode; ///< Select the C1e Mode that will used. + IN UINT32 CfgPlatformC1eOpData; ///< An IO port or additional C1e setup data, depends on C1e mode. + IN UINT32 CfgPlatformC1eOpData1; ///< An IO port or additional C1e setup data, depends on C1e mode. + IN UINT32 CfgPlatformC1eOpData2; ///< An IO port or additional C1e setup data, depends on C1e mode. + IN UINT32 CfgPlatformC1eOpData3; ///< An IO port or additional C1e setup data, depends on C1e mode. + IN PLATFORM_CSTATE_MODES CfgPlatformCStateMode; ///< Select the C-State Mode that will used. + IN UINT32 CfgPlatformCStateOpData; ///< An IO port or additional C-State setup data, depends on C-State mode. + IN UINT16 CfgPlatformCStateIoBaseAddress; ///< Specifies I/O ports that can be used to allow CPU to enter CStates + IN PLATFORM_CPB_MODES CfgPlatformCpbMode; ///< Enable or disable core performance boost + IN PLATFORM_LOW_POWER_PSTATE_MODES CfgLowPowerPstateForProcHot; ///< Low power Pstate for PROCHOT mode + IN UINT32 CfgCoreLevelingMode; ///< Apply any downcoring or core count leveling as specified. + IN PERFORMANCE_PROFILE CfgPerformanceProfile; ///< The platform's control flow mode and platform performance settings. + IN CPU_HT_DEEMPHASIS_LEVEL *CfgPlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links. + + IN UINT32 CfgAmdPlatformType; ///< Designate the platform as a Server, Desktop, or Mobile. + IN UINT32 CfgAmdPstateCapValue; ///< Amd pstate ceiling enabling deck + + IN MEMORY_BUS_SPEED CfgMemoryBusFrequencyLimit; ///< Memory Bus Frequency Limit. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT} + IN BOOLEAN CfgMemoryModeUnganged; ///< Memory Mode Unganged. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_MODE_UNGANGED} + IN BOOLEAN CfgMemoryQuadRankCapable; ///< Memory Quad Rank Capable. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUAD_RANK_CAPABLE} + IN QUANDRANK_TYPE CfgMemoryQuadrankType; ///< Memory Quadrank Type. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUADRANK_TYPE} + IN BOOLEAN CfgMemoryRDimmCapable; ///< Memory RDIMM Capable. + IN BOOLEAN CfgMemoryLRDimmCapable; ///< Memory LRDIMM Capable. + IN BOOLEAN CfgMemoryUDimmCapable; ///< Memory UDIMM Capable. + IN BOOLEAN CfgMemorySODimmCapable; ///< Memory SODimm Capable. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_SODIMM_CAPABLE} + IN BOOLEAN CfgLimitMemoryToBelow1Tb; ///< Limit memory address space to below 1TB + IN BOOLEAN CfgMemoryEnableBankInterleaving; ///< Memory Enable Bank Interleaving. + IN BOOLEAN CfgMemoryEnableNodeInterleaving; ///< Memory Enable Node Interleaving. + IN BOOLEAN CfgMemoryChannelInterleaving; ///< Memory Channel Interleaving. + IN BOOLEAN CfgMemoryPowerDown; ///< Memory Power Down. + IN POWER_DOWN_MODE CfgPowerDownMode; ///< Power Down Mode. + IN BOOLEAN CfgOnlineSpare; ///< Online Spare. + IN BOOLEAN CfgMemoryParityEnable; ///< Memory Parity Enable. + IN BOOLEAN CfgBankSwizzle; ///< Bank Swizzle. + IN USER_MEMORY_TIMING_MODE CfgTimingModeSelect; ///< Timing Mode Select. + IN MEMORY_BUS_SPEED CfgMemoryClockSelect; ///< Memory Clock Select. + IN BOOLEAN CfgDqsTrainingControl; ///< Dqs Training Control. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_DQS_TRAINING_CONTROL} + IN BOOLEAN CfgIgnoreSpdChecksum; ///< Ignore Spd Checksum. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGNORE_SPD_CHECKSUM} + IN BOOLEAN CfgUseBurstMode; ///< Use Burst Mode. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_USE_BURST_MODE} + IN BOOLEAN CfgMemoryAllClocksOn; ///< Memory All Clocks On. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_ALL_CLOCKS_ON} + IN BOOLEAN CfgEnableEccFeature; ///< Enable ECC Feature. + IN BOOLEAN CfgEccRedirection; ///< ECC Redirection. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_REDIRECTION} + IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DRAM_RATE} + IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L2_RATE} + IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L3_RATE} + IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_IC_RATE} + IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DC_RATE} + IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYNC_FLOOD} + IN UINT16 CfgEccSymbolSize; ///< ECC Symbol Size. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYMBOL_SIZE} + IN UINT64 CfgHeapDramAddress; ///< Heap contents will be temporarily stored in this address during the transition. + ///< Build-time customizable only - @BldCfgItem{BLDCFG_HEAP_DRAM_ADDRESS} + IN BOOLEAN CfgNodeMem1GBAlign; ///< Node Mem 1GB boundary Alignment + IN BOOLEAN CfgS3LateRestore; ///< S3 Late Restore + IN BOOLEAN CfgAcpiPstateIndependent; ///< PSD method dependent/Independent + IN AP_MTRR_SETTINGS *CfgApMtrrSettingsList; ///< The AP's MTRR settings before final halt + ///< Build-time customizable only - @BldCfgItem{BLDCFG_AP_MTRR_SETTINGS_LIST} + IN UMA_MODE CfgUmaMode; ///< Uma Mode + IN UINT32 CfgUmaSize; ///< Uma Size [31:0]=Addr[47:16] + IN BOOLEAN CfgUmaAbove4G; ///< Uma Above 4G Support + IN UMA_ALIGNMENT CfgUmaAlignment; ///< Uma alignment + IN BOOLEAN CfgProcessorScopeInSb; ///< ACPI Processor Object in \_SB scope + IN CHAR8 CfgProcessorScopeName0; ///< OEM specific 1st character of processor scope name. + IN CHAR8 CfgProcessorScopeName1; ///< OEM specific 2nd character of processor scope name. + IN UINT8 CfgGnbHdAudio; ///< GNB HD Audio + IN UINT8 CfgAbmSupport; ///< Abm Support + IN UINT8 CfgDynamicRefreshRate; ///< DRR Dynamic Refresh Rate + IN UINT16 CfgLcdBackLightControl; ///< LCD Backlight Control + IN UINT8 CfgGnb3dStereoPinIndex; ///< 3D Stereo Pin ID. + IN UINT32 CfgTempPcieMmioBaseAddress; ///< Temp pcie MMIO base Address + ///< Build-time customizable only - @BldCfgItem{BLDCFG_TEMP_PCIE_MMIO_BASE_ADDRESS} + IN UINT32 CfgGnbIGPUSSID; ///< Gnb internal GPU SSID + ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_SUBSYSTEM_ID} + IN UINT32 CfgGnbHDAudioSSID; ///< Gnb HD Audio SSID + ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID} + IN UINT32 CfgGnbPcieSSID; ///< Gnb PCIe SSID + ///< Build-time customizable only - @BldCfgItem{BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID} + IN UINT16 CfgLvdsSpreadSpectrum; ///< Lvds Spread Spectrum + ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM} + IN UINT16 CfgLvdsSpreadSpectrumRate; ///< Lvds Spread Spectrum Rate + ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE} + IN FCH_PLATFORM_POLICY *FchBldCfg; ///< FCH platform build configuration policy + + IN BOOLEAN CfgIommuSupport; ///< IOMMU support + IN UINT8 CfgLvdsPowerOnSeqDigonToDe; ///< Panel initialization timing + IN UINT8 CfgLvdsPowerOnSeqDeToVaryBl; ///< Panel initialization timing + IN UINT8 CfgLvdsPowerOnSeqDeToDigon; ///< Panel initialization timing + IN UINT8 CfgLvdsPowerOnSeqVaryBlToDe; ///< Panel initialization timing + IN UINT8 CfgLvdsPowerOnSeqOnToOffDelay; ///< Panel initialization timing + IN UINT8 CfgLvdsPowerOnSeqVaryBlToBlon; ///< Panel initialization timing + IN UINT8 CfgLvdsPowerOnSeqBlonToVaryBl; ///< Panel initialization timing + IN UINT16 CfgLvdsMaxPixelClockFreq; ///< The maximum pixel clock frequency supported + IN UINT32 CfgLcdBitDepthControlValue; ///< The LCD bit depth control settings + IN UINT8 CfgLvds24bbpPanelMode; ///< The LVDS 24 BBP mode + IN LVDS_MISC_CONTROL CfgLvdsMiscControl; ///< THe LVDS Misc control + IN UINT16 CfgPcieRefClkSpreadSpectrum; ///< PCIe Reference Clock Spread Spectrum + ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM} + IN BOOLEAN CfgExternalVrefCtlFeature; ///< External Vref control + IN FORCE_TRAIN_MODE CfgForceTrainMode; ///< Force Train Mode + IN BOOLEAN CfgGnbRemoteDisplaySupport; ///< Wireless Display Support + IN IOMMU_EXCLUSION_RANGE_DESCRIPTOR *CfgIvrsExclusionRangeList; + IN BOOLEAN CfgGnbSyncFloodPinAsNmi; ///< @ref BLDCFG_USE_SYNCFLOOD_AS_NMI "BLDCFG_USE_SYNCFLOOD_AS_NMI" + IN UINT8 CfgIgpuEnableDisablePolicy; ///< This item defines the iGPU Enable/Disable policy + ///< @li 0 = Auto - use current default + ///< @li 2 = Disable iGPU if ANY PCI or PCIe Graphics card is present + ///< @BldCfgItem{BLDCFG_IGPU_ENABLE_DISABLE_POLICY} + IN UINT8 CfgGnbSwTjOffset; ///< Software-writeable TjOffset to account for changes in junction temperature + ///< Build-time customizable only - @BldCfgItem{BLDCFG_GNB_THERMAL_SENSOR_CORRECTION} + IN UINT8 CfgLvdsMiscVoltAdjustment; ///< Travis register LVDS_CTRL_4 to adjust LVDS output voltage + ///< Build-time customizable only - @BldCfgItem{BLDCFG_LVDS_MISC_VOL_ADJUSTMENT} + IN DISPLAY_MISC_CONTROL CfgDisplayMiscControl; ///< The Display Misc control + IN BOOLEAN Reserved; ///< reserved... +} BUILD_OPT_CFG; + +/// A structure containing platform specific operational characteristics. This +/// structure is initially populated by the initializer with a copy of the same +/// structure that was created at build time using the build configuration controls. +typedef struct _PLATFORM_CONFIGURATION { + IN PERFORMANCE_PROFILE PlatformProfile; ///< Several configuration settings for the processor. + IN CPU_HT_DEEMPHASIS_LEVEL *PlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links. + ///< @BldCfgItem{BLDCFG_PLATFORM_DEEMPHASIS_LIST}. + ///< @n @e Examples: See @ref DeemphasisExamples "Deemphasis List Examples". + IN UINT8 CoreLevelingMode; ///< Indicates how to balance the number of cores per processor. + ///< @BldCfgItem{BLDCFG_CORE_LEVELING_MODE} + IN PLATFORM_C1E_MODES C1eMode; ///< Specifies the method of C1e enablement - Disabled, HW, or message based. + ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_MODE} + IN UINT32 C1ePlatformData; ///< If C1eMode is HW, specifies the P_LVL3 I/O port of the platform. + ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA} + IN UINT32 C1ePlatformData1; ///< If C1eMode is SW, specifies the address of chipset's SMI command port. + ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA1} + IN UINT32 C1ePlatformData2; ///< If C1eMode is SW, specifies the unique number used by the SMI handler to identify SMI source. + ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA2} + IN UINT32 C1ePlatformData3; ///< If C1eMode is Auto, specifies the P_LVL3 I/O port of the platform for HW C1e + ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA3} + IN PLATFORM_CSTATE_MODES CStateMode; ///< Specifies the method of C-State enablement - Disabled, or C6. + ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_MODE} + IN UINT32 CStatePlatformData; ///< This element specifies some pertinent data needed for the operation of the Cstate feature + ///< If CStateMode is CStateModeC6, this item is reserved + ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_OPDATA} + IN UINT16 CStateIoBaseAddress; ///< This item specifies a free block of 8 consecutive bytes of I/O ports that + ///< can be used to allow the CPU to enter Cstates. + ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS} + IN PLATFORM_CPB_MODES CpbMode; ///< Specifies the method of core performance boost enablement - Disabled, or Auto. + ///< @BldCfgItem{BLDCFG_PLATFORM_CPB_MODE} + IN BOOLEAN UserOptionDmi; ///< When set to TRUE, the DMI data table is generated. + IN BOOLEAN UserOptionPState; ///< When set to TRUE, the PState data tables are generated. + IN BOOLEAN UserOptionCrat; ///< When set to TRUE, the CRAT data table is generated. + IN BOOLEAN UserOptionCdit; ///< When set to TRUE, the CDIT data table is generated. + IN BOOLEAN UserOptionSrat; ///< When set to TRUE, the SRAT data table is generated. + IN BOOLEAN UserOptionSlit; ///< When set to TRUE, the SLIT data table is generated. + IN BOOLEAN UserOptionWhea; ///< When set to TRUE, the WHEA data table is generated. + IN PLATFORM_LOW_POWER_PSTATE_MODES LowPowerPstateForProcHot; ///< Specifies the method of low power Pstate for PROCHOT enablement - Disabled, or Auto. + IN UINT32 PowerCeiling; ///< P-State Ceiling Enabling Deck - Max power milli-watts. + IN BOOLEAN ForcePstateIndependent; ///< P-State _PSD independence or dependence. + ///< @BldCfgItem{BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT} + IN BOOLEAN PStatesInHpcMode; ///< @BldCfgItem{BLDCFG_PSTATE_HPC_MODE} + IN UINT32 NumberOfIoApics; ///< Number of I/O APICs in the system + ///< @BldCfgItem{BLDCFG_PLATFORM_NUM_IO_APICS} + IN PLATFORM_VRM_CONFIGURATION VrmProperties[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules. + IN BOOLEAN ProcessorScopeInSb; ///< ACPI Processor Object in \_SB scope + ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_IN_SB} + IN CHAR8 ProcessorScopeName0; ///< OEM specific 1st character of processor scope name. + ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME0} + IN CHAR8 ProcessorScopeName1; ///< OEM specific 2nd character of processor scope name. + ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME1} + IN UINT8 GnbHdAudio; ///< Control GFX HD Audio controller(Used for HDMI and DP display output), + ///< essentially it enables function 1 of graphics device. + ///< @li 0 = HD Audio disable + ///< @li 1 = HD Audio enable + ///< @BldCfgItem{BLDCFG_CFG_GNB_HD_AUDIO} + IN UINT8 AbmSupport; ///< Automatic adjust LVDS/eDP Back light level support.It is + ///< characteristic specific to display panel which used by platform design. + ///< @li 0 = ABM support disabled + ///< @li 1 = ABM support enabled + ///< @BldCfgItem{BLDCFG_CFG_ABM_SUPPORT} + IN UINT8 DynamicRefreshRate; ///< Adjust refresh rate on LVDS/eDP. + ///< @BldCfgItem{BLDCFG_CFG_DYNAMIC_REFRESH_RATE} + IN UINT16 LcdBackLightControl; ///< The PWM frequency to LCD backlight control. + ///< If equal to 0 backlight not controlled by iGPU + ///< @BldCfgItem{BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL} +} PLATFORM_CONFIGURATION; + + +/********************************************************************** + * Structures for: AmdInitLate + **********************************************************************/ +#define PROC_VERSION_LENGTH 48 +#define MAX_DIMMS_PER_SOCKET 16 +#define PROC_MANU_LENGTH 29 + +/* Interface Parameter Structures */ +/// DMI Type4 - Processor ID +typedef struct { + OUT UINT32 ProcIdLsd; ///< Lower half of 64b ID + OUT UINT32 ProcIdMsd; ///< Upper half of 64b ID +} TYPE4_PROC_ID; + +/// DMI Type 4 - Processor information +typedef struct { + OUT UINT8 T4ProcType; ///< CPU Type + OUT UINT8 T4ProcFamily; ///< Family 1 + OUT TYPE4_PROC_ID T4ProcId; ///< Id + OUT UINT8 T4Voltage; ///< Voltage + OUT UINT16 T4ExternalClock; ///< External clock + OUT UINT16 T4MaxSpeed; ///< Max speed + OUT UINT16 T4CurrentSpeed; ///< Current speed + OUT UINT8 T4Status; ///< Status + OUT UINT8 T4ProcUpgrade; ///< Up grade + OUT UINT8 T4CoreCount; ///< Core count + OUT UINT8 T4CoreEnabled; ///< Core Enable + OUT UINT8 T4ThreadCount; ///< Thread count + OUT UINT16 T4ProcCharacteristics; ///< Characteristics + OUT UINT16 T4ProcFamily2; ///< Family 2 + OUT CHAR8 T4ProcVersion[PROC_VERSION_LENGTH]; ///< Cpu version + OUT CHAR8 T4ProcManufacturer[PROC_MANU_LENGTH]; ///< Manufacturer +} TYPE4_DMI_INFO; + +/// DMI Type 7 - Cache information +typedef struct _TYPE7_DMI_INFO { + OUT UINT16 T7CacheCfg; ///< Cache cfg + OUT UINT16 T7MaxCacheSize; ///< Max size + OUT UINT16 T7InstallSize; ///< Install size + OUT UINT16 T7SupportedSramType; ///< Supported Sram Type + OUT UINT16 T7CurrentSramType; ///< Current type + OUT UINT8 T7CacheSpeed; ///< Speed + OUT UINT8 T7ErrorCorrectionType; ///< ECC type + OUT UINT8 T7SystemCacheType; ///< Cache type + OUT UINT8 T7Associativity; ///< Associativity +} TYPE7_DMI_INFO; + +/// DMI Type 16 offset 04h - Location +typedef enum { + OtherLocation = 0x01, ///< Assign 01 to Other + UnknownLocation, ///< Assign 02 to Unknown + SystemboardOrMotherboard, ///< Assign 03 to systemboard or motherboard + IsaAddonCard, ///< Assign 04 to ISA add-on card + EisaAddonCard, ///< Assign 05 to EISA add-on card + PciAddonCard, ///< Assign 06 to PCI add-on card + McaAddonCard, ///< Assign 07 to MCA add-on card + PcmciaAddonCard, ///< Assign 08 to PCMCIA add-on card + ProprietaryAddonCard, ///< Assign 09 to proprietary add-on card + NuBus, ///< Assign 0A to NuBus + Pc98C20AddonCard, ///< Assign 0A0 to PC-98/C20 add-on card + Pc98C24AddonCard, ///< Assign 0A1 to PC-98/C24 add-on card + Pc98EAddoncard, ///< Assign 0A2 to PC-98/E add-on card + Pc98LocalBusAddonCard ///< Assign 0A3 to PC-98/Local bus add-on card +} DMI_T16_LOCATION; + +/// DMI Type 16 offset 05h - Memory Error Correction +typedef enum { + OtherUse = 0x01, ///< Assign 01 to Other + UnknownUse, ///< Assign 02 to Unknown + SystemMemory, ///< Assign 03 to system memory + VideoMemory, ///< Assign 04 to video memory + FlashMemory, ///< Assign 05 to flash memory + NonvolatileRam, ///< Assign 06 to non-volatile RAM + CacheMemory ///< Assign 07 to cache memory +} DMI_T16_USE; + +/// DMI Type 16 offset 07h - Maximum Capacity +typedef enum { + Dmi16OtherErrCorrection = 0x01, ///< Assign 01 to Other + Dmi16UnknownErrCorrection, ///< Assign 02 to Unknown + Dmi16NoneErrCorrection, ///< Assign 03 to None + Dmi16Parity, ///< Assign 04 to parity + Dmi16SingleBitEcc, ///< Assign 05 to Single-bit ECC + Dmi16MultiBitEcc, ///< Assign 06 to Multi-bit ECC + Dmi16Crc ///< Assign 07 to CRC +} DMI_T16_ERROR_CORRECTION; + +/// DMI Type 16 - Physical Memory Array +typedef struct { + OUT DMI_T16_LOCATION Location; ///< The physical location of the Memory Array, + ///< whether on the system board or an add-in board. + OUT DMI_T16_USE Use; ///< Identifies the function for which the array + ///< is used. + OUT DMI_T16_ERROR_CORRECTION MemoryErrorCorrection; ///< The primary hardware error correction or + ///< detection method supported by this memory array. + OUT UINT32 MaximumCapacity; ///< The maximum memory capacity, in kilobytes, + ///< for the array. + OUT UINT16 NumberOfMemoryDevices; ///< The number of slots or sockets available + ///< for memory devices in this array. + OUT UINT64 ExtMaxCapacity; ///< The maximum memory capacity, in bytes, + ///< for this array. +} TYPE16_DMI_INFO; + +/// DMI Type 17 offset 0Eh - Form Factor +typedef enum { + OtherFormFactor = 0x01, ///< Assign 01 to Other + UnknowFormFactor, ///< Assign 02 to Unknown + SimmFormFactor, ///< Assign 03 to SIMM + SipFormFactor, ///< Assign 04 to SIP + ChipFormFactor, ///< Assign 05 to Chip + DipFormFactor, ///< Assign 06 to DIP + ZipFormFactor, ///< Assign 07 to ZIP + ProprietaryCardFormFactor, ///< Assign 08 to Proprietary Card + DimmFormFactorFormFactor, ///< Assign 09 to DIMM + TsopFormFactor, ///< Assign 10 to TSOP + RowOfChipsFormFactor, ///< Assign 11 to Row of chips + RimmFormFactor, ///< Assign 12 to RIMM + SodimmFormFactor, ///< Assign 13 to SODIMM + SrimmFormFactor, ///< Assign 14 to SRIMM + FbDimmFormFactor ///< Assign 15 to FB-DIMM +} DMI_T17_FORM_FACTOR; + +/// DMI Type 17 offset 12h - Memory Type +typedef enum { + OtherMemType = 0x01, ///< Assign 01 to Other + UnknownMemType, ///< Assign 02 to Unknown + DramMemType, ///< Assign 03 to DRAM + EdramMemType, ///< Assign 04 to EDRAM + VramMemType, ///< Assign 05 to VRAM + SramMemType, ///< Assign 06 to SRAM + RamMemType, ///< Assign 07 to RAM + RomMemType, ///< Assign 08 to ROM + FlashMemType, ///< Assign 09 to Flash + EepromMemType, ///< Assign 10 to EEPROM + FepromMemType, ///< Assign 11 to FEPROM + EpromMemType, ///< Assign 12 to EPROM + CdramMemType, ///< Assign 13 to CDRAM + ThreeDramMemType, ///< Assign 14 to 3DRAM + SdramMemType, ///< Assign 15 to SDRAM + SgramMemType, ///< Assign 16 to SGRAM + RdramMemType, ///< Assign 17 to RDRAM + DdrMemType, ///< Assign 18 to DDR + Ddr2MemType, ///< Assign 19 to DDR2 + Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM + Ddr3MemType = 0x18, ///< Assign 24 to DDR3 + Fbd2MemType ///< Assign 25 to FBD2 +} DMI_T17_MEMORY_TYPE; + +/// DMI Type 17 offset 13h - Type Detail +typedef struct { + OUT UINT16 Reserved1:1; ///< Reserved + OUT UINT16 Other:1; ///< Other + OUT UINT16 Unknown:1; ///< Unknown + OUT UINT16 FastPaged:1; ///< Fast-Paged + OUT UINT16 StaticColumn:1; ///< Static column + OUT UINT16 PseudoStatic:1; ///< Pseudo-static + OUT UINT16 Rambus:1; ///< RAMBUS + OUT UINT16 Synchronous:1; ///< Synchronous + OUT UINT16 Cmos:1; ///< CMOS + OUT UINT16 Edo:1; ///< EDO + OUT UINT16 WindowDram:1; ///< Window DRAM + OUT UINT16 CacheDram:1; ///< Cache Dram + OUT UINT16 NonVolatile:1; ///< Non-volatile + OUT UINT16 Registered:1; ///< Registered (Buffered) + OUT UINT16 Unbuffered:1; ///< Unbuffered (Unregistered) + OUT UINT16 Reserved2:1; ///< Reserved +} DMI_T17_TYPE_DETAIL; + +/// DMI Type 17 - Memory Device +typedef struct { + OUT UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits. + OUT UINT16 DataWidth; ///< Data Width, in bits, of this memory device. + OUT UINT16 MemorySize; ///< The size of the memory device. + OUT DMI_T17_FORM_FACTOR FormFactor; ///< The implementation form factor for this memory device. + OUT UINT8 DeviceSet; ///< Identifies when the Memory Device is one of a set of + ///< Memory Devices that must be populated with all devices of + ///< the same type and size, and the set to which this device belongs. + OUT CHAR8 DeviceLocator[8]; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located. + OUT CHAR8 BankLocator[10]; ///< The string number of the string that identifies the physically labeled bank where the memory device is located. + OUT DMI_T17_MEMORY_TYPE MemoryType; ///< The type of memory used in this device. + OUT DMI_T17_TYPE_DETAIL TypeDetail; ///< Additional detail on the memory device type + OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz). + OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code. + OUT CHAR8 SerialNumber[9]; ///< Serial Number. + OUT CHAR8 PartNumber[19]; ///< Part Number. + OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank. + OUT UINT32 ExtSize; ///< Extended Size. + OUT UINT16 ConfigSpeed; ///< Configured memory clock speed +} TYPE17_DMI_INFO; + +/// Memory DMI Type 17 and 20 - for memory use +typedef struct { + OUT UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits. + OUT UINT16 DataWidth; ///< Data Width, in bits, of this memory device. + OUT UINT16 MemorySize; ///< The size of the memory device. + OUT DMI_T17_FORM_FACTOR FormFactor; ///< The implementation form factor for this memory device. + OUT UINT8 DeviceLocator; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located. + OUT UINT8 BankLocator; ///< The string number of the string that identifies the physically labeled bank where the memory device is located. + OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz). + OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code. + OUT UINT8 SerialNumber[4]; ///< Serial Number. + OUT UINT8 PartNumber[18]; ///< Part Number. + OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank. + OUT UINT32 ExtSize; ///< Extended Size. + OUT UINT8 Socket:3; ///< Socket ID + OUT UINT8 Channel:2; ///< Channel ID + OUT UINT8 Dimm:2; ///< DIMM ID + OUT UINT8 DimmPresent:1; ///< Dimm Present + OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, of a range + ///< of memory mapped to the referenced Memory Device. + OUT UINT32 EndingAddr; ///< The handle, or instance number, associated with + ///< the Memory Device structure to which this address + ///< range is mapped. + OUT UINT16 ConfigSpeed; ///< Configured memory clock speed + OUT UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of + ///< memory mapped to the referenced Memory Device. + OUT UINT64 ExtEndingAddr; ///< The physical ending address, in bytes, of the last of + ///< a range of addresses mapped to the referenced Memory Device. +} MEM_DMI_INFO; + +/// DMI Type 19 - Memory Array Mapped Address +typedef struct { + OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, + ///< of a range of memory mapped to the + ///< specified physical memory array. + OUT UINT32 EndingAddr; ///< The physical ending address of the + ///< last kilobyte of a range of addresses + ///< mapped to the specified physical memory array. + OUT UINT16 MemoryArrayHandle; ///< The handle, or instance number, associated + ///< with the physical memory array to which this + ///< address range is mapped. + OUT UINT8 PartitionWidth; ///< Identifies the number of memory devices that + ///< form a single row of memory for the address + ///< partition defined by this structure. + OUT UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of + ///< memory mapped to the specified Physical Memory Array. + OUT UINT64 ExtEndingAddr; ///< The physical address, in bytes, of a range of + ///< memory mapped to the specified Physical Memory Array. +} TYPE19_DMI_INFO; + +///DMI Type 20 - Memory Device Mapped Address +typedef struct { + OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, of a range + ///< of memory mapped to the referenced Memory Device. + OUT UINT32 EndingAddr; ///< The handle, or instance number, associated with + ///< the Memory Device structure to which this address + ///< range is mapped. + OUT UINT16 MemoryDeviceHandle; ///< The handle, or instance number, associated with + ///< the Memory Device structure to which this address + ///< range is mapped. + OUT UINT16 MemoryArrayMappedAddressHandle; ///< The handle, or instance number, associated + ///< with the Memory Array Mapped Address structure to + ///< which this device address range is mapped. + OUT UINT8 PartitionRowPosition; ///< Identifies the position of the referenced Memory + ///< Device in a row of the address partition. + OUT UINT8 InterleavePosition; ///< The position of the referenced Memory Device in + ///< an interleave. + OUT UINT8 InterleavedDataDepth; ///< The maximum number of consecutive rows from the + ///< referenced Memory Device that are accessed in a + ///< single interleaved transfer. + OUT UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of + ///< memory mapped to the referenced Memory Device. + OUT UINT64 ExtEndingAddr; ///< The physical ending address, in bytes, of the last of + ///< a range of addresses mapped to the referenced Memory Device. +} TYPE20_DMI_INFO; + +/// Collection of pointers to the DMI records +typedef struct { + OUT TYPE4_DMI_INFO T4[MAX_SOCKETS_SUPPORTED]; ///< Type 4 struc + OUT TYPE7_DMI_INFO T7L1[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 1 + OUT TYPE7_DMI_INFO T7L2[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 2 + OUT TYPE7_DMI_INFO T7L3[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 3 + OUT TYPE16_DMI_INFO T16; ///< Type 16 struc + OUT TYPE17_DMI_INFO T17[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 17 struc + OUT TYPE19_DMI_INFO T19; ///< Type 19 struc + OUT TYPE20_DMI_INFO T20[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 20 struc +} DMI_INFO; + +/********************************************************************** + * Interface call: AllocateExecutionCache + **********************************************************************/ +#define MAX_CACHE_REGIONS 3 + +/// AllocateExecutionCache sub param structure for cached memory region +typedef struct { + IN OUT UINT32 ExeCacheStartAddr; ///< Start address + IN OUT UINT32 ExeCacheSize; ///< Size +} EXECUTION_CACHE_REGION; + +/********************************************************************** + * Interface call: AmdGetAvailableExeCacheSize + **********************************************************************/ +/// Get available Cache remain +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + OUT UINT32 AvailableExeCacheSize; ///< Remain size +} AMD_GET_EXE_SIZE_PARAMS; + +AGESA_STATUS +AmdGetAvailableExeCacheSize ( + IN OUT AMD_GET_EXE_SIZE_PARAMS *AmdGetExeSizeParams + ); + +/// Selection type for core leveling +typedef enum { + CORE_LEVEL_LOWEST, ///< Level to lowest common denominator + CORE_LEVEL_TWO, ///< Level to 2 cores + CORE_LEVEL_POWER_OF_TWO, ///< Level to 1,2,4 or 8 + CORE_LEVEL_NONE, ///< Do no leveling + CORE_LEVEL_COMPUTE_UNIT, ///< Level cores to one core per compute unit + CORE_LEVEL_ONE, ///< Level to 1 core + CORE_LEVEL_THREE, ///< Level to 3 cores + CORE_LEVEL_FOUR, ///< Level to 4 cores + CORE_LEVEL_FIVE, ///< Level to 5 cores + CORE_LEVEL_SIX, ///< Level to 6 cores + CORE_LEVEL_SEVEN, ///< Level to 7 cores + CORE_LEVEL_EIGHT, ///< Level to 8 cores + CORE_LEVEL_NINE, ///< Level to 9 cores + CORE_LEVEL_TEN, ///< Level to 10 cores + CORE_LEVEL_ELEVEN, ///< Level to 11 cores + CORE_LEVEL_TWELVE, ///< Level to 12 cores + CORE_LEVEL_THIRTEEN, ///< Level to 13 cores + CORE_LEVEL_FOURTEEN, ///< Level to 14 cores + CORE_LEVEL_FIFTEEN, ///< Level to 15 cores + CoreLevelModeMax ///< Used for bounds checking +} CORE_LEVELING_TYPE; + + + + + +/************************************************************************ + * + * AGESA Basic Level interface structure definition and function prototypes + * + ***********************************************************************/ + +/********************************************************************** + * Interface call: AmdCreateStruct + **********************************************************************/ +AGESA_STATUS +AmdCreateStruct ( + IN OUT AMD_INTERFACE_PARAMS *InterfaceParams + ); + +/********************************************************************** + * Interface call: AmdReleaseStruct + **********************************************************************/ +AGESA_STATUS +AmdReleaseStruct ( + IN OUT AMD_INTERFACE_PARAMS *InterfaceParams + ); + +/********************************************************************** + * Interface call: AmdInitReset + **********************************************************************/ +/// AmdInitReset param structure +typedef struct { + IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< The cached memory region + IN AMD_HT_RESET_INTERFACE HtConfig; ///< The interface for Ht Recovery + IN FCH_RESET_INTERFACE FchInterface; ///< Interface for FCH configuration +} AMD_RESET_PARAMS; + +AGESA_STATUS +AmdInitReset ( + IN OUT AMD_RESET_PARAMS *ResetParams + ); + + +/********************************************************************** + * Interface call: AmdInitEarly + **********************************************************************/ +/// InitEarly param structure +/// +/// Provide defaults or customizations to each service performed in AmdInitEarly. +/// +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< Execution Map Interface + IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. + IN AMD_HT_INTERFACE HtConfig; ///< HyperTransport Interface + IN GNB_CONFIGURATION GnbConfig; ///< GNB configuration +} AMD_EARLY_PARAMS; + +AGESA_STATUS +AmdInitEarly ( + IN OUT AMD_EARLY_PARAMS *EarlyParams + ); + + +/********************************************************************** + * Interface call: AmdInitPost + **********************************************************************/ +/// AmdInitPost param structure +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. + IN MEM_PARAMETER_STRUCT MemConfig; ///< Memory post param + IN GNB_POST_CONFIGURATION GnbPostConfig; ///< GNB post param +} AMD_POST_PARAMS; + +AGESA_STATUS +AmdInitPost ( + IN OUT AMD_POST_PARAMS *PostParams ///< Amd Cpu init param + ); + + +/********************************************************************** + * Interface call: AmdInitEnv + **********************************************************************/ +/// AmdInitEnv param structure +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. + IN GNB_ENV_CONFIGURATION GnbEnvConfiguration; ///< GNB configuration + IN FCH_INTERFACE FchInterface; ///< FCH configuration +} AMD_ENV_PARAMS; + +AGESA_STATUS +AmdInitEnv ( + IN OUT AMD_ENV_PARAMS *EnvParams + ); + + +/********************************************************************** + * Interface call: AmdInitMid + **********************************************************************/ +/// AmdInitMid param structure +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. + IN GNB_MID_CONFIGURATION GnbMidConfiguration; ///< GNB configuration + IN FCH_INTERFACE FchInterface; ///< FCH configuration +} AMD_MID_PARAMS; + +AGESA_STATUS +AmdInitMid ( + IN OUT AMD_MID_PARAMS *MidParams + ); + + +/********************************************************************** + * Interface call: AmdInitLate + **********************************************************************/ +/// AmdInitLate param structure +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. + IN IOMMU_EXCLUSION_RANGE_DESCRIPTOR *IvrsExclusionRangeList; ///< Pointer to array of exclusion ranges + OUT DMI_INFO *DmiTable; ///< DMI Interface + OUT VOID *AcpiPState; ///< Acpi Pstate SSDT Table + OUT VOID *AcpiSrat; ///< SRAT Table + OUT VOID *AcpiSlit; ///< SLIT Table + OUT VOID *AcpiWheaMce; ///< WHEA MCE Table + OUT VOID *AcpiWheaCmc; ///< WHEA CMC Table + OUT VOID *AcpiAlib; ///< ACPI SSDT table with ALIB implementation + OUT VOID *AcpiIvrs; ///< IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table + OUT VOID *AcpiCrat; ///< Component Resource Affinity Table table + OUT VOID *AcpiCdit; ///< Component Locality Distance Information table +} AMD_LATE_PARAMS; + +AGESA_STATUS +AmdInitLate ( + IN OUT AMD_LATE_PARAMS *LateParams + ); + +/********************************************************************** + * Interface call: AmdInitRecovery + **********************************************************************/ +/// CPU Recovery Parameters +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. +} AMD_CPU_RECOVERY_PARAMS; + +/// AmdInitRecovery param structure +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN MEM_PARAMETER_STRUCT MemConfig; ///< Memory post param + IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< The cached memory region. And the max cache region is 3 + IN AMD_CPU_RECOVERY_PARAMS CpuRecoveryParams; ///< Params for CPU related recovery init. +} AMD_RECOVERY_PARAMS; + +AGESA_STATUS +AmdInitRecovery ( + IN OUT AMD_RECOVERY_PARAMS *RecoveryParams + ); + +/********************************************************************** + * Interface call: AmdInitResume + **********************************************************************/ +/// AmdInitResume param structure +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN PLATFORM_CONFIGURATION PlatformConfig; ///< Platform operational characteristics + IN AMD_S3_PARAMS S3DataBlock; ///< Save state data +} AMD_RESUME_PARAMS; + +AGESA_STATUS +AmdInitResume ( + IN AMD_RESUME_PARAMS *ResumeParams + ); + + +/********************************************************************** + * Interface call: AmdS3LateRestore + **********************************************************************/ +/// AmdS3LateRestore param structure +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. + IN AMD_S3_PARAMS S3DataBlock; ///< Save state data +} AMD_S3LATE_PARAMS; + +AGESA_STATUS +AmdS3LateRestore ( + IN OUT AMD_S3LATE_PARAMS *S3LateParams + ); + + +/********************************************************************** + * Interface call: AmdS3Save + **********************************************************************/ +/// AmdS3Save param structure +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. + OUT AMD_S3_PARAMS S3DataBlock; ///< Standard header + IN FCH_INTERFACE FchInterface; ///< FCH configuration +} AMD_S3SAVE_PARAMS; + +AGESA_STATUS +AmdS3Save ( + IN OUT AMD_S3SAVE_PARAMS *AmdS3SaveParams + ); + + +/********************************************************************** + * Interface call: AmdLateRunApTask + **********************************************************************/ +/** + * Entry point for AP tasking. + */ +AGESA_STATUS +AmdLateRunApTask ( + IN AP_EXE_PARAMS *AmdApExeParams +); + +// +// General Services API +// + +/********************************************************************** + * Interface service call: AmdGetApicId + **********************************************************************/ +/// Request the APIC ID of a particular core. + +typedef struct { + IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN UINT8 Socket; ///< The Core's Socket. + IN UINT8 Core; ///< The Core id. + OUT BOOLEAN IsPresent; ///< The Core is present, and ApicAddress is valid. + OUT UINT8 ApicAddress; ///< The Core's APIC ID. +} AMD_APIC_PARAMS; + +/** + * Get a specified Core's APIC ID. + */ +AGESA_STATUS +AmdGetApicId ( + IN OUT AMD_APIC_PARAMS *AmdParamApic +); + +/********************************************************************** + * Interface service call: AmdGetPciAddress + **********************************************************************/ +/// Request the PCI Address of a Processor Module (that is, its Northbridge) + +typedef struct { + IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN UINT8 Socket; ///< The Processor's socket + IN UINT8 Module; ///< The Module in that Processor + OUT BOOLEAN IsPresent; ///< The Core is present, and PciAddress is valid. + OUT PCI_ADDR PciAddress; ///< The Processor's PCI Config Space address (Function 0, Register 0) +} AMD_GET_PCI_PARAMS; + +/** + * Get Processor Module's PCI Config Space address. + */ +AGESA_STATUS +AmdGetPciAddress ( + IN OUT AMD_GET_PCI_PARAMS *AmdParamGetPci +); + +/********************************************************************** + * Interface service call: AmdIdentifyCore + **********************************************************************/ +/// Request the identity (Socket, Module, Core) of the current Processor Core + +typedef struct { + IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + OUT UINT8 Socket; ///< The current Core's Socket + OUT UINT8 Module; ///< The current Core's Processor Module + OUT UINT8 Core; ///< The current Core's core id. +} AMD_IDENTIFY_PARAMS; + +/** + * "Who am I" for the current running core. + */ +AGESA_STATUS +AmdIdentifyCore ( + IN OUT AMD_IDENTIFY_PARAMS *AmdParamIdentify +); + +/********************************************************************** + * Interface service call: AmdReadEventLog + **********************************************************************/ +/// An Event Log Entry. +typedef struct { + IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + OUT UINT32 EventClass; ///< The severity of this event, matches AGESA_STATUS. + OUT UINT32 EventInfo; ///< The unique event identifier, zero means "no event". + OUT UINT32 DataParam1; ///< Data specific to the Event. + OUT UINT32 DataParam2; ///< Data specific to the Event. + OUT UINT32 DataParam3; ///< Data specific to the Event. + OUT UINT32 DataParam4; ///< Data specific to the Event. +} EVENT_PARAMS; + +/** + * Read an Event from the Event Log. + */ +AGESA_STATUS +AmdReadEventLog ( + IN EVENT_PARAMS *Event +); + +/********************************************************************** + * Interface service call: AmdIdentifyDimm + **********************************************************************/ +/// Request the identity of dimm from system address + +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN UINT64 MemoryAddress; ///< System Address that needs to be translated to dimm identification. + OUT UINT8 SocketId; ///< The socket on which the targeted address locates. + OUT UINT8 MemChannelId; ///< The channel on which the targeted address locates. + OUT UINT8 DimmId; ///< The dimm on which the targeted address locates. +} AMD_IDENTIFY_DIMM; + +/** + * Get the dimm identification for the address. + */ +AGESA_STATUS +AmdIdentifyDimm ( + IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify +); + +AGESA_STATUS +AmdIdsRunApTaskLate ( + IN AP_EXE_PARAMS *AmdApExeParams + ); + + +#define AGESA_IDS_DFT_VAL 0xFFFF ///< Default value of every uninitlized NV item, the action for it will be ignored +#define AGESA_IDS_NV_END 0xFFFF ///< Flag specify end of option structure +/// WARNING: Don't change the comment below, it used as signature for script +/// AGESA IDS NV ID Definitions +typedef enum { + AGESA_IDS_EXT_ID_START = 0x0000,///< 0x0000 specify the start of external NV id + + AGESA_IDS_NV_UCODE, ///< 0x0001 Enable or disable microcode patching + + AGESA_IDS_NV_TARGET_PSTATE, ///< 0x0002 Set the P-state required to be activated + AGESA_IDS_NV_POSTPSTATE, ///< 0x0003 Set the P-state required to be activated through POST + + AGESA_IDS_NV_BANK_INTERLEAVE, ///< 0x0004 Enable or disable Bank Interleave + AGESA_IDS_NV_CHANNEL_INTERLEAVE, ///< 0x0005 Enable or disable Channel Interleave + AGESA_IDS_NV_NODE_INTERLEAVE, ///< 0x0006 Enable or disable Node Interleave + AGESA_IDS_NV_MEMHOLE, ///< 0x0007 Enables or disable memory hole + + AGESA_IDS_NV_SCRUB_REDIRECTION, ///< 0x0008 Enable or disable a write to dram with corrected data + AGESA_IDS_NV_DRAM_SCRUB, ///< 0x0009 Set the rate of background scrubbing for DRAM + AGESA_IDS_NV_DCACHE_SCRUB, ///< 0x000A Set the rate of background scrubbing for the DCache. + AGESA_IDS_NV_L2_SCRUB, ///< 0x000B Set the rate of background scrubbing for the L2 cache + AGESA_IDS_NV_L3_SCRUB, ///< 0x000C Set the rate of background scrubbing for the L3 cache + AGESA_IDS_NV_ICACHE_SCRUB, ///< 0x000D Set the rate of background scrubbing for the Icache + AGESA_IDS_NV_SYNC_ON_ECC_ERROR, ///< 0x000E Enable or disable the sync flood on un-correctable ECC error + AGESA_IDS_NV_ECC_SYMBOL_SIZE, ///< 0x000F Set ECC symbol size + + AGESA_IDS_NV_ALL_MEMCLKS, ///< 0x0010 Enable or disable all memory clocks enable + AGESA_IDS_NV_DCT_GANGING_MODE, ///< 0x0011 Set the Ganged mode + AGESA_IDS_NV_DRAM_BURST_LENGTH32, ///< 0x0012 Set the DRAM Burst Length 32 + AGESA_IDS_NV_MEMORY_POWER_DOWN, ///< 0x0013 Enable or disable Memory power down mode + AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE, ///< 0x0014 Set the Memory power down mode + AGESA_IDS_NV_DLL_SHUT_DOWN, ///< 0x0015 Enable or disable DLLShutdown + AGESA_IDS_NV_ONLINE_SPARE, ///< 0x0016 Enable or disable the Dram controller to designate a DIMM bank as a spare for logical swap + + AGESA_IDS_NV_HT_ASSIST, ///< 0x0017 Enable or Disable HT Assist + AGESA_IDS_NV_ATMMODE, ///< 0x0018 Enable or Disable ATM mode + + AGESA_IDS_NV_HDTOUT, ///< 0x0019 Enable or disable HDTOUT feature + + AGESA_IDS_NV_HTLINKSOCKET, ///< 0x001A HT Link Socket + AGESA_IDS_NV_HTLINKPORT, ///< 0x001B HT Link Port + AGESA_IDS_NV_HTLINKFREQ, ///< 0x001C HT Link Frequency + AGESA_IDS_NV_HTLINKWIDTHIN, ///< 0x001D HT Link In Width + AGESA_IDS_NV_HTLINKWIDTHOUT, ///< 0x001E HT Link Out Width + + AGESA_IDS_NV_GNBHDAUDIOEN, ///< 0x001F Enable or disable GNB HD Audio + + AGESA_IDS_NV_CPB_EN, ///< 0x0020 Core Performance Boost + + AGESA_IDS_NV_HTC_EN, ///< 0x0021 HTC Enable + AGESA_IDS_NV_HTC_OVERRIDE, ///< 0x0022 HTC Override + AGESA_IDS_NV_HTC_PSTATE_LIMIT, ///< 0x0023 HTC P-state limit select + AGESA_IDS_NV_HTC_TEMP_HYS, ///< 0x0024 HTC Temperature Hysteresis + AGESA_IDS_NV_HTC_ACT_TEMP, ///< 0x0025 HTC Activation Temp + + AGESA_IDS_NV_POWER_POLICY, ///< 0x0026 Select Platform Power Policy + AGESA_IDS_EXT_ID_END, ///< 0x0027 specify the end of external NV ID +} IDS_EX_NV_ID; + + +#define IDS_NUM_EXT_NV_ITEM (AGESA_IDS_EXT_ID_END - AGESA_IDS_EXT_ID_START + 1) + + +#endif // _AGESA_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/AMD.h b/src/vendorcode/amd/agesa/f15tn/AMD.h new file mode 100644 index 0000000..fe2a086 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/AMD.h @@ -0,0 +1,506 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Agesa structures and definitions + * + * Contains AMD AGESA core interface + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Include + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + + +#ifndef _AMD_H_ +#define _AMD_H_ + +#define AGESA_REVISION "Arch2008" +#define AGESA_ID "AGESA" + +#define Int16FromChar(a,b) ((a) << 0 | (b) << 8) +#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24) +// +// +// AGESA Types and Definitions +// +// +#define LAST_ENTRY 0xFFFFFFFF +#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D') +#define IOCF8 0xCF8 +#define IOCFC 0xCFC + +/// The return status for all AGESA public services. +/// +/// Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK +/// will have log entries with more detail. +/// +typedef enum { + AGESA_SUCCESS = 0, ///< The service completed normally. Info may be logged. + AGESA_UNSUPPORTED, ///< The dispatcher or create struct had an unimplemented function requested. + ///< Not logged. + AGESA_BOUNDS_CHK, ///< A dynamic parameter was out of range and the service was not provided. + ///< Example, memory address not installed, heap buffer handle not found. + ///< Not Logged. + // AGESA_STATUS of greater severity (the ones below this line), always have a log entry available. + AGESA_ALERT, ///< An observed condition, but no loss of function. + ///< See log. Example, HT CRC. + AGESA_WARNING, ///< Possible or minor loss of function. See Log. + AGESA_ERROR, ///< Significant loss of function, boot may be possible. See Log. + AGESA_CRITICAL, ///< Continue boot only to notify user. See Log. + AGESA_FATAL, ///< Halt booting. See Log, however Fatal errors pertaining to heap problems + ///< may not be able to reliably produce log events. + AgesaStatusMax ///< Not a status, for limit checking. +} AGESA_STATUS; + +/// For checking whether a status is at or above the mandatory log level. +#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT + +/** + * Callout method to the host environment. + * + * Callout using a dispatch with appropriate thunk layer, which is determined by the host environment. + * + * @param[in] Function The specific callout function being invoked. + * @param[in] FcnData Function specific data item. + * @param[in,out] ConfigPtr Reference to Callout params. + */ +typedef AGESA_STATUS (*CALLOUT_ENTRY) ( + IN UINT32 Function, + IN UINTN FcnData, + IN OUT VOID *ConfigPtr + ); + +typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr); +typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr); + +///This allocation type is used by the AmdCreateStruct entry point +typedef enum { + PreMemHeap = 0, ///< Create heap in cache. + PostMemDram, ///< Create heap in memory. + ByHost ///< Create heap by Host. +} ALLOCATION_METHOD; + +/// These width descriptors are used by the library function, and others, to specify the data size +typedef enum ACCESS_WIDTH { + AccessWidth8 = 1, ///< Access width is 8 bits. + AccessWidth16, ///< Access width is 16 bits. + AccessWidth32, ///< Access width is 32 bits. + AccessWidth64, ///< Access width is 64 bits. + + AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. + AccessS3SaveWidth16, ///< Save 16 bits data. + AccessS3SaveWidth32, ///< Save 32 bits data. + AccessS3SaveWidth64, ///< Save 64 bits data. +} ACCESS_WIDTH; + +/// AGESA struct name +typedef enum { + // AGESA BASIC FUNCTIONS + AMD_INIT_RECOVERY = 0x00020000, ///< AmdInitRecovery entry point handle + AMD_CREATE_STRUCT, ///< AmdCreateStruct handle + AMD_INIT_EARLY, ///< AmdInitEarly entry point handle + AMD_INIT_ENV, ///< AmdInitEnv entry point handle + AMD_INIT_LATE, ///< AmdInitLate entry point handle + AMD_INIT_MID, ///< AmdInitMid entry point handle + AMD_INIT_POST, ///< AmdInitPost entry point handle + AMD_INIT_RESET, ///< AmdInitReset entry point handle + AMD_INIT_RESUME, ///< AmdInitResume entry point handle + AMD_RELEASE_STRUCT, ///< AmdReleaseStruct handle + AMD_S3LATE_RESTORE, ///< AmdS3LateRestore entry point handle + AMD_S3_SAVE, ///< AmdS3Save entry point handle + AMD_GET_APIC_ID, ///< AmdGetApicId entry point handle + AMD_GET_PCI_ADDRESS, ///< AmdGetPciAddress entry point handle + AMD_IDENTIFY_CORE, ///< AmdIdentifyCore general service handle + AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle + AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle + AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle + AMD_IDENTIFY_DIMMS ///< AmdIdentifyDimm general service handle +} AGESA_STRUCT_NAME; + + /* ResetType constant values */ +#define WARM_RESET_WHENEVER 1 +#define COLD_RESET_WHENEVER 2 +#define WARM_RESET_IMMEDIATELY 3 +#define COLD_RESET_IMMEDIATELY 4 + + +// AGESA Structures + +/// The standard header for all AGESA services. +/// For internal AGESA naming conventions, see @ref amdconfigparamname . +typedef struct { + IN UINT32 ImageBasePtr; ///< The AGESA Image base address. + IN UINT32 Func; ///< The service desired + IN UINT32 AltImageBasePtr; ///< Alternate Image location + IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA + IN UINT8 HeapStatus; ///< For heap status from boot time slide. + IN UINT64 HeapBasePtr; ///< Location of the heap + IN OUT UINT8 Reserved[7]; ///< This space is reserved for future use. +} AMD_CONFIG_PARAMS; + + +/// Create Struct Interface. +typedef struct { + IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header + IN AGESA_STRUCT_NAME AgesaFunctionName; ///< The service to init + IN ALLOCATION_METHOD AllocationMethod; ///< How to handle buffer allocation + IN OUT UINT32 NewStructSize; ///< The size of the allocated data, in for ByHost, else out only. + IN OUT VOID *NewStructPtr; ///< The struct for the service. + ///< The struct to init for ByHost allocation, + ///< the initialized struct on return. +} AMD_INTERFACE_PARAMS; + +#define FUNC_0 0 // bit-placed for PCI address creation +#define FUNC_1 1 +#define FUNC_2 2 +#define FUNC_3 3 +#define FUNC_4 4 +#define FUNC_5 5 +#define FUNC_6 6 +#define FUNC_7 7 + +/// AGESA Binary module header structure +typedef struct { + IN UINT32 Signature; ///< Binary Signature + IN CHAR8 CreatorID[8]; ///< 8 characters ID + IN CHAR8 Version[12]; ///< 12 characters version + IN UINT32 ModuleInfoOffset; ///< Offset of module + IN UINT32 EntryPointAddress; ///< Entry address + IN UINT32 ImageBase; ///< Image base + IN UINT32 RelocTableOffset; ///< Relocate Table offset + IN UINT32 ImageSize; ///< Size + IN UINT16 Checksum; ///< Checksum + IN UINT8 ImageType; ///< Type + IN UINT8 V_Reserved; ///< Reserved +} AMD_IMAGE_HEADER; +/// AGESA Binary module header structure +typedef struct _AMD_MODULE_HEADER { + IN UINT32 ModuleHeaderSignature; ///< Module signature + IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID + IN CHAR8 ModuleVersion[12]; ///< 12 characters version + IN VOID *ModuleDispatcher; ///< A pointer point to dispatcher + IN struct _AMD_MODULE_HEADER *NextBlock; ///< Next module header link +} AMD_MODULE_HEADER; + +// AMD_CODE_HEADER Signatures. +#define AGESA_CODE_SIGNATURE {'!', '!', 'A', 'G', 'E', 'S', 'A', ' '} +#define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'} +#define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'} + +/// AGESA_CODE_SIGNATURE +typedef struct { + IN CHAR8 Signature[8]; ///< code header Signature + IN CHAR8 ComponentName[8]; ///< 8 character name of the code module + IN CHAR8 Version[12]; ///< 12 character version string + IN CHAR8 TerminatorNull; ///< null terminated string + IN CHAR8 VerReserved[7]; ///< reserved space +} AMD_CODE_HEADER; + +/// Extended PCI address format +typedef struct { + IN OUT UINT32 Register:12; ///< Register offset + IN OUT UINT32 Function:3; ///< Function number + IN OUT UINT32 Device:5; ///< Device number + IN OUT UINT32 Bus:8; ///< Bus number + IN OUT UINT32 Segment:4; ///< Segment +} EXT_PCI_ADDR; + +/// Union type for PCI address +typedef union _PCI_ADDR { + IN UINT32 AddressValue; ///< Formal address + IN EXT_PCI_ADDR Address; ///< Extended address +} PCI_ADDR; + +// SBDFO - Segment Bus Device Function Offset +// 31:28 Segment (4-bits) +// 27:20 Bus (8-bits) +// 19:15 Device (5-bits) +// 14:12 Function(3-bits) +// 11:00 Offset (12-bits) + +#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \ + (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off))) +#define ILLEGAL_SBDFO 0xFFFFFFFF + +/// CPUID data received registers format +typedef struct { + OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX + OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX + OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX + OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX +} CPUID_DATA; + +/// HT frequency for external callbacks +typedef enum { + HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks + HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks + HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks + HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks + HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks + HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks + HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks + HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks + HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks + HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks + HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks + HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks + HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks + HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks + HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks + HT_FREQUENCY_3200M = 19, ///< HT speed 3200 for external callbacks + HT_FREQUENCY_MAX ///< Limit check. +} HT_FREQUENCIES; +// The minimum HT3 frequency +#define HT3_FREQUENCY_MIN HT_FREQUENCY_1200M + +#ifndef BIT0 + #define BIT0 0x0000000000000001ull +#endif +#ifndef BIT1 + #define BIT1 0x0000000000000002ull +#endif +#ifndef BIT2 + #define BIT2 0x0000000000000004ull +#endif +#ifndef BIT3 + #define BIT3 0x0000000000000008ull +#endif +#ifndef BIT4 + #define BIT4 0x0000000000000010ull +#endif +#ifndef BIT5 + #define BIT5 0x0000000000000020ull +#endif +#ifndef BIT6 + #define BIT6 0x0000000000000040ull +#endif +#ifndef BIT7 + #define BIT7 0x0000000000000080ull +#endif +#ifndef BIT8 + #define BIT8 0x0000000000000100ull +#endif +#ifndef BIT9 + #define BIT9 0x0000000000000200ull +#endif +#ifndef BIT10 + #define BIT10 0x0000000000000400ull +#endif +#ifndef BIT11 + #define BIT11 0x0000000000000800ull +#endif +#ifndef BIT12 + #define BIT12 0x0000000000001000ull +#endif +#ifndef BIT13 + #define BIT13 0x0000000000002000ull +#endif +#ifndef BIT14 + #define BIT14 0x0000000000004000ull +#endif +#ifndef BIT15 + #define BIT15 0x0000000000008000ull +#endif +#ifndef BIT16 + #define BIT16 0x0000000000010000ull +#endif +#ifndef BIT17 + #define BIT17 0x0000000000020000ull +#endif +#ifndef BIT18 + #define BIT18 0x0000000000040000ull +#endif +#ifndef BIT19 + #define BIT19 0x0000000000080000ull +#endif +#ifndef BIT20 + #define BIT20 0x0000000000100000ull +#endif +#ifndef BIT21 + #define BIT21 0x0000000000200000ull +#endif +#ifndef BIT22 + #define BIT22 0x0000000000400000ull +#endif +#ifndef BIT23 + #define BIT23 0x0000000000800000ull +#endif +#ifndef BIT24 + #define BIT24 0x0000000001000000ull +#endif +#ifndef BIT25 + #define BIT25 0x0000000002000000ull +#endif +#ifndef BIT26 + #define BIT26 0x0000000004000000ull +#endif +#ifndef BIT27 + #define BIT27 0x0000000008000000ull +#endif +#ifndef BIT28 + #define BIT28 0x0000000010000000ull +#endif +#ifndef BIT29 + #define BIT29 0x0000000020000000ull +#endif +#ifndef BIT30 + #define BIT30 0x0000000040000000ull +#endif +#ifndef BIT31 + #define BIT31 0x0000000080000000ull +#endif +#ifndef BIT32 + #define BIT32 0x0000000100000000ull +#endif +#ifndef BIT33 + #define BIT33 0x0000000200000000ull +#endif +#ifndef BIT34 + #define BIT34 0x0000000400000000ull +#endif +#ifndef BIT35 + #define BIT35 0x0000000800000000ull +#endif +#ifndef BIT36 + #define BIT36 0x0000001000000000ull +#endif +#ifndef BIT37 + #define BIT37 0x0000002000000000ull +#endif +#ifndef BIT38 + #define BIT38 0x0000004000000000ull +#endif +#ifndef BIT39 + #define BIT39 0x0000008000000000ull +#endif +#ifndef BIT40 + #define BIT40 0x0000010000000000ull +#endif +#ifndef BIT41 + #define BIT41 0x0000020000000000ull +#endif +#ifndef BIT42 + #define BIT42 0x0000040000000000ull +#endif +#ifndef BIT43 + #define BIT43 0x0000080000000000ull +#endif +#ifndef BIT44 + #define BIT44 0x0000100000000000ull +#endif +#ifndef BIT45 + #define BIT45 0x0000200000000000ull +#endif +#ifndef BIT46 + #define BIT46 0x0000400000000000ull +#endif +#ifndef BIT47 + #define BIT47 0x0000800000000000ull +#endif +#ifndef BIT48 + #define BIT48 0x0001000000000000ull +#endif +#ifndef BIT49 + #define BIT49 0x0002000000000000ull +#endif +#ifndef BIT50 + #define BIT50 0x0004000000000000ull +#endif +#ifndef BIT51 + #define BIT51 0x0008000000000000ull +#endif +#ifndef BIT52 + #define BIT52 0x0010000000000000ull +#endif +#ifndef BIT53 + #define BIT53 0x0020000000000000ull +#endif +#ifndef BIT54 + #define BIT54 0x0040000000000000ull +#endif +#ifndef BIT55 + #define BIT55 0x0080000000000000ull +#endif +#ifndef BIT56 + #define BIT56 0x0100000000000000ull +#endif +#ifndef BIT57 + #define BIT57 0x0200000000000000ull +#endif +#ifndef BIT58 + #define BIT58 0x0400000000000000ull +#endif +#ifndef BIT59 + #define BIT59 0x0800000000000000ull +#endif +#ifndef BIT60 + #define BIT60 0x1000000000000000ull +#endif +#ifndef BIT61 + #define BIT61 0x2000000000000000ull +#endif +#ifndef BIT62 + #define BIT62 0x4000000000000000ull +#endif +#ifndef BIT63 + #define BIT63 0x8000000000000000ull +#endif + +#endif // _AMD_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Dispatcher.h b/src/vendorcode/amd/agesa/f15tn/Dispatcher.h new file mode 100644 index 0000000..a5be609 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Dispatcher.h @@ -0,0 +1,78 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Pushhigh Interface + * + * Contains interface to Pushhigh entry + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Legacy + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * *************************************************************************** + */ + +#ifndef _DISPATCHER_H_ +#define _DISPATCHER_H_ + +// AGESA function prototypes +AGESA_STATUS CALLCONV AmdAgesaDispatcher ( IN OUT VOID *ConfigPtr ); +AGESA_STATUS CALLCONV AmdAgesaCallout ( IN UINT32 Func, IN UINT32 Data, IN OUT VOID *ConfigPtr ); + +#endif // _DISPATCHER_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h b/src/vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h new file mode 100644 index 0000000..666cfe1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h @@ -0,0 +1,193 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Advanced API Interface for HT, Memory and CPU + * + * Contains additional declarations need to use HT, Memory and CPU Advanced interface, such as + * would be required by the basic interface implementations. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Include + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + + +#ifndef _ADVANCED_API_H_ +#define _ADVANCED_API_H_ + +/*---------------------------------------------------------------------------- + * HT FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +/** + * A constructor for the HyperTransport input structure. + * + * Sets inputs to valid, basic level, defaults. + * + * @param[in] StdHeader Opaque handle to standard config header + * @param[in] AmdHtInterface HT Interface structure to initialize. + * + * @retval AGESA_SUCCESS Constructors are not allowed to fail +*/ +AGESA_STATUS +AmdHtInterfaceConstructor ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_HT_INTERFACE *AmdHtInterface + ); + +/** + * The top level external interface for Hypertransport Initialization. + * + * Create our initial internal state, initialize the coherent fabric, + * initialize the non-coherent chains, and perform any required fabric tuning or + * optimization. + * + * @param[in] StdHeader Opaque handle to standard config header + * @param[in] PlatformConfiguration The platform configuration options. + * @param[in] AmdHtInterface HT Interface structure. + * + * @retval AGESA_SUCCESS Only information events logged. + * @retval AGESA_ALERT Sync Flood or CRC error logged. + * @retval AGESA_WARNING Example: expected capability not found + * @retval AGESA_ERROR logged events indicating some devices may not be available + * @retval AGESA_FATAL Mixed Family or MP capability mismatch + * + */ +AGESA_STATUS +AmdHtInitialize ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfiguration, + IN AMD_HT_INTERFACE *AmdHtInterface + ); + +/*---------------------------------------------------------------------------- + * HT Recovery FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +/** + * A constructor for the HyperTransport input structure. + * + */ +AGESA_STATUS +AmdHtResetConstructor ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface + ); + +/** + * Initialize HT at Reset for both Normal and Recovery. + * + */ +AGESA_STATUS +AmdHtInitReset ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface + ); + +/** + * Initialize the Node and Socket maps for an AP Core. + * + */ +AGESA_STATUS +AmdHtInitRecovery ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +///---------------------------------------------------------------------------- +/// MEMORY FUNCTIONS PROTOTYPE +/// +///---------------------------------------------------------------------------- + +AGESA_STATUS +AmdMemRecovery ( + IN OUT MEM_DATA_STRUCT *MemPtr + ); + +AGESA_STATUS +AmdMemAuto ( + IN OUT MEM_DATA_STRUCT *MemPtr + ); + +VOID +AmdMemInitDataStructDef ( + IN OUT MEM_DATA_STRUCT *MemPtr, + IN OUT PLATFORM_CONFIGURATION *PlatFormConfig + ); + +VOID +memDefRet ( VOID ); + +BOOLEAN +memDefTrue ( VOID ); + +BOOLEAN +memDefFalse ( VOID ); + +VOID +MemRecDefRet ( VOID ); + +BOOLEAN +MemRecDefTrue ( VOID ); + +#endif // _ADVANCED_API_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/ComalInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/ComalInstall.h new file mode 100644 index 0000000..7342d26 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/ComalInstall.h @@ -0,0 +1,186 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build options for a Comal platform solution + * + * This file generates the defaults tables for the "Comal" platform solution + * set of processors. The documented build options are imported from a user + * controlled file for processing. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e $Revision: 65876 $ @e $Date: 2012-02-26 21:30:10 -0600 (Sun, 26 Feb 2012) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "CommonReturns.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterface.h" + +/***************************************************************************** + * Define the RELEASE VERSION string + * + * The Release Version string should identify the next planned release. + * When a branch is made in preparation for a release, the release manager + * should change/confirm that the branch version of this file contains the + * string matching the desired version for the release. The trunk version of + * the file should always contain a trailing 'X'. This will make sure that a + * development build from trunk will not be confused for a released version. + * The release manager will need to remove the trailing 'X' and update the + * version string as appropriate for the release. The trunk copy of this file + * should also be updated/incremented for the next expected version, + trailing 'X' + ****************************************************************************/ + // This is the delivery package title, "TrinyPI " + // This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'T', 'r', 'i', 'n', 'y', 'P', 'I', ' '} + + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '2', ' ', ' ', ' ', ' '} + + +// The Comal solution is defined to be family 0x15 models 0x10 - 0x1F in the FS1 and FP2 sockets. +#define INSTALL_FS1_SOCKET_SUPPORT TRUE +#define INSTALL_FP2_SOCKET_SUPPORT TRUE +#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE + +#ifdef BLDOPT_REMOVE_FS1_SOCKET_SUPPORT + #if BLDOPT_REMOVE_FS1_SOCKET_SUPPORT == TRUE + #undef INSTALL_FS1_SOCKET_SUPPORT + #define INSTALL_FS1_SOCKET_SUPPORT FALSE + #endif +#endif + +#ifdef BLDOPT_REMOVE_FP2_SOCKET_SUPPORT + #if BLDOPT_REMOVE_FP2_SOCKET_SUPPORT == TRUE + #undef INSTALL_FP2_SOCKET_SUPPORT + #define INSTALL_FP2_SOCKET_SUPPORT FALSE + #endif +#endif + + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) + + +#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 +#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 +#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 +#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 +#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 +#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 +#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 +#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x420 +#define DFLT_SPI_BASE_ADDRESS 0xFEC10000ul +#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0ul +#define DFLT_HPET_BASE_ADDRESS 0xFED00000ul +#define DFLT_SMI_CMD_PORT 0xB0 +#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 +#define DFLT_GEC_BASE_ADDRESS 0xFED61000ul +#define DFLT_SMBUS_SSID 0x780B1022ul +#define DFLT_IDE_SSID 0x780C1022ul +#define DFLT_SATA_AHCI_SSID 0x78011022ul +#define DFLT_SATA_IDE_SSID 0x78001022ul +#define DFLT_SATA_RAID5_SSID 0x78031022ul +#define DFLT_SATA_RAID_SSID 0x78021022ul +#define DFLT_EHCI_SSID 0x78081022ul +#define DFLT_OHCI_SSID 0x78071022ul +#define DFLT_LPC_SSID 0x780E1022ul +#define DFLT_SD_SSID 0x78061022ul +#define DFLT_XHCI_SSID 0x78121022ul +#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE +#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +#define DFLT_FCH_GPP_LINK_CONFIG PortA4 +#define DFLT_FCH_GPP_PORT0_PRESENT FALSE +#define DFLT_FCH_GPP_PORT1_PRESENT FALSE +#define DFLT_FCH_GPP_PORT2_PRESENT FALSE +#define DFLT_FCH_GPP_PORT3_PRESENT FALSE +#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE + +#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT + #error BLDCFG: BLDCFG_VRM_INRUSH_CURRENT_LIMIT is deprecated. Use BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT instead. +#endif + +#ifdef BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT + #error BLDCFG: BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT is deprecated. Use BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT instead. +#endif + +// Instantiate all solution relevant data. +#include "PlatformInstall.h" + diff --git a/src/vendorcode/amd/agesa/f15tn/Include/CommonReturns.h b/src/vendorcode/amd/agesa/f15tn/Include/CommonReturns.h new file mode 100644 index 0000000..5bcc1ba --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/CommonReturns.h @@ -0,0 +1,151 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Common Return routines. + * + * Routines which do nothing, returning a result (preferably some version of zero) which + * is consistent with "do nothing" or "default". Useful for function pointer tables. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Common + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _COMMON_RETURNS_H_ +#define _COMMON_RETURNS_H_ + + +/** +* Return True +* +* @retval True Default case, no special action +*/ +BOOLEAN +CommonReturnTrue ( VOID ); + +/** +* Return False. +* +* @retval FALSE Default case, no special action +*/ +BOOLEAN +CommonReturnFalse ( VOID ); + +/** + * Return (UINT8)zero. + * + * + * @retval zero None, or only case zero. + */ +UINT8 +CommonReturnZero8 ( VOID ); + +/** + * Return (UINT32)zero. + * + * + * @retval zero None, or only case zero. + */ +UINT32 +CommonReturnZero32 ( VOID ); + +/** + * Return (UINT64)zero. + * + * + * @retval zero None, or only case zero. + */ +UINT64 +CommonReturnZero64 ( VOID ); + +/** + * Return NULL + * + * @retval NULL pointer to nothing + */ +VOID * +CommonReturnNULL ( VOID ); + +/** +* Return AGESA_SUCCESS. +* +* @retval AGESA_SUCCESS Success. +*/ +AGESA_STATUS +CommonReturnAgesaSuccess ( VOID ); + +/** + * Do Nothing. + * + */ +VOID +CommonVoid ( VOID ); + +/** + * ASSERT if this routine is called. + * + */ +VOID +CommonAssert ( VOID ); + +#endif // _COMMON_RETURNS_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/Filecode.h b/src/vendorcode/amd/agesa/f15tn/Include/Filecode.h new file mode 100644 index 0000000..c31410b --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/Filecode.h @@ -0,0 +1,1113 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Collectively assign unique filecodes for assert and debug to each source file. + * + * Publish values for decorated filenames, which can be used for + * ASSERT and debug support using a preprocessor define like: + * @n <tt> #define FILECODE MY_C_FILENAME_FILECODE </tt> @n + * This file serves as a reference for debugging to associate the code and filename. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Include + * @e $Revision: 64574 $ @e $Date: 2012-01-25 01:01:51 -0600 (Wed, 25 Jan 2012) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _FILECODE_H_ +#define _FILECODE_H_ + +#define UNASSIGNED_FILE_FILECODE (0xFFFF) + +/// For debug use in any Platform's options C file. +/// Can be reused for platforms and image builds, since only one options file can be built. +#define PLATFORM_SPECIFIC_OPTIONS_FILECODE (0xBBBB) + + +#define PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE (0xA001) +#define PROC_GNB_GFX_FAMILY_LN_F12GFXSERVICES_FILECODE (0xA002) +#define PROC_GNB_GFX_FAMILY_ON_F14GFXSERVICES_FILECODE (0xA003) +#define PROC_GNB_GFX_GFXGMCINIT_FILECODE (0xA006) +#define PROC_GNB_GFX_GFXINITATENVPOST_FILECODE (0xA010) +#define PROC_GNB_GFX_GFXINITATMIDPOST_FILECODE (0xA011) +#define PROC_GNB_GFX_GFXINITATPOST_FILECODE (0xA012) +#define PROC_GNB_GFX_GFXINTEGRATEDINFOTABLEINIT_FILECODE (0xA013) +#define PROC_GNB_GFX_GFXLIB_FILECODE (0xA014) +#define PROC_GNB_GFX_GFXREGISTERACC_FILECODE (0xA015) +#define PROC_GNB_GFX_GFXSTRAPSINIT_FILECODE (0xA016) +#define PROC_GNB_GNBINITATEARLY_FILECODE (0xA017) +#define PROC_GNB_GNBINITATENV_FILECODE (0xA020) +#define PROC_GNB_GNBINITATLATE_FILECODE (0xA021) +#define PROC_GNB_GNBINITATMID_FILECODE (0xA022) +#define PROC_GNB_GNBINITATPOST_FILECODE (0xA023) +#define PROC_GNB_GNBINITATRESET_FILECODE (0xA024) +#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIB_FILECODE (0xA025) +#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE (0xA026) +#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE (0xA027) +#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBIOACC_FILECODE (0xA028) +#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBMEMACC_FILECODE (0xA029) +#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE (0xA02A) +#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCIACC_FILECODE (0xA030) +#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXCARDINFO_FILECODE (0xA031) +#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE (0xA032) +#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXPOWERPLAYTABLE_FILECODE (0xA033) +#define PROC_GNB_MODULES_GNBNBINITLIBV1_GNBNBINITLIBV1_FILECODE (0xA034) +#define PROC_GNB_MODULES_GNBPCIEALIBV1_PCIEALIB_FILECODE (0xA035) +#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE (0xA036) +#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE (0xA037) +#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE (0xA038) +#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEMAPTOPOLOGY_FILECODE (0xA039) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMBLACKLIST_FILECODE (0xA03B) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMEXITLATENCY_FILECODE (0xA03C) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPHYSERVICES_FILECODE (0xA03D) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE (0xA03E) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE (0xA03F) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE (0xA041) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPOWERMGMT_FILECODE (0xA043) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESILICONSERVICES_FILECODE (0xA045) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETIMER_FILECODE (0xA046) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETOPOLOGYSERVICES_FILECODE (0xA047) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE (0xA048) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE (0xA049) +#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIETRAINING_FILECODE (0xA04A) +#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIEWORKAROUNDS_FILECODE (0xA04B) +#define PROC_GNB_NB_FAMILY_LN_F12NBPOWERGATE_FILECODE (0xA04C) +#define PROC_GNB_NB_FAMILY_LN_F12NBSERVICES_FILECODE (0xA04D) +#define PROC_GNB_NB_FAMILY_LN_F12NBSMU_FILECODE (0xA04E) +#define PROC_GNB_NB_FAMILY_ON_F14NBLCLKNCLKRATIO_FILECODE (0xA04F) +#define PROC_GNB_NB_FAMILY_ON_F14NBPOWERGATE_FILECODE (0xA050) +#define PROC_GNB_NB_FAMILY_ON_F14NBSERVICES_FILECODE (0xA051) +#define PROC_GNB_NB_FAMILY_ON_F14NBSMU_FILECODE (0xA052) +#define PROC_GNB_NB_FEATURE_NBFUSETABLE_FILECODE (0xA053) +#define PROC_GNB_NB_FEATURE_NBLCLKDPM_FILECODE (0xA054) +#define PROC_GNB_NB_FAMILY_LN_F12NBLCLKDPM_FILECODE (0xA055) +#define PROC_GNB_NB_FAMILY_ON_F14NBLCLKDPM_FILECODE (0xA056) +#define PROC_GNB_NB_NBCONFIGDATA_FILECODE (0xA060) +#define PROC_GNB_NB_NBINIT_FILECODE (0xA061) +#define PROC_GNB_NB_NBINITATEARLY_FILECODE (0xA062) +#define PROC_GNB_NB_NBINITATENV_FILECODE (0xA063) +#define PROC_GNB_NB_NBINITATLATEPOST_FILECODE (0xA070) +#define PROC_GNB_NB_NBINITATPOST_FILECODE (0xA071) +#define PROC_GNB_NB_NBINITATRESET_FILECODE (0xA072) +#define PROC_GNB_NB_NBPOWERMGMT_FILECODE (0xA073) +#define PROC_GNB_NB_NBSMULIB_FILECODE (0xA074) +#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEALIBFS1_FILECODE (0xA075) +#define PROC_GNB_PCIE_FAMILY_LN_F12PCIECOMPLEXCONFIG_FILECODE (0xA076) +#define PROC_GNB_PCIE_FAMILY_LN_F12PCIECOMPLEXSERVICES_FILECODE (0xA077) +#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEPHYSERVICES_FILECODE (0xA078) +#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEPIFSERVICES_FILECODE (0xA079) +#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEWRAPPERSERVICES_FILECODE (0xA07A) +#define PROC_GNB_PCIE_FAMILY_ON_F14PCIEALIB_FILECODE (0xA07D) +#define PROC_GNB_PCIE_FAMILY_ON_F14PCIECOMPLEXCONFIG_FILECODE (0xA07E) +#define PROC_GNB_PCIE_FAMILY_ON_F14PCIECOMPLEXSERVICES_FILECODE (0xA07F) +#define PROC_GNB_PCIE_FAMILY_ON_F14PCIEPHYSERVICES_FILECODE (0xA080) +#define PROC_GNB_PCIE_FAMILY_ON_F14PCIEPIFSERVICES_FILECODE (0xA081) +#define PROC_GNB_PCIE_FAMILY_ON_F14PCIEWRAPPERSERVICES_FILECODE (0xA082) +#define PROC_GNB_PCIE_FEATURE_PCIEPOWERGATE_FILECODE (0xA083) +#define PROC_GNB_PCIE_PCIEINIT_FILECODE (0xA084) +#define PROC_GNB_PCIE_PCIEINITATEARLYPOST_FILECODE (0xA085) +#define PROC_GNB_PCIE_PCIEINITATENV_FILECODE (0xA086) +#define PROC_GNB_PCIE_PCIEINITATLATEPOST_FILECODE (0xA087) +#define PROC_GNB_PCIE_PCIEINITATPOST_FILECODE (0xA088) +#define PROC_GNB_PCIE_PCIELATEINIT_FILECODE (0xA089) +#define PROC_GNB_PCIE_PCIEPORTINIT_FILECODE (0xA08B) +#define PROC_GNB_PCIE_PCIEPORTLATEINIT_FILECODE (0xA08C) +#define PROC_GNB_MODULES_GNBCABLESAFE_GNBCABLESAFE_FILECODE (0xA08D) +#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGENV_FILECODE (0xA08E) +#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGPOST_FILECODE (0xA08F) +#define PROC_GNB_MODULES_GNBTABLE_GNBTABLE_FILECODE (0xA090) +#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GNBGFXINITLIBV1_FILECODE (0xA091) +#define PROC_GNB_MODULES_GNBINITTN_GFXENVINITTN_FILECODE (0xA092) +#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGLIB_FILECODE (0xA093) +#define PROC_GNB_MODULES_GNBINITTN_GFXGMCINITTN_FILECODE (0xA094) +#define PROC_GNB_MODULES_GNBINITTN_GFXINTEGRATEDINFOTABLETN_FILECODE (0xA095) +#define PROC_GNB_MODULES_GNBINITTN_GFXLIBTN_FILECODE (0xA096) +#define PROC_GNB_MODULES_GNBINITTN_GFXMIDINITTN_FILECODE (0xA097) +#define PROC_GNB_MODULES_GNBINITTN_GNBPOSTINITTN_FILECODE (0xA098) +#define PROC_GNB_MODULES_GNBINITTN_GNBEARLYINITTN_FILECODE (0xA09A) +#define PROC_GNB_MODULES_GNBINITTN_GNBENVINITTN_FILECODE (0xA09B) +#define PROC_GNB_MODULES_GNBINITTN_GNBFUSETABLETN_FILECODE (0xA09C) +#define PROC_GNB_MODULES_GNBINITTN_GNBMIDINITTN_FILECODE (0xA09D) +#define PROC_GNB_MODULES_GNBINITTN_GFXPOSTINITTN_FILECODE (0xA09E) +#define PROC_GNB_MODULES_GNBINITTN_GNBREGISTERACCTN_FILECODE (0xA09F) +#define PROC_GNB_MODULES_GNBINITTN_PCIECONFIGTN_FILECODE (0xA0A0) +#define PROC_GNB_MODULES_GNBINITTN_PCIEEARLYINITTN_FILECODE (0xA0A1) +#define PROC_GNB_MODULES_GNBINITTN_PCIEENVINITTN_FILECODE (0xA0A2) +#define PROC_GNB_MODULES_GNBINITTN_PCIELIBTN_FILECODE (0xA0A3) +#define PROC_GNB_MODULES_GNBINITTN_PCIEMIDINITTN_FILECODE (0xA0A4) +#define PROC_GNB_MODULES_GNBINITTN_PCIEPOSTINITTN_FILECODE (0xA0A5) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEWRAPPERSERVICESV4_FILECODE (0xA0A6) +#define PROC_GNB_MODULES_GNBIOMMUIVRS_GNBIOMMUIVRS_FILECODE (0xA0A7) +#define PROC_GNB_MODULES_GNBIVRSLIB_GNBIVRSLIB_FILECODE (0xA0A8) +#define PROC_GNB_MODULES_GNBNBINITLIBV4_GNBNBINITLIBV4_FILECODE (0xA0A9) +#define PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBPCIETRANSLATION_FILECODE (0xA0AA) +#define PROC_GNB_MODULES_GNBINITTN_GNBIOMMUIVRSTN_FILECODE (0xA0AB) +#define PROC_GNB_MODULES_GNBINITTN_PCIEPOWERGATETN_FILECODE (0xA0B8) +#define PROC_GNB_MODULES_GNBINITTN_PCIEALIBTNFS1_FILECODE (0xA0B9) +#define PROC_GNB_MODULES_GNBSBLIB_GNBSBPCIE_FILECODE (0xA0BA) +#define PROC_GNB_MODULES_GNBSBLIB_GNBSBLIB_FILECODE (0xA0BB) +#define PROC_GNB_MODULES_GNBSBIOMMULIB_GNBSBIOMMULIB_FILECODE (0xA0BC) +#define PROC_GNB_LIBRARY_GNBTIMERLIBWRAP0_GNBTIMERLIBWRAP0_FILECODE (0xA0BD) +#define PROC_GNB_MODULES_GNBMSOCKETLIB_GNBMSOCKETLIB_FILECODE (0xA0BE) +#define PROC_GNB_MODULES_GNBSSOCKETLIB_GNBSSOCKETLIB_FILECODE (0xA0BF) +#define PROC_GNB_MODULES_GNBPCIECONFIG_GNBHANDLELIB_FILECODE (0xA0C0) + +#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPHYSERVICESV5_FILECODE (0xA0C5) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPIFSERVICESV5_FILECODE (0xA0C6) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPORTSERVICESV5_FILECODE (0xA0C7) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPOWERMGMTV5_FILECODE (0xA0C8) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIESILICONSERVICESV5_FILECODE (0xA0C9) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEWRAPPERSERVICESV5_FILECODE (0xA0CA) +#define PROC_GNB_MODULES_GNBNBINITLIBV5_GNBNBINITLIBV5_FILECODE (0xA0CB) + +#define PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBTRANSLATION_FILECODE (0xA0DB) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPOWERMGMTV4_FILECODE (0xA0DC) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPORTSERVICESV4_FILECODE (0xA0DD) +#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEALIBFM1_FILECODE (0xA0DE) +#define PROC_GNB_MODULES_GNBINITTN_PCIEALIBTNFM2_FILECODE (0xA0DF) +#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGMID_FILECODE (0xA0E0) +#define PROC_GNB_MODULES_GNBIOAPIC_GNBIOAPIC_FILECODE (0xA0EE) +#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEMAXPAYLOADV4_FILECODE (0xA0F4) +#define PROC_GNB_MODULES_GNBPCIECLKPM_PCIECLKPM_FILECODE (0xA0F5) + +#define PROC_RECOVERY_GNB_GNBRECOVERY_FILECODE (0xAE01) +#define PROC_RECOVERY_GNB_NBINITRECOVERY_FILECODE (0xAE02) +#define PROC_GNB_GNBINITATS3SAVE_FILECODE (0xAE03) +#define PROC_GNB_MODULES_GNBSVIEW_GNBSVIEW_FILECODE (0xAE04) + +#define PROC_GNB_LIBRARY_GNBTIMERLIBWRAP2_GNBTIMERLIBWRAP2_FILECODE (0xAE17) +#define PROC_GNB_MODULES_GNBIOMMUSCRATCH_GNBIOMMUSCRATCH_FILECODE (0xAE18) +// FCH +#define PROC_FCH_COMMON_ACPILIB_FILECODE (0xB010) +#define PROC_FCH_COMMON_FCHLIB_FILECODE (0xB011) +#define PROC_FCH_COMMON_FCHCOMMON_FILECODE (0xB012) +#define PROC_FCH_COMMON_FCHCOMMONSMM_FILECODE (0xB013) +#define PROC_FCH_COMMON_MEMLIB_FILECODE (0xB014) +#define PROC_FCH_COMMON_PCILIB_FILECODE (0xB015) +#define PROC_FCH_COMMON_FCHPELIB_FILECODE (0xB016) +#define PROC_FCH_GEC_GECRESET_FILECODE (0xB020) +#define PROC_FCH_GEC_GECENV_FILECODE (0xB021) +#define PROC_FCH_GEC_GECMID_FILECODE (0xB022) +#define PROC_FCH_GEC_GECLATE_FILECODE (0xB023) +#define PROC_FCH_GEC_FAMILY_HUDSON2_HUDSON2GECSERVICE_FILECODE (0xB024) +#define PROC_FCH_GEC_FAMILY_HUDSON2_HUDSON2GECENVSERVICE_FILECODE (0xB025) +#define PROC_FCH_HWACPI_HWACPIRESET_FILECODE (0xB030) +#define PROC_FCH_HWACPI_HWACPIENV_FILECODE (0xB031) +#define PROC_FCH_HWACPI_HWACPIMID_FILECODE (0xB032) +#define PROC_FCH_HWACPI_HWACPILATE_FILECODE (0xB033) +#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPIENVSERVICE_FILECODE (0xB034) +#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPIMIDSERVICE_FILECODE (0xB035) +#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPILATESERVICE_FILECODE (0xB036) +#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2SSSERVICE_FILECODE (0xB037) +#define PROC_FCH_HWM_HWMRESET_FILECODE (0xB040) +#define PROC_FCH_HWM_HWMENV_FILECODE (0xB041) +#define PROC_FCH_HWM_HWMMID_FILECODE (0xB042) +#define PROC_FCH_HWM_HWMLATE_FILECODE (0xB043) +#define PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMENVSERVICE_FILECODE (0xB044) +#define PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMMIDSERVICE_FILECODE (0xB045) +#define PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMLATESERVICE_FILECODE (0xB046) +#define PROC_FCH_IDE_IDEENV_FILECODE (0xB050) +#define PROC_FCH_IDE_IDEMID_FILECODE (0xB051) +#define PROC_FCH_IDE_IDELATE_FILECODE (0xB052) +#define PROC_FCH_IMC_IMCENV_FILECODE (0xB060) +#define PROC_FCH_IMC_IMCMID_FILECODE (0xB061) +#define PROC_FCH_IMC_IMCLATE_FILECODE (0xB062) +#define PROC_FCH_IMC_IMCLIB_FILECODE (0xB063) +#define PROC_FCH_IMC_IMCRESET_FILECODE (0xB064) +#define PROC_FCH_IMC_FCHECENV_FILECODE (0xB065) +#define PROC_FCH_IMC_FCHECMID_FILECODE (0xB066) +#define PROC_FCH_IMC_FCHECLATE_FILECODE (0xB067) +#define PROC_FCH_IMC_FCHECRESET_FILECODE (0xB068) +#define PROC_FCH_IMC_FAMILY_HUDSON2_HUDSON2IMCSERVICE_FILECODE (0xB069) +#define PROC_FCH_INTERFACE_INITRESETDEF_FILECODE (0xB070) +#define PROC_FCH_INTERFACE_INITENVDEF_FILECODE (0xB071) +#define PROC_FCH_INTERFACE_FCHINITRESET_FILECODE (0xB072) +#define PROC_FCH_INTERFACE_FCHINITENV_FILECODE (0xB073) +#define PROC_FCH_INTERFACE_FCHINITLATE_FILECODE (0xB074) +#define PROC_FCH_INTERFACE_FCHINITMID_FILECODE (0xB075) +#define PROC_FCH_INTERFACE_FCHINITS3_FILECODE (0xB076) +#define PROC_FCH_INTERFACE_FCHTASKLAUNCHER_FILECODE (0xB077) +#define PROC_FCH_IR_IRENV_FILECODE (0xB080) +#define PROC_FCH_IR_IRMID_FILECODE (0xB081) +#define PROC_FCH_IR_IRLATE_FILECODE (0xB082) +#define PROC_FCH_PCIB_PCIBRESET_FILECODE (0xB090) +#define PROC_FCH_PCIB_PCIBENV_FILECODE (0xB091) +#define PROC_FCH_PCIB_PCIBMID_FILECODE (0xB092) +#define PROC_FCH_PCIB_PCIBLATE_FILECODE (0xB093) +#define PROC_FCH_PCIE_ABRESET_FILECODE (0xB0A0) +#define PROC_FCH_PCIE_ABENV_FILECODE (0xB0A1) +#define PROC_FCH_PCIE_ABMID_FILECODE (0xB0A2) +#define PROC_FCH_PCIE_ABLATE_FILECODE (0xB0A3) +#define PROC_FCH_PCIE_GPPHP_FILECODE (0xB0A4) +#define PROC_FCH_PCIE_GPPLIB_FILECODE (0xB0A5) +#define PROC_FCH_PCIE_GPPRESET_FILECODE (0xB0A6) +#define PROC_FCH_PCIE_GPPENV_FILECODE (0xB0A7) +#define PROC_FCH_PCIE_GPPMID_FILECODE (0xB0A8) +#define PROC_FCH_PCIE_GPPLATE_FILECODE (0xB0A9) +#define PROC_FCH_PCIE_PCIERESET_FILECODE (0xB0AA) +#define PROC_FCH_PCIE_PCIEENV_FILECODE (0xB0AB) +#define PROC_FCH_PCIE_PCIEMID_FILECODE (0xB0AC) +#define PROC_FCH_PCIE_PCIELATE_FILECODE (0xB0AD) +#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABRESETSERVICE_FILECODE (0xB0AE) +#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABENVSERVICE_FILECODE (0xB0AF) +#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABSERVICE_FILECODE (0xB0B0) +#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPRESETSERVICE_FILECODE (0xB0B1) +#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPSERVICE_FILECODE (0xB0B2) +#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIEENVSERVICE_FILECODE (0xB0B3) +#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIESERVICE_FILECODE (0xB0B4) +#define PROC_FCH_SATA_AHCIENV_FILECODE (0xB0C0) +#define PROC_FCH_SATA_AHCIMID_FILECODE (0xB0C1) +#define PROC_FCH_SATA_AHCILATE_FILECODE (0xB0C2) +#define PROC_FCH_SATA_AHCILIB_FILECODE (0xB0C3) +#define PROC_FCH_SATA_IDE2AHCIENV_FILECODE (0xB0C4) +#define PROC_FCH_SATA_IDE2AHCIMID_FILECODE (0xB0C5) +#define PROC_FCH_SATA_IDE2AHCILATE_FILECODE (0xB0C6) +#define PROC_FCH_SATA_IDE2AHCILIB_FILECODE (0xB0C7) +#define PROC_FCH_SATA_RAIDENV_FILECODE (0xB0C8) +#define PROC_FCH_SATA_RAIDMID_FILECODE (0xB0C9) +#define PROC_FCH_SATA_RAIDLATE_FILECODE (0xB0CA) +#define PROC_FCH_SATA_RAIDLIB_FILECODE (0xB0CB) +#define PROC_FCH_SATA_SATAENV_FILECODE (0xB0CC) +#define PROC_FCH_SATA_SATAENVLIB_FILECODE (0xB0CD) +#define PROC_FCH_SATA_SATAIDEENV_FILECODE (0xB0CE) +#define PROC_FCH_SATA_SATAIDEMID_FILECODE (0xB0CF) +#define PROC_FCH_SATA_SATAIDELATE_FILECODE (0xB0D0) +#define PROC_FCH_SATA_SATAIDELIB_FILECODE (0xB0D1) +#define PROC_FCH_SATA_SATAMID_FILECODE (0xB0D2) +#define PROC_FCH_SATA_SATALATE_FILECODE (0xB0D3) +#define PROC_FCH_SATA_SATALIB_FILECODE (0xB0D4) +#define PROC_FCH_SATA_SATARESET_FILECODE (0xB0D5) +#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATARESETSERVICE_FILECODE (0xB0D6) +#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATAENVSERVICE_FILECODE (0xB0D7) +#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATASERVICE_FILECODE (0xB0D8) +#define PROC_FCH_SD_SDENV_FILECODE (0xB0E0) +#define PROC_FCH_SD_SDMID_FILECODE (0xB0E1) +#define PROC_FCH_SD_SDLATE_FILECODE (0xB0E2) +#define PROC_FCH_SD_FAMILY_HUDSON2_HUDSON2SDSERVICE_FILECODE (0xB0E3) +#define PROC_FCH_SD_FAMILY_HUDSON2_HUDSON2SDRESETSERVICE_FILECODE (0xB0E4) +#define PROC_FCH_SD_FAMILY_HUDSON2_HUDSON2SDENVSERVICE_FILECODE (0xB0E5) +#define PROC_FCH_SPI_LPCRESET_FILECODE (0xB0F0) +#define PROC_FCH_SPI_LPCENV_FILECODE (0xB0F1) +#define PROC_FCH_SPI_LPCMID_FILECODE (0xB0F2) +#define PROC_FCH_SPI_LPCLATE_FILECODE (0xB0F3) +#define PROC_FCH_SPI_SPIRESET_FILECODE (0xB0F4) +#define PROC_FCH_SPI_SPIENV_FILECODE (0xB0F5) +#define PROC_FCH_SPI_SPIMID_FILECODE (0xB0F6) +#define PROC_FCH_SPI_SPILATE_FILECODE (0xB0F7) +#define PROC_FCH_SPI_FAMILY_HUDSON2_HUDSON2LPCENVSERVICE_FILECODE (0xB0F8) +#define PROC_FCH_SPI_FAMILY_HUDSON2_HUDSON2LPCRESETSERVICE_FILECODE (0xB0F9) +#define PROC_FCH_SPI_FAMILY_HUDSON2T_HUDSON2TLPCENVSERVICE_FILECODE (0xB0FA) +#define PROC_FCH_SPI_FAMILY_HUDSON2T_HUDSON2TLPCRESETSERVICE_FILECODE (0xB0FB) +#define PROC_FCH_USB_EHCIRESET_FILECODE (0xB100) +#define PROC_FCH_USB_EHCIENV_FILECODE (0xB101) +#define PROC_FCH_USB_EHCIMID_FILECODE (0xB102) +#define PROC_FCH_USB_EHCILATE_FILECODE (0xB103) +#define PROC_FCH_USB_OHCIRESET_FILECODE (0xB104) +#define PROC_FCH_USB_OHCIENV_FILECODE (0xB105) +#define PROC_FCH_USB_OHCIMID_FILECODE (0xB106) +#define PROC_FCH_USB_OHCILATE_FILECODE (0xB107) +#define PROC_FCH_USB_USBRESET_FILECODE (0xB108) +#define PROC_FCH_USB_USBENV_FILECODE (0xB109) +#define PROC_FCH_USB_USBMID_FILECODE (0xB10A) +#define PROC_FCH_USB_USBLATE_FILECODE (0xB10B) +#define PROC_FCH_USB_XHCIRESET_FILECODE (0xB10C) +#define PROC_FCH_USB_XHCIENV_FILECODE (0xB10D) +#define PROC_FCH_USB_XHCIMID_FILECODE (0xB10E) +#define PROC_FCH_USB_XHCILATE_FILECODE (0xB10F) +#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCIENVSERVICE_FILECODE (0xB110) +#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCIMIDSERVICE_FILECODE (0xB111) +#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCILATESERVICE_FILECODE (0xB112) +#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCIENVSERVICE_FILECODE (0xB113) +#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCIMIDSERVICE_FILECODE (0xB114) +#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCILATESERVICE_FILECODE (0xB115) +#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIRESETSERVICE_FILECODE (0xB116) +#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIENVSERVICE_FILECODE (0xB117) +#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIMIDSERVICE_FILECODE (0xB118) +#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCILATESERVICE_FILECODE (0xB119) +#define PROC_FCH_USB_XHCIRECOVERY_FILECODE (0xB124) +#define PROC_FCH_PCIE_GPPPORTINIT_FILECODE (0xB125) + +#define UEFI_DXE_FCHDXE_FCHDXE_FILECODE (0xB200) +#define UEFI_DXE_FCHDXE_USBOC_FILECODE (0xB201) +#define UEFI_DXE_FCHDXEAUX_DXEGPIO_FILECODE (0xB202) +#define UEFI_DXE_FCHDXEAUX_DXEGPIOREAD_FILECODE (0xB203) +#define UEFI_DXE_AMDFCHWHEA_AMDFCHWHEA_FILECODE (0xB210) +#define UEFI_DXE_AMDFCHWHEA_AMDFCHWHEAEINJ_FILECODE (0xB211) +#define UEFI_DXE_AMDFCHWHEA_AMDFCHWHEAHEST_FILECODE (0xB212) +#define UEFI_DXE_FCHDXEAUX_DXEDISUSBPORT_FILECODE (0xB213) +#define UEFI_DXE_FCHDXEAUX_DXEBOOTTIMER_FILECODE (0xB214) +#define UEFI_DXE_FCHDXEAUX_DXEESATAPORT_FILECODE (0xB215) +#define UEFI_DXE_AMDFCHHWM_AMDFCHHWM_FILECODE (0xB216) +#define UEFI_DXE_CF9RESET_CF9RESET_FILECODE (0xB220) +#define UEFI_DXE_CF9RESET_IA32_IA32CF9RESET_FILECODE (0xB221) +#define UEFI_DXE_CF9RESET_X64_X64CF9RESET_FILECODE (0xB222) +#define UEFI_DXE_LEGACYINTERRUPT_LEGACYINTERRUPT_FILECODE (0xB230) +#define UEFI_DXE_SMMCONTROL_SMMCONTROL_FILECODE (0xB240) +#define UEFI_SMM_FCHSMMLIB_FCHDXECOMMON_FILECODE (0xB250) +#define UEFI_SMM_FCHSMMLIB_FCHSMMLIB_FILECODE (0xB251) +#define UEFI_DXE_FCHDXELIB_FCHDXELIB_FILECODE (0xB252) +#define UEFI_PEI_FCHPEI_FCHPEI_FILECODE (0xB260) +#define UEFI_PEI_FCHPEI_FCHRESET_FILECODE (0xB261) +#define UEFI_PEI_FCHPEI_FCHSTALL_FILECODE (0xB262) +#define UEFI_DXE_FCHDXEAUX_FCHDXEAUX_FILECODE (0xB263) +#define UEFI_PEI_FCHPEIAUX_FCHPEIAUX_FILECODE (0xB264) +#define UEFI_PEI_FCHPEILIB_FCHPEILIB_FILECODE (0xB265) +#define UEFI_PEI_FCHPEILIB_LIBAMDPEI_FILECODE (0xB266) +#define UEFI_PEI_FCHPEIAUX_PEIGPIO_FILECODE (0xB267) +#define UEFI_PEI_FCHPEIAUX_PEIGPIOREAD_FILECODE (0xB268) +#define UEFI_PEI_FCHPEIAUX_PEIDISUSBPORT_FILECODE (0xB269) +#define UEFI_PEI_FCHPEIAUX_PEIBOOTTIMER_FILECODE (0xB270) +#define UEFI_PEI_SMBUS_SMBUS_FILECODE (0xB279) +#define UEFI_SMM_FCHSMM_FCHSMM_FILECODE (0xB280) +#define UEFI_SMM_FCHSMMCOMPLEMENT_SDIOPOWER_SDIOPOWER_FILECODE (0xB281) +#define UEFI_SMM_FCHSMMCOMPLEMENT_USB3PORTPROTECTWA_USB3PORTPROTECTWA_FILECODE (0xB282) +#define UEFI_SMM_FCHSMM_GPESMI_FILECODE (0xB283) +#define UEFI_SMM_FCHSMM_IOTRAPSMI_FILECODE (0xB284) +#define UEFI_SMM_FCHSMM_MISCSMI_FILECODE (0xB285) +#define UEFI_SMM_FCHSMM_PERIODICTIMERSMI_FILECODE (0xB286) +#define UEFI_SMM_FCHSMM_POWERBUTTONSMI_FILECODE (0xB287) +#define UEFI_SMM_FCHSMM_SWSMI_FILECODE (0xB288) +#define UEFI_SMM_FCHSMM_SXSMI_FILECODE (0xB289) +#define UEFI_DXE_SMBUS_SMBUSLIGHT_FILECODE (0xB2A0) +#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMDISPATCHER_FILECODE (0xB290) +#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMGPEDISPATCHER_FCHSMMGPEDISPATCHER_FILECODE (0xB292) +#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMIOTRAPDISPATCHER_FCHSMMIOTRAPDISPATCHER_FILECODE (0xB293) +#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMMISCDISPATCHER_FCHSMMMISCDISPATCHER_FILECODE (0xB294) +#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMPERIODICALDISPATCHER_FCHSMMPERIODICALDISPATCHER_FILECODE (0xB295) +#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMPWRBTNDISPATCHER_FCHSMMPWRBTNDISPATCHER_FILECODE (0xB296) +#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMSWDISPATCHER_FCHSMMSWDISPATCHER_FILECODE (0xB297) +#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMSXDISPATCHER_FCHSMMSXDISPATCHER_FILECODE (0xB298) +#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMUSBDISPATCHER_FCHSMMUSBDISPATCHER_FILECODE (0xB299) + +#define LIB_AMDLIB_FILECODE (0xC001) + +#define LEGACY_PROC_AGESACALLOUTS_FILECODE (0xC010) +#define LEGACY_PROC_HOBTRANSFER_FILECODE (0xC011) +#define LEGACY_PROC_DISPATCHER_FILECODE (0xC012) + +#define UEFI_DXE_AMDAGESADXEDRIVER_AMDAGESADXEDRIVER_FILECODE (0xC120) + +#define UEFI_PEI_AMDINITPOSTPEIM_AMDINITPOSTPEIM_FILECODE (0xC140) +#define UEFI_PEI_AMDPROCESSORINITPEIM_AMDPROCESSORINITPEIM_FILECODE (0xC141) +#define UEFI_PEI_AMDRESETMANAGER_AMDRESETMANAGER_FILECODE (0xC142) +#define UEFI_PROC_HOBTRANSFERUEFI_FILECODE (0xC162) + +#define PROC_COMMON_AMDINITEARLY_FILECODE (0xC020) +#define PROC_COMMON_AMDINITENV_FILECODE (0xC021) +#define PROC_COMMON_AMDINITLATE_FILECODE (0xC022) +#define PROC_COMMON_AMDINITMID_FILECODE (0xC023) +#define PROC_COMMON_AMDINITPOST_FILECODE (0xC024) +#define PROC_COMMON_AMDINITRECOVERY_FILECODE (0xC025) +#define PROC_COMMON_AMDINITRESET_FILECODE (0xC026) +#define PROC_COMMON_AMDINITRESUME_FILECODE (0xC027) +#define PROC_COMMON_AMDS3LATERESTORE_FILECODE (0xC028) +#define PROC_COMMON_AMDS3SAVE_FILECODE (0xC029) +#define PROC_COMMON_AMDLATERUNAPTASK_FILECODE (0xC02A) + +#define PROC_COMMON_COMMONRETURNS_FILECODE (0xC0C0) +#define PROC_COMMON_CREATESTRUCT_FILECODE (0xC0D0) +#define PROC_COMMON_COMMONINITS_FILECODE (0xC0F0) +#define PROC_COMMON_S3RESTORESTATE_FILECODE (0xC0F8) +#define PROC_COMMON_S3SAVESTATE_FILECODE (0xC0F9) + +#define PROC_CPU_CPUAPICUTILITIES_FILECODE (0xC401) +#define PROC_CPU_CPUBRANDID_FILECODE (0xC402) +#define PROC_CPU_TABLE_FILECODE (0xC403) +#define PROC_CPU_TABLEHT_FILECODE (0xC404) +#define PROC_CPU_CPUEARLYINIT_FILECODE (0xC405) +#define PROC_CPU_CPUEVENTLOG_FILECODE (0xC406) +#define PROC_CPU_CPUFAMILYTRANSLATION_FILECODE (0xC407) +#define PROC_CPU_CPUGENERALSERVICES_FILECODE (0xC408) +#define PROC_CPU_CPUINITEARLYTABLE_FILECODE (0xC409) +#define PROC_CPU_CPULATEINIT_FILECODE (0xC40A) +#define PROC_CPU_CPUMICROCODEPATCH_FILECODE (0xC40B) +#define PROC_CPU_CPUWARMRESET_FILECODE (0xC40C) +#define PROC_CPU_HEAPMANAGER_FILECODE (0xC40D) +#define PROC_CPU_CPUBIST_FILECODE (0xC40E) +#define PROC_CPU_MMIOMAPMANAGER_FILECODE (0xC40F) + +#define PROC_CPU_CPUPOSTINIT_FILECODE (0xC420) +#define PROC_CPU_CPUPOWERMGMT_FILECODE (0xC430) +#define PROC_CPU_CPUPOWERMGMTMULTISOCKET_FILECODE (0xC431) +#define PROC_CPU_CPUPOWERMGMTSINGLESOCKET_FILECODE (0xC432) +#define PROC_CPU_S3_FILECODE (0xC460) + +// Family 10h +#define PROC_CPU_FAMILY_0X10_CPUCOMMONF10UTILITIES_FILECODE (0xC801) +#define PROC_CPU_FAMILY_0X10_CPUF10BRANDID_FILECODE (0xC802) +#define PROC_CPU_FAMILY_0X10_CPUF10CACHEDEFAULTS_FILECODE (0xC803) +#define PROC_CPU_FAMILY_0X10_CPUF10CACHEFLUSHONHALT_FILECODE (0xC804) +#define PROC_CPU_FAMILY_0X10_CPUF10DMI_FILECODE (0xC805) +#define PROC_CPU_FAMILY_0X10_CPUF10EARLYINIT_FILECODE (0xC806) +#define PROC_CPU_FAMILY_0X10_CPUF10FEATURELEVELING_FILECODE (0xC807) +#define PROC_CPU_FAMILY_0X10_CPUF10HTPHYTABLES_FILECODE (0xC808) +#define PROC_CPU_FAMILY_0X10_CPUF10MSRTABLES_FILECODE (0xC809) +#define PROC_CPU_FAMILY_0X10_CPUF10PCITABLES_FILECODE (0xC80A) +#define PROC_CPU_FAMILY_0X10_CPUF10POWERCHECK_FILECODE (0xC80B) +#define PROC_CPU_FAMILY_0X10_CPUF10POWERMGMTSYSTEMTABLES_FILECODE (0xC80C) +#define PROC_CPU_FAMILY_0X10_CPUF10POWERPLANE_FILECODE (0xC80D) +#define PROC_CPU_FAMILY_0X10_CPUF10SOFTWARETHERMAL_FILECODE (0xC80E) +#define PROC_CPU_FAMILY_0X10_CPUF10UTILITIES_FILECODE (0xC80F) +#define PROC_CPU_FAMILY_0X10_CPUF10WHEAINITDATATABLES_FILECODE (0xC810) +#define PROC_CPU_FAMILY_0X10_CPUF10PSTATE_FILECODE (0xC811) +#define PROC_CPU_FAMILY_0X10_CPUF10CPB_FILECODE (0xC812) +#define PROC_CPU_FAMILY_0X10_CPUF10WORKAROUNDSTABLE_FILECODE (0xC813) +#define PROC_CPU_FAMILY_0X10_F10PMNBCOFVIDINIT_FILECODE (0xC820) +#define PROC_CPU_FAMILY_0X10_F10SINGLELINKPCITABLES_FILECODE (0xC821) +#define PROC_CPU_FAMILY_0X10_F10MULTILINKPCITABLES_FILECODE (0xC822) +#define PROC_CPU_FAMILY_0X10_F10PMNBPSTATEINIT_FILECODE (0xC823) +#define PROC_CPU_FAMILY_0X10_F10PMASYMBOOSTINIT_FILECODE (0xC824) +#define PROC_CPU_FAMILY_0X10_F10INITEARLYTABLE_FILECODE (0xC825) +#define PROC_CPU_FAMILY_0X10_F10PMDUALPLANEONLYSUPPORT_FILECODE (0xC826) +#define PROC_CPU_FAMILY_0X10_F10IOCSTATE_FILECODE (0xC827) +#define PROC_CPU_FAMILY_0X10_REVC_F10REVCUTILITIES_FILECODE (0xC830) +#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHWC1E_FILECODE (0xC831) +#define PROC_CPU_FAMILY_0X10_REVC_F10REVCSWC1E_FILECODE (0xC832) +#define PROC_CPU_FAMILY_0X10_REVC_F10REVCPCITABLES_FILECODE (0xC833) +#define PROC_CPU_FAMILY_0X10_REVC_F10REVCMSRTABLES_FILECODE (0xC834) +#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHTPHYTABLES_FILECODE (0xC835) +#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLHTPHYTABLES_FILECODE (0xC836) +#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLLOGICALIDTABLES_FILECODE (0xC837) +#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMICROCODEPATCHTABLES_FILECODE (0xC838) +#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMSRTABLES_FILECODE (0xC839) +#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLEQUIVALENCETABLE_FILECODE (0xC83A) +#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLPCITABLES_FILECODE (0xC83B) +#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLCACHEFLUSHONHALT_FILECODE (0xC83C) +#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAHTPHYTABLES_FILECODE (0xC83D) +#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DALOGICALIDTABLES_FILECODE (0xC83E) +#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMICROCODEPATCHTABLES_FILECODE (0xC83F) +#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMSRTABLES_FILECODE (0xC840) +#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAEQUIVALENCETABLE_FILECODE (0xC841) +#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAPCITABLES_FILECODE (0xC842) +#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DACACHEFLUSHONHALT_FILECODE (0xC843) +#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBHTPHYTABLES_FILECODE (0xC844) +#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBLOGICALIDTABLES_FILECODE (0xC845) +#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMICROCODEPATCHTABLES_FILECODE (0xC846) +#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMSRTABLES_FILECODE (0xC847) +#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBEQUIVALENCETABLE_FILECODE (0xC848) +#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBPCITABLES_FILECODE (0xC849) +#define PROC_CPU_FAMILY_0X10_REVD_F10REVDUTILITIES_FILECODE (0xC850) +#define PROC_CPU_FAMILY_0X10_REVD_F10REVDMSGBASEDC1E_FILECODE (0xC851) +#define PROC_CPU_FAMILY_0X10_REVD_F10REVDL3FEATURES_FILECODE (0xC852) +#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYHTPHYTABLES_FILECODE (0xC853) +#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYINITEARLYTABLE_FILECODE (0xC854) +#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYLOGICALIDTABLES_FILECODE (0xC855) +#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMICROCODEPATCHTABLES_FILECODE (0xC856) +#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMSRTABLES_FILECODE (0xC857) +#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYEQUIVALENCETABLE_FILECODE (0xC858) +#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYPCITABLES_FILECODE (0xC859) +#define PROC_CPU_FAMILY_0X10_REVE_F10REVEUTILITIES_FILECODE (0xC860) +#define PROC_CPU_FAMILY_0X10_REVE_F10REVEMSRTABLES_FILECODE (0xC861) +#define PROC_CPU_FAMILY_0X10_REVE_F10REVEPCITABLES_FILECODE (0xC862) +#define PROC_CPU_FAMILY_0X10_REVE_F10REVEHTPHYTABLES_FILECODE (0xC863) +#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHEQUIVALENCETABLE_FILECODE (0xC864) +#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHHTPHYTABLES_FILECODE (0xC865) +#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHLOGICALIDTABLES_FILECODE (0xC866) +#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHMICROCODEPATCHTABLES_FILECODE (0xC867) + +// Family 12h +#define PROC_CPU_FAMILY_0X12_CPUCOMMONF12UTILITIES_FILECODE (0xC901) +#define PROC_CPU_FAMILY_0X12_CPUF12BRANDID_FILECODE (0xC902) +#define PROC_CPU_FAMILY_0X12_CPUF12CACHEDEFAULTS_FILECODE (0xC903) +#define PROC_CPU_FAMILY_0X12_CPUF12DMI_FILECODE (0xC904) +#define PROC_CPU_FAMILY_0X12_CPUF12MSRTABLES_FILECODE (0xC905) +#define PROC_CPU_FAMILY_0X12_CPUF12EARLYNBPSTATEINIT_FILECODE (0xC906) +#define PROC_CPU_FAMILY_0X12_CPUF12PCITABLES_FILECODE (0xC907) +#define PROC_CPU_FAMILY_0X12_CPUF12POWERCHECK_FILECODE (0xC908) +#define PROC_CPU_FAMILY_0X12_CPUF12POWERMGMTSYSTEMTABLES_FILECODE (0xC909) +#define PROC_CPU_FAMILY_0X12_CPUF12POWERPLANE_FILECODE (0xC90A) +#define PROC_CPU_FAMILY_0X12_CPUF12SOFTWARETHERMAL_FILECODE (0xC90B) +#define PROC_CPU_FAMILY_0X12_CPUF12UTILITIES_FILECODE (0xC90C) +#define PROC_CPU_FAMILY_0X12_CPUF12WHEAINITDATATABLES_FILECODE (0xC90D) +#define PROC_CPU_FAMILY_0X12_CPUF12PSTATE_FILECODE (0xC90E) +#define PROC_CPU_FAMILY_0X12_F12C6STATE_FILECODE (0xC90F) +#define PROC_CPU_FAMILY_0X12_F12CPB_FILECODE (0xC910) +#define PROC_CPU_FAMILY_0X12_F12IOCSTATE_FILECODE (0xC911) +#define PROC_CPU_FAMILY_0X12_LN_F12LNLOGICALIDTABLES_FILECODE (0xC921) +#define PROC_CPU_FAMILY_0X12_LN_F12LNMICROCODEPATCHTABLES_FILECODE (0xC922) +#define PROC_CPU_FAMILY_0X12_LN_F12LNEQUIVALENCETABLE_FILECODE (0xC923) +#define PROC_CPU_FAMILY_0X12_CPUF12PERCOREPCITABLES_FILECODE (0xC924) +#define PROC_CPU_FAMILY_0X12_LN_F12LNEARLYSAMPLES_FILECODE (0xC925) + +// Family 14h +#define PROC_CPU_FAMILY_0X14_CPUCOMMONF14UTILITIES_FILECODE (0xCA01) +#define PROC_CPU_FAMILY_0X14_CPUF14BRANDID_FILECODE (0xCA02) +#define PROC_CPU_FAMILY_0X14_CPUF14CACHEDEFAULTS_FILECODE (0xCA03) +#define PROC_CPU_FAMILY_0X14_CPUF14DMI_FILECODE (0xCA04) +#define PROC_CPU_FAMILY_0X14_CPUF14MSRTABLES_FILECODE (0xCA05) +#define PROC_CPU_FAMILY_0X14_CPUF14PCITABLES_FILECODE (0xCA06) +#define PROC_CPU_FAMILY_0X14_CPUF14UTILITIES_FILECODE (0xCA07) +#define PROC_CPU_FAMILY_0X14_CPUF14WHEAINITDATATABLES_FILECODE (0xCA08) +#define PROC_CPU_FAMILY_0X14_CPUF14PSTATE_FILECODE (0xCA09) +#define PROC_CPU_FAMILY_0X14_F14IOCSTATE_FILECODE (0xCA0A) +#define PROC_CPU_FAMILY_0X14_CPUF14PERCOREPCITABLES_FILECODE (0xCA0B) + +#define PROC_CPU_FAMILY_0X14_ON_F14ONPOWERPLANE_FILECODE (0xCA21) +#define PROC_CPU_FAMILY_0X14_ON_F14ONC6STATE_FILECODE (0xCA22) +#define PROC_CPU_FAMILY_0X14_ON_F14ONLOGICALIDTABLES_FILECODE (0xCA23) +#define PROC_CPU_FAMILY_0X14_ON_F14ONMICROCODEPATCHTABLES_FILECODE (0xCA24) +#define PROC_CPU_FAMILY_0X14_ON_F14ONEQUIVALENCETABLE_FILECODE (0xCA25) +#define PROC_CPU_FAMILY_0X14_ON_F14ONINITEARLYTABLE_FILECODE (0xCA26) +#define PROC_CPU_FAMILY_0X14_ON_F14ONEARLYSAMPLES_FILECODE (0xCA27) +#define PROC_CPU_FAMILY_0X14_ON_F14ONMSRTABLES_FILECODE (0xCA28) +#define PROC_CPU_FAMILY_0X14_ON_F14ONUTILITIES_FILECODE (0xCA29) +#define PROC_CPU_FAMILY_0X14_ON_F14ONPOWERMGMTSYSTEMTABLES_FILECODE (0xCA2A) +#define PROC_CPU_FAMILY_0X14_ON_F14ONLOWPOWERINIT_FILECODE (0xCA2B) +#define PROC_CPU_FAMILY_0X14_ON_F14ONCPB_FILECODE (0xCA2C) +#define PROC_CPU_FAMILY_0X14_ON_F14ONSOFTWARETHERMAL_FILECODE (0xCA2D) +#define PROC_CPU_FAMILY_0X14_ON_F14ONPOWERCHECK_FILECODE (0xCA2E) + + +// Family 15h +#define PROC_CPU_FAMILY_0X15_CPUCOMMONF15UTILITIES_FILECODE (0xCB01) +#define PROC_CPU_FAMILY_0X15_CPUF15BRANDID_FILECODE (0xCB02) +#define PROC_CPU_FAMILY_0X15_CPUF15CACHEDEFAULTS_FILECODE (0xCB03) +#define PROC_CPU_FAMILY_0X15_CPUF15DMI_FILECODE (0xCB04) +#define PROC_CPU_FAMILY_0X15_CPUF15MSRTABLES_FILECODE (0xCB05) +#define PROC_CPU_FAMILY_0X15_CPUF15PCITABLES_FILECODE (0xCB06) +#define PROC_CPU_FAMILY_0X15_CPUF15POWERCHECK_FILECODE (0xCB07) +#define PROC_CPU_FAMILY_0X15_CPUF15UTILITIES_FILECODE (0xCB08) +#define PROC_CPU_FAMILY_0X15_CPUF15WHEAINITDATATABLES_FILECODE (0xCB09) +#define PROC_CPU_FAMILY_0X15_F15PSTATEHPCMODE_FILECODE (0xCB0A) +#define PROC_CPU_FAMILY_0X15_CPUF15APM_FILECODE (0xCB0B) +#define PROC_CPU_FAMILY_0X15_CPUF15CRAT_FILECODE (0xCB0C) +#define PROC_CPU_FAMILY_0X15_CPUF15MMIOMAP_FILECODE (0xCB0D) + +#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORCOREAFTERRESET_FILECODE (0xCB20) +#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORDMI_FILECODE (0xCB21) +#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORNBAFTERRESET_FILECODE (0xCB22) +#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORPSTATE_FILECODE (0xCB23) +#define PROC_CPU_FAMILY_0X15_OR_F15ORL3FEATURES_FILECODE (0xCB24) +#define PROC_CPU_FAMILY_0X15_OR_F15ORMSGBASEDC1E_FILECODE (0xCB25) +#define PROC_CPU_FAMILY_0X15_OR_F15ORLOGICALIDTABLES_FILECODE (0xCB26) +#define PROC_CPU_FAMILY_0X15_OR_F15ORMICROCODEPATCHTABLES_FILECODE (0xCB27) +#define PROC_CPU_FAMILY_0X15_OR_F15ORMSRTABLES_FILECODE (0xCB28) +#define PROC_CPU_FAMILY_0X15_OR_F15ORSHAREDMSRTABLE_FILECODE (0xCB29) +#define PROC_CPU_FAMILY_0X15_OR_F15OREQUIVALENCETABLE_FILECODE (0xCB2A) +#define PROC_CPU_FAMILY_0X15_OR_F15ORPCITABLES_FILECODE (0xCB2B) +#define PROC_CPU_FAMILY_0X15_OR_F15ORPOWERMGMTSYSTEMTABLES_FILECODE (0xCB2C) +#define PROC_CPU_FAMILY_0X15_OR_F15ORPOWERPLANE_FILECODE (0xCB2D) +#define PROC_CPU_FAMILY_0X15_OR_F15ORUTILITIES_FILECODE (0xCB2E) +#define PROC_CPU_FAMILY_0X15_OR_F15ORWORKAROUNDSTABLE_FILECODE (0xCB2F) +#define PROC_CPU_FAMILY_0X15_OR_F15ORPMNBCOFVIDINIT_FILECODE (0xCB30) +#define PROC_CPU_FAMILY_0X15_OR_F15ORLOWPWRPSTATE_FILECODE (0xCB31) +#define PROC_CPU_FAMILY_0X15_OR_F15ORSINGLELINKPCITABLES_FILECODE (0xCB32) +#define PROC_CPU_FAMILY_0X15_OR_F15ORMULTILINKPCITABLES_FILECODE (0xCB33) +#define PROC_CPU_FAMILY_0X15_OR_F15ORC6STATE_FILECODE (0xCB34) +#define PROC_CPU_FAMILY_0X15_OR_F15OREARLYSAMPLES_FILECODE (0xCB35) +#define PROC_CPU_FAMILY_0X15_OR_F15ORCPB_FILECODE (0xCB36) +#define PROC_CPU_FAMILY_0X15_OR_F15ORIOCSTATE_FILECODE (0xCB37) +#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORCACHEFLUSHONHALT_FILECODE (0xCB38) +#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORFEATURELEVELING_FILECODE (0xCB39) +#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORSOFTWARETHERMAL_FILECODE (0xCB3A) +#define PROC_CPU_FAMILY_0X15_OR_F15ORINITEARLYTABLE_FILECODE (0xCB3B) + +#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNCOREAFTERRESET_FILECODE (0xCB50) +#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNDMI_FILECODE (0xCB51) +#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNNBAFTERRESET_FILECODE (0xCB52) +#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNPSTATE_FILECODE (0xCB53) +#define PROC_CPU_FAMILY_0X15_TN_F15TNLOGICALIDTABLES_FILECODE (0xCB54) +#define PROC_CPU_FAMILY_0X15_TN_F15TNMICROCODEPATCHTABLES_FILECODE (0xCB55) +#define PROC_CPU_FAMILY_0X15_TN_F15TNMSRTABLES_FILECODE (0xCB56) +#define PROC_CPU_FAMILY_0X15_TN_F15TNSHAREDMSRTABLE_FILECODE (0xCB57) +#define PROC_CPU_FAMILY_0X15_TN_F15TNEQUIVALENCETABLE_FILECODE (0xCB58) +#define PROC_CPU_FAMILY_0X15_TN_F15TNPCITABLES_FILECODE (0xCB59) +#define PROC_CPU_FAMILY_0X15_TN_F15TNPOWERMGMTSYSTEMTABLES_FILECODE (0xCB5A) +#define PROC_CPU_FAMILY_0X15_TN_F15TNPOWERPLANE_FILECODE (0xCB5B) +#define PROC_CPU_FAMILY_0X15_TN_F15TNUTILITIES_FILECODE (0xCB5C) +#define PROC_CPU_FAMILY_0X15_TN_F15TNC6STATE_FILECODE (0xCB5D) +#define PROC_CPU_FAMILY_0X15_TN_F15TNCPB_FILECODE (0xCB5E) +#define PROC_CPU_FAMILY_0X15_TN_F15TNIOCSTATE_FILECODE (0xCB5F) +#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNCACHEFLUSHONHALT_FILECODE (0xCB60) +#define PROC_CPU_FAMILY_0X15_TN_F15TNINITEARLYTABLE_FILECODE (0xCB62) +#define PROC_CPU_FAMILY_0X15_TN_F15TNEARLYSAMPLES_FILECODE (0xCB63) +#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNPOWERCHECK_FILECODE (0xCB64) +#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNPSI_FILECODE (0xCB65) +#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNHTC_FILECODE (0xCB66) + +#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVPSI_FILECODE (0xCBF5) + +// Family 16h + +#define PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE (0xDC01) +#define PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE (0xDC02) +#define PROC_CPU_FEATURE_CPUDMI_FILECODE (0xDC10) +#define PROC_CPU_FEATURE_CPUFEATURELEVELING_FILECODE (0xDC20) +#define PROC_CPU_FEATURE_CPUL3FEATURES_FILECODE (0xDC30) +#define PROC_CPU_FEATURE_CPUPSTATEGATHER_FILECODE (0xDC41) +#define PROC_CPU_FEATURE_CPUPSTATELEVELING_FILECODE (0xDC42) +#define PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE (0xDC43) +#define PROC_CPU_FEATURE_CPUSLIT_FILECODE (0xDC50) +#define PROC_CPU_FEATURE_CPUSRAT_FILECODE (0xDC60) +#define PROC_CPU_FEATURE_CPUWHEA_FILECODE (0xDC70) +#define PROC_CPU_FEATURE_CPUHWC1E_FILECODE (0xDC80) +#define PROC_CPU_FEATURE_CPUSWC1E_FILECODE (0xDC81) +#define PROC_CPU_FEATURE_CPUC6STATE_FILECODE (0xDC82) +#define PROC_CPU_FEATURE_CPUCPB_FILECODE (0xDC83) +#define PROC_CPU_FEATURE_CPULOWPWRPSTATE_FILECODE (0xDC84) +#define PROC_CPU_FEATURE_CPUIOCSTATE_FILECODE (0xDC85) +#define PROC_CPU_FEATURE_CPUPSTATEHPCMODE_FILECODE (0xDC86) +#define PROC_CPU_FEATURE_CPUAPM_FILECODE (0xDC87) +#define PROC_CPU_FEATURE_CPUFEATURES_FILECODE (0xDC90) +#define PROC_CPU_FEATURE_CPUMSGBASEDC1E_FILECODE (0xDCA0) +#define PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE (0xDCB0) +#define PROC_CPU_FEATURE_PRESERVEMAILBOX_FILECODE (0xDCC0) +#define PROC_CPU_FEATURE_CPUPSI_FILECODE (0xDCC1) +#define PROC_CPU_FEATURE_CPUHTC_FILECODE (0xDCC2) +#define PROC_CPU_FEATURE_CPUCRAT_FILECODE (0xDCD0) +#define PROC_CPU_FEATURE_CPUCDIT_FILECODE (0xDCD1) + +#define PROC_RECOVERY_CPU_CPURECOVERY_FILECODE (0xDE01) + +#define PROC_HT_FEATURES_HTFEATSETS_FILECODE (0xE001) +#define PROC_HT_FEATURES_HTFEATDYNAMICDISCOVERY_FILECODE (0xE002) +#define PROC_HT_FEATURES_HTFEATGANGING_FILECODE (0xE003) +#define PROC_HT_FEATURES_HTFEATNONCOHERENT_FILECODE (0xE004) +#define PROC_HT_FEATURES_HTFEATOPTIMIZATION_FILECODE (0xE005) +#define PROC_HT_FEATURES_HTFEATROUTING_FILECODE (0xE006) +#define PROC_HT_FEATURES_HTFEATSUBLINKS_FILECODE (0xE007) +#define PROC_HT_FEATURES_HTFEATTRAFFICDISTRIBUTION_FILECODE (0xE008) +#define PROC_HT_FEATURES_HTIDS_FILECODE (0xE009) +#define PROC_HT_HTFEAT_FILECODE (0xE021) +#define PROC_HT_HTINTERFACE_FILECODE (0xE022) +#define PROC_HT_HTINTERFACECOHERENT_FILECODE (0xE023) +#define PROC_HT_HTINTERFACEGENERAL_FILECODE (0xE024) +#define PROC_HT_HTINTERFACENONCOHERENT_FILECODE (0xE025) +#define PROC_HT_HTMAIN_FILECODE (0xE026) +#define PROC_HT_HTNOTIFY_FILECODE (0xE027) +#define PROC_HT_HTGRAPH_HTGRAPH_FILECODE (0xE028) +#define PROC_HT_HTNB_FILECODE (0xE081) +#define PROC_HT_NBCOMMON_HTNBCOHERENT_FILECODE (0xE082) +#define PROC_HT_NBCOMMON_HTNBNONCOHERENT_FILECODE (0xE083) +#define PROC_HT_NBCOMMON_HTNBOPTIMIZATION_FILECODE (0xE084) +#define PROC_HT_NBCOMMON_HTNBUTILITIES_FILECODE (0xE085) +#define PROC_HT_FAM10_HTNBFAM10_FILECODE (0xE0C1) +#define PROC_HT_FAM10_HTNBCOHERENTFAM10_FILECODE (0xE0C2) +#define PROC_HT_FAM10_HTNBNONCOHERENTFAM10_FILECODE (0xE0C3) +#define PROC_HT_FAM10_HTNBOPTIMIZATIONFAM10_FILECODE (0xE0C4) +#define PROC_HT_FAM10_HTNBSYSTEMFAM10_FILECODE (0xE0C5) +#define PROC_HT_FAM10_HTNBUTILITIESFAM10_FILECODE (0xE0C6) +#define PROC_HT_FAM12_HTNBFAM12_FILECODE (0xE101) +#define PROC_HT_FAM12_HTNBUTILITIESFAM12_FILECODE (0xE102) +#define PROC_HT_FAM14_HTNBFAM14_FILECODE (0xE141) +#define PROC_HT_FAM14_HTNBUTILITIESFAM14_FILECODE (0xE142) +#define PROC_HT_FAM15_HTNBFAM15_FILECODE (0xE181) +#define PROC_HT_FAM15_HTNBCOHERENTFAM15_FILECODE (0xE182) +#define PROC_HT_FAM15_HTNBNONCOHERENTFAM15_FILECODE (0xE183) +#define PROC_HT_FAM15_HTNBOPTIMIZATIONFAM15_FILECODE (0xE184) +#define PROC_HT_FAM15_HTNBSYSTEMFAM15_FILECODE (0xE185) +#define PROC_HT_FAM15_HTNBUTILITIESFAM15_FILECODE (0xE186) +#define PROC_HT_FAM15MOD1X_HTNBFAM15MOD1X_FILECODE (0xE187) +#define PROC_HT_FAM15MOD1X_HTNBUTILITIESFAM15MOD1X_FILECODE (0xE188) +#define PROC_HT_FAM14MOD1X_HTNBFAM14MOD1X_FILECODE (0xE189) +#define PROC_HT_FAM14MOD1X_HTNBUTILITIESFAM14MOD1X_FILECODE (0xE18A) +#define PROC_HT_FAM15MOD2X_HTNBFAM15MOD2X_FILECODE (0xE191) +#define PROC_HT_FAM15MOD2X_HTNBCOHERENTFAM15MOD2X_FILECODE (0xE192) +#define PROC_HT_FAM15MOD2X_HTNBNONCOHERENTFAM15MOD2X_FILECODE (0xE193) +#define PROC_HT_FAM15MOD2X_HTNBOPTIMIZATIONFAM15MOD2X_FILECODE (0xE194) +#define PROC_HT_FAM15MOD2X_HTNBSYSTEMFAM15MOD2X_FILECODE (0xE195) +#define PROC_HT_FAM15MOD2X_HTNBUTILITIESFAM15MOD2X_FILECODE (0xE196) + +#define PROC_RECOVERY_HT_HTINITRECOVERY_FILECODE (0xE302) +#define PROC_RECOVERY_HT_HTINITRESET_FILECODE (0xE301) + +#define PROC_IDS_CONTROL_IDSCTRL_FILECODE (0xE801) +#define PROC_IDS_LIBRARY_IDSLIB_FILECODE (0xE802) +#define PROC_IDS_DEBUG_IDSDEBUG_FILECODE (0xE803) +#define PROC_IDS_PERF_IDSPERF_FILECODE (0xE804) +#define PROC_IDS_FAMILY_0X10_IDSF10ALLSERVICE_FILECODE (0xE805) +#define PROC_IDS_FAMILY_0X10_BL_IDSF10BLSERVICE_FILECODE (0xE806) +#define PROC_IDS_FAMILY_0X10_DA_IDSF10DASERVICE_FILECODE (0xE807) +#define PROC_IDS_FAMILY_0X10_HY_IDSF10HYSERVICE_FILECODE (0xE808) +#define PROC_IDS_FAMILY_0X10_RB_IDSF10RBSERVICE_FILECODE (0xE809) +#define PROC_IDS_FAMILY_0X12_IDSF12ALLSERVICE_FILECODE (0xE80A) +#define PROC_IDS_FAMILY_0X14_IDSF14ALLSERVICE_FILECODE (0xE80B) +#define PROC_IDS_FAMILY_0X15_IDSF15ALLSERVICE_FILECODE (0xE80C) +#define PROC_IDS_FAMILY_0X15_OR_IDSF15ORALLSERVICE_FILECODE (0xE80E) +#define PROC_IDS_FAMILY_0X15_TN_IDSF15TNALLSERVICE_FILECODE (0xE80F) +#define PROC_IDS_LIBRARY_IDSREGACC_FILECODE (0xE810) +#define PROC_IDS_DEBUG_IDSDPHDTOUT_FILECODE (0xE811) +#define PROC_IDS_DEBUG_IDSDEBUGPRINT_FILECODE (0xE812) +#define PROC_IDS_DEBUG_IDSDPSERIAL_FILECODE (0xE813) +#define PROC_IDS_DEBUG_IDSDPREDIRECTIO_FILECODE (0xE814) + +#define PROC_IDS_DEBUG_IDSIDTTABLE_FILECODE (0xE81E) +#define PROC_IDS_CONTROL_IDSNVTOCMOS_FILECODE (0xE81F) + +///0xE820 ~ 0xE840 is reserved for ids extend module + +#define PROC_MEM_ARDK_MA_FILECODE (0xF001) +#define PROC_MEM_ARDK_DR_MARDR2_FILECODE (0xF002) +#define PROC_MEM_ARDK_DR_MARDR3_FILECODE (0xF003) +#define PROC_MEM_ARDK_HY_MARHY3_FILECODE (0xF004) +#define PROC_MEM_ARDK_LN_MASLN3_FILECODE (0xF005) +#define PROC_MEM_ARDK_DR_MAUDR3_FILECODE (0xF006) +#define PROC_MEM_ARDK_HY_MAUHY3_FILECODE (0xF007) +#define PROC_MEM_ARDK_LN_MAULN3_FILECODE (0xF008) +#define PROC_MEM_ARDK_DA_MAUDA3_FILECODE (0xF009) +#define PROC_MEM_ARDK_DA_MASDA2_FILECODE (0xF00A) +#define PROC_MEM_ARDK_DA_MASDA3_FILECODE (0xF00B) +#define PROC_MEM_ARDK_NI_MASNI3_FILECODE (0xF00C) +#define PROC_MEM_ARDK_C32_MARC32_3_FILECODE (0xF00D) +#define PROC_MEM_ARDK_C32_MAUC32_3_FILECODE (0xF00E) +#define PROC_MEM_ARDK_NI_MAUNI3_FILECODE (0xF00F) +#define PROC_MEM_ARDK_ON_MASON3_FILECODE (0xF010) +#define PROC_MEM_ARDK_ON_MAUON3_FILECODE (0xF011) +#define PROC_MEM_ARDK_PH_MASPH3_FILECODE (0xF012) +#define PROC_MEM_ARDK_PH_MAUPH3_FILECODE (0xF013) +#define PROC_MEM_ARDK_OR_MAROR3_FILECODE (0xF014) +#define PROC_MEM_ARDK_OR_MAUOR3_FILECODE (0xF017) +#define PROC_MEM_ARDK_RB_MASRB3_FILECODE (0xF018) +#define PROC_MEM_ARDK_RB_MAURB3_FILECODE (0xF019) + +#define PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE (0xF081) +#define PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE (0xF082) +#define PROC_MEM_FEAT_ECC_MFECC_FILECODE (0xF083) +#define PROC_MEM_FEAT_ECC_MFEMP_FILECODE (0xF085) +#define PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE (0xF086) +#define PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE (0xF088) +#define PROC_MEM_FEAT_INTLVRN_MFINTLVRN_FILECODE (0xF089) +#define PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE (0xF08A) +#define PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE (0xF08B) +#define PROC_MEM_FEAT_NDINTLV_MFNDI_FILECODE (0xF08C) +#define PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE (0xF08D) +#define PROC_MEM_FEAT_OLSPARE_MFSPR_FILECODE (0xF08E) +#define PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE (0xF08F) +#define PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE (0xF091) +#define PROC_MEM_FEAT_S3_MFS3_FILECODE (0xF092) +#define PROC_MEM_FEAT_TABLE_MFTDS_FILECODE (0xF093) +#define PROC_MEM_FEAT_CHINTLV_MFMCHI_FILECODE (0xF094) + +#define PROC_MEM_MAIN_MDEF_FILECODE (0xF101) +#define PROC_MEM_MAIN_MINIT_FILECODE (0xF102) +#define PROC_MEM_MAIN_MM_FILECODE (0xF103) +#define PROC_MEM_FEAT_DMI_MFDMI_FILECODE (0xF104) +#define PROC_MEM_MAIN_MMECC_FILECODE (0xF105) +#define PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE (0xF106) +#define PROC_MEM_MAIN_DR_MMFLOWDR_FILECODE (0xF107) +#define PROC_MEM_MAIN_HY_MMFLOWHY_FILECODE (0xF108) +#define PROC_MEM_MAIN_LN_MMFLOWLN_FILECODE (0xF109) +#define PROC_MEM_MAIN_ON_MMFLOWON_FILECODE (0xF10A) +#define PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE (0xF10B) +#define PROC_MEM_MAIN_MMONLINESPARE_FILECODE (0xF10C) +#define PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE (0xF10D) +#define PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE (0xF10E) +#define PROC_MEM_MAIN_MUC_FILECODE (0xF10F) +#define PROC_MEM_MAIN_MMMEMCLR_FILECODE (0xF110) +#define PROC_MEM_MAIN_DA_MMFLOWDA_FILECODE (0xF111) +#define PROC_MEM_MAIN_MMFLOW_FILECODE (0xF112) +#define PROC_MEM_MAIN_MERRHDL_FILECODE (0xF113) +#define PROC_MEM_MAIN_C32_MMFLOWC32_FILECODE (0xF114) +#define PROC_MEM_MAIN_MMLVDDR3_FILECODE (0xF115) +#define PROC_MEM_MAIN_MMUMAALLOC_FILECODE (0xF116) +#define PROC_MEM_MAIN_MMMEMRESTORE_FILECODE (0xF117) +#define PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE (0xF118) +#define PROC_MEM_MAIN_OR_MMFLOWOR_FILECODE (0xF119) +#define PROC_MEM_MAIN_RB_MMFLOWRB_FILECODE (0xF11A) +#define PROC_MEM_MAIN_PH_MMFLOWPH_FILECODE (0xF11B) +#define PROC_MEM_MAIN_TN_MMFLOWTN_FILECODE (0xF11C) + +#define PROC_MEM_NB_DR_MNDR_FILECODE (0XF213) +#define PROC_MEM_NB_DR_MNFLOWDR_FILECODE (0XF214) +#define PROC_MEM_NB_DR_MNIDENDIMMDR_FILECODE (0XF216) +#define PROC_MEM_NB_DR_MNMCTDR_FILECODE (0XF217) +#define PROC_MEM_NB_DR_MNDCTDR_FILECODE (0XF218) +#define PROC_MEM_NB_DR_MNOTDR_FILECODE (0XF219) +#define PROC_MEM_NB_DR_MNPARTRAINDR_FILECODE (0XF21A) +#define PROC_MEM_NB_DR_MNPROTODR_FILECODE (0XF21C) +#define PROC_MEM_NB_DR_MNS3DR_FILECODE (0XF21D) +#define PROC_MEM_NB_DR_MNREGDR_FILECODE (0XF21E) +#define PROC_MEM_NB_RB_MNRB_FILECODE (0XF220) +#define PROC_MEM_NB_RB_MNFLOWRB_FILECODE (0XF221) +#define PROC_MEM_NB_RB_MNS3RB_FILECODE (0XF222) +#define PROC_MEM_NB_RB_MNIDENDIMMRB_FILECODE (0XF223) +#define PROC_MEM_NB_HY_MNFLOWHY_FILECODE (0XF233) +#define PROC_MEM_NB_HY_MNHY_FILECODE (0XF235) +#define PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE (0XF236) +#define PROC_MEM_NB_HY_MNMCTHY_FILECODE (0XF237) +#define PROC_MEM_NB_HY_MNDCTHY_FILECODE (0XF238) +#define PROC_MEM_NB_HY_MNOTHY_FILECODE (0XF239) +#define PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE (0XF23A) +#define PROC_MEM_NB_HY_MNPHYHY_FILECODE (0XF23B) +#define PROC_MEM_NB_HY_MNPROTOHY_FILECODE (0XF23C) +#define PROC_MEM_NB_HY_MNS3HY_FILECODE (0XF23D) +#define PROC_MEM_NB_HY_MNREGHY_FILECODE (0XF23E) +#define PROC_MEM_NB_ON_MNON_FILECODE (0xF240) +#define PROC_MEM_NB_ON_MNREGON_FILECODE (0xF241) +#define PROC_MEM_NB_ON_MNDCTON_FILECODE (0xF242) +#define PROC_MEM_NB_ON_MNIDENDIMMON_FILECODE (0xF244) +#define PROC_MEM_NB_ON_MNMCTON_FILECODE (0xF245) +#define PROC_MEM_NB_ON_MNOTON_FILECODE (0xF246) +#define PROC_MEM_NB_ON_MNPHYON_FILECODE (0xF247) +#define PROC_MEM_NB_ON_MNS3ON_FILECODE (0xF248) +#define PROC_MEM_NB_ON_MNFLOWON_FILECODE (0xF249) +#define PROC_MEM_NB_ON_MNPROTOON_FILECODE (0xF24A) +#define PROC_MEM_NB_LN_MNDCTLN_FILECODE (0XF252) +#define PROC_MEM_NB_LN_MNFLOWLN_FILECODE (0XF253) +#define PROC_MEM_NB_LN_MNIDENDIMMLN_FILECODE (0XF254) +#define PROC_MEM_NB_LN_MNMCTLN_FILECODE (0XF255) +#define PROC_MEM_NB_LN_MNOTLN_FILECODE (0XF256) +#define PROC_MEM_NB_LN_MNPHYLN_FILECODE (0XF257) +#define PROC_MEM_NB_LN_MNPROTOLN_FILECODE (0XF258) +#define PROC_MEM_NB_LN_MNLN_FILECODE (0XF259) +#define PROC_MEM_NB_LN_MNS3LN_FILECODE (0XF25A) +#define PROC_MEM_NB_LN_MNREGLN_FILECODE (0XF25B) +#define PROC_MEM_NB_DA_MNDA_FILECODE (0XF260) +#define PROC_MEM_NB_DA_MNFLOWDA_FILECODE (0XF261) +#define PROC_MEM_NB_DA_MNIDENDIMMDA_FILECODE (0XF263) +#define PROC_MEM_NB_DA_MNMCTDA_FILECODE (0XF264) +#define PROC_MEM_NB_DA_MNDCTDA_FILECODE (0XF265) +#define PROC_MEM_NB_DA_MNOTDA_FILECODE (0XF266) +#define PROC_MEM_NB_DA_MNPARTRAINDA_FILECODE (0XF267) +#define PROC_MEM_NB_DA_MNPROTODA_FILECODE (0XF269) +#define PROC_MEM_NB_DA_MNS3DA_FILECODE (0XF26A) +#define PROC_MEM_NB_DA_MNREGDA_FILECODE (0XF26B) +#define PROC_MEM_NB_C32_MNC32_FILECODE (0XF26C) +#define PROC_MEM_NB_C32_MNDCTC32_FILECODE (0XF26D) +#define PROC_MEM_NB_C32_MNFLOWC32_FILECODE (0XF26E) +#define PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE (0XF26F) +#define PROC_MEM_NB_C32_MNMCTC32_FILECODE (0XF270) +#define PROC_MEM_NB_C32_MNOTC32_FILECODE (0XF271) +#define PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE (0XF272) +#define PROC_MEM_NB_C32_MNPHYC32_FILECODE (0XF273) +#define PROC_MEM_NB_C32_MNPROTOC32_FILECODE (0XF274) +#define PROC_MEM_NB_C32_MNS3C32_FILECODE (0XF275) +#define PROC_MEM_NB_C32_MNREGC32_FILECODE (0XF277) +#define PROC_MEM_NB_MN_FILECODE (0XF27C) +#define PROC_MEM_NB_MNDCT_FILECODE (0XF27D) +#define PROC_MEM_NB_MNPHY_FILECODE (0XF27E) +#define PROC_MEM_NB_MNMCT_FILECODE (0XF27F) +#define PROC_MEM_NB_MNS3_FILECODE (0XF280) +#define PROC_MEM_NB_MNFLOW_FILECODE (0XF281) +#define PROC_MEM_NB_MNFEAT_FILECODE (0XF282) +#define PROC_MEM_NB_MNTRAIN2_FILECODE (0XF283) +#define PROC_MEM_NB_MNTRAIN3_FILECODE (0XF284) +#define PROC_MEM_NB_MNREG_FILECODE (0XF285) +#define PROC_MEM_NB_NI_MNNI_FILECODE (0XF286) +#define PROC_MEM_NB_NI_MNS3NI_FILECODE (0XF287) +#define PROC_MEM_NB_NI_MNFLOWNI_FILECODE (0XF288) +#define PROC_MEM_NB_PH_MNFLOWPH_FILECODE (0XF289) +#define PROC_MEM_NB_PH_MNPH_FILECODE (0XF28A) +#define PROC_MEM_NB_PH_MNS3PH_FILECODE (0XF28B) +#define PROC_MEM_NB_PH_MNIDENDIMMPH_FILECODE (0XF28C) +#define PROC_MEM_NB_OR_MNFLOWOR_FILECODE (0XF290) +#define PROC_MEM_NB_OR_MNOR_FILECODE (0XF291) +#define PROC_MEM_NB_OR_MNIDENDIMMOR_FILECODE (0XF292) +#define PROC_MEM_NB_OR_MNMCTOR_FILECODE (0XF293) +#define PROC_MEM_NB_OR_MNDCTOR_FILECODE (0XF294) +#define PROC_MEM_NB_OR_MNOTOR_FILECODE (0XF295) +#define PROC_MEM_NB_OR_MNPARTRAINOR_FILECODE (0XF296) +#define PROC_MEM_NB_OR_MNPHYOR_FILECODE (0XF297) +#define PROC_MEM_NB_OR_MNPROTOOR_FILECODE (0XF298) +#define PROC_MEM_NB_OR_MNS3OR_FILECODE (0XF299) +#define PROC_MEM_NB_OR_MNREGOR_FILECODE (0XF29A) +#define PROC_MEM_NB_TN_MNREGTN_FILECODE (0XF29B) +#define PROC_MEM_NB_TN_MNTN_FILECODE (0XF29C) +#define PROC_MEM_NB_TN_MNMCTTN_FILECODE (0XF29D) +#define PROC_MEM_NB_TN_MNOTTN_FILECODE (0XF29E) +#define PROC_MEM_NB_TN_MNDCTTN_FILECODE (0XF29F) +#define PROC_MEM_NB_TN_MNPHYTN_FILECODE (0XF2A0) +#define PROC_MEM_NB_TN_MNS3TN_FILECODE (0XF2A1) +#define PROC_MEM_NB_TN_MNIDENDIMMTN_FILECODE (0XF2A2) +#define PROC_MEM_NB_TN_MNFLOWTN_FILECODE (0XF2A3) +#define PROC_MEM_NB_TN_MNPROTOTN_FILECODE (0XF2A4) + + + +#define PROC_MEM_PS_MP_FILECODE (0XF401) +#define PROC_MEM_PS_DR_MPRDR3_FILECODE (0XF402) +#define PROC_MEM_PS_HY_MPRHY3_FILECODE (0XF403) +#define PROC_MEM_PS_LN_MPRLN3_FILECODE (0XF404) +#define PROC_MEM_PS_DR_MPSDR3_FILECODE (0XF405) +#define PROC_MEM_PS_HY_MPSHY3_FILECODE (0XF406) +#define PROC_MEM_PS_LN_MPSLN3_FILECODE (0XF407) +#define PROC_MEM_PS_DR_MPUDR3_FILECODE (0XF408) +#define PROC_MEM_PS_HY_MPUHY3_FILECODE (0XF409) +#define PROC_MEM_PS_LN_MPULN3_FILECODE (0XF40A) +#define PROC_MEM_PS_DA_MPUDA3_FILECODE (0XF40B) +#define PROC_MEM_PS_DA_MPSDA2_FILECODE (0XF40C) +#define PROC_MEM_PS_DA_MPSDA3_FILECODE (0XF40D) +#define PROC_MEM_PS_DR_MPRDR2_FILECODE (0XF40E) +#define PROC_MEM_PS_DR_MPUDR2_FILECODE (0XF40F) +#define PROC_MEM_PS_C32_MPRC32_3_FILECODE (0XF410) +#define PROC_MEM_PS_C32_MPUC32_3_FILECODE (0XF411) +#define PROC_MEM_PS_NI_MPSNI3_FILECODE (0XF412) +#define PROC_MEM_PS_NI_MPUNI3_FILECODE (0XF413) +#define PROC_MEM_PS_ON_MPSON3_FILECODE (0XF414) +#define PROC_MEM_PS_ON_MPUON3_FILECODE (0XF415) +#define PROC_MEM_PS_PH_MPSPH3_FILECODE (0XF416) +#define PROC_MEM_PS_PH_MPUPH3_FILECODE (0XF417) +#define PROC_MEM_PS_RB_MPSRB3_FILECODE (0XF418) +#define PROC_MEM_PS_RB_MPURB3_FILECODE (0XF419) +#define PROC_MEM_PS_OR_AM3_MPUORA3_FILECODE (0XF41A) +#define PROC_MEM_PS_OR_AM3_MPSORA3_FILECODE (0XF41B) +#define PROC_MEM_PS_OR_C32_MPRORC3_FILECODE (0XF41C) +#define PROC_MEM_PS_OR_C32_MPUORC3_FILECODE (0XF41D) +#define PROC_MEM_PS_OR_C32_MPLORC3_FILECODE (0XF41E) +#define PROC_MEM_PS_OR_G34_MPRORG3_FILECODE (0XF41F) +#define PROC_MEM_PS_OR_G34_MPUORG3_FILECODE (0XF420) +#define PROC_MEM_PS_OR_G34_MPLORG3_FILECODE (0XF421) +#define PROC_MEM_PS_MPRTT_FILECODE (0XF422) +#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0XF423) +#define PROC_MEM_PS_MPODTPAT_FILECODE (0XF424) +#define PROC_MEM_PS_MPSAO_FILECODE (0XF425) +#define PROC_MEM_PS_MPMR0_FILECODE (0XF426) +#define PROC_MEM_PS_MPRC2IBT_FILECODE (0XF427) +#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0XF428) +#define PROC_MEM_PS_MPLRIBT_FILECODE (0XF429) +#define PROC_MEM_PS_MPLRNPR_FILECODE (0XF42A) +#define PROC_MEM_PS_MPLRNLR_FILECODE (0XF42B) +#define PROC_MEM_PS_OR_MPOR3_FILECODE (0XF42C) +#define PROC_MEM_PS_TN_MPSTN3_FILECODE (0XF42D) +#define PROC_MEM_PS_TN_MPTN3_FILECODE (0XF42E) +#define PROC_MEM_PS_TN_MPUTN3_FILECODE (0XF42F) +#define PROC_MEM_PS_TN_FM2_MPUTNFM2_FILECODE (0XF430) +#define PROC_MEM_PS_TN_FP2_MPSTNFP2_FILECODE (0XF431) +#define PROC_MEM_PS_TN_FS1_MPSTNFS1_FILECODE (0XF432) +#define PROC_MEM_PS_MPSEEDS_FILECODE (0XF43F) + +#define PROC_MEM_TECH_MT_FILECODE (0XF501) +#define PROC_MEM_TECH_MTHDI_FILECODE (0XF502) +#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0XF504) +#define PROC_MEM_TECH_MTTECC_FILECODE (0XF505) +#define PROC_MEM_TECH_MTTHRC_FILECODE (0XF506) +#define PROC_MEM_TECH_MTTML_FILECODE (0XF507) +#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0XF509) +#define PROC_MEM_TECH_MTTSRC_FILECODE (0XF50B) +#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0XF50C) +#define PROC_MEM_TECH_DDR2_MT2_FILECODE (0XF541) +#define PROC_MEM_TECH_DDR2_MTOT2_FILECODE (0XF543) +#define PROC_MEM_TECH_DDR2_MTSPD2_FILECODE (0XF544) +#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0XF581) +#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0XF583) +#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0XF584) +#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0XF585) +#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0XF586) +#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0XF587) +#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588) +#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0XF589) +#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0XF58A) + +#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0XF801) +#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0XF802) +#define PROC_RECOVERY_MEM_MRM_FILECODE (0XF803) +#define PROC_RECOVERY_MEM_MRUC_FILECODE (0XF804) +#define PROC_RECOVERY_MEM_NB_DR_MRNDR_FILECODE (0XF812) +#define PROC_RECOVERY_MEM_NB_DR_MRNMCTDR_FILECODE (0XF813) +#define PROC_RECOVERY_MEM_NB_HY_MRNDCTHY_FILECODE (0XF821) +#define PROC_RECOVERY_MEM_NB_HY_MRNHY_FILECODE (0XF822) +#define PROC_RECOVERY_MEM_NB_HY_MRNMCTHY_FILECODE (0XF823) +#define PROC_RECOVERY_MEM_NB_HY_MRNPROTOHY_FILECODE (0XF825) +#define PROC_RECOVERY_MEM_NB_LN_MRNDCTLN_FILECODE (0XF831) +#define PROC_RECOVERY_MEM_NB_LN_MRNMCTLN_FILECODE (0XF832) +#define PROC_RECOVERY_MEM_NB_LN_MRNLN_FILECODE (0XF833) +#define PROC_RECOVERY_MEM_NB_DA_MRNDA_FILECODE (0XF842) +#define PROC_RECOVERY_MEM_NB_DA_MRNMCTDA_FILECODE (0XF843) +#define PROC_RECOVERY_MEM_NB_NI_MRNNI_FILECODE (0XF845) +#define PROC_RECOVERY_MEM_NB_C32_MRNC32_FILECODE (0XF851) +#define PROC_RECOVERY_MEM_NB_C32_MRNMCTC32_FILECODE (0XF852) +#define PROC_RECOVERY_MEM_NB_C32_MRNPROTOC32_FILECODE (0XF853) +#define PROC_RECOVERY_MEM_NB_ON_MRNDCTON_FILECODE (0xF861) +#define PROC_RECOVERY_MEM_NB_ON_MRNMCTON_FILECODE (0xF862) +#define PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE (0xF863) +#define PROC_RECOVERY_MEM_NB_PH_MRNPH_FILECODE (0xF871) +#define PROC_RECOVERY_MEM_NB_RB_MRNRB_FILECODE (0xF881) +#define PROC_RECOVERY_MEM_NB_KR_MRNDCTKR_FILECODE (0xF891) +#define PROC_RECOVERY_MEM_NB_KR_MRNMCTKR_FILECODE (0xF892) +#define PROC_RECOVERY_MEM_NB_KR_MRNKR_FILECODE (0xF893) +#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0XF8C1) +#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0XF8C2) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0XF8C3) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0XF8C4) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0XF8C5) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0XF8C6) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0XF8C7) +#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0XF8C8) +#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0XF8C9) +#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0XF8CA) +#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0XF8CB) +#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0XF8CC) +#define PROC_RECOVERY_MEM_NB_OR_MRNDCTOR_FILECODE (0XF8CD) +#define PROC_RECOVERY_MEM_NB_OR_MRNOR_FILECODE (0XF8CE) +#define PROC_RECOVERY_MEM_NB_OR_MRNMCTOR_FILECODE (0XF8CF) +#define PROC_RECOVERY_MEM_NB_OR_MRNPROTOOR_FILECODE (0XF8D0) +#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0XF8E0) +#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0XF8E1) +#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0XF8E2) +#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0XF8E3) +#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0XF8E4) +#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0XF8E5) +#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0XF8E6) +#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0XF8E7) +#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0XF8E8) +#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0XF8E9) +#define PROC_RECOVERY_MEM_NB_TN_MRNDCTTN_FILECODE (0XF8F3) +#define PROC_RECOVERY_MEM_NB_TN_MRNTN_FILECODE (0XF8F4) +#define PROC_RECOVERY_MEM_NB_TN_MRNMCTTN_FILECODE (0XF8F5) +#define PROC_RECOVERY_MEM_NB_TN_MRNPROTOTN_FILECODE (0XF8F6) +#define PROC_RECOVERY_MEM_PS_TN_MRPSTN3_FILECODE (0XF8F7) +#define PROC_RECOVERY_MEM_PS_TN_MRPTN3_FILECODE (0XF8F8) +#define PROC_RECOVERY_MEM_PS_TN_MRPUTN3_FILECODE (0XF8F9) +#define PROC_RECOVERY_MEM_NB_KM_MRNDCTKM_FILECODE (0XF8FA) +#define PROC_RECOVERY_MEM_NB_KM_MRNKM_FILECODE (0XF8FB) +#define PROC_RECOVERY_MEM_NB_KM_MRNMCTKM_FILECODE (0XF8FC) +#define PROC_RECOVERY_MEM_NB_KM_MRNPROTOKM_FILECODE (0XF8FD) +#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE (0XF8FE) + +#endif // _FILECODE_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/GeneralServices.h b/src/vendorcode/amd/agesa/f15tn/Include/GeneralServices.h new file mode 100644 index 0000000..783db6d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/GeneralServices.h @@ -0,0 +1,228 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * General Services + * + * Provides Services similar to the external General Services API, except + * suited to use within AGESA components. Socket, Core and PCI identification. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Common + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _GENERAL_SERVICES_H_ +#define _GENERAL_SERVICES_H_ + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define NUMBER_OF_EVENT_DATA_PARAMS 4 + +/** + * AMD Device id for MMIO check. + */ +#define AMD_DEV_VEN_ID 0x1022 +#define AMD_DEV_VEN_ID_ADDRESS 0 + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *---------------------------------------------------------------------------------------- + */ + +/** + * An AGESA Event Log entry. + */ +typedef struct { + AGESA_STATUS EventClass; ///< The severity of the event, its associated AGESA_STATUS. + UINT32 EventInfo; ///< Uniquely identifies the event. + UINT32 DataParam1; ///< Event specific additional data + UINT32 DataParam2; ///< Event specific additional data + UINT32 DataParam3; ///< Event specific additional data + UINT32 DataParam4; ///< Event specific additional data +} AGESA_EVENT; + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ + +/** + * Get a specified Core's APIC ID. + * + * @param[in] StdHeader Header for library and services. + * @param[in] Socket The Core's Socket. + * @param[in] Core The Core id. + * @param[out] ApicAddress The Core's APIC ID. + * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. + * + * @retval TRUE The core is present, APIC Id valid + * @retval FALSE The core is not present, APIC Id not valid. + */ +BOOLEAN +GetApicId ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT32 Socket, + IN UINT32 Core, + OUT UINT8 *ApicAddress, + OUT AGESA_STATUS *AgesaStatus +); + +/** + * Get Processor Module's PCI Config Space address. + * + * @param[in] StdHeader Header for library and services. + * @param[in] Socket The Core's Socket. + * @param[in] Module The Module in that Processor + * @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0) + * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. + * + * @retval TRUE The core is present, PCI Address valid + * @retval FALSE The core is not present, PCI Address not valid. + */ +BOOLEAN +GetPciAddress ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT32 Socket, + IN UINT32 Module, + OUT PCI_ADDR *PciAddress, + OUT AGESA_STATUS *AgesaStatus +); + +/** + * "Who am I" for the current running core. + * + * @param[in] StdHeader Header for library and services. + * @param[out] Socket The current Core's Socket + * @param[out] Module The current Core's Processor Module + * @param[out] Core The current Core's core id. + * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. + * + */ +VOID +IdentifyCore ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT UINT32 *Socket, + OUT UINT32 *Module, + OUT UINT32 *Core, + OUT AGESA_STATUS *AgesaStatus +); + +/** + * A boolean function determine executed CPU is BSP core. + */ +BOOLEAN +IsBsp ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + OUT AGESA_STATUS *AgesaStatus + ); + +/** + * This function logs AGESA events into the event log. + */ +VOID +PutEventLog ( + IN AGESA_STATUS EventClass, + IN UINT32 EventInfo, + IN UINT32 DataParam1, + IN UINT32 DataParam2, + IN UINT32 DataParam3, + IN UINT32 DataParam4, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * This function gets event logs from the circular buffer. + */ +AGESA_STATUS +GetEventLog ( + OUT AGESA_EVENT *EventRecord, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * This function gets event logs from the circular buffer without flushing the entry. + */ +BOOLEAN +PeekEventLog ( + OUT AGESA_EVENT *EventRecord, + IN UINT16 Index, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------*/ +/** + * This routine programs the registers necessary to get the PCI MMIO mechanism + * up and functioning. + */ +VOID +InitializePciMmio ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif // _GENERAL_SERVICES_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/GnbInterface.h b/src/vendorcode/amd/agesa/f15tn/Include/GnbInterface.h new file mode 100644 index 0000000..3909784 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/GnbInterface.h @@ -0,0 +1,138 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB API definition. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _GNBINTERFACE_H_ +#define _GNBINTERFACE_H_ + +AGESA_STATUS +GnbInitAtReset ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbInitAtEarly ( + IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr + ); + +VOID +GnbInitDataStructAtPostDef ( + IN OUT GNB_POST_CONFIGURATION *GnbPostConfigPtr, + IN AMD_POST_PARAMS *PostParamsPtr + ); + +AGESA_STATUS +GnbInitAtPost ( + IN OUT AMD_POST_PARAMS *PostParamsPtr + ); + +VOID +GnbInitDataStructAtEnvDef ( + IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr, + IN AMD_ENV_PARAMS *EnvParamsPtr + ); + +AGESA_STATUS +GnbInitAtEnv ( + IN AMD_ENV_PARAMS *EnvParamsPtr + ); + +AGESA_STATUS +GnbInitAtMid ( + IN OUT AMD_MID_PARAMS *MidParamsPtr + ); + +AGESA_STATUS +GnbInitAtLate ( + IN OUT AMD_LATE_PARAMS *LateParamsPtr + ); + +AGESA_STATUS +GnbInitAtPostAfterDram ( + IN OUT AMD_POST_PARAMS *PostParamsPtr + ); + +AGESA_STATUS +AmdGnbRecovery ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbInitAtEarlier ( + IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr + ); + +AGESA_STATUS +GnbInitAtS3Save ( + IN OUT AMD_S3SAVE_PARAMS *AmdS3SaveParams + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Include/GnbPage.h b/src/vendorcode/amd/agesa/f15tn/Include/GnbPage.h new file mode 100644 index 0000000..9c051c5 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/GnbPage.h @@ -0,0 +1,2020 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Create outline and references for GNB Component mainpage documentation. + * + * Design guides, maintenance guides, and general documentation, are + * collected using this file onto the documentation mainpage. + * This file contains doxygen comment blocks, only. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Documentation + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + + +/** + * @page gnbmain GNB Component Documentation + * + * Additional documentation for the GNB component consists of + * + * - Maintenance Guides: + * - @subpage F12PcieLaneDescription "Family 0x12 PCIe/DDI Lane description table" + * - @subpage F14ONPcieLaneDescription "Family 0x14(ON) PCIe/DDI Lane description table" + * - @subpage F12LaneConfigurations "Family 0x12 PCIe port/DDI link configurations" + * - @subpage F14ONLaneConfigurations "Family 0x14(ON) PCIe port/DDI link configurations" + * - @subpage F12DualLinkDviDescription "Family 0x12 Dual Link DVI connector description" + * - add here >>> + * - Design Guides: + * - @subpage BuildConfigDescription "Build Configurations" + * - add here >>> + * + */ + + +/** + * @page F12PcieLaneDescription Family 0x12 PCIe/DDI Lanes + * <TABLE border="0"> + * <TR><TD class="indexkey" width=160> Lane ID</TD><TD class="indexkey">Lane group</TD><TD class="indexkey">Pin</TD></TR> + * <TR><TD class="indexvalue" > 0 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][0]</TD></TR> + * <TR><TD class="indexvalue" > 1 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][1]</TD></TR> + * <TR><TD class="indexvalue" > 2 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][2]</TD></TR> + * <TR><TD class="indexvalue" > 3 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][3]</TD></TR> + * <TR><TD class="indexvalue" > 4 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][0]</TD></TR> + * <TR><TD class="indexvalue" > 5 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][1]</TD></TR> + * <TR><TD class="indexvalue" > 6 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][2]</TD></TR> + * <TR><TD class="indexvalue" > 7 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][3]</TD></TR> + * <TR><TD class="indexvalue" > 8 </TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][0]</TD></TR> + * <TR><TD class="indexvalue" > 9 </TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][1]</TD></TR> + * <TR><TD class="indexvalue" > 10</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][2]</TD></TR> + * <TR><TD class="indexvalue" > 11</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][3]</TD></TR> + * <TR><TD class="indexvalue" > 12</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][4]</TD></TR> + * <TR><TD class="indexvalue" > 13</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][5]</TD></TR> + * <TR><TD class="indexvalue" > 14</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][6]</TD></TR> + * <TR><TD class="indexvalue" > 15</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][7]</TD></TR> + * <TR><TD class="indexvalue" > 16</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][8]</TD></TR> + * <TR><TD class="indexvalue" > 17</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][9]</TD></TR> + * <TR><TD class="indexvalue" > 18</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][10]</TD></TR> + * <TR><TD class="indexvalue" > 19</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][11]</TD></TR> + * <TR><TD class="indexvalue" > 20</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][12]</TD></TR> + * <TR><TD class="indexvalue" > 21</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][13]</TD></TR> + * <TR><TD class="indexvalue" > 22</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][14]</TD></TR> + * <TR><TD class="indexvalue" > 23</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][15]</TD></TR> + * <TR><TD class="indexvalue" > 24</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[0]</TD></TR> + * <TR><TD class="indexvalue" > 25</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[1]</TD></TR> + * <TR><TD class="indexvalue" > 26</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[2]</TD></TR> + * <TR><TD class="indexvalue" > 27</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[3]</TD></TR> + * <TR><TD class="indexvalue" > 28</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[0]</TD></TR> + * <TR><TD class="indexvalue" > 29</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[1]</TD></TR> + * <TR><TD class="indexvalue" > 30</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[2]</TD></TR> + * <TR><TD class="indexvalue" > 31</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[3]</TD></TR> + * </TABLE> + * + */ + + +/** + * @page F14ONPcieLaneDescription Family 0x14(ON) PCIe/DDI Lanes + * <TABLE border="0"> + * <TR><TD class="indexkey" width=160> Lane ID</TD><TD class="indexkey">Lane group</TD><TD class="indexkey">Pin</TD></TR> + * <TR><TD class="indexvalue" > 0 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][0]</TD></TR> + * <TR><TD class="indexvalue" > 1 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][1]</TD></TR> + * <TR><TD class="indexvalue" > 2 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][2]</TD></TR> + * <TR><TD class="indexvalue" > 3 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][3]</TD></TR> + * <TR><TD class="indexvalue" > 4 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][0]</TD></TR> + * <TR><TD class="indexvalue" > 5 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][1]</TD></TR> + * <TR><TD class="indexvalue" > 6 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][2]</TD></TR> + * <TR><TD class="indexvalue" > 7 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][3]</TD></TR> + * <TR><TD class="indexvalue" > 8</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[0]</TD></TR> + * <TR><TD class="indexvalue" > 9</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[1]</TD></TR> + * <TR><TD class="indexvalue" > 10</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[2]</TD></TR> + * <TR><TD class="indexvalue" > 11</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[3]</TD></TR> + * <TR><TD class="indexvalue" > 12</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[0]</TD></TR> + * <TR><TD class="indexvalue" > 13</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[1]</TD></TR> + * <TR><TD class="indexvalue" > 14</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[2]</TD></TR> + * <TR><TD class="indexvalue" > 15</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[3]</TD></TR> + * </TABLE> + * + */ + + +/** + * @page F12DualLinkDviDescription Family 0x12 Dual Link DVI connector description + * Examples of various Dual Link DVI descriptors. + * @code + * // Dual Link DVI on dedicated display lanes. DP1_TXP/N[0]..DP1_TXP/N[3] - master, DP0_TXP/N[0]..DP0_TXP/N[3] - slave. + * PCIe_PORT_DESCRIPTOR DdiList [] = { + * { + * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags + * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 32), + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) + * } + * } + * // Dual Link DVI on dedicated display lanes. DP0_TXP/N[0]..DP0_TXP/N[3] - master, DP1_TXP/N[0]..DP1_TXP/N[3] - slave. + * PCIe_PORT_DESCRIPTOR DdiList [] = { + * { + * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags + * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 24), + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) + * } + * } + * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - master, P_GFX_TXP/N[4]..P_GFX_TXP/N[7] - slave. + * PCIe_PORT_DESCRIPTOR DdiList [] = { + * { + * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags + * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 15), + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) + * } + * } + * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[7]..P_GFX_TXP/N[4] - master, P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - slave. + * PCIe_PORT_DESCRIPTOR DdiList [] = { + * { + * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags + * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 15, 8), + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) + * } + * } + * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - master, P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - slave. + * PCIe_PORT_DESCRIPTOR DdiList [] = { + * { + * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags + * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 23), + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) + * } + * } + * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - master, P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - slave. + * PCIe_PORT_DESCRIPTOR DdiList [] = { + * { + * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags + * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 23, 16), + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) + * } + * } + * @endcode + */ + +/** + * @page F12LaneConfigurations Family 0x12 PCIe port/DDI link configurations + * <div class=WordSection1> + * + * <p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>PCIe port + * configurations for lane 8 through 23. </span></p> + * + * <table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0 + * style='border-collapse:collapse;border:none'> + * <tr> + * <td width=167 valign=top style='width:125.25pt;border:solid windowtext 1.5pt; + * background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Configuration</p> + * </td> + * <td width=132 valign=top style='width:99.0pt;border:solid windowtext 1.5pt; + * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>PCIe Port Device Number</p> + * </td> + * <td width=180 valign=top style='width:135.0pt;border:solid windowtext 1.5pt; + * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Start Lane (Start Lane in reverse + * configuration)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border:solid windowtext 1.5pt; + * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>End Line (End lane in reverse + * configuration)</p> + * </td> + * </tr> + * <tr> + * <td width=167 rowspan=29 valign=top style='width:125.25pt;border-top:none; + * border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt; + * border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Config A*</p> + * </td> + * <td width=132 rowspan=15 valign=top style='width:99.0pt;border-top:none; + * border-left:none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>2</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'> </p> + * </td> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>8(23)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>23(8)</p> + * </td> + * </tr> + * <tr> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>8(15)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>15(8)</p> + * </td> + * </tr> + * <tr> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>8(11)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>11(8)</p> + * </td> + * </tr> + * <tr> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>8(9)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>9(8)</p> + * </td> + * </tr> + * <tr> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>10(11)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>11(10)</p> + * </td> + * </tr> + * <tr> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>12(15)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>15(12)</p> + * </td> + * </tr> + * <tr> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>12(13)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>13(12)</p> + * </td> + * </tr> + * <tr style='height:15.25pt'> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:15.25pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>14(15)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:15.25pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>15(14)</p> + * </td> + * </tr> + * <tr> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>16(23)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>23(16)</p> + * </td> + * </tr> + * <tr> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>16(19)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>19(16)</p> + * </td> + * </tr> + * <tr> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>16(17)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>17(16)</p> + * </td> + * </tr> + * <tr> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>18(19)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>19(18)</p> + * </td> + * </tr> + * <tr> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>20(23)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>23(20)</p> + * </td> + * </tr> + * <tr> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>20(21)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>21(20)</p> + * </td> + * </tr> + * <tr style='height:15.25pt'> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:15.25pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>22(23)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:15.25pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>23(22)</p> + * </td> + * </tr> + * <tr> + * <td width=132 rowspan=14 valign=top style='width:99.0pt;border-top:none; + * border-left:none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>3</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'> </p> + * </td> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>8(15)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>15(8)</p> + * </td> + * </tr> + * <tr> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>8(11)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>11(8)</p> + * </td> + * </tr> + * <tr> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>8(9)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>9(8)</p> + * </td> + * </tr> + * <tr> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>10(11)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>11(10)</p> + * </td> + * </tr> + * <tr> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>12(15)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>15(12)</p> + * </td> + * </tr> + * <tr> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>12(13)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>13(12)</p> + * </td> + * </tr> + * <tr> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>14(15)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>15(14)</p> + * </td> + * </tr> + * <tr style='height:15.25pt'> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:15.25pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>16(23)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:15.25pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>23(16)</p> + * </td> + * </tr> + * <tr> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>16(19)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>19(16)</p> + * </td> + * </tr> + * <tr> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>16(17)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>17(16)</p> + * </td> + * </tr> + * <tr> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>18(19)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>19(18)</p> + * </td> + * </tr> + * <tr> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>20(23)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>23(20)</p> + * </td> + * </tr> + * <tr> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>20(21)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>21(20)</p> + * </td> + * </tr> + * <tr> + * <td width=180 valign=top style='width:135.0pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>22(23)</p> + * </td> + * <td width=162 valign=top style='width:121.5pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>23(22)</p> + * </td> + * </tr> + * <tr> + * <td width=641 colspan=4 valign=top style='width:480.75pt;border:solid windowtext 1.5pt; + * border-top:none;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: + * normal'>* Lanes selection for port 2/3 should not overlap in port configuration</p> + * </td> + * </tr> + * </table> + * + * <p class=MsoNormal> </p> + * + * <p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>PCIe port + * configurations for lane 4 through 7.</span></p> + * + * <table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0 + * style='border-collapse:collapse;border:none'> + * <tr> + * <td width=167 valign=top style='width:125.0pt;border:solid windowtext 1.5pt; + * background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: + * normal'>Configuration</p> + * </td> + * <td width=135 valign=top style='width:100.9pt;border:solid windowtext 1.5pt; + * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>PCIe Port Device Number</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border:solid windowtext 1.5pt; + * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Start Lane (Start Lane in reverse + * configuration)</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border:solid windowtext 1.5pt; + * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>End Line (End lane in reverse + * configuration)</p> + * </td> + * </tr> + * <tr> + * <td width=167 rowspan=3 valign=top style='width:125.0pt;border:solid windowtext 1.5pt; + * border-top:none;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: + * normal'>Config A</p> + * </td> + * <td width=135 rowspan=3 valign=top style='width:100.9pt;border-top:none; + * border-left:none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4(7)</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>7(4)</p> + * </td> + * </tr> + * <tr> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4(5)</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>5(4)</p> + * </td> + * </tr> + * <tr> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4</p> + * </td> + * </tr> + * <tr> + * <td width=167 rowspan=4 valign=top style='width:125.0pt;border-top:none; + * border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt; + * border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: + * normal'>Config B</p> + * </td> + * <td width=135 rowspan=2 valign=top style='width:100.9pt;border-top:none; + * border-left:none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4(5)</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>5(4)</p> + * </td> + * </tr> + * <tr> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4</p> + * </td> + * </tr> + * <tr> + * <td width=135 rowspan=2 valign=top style='width:100.9pt;border-top:none; + * border-left:none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>5 or 6</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>6(7)</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>7(6)</p> + * </td> + * </tr> + * <tr> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>6</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>6</p> + * </td> + * </tr> + * <tr> + * <td width=167 rowspan=4 valign=top style='width:125.0pt;border-top:none; + * border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt; + * border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: + * normal'>Config C</p> + * </td> + * <td width=135 rowspan=2 valign=top style='width:100.9pt;border-top:none; + * border-left:none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4(5)</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>5(4)</p> + * </td> + * </tr> + * <tr> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4</p> + * </td> + * </tr> + * <tr> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>5 or 6</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>6</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>6</p> + * </td> + * </tr> + * <tr> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>6 or 7</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>7</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>7</p> + * </td> + * </tr> + * <tr> + * <td width=167 rowspan=4 valign=top style='width:125.0pt;border:solid windowtext 1.5pt; + * border-top:none;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: + * normal'>Config D</p> + * </td> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4</p> + * </td> + * </tr> + * <tr> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>5</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>5</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>5</p> + * </td> + * </tr> + * <tr> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>6</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>6</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>6</p> + * </td> + * </tr> + * <tr> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>7</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>7</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>7</p> + * </td> + * </tr> + * </table> + * + * <p class=MsoNormal> </p> + * + * <p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>DDI link + * configurations for lanes 24 through 31.</span></p> + * + * <table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0 + * style='border-collapse:collapse;border:none'> + * <tr> + * <td width=167 valign=top style='width:125.0pt;border:solid windowtext 1.5pt; + * background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: + * normal'>Configuration</p> + * </td> + * <td width=135 valign=top style='width:100.9pt;border:solid windowtext 1.5pt; + * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Connector type</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border:solid windowtext 1.5pt; + * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Start Lane (Start Lane in reverse + * configuration)</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border:solid windowtext 1.5pt; + * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>End Line (End lane in reverse + * configuration)</p> + * </td> + * </tr> + * <tr style='height:28.35pt'> + * <td width=167 valign=top style='width:125.0pt;border-top:none;border-left: + * solid windowtext 1.5pt;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:28.35pt'> + * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: + * normal'>Config A</p> + * </td> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:28.35pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Dual Link DVI-D</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:28.35pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>24(31)</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:28.35pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>31(24)</p> + * </td> + * </tr> + * <tr style='height:95.0pt'> + * <td width=167 rowspan=2 valign=top style='width:125.0pt;border:solid windowtext 1.5pt; + * border-top:none;padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: + * normal'>Config B</p> + * </td> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>HDMI</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Single Link DVI-D</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>DP </p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>eDP</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Travis DP-to-CRT</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Travis DP-to-LVDS</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Hudson2 DP-to-CRT </p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>24</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>27</p> + * </td> + * </tr> + * <tr style='height:95.0pt'> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>HDMI</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Single Link DVI-D</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>DP </p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>eDP</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Travis DP-to-CRT</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Travis DP-to-LVDS</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>28</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>31</p> + * </td> + * </tr> + * </table> + * + * <p class=MsoNormal> </p> + * + * <p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>DDI link + * configurations for lanes 8 through 23.</span></p> + * + * <table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0 + * style='border-collapse:collapse;border:none'> + * <tr> + * <td width=167 valign=top style='width:125.0pt;border:solid windowtext 1.5pt; + * background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: + * normal'>Configuration</p> + * </td> + * <td width=135 valign=top style='width:100.9pt;border:solid windowtext 1.5pt; + * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Connector type</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border:solid windowtext 1.5pt; + * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Start Lane (Start Lane in reverse + * configuration)</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border:solid windowtext 1.5pt; + * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>End Line (End lane in reverse + * configuration)</p> + * </td> + * </tr> + * <tr style='height:17.85pt'> + * <td width=167 rowspan=2 valign=top style='width:125.0pt;border-top:none; + * border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt; + * border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt;height:17.85pt'> + * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: + * normal'>Config A</p> + * </td> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:17.85pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Dual Link DVI-D</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:17.85pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>8(15)</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:17.85pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>15(8)</p> + * </td> + * </tr> + * <tr style='height:16.5pt'> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:16.5pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Dual Link DVI-D</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:16.5pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>16(23)</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:16.5pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>23(16)</p> + * </td> + * </tr> + * <tr style='height:16.5pt'> + * <td width=167 rowspan=3 valign=top style='width:125.0pt;border-top:none; + * border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt; + * border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt;height:16.5pt'> + * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: + * normal'>Config B</p> + * </td> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:16.5pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Dual Link DVI-D</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:16.5pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>8(15)</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:16.5pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>15(8)</p> + * </td> + * </tr> + * <tr style='height:95.0pt'> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>HDMI</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Single Link DVI-D</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>DP </p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>eDP</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Travis DP-to-CRT</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Travis DP-to-LVDS</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>16</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>19</p> + * </td> + * </tr> + * <tr style='height:95.0pt'> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>HDMI</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Single Link DVI-D</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>DP </p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>eDP</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Travis DP-to-CRT</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Travis DP-to-LVDS</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>20</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>23</p> + * </td> + * </tr> + * <tr style='height:93.0pt'> + * <td width=167 rowspan=3 valign=top style='width:125.0pt;border-top:none; + * border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt; + * border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt;height:93.0pt'> + * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: + * normal'>Config C</p> + * </td> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:93.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>HDMI</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Single Link DVI-D</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>DP </p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>eDP</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Travis DP-to-CRT</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Travis DP-to-LVDS</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:93.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>8</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:93.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>11</p> + * </td> + * </tr> + * <tr style='height:95.0pt'> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>HDMI</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Single Link DVI-D</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>DP </p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>eDP</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Travis DP-to-CRT</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Travis DP-to-LVDS</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>12</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>15</p> + * </td> + * </tr> + * <tr style='height:18.3pt'> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:18.3pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Dual Link DVI-D</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:18.3pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>16(23)</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:18.3pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>23(16)</p> + * </td> + * </tr> + * <tr style='height:95.0pt'> + * <td width=167 rowspan=4 valign=top style='width:125.0pt;border:solid windowtext 1.5pt; + * border-top:none;padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: + * normal'>Config D</p> + * </td> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>HDMI</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Single Link DVI-D</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>DP </p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>eDP</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Travis DP-to-CRT</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Travis DP-to-LVDS</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Hudson2 DP-to-CRT </p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>8</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>11</p> + * </td> + * </tr> + * <tr style='height:95.0pt'> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>HDMI</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Single Link DVI-D</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>DP </p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>eDP</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Travis DP-to-CRT</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Travis DP-to-LVDS</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>12</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>15</p> + * </td> + * </tr> + * <tr style='height:95.0pt'> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>HDMI</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Single Link DVI-D</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>DP </p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>eDP</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Travis DP-to-CRT</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Travis DP-to-LVDS</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Hudson2 DP-to-CRT </p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>16</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>19</p> + * </td> + * </tr> + * <tr style='height:95.0pt'> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>HDMI</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Single Link DVI-D</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>DP </p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>eDP</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Travis DP-to-CRT</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Travis DP-to-LVDS</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>20</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>23</p> + * </td> + * </tr> + * </table> + * + * <p class=MsoNormal> </p> + * </div> + */ + +/** + * @page F14ONLaneConfigurations Family 0x14(ON) PCIe port/DDI link configurations + * <div class=WordSection1> + * <p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>PCIe port + * configurations for lane 4 through 7.</span></p> + * + * <table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0 + * style='border-collapse:collapse;border:none'> + * <tr> + * <td width=167 valign=top style='width:125.0pt;border:solid windowtext 1.5pt; + * background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: + * normal'>Configuration</p> + * </td> + * <td width=135 valign=top style='width:100.9pt;border:solid windowtext 1.5pt; + * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>PCIe Port Device Number</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border:solid windowtext 1.5pt; + * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Start Lane (Start Lane in reverse + * configuration)</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border:solid windowtext 1.5pt; + * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>End Line (End lane in reverse + * configuration)</p> + * </td> + * </tr> + * <tr> + * <td width=167 rowspan=3 valign=top style='width:125.0pt;border:solid windowtext 1.5pt; + * border-top:none;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: + * normal'>Config A</p> + * </td> + * <td width=135 rowspan=3 valign=top style='width:100.9pt;border-top:none; + * border-left:none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4(7)</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>7(4)</p> + * </td> + * </tr> + * <tr> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4(5)</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>5(4)</p> + * </td> + * </tr> + * <tr> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4</p> + * </td> + * </tr> + * <tr> + * <td width=167 rowspan=4 valign=top style='width:125.0pt;border-top:none; + * border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt; + * border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: + * normal'>Config B</p> + * </td> + * <td width=135 rowspan=2 valign=top style='width:100.9pt;border-top:none; + * border-left:none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4(5)</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>5(4)</p> + * </td> + * </tr> + * <tr> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4</p> + * </td> + * </tr> + * <tr> + * <td width=135 rowspan=2 valign=top style='width:100.9pt;border-top:none; + * border-left:none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>5 or 6</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>6(7)</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>7(6)</p> + * </td> + * </tr> + * <tr> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>6</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>6</p> + * </td> + * </tr> + * <tr> + * <td width=167 rowspan=4 valign=top style='width:125.0pt;border-top:none; + * border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt; + * border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: + * normal'>Config C</p> + * </td> + * <td width=135 rowspan=2 valign=top style='width:100.9pt;border-top:none; + * border-left:none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4(5)</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>5(4)</p> + * </td> + * </tr> + * <tr> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4</p> + * </td> + * </tr> + * <tr> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>5 or 6</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>6</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>6</p> + * </td> + * </tr> + * <tr> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>6 or 7</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>7</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>7</p> + * </td> + * </tr> + * <tr> + * <td width=167 rowspan=4 valign=top style='width:125.0pt;border:solid windowtext 1.5pt; + * border-top:none;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: + * normal'>Config D</p> + * </td> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>4</p> + * </td> + * </tr> + * <tr> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>5</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>5</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>5</p> + * </td> + * </tr> + * <tr> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>6</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>6</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>6</p> + * </td> + * </tr> + * <tr> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>7</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>7</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>7</p> + * </td> + * </tr> + * </table> + * + * <p class=MsoNormal> </p> + * + * <p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>CRT/DDI link + * configurations for lanes 8 through 19.</span></p> + * + * <table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0 + * style='border-collapse:collapse;border:none'> + * <tr> + * <td width=167 valign=top style='width:125.0pt;border:solid windowtext 1.5pt; + * background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: + * normal'>Configuration</p> + * </td> + * <td width=135 valign=top style='width:100.9pt;border:solid windowtext 1.5pt; + * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Connector type</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border:solid windowtext 1.5pt; + * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Start Lane (Start Lane in reverse + * configuration)</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border:solid windowtext 1.5pt; + * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>End Line (End lane in reverse + * configuration)</p> + * </td> + * </tr> + * <tr style='height:95.0pt'> + * <td width=167 rowspan=3 valign=top style='width:125.0pt;border-top:none; + * border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt; + * border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: + * normal'>Config A</p> + * </td> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>HDMI</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Single Link DVI-D</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Single Link DVI-I*</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>DP </p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>eDP</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Travis DP-to-CRT</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Travis DP-to-LVDS</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Hudson2 DP-to-CRT </p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>8</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>11</p> + * </td> + * </tr> + * <tr style='height:95.0pt'> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>HDMI</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Single Link DVI-D</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Single Link DVI-I*</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>DP </p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>eDP</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Travis DP-to-CRT</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Travis DP-to-LVDS</p> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>12</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>15</p> + * </td> + * </tr> + * <tr style='height:95.0pt'> + * <td width=135 valign=top style='width:100.9pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>CRT*</p> + * </td> + * <td width=179 valign=top style='width:134.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>16</p> + * </td> + * <td width=158 valign=top style='width:118.45pt;border-top:none;border-left: + * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt; + * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'> + * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt; + * text-align:center;line-height:normal'>19</p> + * </td> + * </tr> + * <tr style='height:35.85pt'> + * <td width=638 colspan=4 valign=top style='width:6.65in;border:solid windowtext 1.5pt; + * border-top:none;padding:0in 5.4pt 0in 5.4pt;height:35.85pt'> + * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height: + * normal'>* - Only one connector of this time can exist in configuration</p> + * </td> + * </tr> + * </table> + * + * <p class=MsoNormal> </p> + * + * <p class=MsoNormal> </p> + * + * </div> + */ + + /** + * @page BuildConfigDescription GNB Build Configurations. + * + * Build configurations are configuration constants. The purpose + * of build configurations is to specify configuration info + * regarding the GNB component. + * + * The documented build configurations are imported from a user + * controlled file for processing. The build configurations for + * all platform solutions are listed below: + * + * @anchor BLDCFG_USE_SYNCFLOOD_AS_NMI + * @li @e BLDCFG_USE_SYNCFLOOD_AS_NMI @n + * This build configuration defines the function of the + * SYNCFLOOD/NMI# pin. If TRUE, then the pin is defined + * as NMI#. If FALSE or undefined, the pin is defined as + * SYNCFLOOD_L. + * + */ + diff --git a/src/vendorcode/amd/agesa/f15tn/Include/Ids.h b/src/vendorcode/amd/agesa/f15tn/Include/Ids.h new file mode 100644 index 0000000..a19d80d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/Ids.h @@ -0,0 +1,1365 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD IDS Routines + * + * Contains AMD AGESA Integrated Debug Macros + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: IDS + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + + /* Macros to aid debugging */ + /* These definitions expand to zero (0) bytes of code when disabled */ + +#ifndef _IDS_H_ +#define _IDS_H_ + +#undef FALSE +#undef TRUE +#define FALSE 0 +#define TRUE 1 +// Proto type for optionsids.h +typedef UINT32 IDS_STATUS; ///< Status of IDS function. +#define IDS_SUCCESS ((IDS_STATUS) 0x00000000ul) ///< IDS Function is Successful. +#define IDS_UNSUPPORTED ((IDS_STATUS) 0xFFFFFFFFul) ///< IDS Function is not existed. + +#define IDS_STRINGIZE(a) #a ///< for define stringize macro +#ifndef IDS_DEADLOOP + #define IDS_DEADLOOP() { volatile UINTN __i; __i = 1; while (__i); } +#endif +/** + * IDS Option Hook Points + * + * These are the values to indicate hook point in AGESA for IDS Options. + * + */ +typedef enum { //vv- for debug reference only + IDS_INIT_EARLY_BEFORE, ///< 00 Option Hook Point before AGESA function AMD_INIT_EARLY. + ///< IDS Object is initialized. + ///< Override CPU Core Leveling Mode. + ///< Set P-State in Post + IDS_INIT_EARLY_AFTER, ///< 01 Option Hook Point after AGESA function AMD_INIT_EARLY. + IDS_INIT_LATE_BEFORE, ///< 02 Option Hook Point before AGESA function AMD_INIT_LATE. + ///< It will be used to control the following tables. + ///< ACPI P-State Table (_PSS, XPSS, _PCT, _PSD, _PPC) + ///< ACPI SRAT Table + ///< ACPI SLIT Table + ///< ACPI WHEA Table + ///< DMI Table + IDS_INIT_LATE_AFTER, ///< 03 Option Hook Point after AGESA function AMD_INIT_LATE. + IDS_INIT_MID_BEFORE, ///< 04 Option Hook Point before AGESA function AMD_INIT_MID. + IDS_INIT_MID_AFTER, ///< 05 Option Hook Point after AGESA function AMD_INIT_MID. + IDS_INIT_POST_BEFORE, ///< 06 Option Hook Point before AGESA function AMD_INIT_POST. + ///< Control Interleaving and DRAM memory hole + ///< Override the setting of ECC Control + ///< Override the setting of Online Spare Rank + IDS_INIT_POST_AFTER, ///< 07 Option Hook Point after AGESA function AMD_INIT_POST. + IDS_INIT_RESET_BEFORE, ///< 08 Option Hook Point before AGESA function AMD_INIT_RESET. + IDS_INIT_RESET_AFTER, ///< 09 Option Hook Point after AGESA function AMD_INIT_RESET. + IDS_INIT_POST_MID, ///< 0a Option Hook Point after AGESA function AMD_INIT_POST. + IDS_BEFORE_S3_SAVE, ///< 0b override any settings before S3 save. + IDS_BEFORE_S3_RESTORE, ///< 0c override any settings before S3 restore + IDS_AFTER_S3_SAVE, ///< 0d Override any settings after S3 save + IDS_AFTER_S3_RESTORE, ///< 0e Override any settings after S3 restore + IDS_BEFORE_DQS_TRAINING, ///< 0f override any settings before DQS training + IDS_BEFORE_DRAM_INIT, ///< 10 override any settings before Dram initialization + IDS_BEFORE_MEM_FREQ_CHG, ///< 11 override settings before MemClk frequency change + IDS_BEFORE_WARM_RESET , ///< 12 Override PCI or MSR Registers Before Warm Reset + IDS_BEFORE_PCI_INIT, ///< 13 Override PCI or MSR Registers Before PCI Init + IDS_BEFORE_AP_EARLY_HALT, ///< 14 Option Hook Point before AP early halt + IDS_BEFORE_S3_RESUME, ///< 15 Option Hook Point before s3 resume + IDS_AFTER_S3_RESUME, ///< 16 Option Hook Point after s3 resume + IDS_BEFORE_PM_INIT, ///< 17 Option Hook Point Before Pm Init + + IDS_MT_BASE = 0x20, ///< 0x20 ~ 0x38 24 time points reserved for MTTime + + IDS_PLATFORM_RSVD1 = 0x38, ///< from 0x38 to 0x3f will reserved for platform used + IDS_PLATFORM_RSVD2 = 0x39, ///< from 0x38 to 0x3f will reserved for platform used + IDS_PLATFORM_RSVD3 = 0x3a, ///< from 0x38 to 0x3f will reserved for platform used + IDS_PLATFORM_RSVD4 = 0x3b, ///< from 0x38 to 0x3f will reserved for platform used + IDS_PLATFORM_RSVD5 = 0x3c, ///< from 0x38 to 0x3f will reserved for platform used + IDS_PLATFORM_RSVD6 = 0x3d, ///< from 0x38 to 0x3f will reserved for platform used + IDS_PLATFORM_RSVD7 = 0x3e, ///< from 0x38 to 0x3f will reserved for platform used + IDS_PLATFORM_RSVD8 = 0x3f, ///< from 0x38 to 0x3f will reserved for platform used + + // All the above timing point is used by BVM, their value should never be changed + IDS_HT_CONTROL, ///< 40 Override the setting of HT Link Control + IDS_HT_TRISTATE, ///< 41 Enable or Disable HT Tri-state during an LDTSTP# + IDS_INIT_DRAM_TABLE, ///< 42 Generate override table for Dram Timing + ///< Dram Controller, Drive Strength and DQS Timing + IDS_GET_DRAM_TABLE, ///< 43 Generate override table for Dram Timing + IDS_GANGING_MODE, ///< 44 override Memory Mode Unganged + IDS_POWERDOWN_MODE, ///< 45 override Power Down Mode + IDS_BURST_LENGTH32, ///< 46 override Burst Length32 + IDS_ALL_MEMORY_CLOCK, ///< 47 override All Memory Clks Enable + IDS_ECC, ///< 48 override ECC parameter + IDS_ECCSYMBOLSIZE, ///< 49 override ECC symbol size + IDS_CPU_Early_Override, ///< 4a override CPU early parameter + IDS_CACHE_FLUSH_HLT, ///< 4b override Cache Flush Hlt + IDS_CHANNEL_INTERLEAVE, ///< 4c override Channel Interleave + IDS_MEM_ERROR_RECOVERY, ///< 4d override memory error recovery + IDS_MEM_RETRAIN_TIMES, ///< 4e override memory retrain times + IDS_MEM_SIZE_OVERLAY, ///< 4f Override the syslimit + IDS_HT_ASSIST, ///< 50 Override Probe Filter + IDS_CHECK_NEGATIVE_WL, ///< 51 Check for negative write leveling result + IDS_DLL_SHUT_DOWN, ///< 52 Check for Dll Shut Down + IDS_POR_MEM_FREQ, ///< 53 Entry to enable/disable MemClk frequency enforcement + IDS_PHY_DLL_STANDBY_CTRL, ///< 54 Enable/Disable Phy DLL standby feature + IDS_PLATFORMCFG_OVERRIDE, ///< 55 Hook for Override PlatformConfig structure + IDS_LOADCARD_ERROR_RECOVERY, ///< 56 Special error handling for load card support + IDS_MEM_IGNORE_ERROR, ///< 57 Ignore error and do not do fatal exit in memory + IDS_GNB_SMU_SERVICE_CONFIG, ///< 58 Config GNB SMU service + IDS_GNB_ORBDYNAMIC_WAKE, ///< 59 config GNB dynamic wake + IDS_GNB_PLATFORMCFG_OVERRIDE, ///< 5a override ids gnb platform config + IDS_GNB_LCLK_DPM_EN, ///< 5b override GNB LCLK DPM configuration + IDS_GNB_LCLK_DEEP_SLEEP, ///< 5c override GNB LCLK DPM deep sleep + IDS_GNB_CLOCK_GATING, ///< 5d Override GNB Clock gating config + IDS_NB_PSTATE_DIDVID, ///< 5e Override NB P-state settings + IDS_CPB_CTRL, ///< 5f Config the Core peformance boost feature + IDS_HTC_CTRL, ///< 60 Hook for Hardware Thermal Control + IDS_CC6_WORKAROUND, ///< 61 Hook for skip CC6 work around + IDS_MEM_MR0, ///< 62 Hook for override Memory Mr0 register + IDS_TRAP_TABLE, ///< 63 Hook for add IDS register table to the loop + IDS_NBBUFFERALLOCATIONATEARLY, ///< 64 Hook for override North bridge bufer allocation + IDS_BEFORE_S3_SPECIAL, ///< 65 Hook to bypass S3 special functions + IDS_SET_PCI_REGISTER_ENTRY, ///< 66 Hook to SetRegisterForPciEntry + IDS_ERRATUM463_WORKAROUND, ///< 67 Hook to Erratum 463 workaround + IDS_BEFORE_MEMCLR, ///< 68 Hook before set Memclr bit + IDS_OVERRIDE_IO_CSTATE, ///< 69 Hook for override io C-state setting + IDS_NBPSDIS_OVERRIDE, ///< 6a Hook for override NB pstate disable setting + IDS_NBPS_REG_OVERRIDE, ///< 6b Hook for override Memory NBps reg + IDS_LOW_POWER_PSTATE, ///< 6c Hook for disalbe Low power_Pstates feature + IDS_CST_CREATE, ///< 6d Hook for create _CST + IDS_CST_SIZE, ///< 6e Hook for get _CST size + IDS_ENFORCE_VDDIO, ///< 6f Hook to override VDDIO + IDS_STRETCH_FREQUENCY_LIMIT, ///< 70 Hook for enforcing memory stretch frequency limit + IDS_INIT_MEM_REG_TABLE, ///< 71 Hook for init memory register table + IDS_SKIP_FUSED_MAX_RATE, ///< 72 Hook to skip fused max rate cap + IDS_FCH_INIT_AT_RESET, ///< 73 Hook for FCH reset parameter + IDS_FCH_INIT_AT_ENV, ///< 74 Hook for FCH ENV parameter + IDS_ENFORCE_PLAT_TABLES, ///< 75 Hook to enforce platform specific tables + IDS_NBPS_MIN_FREQ, ///< 76 Hook for override MIN nb ps freq + IDS_GNB_FORCE_CABLESAFE, ///< 77 Hook for override Force Cable Safe + IDS_SKIP_PM_TRANSITION_STEP, ///< 78 Hook for provide IDS ability to skip this PM step + IDS_GNB_PROPERTY, ///< 79 Hook for GNB Property + IDS_GNB_PCIE_POWER_GATING, ///< 7A Hook for GNB PCIe Power Gating + IDS_MEM_DYN_DRAM_TERM, ///< 7B Hook for Override Dynamic Dram Term + IDS_MEM_DRAM_TERM, ///< 7C Hook for Override Dram Term + IDS_HT_TRACE_MODE, ///< 7D Trace Mode + IDS_GNB_ALTVDDNB, ///< 7E Hook for Override AltVddNB + IDS_UCODE, ///< 7F Enable or Disable microcode patching + IDS_FAM_REG_GMMX, ///< 80 GMMX register access + IDS_MEMORY_POWER_POLICY, ///< 81 Memory power policy + IDS_GET_STRETCH_FREQUENCY_LIMIT, ///< 82 Hook for enforcing memory stretch frequency limit + IDS_CPU_FEAT, ///< 83 Hook for runtime force cpu feature disable + IDS_AFTER_DCT_PHY_ACCESS, ///< 84 Hook for DctAccessDone check + IDS_FORCE_PHY_TO_M0, ///< 85 Hook to bypass M0 enforcement + IDS_GNB_PMM_SWTJOFFSET, ///< 86 Hook to GNBSWTJOFFSET + IDS_LOCK_DRAM_CFG, ///< 87 Hook to BFLockDramCfg + IDS_OPTION_END, ///< 88 End of IDS option +} AGESA_IDS_OPTION; + +#include "OptionsIds.h" +#include "Filecode.h" + +/* Initialize IDS controls */ +#ifndef IDSOPT_IDS_ENABLED + #define IDSOPT_IDS_ENABLED FALSE +#endif + +#ifndef IDSOPT_CONTROL_ENABLED + #define IDSOPT_CONTROL_ENABLED FALSE +#endif + +#ifndef IDSOPT_CONTROL_NV_TO_CMOS + #define IDSOPT_CONTROL_NV_TO_CMOS FALSE +#endif + +#ifndef IDSOPT_TRACING_ENABLED + #define IDSOPT_TRACING_ENABLED FALSE +#endif + +#ifndef IDSOPT_TRACE_USER_OPTIONS + #define IDSOPT_TRACE_USER_OPTIONS TRUE +#endif + +#ifndef IDSOPT_PERF_ANALYSIS + #define IDSOPT_PERF_ANALYSIS FALSE +#endif + +#ifndef IDSOPT_HEAP_CHECKING + #define IDSOPT_HEAP_CHECKING FALSE +#endif + +#ifndef IDSOPT_ASSERT_ENABLED + #define IDSOPT_ASSERT_ENABLED FALSE +#endif + +#ifndef IDSOPT_ERROR_TRAP_ENABLED + #define IDSOPT_ERROR_TRAP_ENABLED FALSE +#endif + +#ifndef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE +#endif + +#ifndef IDSOPT_DEBUG_CODE_ENABLED + #define IDSOPT_DEBUG_CODE_ENABLED FALSE +#endif + +#ifndef IDSOPT_IDT_EXCEPTION_TRAP + #define IDSOPT_IDT_EXCEPTION_TRAP FALSE +#endif + +#ifndef IDSOPT_C_OPTIMIZATION_DISABLED + #define IDSOPT_C_OPTIMIZATION_DISABLED FALSE +#endif + +#ifndef IDSOPT_TRACING_CONSOLE_HDTOUT + #define IDSOPT_TRACING_CONSOLE_HDTOUT FALSE +#endif + +#ifndef IDSOPT_TRACING_CONSOLE_SERIALPORT + #define IDSOPT_TRACING_CONSOLE_SERIALPORT FALSE +#endif + +#ifndef IDSOPT_TRACING_CONSOLE_REDIRECT_IO + #define IDSOPT_TRACING_CONSOLE_REDIRECT_IO FALSE +#endif + +#if IDSOPT_IDS_ENABLED == FALSE + #undef IDSOPT_CONTROL_ENABLED + #undef IDSOPT_TRACING_ENABLED + #undef IDSOPT_PERF_ANALYSIS + #undef IDSOPT_HEAP_CHECKING + #undef IDSOPT_ASSERT_ENABLED + #undef IDSOPT_ERROR_TRAP_ENABLED + #undef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + #undef IDSOPT_DEBUG_CODE_ENABLED + #undef IDSOPT_TRACE_USER_OPTIONS + #undef IDSOPT_TRACING_CONSOLE_HDTOUT + #undef IDSOPT_TRACING_CONSOLE_SERIALPORT + #undef IDSOPT_TRACING_CONSOLE_REDIRECT_IO + + #define IDSOPT_CONTROL_ENABLED FALSE + #define IDSOPT_TRACING_ENABLED FALSE + #define IDSOPT_PERF_ANALYSIS FALSE + #define IDSOPT_HEAP_CHECKING FALSE + #define IDSOPT_ASSERT_ENABLED FALSE + #define IDSOPT_ERROR_TRAP_ENABLED FALSE + #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE + #define IDSOPT_DEBUG_CODE_ENABLED FALSE + #define IDSOPT_TRACE_USER_OPTIONS FALSE + #define IDSOPT_TRACING_CONSOLE_HDTOUT FALSE + #define IDSOPT_TRACING_CONSOLE_SERIALPORT FALSE + #define IDSOPT_TRACING_CONSOLE_REDIRECT_IO FALSE +#endif + +//Disable when master token Tracing is set to FALSE +#if (IDSOPT_TRACING_ENABLED == FALSE) || (defined (IDSOPT_CUSTOMIZE_TRACING_SERVICE)) + #undef IDSOPT_TRACING_CONSOLE_HDTOUT + #define IDSOPT_TRACING_CONSOLE_HDTOUT FALSE + + #undef IDSOPT_TRACING_CONSOLE_SERIALPORT + #define IDSOPT_TRACING_CONSOLE_SERIALPORT FALSE + + #undef IDSOPT_TRACING_CONSOLE_REDIRECT_IO + #define IDSOPT_TRACING_CONSOLE_REDIRECT_IO FALSE +#endif + +//Disable Tracing if all support HW layer set to FALSE +#if ((IDSOPT_TRACING_CONSOLE_HDTOUT == FALSE) && (IDSOPT_TRACING_CONSOLE_SERIALPORT == FALSE) && (IDSOPT_TRACING_CONSOLE_REDIRECT_IO == FALSE)) + #ifndef IDSOPT_CUSTOMIZE_TRACING_SERVICE + #undef IDSOPT_TRACING_ENABLED + #define IDSOPT_TRACING_ENABLED FALSE + #endif +#endif +/** + * Make a Progress Report to the User. + * + * This Macro is always enabled. The default action is to write the TestPoint value + * to an I/O port. The I/O port is 8 bits in size and the default address is 0x80. + * IBVs can change AGESA's default port by defining IDS_DEBUG_PORT to desired port + * in OptionsIds.h in their build tip. + * + * @param[in] TestPoint The value for display indicating progress + * @param[in,out] StdHeader Pointer of AMD_CONFIG_PARAMS + * + **/ + +#define AGESA_TESTPOINT(TestPoint, StdHeader) IdsAgesaTestPoint ((TestPoint), (StdHeader)) + +#ifndef IDS_DEBUG_PORT + #define IDS_DEBUG_PORT 0x80 +#endif + +/** + * @def STOP_HERE + * (macro) - Causes program to halt. This is @b only for use during active debugging . + * + * Causes the program to halt and display the file number of the source of the + * halt (displayed in decimal). + * + **/ +#if IDSOPT_IDS_ENABLED == TRUE + #ifdef STOP_CODE + #undef STOP_CODE + #endif + #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \ + ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \ + (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000)) + #define STOP_HERE IdsErrorStop (STOP_CODE); +#else + #define STOP_HERE STOP_HERE_Needs_To_Be_Removed //"WARNING: Debug code needs to be removed for production builds." +#endif + +/** + * @def ASSERT + * Test an assertion that the given statement is True. + * + * The statement is evaluated to a boolean value. If the statement is True, + * then no action is taken (no error). If the statement is False, a error stop + * is generated to halt the program. Used for testing for fatal errors that + * must be resolved before production. This is used to do parameter checks, + * bounds checking, range checks and 'sanity' checks. + * + * @param[in] conditional Assert that evaluating this conditional results in TRUE. + * + **/ +#ifndef ASSERT + #if IDSOPT_ASSERT_ENABLED == TRUE + #ifdef STOP_CODE + #undef STOP_CODE + #endif + #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \ + ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \ + (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000)) + + #define ASSERT(conditional) ((conditional) ? 0 : IdsAssert (STOP_CODE)); + #else + #define ASSERT(conditional) + #endif +#endif + +#if IDSOPT_CAR_CORRUPTION_CHECK_ENABLED == TRUE + #undef IDSOPT_ERROR_TRAP_ENABLED + #define IDSOPT_ERROR_TRAP_ENABLED TRUE + #define IDS_CAR_CORRUPTION_CHECK(StdHeader) IdsCarCorruptionCheck(StdHeader) +#else + #define IDS_CAR_CORRUPTION_CHECK(StdHeader) +#endif +/** + * @def DEBUG_CODE + * Make the code active when IDSOPT_DEBUG_CODE_ENABLED enable + * + */ +#ifndef DEBUG_CODE + #if IDSOPT_DEBUG_CODE_ENABLED == TRUE + #define DEBUG_CODE(Code) Code + #else + #define DEBUG_CODE(Code) + #endif +#endif + +/** + * @def IDS_ERROR_TRAP + * Trap AGESA Error events with stop code display. + * + * Works similarly to use of "ASSERT (FALSE);" + * + */ +#if IDSOPT_ERROR_TRAP_ENABLED == TRUE + #ifdef STOP_CODE + #undef STOP_CODE + #endif + #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \ + ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \ + (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000)) + + #define IDS_ERROR_TRAP IdsErrorStop (STOP_CODE) +#else + #define IDS_ERROR_TRAP +#endif + +///give the extended Macro default value +#ifndef __IDS_EXTENDED__ + #define IDS_EXTENDED_HOOK(idsoption, dataptr, idsnvptr, stdheader) IDS_SUCCESS + #define IDS_TRACE_DEFAULT (0) + #define IDS_INITIAL_F10_PM_STEP + #define IDS_INITIAL_F12_PM_STEP + #define IDS_INITIAL_F14_PM_STEP + #define IDS_INITIAL_F15_OR_PM_STEP + #define IDS_INITIAL_F15_TN_PM_STEP + #define IDS_F15_TN_PM_CUSTOM_STEP + #define IDS_EXTENDED_GET_DATA_EARLY(data, StdHeader) + #define IDS_EXTENDED_GET_DATA_LATE(data, StdHeader) + #define IDS_EXTENDED_HEAP_SIZE 0 + #define IDS_EXT_INCLUDE_F10(file) + #define IDS_EXT_INCLUDE_F12(file) + #define IDS_EXT_INCLUDE_F14(file) + #define IDS_EXT_INCLUDE_F15(file) + #define IDS_EXT_INCLUDE(file) + #define IDS_PAD_4K + #define IDS_EXTENDED_CODE(code) +#endif + +#ifndef IDS_NUM_NV_ITEM + #define IDS_NUM_NV_ITEM (IDS_NUM_EXT_NV_ITEM) +#endif + +#define IDS_CMOS_INDEX_PORT 0x70 +#define IDS_CMOS_DATA_PORT 0x71 +#define IDS_CMOS_REGION_START 0x20 +#define IDS_CMOS_REGION_END 0x7F +#define IDS_AP_GET_NV_FROM_CMOS(x) FALSE + +#if IDSOPT_CONTROL_ENABLED == TRUE + #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader) \ + AmdIdsCtrlDispatcher ((IdsOption), (DataPtr), (StdHeader)) + + #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) \ + IdsOptionCallout ((CallOutId), (DataPtr), (StdHeader)) + #if IDSOPT_CONTROL_NV_TO_CMOS == TRUE + #undef IDS_AP_GET_NV_FROM_CMOS + #define IDS_AP_GET_NV_FROM_CMOS(x) AmdIdsApGetNvFromCmos(x) + #ifdef IDS_OPT_CMOS_INDEX_PORT + #undef IDS_CMOS_INDEX_PORT + #define IDS_CMOS_INDEX_PORT IDS_OPT_CMOS_INDEX_PORT + #endif + + #ifdef IDS_OPT_CMOS_DATA_PORT + #undef IDS_CMOS_DATA_PORT + #define IDS_CMOS_DATA_PORT IDS_OPT_CMOS_DATA_PORT + #endif + + #ifdef IDS_OPT_CMOS_REGION_START + #undef IDS_CMOS_REGION_START + #define IDS_CMOS_REGION_START IDS_OPT_CMOS_REGION_START + #endif + + #ifdef IDS_OPT_CMOS_REGION_END + #undef IDS_CMOS_REGION_END + #define IDS_CMOS_REGION_END IDS_OPT_CMOS_REGION_END + #endif + #endif +#else + #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader) + + #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) //AGESA_SUCCESS +#endif + +/** + * Macro to add a *skip* hook for IDS options + * + * The default minimal action is to do nothing and there is no any code to increase. + * For debug environments, IDS dispatcher function will be called to perform + * the detailed action and to skip AGESA code if necessary. + * + * @param[in] IdsOption IDS Option ID for this hook point + * @param[in, out] DataPtr Data Pointer to override + * @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS + * + * + **/ + +#if IDSOPT_CONTROL_ENABLED == TRUE + #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader) \ + if (AmdIdsCtrlDispatcher (IdsOption, DataPtr, StdHeader) == IDS_SUCCESS) +#else + #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader) +#endif + +/** + * Macro to add a heap manager routine + * + * when memory is allocated the heap manager actually allocates two extra dwords of data, + * one dword buffer before the actual memory, and one dword afterwards. + * a complete heap walk and check to be performed at any time. + * it would ASSERT if the heap is corrupt + * + * @param[in] StdHeader Pointer of AMD_CONFIG_PARAMS + * + * + **/ + +// Heap debug feature +#define SENTINEL_BEFORE_VALUE 0x64616548ul // "Head" +#define SENTINEL_AFTER_VALUE 0x6C696154ul // "Tail" +#if IDSOPT_IDS_ENABLED == TRUE + #if IDSOPT_HEAP_CHECKING == TRUE + #define SIZE_OF_SENTINEL 4 + #define NUM_OF_SENTINEL 2 // Before ("Head") and After ("Tail") + #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE) + AlignTo16Byte) = SENTINEL_BEFORE_VALUE); + #define SET_SENTINEL_AFTER(NodePtr) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE) + NodePtr->BufferSize - SIZE_OF_SENTINEL) = SENTINEL_AFTER_VALUE); + #define Heap_Check(stdheader) AmdHeapIntactCheck(stdheader) + #else + #define SIZE_OF_SENTINEL 0 + #define NUM_OF_SENTINEL 0 + #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) + #define SET_SENTINEL_AFTER(NodePtr) + #define Heap_Check(stdheader) + #endif +#else + #define SIZE_OF_SENTINEL 0 + #define NUM_OF_SENTINEL 0 + #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) + #define SET_SENTINEL_AFTER(NodePtr) + #define Heap_Check(stdheader) +#endif + +/** + * Macro to add IDT for debugging exception. + * + * A debug feature. Adding a 'jmp $' into every exception handler. + * So debugger could use HDT to skip 'jmp $' and execute the iret, + * then they could find which instruction cause the exception. + * + * @param[in] FunctionId IDS Function ID for this hook point + * @param[in, out] DataPtr Data Pointer to override + * @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS + * + * + **/ +#if IDSOPT_IDS_ENABLED == TRUE + #if IDSOPT_IDT_EXCEPTION_TRAP == TRUE + #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader) IdsExceptionTrap (FunctionId, DataPtr, StdHeader) + #else + #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader) + #endif +#else + #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader) +#endif + + + //Note a is from 0 to 63 +#define DEBUG_PRINT_SHIFT(a) ((UINT64)1 << a) +//If you change the Bitmap definition below, please change the Hash in ParseFilter of hdtout2008.pl accordingly +//Memory Masks +#define MEM_SETREG DEBUG_PRINT_SHIFT (0) +#define MEM_GETREG DEBUG_PRINT_SHIFT (1) +#define MEM_FLOW DEBUG_PRINT_SHIFT (2) +#define MEM_STATUS DEBUG_PRINT_SHIFT (3) +#define MEM_UNDEF_BF DEBUG_PRINT_SHIFT (4) +#define MEMORY_TRACE_RSV2 DEBUG_PRINT_SHIFT (5) +#define MEMORY_TRACE_RSV3 DEBUG_PRINT_SHIFT (6) +#define MEMORY_TRACE_RSV4 DEBUG_PRINT_SHIFT (7) +#define MEMORY_TRACE_RSV5 DEBUG_PRINT_SHIFT (8) +#define MEMORY_TRACE_RSV6 DEBUG_PRINT_SHIFT (9) + + + +//CPU Masks +#define CPU_TRACE DEBUG_PRINT_SHIFT (10) +#define CPU_TRACE_RSV1 DEBUG_PRINT_SHIFT (11) +#define CPU_TRACE_RSV2 DEBUG_PRINT_SHIFT (12) +#define CPU_TRACE_RSV3 DEBUG_PRINT_SHIFT (13) +#define CPU_TRACE_RSV4 DEBUG_PRINT_SHIFT (14) +#define CPU_TRACE_RSV5 DEBUG_PRINT_SHIFT (15) +#define CPU_TRACE_RSV6 DEBUG_PRINT_SHIFT (16) +#define CPU_TRACE_RSV7 DEBUG_PRINT_SHIFT (17) +#define CPU_TRACE_RSV8 DEBUG_PRINT_SHIFT (18) +#define CPU_TRACE_RSV9 DEBUG_PRINT_SHIFT (19) + +//GNB Masks +#define GNB_TRACE DEBUG_PRINT_SHIFT (20) +#define PCIE_MISC DEBUG_PRINT_SHIFT (21) +#define PCIE_PORTREG_TRACE DEBUG_PRINT_SHIFT (22) +#define PCIE_HOSTREG_TRACE DEBUG_PRINT_SHIFT (23) +#define GNB_TRACE_RSV2 DEBUG_PRINT_SHIFT (24) +#define NB_MISC DEBUG_PRINT_SHIFT (25) +#define GNB_TRACE_RSV3 DEBUG_PRINT_SHIFT (26) +#define GFX_MISC DEBUG_PRINT_SHIFT (27) +#define NB_SMUREG_TRACE DEBUG_PRINT_SHIFT (28) +#define GNB_TRACE_RSV1 DEBUG_PRINT_SHIFT (29) + +//HT Masks +#define HT_TRACE DEBUG_PRINT_SHIFT (30) +#define HT_TRACE_RSV1 DEBUG_PRINT_SHIFT (31) +#define HT_TRACE_RSV2 DEBUG_PRINT_SHIFT (32) +#define HT_TRACE_RSV3 DEBUG_PRINT_SHIFT (33) +#define HT_TRACE_RSV4 DEBUG_PRINT_SHIFT (34) +#define HT_TRACE_RSV5 DEBUG_PRINT_SHIFT (35) +#define HT_TRACE_RSV6 DEBUG_PRINT_SHIFT (36) +#define HT_TRACE_RSV7 DEBUG_PRINT_SHIFT (37) +#define HT_TRACE_RSV8 DEBUG_PRINT_SHIFT (38) +#define HT_TRACE_RSV9 DEBUG_PRINT_SHIFT (39) + +//FCH Masks +#define FCH_TRACE DEBUG_PRINT_SHIFT (40) +#define FCH_TRACE_RSV1 DEBUG_PRINT_SHIFT (41) +#define FCH_TRACE_RSV2 DEBUG_PRINT_SHIFT (42) +#define FCH_TRACE_RSV3 DEBUG_PRINT_SHIFT (43) +#define FCH_TRACE_RSV4 DEBUG_PRINT_SHIFT (44) +#define FCH_TRACE_RSV5 DEBUG_PRINT_SHIFT (45) +#define FCH_TRACE_RSV6 DEBUG_PRINT_SHIFT (46) +#define FCH_TRACE_RSV7 DEBUG_PRINT_SHIFT (47) +#define FCH_TRACE_RSV8 DEBUG_PRINT_SHIFT (48) +#define FCH_TRACE_RSV9 DEBUG_PRINT_SHIFT (49) + +//Other Masks +#define MAIN_FLOW DEBUG_PRINT_SHIFT (50) +#define EVENT_LOG DEBUG_PRINT_SHIFT (51) +#define PERFORMANCE_ANALYSE DEBUG_PRINT_SHIFT (52) + +//Ids Masks +#define IDS_TRACE DEBUG_PRINT_SHIFT (53) +#define BVM_TRACE DEBUG_PRINT_SHIFT (54) +#define IDS_TRACE_RSV2 DEBUG_PRINT_SHIFT (55) +#define IDS_TRACE_RSV3 DEBUG_PRINT_SHIFT (56) + +//S3 +#define S3_TRACE DEBUG_PRINT_SHIFT (57) + +//Library function to read/write PCI/MSR registers +#define LIB_PCI_RD DEBUG_PRINT_SHIFT (58) +#define LIB_PCI_WR DEBUG_PRINT_SHIFT (59) + +//Reserved +#define TRACE_RSV3 DEBUG_PRINT_SHIFT (60) +#define TRACE_RSV4 DEBUG_PRINT_SHIFT (61) +#define TRACE_RSV5 DEBUG_PRINT_SHIFT (62) +#define TRACE_RSV6 DEBUG_PRINT_SHIFT (63) + +#define GNB_TRACE_DEFAULT\ + (\ + GNB_TRACE | PCIE_MISC | NB_MISC | GFX_MISC \ + ) + +#define GNB_TRACE_REG\ + (\ + PCIE_PORTREG_TRACE | PCIE_HOSTREG_TRACE | \ + NB_SMUREG_TRACE | GNB_TRACE_RSV1 \ + ) + +#define GNB_TRACE_ALL\ + (\ + GNB_TRACE_DEFAULT | GNB_TRACE_REG \ + ) + +#define CPU_TRACE_ALL\ + (\ + CPU_TRACE | CPU_TRACE_RSV1 | CPU_TRACE_RSV2 | CPU_TRACE_RSV3 | \ + CPU_TRACE_RSV4 | CPU_TRACE_RSV5 | CPU_TRACE_RSV6 | CPU_TRACE_RSV7 | \ + CPU_TRACE_RSV8 | CPU_TRACE_RSV9\ + ) + +#define MEMORY_TRACE_ALL\ + (\ + MEM_FLOW | MEM_GETREG | MEM_SETREG | MEM_STATUS | \ + MEMORY_TRACE_RSV1 | MEMORY_TRACE_RSV2 | MEMORY_TRACE_RSV3 | MEMORY_TRACE_RSV4 | \ + MEMORY_TRACE_RSV5 | MEMORY_TRACE_RSV6\ + ) + +#define HT_TRACE_ALL\ + (\ + HT_TRACE | HT_TRACE_RSV1 | HT_TRACE_RSV2 | HT_TRACE_RSV3 | \ + HT_TRACE_RSV4 | HT_TRACE_RSV5 | HT_TRACE_RSV6 | HT_TRACE_RSV7 | \ + HT_TRACE_RSV8 | HT_TRACE_RSV9\ + ) + +#define FCH_TRACE_ALL\ + (\ + FCH_TRACE | FCH_TRACE_RSV1 | FCH_TRACE_RSV2 | FCH_TRACE_RSV3 | \ + FCH_TRACE_RSV4 | FCH_TRACE_RSV5 | FCH_TRACE_RSV6 | FCH_TRACE_RSV7 | \ + FCH_TRACE_RSV8 | FCH_TRACE_RSV9\ + ) + +#define IDS_TRACE_ALL\ + (\ + IDS_TRACE | BVM_TRACE | IDS_TRACE_RSV2 | IDS_TRACE_RSV3\ + ) + +#define OTHER_TRACE_ALL\ + (\ + MAIN_FLOW | EVENT_LOG | PERFORMANCE_ANALYSE\ + ) + + +#define TRACE_MASK_ALL (0xFFFFFFFFFFFFFFFFull) +#ifndef IDS_DEBUG_PRINT_MASK + #define IDS_DEBUG_PRINT_MASK (GNB_TRACE_DEFAULT | CPU_TRACE_ALL | MEM_FLOW | MEM_STATUS | HT_TRACE_ALL | FCH_TRACE_ALL | MAIN_FLOW | IDS_TRACE_DEFAULT) +#endif + +/// if no specific define INIT & EXIT will be NULL +#define IDS_HDT_CONSOLE_INIT(x) +#define IDS_HDT_CONSOLE_EXIT(x) + +/// AGESA tracing service +#if IDSOPT_TRACING_ENABLED == TRUE + #ifdef IDSOPT_CUSTOMIZE_TRACING_SERVICE + #define IDS_HDT_CONSOLE IDSOPT_CUSTOMIZE_TRACING_SERVICE + #ifdef IDSOPT_CUSTOMIZE_TRACING_SERVICE_INIT + #undef IDS_HDT_CONSOLE_INIT + #define IDS_HDT_CONSOLE_INIT(x) IDSOPT_CUSTOMIZE_TRACING_SERVICE_INIT (x) + #endif + #ifdef IDSOPT_CUSTOMIZE_TRACING_SERVICE_EXIT + #undef IDS_HDT_CONSOLE_EXIT + #define IDS_HDT_CONSOLE_EXIT(x) IDSOPT_CUSTOMIZE_TRACING_SERVICE_EXIT (x) + #endif + #else + #ifdef VA_ARGS_SUPPORTED + #if IDSOPT_C_OPTIMIZATION_DISABLED == TRUE + #define IDS_HDT_CONSOLE(f, s, ...) AmdIdsDebugPrint (f, s, __VA_ARGS__) + #else + #pragma warning(disable: 4127) + #define IDS_HDT_CONSOLE(f, s, ...) if (f == MEM_FLOW) AmdIdsDebugPrintMem (s, __VA_ARGS__); \ + else if (f == CPU_TRACE) AmdIdsDebugPrintCpu (s, __VA_ARGS__); \ + else if (f == HT_TRACE) AmdIdsDebugPrintHt (s, __VA_ARGS__); \ + else if (f == GNB_TRACE) AmdIdsDebugPrintGnb (s, __VA_ARGS__); \ + else AmdIdsDebugPrint (f, s, __VA_ARGS__) + #endif + #else + #define IDS_HDT_CONSOLE AmdIdsDebugPrint + #endif + #define CONSOLE AmdIdsDebugPrintAll + #endif + #define IDS_HDT_CONSOLE_DEBUG_CODE(Code) Code + #define IDS_TIMEOUT_CTL(t) IdsMemTimeOut (t) +#else + #define IDS_HDT_CONSOLE 1 ? (VOID) 0 : AmdIdsDebugPrint + #define IDS_HDT_CONSOLE_DEBUG_CODE(Code) + #define CONSOLE CONSOLE_Needs_To_Be_Removed_For_Production_Build //"WARNING: CONSOLE needs to be removed for production builds." + #define IDS_TIMEOUT_CTL(t) +#endif + +/// Macros for serial port tracing +#ifdef IDSOPT_SERIAL_PORT + #define IDS_SERIAL_PORT IDSOPT_SERIAL_PORT +#endif + +#ifndef IDS_SERIAL_PORT + #define IDS_SERIAL_PORT 0x3F8 +#endif + +// Macros for redirect IO tracing +#ifdef IDSOPT_DEBUG_PRINT_IO_PORT + #define IDS_DEBUG_PRINT_IO_PORT IDSOPT_DEBUG_PRINT_IO_PORT +#endif + +#ifndef IDS_DEBUG_PRINT_IO_PORT + #define IDS_DEBUG_PRINT_IO_PORT 0x80 +#endif + +/** + * Macros to add HDT OUT + * + * The default minimal action is to do nothing and there is no any code to increase. + * For debug environments, the debug information can be displayed in HDT or other + * devices. + * + **/ +#if IDSOPT_TRACING_CONSOLE_HDTOUT == TRUE + #undef IDS_HDT_CONSOLE_INIT + #undef IDS_HDT_CONSOLE_EXIT + #define IDS_HDT_CONSOLE_INIT(x) AmdIdsHdtOutInit (x) + #define IDS_HDT_CONSOLE_EXIT(x) AmdIdsHdtOutExit (x) + #define IDS_HDT_CONSOLE_S3_EXIT(x) AmdIdsHdtOutS3Exit (x) + #define IDS_HDT_CONSOLE_S3_AP_EXIT(x) AmdIdsHdtOutS3ApExit (x) + + #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x) AmdIdsHdtOutBufferFlush (x) + #define IDS_HDT_CONSOLE_ASSERT(x) AmdIdsDebugPrintAssert (x) + #define IDS_FUNCLIST_ADDR ScriptFuncList + #define IDS_FUNCLIST_EXTERN() extern SCRIPT_FUNCTION ScriptFuncList[] +#else + #define IDS_HDT_CONSOLE_S3_EXIT(x) + #define IDS_HDT_CONSOLE_S3_AP_EXIT(x) + #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x) + #define IDS_HDT_CONSOLE_ASSERT(x) + #define IDS_FUNCLIST_ADDR NULL + #define IDS_FUNCLIST_EXTERN() +#endif + +#define IDS_TRACE_SHOW_BLD_OPT_CFG IDSOPT_TRACE_USER_OPTIONS + +#if IDSOPT_PERF_ANALYSIS == TRUE + #ifdef STOP_CODE + #undef STOP_CODE + #endif + #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \ + ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \ + (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000)) + + #define IDS_PERF_TIMESTAMP(StdHeader) IdsPerfTimestamp (STOP_CODE, (StdHeader)) + #define IDS_PERF_ANALYSE(StdHeader) IdsPerfAnalyseTimestamp (StdHeader) +#else + #define IDS_PERF_TIMESTAMP(StdHeader) + #define IDS_PERF_ANALYSE(StdHeader) +#endif + +///For IDS feat use +#define IDS_FAMILY_ALL 0xFFFFFFFFFFFFFFFFull +#define IDS_BSP_ONLY TRUE +#define IDS_ALL_CORES FALSE + +#define IDS_LATE_RUN_AP_TASK_ID PROC_IDS_LIBRARY_IDSLIB_FILECODE + +#define IDS_CALLOUT_INIT 0x01 ///< The function data of IDS callout function of initialization. + +#define IDS_CALLOUT_GNB_PPFUSE_OVERRIDE 0x83 ///< The function data of IDS callout function of GNB pp fuse table. +#define IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG 0x84 ///< The function data of IDS callout function of GNB integrated table. +#define IDS_CALLOUT_GNB_NB_POWERGATE_CONFIG 0x85 ///< The function data of IDS callout function of GNB NB power gate config. +#define IDS_CALLOUT_GNB_PCIE_POWERGATE_CONFIG 0x86 ///< The function data of IDS callout function of GNB PCIE power gateconfig. +#define IDS_CALLOUT_GNB_PCIE_PLATFORM_CONFIG 0x87 ///< The function data of IDS callout function of GNB pcie platform config. +#define IDS_CALLOUT_GNB_PCIE_PHY_CONFIG 0x88 ///< The function data of IDS callout function of GNB pcie PHY config. +#define IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE 0x89 ///< The function data of IDS callout function of GNB GMM register override +#define IDS_CALLOUT_MTC1E_PLATFORM_CONFIG 0x8A ///< The function data of IDS callout function of Message Triggered C1e platform config. +#define IDS_CALLOUT_FCH_INIT_RESET 0x8B ///< The function data of IDS callout function of FchInitReset +#define IDS_CALLOUT_FCH_INIT_ENV 0x8C ///< The function data of IDS callout function of FchInitEnv. +#define IDS_CALLOUT_POWER_PLAN_INIT 0x8D ///< The function data of IDS callout function of Override Power Plan Init +/// Function entry for HDT script to call +typedef struct _SCRIPT_FUNCTION { + UINT32 FuncAddr; ///< Function address in ROM + CHAR8 FuncName[40]; ///< Function name +} SCRIPT_FUNCTION; + +/// Data Structure for Mem ECC parameter override +typedef struct { + IN BOOLEAN CfgEccRedirection; ///< ECC Redirection + IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate + IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate + IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate + IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate + IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate + IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood +} ECC_OVERRIDE_STRUCT; + + + + +/** + * AGESA Test Points + * + * These are the values displayed to the user to indicate progress through boot. + * These can be used in a debug environment to stop the debugger at a specific + * test point: + * For SimNow!, this command + * bi 81 w vb 49 + * will stop the debugger on one of the TracePoints (49 is the TP value in this example). + * + */ +typedef enum { + StartProcessorTestPoints, ///< 00 Entry used for range testing for @b Processor related TPs + + // Memory test points + TpProcMemBeforeMemDataInit, ///< 01 .. Memory structure initialization (Public interface) + TpProcMemBeforeSpdProcessing, ///< 02 .. SPD Data processing (Public interface) + TpProcMemAmdMemAuto, ///< 03 .. Memory configuration (Public interface) + TpProcMemDramInit, ///< 04 .. DRAM initialization + TpProcMemSPDChecking, ///< 05 .. + TpProcMemModeChecking, ///< 06 .. + TpProcMemSpeedTclConfig, ///< 07 .. Speed and TCL configuration + TpProcMemSpdTiming, ///< 08 .. + TpProcMemDramMapping, ///< 09 .. + TpProcMemPlatformSpecificConfig, ///< 0A .. + TPProcMemPhyCompensation, ///< 0B .. + TpProcMemStartDcts, ///< 0C .. + TpProcMemBeforeDramInit, ///< 0D .. (Public interface) + TpProcMemPhyFenceTraining, ///< 0E .. + TpProcMemSynchronizeDcts, ///< 0F .. + TpProcMemSystemMemoryMapping, ///< 10 .. + TpProcMemMtrrConfiguration, ///< 11 .. + TpProcMemDramTraining, ///< 12 .. + TpProcMemBeforeAnyTraining, ///< 13 .. (Public interface) + TpProcMemWriteLevelizationTraining, ///< 14 .. + TpProcMemWlFirstPass, ///< 15 .. Below 800Mhz first pass start + TpProcMemWlSecondPass, ///< 16 .. Above 800Mhz second pass start + TpProcMemWlTrainTargetDimm, ///< 17 .. Target DIMM configured + TpProcMemWlPrepDimms, ///< 18 .. Prepare DIMMS for WL + TpProcMemWlConfigDimms, ///< 19 .. Configure DIMMS for WL + TpProcMemReceiverEnableTraining, ///< 1A .. + TpProcMemRcvrStartSweep, ///< 1B .. Start sweep loop + TpProcMemRcvrSetDelay, ///< 1C .. Set receiver Delay + TpProcMemRcvrWritePattern, ///< 1D .. Write test pattern + TpProcMemRcvrReadPattern, ///< 1E .. Read test pattern + TpProcMemRcvrTestPattern, ///< 1F .. Compare test pattern + TpProcMemRcvrCalcLatency, ///< 20 .. Calculate MaxRdLatency per channel + TpProcMemReceiveDqsTraining, ///< 21 .. + TpProcMemRcvDqsSetDelay, ///< 22 .. Set Write Data delay + TpProcMemRcvDqsWritePattern, ///< 23 .. Write test pattern + TpProcMemRcvDqsStartSweep, ///< 24 .. Start read sweep + TpProcMemRcvDqsSetRcvDelay, ///< 25 .. Set Receive DQS delay + TpProcMemRcvDqsReadPattern, ///< 26 .. Read Test pattern + TpProcMemRcvDqsTstPattern, ///< 27 .. Compare Test pattern + TpProcMemRcvDqsResults, ///< 28 .. Update results + TpProcMemRcvDqsFindWindow, ///< 29 .. Start Find passing window + TpProcMemTransmitDqsTraining, ///< 2A .. + TpProcMemTxDqStartSweep, ///< 2B .. Start write sweep + TpProcMemTxDqSetDelay, ///< 2C .. Set Transmit DQ delay + TpProcMemTxDqWritePattern, ///< 2D .. Write test pattern + TpProcMemTxDqReadPattern, ///< 2E .. Read Test pattern + TpProcMemTxDqTestPattern, ///< 2F .. Compare Test pattern + TpProcMemTxDqResults, ///< 30 .. Update results + TpProcMemTxDqFindWindow, ///< 31 .. Start Find passing window + TpProcMemMaxRdLatencyTraining, ///< 32 .. + TpProcMemMaxRdLatStartSweep, ///< 33 .. Start sweep + TpProcMemMaxRdLatSetDelay, ///< 34 .. Set delay + TpProcMemMaxRdLatWritePattern, ///< 35 .. Write test pattern + TpProcMemMaxRdLatReadPattern, ///< 36 .. Read Test pattern + TpProcMemMaxRdLatTestPattern, ///< 37 .. Compare Test pattern + TpProcMemOnlineSpareInit, ///< 38 .. Online Spare init + TpProcMemBankInterleaveInit, ///< 39 .. Bank Interleave Init + TpProcMemNodeInterleaveInit, ///< 3A .. Node Interleave Init + TpProcMemChannelInterleaveInit, ///< 3B .. Channel Interleave Init + TpProcMemEccInitialization, ///< 3C .. ECC initialization + TpProcMemPlatformSpecificInit, ///< 3D .. Platform Specific Init + TpProcMemBeforeAgesaReadSpd, ///< 3E .. Before callout for "AgesaReadSpd" + TpProcMemAfterAgesaReadSpd, ///< 3F .. After callout for "AgesaReadSpd" + TpProcMemBeforeAgesaHookBeforeDramInit, ///< 40 .. Before optional callout "AgesaHookBeforeDramInit" + TpProcMemAfterAgesaHookBeforeDramInit, ///< 41 .. After optional callout "AgesaHookBeforeDramInit" + TpProcMemBeforeAgesaHookBeforeDQSTraining, ///< 42 .. Before optional callout "AgesaHookBeforeDQSTraining" + TpProcMemAfterAgesaHookBeforeDQSTraining, ///< 43 .. After optional callout "AgesaHookBeforeDQSTraining" + TpProcMemBeforeAgesaHookBeforeExitSelfRef, ///< 44 .. Before optional callout "AgesaHookBeforeDramInit" + TpProcMemAfterAgesaHookBeforeExitSelfRef, ///< 45 .. After optional callout "AgesaHookBeforeDramInit" + TpProcMemAfterMemDataInit, ///< 46 .. After MemDataInit + TpProcMemInitializeMCT, ///< 47 .. Before InitializeMCT + TpProcMemLvDdr3, ///< 48 .. Before LV DDR3 + TpProcMemInitMCT, ///< 49 .. Before InitMCT + TpProcMemOtherTiming, ///< 4A.. Before OtherTiming + TpProcMemUMAMemTyping, ///< 4B .. Before UMAMemTyping + TpProcMemSetDqsEccTmgs, ///< 4C .. Before SetDqsEccTmgs + TpProcMemMemClr, ///< 4D .. Before MemClr + TpProcMemOnDimmThermal, ///< 4E .. Before On DIMM Thermal + TpProcMemDmi, ///< 4F .. Before DMI + TpProcMemEnd, ///< 50 .. End of memory code + + // CPU test points + TpProcCpuEntryDmi, ///< 51 .. Entry point CreateDmiRecords + TpProcCpuEntryPstate, ///< 52 .. Entry point GenerateSsdt + TpProcCpuEntryPstateLeveling, ///< 53 .. Entry point PStateLeveling + TpProcCpuEntryPstateGather, ///< 54 .. Entry point PStateGatherData + TpProcCpuEntryWhea, ///< 55 .. Entry point CreateAcpiWhea + TpProcCpuEntrySrat, ///< 56 .. Entry point CreateAcpiSrat + TpProcCpuEntrySlit, ///< 57 .. Entry point CreateAcpiSlit + TpProcCpuProcessRegisterTables, ///< 58 .. Register table processing + TpProcCpuSetBrandID, ///< 59 .. Set brand ID + TpProcCpuLocalApicInit, ///< 5A .. Initialize local APIC + TpProcCpuLoadUcode, ///< 5B .. Load microcode patch + TpProcCpuBeforePMFeatureInit, ///< 5C .. BeforePM feature dispatch point + TpProcCpuPowerMgmtInit, ///< 5D .. Power Management table processing + TpProcCpuEarlyFeatureInit, ///< 5E .. Early feature dispatch point + TpProcCpuCoreLeveling, ///< 5F .. Core Leveling + TpProcCpuApMtrrSync, ///< 60 .. AP MTRR sync up + TpProcCpuPostFeatureInit, ///< 61 .. POST feature dispatch point + TpProcCpuFeatureLeveling, ///< 62 .. CPU Feature Leveling + TpProcCpuBeforeRelinquishAPsFeatureInit, ///< 63 .. Before Relinquishing control of APs feature dispatch point + TpProcCpuBeforeAllocateWheaBuffer, ///< 64 .. Before the WHEA init code calls out to allocate a buffer + TpProcCpuAfterAllocateWheaBuffer, ///< 65 .. After the WHEA init code calls out to allocate a buffer + TpProcCpuBeforeAllocateSratBuffer, ///< 66 .. Before the SRAT init code calls out to allocate a buffer + TpProcCpuAfterAllocateSratBuffer, ///< 67 .. After the SRAT init code calls out to allocate a buffer + TpProcCpuBeforeLocateSsdtBuffer, ///< 68 .. Before the P-state init code calls out to locate a buffer + TpProcCpuAfterLocateSsdtBuffer, ///< 69 .. After the P-state init code calls out to locate a buffer + TpProcCpuBeforeAllocateSsdtBuffer, ///< 6A .. Before the P-state init code calls out to allocate a buffer + TpProcCpuAfterAllocateSsdtBuffer, ///< 6B .. After the P-state init code calls out to allocate a buffer + Agtp6c , + Agtp6d , + + // HT test points + TpProcHtEntry = 0x71, ///< 71 .. Coherent Discovery begin (Public interface) + TpProcHtTopology, ///< 72 .. Topology match, routing, begin + TpProcHtManualNc, ///< 73 .. Manual Non-coherent Init begin + TpProcHtAutoNc, ///< 74 .. Automatic Non-coherent init begin + TpProcHtOptGather, ///< 75 .. Optimization: Gather begin + TpProcHtOptRegang, ///< 76 .. Optimization: Regang begin + TpProcHtOptLinks, ///< 77 .. Optimization: Link Begin + TpProcHtOptSubLinks, ///< 78 .. Optimization: Sublinks begin + TpProcHtOptFinish, ///< 79 .. Optimization: Set begin + TpProcHtTrafficDist, ///< 7A .. Traffic Distribution begin + TpProcHtTuning, ///< 7B .. Misc Tuning Begin + TpProcHtDone, ///< 7C .. HT Init complete + TpProcHtApMapEntry, ///< 7D .. AP HT: Init Maps begin + TpProcHtApMapDone, ///< 7E .. AP HT: Complete + + // Extended memory test point + TpProcMemSendMRS2 = 0x80, ///< 80 .. Sending MRS2 + TpProcMemSendMRS3, ///< 81 .. Sedding MRS3 + TpProcMemSendMRS1, ///< 82 .. Sending MRS1 + TpProcMemSendMRS0, ///< 83 .. Sending MRS0 + TpProcMemContinPatternGenRead, ///< 84 .. Continuous Pattern Read + TpProcMemContinPatternGenWrite, ///< 85 .. Continuous Pattern Write + Agtp86 , + Agtp87 , + TpProcMemAfter2dTrainExtVrefChange, ///< 88 .. Mem: After optional callout to platfrom BIOS to change External Vref during 2d Training + TpProcMemConfigureDCTForGeneral, ///< 89 .. Configure DCT For General use begin + TpProcMemProcConfigureDCTForTraining, ///< 8A .. Configure DCT For training begin + TpProcMemConfigureDCTNonExplicitSeq,///< 8B .. Configure DCT For Non-Explicit + TpProcMemSynchronizeChannels, ///< 8C .. Configure to Sync channels + TpProcMemC6StorageAllocation, ///< 8D .. Allocate C6 Storage + + StartNbTestPoints = 0x90, ///< 90 Entry used for range testing for @b NorthBridge related TPs + TpNbxxx, ///< 91 . + EndNbTestPoints, ///< 92 End of TP range for NB + + StartFchTestPoints = 0xB0, ///< B0 Entry used for range testing for @b FCH related TPs + TpFchInitResetDispatching, ///< B1 .. FCH InitReset dispatch point + TpFchGppBeforePortTraining, ///< B2 .. Before FCH GPP port training + TpFchGppGen1PortPolling, ///< B3 .. FCH GPP port polling with GEN1 speed + TpFchGppGen2PortPolling, ///< B4 .. FCH GPP port polling with GEN2 speed + TpFchGppAfterPortTraining, ///< B5 .. After FCH GPP port training + TpFchInitEnvDispatching, ///< B6 .. FCH InitEnv dispatch point + TpFchInitMidDispatching, ///< B7 .. FCH InitMid dispatch point + TpFchInitLateDispatching, ///< B8 .. FCH InitLate dispatch point + TpFchGppHotPlugging, ///< B9 .. FCH GPP hot plug event + TpFchGppHotUnplugging, ///< BA .. AFCH GPP hot unplug event + TpFchInitS3EarlyDispatching, ///< BB .. FCH InitS3Early dispatch point + TpFchInitS3LateDispatching, ///< BC .. FCH InitS3Late dispatch point + EndFchTestPoints, ///< BF End of TP range for FCH + + // Interface test points + TpIfAmdInitResetEntry = 0xC0, ///< C0 .. Entry to AmdInitReset + TpIfAmdInitResetExit, ///< C1 .. Exiting from AmdInitReset + TpIfAmdInitRecoveryEntry, ///< C2 .. Entry to AmdInitRecovery + TpIfAmdInitRecoveryExit, ///< C3 .. Exiting from AmdInitRecovery + TpIfAmdInitEarlyEntry, ///< C4 .. Entry to AmdInitEarly + TpIfAmdInitEarlyExit, ///< C5 .. Exiting from AmdInitEarly + TpIfAmdInitPostEntry, ///< C6 .. Entry to AmdInitPost + TpIfAmdInitPostExit, ///< C7 .. Exiting from AmdInitPost + TpIfAmdInitEnvEntry, ///< C8 .. Entry to AmdInitEnv + TpIfAmdInitEnvExit, ///< C9 .. Exiting from AmdInitEnv + TpIfAmdInitMidEntry, ///< CA .. Entry to AmdInitMid + TpIfAmdInitMidExit, ///< CB .. Exiting from AmdInitMid + TpIfAmdInitLateEntry, ///< CC .. Entry to AmdInitLate + TpIfAmdInitLateExit, ///< CD .. Exiting from AmdInitLate + TpIfAmdS3SaveEntry, ///< CE .. Entry to AmdS3Save + TpIfAmdS3SaveExit, ///< CF .. Exiting from AmdS3Save + TpIfAmdInitResumeEntry, ///< D0 .. Entry to AmdInitResume + TpIfAmdInitResumeExit, ///< D1 .. Exiting from AmdInitResume + TpIfAmdS3LateRestoreEntry, ///< D2 .. Entry to AmdS3LateRestore + TpIfAmdS3LateRestoreExit, ///< D3 .. Exiting from AmdS3LateRestore + TpIfAmdLateRunApTaskEntry, ///< D4 .. Entry to AmdS3LateRestore + TpIfAmdLateRunApTaskExit, ///< D5 .. Exiting from AmdS3LateRestore + TpIfAmdReadEventLogEntry, ///< D6 .. Entry to AmdReadEventLog + TpIfAmdReadEventLogExit, ///< D7 .. Exiting from AmdReadEventLog + TpIfAmdGetApicIdEntry, ///< D8 .. Entry to AmdGetApicId + TpIfAmdGetApicIdExit, ///< D9 .. Exiting from AmdGetApicId + TpIfAmdGetPciAddressEntry, ///< DA .. Entry to AmdGetPciAddress + TpIfAmdGetPciAddressExit, ///< DB .. Exiting from AmdGetPciAddress + TpIfAmdIdentifyCoreEntry, ///< DC .. Entry to AmdIdentifyCore + TpIfAmdIdentifyCoreExit, ///< DD .. Exiting from AmdIdentifyCore + TpIfBeforeRunApFromIds, ///< DE .. After IDS calls out to run code on an AP + TpIfAfterRunApFromIds, ///< DF .. After IDS calls out to run code on an AP + TpIfBeforeGetIdsData, ///< E0 .. Before IDS calls out to get IDS data + TpIfAfterGetIdsData, ///< E1 .. After IDS calls out to get IDS data + TpIfBeforeAllocateHeapBuffer, ///< E2 .. Before the heap manager calls out to allocate a buffer + TpIfAfterAllocateHeapBuffer, ///< E3 .. After the heap manager calls out to allocate a buffer + TpIfBeforeDeallocateHeapBuffer, ///< E4 .. Before the heap manager calls out to deallocate a buffer + TpIfAfterDeallocateHeapBuffer, ///< E5 .. After the heap manager calls out to deallocate a buffer + TpIfBeforeLocateHeapBuffer, ///< E6 .. Before the heap manager calls out to locate a buffer + TpIfAfterLocateHeapBuffer, ///< E7 .. After the heap manager calls out to locate a buffer + TpIfBeforeRunApFromAllAps, ///< E8 .. Before the BSP calls out to run code on an AP + TpIfAfterRunApFromAllAps, ///< E9 .. After the BSP calls out to run code on an AP + TpIfBeforeRunApFromAllCore0s, ///< EA .. Before the BSP calls out to run code on an AP + TpIfAfterRunApFromAllCore0s, ///< EB .. After the BSP calls out to run code on an AP + TpIfBeforeAllocateS3SaveBuffer, ///< EC .. Before the S3 save code calls out to allocate a buffer + TpIfAfterAllocateS3SaveBuffer, ///< ED .. After the S3 save code calls out to allocate a buffer + TpIfBeforeAllocateMemoryS3SaveBuffer, ///< EE .. Before the memory S3 save code calls out to allocate a buffer + TpIfAfterAllocateMemoryS3SaveBuffer, ///< EF .. After the memory S3 save code calls out to allocate a buffer + TpIfBeforeLocateS3PciBuffer, ///< F0 .. Before the memory code calls out to locate a buffer + TpIfAfterLocateS3PciBuffer, ///< F1 .. After the memory code calls out to locate a buffer + TpIfBeforeLocateS3CPciBuffer, ///< F2 .. Before the memory code calls out to locate a buffer + TpIfAfterLocateS3CPciBuffer, ///< F3 .. After the memory code calls out to locate a buffer + TpIfBeforeLocateS3MsrBuffer, ///< F4 .. Before the memory code calls out to locate a buffer + TpIfAfterLocateS3MsrBuffer, ///< F5 .. After the memory code calls out to locate a buffer + TpIfBeforeLocateS3CMsrBuffer, ///< F6 .. Before the memory code calls out to locate a buffer + TpIfAfterLocateS3CMsrBuffer, ///< F7 .. After the memory code calls out to locate a buffer + TpPerfUnit, ///< F8 .. The Unit of performance measure. + EndAgesaTps = 0xFF, ///< Last defined AGESA TP +} AGESA_TP; + +///Ids Feat description +typedef enum { + IDS_FEAT_UCODE_UPDATE = 0x0000, ///< Feat for Ucode Update + IDS_FEAT_TARGET_PSTATE, ///< Feat for Target Pstate + IDS_FEAT_POSTPSTATE, ///< Feat for Post Pstate + IDS_FEAT_ECC_CTRL, ///< Feat for Ecc Control + IDS_FEAT_ECC_SYMBOL_SIZE, ///< Feat for Ecc symbol size + IDS_FEAT_DCT_ALLMEMCLK, ///< Feat for all memory clock + IDS_FEAT_DCT_GANGMODE, ///< Feat for Dct gang mode + IDS_FEAT_DCT_BURSTLENGTH, ///< Feat for dct burst length + IDS_FEAT_DCT_POWERDOWN, ///< Feat for dct power down + IDS_FEAT_DCT_DLLSHUTDOWN, ///< Feat for dct dll shut down + IDS_FEAT_PROBE_FILTER, ///< Feat for probe filter + IDS_FEAT_HDTOUT, ///< Feat for hdt out + IDS_FEAT_HT_SETTING, ///< Feat for Ht setting + IDS_FEAT_GNB_PLATFORMCFG, ///< Feat for override GNB platform config + IDS_FEAT_CPB_CTRL, ///< Feat for Config the Core peformance boost feature + IDS_FEAT_HTC_CTRL, ///< Feat for Hardware Thermal Control + IDS_FEAT_MEMORY_MAPPING, ///< Feat for Memory Mapping + IDS_FEAT_POWER_POLICY, ///< Feat for Power Policy + IDS_FEAT_NV_TO_CMOS, ///< Feat for Save BSP Nv to CMOS + IDS_FEAT_COMMON, ///< Common Feat + IDS_FEAT_END = 0xFF ///< End of Common feat +} IDS_FEAT; + +///Ids IDT table function ID +typedef enum { + IDS_IDT_REPLACE_IDTR_FOR_BSC = 0x0000, ///< Function ID for saving IDTR for BSC + IDS_IDT_RESTORE_IDTR_FOR_BSC, ///< Function ID for restoring IDTR for BSC + IDS_IDT_UPDATE_EXCEPTION_VECTOR_FOR_AP, ///< Function ID for updating exception vector +} IDS_IDT_FUNC_ID; + +typedef IDS_STATUS IDS_COMMON_FUNC ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ); + +typedef IDS_COMMON_FUNC *PIDS_COMMON_FUNC; + +/// Data Structure of IDS Feature block +typedef struct _IDS_FAMILY_FEAT_STRUCT { + IDS_FEAT IdsFeat; ///< Ids Feat ID + BOOLEAN IsBsp; ///< swith for Bsp check + AGESA_IDS_OPTION IdsOption; ///< IDS option + UINT64 CpuFamily; ///< + PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function +} IDS_FAMILY_FEAT_STRUCT; + + +/// Data Structure of IDS option +typedef struct _IDS_OPTION_STRUCT { + AGESA_IDS_OPTION idsoption; ///< IDS option + PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function +} IDS_OPTION_STRUCT; + +/// Data Structure of IDS option table +typedef struct _IDS_OPTION_STRUCT_TBL { + UINT8 version; ///<Version of IDS option table + UINT16 size; ///<Size of IDS option table + CONST IDS_OPTION_STRUCT *pIdsOptionStruct; ///<pointer to array of structure +} IDS_OPTION_STRUCT_TBL; + +#define IDS_NV_TO_CMOS_LEN_BYTE 1 +#define IDS_NV_TO_CMOS_LEN_WORD 2 +#define IDS_NV_TO_CMOS_LEN_END 0xFF +#define IDS_NV_TO_CMOS_ID_END 0xFFFF + +/// Data struct of set/get NV to/from CMOS +typedef struct _IDS_NV_TO_CMOS { + UINT8 Length; ///< Length of NV + UINT16 IDS_NV_ID; ///< IDS id +} IDS_NV_TO_CMOS; + +IDS_STATUS +AmdIdsCtrlDispatcher ( + IN AGESA_IDS_OPTION IdsOption, + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +IdsOptionCallout ( + IN UINTN CallOutId, + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +AmdIdsHdtOutInit ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +AmdIdsHdtOutExit ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +AmdIdsHdtOutS3Exit ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +AmdIdsHdtOutS3ApExit ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +AmdIdsDebugPrint ( + IN UINT64 Flag, + IN CONST CHAR8 *Format, + IN ... + ); + +VOID +AmdIdsDebugPrintHt ( + IN CHAR8 *Format, + IN ... + ); + +VOID +AmdIdsDebugPrintCpu ( + IN CHAR8 *Format, + IN ... + ); + +VOID +AmdIdsDebugPrintMem ( + IN CHAR8 *Format, + IN ... + ); + +VOID +AmdIdsDebugPrintGnb ( + IN CHAR8 *Format, + IN ... + ); + +VOID +AmdIdsDebugPrintAll ( + IN CHAR8 *Format, + IN ... + ); + +VOID +AmdIdsHdtOutBufferFlush ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +IdsMemTimeOut ( + IN OUT VOID *DataPtr + ); + +VOID +IdsAgesaTestPoint ( + IN AGESA_TP TestPoint, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * IDS Backend Function for ASSERT + * + * Halt execution with stop code display. Stop Code is displayed on port 80, with rotation so that + * it is visible on 8, 16, or 32 bit display. The stop code is alternated with 0xDEAD on the display, + * to help distinguish the stop code from a post code loop. + * Additional features may be available if using simulation. + * + * @param[in] FileCode File code(define in FILECODE.h) mix with assert Line num. + * + * @retval TRUE No error +**/ +BOOLEAN +IdsAssert ( + IN UINT32 FileCode + ); + +/** + * The engine code for ASSERT MACRO + * + * Halt execution with stop code display. Stop Code is displayed on port 80, with rotation so that + * it is visible on 8, 16, or 32 bit display. The stop code is alternated with 0xDEAD on the display, + * to help distinguish the stop code from a post code loop. + * Additional features may be available if using simulation. + * + * @param[in] FileCode File code(define in FILECODE.h) mix with assert Line num. + * + */ +BOOLEAN +IdsErrorStop ( + IN UINT32 FileCode + ); + +VOID +IdsDelay (VOID +); + +BOOLEAN +AmdHeapIntactCheck ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +IdsCarCorruptionCheck ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +IDS_STATUS +IdsExceptionTrap ( + IN IDS_IDT_FUNC_ID IdsIdtFuncId, + IN VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +IdsPerfTimestamp ( + IN UINT32 LineInFile, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +IdsPerfAnalyseTimestamp ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + + +#if IDSOPT_IDS_ENABLED == FALSE + #undef IEM_SKIP_CODE + #undef IEM_INSERT_CODE +#endif +#ifndef IEM_SKIP_CODE + #define IEM_SKIP_CODE(L) +#endif +#ifndef IEM_INSERT_CODE + #define IEM_INSERT_CODE(L, Fn, Parm) +#endif + +#endif // _IDS_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/IdsHt.h b/src/vendorcode/amd/agesa/f15tn/Include/IdsHt.h new file mode 100644 index 0000000..25a1972 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/IdsHt.h @@ -0,0 +1,150 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD IDS HyperTransport Definitions + * + * Contains AMD AGESA Integrated Debug HT related items. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: IDS + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _IDS_HT_H_ +#define _IDS_HT_H_ + +// Frequency equates for call backs which take an actual frequency setting +#define HT_FREQUENCY_200M 0 +#define HT_FREQUENCY_400M 2 +#define HT_FREQUENCY_600M 4 +#define HT_FREQUENCY_800M 5 +#define HT_FREQUENCY_1000M 6 +#define HT_FREQUENCY_1200M 7 +#define HT_FREQUENCY_1400M 8 +#define HT_FREQUENCY_1600M 9 +#define HT_FREQUENCY_1800M 10 +#define HT_FREQUENCY_2000M 11 +#define HT_FREQUENCY_2200M 12 +#define HT_FREQUENCY_2400M 13 +#define HT_FREQUENCY_2600M 14 +#define HT_FREQUENCY_2800M 17 +#define HT_FREQUENCY_3000M 18 +#define HT_FREQUENCY_3200M 19 +#define HT_FREQUENCY_3600M 20 + +/** + * HT IDS: HT Link Port Override params. + * + * Provide an absolute override of HT Link Port settings. No checking is done that + * the settings obey limits or capabilities, this responsibility rests with the user. + * + * Rules for values of structure items: + * - Socket + * - HT_LIST_TERMINAL == end of port override list, rest of item is not accessed + * - HT_LIST_MATCH_ANY == Match Any Socket + * - 0 .. 7 == The matching socket + * - Link + * - HT_LIST_MATCH_ANY == Match Any package link (that is not the internal links) + * - HT_LIST_MATCH_INTERNAL_LINK == Match the internal links + * - 0 .. 7 == The matching package link. 0 .. 3 are the ganged links or sublink 0's, 4 .. 7 are the sublink1's. + * - Frequency + * - HT_LIST_TERMINAL == Do not override the frequency, AUTO setting + * - HT_FREQUENCY_200M .. HT_FREQUENCY_3600M = The frequency value to use + * - Widthin + * - HT_LIST_TERMINAL == Do not override the width, AUTO setting + * - 2, 4, 8, 16, 32 == The width value to use + * - Widthout + * - HT_LIST_TERMINAL == Do not override the width, AUTO setting + * - 2, 4, 8, 16, 32 == The width value to use + */ +typedef struct { + // Match Fields + UINT8 Socket; ///< The Socket which this port is on. + UINT8 Link; ///< The port for this package link on that socket. + // Override fields + UINT8 Frequency; ///< Absolutely override the port's frequency. + UINT8 WidthIn; ///< Absolutely override the port's width. + UINT8 WidthOut; ///< Absolutely override the port's width. +} HTIDS_PORT_OVERRIDE; + +/** + * A list of port overrides to search. + */ +typedef HTIDS_PORT_OVERRIDE *HTIDS_PORT_OVERRIDE_LIST; +VOID +HtIdsGetPortOverride ( + IN BOOLEAN IsSourcePort, + IN OUT PORT_DESCRIPTOR *Port0, + IN OUT PORT_DESCRIPTOR *Port1, + IN OUT HTIDS_PORT_OVERRIDE_LIST *PortOverrideList, + IN STATE_DATA *State + ); + +typedef +VOID +F_HtIdsGetPortOverride ( + IN BOOLEAN IsSourcePort, + IN OUT PORT_DESCRIPTOR *Port0, + IN OUT PORT_DESCRIPTOR *Port1, + IN OUT HTIDS_PORT_OVERRIDE_LIST *PortOverrideList, + IN STATE_DATA *State + ); +typedef F_HtIdsGetPortOverride* PF_HtIdsGetPortOverride; +#endif // _IDS_HT_H diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionApmInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionApmInstall.h new file mode 100644 index 0000000..1ef77ad --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionApmInstall.h @@ -0,0 +1,113 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: Application Power Management (APM). + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_APM_INSTALL_H_ +#define _OPTION_APM_INSTALL_H_ + +#include "cpuApm.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#define OPTION_CPU_APM_FEAT +#define F15_APM_SUPPORT + +#if OPTION_CPU_APM == TRUE + #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) + // Family 15h + #ifdef OPTION_FAMILY15H + #if OPTION_FAMILY15H == TRUE + #if (OPTION_FAMILY15H_OR == TRUE) + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureApm; + #undef OPTION_CPU_APM_FEAT + #define OPTION_CPU_APM_FEAT &CpuFeatureApm, + extern CONST APM_FAMILY_SERVICES ROMDATA F15ApmSupport; + #undef F15_APM_SUPPORT + #define F15_APM_SUPPORT {AMD_FAMILY_15_OR, &F15ApmSupport}, + #endif + #endif + #endif + #endif +#endif + +CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA ApmFamilyServiceArray[] = +{ + F15_APM_SUPPORT + {0, NULL} +}; + +CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA ApmFamilyServiceTable = +{ + (sizeof (ApmFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &ApmFamilyServiceArray[0] +}; + +#endif // _OPTION_APM_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionC6Install.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionC6Install.h new file mode 100644 index 0000000..9f5d524 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionC6Install.h @@ -0,0 +1,205 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: C6 C-state + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_C6_STATE_INSTALL_H_ +#define _OPTION_C6_STATE_INSTALL_H_ + +#include "cpuC6State.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#define OPTION_C6_STATE_FEAT +#define F12_C6_STATE_SUPPORT +#define F14_ON_C6_STATE_SUPPORT +#define F15_OR_C6_STATE_SUPPORT +#define F15_TN_C6_STATE_SUPPORT + +#if OPTION_C6_STATE == TRUE + #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) + #ifdef OPTION_FAMILY12H + #if OPTION_FAMILY12H == TRUE + #if OPTION_FAMILY12H_LN == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State; + #undef OPTION_C6_STATE_FEAT + #define OPTION_C6_STATE_FEAT &CpuFeatureC6State, + extern CONST C6_FAMILY_SERVICES ROMDATA F12C6Support; + #undef F12_C6_STATE_SUPPORT + #define F12_C6_STATE_SUPPORT {AMD_FAMILY_12_LN, &F12C6Support}, + + #if OPTION_EARLY_SAMPLES == TRUE + extern F_F12_ES_C6_INIT F12C6A0Workaround; + + CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support = + { + F12C6A0Workaround + }; + #else + CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support = + { + (PF_F12_ES_C6_INIT) CommonVoid + }; + #endif + + #endif + #endif + #endif + + #ifdef OPTION_FAMILY14H + #if OPTION_FAMILY14H == TRUE + #if (OPTION_FAMILY14H_ON == TRUE) + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State; + #undef OPTION_C6_STATE_FEAT + #define OPTION_C6_STATE_FEAT &CpuFeatureC6State, + extern CONST C6_FAMILY_SERVICES ROMDATA F14OnC6Support; + #undef F14_ON_C6_STATE_SUPPORT + #define F14_ON_C6_STATE_SUPPORT {AMD_FAMILY_14_ON, &F14OnC6Support}, + + #if (OPTION_EARLY_SAMPLES == TRUE) + extern F_F14_ON_ES_IS_C6_SUPPORTED F14IsC6DisabledEarlySample; + extern F_F14_ON_ES_C6_INIT F14C6A0Workaround; + + CONST F14_ON_ES_C6_SUPPORT ROMDATA F14OnEarlySampleC6Support = + { + F14IsC6DisabledEarlySample, + F14C6A0Workaround + }; + #else + CONST F14_ON_ES_C6_SUPPORT ROMDATA F14OnEarlySampleC6Support = + { + (PF_F14_ON_ES_IS_C6_SUPPORTED) CommonVoid, + (PF_F14_ON_ES_C6_INIT) CommonVoid + }; + #endif + #endif + + + #endif + #endif + + #ifdef OPTION_FAMILY15H + #if OPTION_FAMILY15H == TRUE + #if (OPTION_FAMILY15H_OR == TRUE) + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State; + #undef OPTION_C6_STATE_FEAT + #define OPTION_C6_STATE_FEAT &CpuFeatureC6State, + extern CONST C6_FAMILY_SERVICES ROMDATA F15OrC6Support; + #undef F15_OR_C6_STATE_SUPPORT + #define F15_OR_C6_STATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrC6Support}, + + #if (OPTION_EARLY_SAMPLES == TRUE) + extern F_F15_OR_ES_IS_C6_SUPPORTED F15OrIsC6DisabledEarlySample; + + CONST F15_OR_ES_C6_SUPPORT ROMDATA F15OrEarlySampleC6Support = + { + F15OrIsC6DisabledEarlySample + }; + #else + CONST F15_OR_ES_C6_SUPPORT ROMDATA F15OrEarlySampleC6Support = + { + (PF_F15_OR_ES_IS_C6_SUPPORTED) CommonVoid + }; + #endif + #endif + + #if (OPTION_FAMILY15H_TN == TRUE) + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State; + #undef OPTION_C6_STATE_FEAT + #define OPTION_C6_STATE_FEAT &CpuFeatureC6State, + extern CONST C6_FAMILY_SERVICES ROMDATA F15TnC6Support; + #undef F15_TN_C6_STATE_SUPPORT + #define F15_TN_C6_STATE_SUPPORT {AMD_FAMILY_15_TN, &F15TnC6Support}, + #endif + + + #endif + #endif + #endif +#endif + +CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA C6FamilyServiceArray[] = +{ + F12_C6_STATE_SUPPORT + F14_ON_C6_STATE_SUPPORT + {0, NULL}, + F15_OR_C6_STATE_SUPPORT + F15_TN_C6_STATE_SUPPORT + {0, NULL}, + {0, NULL} +}; + +CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA C6FamilyServiceTable = +{ + (sizeof (C6FamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &C6FamilyServiceArray[0] +}; + +#endif // _OPTION_C6_STATE_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionCpbInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionCpbInstall.h new file mode 100644 index 0000000..4714150 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionCpbInstall.h @@ -0,0 +1,211 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: Core Performance Boost + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_CPB_INSTALL_H_ +#define _OPTION_CPB_INSTALL_H_ + +#include "cpuCpb.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#define OPTION_CPB_FEAT +#define F10_CPB_SUPPORT +#define F12_CPB_SUPPORT +#define F14_ON_CPB_SUPPORT +#define F15_OR_CPB_SUPPORT +#define F15_TN_CPB_SUPPORT + +#if OPTION_CPB == TRUE + #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE) + // Family 10h + #ifdef OPTION_FAMILY10H + #if OPTION_FAMILY10H == TRUE + #if OPTION_FAMILY10H_PH == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb; + #undef OPTION_CPB_FEAT + #define OPTION_CPB_FEAT &CpuFeatureCpb, + extern CONST CPB_FAMILY_SERVICES ROMDATA F10CpbSupport; + #undef F10_CPB_SUPPORT + #define F10_CPB_SUPPORT {AMD_FAMILY_10_PH, &F10CpbSupport}, + #endif + #endif + #endif + + // Family 12h + #ifdef OPTION_FAMILY12H + #if OPTION_FAMILY12H == TRUE + #if OPTION_FAMILY12H_LN == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb; + #undef OPTION_CPB_FEAT + #define OPTION_CPB_FEAT &CpuFeatureCpb, + extern CONST CPB_FAMILY_SERVICES ROMDATA F12CpbSupport; + #undef F12_CPB_SUPPORT + #define F12_CPB_SUPPORT {AMD_FAMILY_12_LN, &F12CpbSupport}, + #if OPTION_EARLY_SAMPLES == TRUE + #if (AGESA_ENTRY_INIT_EARLY == TRUE) + extern F_F12_ES_CPB_INIT F12LnA1CpbHook; + + CONST F12_ES_CPB_SUPPORT ROMDATA F12EarlySampleCpbSupport = + { + F12LnA1CpbHook + }; + #else + CONST F12_ES_CPB_SUPPORT ROMDATA F12EarlySampleCpbSupport = + { + (PF_F12_ES_CPB_INIT) CommonVoid + }; + #endif + #else + CONST F12_ES_CPB_SUPPORT ROMDATA F12EarlySampleCpbSupport = + { + (PF_F12_ES_CPB_INIT) CommonVoid + }; + #endif + #endif + #endif + #endif + + // Family 14h + #ifdef OPTION_FAMILY14H + #if OPTION_FAMILY14H == TRUE + #if OPTION_FAMILY14H_ON == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb; + #undef OPTION_CPB_FEAT + #define OPTION_CPB_FEAT &CpuFeatureCpb, + extern CONST CPB_FAMILY_SERVICES ROMDATA F14OnCpbSupport; + #undef F14_ON_CPB_SUPPORT + #define F14_ON_CPB_SUPPORT {AMD_FAMILY_14_ON, &F14OnCpbSupport}, + #endif + + #endif + #endif + + // Family 15h + #ifdef OPTION_FAMILY15H + #if OPTION_FAMILY15H == TRUE + #if (OPTION_FAMILY15H_OR == TRUE) + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb; + #undef OPTION_CPB_FEAT + #define OPTION_CPB_FEAT &CpuFeatureCpb, + extern CONST CPB_FAMILY_SERVICES ROMDATA F15OrCpbSupport; + #undef F15_OR_CPB_SUPPORT + #define F15_OR_CPB_SUPPORT {AMD_FAMILY_15_OR, &F15OrCpbSupport}, + + #if OPTION_EARLY_SAMPLES == TRUE + extern F_F15_OR_ES_IS_CPB_SUPPORTED F15OrIsCpbDisabledEarlySample; + + CONST F15_OR_ES_CPB_SUPPORT ROMDATA F15OrEarlySampleCpbSupport = + { + F15OrIsCpbDisabledEarlySample + }; + #else + CONST F15_OR_ES_CPB_SUPPORT ROMDATA F15OrEarlySampleCpbSupport = + { + (PF_F15_OR_ES_IS_CPB_SUPPORTED) CommonVoid + }; + #endif + #endif + + #if (OPTION_FAMILY15H_TN == TRUE) + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb; + #undef OPTION_CPB_FEAT + #define OPTION_CPB_FEAT &CpuFeatureCpb, + extern CONST CPB_FAMILY_SERVICES ROMDATA F15TnCpbSupport; + #undef F15_TN_CPB_SUPPORT + #define F15_TN_CPB_SUPPORT {AMD_FAMILY_15_TN, &F15TnCpbSupport}, + #endif + + #endif + #endif + + #endif +#endif + +CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpbFamilyServiceArray[] = +{ + F10_CPB_SUPPORT + F12_CPB_SUPPORT + F14_ON_CPB_SUPPORT + {0, NULL}, + F15_OR_CPB_SUPPORT + F15_TN_CPB_SUPPORT + {0, NULL}, + {0, NULL} +}; + +CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpbFamilyServiceTable = +{ + (sizeof (CpbFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &CpbFamilyServiceArray[0] +}; + +#endif // _OPTION_CPB_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuCacheFlushOnHaltInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuCacheFlushOnHaltInstall.h new file mode 100644 index 0000000..67af761 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuCacheFlushOnHaltInstall.h @@ -0,0 +1,154 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: CPU Cache Flush On Halt + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_ +#define _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_ + +#include "cpuPostInit.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT +#define F10_BL_CPU_CFOH_SUPPORT +#define F10_DA_CPU_CFOH_SUPPORT +#define F10_CPU_CFOH_SUPPORT +#define F15_OR_CPU_CFOH_SUPPORT +#define F15_TN_CPU_CFOH_SUPPORT + +#if OPTION_CPU_CFOH == TRUE + #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) + #ifdef OPTION_FAMILY10H + #if OPTION_FAMILY10H == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt; + #undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT + #define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt, + + #if OPTION_FAMILY10H_BL == TRUE + extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10BlCacheFlushOnHalt; + #undef F10_BL_CPU_CFOH_SUPPORT + #define F10_BL_CPU_CFOH_SUPPORT {AMD_FAMILY_10_BL, &F10BlCacheFlushOnHalt}, + #endif + + #if OPTION_FAMILY10H_DA == TRUE + extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10DaCacheFlushOnHalt; + #undef F10_DA_CPU_CFOH_SUPPORT + #define F10_DA_CPU_CFOH_SUPPORT {AMD_FAMILY_10_DA, &F10DaCacheFlushOnHalt}, + #endif + + #if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_HY == TRUE) || (OPTION_FAMILY10H_PH == TRUE) + extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10CacheFlushOnHalt; + #undef F10_CPU_CFOH_SUPPORT + #define F10_CPU_CFOH_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH, &F10CacheFlushOnHalt}, + #endif + #endif + #endif + + #ifdef OPTION_FAMILY15H + #if OPTION_FAMILY15H == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt; + #undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT + #define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt, + + #if OPTION_FAMILY15H_OR == TRUE + extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15OrCacheFlushOnHalt; + #undef F15_OR_CPU_CFOH_SUPPORT + #define F15_OR_CPU_CFOH_SUPPORT {AMD_FAMILY_15_OR, &F15OrCacheFlushOnHalt}, + #endif + + #if OPTION_FAMILY15H_TN == TRUE + extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15TnCacheFlushOnHalt; + #undef F15_TN_CPU_CFOH_SUPPORT + #define F15_TN_CPU_CFOH_SUPPORT {AMD_FAMILY_15_TN, &F15TnCacheFlushOnHalt}, + #endif + + #endif + #endif + #endif +#endif + +CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CacheFlushOnHaltFamilyServiceArray[] = +{ + F10_BL_CPU_CFOH_SUPPORT + F10_DA_CPU_CFOH_SUPPORT + F10_CPU_CFOH_SUPPORT + F15_OR_CPU_CFOH_SUPPORT + F15_TN_CPU_CFOH_SUPPORT + {0, NULL}, + {0, NULL} +}; +CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CacheFlushOnHaltFamilyServiceTable = +{ + (sizeof (CacheFlushOnHaltFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &CacheFlushOnHaltFamilyServiceArray[0] +}; + +#endif // _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuCoreLevelingInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuCoreLevelingInstall.h new file mode 100644 index 0000000..54ede2e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuCoreLevelingInstall.h @@ -0,0 +1,149 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: CPU Core Leveling + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_CPU_CORELEVELING_INSTALL_H_ +#define _OPTION_CPU_CORELEVELING_INSTALL_H_ + + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#define OPTION_CPU_CORE_LEVELING_FEAT +#define F10_REVE_CPU_CORELEVELING_SUPPORT +#define F10_REVD_CPU_CORELEVELING_SUPPORT +#define F10_REVC_CPU_CORELEVELING_SUPPORT +#define F15_OR_CPU_CORELEVELING_SUPPORT +#define F15_TN_CPU_CORELEVELING_SUPPORT + +#if OPTION_CPU_CORELEVLING == TRUE + #if (AGESA_ENTRY_INIT_EARLY == TRUE) + // Family 10h + #if OPTION_FAMILY10H == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling; + #undef OPTION_CPU_CORE_LEVELING_FEAT + #define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling, + #if OPTION_FAMILY10H_HY == TRUE + extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevDCoreLeveling; + #undef F10_REVD_CPU_CORELEVELING_SUPPORT + #define F10_REVD_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_HY, &F10RevDCoreLeveling}, + #endif + + #if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) + extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling; + #undef F10_REVC_CPU_CORELEVELING_SUPPORT + #define F10_REVC_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA, &F10RevCCoreLeveling}, + #endif + + #if (OPTION_FAMILY10H_PH == TRUE) + extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevECoreLeveling; + #undef F10_REVE_CPU_CORELEVELING_SUPPORT + #define F10_REVE_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_PH, &F10RevECoreLeveling}, + #endif + #endif + // Family 15h + #if OPTION_FAMILY15H == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling; + #undef OPTION_CPU_CORE_LEVELING_FEAT + #define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling, + + #if (OPTION_FAMILY15H_OR == TRUE) + extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15OrCoreLeveling; + #undef F15_OR_CPU_CORELEVELING_SUPPORT + #define F15_OR_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_15_OR, &F15OrCoreLeveling}, + #endif + + #if (OPTION_FAMILY15H_TN == TRUE) + extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15TnCoreLeveling; + #undef F15_TN_CPU_CORELEVELING_SUPPORT + #define F15_TN_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_15_TN, &F15TnCoreLeveling}, + #endif + + #endif + #endif +#endif + +CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CoreLevelingFamilyServiceArray[] = +{ + {0, NULL}, + F15_TN_CPU_CORELEVELING_SUPPORT + F15_OR_CPU_CORELEVELING_SUPPORT + F10_REVE_CPU_CORELEVELING_SUPPORT + F10_REVD_CPU_CORELEVELING_SUPPORT + F10_REVC_CPU_CORELEVELING_SUPPORT + {0, NULL} +}; +CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CoreLevelingFamilyServiceTable = +{ + (sizeof (CoreLevelingFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &CoreLevelingFamilyServiceArray[0] +}; + +#endif // _OPTION_CPU_CORELEVELING_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuFamiliesInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuFamiliesInstall.h new file mode 100644 index 0000000..22e3bb9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuFamiliesInstall.h @@ -0,0 +1,434 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of all appropriate CPU family specific support. + * + * This file generates the defaults tables for all family specific + * combinations. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +/* Default all CPU Specific Service members to off. They + will be enabled as needed by cross referencing families + with entry points in the family / model install files. */ +#define GET_PSTATE_POWER FALSE +#define GET_PSTATE_FREQ FALSE +#define DISABLE_PSTATE FALSE +#define TRANSITION_PSTATE FALSE +#define PROC_IDD_MAX FALSE +#define GET_TSC_RATE FALSE +#define PSTATE_TRANSITION_LATENCY FALSE +#define GET_PSTATE_REGISTER_INFO FALSE +#define GET_PSTATE_MAX_STATE FALSE +#define SET_PSTATE_LEVELING_REG FALSE +#define GET_NB_FREQ FALSE +#define GET_NB_IDD_MAX FALSE +#define IS_NBCOF_INIT_NEEDED FALSE +#define AP_INITIAL_LAUNCH FALSE +#define GET_AP_MAILBOX_FROM_HW FALSE +#define SET_AP_CORE_NUMBER FALSE +#define GET_AP_CORE_NUMBER FALSE +#define TRANSFER_AP_CORE_NUMBER FALSE +#define ID_POSITION_INITIAL_APICID FALSE +#define SAVE_FEATURES FALSE +#define WRITE_FEATURES FALSE +#define SET_DOWN_CORE_REG FALSE +#define SET_WARM_RESET_FLAG FALSE +#define GET_WARM_RESET_FLAG FALSE +#define USES_REGISTER_TABLES FALSE +#define BASE_FAMILY_PCI FALSE +#define MODEL_SPECIFIC_PCI FALSE +#define BASE_FAMILY_MSR FALSE +#define MODEL_SPECIFIC_MSR FALSE +#define BRAND_STRING1 FALSE +#define BRAND_STRING2 FALSE +#define BASE_FAMILY_HT_PCI FALSE +#define MODEL_SPECIFIC_HT_PCI FALSE +#define BASE_FAMILY_WORKAROUNDS FALSE +#define GET_PATCHES FALSE +#define GET_PATCHES_EQUIVALENCE_TABLE FALSE +#define GET_CACHE_INFO FALSE +#define GET_SYSTEM_PM_TABLE FALSE +#define GET_WHEA_INIT FALSE +#define GET_CFOH_REG FALSE +#define GET_PLATFORM_TYPE_SPECIFIC_INFO FALSE +#define IS_NB_PSTATE_ENABLED FALSE + +/* + * Pull in family specific services based on entry point + */ +#if AGESA_ENTRY_INIT_RESET == TRUE + #undef ID_POSITION_INITIAL_APICID + #define ID_POSITION_INITIAL_APICID TRUE + #undef GET_AP_MAILBOX_FROM_HW + #define GET_AP_MAILBOX_FROM_HW TRUE + #undef SET_WARM_RESET_FLAG + #define SET_WARM_RESET_FLAG TRUE + #undef GET_WARM_RESET_FLAG + #define GET_WARM_RESET_FLAG TRUE + #undef GET_CACHE_INFO + #define GET_CACHE_INFO TRUE + #undef GET_AP_CORE_NUMBER + #define GET_AP_CORE_NUMBER TRUE + #undef TRANSFER_AP_CORE_NUMBER + #define TRANSFER_AP_CORE_NUMBER TRUE +#endif + +#if AGESA_ENTRY_INIT_RECOVERY == TRUE + #undef ID_POSITION_INITIAL_APICID + #define ID_POSITION_INITIAL_APICID TRUE + #undef USES_REGISTER_TABLES + #define USES_REGISTER_TABLES TRUE + #undef BASE_FAMILY_PCI + #define BASE_FAMILY_PCI TRUE + #undef MODEL_SPECIFIC_PCI + #define MODEL_SPECIFIC_PCI TRUE + #undef BASE_FAMILY_MSR + #define BASE_FAMILY_MSR TRUE + #undef MODEL_SPECIFIC_MSR + #define MODEL_SPECIFIC_MSR TRUE + #undef GET_CACHE_INFO + #define GET_CACHE_INFO TRUE + #undef GET_PLATFORM_TYPE_SPECIFIC_INFO + #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE + #undef IS_NB_PSTATE_ENABLED + #define IS_NB_PSTATE_ENABLED TRUE + #undef GET_PATCHES + #define GET_PATCHES TRUE + #undef GET_PATCHES_EQUIVALENCE_TABLE + #define GET_PATCHES_EQUIVALENCE_TABLE TRUE +#endif + +#if AGESA_ENTRY_INIT_EARLY == TRUE + #undef TRANSITION_PSTATE + #define TRANSITION_PSTATE TRUE + #undef DISABLE_PSTATE + #define DISABLE_PSTATE TRUE + #undef PROC_IDD_MAX + #define PROC_IDD_MAX TRUE + #undef GET_TSC_RATE + #define GET_TSC_RATE TRUE + #undef GET_NB_FREQ + #define GET_NB_FREQ TRUE + #undef GET_NB_IDD_MAX + #define GET_NB_IDD_MAX TRUE + #undef IS_NBCOF_INIT_NEEDED + #define IS_NBCOF_INIT_NEEDED TRUE + #undef AP_INITIAL_LAUNCH + #define AP_INITIAL_LAUNCH TRUE + #undef GET_AP_MAILBOX_FROM_HW + #define GET_AP_MAILBOX_FROM_HW TRUE + #undef SET_AP_CORE_NUMBER + #define SET_AP_CORE_NUMBER TRUE + #undef GET_AP_CORE_NUMBER + #define GET_AP_CORE_NUMBER TRUE + #undef TRANSFER_AP_CORE_NUMBER + #define TRANSFER_AP_CORE_NUMBER TRUE + #undef ID_POSITION_INITIAL_APICID + #define ID_POSITION_INITIAL_APICID TRUE + #undef SET_DOWN_CORE_REG + #define SET_DOWN_CORE_REG TRUE + #undef SET_WARM_RESET_FLAG + #define SET_WARM_RESET_FLAG TRUE + #undef GET_WARM_RESET_FLAG + #define GET_WARM_RESET_FLAG TRUE + #undef USES_REGISTER_TABLES + #define USES_REGISTER_TABLES TRUE + #undef BASE_FAMILY_PCI + #define BASE_FAMILY_PCI TRUE + #undef MODEL_SPECIFIC_PCI + #define MODEL_SPECIFIC_PCI TRUE + #undef BASE_FAMILY_MSR + #define BASE_FAMILY_MSR TRUE + #undef MODEL_SPECIFIC_MSR + #define MODEL_SPECIFIC_MSR TRUE + #undef BRAND_STRING1 + #define BRAND_STRING1 TRUE + #undef BRAND_STRING2 + #define BRAND_STRING2 TRUE + #undef BASE_FAMILY_HT_PCI + #define BASE_FAMILY_HT_PCI TRUE + #undef MODEL_SPECIFIC_HT_PCI + #define MODEL_SPECIFIC_HT_PCI TRUE + #undef BASE_FAMILY_WORKAROUNDS + #define BASE_FAMILY_WORKAROUNDS TRUE + #undef GET_PATCHES + #define GET_PATCHES TRUE + #undef GET_PATCHES_EQUIVALENCE_TABLE + #define GET_PATCHES_EQUIVALENCE_TABLE TRUE + #undef GET_SYSTEM_PM_TABLE + #define GET_SYSTEM_PM_TABLE TRUE + #undef GET_CACHE_INFO + #define GET_CACHE_INFO TRUE + #undef GET_PLATFORM_TYPE_SPECIFIC_INFO + #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE + #undef IS_NB_PSTATE_ENABLED + #define IS_NB_PSTATE_ENABLED TRUE +#endif + +#if AGESA_ENTRY_INIT_POST == TRUE + #undef ID_POSITION_INITIAL_APICID + #define ID_POSITION_INITIAL_APICID TRUE + #undef GET_PSTATE_POWER + #define GET_PSTATE_POWER TRUE + #undef GET_PSTATE_FREQ + #define GET_PSTATE_FREQ TRUE + #undef TRANSITION_PSTATE + #define TRANSITION_PSTATE TRUE + #undef PROC_IDD_MAX + #define PROC_IDD_MAX TRUE + #undef GET_AP_CORE_NUMBER + #define GET_AP_CORE_NUMBER TRUE + #undef GET_PSTATE_REGISTER_INFO + #define GET_PSTATE_REGISTER_INFO TRUE + #undef GET_PSTATE_MAX_STATE + #define GET_PSTATE_MAX_STATE TRUE + #undef SET_PSTATE_LEVELING_REG + #define SET_PSTATE_LEVELING_REG TRUE + #undef SET_WARM_RESET_FLAG + #define SET_WARM_RESET_FLAG TRUE + #undef GET_WARM_RESET_FLAG + #define GET_WARM_RESET_FLAG TRUE + #undef SAVE_FEATURES + #define SAVE_FEATURES TRUE + #undef WRITE_FEATURES + #define WRITE_FEATURES TRUE + #undef GET_CFOH_REG + #define GET_CFOH_REG TRUE + #undef IS_NB_PSTATE_ENABLED + #define IS_NB_PSTATE_ENABLED TRUE +#endif + +#if AGESA_ENTRY_INIT_ENV == TRUE +#endif + +#if AGESA_ENTRY_INIT_MID == TRUE +#endif + +#if AGESA_ENTRY_INIT_LATE == TRUE + #undef GET_AP_CORE_NUMBER + #define GET_AP_CORE_NUMBER TRUE + #undef GET_PSTATE_FREQ + #define GET_PSTATE_FREQ TRUE + #undef TRANSITION_PSTATE + #define TRANSITION_PSTATE TRUE + #undef PSTATE_TRANSITION_LATENCY + #define PSTATE_TRANSITION_LATENCY TRUE + #undef GET_WHEA_INIT + #define GET_WHEA_INIT TRUE + #undef GET_PLATFORM_TYPE_SPECIFIC_INFO + #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE + #undef GET_TSC_RATE + #define GET_TSC_RATE TRUE + #undef BRAND_STRING1 + #define BRAND_STRING1 TRUE + #undef BRAND_STRING2 + #define BRAND_STRING2 TRUE +#endif + +#if AGESA_ENTRY_INIT_S3SAVE == TRUE +#endif + +#if AGESA_ENTRY_INIT_RESUME == TRUE + #undef GET_CFOH_REG + #define GET_CFOH_REG TRUE +#endif + +#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE +#endif + +#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE + #undef ID_POSITION_INITIAL_APICID + #define ID_POSITION_INITIAL_APICID TRUE +#endif + +/* + * Initialize PCI MMIO mask to 0 + */ +#define FAMILY_MMIO_BASE_MASK (0ull) + + +/* + * Initialize all families to disabled + */ +#define OPT_F10_TABLE +#define OPT_F12_TABLE +#define OPT_F14_TABLE +#define OPT_F15_TABLE + +#define OPT_F10_ID_TABLE +#define OPT_F12_ID_TABLE +#define OPT_F14_ID_TABLE +#define OPT_F15_ID_TABLE + + +/* + * Install family specific support + */ +#if (OPTION_FAMILY10H == TRUE) + #include "OptionFamily10hInstall.h" +#endif + +#if (OPTION_FAMILY12H == TRUE) + #include "OptionFamily12hInstall.h" +#endif + +#if (OPTION_FAMILY14H == TRUE) + #include "OptionFamily14hInstall.h" +#endif + +#if (OPTION_FAMILY15H_OR == TRUE) || (OPTION_FAMILY15H_TN == TRUE) + #include "OptionFamily15hInstall.h" +#endif + +/* + * Process PCI MMIO mask + */ + +// If size is 0, but base is not, break the build. +#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0) + #error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256 +#endif + +// If base is 0, but size is not, break the build. +#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0) + #error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater +#endif + +#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0) + // Both are non-zero, begin further processing. + + // Heap runs from 4MB to 8MB. Disallow any addresses below 8MB. + #if (CFG_PCI_MMIO_BASE < 0x800000) + #error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater + #endif + + // Break the build if the address is too high for the enabled families. + #if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0) + #error BLDCFG: Invalid PCI MMIO base address for the installed CPU families + #endif + + // If the size parameter is not valid, break the build. + #if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16) + #if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256) + #error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256 + #endif + #endif + + #define PCI_MMIO_ALIGNMENT ((0x100000ul * CFG_PCI_MMIO_SIZE) - 1) + // If the base is not aligned according to size, break the build. + #if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0) + #error BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size + #endif + #undef PCI_MMIO_ALIGNMENT +#endif + +/* + * Process sockets / modules + */ +#ifndef ADVCFG_PLATFORM_SOCKETS + #error BLDOPT Set Family supported sockets. +#endif +#ifndef ADVCFG_PLATFORM_MODULES + #error BLDOPT Set Family supported modules. +#endif + +CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration = +{ + ADVCFG_PLATFORM_SOCKETS, + ADVCFG_PLATFORM_MODULES +}; + +/* + * Instantiate global data needed for processor identification + */ +CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpuSupportedFamiliesArray[] = +{ + OPT_F10_TABLE + OPT_F12_TABLE + OPT_F14_TABLE + OPT_F15_TABLE + {0, NULL} +}; + +CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpuSupportedFamiliesTable = +{ + (sizeof (CpuSupportedFamiliesArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &CpuSupportedFamiliesArray[0] +}; + + +CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] = +{ + OPT_F10_ID_TABLE + OPT_F12_ID_TABLE + OPT_F14_ID_TABLE + OPT_F15_ID_TABLE + +}; + +CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable = +{ + (sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)), + CpuSupportedFamilyIdArray +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuFeaturesInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuFeaturesInstall.h new file mode 100644 index 0000000..26abdc5 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionCpuFeaturesInstall.h @@ -0,0 +1,108 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of multiple CPU features. + * + * Aggregates enabled CPU features into a list for the dispatcher to process. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 63692 $ @e $Date: 2012-01-03 22:13:28 -0600 (Tue, 03 Jan 2012) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_CPU_FEATURES_INSTALL_H_ +#define _OPTION_CPU_FEATURES_INSTALL_H_ + +#include "OptionHwC1eInstall.h" +#include "OptionMsgBasedC1eInstall.h" +#include "OptionSwC1eInstall.h" +#include "OptionL3FeaturesInstall.h" +#include "OptionCpuCoreLevelingInstall.h" +#include "OptionIoCstateInstall.h" +#include "OptionC6Install.h" +#include "OptionCpbInstall.h" +#include "OptionCpuCacheFlushOnHaltInstall.h" +#include "OptionPstateHpcModeInstall.h" +#include "OptionApmInstall.h" +#include "OptionPsiInstall.h" +#include "OptionHtcInstall.h" +#include "OptionPreserveMailboxInstall.h" + +CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[] = +{ + OPTION_HW_C1E_FEAT + OPTION_MSG_BASED_C1E_FEAT + OPTION_SW_C1E_FEAT + OPTION_L3_FEAT + OPTION_CPU_CORE_LEVELING_FEAT + OPTION_IO_CSTATE_FEAT + OPTION_C6_STATE_FEAT + OPTION_CPB_FEAT + OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT + OPTION_CPU_PSTATE_HPC_MODE_FEAT // this function should be run before low power pstate for prochot + OPTION_CPU_APM_FEAT + OPTION_CPU_PSI_FEAT + OPTION_CPU_HTC_FEAT + OPTION_PRESERVE_MAILBOX_FEAT + NULL +}; + + +#endif // _OPTION_CPU_FEATURES_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionDmi.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionDmi.h new file mode 100644 index 0000000..906c3be --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionDmi.h @@ -0,0 +1,116 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD DMI option API. + * + * Contains structures and values used to control the DMI option code. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: OPTION + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _OPTION_DMI_H_ +#define _OPTION_DMI_H_ + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *---------------------------------------------------------------------------------------- + */ + +typedef AGESA_STATUS OPTION_DMI_FEATURE ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT DMI_INFO **DmiPtr + ); + +typedef AGESA_STATUS OPTION_DMI_RELEASE_BUFFER ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +#define DMI_STRUCT_VERSION 0x01 + +/// DMI option configuration. Determine the item of structure when compiling. +typedef struct { + UINT16 OptDmiVersion; ///< Dmi version. + OPTION_DMI_FEATURE *DmiFeature; ///< Feature main routine, otherwise dummy. + OPTION_DMI_RELEASE_BUFFER *DmiReleaseBuffer; ///< Release buffer + UINT16 NumEntries; ///< Number of entry. + VOID *((*FamilyList)[]); ///< Family service. +} OPTION_DMI_CONFIGURATION; + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ + + +#endif // _OPTION_DMI_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h new file mode 100644 index 0000000..3acebaa --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h @@ -0,0 +1,242 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: DMI + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_DMI_INSTALL_H_ +#define _OPTION_DMI_INSTALL_H_ + +#include "cpuLateInit.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#if AGESA_ENTRY_INIT_LATE == TRUE + #ifndef OPTION_DMI + #error BLDOPT: Option not defined: "OPTION_DMI" + #endif + #if OPTION_DMI == TRUE + OPTION_DMI_FEATURE GetDmiInfoMain; + OPTION_DMI_RELEASE_BUFFER ReleaseDmiBuffer; + #define USER_DMI_OPTION &GetDmiInfoMain + #define USER_DMI_RELEASE_BUFFER &ReleaseDmiBuffer + + // This additional check keeps AP launch routines from being unnecessarily included + // in single socket systems. + #if OPTION_MULTISOCKET == TRUE + #undef AGESA_ENTRY_LATE_RUN_AP_TASK + #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE + #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info}, + #else + #define CPU_DMI_AP_GET_TYPE4_TYPE7 + #endif + + // Family 10 + #ifdef OPTION_FAMILY10H + #if OPTION_FAMILY10H == TRUE + extern PROC_FAMILY_TABLE ProcFamily10DmiTable; + #define FAM10_DMI_SUPPORT FAM10_ENABLED, + #define FAM10_DMI_TABLE &ProcFamily10DmiTable, + #else + #define FAM10_DMI_SUPPORT + #define FAM10_DMI_TABLE + #endif + #else + #define FAM10_DMI_SUPPORT + #define FAM10_DMI_TABLE + #endif + + // Family 12 + #ifdef OPTION_FAMILY12H + #if OPTION_FAMILY12H == TRUE + extern PROC_FAMILY_TABLE ProcFamily12DmiTable; + #define FAM12_DMI_SUPPORT FAM12_ENABLED, + #define FAM12_DMI_TABLE &ProcFamily12DmiTable, + #else + #define FAM12_DMI_SUPPORT + #define FAM12_DMI_TABLE + #endif + #else + #define FAM12_DMI_SUPPORT + #define FAM12_DMI_TABLE + #endif + + // Family 14 + #ifdef OPTION_FAMILY14H + #if OPTION_FAMILY14H == TRUE + extern PROC_FAMILY_TABLE ProcFamily14DmiTable; + #define FAM14_DMI_SUPPORT FAM14_ENABLED, + #define FAM14_DMI_TABLE &ProcFamily14DmiTable, + #else + #define FAM14_DMI_SUPPORT + #define FAM14_DMI_TABLE + #endif + #else + #define FAM14_DMI_SUPPORT + #define FAM14_DMI_TABLE + #endif + + // Family 15 + #ifdef OPTION_FAMILY15H + #if OPTION_FAMILY15H == TRUE + #if OPTION_FAMILY15H_OR == TRUE + extern PROC_FAMILY_TABLE ProcFamily15OrDmiTable; + #define FAM15_OR_DMI_SUPPORT FAM15_OR_ENABLED, + #define FAM15_OR_DMI_TABLE &ProcFamily15OrDmiTable, + #else + #define FAM15_OR_DMI_SUPPORT + #define FAM15_OR_DMI_TABLE + #endif + #if OPTION_FAMILY15H_TN == TRUE + extern PROC_FAMILY_TABLE ProcFamily15TnDmiTable; + #define FAM15_TN_DMI_SUPPORT FAM15_TN_ENABLED, + #define FAM15_TN_DMI_TABLE &ProcFamily15TnDmiTable, + #else + #define FAM15_TN_DMI_SUPPORT + #define FAM15_TN_DMI_TABLE + #endif + #else + #define FAM15_OR_DMI_SUPPORT + #define FAM15_OR_DMI_TABLE + #define FAM15_TN_DMI_SUPPORT + #define FAM15_TN_DMI_TABLE + #endif + #else + #define FAM15_OR_DMI_SUPPORT + #define FAM15_OR_DMI_TABLE + #define FAM15_TN_DMI_SUPPORT + #define FAM15_TN_DMI_TABLE + #endif + + #else + OPTION_DMI_FEATURE GetDmiInfoStub; + OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub; + #define USER_DMI_OPTION GetDmiInfoStub + #define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub + #define FAM10_DMI_SUPPORT + #define FAM10_DMI_TABLE + #define FAM12_DMI_SUPPORT + #define FAM12_DMI_TABLE + #define FAM14_DMI_SUPPORT + #define FAM14_DMI_TABLE + #define FAM15_OR_DMI_SUPPORT + #define FAM15_OR_DMI_TABLE + #define FAM15_TN_DMI_SUPPORT + #define FAM15_TN_DMI_TABLE + #define CPU_DMI_AP_GET_TYPE4_TYPE7 + #endif +#else + OPTION_DMI_FEATURE GetDmiInfoStub; + OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub; + #define USER_DMI_OPTION GetDmiInfoStub + #define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub + #define FAM10_DMI_SUPPORT + #define FAM10_DMI_TABLE + #define FAM12_DMI_SUPPORT + #define FAM12_DMI_TABLE + #define FAM14_DMI_SUPPORT + #define FAM14_DMI_TABLE + #define FAM15_OR_DMI_SUPPORT + #define FAM15_OR_DMI_TABLE + #define FAM15_TN_DMI_SUPPORT + #define FAM15_TN_DMI_TABLE + #define CPU_DMI_AP_GET_TYPE4_TYPE7 +#endif + +/// DMI supported families enum +typedef enum { + FAM10_DMI_SUPPORT ///< Conditionally define F10 support + FAM12_DMI_SUPPORT ///< Conditionally define F12 support + FAM14_DMI_SUPPORT ///< Conditionally define F14 support + FAM15_OR_DMI_SUPPORT ///< Conditionally define F15 OR support + FAM15_TN_DMI_SUPPORT ///< Conditionally define F15 TN support + NUM_DMI_FAMILIES ///< Number of installed families +} AGESA_DMI_SUPPORTED_FAM; + +/* Declare the Family List. An array of pointers to tables that each describe a family */ +CONST PROC_FAMILY_TABLE ROMDATA *ProcTables[] = { + FAM10_DMI_TABLE + FAM12_DMI_TABLE + FAM14_DMI_TABLE + FAM15_OR_DMI_TABLE + FAM15_TN_DMI_TABLE + NULL, + NULL +}; + +/* Declare the instance of the DMI option configuration structure */ +CONST OPTION_DMI_CONFIGURATION ROMDATA OptionDmiConfiguration = { + DMI_STRUCT_VERSION, + USER_DMI_OPTION, + USER_DMI_RELEASE_BUFFER, + NUM_DMI_FAMILIES, + (VOID *((*)[])) &ProcTables // Compiler says array size must match struct decl +}; + +#endif // _OPTION_DMI_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionFamily15hInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionFamily15hInstall.h new file mode 100644 index 0000000..2e17573 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionFamily15hInstall.h @@ -0,0 +1,1206 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of family 15h support + * + * This file generates the defaults tables for family 15h processors. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e $Revision: 64491 $ @e $Date: 2012-01-23 12:37:30 -0600 (Mon, 23 Jan 2012) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_FAMILY_15H_INSTALL_H_ +#define _OPTION_FAMILY_15H_INSTALL_H_ + +#include "cpuFamilyTranslation.h" + +/* + * Pull in family specific services based on entry point + */ + +/* + * Common Family 15h routines + */ +extern F_IS_NB_PSTATE_ENABLED F15IsNbPstateEnabled; + +/* + * Install family 15h model 0 support + */ +#ifdef OPTION_FAMILY15H_OR + #if OPTION_FAMILY15H_OR == TRUE + extern F_CPU_GET_IDD_MAX F15OrGetProcIddMax; + extern F_CPU_GET_NB_PSTATE_INFO F15OrGetNbPstateInfo; + extern F_CPU_IS_NBCOF_INIT_NEEDED F15CommonGetNbCofVidUpdate; + extern F_CPU_DISABLE_PSTATE F15DisablePstate; + extern F_CPU_TRANSITION_PSTATE F15TransitionPstate; + extern F_CPU_GET_TSC_RATE F15GetTscRate; + extern F_CPU_GET_NB_FREQ F15OrGetCurrentNbFrequency; + extern F_CPU_GET_MIN_MAX_NB_FREQ F15OrGetMinMaxNbFrequency; + extern F_CPU_AP_INITIAL_LAUNCH F15LaunchApCore; + extern F_CPU_NUMBER_OF_PHYSICAL_CORES F15OrGetNumberOfPhysicalCores; + extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F15OrGetApMailboxFromHardware; + extern F_CPU_SET_AP_CORE_NUMBER F15OrSetApCoreNumber; + extern F_CPU_GET_AP_CORE_NUMBER F15OrGetApCoreNumber; + extern F_CPU_TRANSFER_AP_CORE_NUMBER F15OrTransferApCoreNumber; + extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F15CpuAmdCoreIdPositionInInitialApicId; + extern F_CPU_SET_WARM_RESET_FLAG F15SetAgesaWarmResetFlag; + extern F_CPU_GET_WARM_RESET_FLAG F15GetAgesaWarmResetFlag; + extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15CacheInfo; + extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrSysPmTable; + extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15WheaInitData; + extern F_CPU_SET_CFOH_REG SetF15OrCacheFlushOnHaltRegister; + extern F_NEXT_LINK_HAS_HTFPY_FEATS F15NextLinkHasHtPhyFeats; + extern F_SET_HT_PHY_REGISTER F15SetHtPhyRegister; + extern F_GET_NEXT_HT_LINK_FEATURES F15GetNextHtLinkFeatures; + extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrMicroCodePatchesStruct; + extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrMicrocodeEquivalenceTable; + extern F_GET_EARLY_INIT_TABLE GetF15OrEarlyInitOnCoreTable; + extern CONST REGISTER_TABLE ROMDATA F15OrPciRegisterTable; + extern CONST REGISTER_TABLE ROMDATA F15OrMsrRegisterTable; + extern CONST REGISTER_TABLE ROMDATA F15OrSharedMsrRegisterTable; + extern CONST REGISTER_TABLE ROMDATA F15OrSharedMsrCuRegisterTable; + extern CONST REGISTER_TABLE ROMDATA F15OrSharedMsrWorkaroundTable; + extern CONST REGISTER_TABLE ROMDATA F15OrHtPhyRegisterTable; + extern CONST REGISTER_TABLE ROMDATA F15PciRegisterTable; + extern CONST REGISTER_TABLE ROMDATA F15MsrRegisterTable; + extern CONST REGISTER_TABLE ROMDATA F15OrMultiLinkPciRegisterTable; + extern CONST REGISTER_TABLE ROMDATA F15OrSingleLinkPciRegisterTable; + extern CONST REGISTER_TABLE ROMDATA F15OrWorkaroundsTable; + extern CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam15PackageLinkMap[]; + + /** + * Core Pair and core pair primary determination table. + * + * The two fields from the core pair hardware register can be used to determine whether + * even number cores are primary or all cores are primary. It can be extended if it is + * decided to have other configs as well. The other logically possible value sets are BitMapMapping, + * but they are currently not supported by the processor. + */ + CONST CORE_PAIR_MAP ROMDATA HtFam15CorePairMapping[] = + { + {1, 1, EvenCoresMapping}, ///< 1 Compute Unit with 2 cores + {3, 3, EvenCoresMapping}, ///< 2 Compute Units both with 2 Cores + {7, 7, EvenCoresMapping}, ///< 3 Compute Units all with 2 Cores + {0xF, 0xF, EvenCoresMapping}, ///< 4 Compute Units all with 2 Cores + {1, 0, AllCoresMapping}, ///< 1 Compute Unit with 1 core + {3, 0, AllCoresMapping}, ///< 2 Compute Units both with 1 Core + {7, 0, AllCoresMapping}, ///< 3 Compute Units all with 1 Core + {0xF, 0, AllCoresMapping}, ///< 4 Compute Units all with 1 Core + {HT_LIST_TERMINAL, HT_LIST_TERMINAL, MaxComputeUnitMapping} ///< End + }; + + + #if USES_REGISTER_TABLES == TRUE + CONST REGISTER_TABLE ROMDATA *F15OrRegisterTables[] = + { + #if BASE_FAMILY_PCI == TRUE + &F15PciRegisterTable, + #endif + #if MODEL_SPECIFIC_PCI == TRUE + &F15OrMultiLinkPciRegisterTable, + &F15OrSingleLinkPciRegisterTable, + #endif + #if MODEL_SPECIFIC_PCI == TRUE + &F15OrPciRegisterTable, + #if OPTION_EARLY_SAMPLES == TRUE + &F15OrEarlySamplePciRegisterTable, + #endif + #endif + #if BASE_FAMILY_MSR == TRUE + &F15MsrRegisterTable, + #endif + #if MODEL_SPECIFIC_MSR == TRUE + &F15OrMsrRegisterTable, + #if OPTION_EARLY_SAMPLES == TRUE + &F15OrEarlySampleMsrRegisterTable, + #endif + #endif + #if MODEL_SPECIFIC_MSR == TRUE + &F15OrSharedMsrRegisterTable, + &F15OrSharedMsrCuRegisterTable, + &F15OrSharedMsrWorkaroundTable, + #if OPTION_EARLY_SAMPLES == TRUE + &F15OrEarlySampleSharedMsrRegisterTable, + &F15OrEarlySampleSharedMsrWorkaroundTable, + #endif + #endif + #if MODEL_SPECIFIC_HT_PCI == TRUE + &F15OrHtPhyRegisterTable, + #endif + #if BASE_FAMILY_WORKAROUNDS == TRUE + &F15OrWorkaroundsTable, + #if OPTION_EARLY_SAMPLES == TRUE + &F15OrEarlySampleWorkaroundsTable, + #endif + #endif + // the end. + NULL + }; + #endif + + #if USES_REGISTER_TABLES == TRUE + CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15OrTableEntryTypeDescriptors[] = + { + {MsrRegister, SetRegisterForMsrEntry}, + {PciRegister, SetRegisterForPciEntry}, + {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry}, + {HtPhyRegister, SetRegisterForHtPhyEntry}, + {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry}, + {DeemphasisRegister, SetRegisterForDeemphasisEntry}, + {HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry}, + {ProfileFixup, SetRegisterForPerformanceProfileEntry}, + {HtHostPciRegister, SetRegisterForHtHostEntry}, + {HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry}, + {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry}, + {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry}, + {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry}, + {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry}, + {TokenPciRegister, SetRegisterForTokenPciEntry}, + {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry}, + {HtLinkPciRegister, SetRegisterForHtLinkPciEntry}, + {CompUnitCountsMsr, SetMsrForComputeUnitCountsEntry}, + // End + {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid} + }; + #endif + + CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15OrServices = + { + 0, + #if DISABLE_PSTATE == TRUE + F15DisablePstate, + #else + (PF_CPU_DISABLE_PSTATE) CommonAssert, + #endif + #if TRANSITION_PSTATE == TRUE + F15TransitionPstate, + #else + (PF_CPU_TRANSITION_PSTATE) CommonAssert, + #endif + #if PROC_IDD_MAX == TRUE + F15OrGetProcIddMax, + #else + (PF_CPU_GET_IDD_MAX) CommonAssert, + #endif + #if GET_TSC_RATE == TRUE + F15GetTscRate, + #else + (PF_CPU_GET_TSC_RATE) CommonAssert, + #endif + #if GET_NB_FREQ == TRUE + F15OrGetCurrentNbFrequency, + #else + (PF_CPU_GET_NB_FREQ) CommonAssert, + #endif + #if GET_NB_FREQ == TRUE + F15OrGetMinMaxNbFrequency, + #else + (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert, + #endif + #if GET_NB_FREQ == TRUE + F15OrGetNbPstateInfo, + #else + (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert, + #endif + #if IS_NBCOF_INIT_NEEDED == TRUE + F15CommonGetNbCofVidUpdate, + #else + (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert, + #endif + #if GET_NB_IDD_MAX == TRUE + (PF_CPU_GET_NB_IDD_MAX) CommonAssert, + #else + (PF_CPU_GET_NB_IDD_MAX) CommonAssert, + #endif + #if AP_INITIAL_LAUNCH == TRUE + F15LaunchApCore, + #else + (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert, + #endif + #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE) + F15OrGetNumberOfPhysicalCores, + #else + (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert, + #endif + #if GET_AP_MAILBOX_FROM_HW == TRUE + F15OrGetApMailboxFromHardware, + #else + (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert, + #endif + #if SET_AP_CORE_NUMBER == TRUE + F15OrSetApCoreNumber, + #else + (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert, + #endif + #if GET_AP_CORE_NUMBER == TRUE + F15OrGetApCoreNumber, + #else + (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert, + #endif + #if TRANSFER_AP_CORE_NUMBER == TRUE + F15OrTransferApCoreNumber, + #else + (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert, + #endif + #if ID_POSITION_INITIAL_APICID == TRUE + F15CpuAmdCoreIdPositionInInitialApicId, + #else + (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert, + #endif + #if SAVE_FEATURES == TRUE + // F15OrSaveFeatures, + (PF_CPU_SAVE_FEATURES) CommonVoid, + #else + (PF_CPU_SAVE_FEATURES) CommonAssert, + #endif + #if WRITE_FEATURES == TRUE + // F15OrWriteFeatures, + (PF_CPU_WRITE_FEATURES) CommonVoid, + #else + (PF_CPU_WRITE_FEATURES) CommonAssert, + #endif + #if SET_WARM_RESET_FLAG == TRUE + F15SetAgesaWarmResetFlag, + #else + (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert, + #endif + #if GET_WARM_RESET_FLAG == TRUE + F15GetAgesaWarmResetFlag, + #else + (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert, + #endif + #if BRAND_STRING1 == TRUE + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if BRAND_STRING2 == TRUE + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_PATCHES == TRUE + GetF15OrMicroCodePatchesStruct, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE + GetF15OrMicrocodeEquivalenceTable, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_CACHE_INFO == TRUE + GetF15CacheInfo, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_SYSTEM_PM_TABLE == TRUE + GetF15OrSysPmTable, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_WHEA_INIT == TRUE + GetF15WheaInitData, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE + (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess, + #else + (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert, + #endif + #if IS_NB_PSTATE_ENABLED == TRUE + F15IsNbPstateEnabled, + #else + (PF_IS_NB_PSTATE_ENABLED) CommonAssert, + #endif + #if (BASE_FAMILY_HT_PCI == TRUE) + F15NextLinkHasHtPhyFeats, + #else + (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse, + #endif + #if (BASE_FAMILY_HT_PCI == TRUE) + F15SetHtPhyRegister, + #else + (PF_SET_HT_PHY_REGISTER) CommonAssert, + #endif + #if BASE_FAMILY_PCI == TRUE + F15GetNextHtLinkFeatures, + #else + (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert, + #endif + #if USES_REGISTER_TABLES == TRUE + (REGISTER_TABLE **) F15OrRegisterTables, + #else + NULL, + #endif + #if USES_REGISTER_TABLES == TRUE + (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15OrTableEntryTypeDescriptors, + #else + NULL, + #endif + #if MODEL_SPECIFIC_HT_PCI == TRUE + (PACKAGE_HTLINK_MAP) &HtFam15PackageLinkMap, + #else + NULL, + #endif + (CORE_PAIR_MAP *) &HtFam15CorePairMapping, + InitCacheEnabled, + #if AGESA_ENTRY_INIT_EARLY == TRUE + GetF15OrEarlyInitOnCoreTable + #else + (PF_GET_EARLY_INIT_TABLE) CommonVoid + #endif + }; + + #define OR_SOCKETS 8 + #define OR_MODULES 2 + #define OR_RECOVERY_SOCKETS 1 + #define OR_RECOVERY_MODULES 1 + extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF15OrLogicalIdAndRev; + #define OPT_F15_OR_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF15OrLogicalIdAndRev, + #ifndef ADVCFG_PLATFORM_SOCKETS + #define ADVCFG_PLATFORM_SOCKETS OR_SOCKETS + #else + #if ADVCFG_PLATFORM_SOCKETS < OR_SOCKETS + #undef ADVCFG_PLATFORM_SOCKETS + #define ADVCFG_PLATFORM_SOCKETS OR_SOCKETS + #endif + #endif + #ifndef ADVCFG_PLATFORM_MODULES + #define ADVCFG_PLATFORM_MODULES OR_MODULES + #else + #if ADVCFG_PLATFORM_MODULES < OR_MODULES + #undef ADVCFG_PLATFORM_MODULES + #define ADVCFG_PLATFORM_MODULES OR_MODULES + #endif + #endif + + #if GET_PATCHES == TRUE + #define F15_OR_UCODE_17_UNENC + #define F15_OR_UCODE_11F_UNENC + #define F15_OR_UCODE_425 + #define F15_OR_UCODE_509 + #define F15_OR_UCODE_602 + + #if AGESA_ENTRY_INIT_EARLY == TRUE + extern CONST UINT8 ROMDATA CpuF15OrMicrocodePatch06000602 []; + #undef F15_OR_UCODE_602 + #define F15_OR_UCODE_602 CpuF15OrMicrocodePatch06000602, + #endif + + CONST UINT8 ROMDATA *CpuF15OrMicroCodePatchArray[] = + { + F15_OR_UCODE_602 + F15_OR_UCODE_509 + F15_OR_UCODE_425 + F15_OR_UCODE_11F_UNENC + F15_OR_UCODE_17_UNENC + NULL + }; + + CONST UINT8 ROMDATA CpuF15OrNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF15OrMicroCodePatchArray) / sizeof (CpuF15OrMicroCodePatchArray[0])) - 1); + #endif + + #if OPTION_EARLY_SAMPLES == TRUE + extern F_F15_OR_ES_AVOID_NB_CYCLES_START F15OrEarlySamplesAvoidNbCyclesStart; + extern F_F15_OR_ES_AVOID_NB_CYCLES_END F15OrEarlySamplesAvoidNbCyclesEnd; + extern F_F15_OR_ES_LOAD_MCU_PATCH F15OrEarlySamplesLoadMicrocodePatch; + extern F_F15_OR_ES_AFTER_PATCH_LOADED F15OrEarlySamplesAfterPatchLoaded; + + CONST F15_OR_ES_MCU_PATCH ROMDATA F15OrEarlySampleLoadMcuPatch = + { + F15OrEarlySamplesAvoidNbCyclesStart, + F15OrEarlySamplesAvoidNbCyclesEnd, + F15OrEarlySamplesLoadMicrocodePatch, + F15OrEarlySamplesAfterPatchLoaded + }; + #else + CONST F15_OR_ES_MCU_PATCH ROMDATA F15OrEarlySampleLoadMcuPatch = + { + (PF_F15_OR_ES_AVOID_NB_CYCLES_START) CommonVoid, + (PF_F15_OR_ES_AVOID_NB_CYCLES_END) CommonVoid, + (PF_F15_OR_ES_LOAD_MCU_PATCH) LoadMicrocodePatch, + (PF_F15_OR_ES_AFTER_PATCH_LOADED) CommonVoid + }; + #endif + + #if OPTION_EARLY_SAMPLES == TRUE + extern F_F15_OR_ES_HTC_INIT_HOOK F15OrHtcInitEarlySampleHook; + + CONST F15_OR_ES_CORE_SUPPORT ROMDATA F15OrEarlySampleCoreSupport = + { + #if AGESA_ENTRY_INIT_EARLY == TRUE + F15OrHtcInitEarlySampleHook, + #else + (PF_F15_OR_ES_HTC_INIT_HOOK) CommonAssert, + #endif + }; + #else + CONST F15_OR_ES_CORE_SUPPORT ROMDATA F15OrEarlySampleCoreSupport = + { + #if AGESA_ENTRY_INIT_EARLY == TRUE + (PF_F15_OR_ES_HTC_INIT_HOOK) CommonVoid, + #else + (PF_F15_OR_ES_HTC_INIT_HOOK) CommonAssert, + #endif + }; + #endif + + #define OPT_F15_OR_CPU {AMD_FAMILY_15_OR, &cpuF15OrServices}, + + #else // OPTION_FAMILY15H_OR == TRUE + #define OPT_F15_OR_CPU + #define OPT_F15_OR_ID + #endif // OPTION_FAMILY15H_OR == TRUE +#else // defined (OPTION_FAMILY15H_OR) + #define OPT_F15_OR_CPU + #define OPT_F15_OR_ID +#endif // defined (OPTION_FAMILY15H_OR) + + +/* + * Install family 15h model 10h - 1Fh support + */ +#ifdef OPTION_FAMILY15H_TN + #if OPTION_FAMILY15H_TN == TRUE + extern F_CPU_GET_IDD_MAX F15TnGetProcIddMax; + extern F_CPU_GET_NB_PSTATE_INFO F15TnGetNbPstateInfo; + extern F_CPU_IS_NBCOF_INIT_NEEDED F15CommonGetNbCofVidUpdate; + extern F_CPU_GET_NB_IDD_MAX F15TnGetNbIddMax; + extern F_CPU_DISABLE_PSTATE F15DisablePstate; + extern F_CPU_TRANSITION_PSTATE F15TransitionPstate; + extern F_CPU_GET_TSC_RATE F15GetTscRate; + extern F_CPU_GET_NB_FREQ F15TnGetCurrentNbFrequency; + extern F_CPU_GET_MIN_MAX_NB_FREQ F15TnGetMinMaxNbFrequency; + extern F_CPU_AP_INITIAL_LAUNCH F15LaunchApCore; + extern F_CPU_NUMBER_OF_PHYSICAL_CORES F15TnGetNumberOfPhysicalCores; + extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F15TnGetApMailboxFromHardware; + extern F_CPU_GET_AP_CORE_NUMBER F15TnGetApCoreNumber; + extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F15CpuAmdCoreIdPositionInInitialApicId; + extern F_CPU_SET_WARM_RESET_FLAG F15SetAgesaWarmResetFlag; + extern F_CPU_GET_WARM_RESET_FLAG F15GetAgesaWarmResetFlag; + extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15CacheInfo; + extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15TnSysPmTable; + extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15WheaInitData; + extern F_IS_NB_PSTATE_ENABLED F15TnIsNbPstateEnabled; + extern F_CPU_SET_CFOH_REG SetF15TnCacheFlushOnHaltRegister; + extern F_NEXT_LINK_HAS_HTFPY_FEATS F15NextLinkHasHtPhyFeats; + extern F_SET_HT_PHY_REGISTER F15SetHtPhyRegister; + extern F_GET_NEXT_HT_LINK_FEATURES F15GetNextHtLinkFeatures; + extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15TnMicroCodePatchesStruct; + extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15TnMicrocodeEquivalenceTable; + extern F_GET_EARLY_INIT_TABLE GetF15TnEarlyInitOnCoreTable; + extern CONST REGISTER_TABLE ROMDATA F15TnPciRegisterTable; + extern CONST REGISTER_TABLE ROMDATA F15TnPciWorkaroundTable; + extern CONST REGISTER_TABLE ROMDATA F15TnMsrRegisterTable; + extern CONST REGISTER_TABLE ROMDATA F15TnMsrWorkaroundTable; + extern CONST REGISTER_TABLE ROMDATA F15TnSharedMsrRegisterTable; + extern CONST REGISTER_TABLE ROMDATA F15TnSharedMsrCuRegisterTable; + extern CONST REGISTER_TABLE ROMDATA F15TnSharedMsrWorkaroundTable; + extern CONST REGISTER_TABLE ROMDATA F15TnPerNodeMsrWorkaroundTable; + extern CONST REGISTER_TABLE ROMDATA F15PciRegisterTable; + extern CONST REGISTER_TABLE ROMDATA F15MsrRegisterTable; + + /** + * Core Pair and core pair primary determination table. + * + * The two fields from the core pair hardware register can be used to determine whether + * even number cores are primary or all cores are primary. It can be extended if it is + * decided to have other configs as well. The other logically possible value sets are BitMapMapping, + * but they are currently not supported by the processor. + */ + CONST CORE_PAIR_MAP ROMDATA HtFam15TnCorePairMapping[] = + { + {1, 1, EvenCoresMapping}, ///< 1 Compute Unit with 2 cores + {3, 3, EvenCoresMapping}, ///< 2 Compute Units both with 2 Cores + {1, 0, AllCoresMapping}, ///< 1 Compute Unit with 1 core + {3, 0, AllCoresMapping}, ///< 2 Compute Units both with 1 Core + {HT_LIST_TERMINAL, HT_LIST_TERMINAL, MaxComputeUnitMapping} ///< End + }; + + + #if USES_REGISTER_TABLES == TRUE + CONST REGISTER_TABLE ROMDATA *F15TnRegisterTables[] = + { + #if BASE_FAMILY_PCI == TRUE + &F15PciRegisterTable, + #endif + #if MODEL_SPECIFIC_PCI == TRUE + &F15TnPciRegisterTable, + &F15TnPciWorkaroundTable, + #endif + #if BASE_FAMILY_MSR == TRUE + &F15MsrRegisterTable, + #endif + #if MODEL_SPECIFIC_MSR == TRUE + &F15TnMsrRegisterTable, + &F15TnMsrWorkaroundTable, + &F15TnSharedMsrRegisterTable, + &F15TnSharedMsrCuRegisterTable, + &F15TnSharedMsrWorkaroundTable, + &F15TnPerNodeMsrWorkaroundTable, + #endif + // the end. + NULL + }; + #endif + + #if USES_REGISTER_TABLES == TRUE + CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15TnTableEntryTypeDescriptors[] = + { + {MsrRegister, SetRegisterForMsrEntry}, + {PciRegister, SetRegisterForPciEntry}, + {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry}, + {ProfileFixup, SetRegisterForPerformanceProfileEntry}, + {CompUnitCountsMsr, SetMsrForComputeUnitCountsEntry}, + {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry}, + {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry}, + {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry}, + // End + {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid} + }; + #endif + + CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15TnServices = + { + 0, + #if DISABLE_PSTATE == TRUE + F15DisablePstate, + #else + (PF_CPU_DISABLE_PSTATE) CommonAssert, + #endif + #if TRANSITION_PSTATE == TRUE + F15TransitionPstate, + #else + (PF_CPU_TRANSITION_PSTATE) CommonAssert, + #endif + #if PROC_IDD_MAX == TRUE + F15TnGetProcIddMax, + #else + (PF_CPU_GET_IDD_MAX) CommonAssert, + #endif + #if GET_TSC_RATE == TRUE + F15GetTscRate, + #else + (PF_CPU_GET_TSC_RATE) CommonAssert, + #endif + #if GET_NB_FREQ == TRUE + F15TnGetCurrentNbFrequency, + #else + (PF_CPU_GET_NB_FREQ) CommonAssert, + #endif + #if GET_NB_FREQ == TRUE + F15TnGetMinMaxNbFrequency, + #else + (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert, + #endif + #if GET_NB_FREQ == TRUE + F15TnGetNbPstateInfo, + #else + (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert, + #endif + #if IS_NBCOF_INIT_NEEDED == TRUE + F15CommonGetNbCofVidUpdate, + #else + (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert, + #endif + #if GET_NB_IDD_MAX == TRUE + (PF_CPU_GET_NB_IDD_MAX) F15TnGetNbIddMax, + #else + (PF_CPU_GET_NB_IDD_MAX) CommonAssert, + #endif + #if AP_INITIAL_LAUNCH == TRUE + F15LaunchApCore, + #else + (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert, + #endif + #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE) + F15TnGetNumberOfPhysicalCores, + #else + (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert, + #endif + #if GET_AP_MAILBOX_FROM_HW == TRUE + F15TnGetApMailboxFromHardware, + #else + (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert, + #endif + #if SET_AP_CORE_NUMBER == TRUE + (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid, + #else + (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert, + #endif + #if GET_AP_CORE_NUMBER == TRUE + F15TnGetApCoreNumber, + #else + (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert, + #endif + #if TRANSFER_AP_CORE_NUMBER == TRUE + (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid, + #else + (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert, + #endif + #if ID_POSITION_INITIAL_APICID == TRUE + F15CpuAmdCoreIdPositionInInitialApicId, + #else + (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert, + #endif + #if SAVE_FEATURES == TRUE + (PF_CPU_SAVE_FEATURES) CommonVoid, + #else + (PF_CPU_SAVE_FEATURES) CommonAssert, + #endif + #if WRITE_FEATURES == TRUE + (PF_CPU_WRITE_FEATURES) CommonVoid, + #else + (PF_CPU_WRITE_FEATURES) CommonAssert, + #endif + #if SET_WARM_RESET_FLAG == TRUE + F15SetAgesaWarmResetFlag, + #else + (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert, + #endif + #if GET_WARM_RESET_FLAG == TRUE + F15GetAgesaWarmResetFlag, + #else + (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert, + #endif + #if BRAND_STRING1 == TRUE + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if BRAND_STRING2 == TRUE + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_PATCHES == TRUE + GetF15TnMicroCodePatchesStruct, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE + GetF15TnMicrocodeEquivalenceTable, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_CACHE_INFO == TRUE + GetF15CacheInfo, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_SYSTEM_PM_TABLE == TRUE + GetF15TnSysPmTable, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_WHEA_INIT == TRUE + GetF15WheaInitData, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE + (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess, + #else + (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert, + #endif + #if IS_NB_PSTATE_ENABLED == TRUE + F15TnIsNbPstateEnabled, + #else + (PF_IS_NB_PSTATE_ENABLED) CommonAssert, + #endif + #if (BASE_FAMILY_HT_PCI == TRUE) + F15NextLinkHasHtPhyFeats, + #else + (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse, + #endif + #if (BASE_FAMILY_HT_PCI == TRUE) + F15SetHtPhyRegister, + #else + (PF_SET_HT_PHY_REGISTER) CommonAssert, + #endif + #if BASE_FAMILY_PCI == TRUE + F15GetNextHtLinkFeatures, + #else + (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert, + #endif + #if USES_REGISTER_TABLES == TRUE + (REGISTER_TABLE **) F15TnRegisterTables, + #else + NULL, + #endif + #if USES_REGISTER_TABLES == TRUE + (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15TnTableEntryTypeDescriptors, + #else + NULL, + #endif + #if MODEL_SPECIFIC_HT_PCI == TRUE + NULL, + #else + NULL, + #endif + (CORE_PAIR_MAP *) &HtFam15TnCorePairMapping, + InitCacheEnabled, + #if AGESA_ENTRY_INIT_EARLY == TRUE + GetF15TnEarlyInitOnCoreTable + #else + (PF_GET_EARLY_INIT_TABLE) CommonVoid + #endif + }; + + #define TN_SOCKETS 1 + #define TN_MODULES 1 + #define TN_RECOVERY_SOCKETS 1 + #define TN_RECOVERY_MODULES 1 + extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF15TnLogicalIdAndRev; + #define OPT_F15_TN_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF15TnLogicalIdAndRev, + #ifndef ADVCFG_PLATFORM_SOCKETS + #define ADVCFG_PLATFORM_SOCKETS TN_SOCKETS + #else + #if ADVCFG_PLATFORM_SOCKETS < TN_SOCKETS + #undef ADVCFG_PLATFORM_SOCKETS + #define ADVCFG_PLATFORM_SOCKETS TN_SOCKETS + #endif + #endif + #ifndef ADVCFG_PLATFORM_MODULES + #define ADVCFG_PLATFORM_MODULES TN_MODULES + #else + #if ADVCFG_PLATFORM_MODULES < TN_MODULES + #undef ADVCFG_PLATFORM_MODULES + #define ADVCFG_PLATFORM_MODULES TN_MODULES + #endif + #endif + + #if GET_PATCHES == TRUE + #define F15_TN_UCODE_10F + #define F15_TN_UCODE_0E + + #if AGESA_ENTRY_INIT_EARLY == TRUE + extern CONST UINT8 ROMDATA CpuF15TnMicrocodePatch0600110F_Enc []; + #undef F15_TN_UCODE_10F + #define F15_TN_UCODE_10F CpuF15TnMicrocodePatch0600110F_Enc, + + #endif + + CONST UINT8 ROMDATA *CpuF15TnMicroCodePatchArray[] = + { + F15_TN_UCODE_10F + F15_TN_UCODE_0E + NULL + }; + + CONST UINT8 ROMDATA CpuF15TnNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF15TnMicroCodePatchArray) / sizeof (CpuF15TnMicroCodePatchArray[0])) - 1); + #endif + + + + #define OPT_F15_TN_CPU {AMD_FAMILY_15_TN, &cpuF15TnServices}, + + #else // OPTION_FAMILY15H_TN == TRUE + #define OPT_F15_TN_CPU + #define OPT_F15_TN_ID + #endif // OPTION_FAMILY15H_TN == TRUE +#else // defined (OPTION_FAMILY15H_TN) + #define OPT_F15_TN_CPU + #define OPT_F15_TN_ID +#endif // defined (OPTION_FAMILY15H_TN) + + + +/* + * Install unknown family 15h support + */ + +#ifdef OPTION_FAMILY15H_UNKNOWN + #if OPTION_FAMILY15H_UNKNOWN == TRUE + #if USES_REGISTER_TABLES == TRUE + CONST REGISTER_TABLE ROMDATA *F15UnknownRegisterTables[] = + { + #if BASE_FAMILY_PCI == TRUE + &F15PciRegisterTable, + #endif + #if BASE_FAMILY_MSR == TRUE + &F15MsrRegisterTable, + #endif + // the end. + NULL + }; + #endif + + #if USES_REGISTER_TABLES == TRUE + CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15UnknownTableEntryTypeDescriptors[] = + { + {MsrRegister, SetRegisterForMsrEntry}, + {PciRegister, SetRegisterForPciEntry}, + {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry}, + {HtPhyRegister, SetRegisterForHtPhyEntry}, + {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry}, + {DeemphasisRegister, SetRegisterForDeemphasisEntry}, + {ProfileFixup, SetRegisterForPerformanceProfileEntry}, + {HtHostPciRegister, SetRegisterForHtHostEntry}, + {HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry}, + {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid}, + {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry}, + {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry}, + {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry}, + {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry}, + {CompUnitCountsMsr, SetMsrForComputeUnitCountsEntry}, + // End + {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid} + }; + #endif + + + CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15UnknownServices = + { + 0, + #if DISABLE_PSTATE == TRUE + F15DisablePstate, + #else + (PF_CPU_DISABLE_PSTATE) CommonAssert, + #endif + #if TRANSITION_PSTATE == TRUE + F15TransitionPstate, + #else + (PF_CPU_TRANSITION_PSTATE) CommonAssert, + #endif + #if PROC_IDD_MAX == TRUE + (PF_CPU_GET_IDD_MAX) CommonReturnFalse, + #else + (PF_CPU_GET_IDD_MAX) CommonAssert, + #endif + #if GET_TSC_RATE == TRUE + F15GetTscRate, + #else + (PF_CPU_GET_TSC_RATE) CommonAssert, + #endif + #if GET_NB_FREQ == TRUE + (PF_CPU_GET_NB_FREQ) CommonAssert, + #else + (PF_CPU_GET_NB_FREQ) CommonAssert, + #endif + #if GET_NB_FREQ == TRUE + (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert, + #else + (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert, + #endif + #if GET_NB_FREQ == TRUE + (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert, + #else + (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert, + #endif + #if IS_NBCOF_INIT_NEEDED == TRUE + (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnFalse, + #else + (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert, + #endif + #if GET_NB_IDD_MAX == TRUE + (PF_CPU_GET_NB_IDD_MAX) CommonAssert, + #else + (PF_CPU_GET_NB_IDD_MAX) CommonAssert, + #endif + #if AP_INITIAL_LAUNCH == TRUE + F15LaunchApCore, + #else + (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert, + #endif + #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE) + (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonVoid, + #else + (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert, + #endif + #if GET_AP_MAILBOX_FROM_HW == TRUE + (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert, + #else + (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert, + #endif + #if SET_AP_CORE_NUMBER == TRUE + (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert, + #else + (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert, + #endif + #if GET_AP_CORE_NUMBER == TRUE + (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert, + #else + (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert, + #endif + #if TRANSFER_AP_CORE_NUMBER == TRUE + (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert, + #else + (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert, + #endif + #if ID_POSITION_INITIAL_APICID == TRUE + F15CpuAmdCoreIdPositionInInitialApicId, + #else + (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert, + #endif + #if SAVE_FEATURES == TRUE + // F15SaveFeatures, + (PF_CPU_SAVE_FEATURES) CommonVoid, + #else + (PF_CPU_SAVE_FEATURES) CommonAssert, + #endif + #if WRITE_FEATURES == TRUE + // F15WriteFeatures, + (PF_CPU_WRITE_FEATURES) CommonVoid, + #else + (PF_CPU_WRITE_FEATURES) CommonAssert, + #endif + #if SET_WARM_RESET_FLAG == TRUE + F15SetAgesaWarmResetFlag, + #else + (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert, + #endif + #if GET_WARM_RESET_FLAG == TRUE + F15GetAgesaWarmResetFlag, + #else + (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert, + #endif + #if BRAND_STRING1 == TRUE + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if BRAND_STRING2 == TRUE + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_PATCHES == TRUE + GetEmptyArray, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE + GetEmptyArray, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_CACHE_INFO == TRUE + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_SYSTEM_PM_TABLE == TRUE + GetEmptyArray, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_WHEA_INIT == TRUE + GetF15WheaInitData, + #else + (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert, + #endif + #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE + (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess, + #else + (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert, + #endif + #if IS_NB_PSTATE_ENABLED == TRUE + F15IsNbPstateEnabled, + #else + (PF_IS_NB_PSTATE_ENABLED) CommonAssert, + #endif + #if (BASE_FAMILY_HT_PCI == TRUE) + F15NextLinkHasHtPhyFeats, + #else + (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse, + #endif + #if (BASE_FAMILY_HT_PCI == TRUE) + F15SetHtPhyRegister, + #else + (PF_SET_HT_PHY_REGISTER) CommonVoid, + #endif + #if BASE_FAMILY_PCI == TRUE + F15GetNextHtLinkFeatures, + #else + (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert, + #endif + #if USES_REGISTER_TABLES == TRUE + (REGISTER_TABLE **) F15UnknownRegisterTables, + #else + NULL, + #endif + #if USES_REGISTER_TABLES == TRUE + (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15UnknownTableEntryTypeDescriptors, + #else + NULL, + #endif + NULL, + NULL, + InitCacheEnabled, + #if AGESA_ENTRY_INIT_EARLY == TRUE + (PF_GET_EARLY_INIT_TABLE) CommonVoid + #else + (PF_GET_EARLY_INIT_TABLE) CommonVoid + #endif + }; + + #define OPT_F15_UNKNOWN_CPU {(AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , &cpuF15UnknownServices}, + + #else // OPTION_FAMILY15H_UNKNOWN == TRUE + #define OPT_F15_UNKNOWN_CPU + #define OPT_F15_UNKNOWN_ID + #endif // OPTION_FAMILY15H_UNKNOWN == TRUE +#else // defined OPTION_FAMILY15H_UNKNOWN + #define OPT_F15_UNKNOWN_CPU + #define OPT_F15_UNKNOWN_ID +#endif // defined OPTION_FAMILY15H_UNKNOWN + + +// Family 15h maximum base address is 48 bits. Limit BLDCFG to 48 bits, if appropriate. +#if (FAMILY_MMIO_BASE_MASK < 0xFFFF000000000000ull) + #undef FAMILY_MMIO_BASE_MASK + #define FAMILY_MMIO_BASE_MASK (0xFFFF000000000000ull) +#endif + + +#undef OPT_F15_ID_TABLE +#define OPT_F15_ID_TABLE {0x15, {(AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , (AMD_FAMILY_UNKNOWN | AMD_F15_OR_B2 | AMD_F15_TN_A0 | 0x0000000000100000ull ) }, F15LogicalIdTable, (sizeof (F15LogicalIdTable) / sizeof (F15LogicalIdTable[0]))}, + +#undef OPT_F15_TABLE +#define OPT_F15_TABLE OPT_F15_OR_CPU OPT_F15_TN_CPU {0, NULL}, OPT_F15_UNKNOWN_CPU + +#if OPTION_G34_SOCKET_SUPPORT == TRUE + #define F15_G34_BRANDSTRING1 NULL, + #define F15_G34_BRANDSTRING2 NULL, +#else + #define F15_G34_BRANDSTRING1 + #define F15_G34_BRANDSTRING2 +#endif +#if OPTION_C32_SOCKET_SUPPORT == TRUE + #define F15_C32_BRANDSTRING1 NULL, + #define F15_C32_BRANDSTRING2 NULL, +#else + #define F15_C32_BRANDSTRING1 + #define F15_C32_BRANDSTRING2 +#endif +#if OPTION_AM3_SOCKET_SUPPORT == TRUE + #define F15_AM3_BRANDSTRING1 NULL, + #define F15_AM3_BRANDSTRING2 NULL, +#else + #define F15_AM3_BRANDSTRING1 + #define F15_AM3_BRANDSTRING2 +#endif +#if OPTION_FS1_SOCKET_SUPPORT == TRUE + #define F15_FS1_BRANDSTRING1 NULL, + #define F15_FS1_BRANDSTRING2 NULL, +#else + #define F15_FS1_BRANDSTRING1 + #define F15_FS1_BRANDSTRING2 +#endif +#if OPTION_FM2_SOCKET_SUPPORT == TRUE + #define F15_FM2_BRANDSTRING1 NULL, + #define F15_FM2_BRANDSTRING2 NULL, +#else + #define F15_FM2_BRANDSTRING1 + #define F15_FM2_BRANDSTRING2 +#endif +#if OPTION_FP2_SOCKET_SUPPORT == TRUE + #define F15_FP2_BRANDSTRING1 NULL, + #define F15_FP2_BRANDSTRING2 NULL, +#else + #define F15_FP2_BRANDSTRING1 + #define F15_FP2_BRANDSTRING2 +#endif + + +#if BRAND_STRING1 == TRUE + CONST CPU_BRAND_TABLE ROMDATA *F15BrandIdString1Tables[] = + { + F15_G34_BRANDSTRING1 + F15_C32_BRANDSTRING1 + F15_AM3_BRANDSTRING1 + F15_FS1_BRANDSTRING1 + NULL, + F15_FM2_BRANDSTRING1 + NULL, + F15_FP2_BRANDSTRING1 + }; + + CONST UINT8 F15BrandIdString1TableCount = (sizeof (F15BrandIdString1Tables) / sizeof (F15BrandIdString1Tables[0])); +#endif + +#if BRAND_STRING2 == TRUE + CONST CPU_BRAND_TABLE ROMDATA *F15BrandIdString2Tables[] = + { + F15_G34_BRANDSTRING2 + F15_C32_BRANDSTRING2 + F15_AM3_BRANDSTRING2 + F15_FS1_BRANDSTRING2 + NULL, + F15_FM2_BRANDSTRING2 + NULL, + F15_FP2_BRANDSTRING2 + }; + + CONST UINT8 F15BrandIdString2TableCount = (sizeof (F15BrandIdString2Tables) / sizeof (F15BrandIdString2Tables[0])); +#endif + +CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F15LogicalIdTable[] = +{ + OPT_F15_OR_ID + OPT_F15_TN_ID + NULL +}; + +#endif // _OPTION_FAMILY_15H_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionFchInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionFchInstall.h new file mode 100644 index 0000000..ae1e765 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionFchInstall.h @@ -0,0 +1,1024 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of family 15h support + * + * This file generates the defaults tables for family 15h processors. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/********************************************************************************* +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ + +#ifndef _OPTION_FCH_INSTALL_H_ +#define _OPTION_FCH_INSTALL_H_ + +#include "AmdFch.h" + +#ifndef FCH_SUPPORT + #define FCH_SUPPORT FALSE +#endif + + +/* ACPI block register offset definitions */ +#define PM1_STATUS_OFFSET 0x00 +#define PM1_ENABLE_OFFSET 0x02 +#define PM_CONTROL_OFFSET 0x04 +#define PM_TIMER_OFFSET 0x08 +#define CPU_CONTROL_OFFSET 0x10 +#define EVENT_STATUS_OFFSET 0x20 +#define EVENT_ENABLE_OFFSET 0x24 + + +#if FCH_SUPPORT == TRUE + /* + * FCH subfunctions + */ + #ifdef AGESA_ENTRY_INIT_RESET + #if AGESA_ENTRY_INIT_RESET == TRUE + extern FCH_TASK_ENTRY FchInitResetHwAcpiP; + extern FCH_TASK_ENTRY FchInitResetHwAcpi; + extern FCH_TASK_ENTRY FchInitResetAb; + extern FCH_TASK_ENTRY FchInitResetSpi; + extern FCH_TASK_ENTRY FchInitResetGec; + extern FCH_TASK_ENTRY FchInitResetSata; + extern FCH_TASK_ENTRY FchInitResetLpc; + extern FCH_TASK_ENTRY FchInitResetPcib; + extern FCH_TASK_ENTRY FchInitResetPcie; + extern FCH_TASK_ENTRY FchInitResetGpp; + extern FCH_TASK_ENTRY FchInitResetUsb; + extern FCH_TASK_ENTRY FchInitResetEhci; + extern FCH_TASK_ENTRY FchInitResetOhci; + extern FCH_TASK_ENTRY FchInitResetXhci; + extern FCH_TASK_ENTRY FchInitResetImc; + #endif + #endif + + #ifdef AGESA_ENTRY_INIT_ENV + #if AGESA_ENTRY_INIT_ENV == TRUE + extern FCH_TASK_ENTRY FchInitEnvUsbXhci; + extern FCH_TASK_ENTRY FchInitEnvUsbOhci; + extern FCH_TASK_ENTRY FchInitEnvUsbEhci; + extern FCH_TASK_ENTRY FchInitEnvUsb; + extern FCH_TASK_ENTRY FchInitEnvAb; + extern FCH_TASK_ENTRY FchInitEnvGpp; + extern FCH_TASK_ENTRY FchInitEnvGppPhaseII; + extern FCH_TASK_ENTRY FchInitEnvPcie; + extern FCH_TASK_ENTRY FchInitEnvPcib; + extern FCH_TASK_ENTRY FchInitEnvHwAcpiP; + extern FCH_TASK_ENTRY FchInitEnvHwAcpi; + extern FCH_TASK_ENTRY FchInitEnvAbSpecial; + extern FCH_TASK_ENTRY FchInitEnvSpi; + extern FCH_TASK_ENTRY FchInitEnvGec; + extern FCH_TASK_ENTRY FchInitEnvSata; + extern FCH_TASK_ENTRY FchInitEnvIde; + extern FCH_TASK_ENTRY FchInitEnvSd; + extern FCH_TASK_ENTRY FchInitEnvIr; + extern FCH_TASK_ENTRY Fchdef178 ; + extern FCH_TASK_ENTRY FchInitEnvHwm; + extern FCH_TASK_ENTRY FchInitEnvImc; + #endif + #endif + + #ifdef AGESA_ENTRY_INIT_MID + #if AGESA_ENTRY_INIT_MID == TRUE + extern FCH_TASK_ENTRY FchInitMidHwm; + extern FCH_TASK_ENTRY FchInitMidGec; + extern FCH_TASK_ENTRY FchInitMidSata; + extern FCH_TASK_ENTRY FchInitMidIde; + extern FCH_TASK_ENTRY FchInitMidAb; + extern FCH_TASK_ENTRY FchInitMidUsb; + extern FCH_TASK_ENTRY FchInitMidUsbEhci; + extern FCH_TASK_ENTRY FchInitMidUsbOhci; + extern FCH_TASK_ENTRY FchInitMidUsbXhci; + extern FCH_TASK_ENTRY FchInitMidImc; + #endif + #endif + + #ifdef AGESA_ENTRY_INIT_LATE + #if AGESA_ENTRY_INIT_LATE == TRUE + extern FCH_TASK_ENTRY FchInitLateHwAcpi; + extern FCH_TASK_ENTRY FchInitLateSpi; + extern FCH_TASK_ENTRY FchInitLateGec; + extern FCH_TASK_ENTRY FchInitLateSata; + extern FCH_TASK_ENTRY FchInitLateIde; + extern FCH_TASK_ENTRY FchInitLatePcib; + extern FCH_TASK_ENTRY FchInitLateAb; + extern FCH_TASK_ENTRY FchInitLatePcie; + extern FCH_TASK_ENTRY FchInitLateGpp; + extern FCH_TASK_ENTRY FchInitLateUsb; + extern FCH_TASK_ENTRY FchInitLateUsbEhci; + extern FCH_TASK_ENTRY FchInitLateUsbOhci; + extern FCH_TASK_ENTRY FchInitLateUsbXhci; + extern FCH_TASK_ENTRY FchInitLateImc; + extern FCH_TASK_ENTRY FchInitLateHwm; + #endif + #endif + + extern FCH_TASK_ENTRY FchTaskDummy; + extern FCH_TASK_ENTRY FchGppHotplugSmiCallback; + /* FCH Interface entries */ + extern FCH_INIT CommonFchInitStub; + + /* FCH Interface entries */ + #ifdef AGESA_ENTRY_INIT_RESET + #if AGESA_ENTRY_INIT_RESET == TRUE + extern FCH_INIT FchInitReset; + extern FCH_INIT FchResetConstructor; + + #define FP_FCH_INIT_RESET &FchInitReset + #define FP_FCH_INIT_RESET_CONSTRUCT &FchResetConstructor + #else + #define FP_FCH_INIT_RESET &CommonFchInitStub + #define FP_FCH_INIT_RESET_CONSTRUCT &CommonFchInitStub + #endif + #endif + + #ifdef AGESA_ENTRY_INIT_ENV + #if AGESA_ENTRY_INIT_ENV == TRUE + extern FCH_INIT FchInitEnv; + extern FCH_INIT FchEnvConstructor; + + #define FP_FCH_INIT_ENV &FchInitEnv + #define FP_FCH_INIT_ENV_CONSTRUCT &FchEnvConstructor + #else + #define FP_FCH_INIT_ENV &CommonFchInitStub + #define FP_FCH_INIT_ENV_CONSTRUCT &CommonFchInitStub + #endif + #endif + + #ifdef AGESA_ENTRY_INIT_MID + #if AGESA_ENTRY_INIT_MID == TRUE + extern FCH_INIT FchInitMid; + extern FCH_INIT FchMidConstructor; + + #define FP_FCH_INIT_MID &FchInitMid + #define FP_FCH_INIT_MID_CONSTRUCT &FchMidConstructor + #else + #define FP_FCH_INIT_MID &CommonFchInitStub + #define FP_FCH_INIT_MID_CONSTRUCT &CommonFchInitStub + #endif + #endif + + #ifdef AGESA_ENTRY_INIT_LATE + #if AGESA_ENTRY_INIT_LATE == TRUE + extern FCH_INIT FchInitLate; + extern FCH_INIT FchLateConstructor; + + #define FP_FCH_INIT_LATE &FchInitLate + #define FP_FCH_INIT_LATE_CONSTRUCT &FchLateConstructor + #else + #define FP_FCH_INIT_LATE &CommonFchInitStub + #define FP_FCH_INIT_LATE_CONSTRUCT &CommonFchInitStub + #endif + #endif + + /* FCH subcomponent build options */ + #undef FCH_NO_HWACPI_SUPPORT + #undef FCH_NO_AB_SUPPORT + #undef FCH_NO_SPI_SUPPORT + #undef FCH_NO_GEC_SUPPORT + #undef FCH_NO_SATA_SUPPORT + #undef FCH_NO_IDE_SUPPORT + #undef FCH_NO_LPC_SUPPORT + #undef FCH_NO_PCIB_SUPPORT + #undef FCH_NO_PCIE_SUPPORT + #undef FCH_NO_GPP_SUPPORT + #undef FCH_NO_USB_SUPPORT + #undef FCH_NO_EHCI_SUPPORT + #undef FCH_NO_OHCI_SUPPORT + #undef FCH_NO_XHCI_SUPPORT + #undef FCH_NO_IMC_SUPPORT + #undef FCH_NO_SD_SUPPORT + #undef FCH_NO_IR_SUPPORT + #undef FCH_NO_HWM_SUPPORT + + #define FCH_NO_GEC_SUPPORT TRUE + + // Following are determined by silicon characteristics + #if (OPTION_FAMILY15H_TN == TRUE) + //#define FCH_NO_GEC_SUPPORT TRUE + #else + #if (OPTION_FAMILY14H_ON == TRUE) + #define FCH_NO_XHCI_SUPPORT TRUE + #else + #error FCH_SUPPORT: No chip type selected. + #endif + #endif + // + // Installable blocks depending on build switches + // + #ifndef FCH_NO_HWACPI_SUPPORT + #define BLOCK_HWACPI_SIZE sizeof (FCH_ACPI) + #define InstallFchInitResetHwAcpiP &FchInitResetHwAcpiP + #define InstallFchInitResetHwAcpi &FchInitResetHwAcpi + #define InstallFchInitEnvHwAcpiP &FchInitEnvHwAcpiP + #define InstallFchInitEnvHwAcpi &FchInitEnvHwAcpi + #define InstallFchInitMidHwAcpi &FchTaskDummy + #define InstallFchInitLateHwAcpi &FchInitLateHwAcpi + #else + #define BLOCK_HWACPI_SIZE 0 + #define InstallFchInitResetHwAcpiP &FchTaskDummy + #define InstallFchInitResetHwAcpi &FchTaskDummy + #define InstallFchInitEnvHwAcpi &FchTaskDummy + #define InstallFchInitMidHwAcpi &FchTaskDummy + #define InstallFchInitLateHwAcpi &FchTaskDummy + #endif + + #ifndef FCH_NO_AB_SUPPORT + #define BLOCK_AB_SIZE sizeof (FCH_AB) + #define InstallFchInitResetAb &FchInitResetAb + #define InstallFchInitEnvAb &FchInitEnvAb + #define InstallFchInitEnvAbS &FchInitEnvAbSpecial + #define InstallFchInitMidAb &FchInitMidAb + #define InstallFchInitLateAb &FchInitLateAb + #else + #define BLOCK_AB_SIZE 0 + #define InstallFchInitResetAb &FchTaskDummy + #define InstallFchInitEnvAb &FchTaskDummy + #define InstallFchInitEnvAbS &FchTaskDummy + #define InstallFchInitMidAb &FchTaskDummy + #define InstallFchInitLateAb &FchTaskDummy + #endif + + #ifndef FCH_NO_SPI_SUPPORT + #define BLOCK_SPI_SIZE sizeof (FCH_SPI) + #define InstallFchInitResetSpi &FchInitResetSpi + #define InstallFchInitEnvSpi &FchInitEnvSpi + #define InstallFchInitMidSpi &FchTaskDummy + #define InstallFchInitLateSpi &FchInitLateSpi + #else + #define BLOCK_SPI_SIZE 0 + #define InstallFchInitResetSpi &FchTaskDummy + #define InstallFchInitEnvSpi &FchTaskDummy + #define InstallFchInitMidSpi &FchTaskDummy + #define InstallFchInitLateSpi &FchTaskDummy + #endif + + #ifndef FCH_NO_GEC_SUPPORT + #define BLOCK_GEC_SIZE sizeof (FCH_GEC) + #define InstallFchInitResetGec &FchInitResetGec + #define InstallFchInitEnvGec &FchInitEnvGec + #define InstallFchInitMidGec &FchInitMidGec + #define InstallFchInitLateGec &FchInitLateGec + #else + #define BLOCK_GEC_SIZE 0 + #define InstallFchInitResetGec &FchTaskDummy + #define InstallFchInitEnvGec &FchTaskDummy + #define InstallFchInitMidGec &FchTaskDummy + #define InstallFchInitLateGec &FchTaskDummy + #endif + + #ifndef FCH_NO_SATA_SUPPORT + #define BLOCK_SATA_SIZE sizeof (FCH_SATA) + #define InstallFchInitResetSata &FchInitResetSata + #define InstallFchInitEnvSata &FchInitEnvSata + #define InstallFchInitMidSata &FchInitMidSata + #define InstallFchInitLateSata &FchInitLateSata + #else + #define BLOCK_SATA_SIZE 0 + #define InstallFchInitResetSata &FchTaskDummy + #define InstallFchInitEnvSata &FchTaskDummy + #define InstallFchInitMidSata &FchTaskDummy + #define InstallFchInitLateSata &FchTaskDummy + #endif + + #ifndef FCH_NO_IDE_SUPPORT + #define BLOCK_IDE_SIZE sizeof (FCH_IDE) + #define InstallFchInitResetIde &FchTaskDummy + #define InstallFchInitEnvIde &FchInitEnvIde + #define InstallFchInitMidIde &FchInitMidIde + #define InstallFchInitLateIde &FchInitLateIde + #else + #define BLOCK_IDE_SIZE 0 + #define InstallFchInitResetIde &FchTaskDummy + #define InstallFchInitEnvIde &FchTaskDummy + #define InstallFchInitMidIde &FchTaskDummy + #define InstallFchInitLateIde &FchTaskDummy + #endif + + #ifndef FCH_NO_LPC_SUPPORT + #define BLOCK_LPC_SIZE sizeof (FCH_LPC) + #define InstallFchInitResetLpc &FchInitResetLpc + #define InstallFchInitEnvLpc &FchTaskDummy + #define InstallFchInitMidLpc &FchTaskDummy + #define InstallFchInitLateLpc &FchTaskDummy + #else + #define BLOCK_LPC_SIZE 0 + #define InstallFchInitResetLpc &FchTaskDummy + #define InstallFchInitEnvLpc &FchTaskDummy + #define InstallFchInitMidLpc &FchTaskDummy + #define InstallFchInitLateLpc &FchTaskDummy + #endif + + #ifndef FCH_NO_PCIB_SUPPORT + #define BLOCK_PCIB_SIZE sizeof (FCH_PCIB) + #define InstallFchInitResetPcib &FchInitResetPcib + #define InstallFchInitEnvPcib &FchInitEnvPcib + #define InstallFchInitMidPcib &FchTaskDummy + #define InstallFchInitLatePcib &FchInitLatePcib + #else + #define BLOCK_PCIB_SIZE 0 + #define InstallFchInitResetPcib &FchTaskDummy + #define InstallFchInitEnvPcib &FchTaskDummy + #define InstallFchInitMidPcib &FchTaskDummy + #define InstallFchInitLatePcib &FchTaskDummy + #endif + + #ifndef FCH_NO_PCIE_SUPPORT + #define InstallFchInitResetPcie &FchInitResetPcie + #define InstallFchInitEnvPcie &FchInitEnvPcie + #define InstallFchInitMidPcie &FchTaskDummy + #define InstallFchInitLatePcie &FchInitLatePcie + #else + #define InstallFchInitResetPcie &FchTaskDummy + #define InstallFchInitEnvPcie &FchTaskDummy + #define InstallFchInitMidPcie &FchTaskDummy + #define InstallFchInitLatePcie &FchTaskDummy + #endif + + #ifndef FCH_NO_GPP_SUPPORT + #define BLOCK_GPP_SIZE sizeof (FCH_GPP) + #define InstallFchInitResetGpp &FchInitResetGpp + #define InstallFchInitEnvGpp &FchInitEnvGpp + #define InstallFchInitEnvGppPhaseII &FchInitEnvGppPhaseII + #define InstallFchInitMidGpp &FchTaskDummy + #define InstallFchInitLateGpp &FchInitLateGpp + #define InstallHpSmiCallback &FchGppHotplugSmiCallback + #else + #define BLOCK_GPP_SIZE 0 + #define InstallFchInitResetGpp &FchTaskDummy + #define InstallFchInitEnvGpp &FchTaskDummy + #define InstallFchInitEnvGppPhaseII &FchTaskDummy + #define InstallFchInitMidGpp &FchTaskDummy + #define InstallFchInitLateGpp &FchTaskDummy + #define InstallHpSmiCallback &FchTaskDummy + #endif + + #ifndef FCH_NO_USB_SUPPORT + #define BLOCK_USB_SIZE sizeof (FCH_USB) + #define InstallFchInitResetUsb &FchInitResetUsb + #define InstallFchInitEnvUsb &FchInitEnvUsb + #define InstallFchInitMidUsb &FchInitMidUsb + #define InstallFchInitLateUsb &FchInitLateUsb + #else + #define BLOCK_USB_SIZE 0 + #define InstallFchInitResetUsb &FchTaskDummy + #define InstallFchInitEnvUsb &FchTaskDummy + #define InstallFchInitMidUsb &FchTaskDummy + #define InstallFchInitLateUsb &FchTaskDummy + #endif + + #ifndef FCH_NO_EHCI_SUPPORT + #define InstallFchInitResetUsbEhci &FchInitResetEhci + #define InstallFchInitEnvUsbEhci &FchInitEnvUsbEhci + #define InstallFchInitMidUsbEhci &FchInitMidUsbEhci + #define InstallFchInitLateUsbEhci &FchInitLateUsbEhci + #else + #define InstallFchInitResetUsbEhci &FchTaskDummy + #define InstallFchInitEnvUsbEhci &FchTaskDummy + #define InstallFchInitMidUsbEhci &FchTaskDummy + #define InstallFchInitLateUsbEhci &FchTaskDummy + #endif + + #ifndef FCH_NO_OHCI_SUPPORT + #define InstallFchInitResetUsbOhci &FchInitResetOhci + #define InstallFchInitEnvUsbOhci &FchInitEnvUsbOhci + #define InstallFchInitMidUsbOhci &FchInitMidUsbOhci + #define InstallFchInitLateUsbOhci &FchInitLateUsbOhci + #else + #define InstallFchInitResetUsbOhci &FchTaskDummy + #define InstallFchInitEnvUsbOhci &FchTaskDummy + #define InstallFchInitMidUsbOhci &FchTaskDummy + #define InstallFchInitLateUsbOhci &FchTaskDummy + #endif + + #ifndef FCH_NO_XHCI_SUPPORT + #define InstallFchInitResetUsbXhci &FchInitResetXhci + #define InstallFchInitEnvUsbXhci &FchInitEnvUsbXhci + #define InstallFchInitMidUsbXhci &FchInitMidUsbXhci + #define InstallFchInitLateUsbXhci &FchInitLateUsbXhci + #else + #define InstallFchInitResetUsbXhci &FchTaskDummy + #define InstallFchInitEnvUsbXhci &FchTaskDummy + #define InstallFchInitMidUsbXhci &FchTaskDummy + #define InstallFchInitLateUsbXhci &FchTaskDummy + #endif + + #ifndef FCH_NO_IMC_SUPPORT + #define BLOCK_IMC_SIZE sizeof (FCH_IMC) + #define InstallFchInitResetImc &FchInitResetImc + #define InstallFchInitEnvImc &FchInitEnvImc + #define InstallFchInitMidImc &FchInitMidImc + #define InstallFchInitLateImc &FchInitLateImc + #else + #define BLOCK_IMC_SIZE 0 + #define InstallFchInitResetImc &FchTaskDummy + #define InstallFchInitEnvImc &FchTaskDummy + #define InstallFchInitMidImc &FchTaskDummy + #define InstallFchInitLateImc &FchTaskDummy + #endif + + + #ifndef FCH_NO_SD_SUPPORT + #define BLOCK_SD_SIZE sizeof (FCH_SD) + #define InstallFchInitResetSd &FchTaskDummy + #define InstallFchInitEnvSd &FchInitEnvSd + #define InstallFchInitMidSd &FchTaskDummy + #define InstallFchInitLateSd &FchTaskDummy + #else + #define BLOCK_SD_SIZE 0 + #define InstallFchInitResetSd &FchTaskDummy + #define InstallFchInitEnvSd &FchTaskDummy + #define InstallFchInitMidSd &FchTaskDummy + #define InstallFchInitLateSd &FchTaskDummy + #endif + + #ifndef FCH_NO_IR_SUPPORT + #define BLOCK_IR_SIZE sizeof (FCH_IR) + #define InstallFchInitResetIr &FchTaskDummy + #define InstallFchInitEnvIr &FchInitEnvIr + #define InstallFchInitMidIr &FchTaskDummy + #define InstallFchInitLateIr &FchTaskDummy + #else + #define BLOCK_IR_SIZE 0 + #define InstallFchInitResetIr &FchTaskDummy + #define InstallFchInitEnvIr &FchTaskDummy + #define InstallFchInitMidIr &FchTaskDummy + #define InstallFchInitLateIr &FchTaskDummy + #endif + + + #ifndef FCH_NO_HWM_SUPPORT + #define BLOCK_HWM_SIZE sizeof (FCH_HWM) + #define InstallFchInitResetHwm &FchTaskDummy + #define InstallFchInitEnvHwm &FchTaskDummy + #define InstallFchInitMidHwm &FchTaskDummy + #define InstallFchInitLateHwm &FchInitLateHwm + #else + #define InstallFchInitResetHwm &FchTaskDummy + #define InstallFchInitEnvHwm &FchTaskDummy + #define InstallFchInitMidHwm &FchTaskDummy + #define InstallFchInitLateHwm &FchTaskDummy + #endif + + + #define BLOCK_SMBUS_SIZE sizeof (FCH_SMBUS) + #define BLOCK_HPET_SIZE sizeof (FCH_HPET) + #define BLOCK_GCPU_SIZE sizeof (FCH_GCPU) + #define BLOCK_SDB_SIZE sizeof (FCH_SERIALDB) + #define BLOCK_MISC_SIZE sizeof (FCH_MISC) + + + // Optionally declare OEM hooks after each phase + #ifndef FCH_INIT_RESET_HOOK + #define InstallFchInitResetHook FchTaskDummy + #else + #define InstallFchInitResetHook OemFchInitResetHook + #endif + + + // + // Define FCH build time options and configurations + // + #ifdef BLDCFG_SMBUS0_BASE_ADDRESS + #define CFG_SMBUS0_BASE_ADDRESS BLDCFG_SMBUS0_BASE_ADDRESS + #else + #define CFG_SMBUS0_BASE_ADDRESS DFLT_SMBUS0_BASE_ADDRESS + #endif + + #ifdef BLDCFG_SMBUS1_BASE_ADDRESS + #define CFG_SMBUS1_BASE_ADDRESS BLDCFG_SMBUS1_BASE_ADDRESS + #else + #define CFG_SMBUS1_BASE_ADDRESS DFLT_SMBUS1_BASE_ADDRESS + #endif + + #ifdef BLDCFG_SIO_PME_BASE_ADDRESS + #define CFG_SIO_PME_BASE_ADDRESS BLDCFG_SIO_PME_BASE_ADDRESS + #else + #define CFG_SIO_PME_BASE_ADDRESS DFLT_SIO_PME_BASE_ADDRESS + #endif + + #ifdef BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS + #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS + #else + #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS + #endif + #ifdef BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS + #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS + #else + #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS + #endif + #ifdef BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS + #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS + #else + #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS DFLT_ACPI_PM_TMR_BLOCK_ADDRESS + #endif + #ifdef BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS + #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS + #else + #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS + #endif + #ifdef BLDCFG_ACPI_GPE0_BLOCK_ADDRESS + #define CFG_ACPI_GPE0_BLOCK_ADDRESS BLDCFG_ACPI_GPE0_BLOCK_ADDRESS + #else + #define CFG_ACPI_GPE0_BLOCK_ADDRESS DFLT_ACPI_GPE0_BLOCK_ADDRESS + #endif + + + #ifdef BLDCFG_WATCHDOG_TIMER_BASE + #define CFG_WATCHDOG_TIMER_BASE BLDCFG_WATCHDOG_TIMER_BASE + #else + #define CFG_WATCHDOG_TIMER_BASE DFLT_WATCHDOG_TIMER_BASE_ADDRESS + #endif + + #ifdef BLDCFG_ACPI_PMA_BLK_ADDRESS + #define CFG_ACPI_PMA_CNTBLK_ADDRESS BLDCFG_ACPI_PMA_BLK_ADDRESS + #else + #define CFG_ACPI_PMA_CNTBLK_ADDRESS DFLT_ACPI_PMA_CNT_BLK_ADDRESS + #endif + + #ifdef BLDCFG_SMI_CMD_PORT_ADDRESS + #define CFG_SMI_CMD_PORT_ADDRESS BLDCFG_SMI_CMD_PORT_ADDRESS + #else + #define CFG_SMI_CMD_PORT_ADDRESS DFLT_SMI_CMD_PORT + #endif + + #ifdef BLDCFG_ROM_BASE_ADDRESS + #define CFG_SPI_ROM_BASE_ADDRESS BLDCFG_ROM_BASE_ADDRESS + #else + #define CFG_SPI_ROM_BASE_ADDRESS DFLT_SPI_BASE_ADDRESS + #endif + + #ifdef BLDCFG_GEC_SHADOW_ROM_BASE + #define CFG_GEC_SHADOW_ROM_BASE BLDCFG_GEC_SHADOW_ROM_BASE + #else + #define CFG_GEC_SHADOW_ROM_BASE DFLT_GEC_BASE_ADDRESS + #endif + + #ifdef BLDCFG_HPET_BASE_ADDRESS + #define CFG_HPET_BASE_ADDRESS BLDCFG_HPET_BASE_ADDRESS + #else + #define CFG_HPET_BASE_ADDRESS DFLT_HPET_BASE_ADDRESS + #endif + + + #ifdef BLDCFG_SMBUS_SSID + #define CFG_SMBUS_SSID BLDCFG_SMBUS_SSID + #else + #define CFG_SMBUS_SSID DFLT_SMBUS_SSID + #endif + + #ifdef BLDCFG_IDE_SSID + #define CFG_IDE_SSID BLDCFG_IDE_SSID + #else + #define CFG_IDE_SSID DFLT_IDE_SSID + #endif + + #ifdef BLDCFG_SATA_AHCI_SSID + #define CFG_SATA_AHCI_SSID BLDCFG_SATA_AHCI_SSID + #else + #define CFG_SATA_AHCI_SSID DFLT_SATA_AHCI_SSID + #endif + + #ifdef BLDCFG_SATA_IDE_SSID + #define CFG_SATA_IDE_SSID BLDCFG_SATA_IDE_SSID + #else + #define CFG_SATA_IDE_SSID DFLT_SATA_IDE_SSID + #endif + + #ifdef BLDCFG_SATA_RAID5_SSID + #define CFG_SATA_RAID5_SSID BLDCFG_SATA_RAID5_SSID + #else + #define CFG_SATA_RAID5_SSID DFLT_SATA_RAID5_SSID + #endif + + #ifdef BLDCFG_SATA_RAID_SSID + #define CFG_SATA_RAID_SSID BLDCFG_SATA_RAID_SSID + #else + #define CFG_SATA_RAID_SSID DFLT_SATA_RAID_SSID + #endif + + #ifdef BLDCFG_EHCI_SSID + #define CFG_EHCI_SSID BLDCFG_EHCI_SSID + #else + #define CFG_EHCI_SSID DFLT_EHCI_SSID + #endif + + #ifdef BLDCFG_OHCI_SSID + #define CFG_OHCI_SSID BLDCFG_OHCI_SSID + #else + #define CFG_OHCI_SSID DFLT_OHCI_SSID + #endif + + #ifdef BLDCFG_LPC_SSID + #define CFG_LPC_SSID BLDCFG_LPC_SSID + #else + #define CFG_LPC_SSID DFLT_LPC_SSID + #endif + + #ifdef BLDCFG_SD_SSID + #define CFG_SD_SSID BLDCFG_SD_SSID + #else + #define CFG_SD_SSID DFLT_SD_SSID + #endif + + #ifdef BLDCFG_XHCI_SSID + #define CFG_XHCI_SSID BLDCFG_XHCI_SSID + #else + #define CFG_XHCI_SSID DFLT_XHCI_SSID + #endif + + #ifdef BLDCFG_FCH_PORT80_BEHIND_PCIB + #define CFG_FCH_PORT80_BEHIND_PCIB BLDCFG_FCH_PORT80_BEHIND_PCIB + #else + #define CFG_FCH_PORT80_BEHIND_PCIB DFLT_FCH_PORT80_BEHIND_PCIB + #endif + + #ifdef BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP + #define CFG_FCH_ENABLE_ACPI_SLEEP_TRAP BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP + #else + #define CFG_FCH_ENABLE_ACPI_SLEEP_TRAP DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP + #endif + + #ifdef BLDCFG_FCH_GPP_LINK_CONFIG + #define CFG_FCH_GPP_LINK_CONFIG BLDCFG_FCH_GPP_LINK_CONFIG + #else + #define CFG_FCH_GPP_LINK_CONFIG DFLT_FCH_GPP_LINK_CONFIG + #endif + + #ifdef BLDCFG_FCH_GPP_PORT0_PRESENT + #define CFG_FCH_GPP_PORT0_PRESENT BLDCFG_FCH_GPP_PORT0_PRESENT + #else + #define CFG_FCH_GPP_PORT0_PRESENT DFLT_FCH_GPP_PORT0_PRESENT + #endif + + #ifdef BLDCFG_FCH_GPP_PORT1_PRESENT + #define CFG_FCH_GPP_PORT1_PRESENT BLDCFG_FCH_GPP_PORT1_PRESENT + #else + #define CFG_FCH_GPP_PORT1_PRESENT DFLT_FCH_GPP_PORT1_PRESENT + #endif + + #ifdef BLDCFG_FCH_GPP_PORT2_PRESENT + #define CFG_FCH_GPP_PORT2_PRESENT BLDCFG_FCH_GPP_PORT2_PRESENT + #else + #define CFG_FCH_GPP_PORT2_PRESENT DFLT_FCH_GPP_PORT2_PRESENT + #endif + + #ifdef BLDCFG_FCH_GPP_PORT3_PRESENT + #define CFG_FCH_GPP_PORT3_PRESENT BLDCFG_FCH_GPP_PORT3_PRESENT + #else + #define CFG_FCH_GPP_PORT3_PRESENT DFLT_FCH_GPP_PORT3_PRESENT + #endif + + #ifdef BLDCFG_FCH_GPP_PORT0_HOTPLUG + #define CFG_FCH_GPP_PORT0_HOTPLUG BLDCFG_FCH_GPP_PORT0_HOTPLUG + #else + #define CFG_FCH_GPP_PORT0_HOTPLUG DFLT_FCH_GPP_PORT0_HOTPLUG + #endif + + #ifdef BLDCFG_FCH_GPP_PORT1_HOTPLUG + #define CFG_FCH_GPP_PORT1_HOTPLUG BLDCFG_FCH_GPP_PORT1_HOTPLUG + #else + #define CFG_FCH_GPP_PORT1_HOTPLUG DFLT_FCH_GPP_PORT1_HOTPLUG + #endif + + #ifdef BLDCFG_FCH_GPP_PORT2_HOTPLUG + #define CFG_FCH_GPP_PORT2_HOTPLUG BLDCFG_FCH_GPP_PORT2_HOTPLUG + #else + #define CFG_FCH_GPP_PORT2_HOTPLUG DFLT_FCH_GPP_PORT2_HOTPLUG + #endif + + #ifdef BLDCFG_FCH_GPP_PORT3_HOTPLUG + #define CFG_FCH_GPP_PORT3_HOTPLUG BLDCFG_FCH_GPP_PORT3_HOTPLUG + #else + #define CFG_FCH_GPP_PORT3_HOTPLUG DFLT_FCH_GPP_PORT3_HOTPLUG + #endif + + #ifdef BLDCFG_FCH_ESATA_PORT_BITMAP + #define CFG_FCH_ESATA_PORT_BITMAP BLDCFG_FCH_ESATA_PORT_BITMAP + #else + #define CFG_FCH_ESATA_PORT_BITMAP 0 + #endif + + #ifdef BLDCFG_FCH_IR_PIN_CONTROL + #define CFG_FCH_IR_PIN_CONTROL BLDCFG_FCH_IR_PIN_CONTROL + #else + #define CFG_FCH_IR_PIN_CONTROL (BIT5 | BIT1 | BIT0) + #endif + + #ifdef BLDCFG_FCH_SD_CLOCK_CONTROL + #define CFG_FCH_SD_CLOCK_CONTROL BLDCFG_FCH_SD_CLOCK_CONTROL + #else + #define CFG_FCH_SD_CLOCK_CONTROL Sd50MhzTraceCableLengthWithinSixInches + #endif + + #ifdef BLDCFG_FCH_SCI_MAP_LIST + #define CFG_FCH_SCI_MAP_LIST BLDCFG_FCH_SCI_MAP_LIST + #else + #define CFG_FCH_SCI_MAP_LIST NULL + #endif + + #ifdef BLDCFG_FCH_SATA_PHY_LIST + #define CFG_FCH_SATA_PHY_LIST BLDCFG_FCH_SATA_PHY_LIST + #else + #define CFG_FCH_SATA_PHY_LIST NULL + #endif + + #ifdef BLDCFG_FCH_GPIO_CONTROL_LIST + #define CFG_FCH_GPIO_CONTROL_LIST BLDCFG_FCH_GPIO_CONTROL_LIST + #else + #define CFG_FCH_GPIO_CONTROL_LIST NULL + #endif + + + #ifdef AGESA_ENTRY_INIT_RESET + #if AGESA_ENTRY_INIT_RESET == TRUE + // + // Define task list for InitReset phase + // + FCH_TASK_ENTRY ROMDATA *FchInitResetTaskTable[] = { + InstallFchInitResetHwAcpiP, + InstallFchInitResetAb, + InstallFchInitResetSpi, + InstallFchInitResetGec, + InstallFchInitResetHwAcpi, + InstallFchInitResetSata, + InstallFchInitResetLpc, + InstallFchInitResetPcib, + InstallFchInitResetPcie, + InstallFchInitResetGpp, + InstallFchInitResetUsb, + InstallFchInitResetUsbEhci, + InstallFchInitResetUsbOhci, + InstallFchInitResetUsbXhci, + InstallFchInitResetImc, + NULL + }; + #endif + #endif + + #ifdef AGESA_ENTRY_INIT_ENV + #if AGESA_ENTRY_INIT_ENV == TRUE + // + // Define task list for InitEnv phase + // + FCH_TASK_ENTRY ROMDATA *FchInitEnvTaskTable[] = { + InstallFchInitEnvHwAcpiP, + InstallFchInitEnvPcib, + InstallFchInitEnvPcie, + InstallFchInitEnvGpp, + InstallFchInitEnvIr, + InstallFchInitEnvHwAcpi, + InstallFchInitEnvSpi, + InstallFchInitEnvSd, + InstallFchInitEnvImc, + InstallFchInitEnvUsb, + InstallFchInitEnvUsbEhci, + InstallFchInitEnvUsbOhci, + InstallFchInitEnvUsbXhci, + InstallFchInitEnvSata, + InstallFchInitEnvIde, + InstallFchInitEnvGec, + Fchdef178 , + InstallFchInitEnvAb, + InstallFchInitEnvHwm, + InstallFchInitEnvGppPhaseII, + InstallFchInitEnvAbS, + NULL + }; + #endif + #endif + + + #ifdef AGESA_ENTRY_INIT_MID + #if AGESA_ENTRY_INIT_MID == TRUE + // + // Define task list for InitMid phase + // + FCH_TASK_ENTRY ROMDATA *FchInitMidTaskTable[] = { + InstallFchInitMidImc, + InstallFchInitMidUsb, + InstallFchInitMidUsbEhci, + InstallFchInitMidUsbOhci, + InstallFchInitMidUsbXhci, + InstallFchInitMidSata, + InstallFchInitMidIde, + InstallFchInitMidGec, + InstallFchInitMidHwm, + NULL + }; + #endif + #endif + + #ifdef AGESA_ENTRY_INIT_LATE + #if AGESA_ENTRY_INIT_LATE == TRUE + // + // Define task list for InitLate phase + // + FCH_TASK_ENTRY ROMDATA *FchInitLateTaskTable[] = { + InstallFchInitLatePcie, + InstallFchInitLatePcib, + InstallFchInitLateSpi, + InstallFchInitLateUsb, + InstallFchInitLateUsbEhci, + InstallFchInitLateUsbOhci, + InstallFchInitLateUsbXhci, + InstallFchInitLateSata, + InstallFchInitLateIde, + InstallFchInitLateGec, + InstallFchInitLateImc, + InstallFchInitLateHwm, + InstallFchInitLateGpp, + InstallFchInitLateHwAcpi, + NULL + }; + #endif + #endif + + + #ifdef AGESA_ENTRY_INIT_ENV + #if AGESA_ENTRY_INIT_ENV == TRUE + // + // Define task list for S3 resume before PCI phase + // + FCH_TASK_ENTRY ROMDATA *FchInitS3EarlyTaskTable[] = { + InstallFchInitEnvPcie, + InstallFchInitEnvPcib, + InstallFchInitEnvGpp, + InstallFchInitEnvIr, + InstallFchInitEnvHwAcpi, + InstallFchInitEnvSpi, + InstallFchInitEnvSd, + InstallFchInitEnvUsb, + InstallFchInitEnvUsbXhci, + InstallFchInitEnvSata, + InstallFchInitEnvIde, + InstallFchInitEnvGec, + Fchdef178 , + InstallFchInitEnvAb, + InstallFchInitEnvGppPhaseII, + InstallFchInitEnvAbS, + NULL + }; + #endif + #endif + + #ifdef AGESA_ENTRY_INIT_LATE + #if AGESA_ENTRY_INIT_LATE == TRUE + // + // Define task list for S3 resume after PCI phase + // + FCH_TASK_ENTRY ROMDATA *FchInitS3LateTaskTable[] = { + InstallFchInitLatePcie, + InstallFchInitLatePcib, + InstallFchInitLateSpi, + InstallFchInitLateUsb, + InstallFchInitLateUsbEhci, + InstallFchInitLateUsbOhci, + InstallFchInitLateUsbXhci, + InstallFchInitMidSata, + InstallFchInitMidIde, + InstallFchInitMidGec, + InstallFchInitLateSata, + InstallFchInitLateIde, + InstallFchInitLateHwAcpi, + InstallFchInitLateGpp, + InstallFchInitEnvHwm, + InstallFchInitLateGpp, + InstallFchInitLateHwm, + NULL + }; + #endif + #endif + FCH_TASK_ENTRY *FchGppHotplugSmiCallbackPtr = InstallHpSmiCallback; + + +#else // FCH_SUPPORT == FALSE + /* FCH Interface entries */ + extern FCH_INIT CommonFchInitStub; + + #define FP_FCH_INIT_RESET &CommonFchInitStub + #define FP_FCH_INIT_RESET_CONSTRUCT &CommonFchInitStub + #define FP_FCH_INIT_ENV &CommonFchInitStub + #define FP_FCH_INIT_ENV_CONSTRUCT &CommonFchInitStub + #define FP_FCH_INIT_MID &CommonFchInitStub + #define FP_FCH_INIT_MID_CONSTRUCT &CommonFchInitStub + #define FP_FCH_INIT_LATE &CommonFchInitStub + #define FP_FCH_INIT_LATE_CONSTRUCT &CommonFchInitStub + + #define CFG_SMBUS0_BASE_ADDRESS 0 + #define CFG_SMBUS1_BASE_ADDRESS 0 + #define CFG_SIO_PME_BASE_ADDRESS 0 + #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0 + #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0 + #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS 0 + #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0 + #define CFG_ACPI_GPE0_BLOCK_ADDRESS 0 + #define CFG_SPI_ROM_BASE_ADDRESS 0 + #define CFG_WATCHDOG_TIMER_BASE 0 + #define CFG_HPET_BASE_ADDRESS 0 + #define CFG_SMI_CMD_PORT_ADDRESS 0 + #define CFG_ACPI_PMA_CNTBLK_ADDRESS 0 + #define CFG_GEC_SHADOW_ROM_BASE 0 + #define CFG_SMBUS_SSID 0 + #define CFG_IDE_SSID 0 + #define CFG_SATA_AHCI_SSID 0 + #define CFG_SATA_IDE_SSID 0 + #define CFG_SATA_RAID5_SSID 0 + #define CFG_SATA_RAID_SSID 0 + #define CFG_EHCI_SSID 0 + #define CFG_OHCI_SSID 0 + #define CFG_LPC_SSID 0 + #define CFG_SD_SSID 0 + #define CFG_XHCI_SSID 0 + #define CFG_FCH_PORT80_BEHIND_PCIB 0 + #define CFG_FCH_ENABLE_ACPI_SLEEP_TRAP 0 + #define CFG_FCH_GPP_LINK_CONFIG 0 + #define CFG_FCH_GPP_PORT0_PRESENT 0 + #define CFG_FCH_GPP_PORT1_PRESENT 0 + #define CFG_FCH_GPP_PORT2_PRESENT 0 + #define CFG_FCH_GPP_PORT3_PRESENT 0 + #define CFG_FCH_GPP_PORT0_HOTPLUG 0 + #define CFG_FCH_GPP_PORT1_HOTPLUG 0 + #define CFG_FCH_GPP_PORT2_HOTPLUG 0 + #define CFG_FCH_GPP_PORT3_HOTPLUG 0 + + #define CFG_FCH_ESATA_PORT_BITMAP 0 + #define CFG_FCH_IR_PIN_CONTROL 0 + #define CFG_FCH_SD_CLOCK_CONTROL 0 + #define CFG_FCH_SCI_MAP_LIST 0 + #define CFG_FCH_SATA_PHY_LIST 0 + #define CFG_FCH_GPIO_CONTROL_LIST 0 + +#endif + + +CONST BLDOPT_FCH_FUNCTION ROMDATA BldoptFchFunction = { + FP_FCH_INIT_RESET, + FP_FCH_INIT_RESET_CONSTRUCT, + FP_FCH_INIT_ENV, + FP_FCH_INIT_ENV_CONSTRUCT, + FP_FCH_INIT_MID, + FP_FCH_INIT_MID_CONSTRUCT, + FP_FCH_INIT_LATE, + FP_FCH_INIT_LATE_CONSTRUCT, +}; + +#endif // _OPTION_FCH_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionGfxRecovery.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionGfxRecovery.h new file mode 100644 index 0000000..8e7a211 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionGfxRecovery.h @@ -0,0 +1,108 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD GFX Recovery option API. + * + * Contains structures and values used to control the GfxRecovery option code. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: OPTION + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _OPTION_GFX_RECOVERY_H_ +#define _OPTION_GFX_RECOVERY_H_ + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *---------------------------------------------------------------------------------------- + */ + +typedef AGESA_STATUS OPTION_GFX_RECOVERY_FEATURE ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +#define GFX_RECOVERY_STRUCT_VERSION 0x01 + +/// The Option Configuration of GFX Recovery +typedef struct { + UINT16 OptGfxRecoveryVersion; ///< The version number of GFX Recovery + OPTION_GFX_RECOVERY_FEATURE *GfxRecoveryFeature; ///< The Option Feature of GFX Recovery +} OPTION_GFX_RECOVERY_CONFIGURATION; + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ + + +#endif // _OPTION_GFX_RECOVERY_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionGfxRecoveryInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionGfxRecoveryInstall.h new file mode 100644 index 0000000..a13fbba --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionGfxRecoveryInstall.h @@ -0,0 +1,80 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: GfxRecovery + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_GFX_RECOVERY_INSTALL_H_ +#define _OPTION_GFX_RECOVERY_INSTALL_H_ + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ + + +#endif // _OPTION_GFX_RECOVERY_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionGnb.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionGnb.h new file mode 100644 index 0000000..6d20229 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionGnb.h @@ -0,0 +1,149 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD ALIB option API. + * + * Contains structures and values used to control the ALIB option code. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: OPTION + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _OPTION_GNB_H_ +#define _OPTION_GNB_H_ + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *---------------------------------------------------------------------------------------- + */ + + +typedef AGESA_STATUS OPTION_GNB_FEATURE ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef AGESA_STATUS F_ALIB_UPDATE ( + IN OUT VOID *AlibSsdtBuffer, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef VOID* F_ALIB_GET ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// The Option Configuration +typedef struct { + UINT64 Type; ///< Type + OPTION_GNB_FEATURE *GnbFeature; ///< The GNB Feature +} OPTION_GNB_CONFIGURATION; + +/// The Build time options configuration +typedef struct { + BOOLEAN IgfxModeAsPcieEp; ///< Itegrated Gfx mode Pcie EP or Legacy + BOOLEAN LclkDeepSleepEn; ///< Default for LCLK deep sleep + BOOLEAN LclkDpmEn; ///< Default for LCLK DPM + UINT8 GmcPowerGating; ///< Control GMC power gating + BOOLEAN SmuSclkClockGatingEnable; ///< Control SMU SCLK gating + BOOLEAN PcieAspmBlackListEnable; ///< Control Pcie Aspm Black List + BOOLEAN IvrsRelativeAddrNamesSupport; ///< Support for relative address names + BOOLEAN GnbLoadRealFuseTable; ///< Support for fuse table loading + UINT32 CfgGnbLinkReceiverDetectionPooling; ///< Receiver pooling detection time in us. + UINT32 CfgGnbLinkL0Pooling; ///< Pooling for link to get to L0 in us + UINT32 CfgGnbLinkGpioResetAssertionTime; ///< Gpio reset assertion time in us + UINT32 CfgGnbLinkResetToTrainingTime; ///< Time duration between deassert GPIO reset and release training in us + UINT8 CfgGnbTrainingAlgorithm; ///< distribution of training across interface calls + BOOLEAN CfgForceCableSafeOff; ///< Force cable safe off + BOOLEAN CfgOrbClockGatingEnable; ///< Control ORB clock gating + UINT8 CfgPciePowerGatingFlags; ///< Pcie Power gating flags + BOOLEAN CfgIocLclkClockGatingEnable; ///< Control IOC LCLK clock gating + BOOLEAN CfgIocSclkClockGatingEnable; ///< Control IOC SCLK clock gating + BOOLEAN CfgIommuL1ClockGatingEnable; ///< Control IOMMU L1 clock gating + BOOLEAN CfgIommuL2ClockGatingEnable; ///< Control IOMMU L2 clock gating + BOOLEAN CfgAltVddNb; ///< AltVDDNB support + BOOLEAN CfgBapmSupport; ///< BAPM support + BOOLEAN CfgUnusedSimdPowerGatingEnable; ///< Control unused SIMD power gate + BOOLEAN CfgUnusedRbPowerGatingEnable; ///< Control unused SIMD power gate + BOOLEAN CfgNbdpmEnable; ///< NBDPM refers to dynamically reprogramming High and Low NB Pstates under different system usage scenarios + BOOLEAN CfgGmcClockGating; ///< Control GMC clock power gate + BOOLEAN CfgMaxPayloadEnable; ///< Enables configuration of Max_Payload_Size in PCIe device links + BOOLEAN CfgOrbDynWakeEnable; ///< Enables ORB Dynamic wake up + BOOLEAN CfgLoadlineEnable; ///< Enable Loadline Optimization +} GNB_BUILD_OPTIONS; + + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ + +#endif // _OPTION_GNB_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionGnbInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionGnbInstall.h new file mode 100644 index 0000000..dcbaa18 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionGnbInstall.h @@ -0,0 +1,942 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: GNB + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 64464 $ @e $Date: 2012-01-21 11:28:59 -0600 (Sat, 21 Jan 2012) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_GNB_INSTALL_H_ +#define _OPTION_GNB_INSTALL_H_ + +#include "S3SaveState.h" +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ + +//--------------------------------------------------------------------------------------------------- +// Family installation +//--------------------------------------------------------------------------------------------------- + + + +#define GNB_TYPE_TN FALSE +#define GNB_TYPE_LN FALSE +#define GNB_TYPE_ON FALSE + +#if (OPTION_FAMILY14H_ON == TRUE) + #undef GNB_TYPE_ON + #define GNB_TYPE_ON TRUE +#endif + +#if (OPTION_FAMILY12H_LN == TRUE) + #undef GNB_TYPE_LN + #define GNB_TYPE_LN TRUE +#endif + +#if (OPTION_FAMILY15H_TN == TRUE) + #undef GNB_TYPE_TN + #define GNB_TYPE_TN TRUE +#endif + + + +#if (GNB_TYPE_TN == TRUE || GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) +//--------------------------------------------------------------------------------------------------- +// Service installation +//--------------------------------------------------------------------------------------------------- + + #include "Gnb.h" + #include "GnbPcie.h" + #include "GnbGfx.h" + + #define SERVICES_POINTER NULL + #if (GNB_TYPE_TN == TRUE) + #include "GnbInitTNInstall.h" + #endif + GNB_SERVICE *ServiceTable = SERVICES_POINTER; + +//--------------------------------------------------------------------------------------------------- +// BUILD options +//--------------------------------------------------------------------------------------------------- + + #ifndef CFG_IGFX_AS_PCIE_EP + #define CFG_IGFX_AS_PCIE_EP TRUE + #endif + + #ifndef CFG_LCLK_DEEP_SLEEP_EN + #if (GNB_TYPE_TN == TRUE) + #define CFG_LCLK_DEEP_SLEEP_EN FALSE + #else + #define CFG_LCLK_DEEP_SLEEP_EN TRUE + #endif + #endif + + #ifndef CFG_LCLK_DPM_EN + #define CFG_LCLK_DPM_EN TRUE + #endif + + #ifndef CFG_GMC_POWER_GATING + #if (GNB_TYPE_TN == TRUE) + #define CFG_GMC_POWER_GATING GmcPowerGatingWidthStutter + #else + #define CFG_GMC_POWER_GATING GmcPowerGatingWidthStutter + #endif + #endif + + #ifndef CFG_SMU_SCLK_CLOCK_GATING_ENABLE + #if (GNB_TYPE_ON == TRUE || GNB_TYPE_TN == TRUE) + #define CFG_SMU_SCLK_CLOCK_GATING_ENABLE TRUE + #else + #define CFG_SMU_SCLK_CLOCK_GATING_ENABLE FALSE + #endif + #endif + + #ifndef CFG_PCIE_ASPM_BLACK_LIST_ENABLE + #define CFG_PCIE_ASPM_BLACK_LIST_ENABLE TRUE + #endif + + #ifndef CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT + #define CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT FALSE + #endif + + #ifndef CFG_GNB_LOAD_REAL_FUSE + #define CFG_GNB_LOAD_REAL_FUSE TRUE + #endif + + #ifndef CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING + #define CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING (60 * 1000) + #endif + + #ifndef CFG_GNB_PCIE_LINK_L0_POOLING + #define CFG_GNB_PCIE_LINK_L0_POOLING (60 * 1000) + #endif + + #ifndef CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME + #define CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000) + #endif + + #ifndef CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME + #define CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000) + #endif + + #ifdef BLDCFG_PCIE_TRAINING_ALGORITHM + #define CFG_GNB_PCIE_TRAINING_ALGORITHM BLDCFG_PCIE_TRAINING_ALGORITHM + #else + #define CFG_GNB_PCIE_TRAINING_ALGORITHM PcieTrainingStandard + #endif + + #ifndef CFG_GNB_FORCE_CABLESAFE_OFF + #define CFG_GNB_FORCE_CABLESAFE_OFF FALSE + #endif + + #ifndef CFG_ORB_CLOCK_GATING_ENABLE + #define CFG_ORB_CLOCK_GATING_ENABLE TRUE + #endif + + #ifndef CFG_GNB_PCIE_POWERGATING_FLAGS + #define CFG_GNB_PCIE_POWERGATING_FLAGS 0x0 + #endif + + #ifndef CFG_IOC_LCLK_CLOCK_GATING_ENABLE + #if (GNB_TYPE_TN == TRUE) + #define CFG_IOC_LCLK_CLOCK_GATING_ENABLE TRUE + #else + #define CFG_IOC_LCLK_CLOCK_GATING_ENABLE FALSE + #endif + #endif + + #ifndef CFG_IOC_SCLK_CLOCK_GATING_ENABLE + #if (GNB_TYPE_TN == TRUE) + #define CFG_IOC_SCLK_CLOCK_GATING_ENABLE TRUE + #else + #define CFG_IOC_SCLK_CLOCK_GATING_ENABLE FALSE + #endif + #endif + + #ifndef CFG_IOMMU_L1_CLOCK_GATING_ENABLE + #if (GNB_TYPE_TN == TRUE) + #define CFG_IOMMU_L1_CLOCK_GATING_ENABLE TRUE + #else + #define CFG_IOMMU_L1_CLOCK_GATING_ENABLE FALSE + #endif + #endif + + #ifndef CFG_IOMMU_L2_CLOCK_GATING_ENABLE + #if (GNB_TYPE_TN == TRUE) + #define CFG_IOMMU_L2_CLOCK_GATING_ENABLE TRUE + #else + #define CFG_IOMMU_L2_CLOCK_GATING_ENABLE FALSE + #endif + #endif + + #ifndef CFG_GNB_ALTVDDNB_SUPPORT + #define CFG_GNB_ALTVDDNB_SUPPORT TRUE + #endif + + #ifndef CFG_GNB_BAPM_SUPPORT + #if (GNB_TYPE_TN == TRUE) + #define CFG_GNB_BAPM_SUPPORT TRUE + #else + #define CFG_GNB_BAPM_SUPPORT FALSE + #endif + #endif + + #ifndef CFG_UNUSED_SIMD_POWERGATING_ENABLE + #define CFG_UNUSED_SIMD_POWERGATING_ENABLE TRUE + #endif + + #ifndef CFG_UNUSED_RB_POWERGATING_ENABLE + #define CFG_UNUSED_RB_POWERGATING_ENABLE FALSE + #endif + + #ifndef CFG_NBDPM_ENABLE + #define CFG_NBDPM_ENABLE TRUE + #endif + + #ifndef CFG_MAX_PAYLOAD_ENABLE + #define CFG_MAX_PAYLOAD_ENABLE TRUE + #endif + + #ifndef CFG_GMC_CLOCK_GATING + #if (GNB_TYPE_TN == TRUE) + #define CFG_GMC_CLOCK_GATING TRUE + #else + #define CFG_GMC_CLOCK_GATING TRUE + #endif + #endif + + #ifndef CFG_ORB_DYN_WAKE_ENABLE + #if (GNB_TYPE_TN == TRUE) + #define CFG_ORB_DYN_WAKE_ENABLE TRUE + #else + #define CFG_ORB_DYN_WAKE_ENABLE TRUE + #endif + #endif + + #ifndef CFG_LOADLINE_ENABLE + #define CFG_LOADLINE_ENABLE TRUE + #endif + + GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions = { + CFG_IGFX_AS_PCIE_EP, + CFG_LCLK_DEEP_SLEEP_EN, + CFG_LCLK_DPM_EN, + CFG_GMC_POWER_GATING, + CFG_SMU_SCLK_CLOCK_GATING_ENABLE, + CFG_PCIE_ASPM_BLACK_LIST_ENABLE, + CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT, + CFG_GNB_LOAD_REAL_FUSE, + CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING, + CFG_GNB_PCIE_LINK_L0_POOLING, + CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME, + CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME, + CFG_GNB_PCIE_TRAINING_ALGORITHM, + CFG_GNB_FORCE_CABLESAFE_OFF, + CFG_ORB_CLOCK_GATING_ENABLE, + CFG_GNB_PCIE_POWERGATING_FLAGS, + CFG_IOC_LCLK_CLOCK_GATING_ENABLE, + CFG_IOC_SCLK_CLOCK_GATING_ENABLE, + CFG_IOMMU_L1_CLOCK_GATING_ENABLE, + CFG_IOMMU_L2_CLOCK_GATING_ENABLE, + CFG_GNB_ALTVDDNB_SUPPORT, + CFG_GNB_BAPM_SUPPORT, + CFG_UNUSED_SIMD_POWERGATING_ENABLE, + CFG_UNUSED_RB_POWERGATING_ENABLE, + CFG_NBDPM_ENABLE, + CFG_GMC_CLOCK_GATING, + CFG_MAX_PAYLOAD_ENABLE, + CFG_ORB_DYN_WAKE_ENABLE, + CFG_LOADLINE_ENABLE + }; + + //--------------------------------------------------------------------------------------------------- + // Module entries + //--------------------------------------------------------------------------------------------------- + + #if (AGESA_ENTRY_INIT_EARLY == TRUE) + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_NB_EARLY_INIT + #define OPTION_NB_EARLY_INIT TRUE + #endif + #if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) + OPTION_GNB_FEATURE NbInitAtEarly; + #define OPTION_NBINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , NbInitAtEarly}, + #else + #define OPTION_NBINITATEARLY_ENTRY + #endif + #if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_TN == TRUE) + OPTION_GNB_FEATURE GnbEarlyInterfaceTN; + #define OPTION_GNBEARLYINTERFACETN_ENTRY {AMD_FAMILY_TN, GnbEarlyInterfaceTN}, + #else + #define OPTION_GNBEARLYINTERFACETN_ENTRY + #endif + //--------------------------------------------------------------------------------------------------- + // SMU init + #ifndef OPTION_SMU + #define OPTION_SMU TRUE + #endif + #if (OPTION_SMU == TRUE) && (GNB_TYPE_LN == TRUE) + OPTION_GNB_FEATURE F12NbSmuInitFeature; + #define OPTION_F12NBSMUINITFEATURE_ENTRY {AMD_FAMILY_LN, F12NbSmuInitFeature}, + #else + #define OPTION_F12NBSMUINITFEATURE_ENTRY + #endif + #if (OPTION_SMU == TRUE) && (GNB_TYPE_ON == TRUE) + OPTION_GNB_FEATURE F14NbSmuInitFeature; + #define OPTION_F14NBSMUINITFEATURE_ENTRY {AMD_FAMILY_ON, F14NbSmuInitFeature}, + #else + #define OPTION_F14NBSMUINITFEATURE_ENTRY + #endif + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_PCIE_CONFIG_MAP + #define OPTION_PCIE_CONFIG_MAP TRUE + #endif + #if (OPTION_PCIE_CONFIG_MAP == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE || GNB_TYPE_TN == TRUE ) + OPTION_GNB_FEATURE PcieConfigurationMap; + #define OPTION_PCIECONFIGURATIONMAP_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON | AMD_FAMILY_TN , PcieConfigurationMap}, + #else + #define OPTION_PCIECONFIGURATIONMAP_ENTRY + #endif + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_PCIE_EARLY_INIT + #define OPTION_PCIE_EARLY_INIT TRUE + #endif + #if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) + OPTION_GNB_FEATURE PcieInitAtEarly; + #define OPTION_PCIEINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , PcieInitAtEarly}, + #else + #define OPTION_PCIEINITATEARLY_ENTRY + #endif + #if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_TN == TRUE) + OPTION_GNB_FEATURE PcieEarlyInterfaceTN; + #define OPTION_PCIEEARLYINTERFACETN_ENTRY {AMD_FAMILY_TN, PcieEarlyInterfaceTN}, + #else + #define OPTION_PCIEEARLYINTERFACETN_ENTRY + #endif + + //--------------------------------------------------------------------------------------------------- + OPTION_GNB_CONFIGURATION GnbEarlyFeatureTable[] = { + OPTION_NBINITATEARLY_ENTRY + OPTION_GNBEARLYINTERFACETN_ENTRY + OPTION_F12NBSMUINITFEATURE_ENTRY + OPTION_F14NBSMUINITFEATURE_ENTRY + OPTION_PCIECONFIGURATIONMAP_ENTRY + OPTION_PCIEINITATEARLY_ENTRY + OPTION_PCIEEARLYINTERFACETN_ENTRY + {0, NULL} + }; + + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_PCIE_CONFIG_INIT + #define OPTION_PCIE_CONFIG_INIT TRUE + #endif + #if (OPTION_PCIE_CONFIG_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE || GNB_TYPE_TN == TRUE ) + OPTION_GNB_FEATURE PcieConfigurationInit; + #define OPTION_PCIECONFIGURATIONINIT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON | AMD_FAMILY_TN , PcieConfigurationInit}, + #else + #define OPTION_PCIECONFIGURATIONINIT_ENTRY + #endif + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_NB_EARLIER_INIT + #define OPTION_NB_EARLIER_INIT TRUE + #endif + #if (OPTION_NB_EARLIER_INIT == TRUE) && (GNB_TYPE_TN == TRUE) + OPTION_GNB_FEATURE GnbEarlierInterfaceTN; + #define OPTION_GNBEARLIERINTERFACETN_ENTRY {AMD_FAMILY_TN, GnbEarlierInterfaceTN}, + #else + #define OPTION_GNBEARLIERINTERFACETN_ENTRY + #endif + + OPTION_GNB_CONFIGURATION GnbEarlierFeatureTable[] = { + OPTION_PCIECONFIGURATIONINIT_ENTRY + OPTION_GNBEARLIERINTERFACETN_ENTRY + {0, NULL} + }; + #endif + + #if (AGESA_ENTRY_INIT_POST == TRUE) + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_GFX_CONFIG_POST_INIT + #define OPTION_GFX_CONFIG_POST_INIT TRUE + #endif + #if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE || GNB_TYPE_TN == TRUE ) + OPTION_GNB_FEATURE GfxConfigPostInterface; + #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON | AMD_FAMILY_TN , GfxConfigPostInterface}, + #else + #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY + #endif + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_GFX_POST_INIT + #define OPTION_GFX_POST_INIT TRUE + #endif + #if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) + OPTION_GNB_FEATURE GfxInitAtPost; + #define OPTION_GFXINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , GfxInitAtPost}, + #else + #define OPTION_GFXINITATPOST_ENTRY + #endif + #if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE) + OPTION_GNB_FEATURE GfxPostInterfaceTN; + #define OPTION_GFXPOSTINTERFACETN_ENTRY {AMD_FAMILY_TN, GfxPostInterfaceTN}, + #else + #define OPTION_GFXPOSTINTERFACETN_ENTRY + #endif + + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_NB_POST_INIT + #define OPTION_NB_POST_INIT TRUE + #endif + #if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) + OPTION_GNB_FEATURE NbInitAtPost; + #define OPTION_NBINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , NbInitAtPost}, + #else + #define OPTION_NBINITATPOST_ENTRY + #endif + #if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE) + OPTION_GNB_FEATURE GnbPostInterfaceTN; + #define OPTION_GNBPOSTINTERFACETN_ENTRY {AMD_FAMILY_TN, GnbPostInterfaceTN}, + #else + #define OPTION_GNBPOSTINTERFACETN_ENTRY + #endif + + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_PCIE_POST_EALRY_INIT + #define OPTION_PCIE_POST_EALRY_INIT TRUE + #endif + #if (OPTION_PCIE_POST_EALRY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) + OPTION_GNB_FEATURE PcieInitAtPostEarly; + #define OPTION_PCIEINITATPOSTEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , PcieInitAtPostEarly}, + #else + #define OPTION_PCIEINITATPOSTEARLY_ENTRY + #endif + #if (OPTION_PCIE_POST_EALRY_INIT == TRUE) && (GNB_TYPE_TN == TRUE) + OPTION_GNB_FEATURE PciePostEarlyInterfaceTN; + #define OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY {AMD_FAMILY_TN, PciePostEarlyInterfaceTN}, + #else + #define OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY + #endif + + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_PCIE_POST_INIT + #define OPTION_PCIE_POST_INIT TRUE + #endif + #if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) + OPTION_GNB_FEATURE PcieInitAtPost; + #define OPTION_PCIEINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , PcieInitAtPost}, + #else + #define OPTION_PCIEINITATPOST_ENTRY + #endif + #if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE) + OPTION_GNB_FEATURE PciePostInterfaceTN; + #define OPTION_PCIEPOSTINTERFACETN_ENTRY {AMD_FAMILY_TN, PciePostInterfaceTN}, + #else + #define OPTION_PCIEPOSTINTERFACETN_ENTRY + #endif + + //--------------------------------------------------------------------------------------------------- + OPTION_GNB_CONFIGURATION GnbPostFeatureTable[] = { + OPTION_PCIEINITATPOSTEARLY_ENTRY + OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY + OPTION_GFXCONFIGPOSTINTERFACE_ENTRY + OPTION_GFXINITATPOST_ENTRY + OPTION_GFXPOSTINTERFACETN_ENTRY + {0, NULL} + }; + + OPTION_GNB_CONFIGURATION GnbPostAfterDramFeatureTable[] = { + OPTION_NBINITATPOST_ENTRY + OPTION_GNBPOSTINTERFACETN_ENTRY + OPTION_PCIEINITATPOST_ENTRY + OPTION_PCIEPOSTINTERFACETN_ENTRY + {0, NULL} + }; + #endif + + #if (AGESA_ENTRY_INIT_ENV == TRUE) + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_FUSE_TABLE_INIT + #define OPTION_FUSE_TABLE_INIT TRUE + #endif + #if (OPTION_FUSE_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) + OPTION_GNB_FEATURE NbFuseTableFeature; + #define OPTION_NBFUSETABLEFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , NbFuseTableFeature}, + #else + #define OPTION_NBFUSETABLEFEATURE_ENTRY + #endif + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_NB_ENV_INIT + #define OPTION_NB_ENV_INIT TRUE + #endif + #if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) + OPTION_GNB_FEATURE NbInitAtEnv; + #define OPTION_NBINITATENVT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , NbInitAtEnv}, + #else + #define OPTION_NBINITATENVT_ENTRY + #endif + #if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_TN == TRUE) + OPTION_GNB_FEATURE GnbEnvInterfaceTN; + #define OPTION_GNBENVINTERFACETN_ENTRY {AMD_FAMILY_TN, GnbEnvInterfaceTN}, + #else + #define OPTION_GNBENVINTERFACETN_ENTRY + #endif + + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_GFX_CONFIG_ENV_INIT + #define OPTION_GFX_CONFIG_ENV_INIT TRUE + #endif + #if (OPTION_GFX_CONFIG_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE || GNB_TYPE_TN == TRUE ) + OPTION_GNB_FEATURE GfxConfigEnvInterface; + #define OPTION_GFXCONFIGENVINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON | AMD_FAMILY_TN, GfxConfigEnvInterface}, + #else + #define OPTION_GFXCONFIGENVINTERFACE_ENTRY + #endif + + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_GFX_ENV_INIT + #define OPTION_GFX_ENV_INIT TRUE + #endif + #if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) + OPTION_GNB_FEATURE GfxInitAtEnvPost; + #define OPTION_GFXINITATENVPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , GfxInitAtEnvPost}, + #else + #define OPTION_GFXINITATENVPOST_ENTRY + #endif + #if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_TN == TRUE) + OPTION_GNB_FEATURE GfxEnvInterfaceTN; + #define OPTION_GFXENVINTERFACETN_ENTRY {AMD_FAMILY_TN, GfxEnvInterfaceTN}, + #else + #define OPTION_GFXENVINTERFACETN_ENTRY + #endif + + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_POWER_GATE + #define OPTION_POWER_GATE TRUE + #endif + #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE) + OPTION_GNB_FEATURE F12NbPowerGateFeature; + #define OPTION_F12NBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_LN, F12NbPowerGateFeature}, + #else + #define OPTION_F12NBPOWERGATEFEATURE_ENTRY + #endif + #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_ON == TRUE) + OPTION_GNB_FEATURE F14NbPowerGateFeature; + #define OPTION_F14NBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_ON, F14NbPowerGateFeature}, + #else + #define OPTION_F14NBPOWERGATEFEATURE_ENTRY + #endif + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_PCIE_ENV_INIT + #define OPTION_PCIE_ENV_INIT TRUE + #endif + #if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) + OPTION_GNB_FEATURE PcieInitAtEnv; + #define OPTION_PCIEINITATENV_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , PcieInitAtEnv}, + #else + #define OPTION_PCIEINITATENV_ENTRY + #endif + #if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_TN == TRUE) + OPTION_GNB_FEATURE PcieEnvInterfaceTN; + #define OPTION_PCIEENVINTERFACETN_ENTRY {AMD_FAMILY_TN, PcieEnvInterfaceTN}, + #else + #define OPTION_PCIEENVINTERFACETN_ENTRY + #endif + + //--------------------------------------------------------------------------------------------------- + + OPTION_GNB_CONFIGURATION GnbEnvFeatureTable[] = { + OPTION_NBFUSETABLEFEATURE_ENTRY + OPTION_NBINITATENVT_ENTRY + OPTION_GNBENVINTERFACETN_ENTRY + OPTION_PCIEINITATENV_ENTRY + OPTION_PCIEENVINTERFACETN_ENTRY + OPTION_GFXCONFIGENVINTERFACE_ENTRY + OPTION_GFXINITATENVPOST_ENTRY + OPTION_GFXENVINTERFACETN_ENTRY + OPTION_F12NBPOWERGATEFEATURE_ENTRY + OPTION_F14NBPOWERGATEFEATURE_ENTRY + {0, NULL} + }; + #endif + + #if (AGESA_ENTRY_INIT_MID == TRUE) + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_GNB_CABLESAFE + #define OPTION_GNB_CABLESAFE TRUE + #endif + #if (OPTION_GNB_CABLESAFE == TRUE) && (GNB_TYPE_LN == TRUE) + OPTION_GNB_FEATURE GnbCableSafeEntry; + #define OPTION_GNBCABLESAFEENTRY_ENTRY {AMD_FAMILY_LN, GnbCableSafeEntry}, + #else + #define OPTION_GNBCABLESAFEENTRY_ENTRY + #endif + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_NB_LCLK_NCLK_RATIO + #define OPTION_NB_LCLK_NCLK_RATIO TRUE + #endif + #if (OPTION_NB_LCLK_NCLK_RATIO == TRUE) && (GNB_TYPE_ON == TRUE) + OPTION_GNB_FEATURE F14NbLclkNclkRatioFeature; + #define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY {AMD_FAMILY_ON, F14NbLclkNclkRatioFeature}, + #else + #define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY + #endif + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_NB_LCLK_DPM_INIT + #define OPTION_NB_LCLK_DPM_INIT TRUE + #endif + #if (OPTION_NB_LCLK_DPM_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) + OPTION_GNB_FEATURE NbLclkDpmFeature; + #define OPTION_NBLCLKDPMFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , NbLclkDpmFeature}, + #else + #define OPTION_NBLCLKDPMFEATURE_ENTRY + #endif + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_PCIE_POWER_GATE + #define OPTION_PCIE_POWER_GATE TRUE + #endif + #if (OPTION_PCIE_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE) + OPTION_GNB_FEATURE PciePowerGateFeature; + #define OPTION_PCIEPOWERGATEFEATURE_ENTRY {AMD_FAMILY_LN, PciePowerGateFeature}, + #else + #define OPTION_PCIEPOWERGATEFEATURE_ENTRY + #endif + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_GFX_MID_INIT + #define OPTION_GFX_MID_INIT TRUE + #endif + #if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) + OPTION_GNB_FEATURE GfxInitAtMidPost; + #define OPTION_GFXINITATMIDPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , GfxInitAtMidPost}, + #else + #define OPTION_GFXINITATMIDPOST_ENTRY + #endif + #if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_TN == TRUE) + OPTION_GNB_FEATURE GfxMidInterfaceTN; + #define OPTION_GFXMIDINTERFACETN_ENTRY {AMD_FAMILY_TN, GfxMidInterfaceTN}, + #else + #define OPTION_GFXMIDINTERFACETN_ENTRY + #endif + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_GFX_INTEGRATED_TABLE_INIT + #define OPTION_GFX_INTEGRATED_TABLE_INIT TRUE + #endif + #if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) + OPTION_GNB_FEATURE GfxIntegratedInfoTableEntry; + #define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , GfxIntegratedInfoTableEntry}, + #else + #define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY + #endif + #if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_TN == TRUE) + OPTION_GNB_FEATURE GfxIntInfoTableInterfaceTN; + #define OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY {AMD_FAMILY_TN, GfxIntInfoTableInterfaceTN}, + #else + #define OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY + #endif + + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_PCIe_MID_INIT + #define OPTION_PCIe_MID_INIT TRUE + #endif + #if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) + OPTION_GNB_FEATURE PcieInitAtMid; + #define OPTION_PCIEINITATMID_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , PcieInitAtMid}, + #else + #define OPTION_PCIEINITATMID_ENTRY + #endif + #if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_TN == TRUE) + OPTION_GNB_FEATURE PcieMidInterfaceTN; + #define OPTION_PCIEMIDINTERFACETN_ENTRY {AMD_FAMILY_TN, PcieMidInterfaceTN}, + #else + #define OPTION_PCIEMIDINTERFACETN_ENTRY + #endif + + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_NB_MID_INIT + #define OPTION_NB_MID_INIT TRUE + #endif + #if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) + OPTION_GNB_FEATURE NbInitAtLatePost; + #define OPTION_NBINITATLATEPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON , NbInitAtLatePost}, + #else + #define OPTION_NBINITATLATEPOST_ENTRY + #endif + #if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_TN == TRUE) + OPTION_GNB_FEATURE GnbMidInterfaceTN; + #define OPTION_GNBMIDINTERFACETN_ENTRY {AMD_FAMILY_TN, GnbMidInterfaceTN}, + #else + #define OPTION_GNBMIDINTERFACETN_ENTRY + #endif + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_GFX_CONFIG_POST_INIT + #define OPTION_GFX_CONFIG_POST_INIT TRUE + #endif + #if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_TN == TRUE || GNB_TYPE_ON == TRUE) + OPTION_GNB_FEATURE GfxConfigMidInterface; + #define OPTION_GFXCONFIGMIDINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_TN | GNB_TYPE_ON, GfxConfigMidInterface}, + #else + #define OPTION_GFXCONFIGMIDINTERFACE_ENTRY + #endif + //--------------------------------------------------------------------------------------------------- + + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_PCIE_CLK_PM_INTERFACE + #define OPTION_PCIE_CLK_PM_INTERFACE FALSE + #if (GNB_TYPE_ON == TRUE ) + #undef OPTION_PCIE_CLK_PM_INTERFACE + #define OPTION_PCIE_CLK_PM_INTERFACE TRUE + #endif + #if (GNB_TYPE_TN == TRUE && (OPTION_FS1_SOCKET_SUPPORT == TRUE || OPTION_FP1_SOCKET_SUPPORT == TRUE)) + #undef OPTION_PCIE_CLK_PM_INTERFACE + #define OPTION_PCIE_CLK_PM_INTERFACE TRUE + #endif + #endif + + #if (OPTION_PCIE_CLK_PM_INTERFACE == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_ON == TRUE ) + OPTION_GNB_FEATURE PcieClkPmInterface; + #define OPTION_PCIECLKPMINTERFACE_ENTRY {AMD_FAMILY_TN | AMD_FAMILY_ON, PcieClkPmInterface}, + #else + #define OPTION_PCIECLKPMINTERFACE_ENTRY + #endif + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_PCIE_ASPM_INTERFACE + #define OPTION_PCIE_ASPM_INTERFACE TRUE + #endif + #if (OPTION_PCIE_ASPM_INTERFACE == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE || GNB_TYPE_TN == TRUE ) + OPTION_GNB_FEATURE PcieAspmInterface; + #define OPTION_PCIEASPMINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON | AMD_FAMILY_TN , PcieAspmInterface}, + #else + #define OPTION_PCIEASPMINTERFACE_ENTRY + #endif + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_GNB_IOAPIC_INTERFACE + #define OPTION_GNB_IOAPIC_INTERFACE TRUE + #endif + //--------------------------------------------------------------------------------------------------- + OPTION_GNB_CONFIGURATION GnbMidFeatureTable[] = { + OPTION_GFXCONFIGMIDINTERFACE_ENTRY + OPTION_GFXINITATMIDPOST_ENTRY + OPTION_GFXMIDINTERFACETN_ENTRY + OPTION_GFXINTEGRATEDINFOTABLE_ENTRY + OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY + OPTION_GNBCABLESAFEENTRY_ENTRY + OPTION_PCIEINITATMID_ENTRY + OPTION_PCIEMIDINTERFACETN_ENTRY + OPTION_NBINITATLATEPOST_ENTRY + OPTION_GNBMIDINTERFACETN_ENTRY + OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY + OPTION_NBLCLKDPMFEATURE_ENTRY + OPTION_PCIEPOWERGATEFEATURE_ENTRY + OPTION_PCIECLKPMINTERFACE_ENTRY + OPTION_PCIEASPMINTERFACE_ENTRY + {0, NULL} + }; + #endif + + #if (AGESA_ENTRY_INIT_LATE == TRUE) + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_ALIB + #define OPTION_ALIB FALSE + #endif + #if (OPTION_ALIB == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE || GNB_TYPE_TN == TRUE) + extern F_ALIB_UPDATE PcieAlibUpdatePcieMmioInfo; + #if (GNB_TYPE_LN == TRUE) + #if (OPTION_FM1_SOCKET_SUPPORT == TRUE) + extern F_ALIB_GET PcieAlibGetBaseTableLNFM1; + F_ALIB_GET *AlibGetBaseTable = PcieAlibGetBaseTableLNFM1; + #define ALIB_CALL_TABLE PcieAlibUpdatePcieMmioInfo + #else + extern F_ALIB_GET PcieAlibGetBaseTableLNFS1; + F_ALIB_GET *AlibGetBaseTable = PcieAlibGetBaseTableLNFS1; + extern F_ALIB_UPDATE PcieAlibUpdateVoltageInfo; + extern F_ALIB_UPDATE PcieAlibUpdatePcieInfo; + extern F_ALIB_UPDATE PcieAlibBuildAcpiTableLNFS1; + #define ALIB_CALL_TABLE PcieAlibUpdatePcieMmioInfo, \ + PcieAlibUpdateVoltageInfo, \ + PcieAlibUpdatePcieInfo, \ + PcieAlibBuildAcpiTableLNFS1 + #endif + #elif (GNB_TYPE_TN == TRUE) + #if (OPTION_FM2_SOCKET_SUPPORT == TRUE) + extern F_ALIB_GET PcieAlibGetBaseTableTNFM2; + F_ALIB_GET *AlibGetBaseTable = PcieAlibGetBaseTableTNFM2; + #define ALIB_CALL_TABLE PcieAlibUpdatePcieMmioInfo + #else + extern F_ALIB_GET PcieAlibGetBaseTableTNFS1; + F_ALIB_GET *AlibGetBaseTable = PcieAlibGetBaseTableTNFS1; + extern F_ALIB_UPDATE PcieAlibUpdateVoltageInfo; + extern F_ALIB_UPDATE PcieAlibUpdatePcieInfo; + extern F_ALIB_UPDATE PcieAlibBuildAcpiTableLNFS2; + #define ALIB_CALL_TABLE PcieAlibUpdatePcieMmioInfo, \ + PcieAlibUpdateVoltageInfo, \ + PcieAlibUpdatePcieInfo + + #endif + #else + extern F_ALIB_GET PcieAlibGetBaseTable; + F_ALIB_GET *AlibGetBaseTable = PcieAlibGetBaseTable; + extern F_ALIB_UPDATE PcieAlibUpdateVoltageInfo; + extern F_ALIB_UPDATE PcieAlibUpdatePcieInfo; + extern F_ALIB_UPDATE PcieFmAlibBuildAcpiTable; + #define ALIB_CALL_TABLE PcieAlibUpdatePcieMmioInfo, \ + PcieAlibUpdateVoltageInfo, \ + PcieAlibUpdatePcieInfo, \ + PcieFmAlibBuildAcpiTable + #endif + F_ALIB_UPDATE* AlibDispatchTable [] = { + ALIB_CALL_TABLE, + NULL + }; + OPTION_GNB_FEATURE PcieAlibFeature; + #define OPTION_PCIEALIBFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON | AMD_FAMILY_TN, PcieAlibFeature}, + #else + F_ALIB_GET *AlibGetBaseTable = NULL; + F_ALIB_UPDATE* AlibDispatchTable [] = { + NULL + }; + #define OPTION_PCIEALIBFEATURE_ENTRY + #endif + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_IOMMU_ACPI_IVRS + #if (CFG_IOMMU_SUPPORT == TRUE) + #define OPTION_IOMMU_ACPI_IVRS TRUE + #else + #define OPTION_IOMMU_ACPI_IVRS FALSE + #endif + #endif + #if (OPTION_IOMMU_ACPI_IVRS == TRUE) && (GNB_TYPE_TN == TRUE ) + OPTION_GNB_FEATURE GnbIommuIvrsTable; + #define OPTIONIOMMUACPIIVRSLATE_ENTRY {AMD_FAMILY_TN, GnbIommuIvrsTable}, + #else + #define OPTIONIOMMUACPIIVRSLATE_ENTRY + #endif + #if (CFG_IOMMU_SUPPORT == TRUE) && (GNB_TYPE_TN == TRUE ) + OPTION_GNB_FEATURE GnbIommuScratchMemoryRangeInterface; + #define OPTIONIOMMUSCRATCHMEMORYLATE_ENTRY {AMD_FAMILY_TN , GnbIommuScratchMemoryRangeInterface}, + #else + #define OPTIONIOMMUSCRATCHMEMORYLATE_ENTRY + #endif + //--------------------------------------------------------------------------------------------------- + OPTION_GNB_CONFIGURATION GnbLateFeatureTable[] = { + OPTION_PCIEALIBFEATURE_ENTRY + OPTIONIOMMUSCRATCHMEMORYLATE_ENTRY + OPTIONIOMMUACPIIVRSLATE_ENTRY + {0, NULL} + }; + #endif + + #if (AGESA_ENTRY_INIT_S3SAVE == TRUE) + //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_GFX_INIT_SVIEW + #define OPTION_GFX_INIT_SVIEW TRUE + #endif + #if (OPTION_GFX_INIT_SVIEW == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_TN == TRUE || GNB_TYPE_ON == TRUE) + OPTION_GNB_FEATURE GfxInitSview; + #define OPTION_GFXINITSVIEW_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_TN, GfxInitSview}, + #else + #define OPTION_GFXINITSVIEW_ENTRY + #endif + + OPTION_GNB_CONFIGURATION GnbS3SaveFeatureTable[] = { + OPTION_GFXINITSVIEW_ENTRY + {0, NULL} + }; + #endif + #if (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE ) + S3_DISPATCH_FUNCTION NbSmuServiceRequestS3Script; + S3_DISPATCH_FUNCTION PcieLateRestoreS3Script; + S3_DISPATCH_FUNCTION NbSmuIndirectWriteS3Script; + #define GNB_S3_DISPATCH_FUNCTION_TABLE \ + {NbSmuIndirectWriteS3Script_ID, NbSmuIndirectWriteS3Script}, \ + {NbSmuServiceRequestS3Script_ID, NbSmuServiceRequestS3Script}, \ + {PcieLateRestoreS3Script_ID, PcieLateRestoreS3Script}, + #endif + + + #if (GNB_TYPE_TN == TRUE ) + S3_DISPATCH_FUNCTION GnbSmuServiceRequestV4S3Script; + S3_DISPATCH_FUNCTION GnbLibStallS3Script; + #define PCIELATERESTORETN + #define GFXSCLKRESTORETN + #if (GNB_TYPE_TN == TRUE) + S3_DISPATCH_FUNCTION PcieLateRestoreInitTNS3Script; + S3_DISPATCH_FUNCTION GfxRequestSclkTNS3Script; + #undef PCIELATERESTORETN + #define PCIELATERESTORETN {PcieLateRestoreTNS3Script_ID, PcieLateRestoreInitTNS3Script}, + #undef GFXSCLKRESTORETN + #define GFXSCLKRESTORETN {GfxRequestSclkTNS3Script_ID, GfxRequestSclkTNS3Script }, + #endif + #define GNB_S3_DISPATCH_FUNCTION_TABLE \ + {GnbSmuServiceRequestV4S3Script_ID, GnbSmuServiceRequestV4S3Script}, \ + PCIELATERESTORETN \ + GFXSCLKRESTORETN \ + {GnbLibStallS3Script_ID, GnbLibStallS3Script}, + /*these three line should be 1261-1263*/ + + + #endif + +#endif +#endif // _OPTION_GNB_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionHtInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionHtInstall.h new file mode 100644 index 0000000..bcf380b --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionHtInstall.h @@ -0,0 +1,365 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: Ht + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_HT_INSTALL_H_ +#define _OPTION_HT_INSTALL_H_ + +#include "Topology.h" +#include "htFeat.h" +#include "htInterface.h" +#include "htNb.h" +#include "htTopologies.h" +/* + * Advanced Option only, hardware socket naming is the preferred method. + */ +#ifdef BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP + #define CFG_SYSTEM_PHYSICAL_SOCKET_MAP (BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP) +#else + #define CFG_SYSTEM_PHYSICAL_SOCKET_MAP (NULL) +#endif + +/* + * OPTION_IS_RECOVERY_HT is true if Basic API is being used. + */ +#ifndef OPTION_IS_RECOVERY_HT + #define OPTION_IS_RECOVERY_HT TRUE +#endif + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition. + */ + +#ifndef OPTION_MULTISOCKET + #error BLDOPT: Option not defined: "OPTION_MULTISOCKET" +#endif + +/* + * Based on user level options, set Ht internal options. + * For now, Family 10h support will assume single module. For multi module, + * this will have to be changed to not set non-coherent only. + */ +#define OPTION_HT_NON_COHERENT_ONLY FALSE + +#if (OPTION_FAMILY15H_TN == TRUE) +/* Families with only PCIe do not need a non-coherent only option. */ +#else + // Process Family 10h and 15h Models 00h-0Fh by socket, applying the MultiSocket option where it is allowable. + #if OPTION_G34_SOCKET_SUPPORT == FALSE + // Hydra has coherent support, other Family 10h should follow MultiSocket support. + #if OPTION_MULTISOCKET == FALSE + #undef OPTION_HT_NON_COHERENT_ONLY + #define OPTION_HT_NON_COHERENT_ONLY TRUE + #endif + #endif +#endif + +/* + * Macros will generate the correct item reference based on options + */ +#if AGESA_ENTRY_INIT_EARLY == TRUE + // Select the interface and features + #if ((OPTION_FAMILY15H_TN == TRUE)) + #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL + #define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNone + #define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceMapsOnly + #else + #if (FALSE) + #else + // Family 10h and 15h Models 00h-0Fh + #if OPTION_HT_NON_COHERENT_ONLY == FALSE + #define INTERNAL_HT_OPTION_FEATURES &HtFeaturesDefault + #define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceDefault + #else + #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL + #define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNonCoherentOnly + #define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceNonCoherentOnly + #endif + #endif + #endif + // Select Northbridge components + #if OPTION_FAMILY10H == TRUE + #if OPTION_HT_NON_COHERENT_ONLY == TRUE + #define INTERNAL_HT_OPTION_FAM10_NB &HtFam10NbNonCoherentOnly, &HtFam10RevDNbNonCoherentOnly, &HtFam10RevENbNonCoherentOnly, + #else + #define INTERNAL_HT_OPTION_FAM10_NB &HtFam10NbDefault, &HtFam10RevDNbDefault, &HtFam10RevENbDefault, + #endif + #else + #define INTERNAL_HT_OPTION_FAM10_NB + #endif + + #if OPTION_FAMILY12H == TRUE + #define INTERNAL_HT_OPTION_FAM12_NB &HtFam12Nb, + #else + #define INTERNAL_HT_OPTION_FAM12_NB + #endif + + #if OPTION_FAMILY14H == TRUE + #define INTERNAL_HT_OPTION_FAM14_NB &HtFam14Nb, + #else + #define INTERNAL_HT_OPTION_FAM14_NB + #endif + + #if OPTION_FAMILY15H == TRUE + #if OPTION_FAMILY15H_OR == TRUE + #if OPTION_HT_NON_COHERENT_ONLY == TRUE + #define INTERNAL_HT_OPTION_FAM15_NB &HtFam15NbNonCoherentOnly, + #else + #define INTERNAL_HT_OPTION_FAM15_NB &HtFam15NbDefault, + #endif + #else + #define INTERNAL_HT_OPTION_FAM15_NB + #endif + #if OPTION_FAMILY15H_TN == TRUE + #define INTERNAL_HT_OPTION_FAM15TN_NB &HtFam15Mod1xNb, + #else + #define INTERNAL_HT_OPTION_FAM15TN_NB + #endif +// #if OPTION_FAMILY15H_KM == TRUE +// #define INTERNAL_HT_OPTION_FAM15KM_NB &HtFam15Mod2xNbDefault, +// #else +// #define INTERNAL_HT_OPTION_FAM15KM_NB +// #endif +// #if OPTION_FAMILY15H_KV == TRUE +// #define INTERNAL_HT_OPTION_FAM15KV_NB &HtFam15Mod1xNb, +// #else +// #define INTERNAL_HT_OPTION_FAM15KV_NB +// #endif + #else + #define INTERNAL_HT_OPTION_FAM15_NB + #define INTERNAL_HT_OPTION_FAM15TN_NB + //#define INTERNAL_HT_OPTION_FAM15KM_NB + //#define INTERNAL_HT_OPTION_FAM15KV_NB + #endif + + #define INTERNAL_ONLY_NB_LIST_ITEM INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS, + #ifndef INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS + #undef INTERNAL_ONLY_NB_LIST_ITEM + #define INTERNAL_ONLY_NB_LIST_ITEM + #endif + + /* Install the correct set of northbridge implementations. Each item provides its own comma, the last item + * is ok to have a comma because the final item (NULL) is added below. + */ + #define INTERNAL_HT_OPTION_SUPPORTED_NBS \ + INTERNAL_ONLY_NB_LIST_ITEM \ + INTERNAL_HT_OPTION_FAM10_NB \ + INTERNAL_HT_OPTION_FAM15_NB \ + INTERNAL_HT_OPTION_FAM12_NB \ + INTERNAL_HT_OPTION_FAM14_NB \ + INTERNAL_HT_OPTION_FAM15TN_NB + +#else + // Not Init Early + #define INTERNAL_HT_OPTION_FEATURES NULL + #define INTERNAL_HT_OPTION_INTERFACE NULL + #define INTERNAL_HT_OPTION_SUPPORTED_NBS NULL + #define HT_OPTIONS_PLATFORM NULL + #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL +#endif + +#ifdef AGESA_ENTRY_INIT_EARLY + #if AGESA_ENTRY_INIT_EARLY == TRUE + + extern HT_FEATURES HtFeaturesDefault; + extern HT_FEATURES HtFeaturesNonCoherentOnly; + extern HT_FEATURES HtFeaturesCoherentOnly; + extern HT_FEATURES HtFeaturesNone; + extern HT_INTERFACE HtInterfaceDefault; + extern HT_INTERFACE HtInterfaceNonCoherentOnly; + extern HT_INTERFACE HtInterfaceCoherentOnly; + extern HT_INTERFACE HtInterfaceMapsOnly; + extern HT_INTERFACE HtInterfaceNone; + extern NORTHBRIDGE HtFam10NbDefault; + extern NORTHBRIDGE HtFam10RevDNbDefault; + extern NORTHBRIDGE HtFam10NbNonCoherentOnly; + extern NORTHBRIDGE HtFam10RevDNbNonCoherentOnly; + extern NORTHBRIDGE HtFam10RevENbDefault; + extern NORTHBRIDGE HtFam10RevENbNonCoherentOnly; + extern NORTHBRIDGE HtFam12Nb; + extern NORTHBRIDGE HtFam14Nb; + extern NORTHBRIDGE HtFam10NbNone; + extern NORTHBRIDGE HtFam15NbDefault; + extern NORTHBRIDGE HtFam15NbNonCoherentOnly; + extern NORTHBRIDGE HtFam15Mod1xNb; + + CONST VOID * CONST ROMDATA HtInstalledFamilyNorthbridgeList[] = { + INTERNAL_HT_OPTION_SUPPORTED_NBS + NULL + }; + + STATIC CONST AMD_HT_INTERFACE ROMDATA HtOptionsPlatform = + { + CFG_STARTING_BUSNUM, CFG_MAXIMUM_BUSNUM, CFG_ALLOCATED_BUSNUM, + (MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST, + (DEVICE_CAP_OVERRIDE *)CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST, + (CPU_TO_CPU_PCB_LIMITS *)CFG_HTFABRIC_LIMITS_LIST, + (IO_PCB_LIMITS *)CFG_HTCHAIN_LIMITS_LIST, + (OVERRIDE_BUS_NUMBERS *)CFG_BUS_NUMBERS_LIST, + (IGNORE_LINK *)CFG_IGNORE_LINK_LIST, + (SKIP_REGANG *)CFG_LINK_SKIP_REGANG_LIST, + (UINT8 **)CFG_ADDITIONAL_TOPOLOGIES_LIST, + (SYSTEM_PHYSICAL_SOCKET_MAP *)CFG_SYSTEM_PHYSICAL_SOCKET_MAP + }; + #ifndef HT_OPTIONS_PLATFORM + #define HT_OPTIONS_PLATFORM &HtOptionsPlatform + #endif + + /** + * A list of all the supported topologies. + * + */ + #ifndef INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES + CONST UINT8 *CONST ROMDATA AmdTopolist[] = + { + amdHtTopologySingleNode, + amdHtTopologyDualNode, + amdHtTopologyThreeLine, + amdHtTopologyTriangle, + amdHtTopologyFourLine, + amdHtTopologyFourStar, + amdHtTopologyFourDegenerate, + amdHtTopologyFourSquare, + amdHtTopologyFourKite, + amdHtTopologyFourFully, + amdHtTopologyFiveFully, + amdHtTopologyFiveTwistedLadder, + amdHtTopologySixFully, + amdHtTopologySixDoubloonLower, + amdHtTopologySixDoubloonUpper, + amdHtTopologySixTwistedLadder, + amdHtTopologySevenFully, + amdHtTopologySevenTwistedLadder, + amdHtTopologyEightFully, + amdHtTopologyEightDoubloon, + amdHtTopologyEightTwistedLadder, + amdHtTopologyEightStraightLadder, + amdHtTopologySixTwinTriangles, + amdHtTopologyEightTwinFullyFourWays, + NULL + }; + #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES AmdTopolist + #endif + + /** + * Declare the instance of the Ht option configuration structure + */ + CONST OPTION_HT_CONFIGURATION ROMDATA OptionHtConfiguration = { + OPTION_IS_RECOVERY_HT, + CFG_SET_HTCRC_SYNC_FLOOD, + CFG_USE_UNIT_ID_CLUMPING, + HT_OPTIONS_PLATFORM, + INTERNAL_HT_OPTION_INTERFACE, + INTERNAL_HT_OPTION_FEATURES, + &HtInstalledFamilyNorthbridgeList, + INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES + }; + + #endif +#endif + +#ifndef OPTION_HT_INIIT_RESET_ENTRY + + #define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset + #define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY AmdHtResetConstructor + + #if ((OPTION_FAMILY15H_TN == TRUE) ) + #undef OPTION_HT_INIIT_RESET_ENTRY + #undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY + #define OPTION_HT_INIIT_RESET_ENTRY NULL + #define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY NULL + #endif + + #if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H_OR == TRUE)) + #undef OPTION_HT_INIIT_RESET_ENTRY + #undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY + #define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset + #define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY AmdHtResetConstructor + #endif + +#endif + +#ifdef AGESA_ENTRY_INIT_RESET + #if AGESA_ENTRY_INIT_RESET == TRUE + + CONST AMD_HT_RESET_INTERFACE ROMDATA HtOptionResetDefaults = { + (MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST, + 0 // Unused by options + }; + + CONST OPTION_HT_INIT_RESET ROMDATA HtOptionInitReset = { + OPTION_HT_INIIT_RESET_ENTRY, + OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY + }; + #endif + +#endif + +#endif // _OPTION_HT_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionHtcInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionHtcInstall.h new file mode 100644 index 0000000..3f3701f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionHtcInstall.h @@ -0,0 +1,113 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: Hardware Thermal Control (HTC). + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 63692 $ @e $Date: 2012-01-03 22:13:28 -0600 (Tue, 03 Jan 2012) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_HTC_INSTALL_H_ +#define _OPTION_HTC_INSTALL_H_ + +#include "cpuHtc.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#define OPTION_CPU_HTC_FEAT +#define F15_TN_HTC_SUPPORT + +#if OPTION_CPU_HTC == TRUE + #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) + // Family 15h + #ifdef OPTION_FAMILY15H + #if OPTION_FAMILY15H == TRUE + #if OPTION_FAMILY15H_TN == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHtc; + #undef OPTION_CPU_HTC_FEAT + #define OPTION_CPU_HTC_FEAT &CpuFeatureHtc, + extern CONST HTC_FAMILY_SERVICES ROMDATA F15TnHtcSupport; + #undef F15_TN_HTC_SUPPORT + #define F15_TN_HTC_SUPPORT {AMD_FAMILY_15_TN, &F15TnHtcSupport}, + #endif + #endif + #endif + #endif +#endif + +CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HtcFamilyServiceArray[] = +{ + F15_TN_HTC_SUPPORT + {0, NULL} +}; + +CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HtcFamilyServiceTable = +{ + (sizeof (HtcFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &HtcFamilyServiceArray[0] +}; + +#endif // _OPTION_HTC_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionHwC1eInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionHwC1eInstall.h new file mode 100644 index 0000000..9b8a17c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionHwC1eInstall.h @@ -0,0 +1,107 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: HW C1e + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_HW_C1E_INSTALL_H_ +#define _OPTION_HW_C1E_INSTALL_H_ + +#include "cpuHwC1e.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#define OPTION_HW_C1E_FEAT +#define F10_HW_C1E_SUPPORT +#if AGESA_ENTRY_INIT_EARLY == TRUE + #ifdef OPTION_FAMILY10H + #if OPTION_FAMILY10H == TRUE + #if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE) + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHwC1e; + #undef OPTION_HW_C1E_FEAT + #define OPTION_HW_C1E_FEAT &CpuFeatureHwC1e, + extern CONST HW_C1E_FAMILY_SERVICES ROMDATA F10HwC1e; + #undef F10_HW_C1E_SUPPORT + #define F10_HW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10HwC1e}, + #endif + #endif + #endif + CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HwC1eFamilyServiceArray[] = + { + F10_HW_C1E_SUPPORT + {0, NULL} + }; + CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HwC1eFamilyServiceTable = + { + (sizeof (HwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &HwC1eFamilyServiceArray[0] + }; +#endif + +#endif // _OPTION_HW_C1E_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionIdsInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionIdsInstall.h new file mode 100644 index 0000000..0ad2df2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionIdsInstall.h @@ -0,0 +1,666 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * IDS Option Install File + * + * This file generates the defaults tables for family 10h model 5 processors. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ +#ifndef _OPTION_IDS_INSTALL_H_ +#define _OPTION_IDS_INSTALL_H_ +#include "Ids.h" +#include "IdsHt.h" +#include "IdsLib.h" +#include "IdsDebugPrint.h" +#ifdef __IDS_EXTENDED__ + #include OPTION_IDS_EXT_INSTALL_FILE +#endif + +#define IDS_LATE_RUN_AP_TASK + +#define M_HTIDS_PORT_OVERRIDE_HOOK (PF_HtIdsGetPortOverride)CommonVoid +#if (IDSOPT_IDS_ENABLED == TRUE) + #if (IDSOPT_CONTROL_ENABLED == TRUE) + // Check for all families which include HT Features. + #if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H_OR == TRUE) || ) && (AGESA_ENTRY_INIT_POST == TRUE) + #undef M_HTIDS_PORT_OVERRIDE_HOOK + #define M_HTIDS_PORT_OVERRIDE_HOOK HtIdsGetPortOverride + #endif + #endif +#endif // OPTION_IDS_LEVEL +CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVERRIDE_HOOK; + +#if (IDSOPT_IDS_ENABLED == TRUE) + #if (AGESA_ENTRY_INIT_LATE == TRUE) + #undef IDS_LATE_RUN_AP_TASK + #define IDS_LATE_RUN_AP_TASK {IDS_LATE_RUN_AP_TASK_ID, (IMAGE_ENTRY)AmdIdsRunApTaskLate}, + #endif +#endif // OPTION_IDS_LEVEL + +#if (IDSOPT_TRACING_ENABLED == TRUE) + #if (AGESA_ENTRY_INIT_POST == TRUE) + #include <mu.h> + CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = { + { (UINT32) /*(UINT64)*/ MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"}, + { (UINT32) /*(UINT64)*/ MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"}, + { (UINT32) /*(UINT64)*/ MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"} + }; + #elif (AGESA_ENTRY_INIT_RECOVERY == TRUE) + #include <mru.h> + CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = { + { (UINT32) (UINT64) MemRecUWrite1CL, "Write1Cl(PhyAddrLo,BufferAddr)"}, + { (UINT32) (UINT64) MemRecURead1CL, "Read1Cl(BufferAddr,PhyAddrLo)"}, + { (UINT32) (UINT64) MemRecUFlushPattern, "Flush1Cl(PhyAddrLo)"} + }; + #else + CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = { + { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"}, + { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"}, + { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"} + }; + #endif +#else + CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = { + { (UINT32) /*(UINT64)*/ CommonReturnFalse, "DefRet()"}, + { (UINT32) /*(UINT64)*/ CommonReturnFalse, "DefRet()"}, + { (UINT32) /*(UINT64)*/ CommonReturnFalse, "DefRet()"} + }; +#endif + + +#define NV_TO_CMOS(Len, NV_ID) {Len, NV_ID}, +#define OPTION_IDS_NV_TO_CMOS_END NV_TO_CMOS (IDS_NV_TO_CMOS_LEN_END, IDS_NV_TO_CMOS_ID_END) +#if (IDSOPT_IDS_ENABLED == TRUE) + #if ((IDSOPT_CONTROL_ENABLED == TRUE) && \ + ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || \ + (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || \ + (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))) + #if (IDSOPT_CONTROL_NV_TO_CMOS == TRUE) + #define OPTION_IDS_NV_TO_CMOS_COMMON + + #ifdef OPTION_FAMILY10H + #if OPTION_FAMILY10H == TRUE + #define OPTION_IDS_NV_TO_CMOS_F10 + #endif + #endif + + #ifdef OPTION_FAMILY12H + #if OPTION_FAMILY12H == TRUE + #define OPTION_IDS_NV_TO_CMOS_F12 + #endif + #endif + + #ifdef OPTION_FAMILY14H + #if OPTION_FAMILY14H == TRUE + #define OPTION_IDS_NV_TO_CMOS_F14 + #endif + #endif + + #ifdef OPTION_FAMILY15H_OR + #if OPTION_FAMILY15H_OR == TRUE + #define OPTION_IDS_NV_TO_CMOS_F15_OR + #endif + #endif + + #ifdef OPTION_FAMILY15H_TN + #if OPTION_FAMILY15H_TN == TRUE + #define OPTION_IDS_NV_TO_CMOS_F15_TN\ + {IDS_NV_TO_CMOS_LEN_BYTE, AGESA_IDS_NV_UCODE}, + #endif + #endif + + #ifndef OPTION_IDS_NV_TO_CMOS_F10 + #define OPTION_IDS_NV_TO_CMOS_F10 + #endif + + #ifndef OPTION_IDS_NV_TO_CMOS_F12 + #define OPTION_IDS_NV_TO_CMOS_F12 + #endif + + #ifndef OPTION_IDS_NV_TO_CMOS_F14 + #define OPTION_IDS_NV_TO_CMOS_F14 + #endif + + #ifndef OPTION_IDS_NV_TO_CMOS_F15_OR + #define OPTION_IDS_NV_TO_CMOS_F15_OR + #endif + + #ifndef OPTION_IDS_NV_TO_CMOS_F15_TN + #define OPTION_IDS_NV_TO_CMOS_F15_TN + #endif + + #ifndef OPTION_IDS_NV_TO_CMOS_EXTEND + #define OPTION_IDS_NV_TO_CMOS_EXTEND + #endif + + IDS_NV_TO_CMOS gIdsNVToCmos[] = { + OPTION_IDS_NV_TO_CMOS_COMMON + OPTION_IDS_NV_TO_CMOS_F10 + OPTION_IDS_NV_TO_CMOS_F12 + OPTION_IDS_NV_TO_CMOS_F14 + OPTION_IDS_NV_TO_CMOS_F15_OR + OPTION_IDS_NV_TO_CMOS_F15_TN + OPTION_IDS_NV_TO_CMOS_EXTEND + OPTION_IDS_NV_TO_CMOS_END + }; + #else + IDS_NV_TO_CMOS gIdsNVToCmos[] = { + OPTION_IDS_NV_TO_CMOS_END + }; + #endif + #else + IDS_NV_TO_CMOS gIdsNVToCmos[] = { + OPTION_IDS_NV_TO_CMOS_END + }; + #endif +#else + IDS_NV_TO_CMOS gIdsNVToCmos[] = { + OPTION_IDS_NV_TO_CMOS_END + }; +#endif + +///Ids Feat Options +#if ((IDSOPT_IDS_ENABLED == TRUE) && \ + ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || \ + (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || \ + (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))) + #if (IDSOPT_CONTROL_ENABLED == TRUE) + #ifndef OPTION_IDS_EXTEND_FEATS + #define OPTION_IDS_EXTEND_FEATS + #endif + + #define OPTION_IDS_FEAT_ECCCTRL\ + OPTION_IDS_FEAT_ECCCTRL_F10 \ + OPTION_IDS_FEAT_ECCCTRL_F12 \ + OPTION_IDS_FEAT_ECCCTRL_F15_OR + + #define OPTION_IDS_FEAT_GNB_PLATFORMCFG\ + OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 \ + OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 \ + OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN + + #define OPTION_IDS_FEAT_CPB_CTRL\ + OPTION_IDS_FEAT_CPB_CTRL_F12 + + #define OPTION_IDS_FEAT_HTC_CTRL\ + OPTION_IDS_FEAT_HTC_CTRL_F15_OR \ + OPTION_IDS_FEAT_HTC_CTRL_F15_TN + + #define OPTION_IDS_FEAT_MEMORY_MAPPING\ + OPTION_IDS_FEAT_MEMORY_MAPPING_F12 \ + OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR \ + OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN + + #define OPTION_IDS_FEAT_HT_ASSIST\ + OPTION_IDS_FEAT_HT_ASSIST_F10HY \ + OPTION_IDS_FEAT_HT_ASSIST_F15_OR + + #define OPTION_IDS_FEAT_ECCSYMBOLSIZE\ + OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 \ + OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR + +/*---------------------------------------------------------------------------- + * Family 10 feat blocks + * + *---------------------------------------------------------------------------- + */ + #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 + #define OPTION_IDS_FEAT_ECCCTRL_F10 + #ifdef OPTION_FAMILY10H + #if OPTION_FAMILY10H == TRUE +//Ecc symbol size + extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF10; + #undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 + #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 &IdsFeatEccSymbolSizeBlockF10, + +//ECC scrub control + extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF10; + #undef OPTION_IDS_FEAT_ECCCTRL_F10 + #define OPTION_IDS_FEAT_ECCCTRL_F10 &IdsFeatEccCtrlBlockF10, + #endif + #endif + + //Misc Features + #define OPTION_IDS_FEAT_HT_ASSIST_F10HY + #ifdef OPTION_FAMILY10H_HY + #if OPTION_FAMILY10H_HY == TRUE + #undef OPTION_IDS_FEAT_HT_ASSIST_F10HY + extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF10Hy; + + #define OPTION_IDS_FEAT_HT_ASSIST_F10HY \ + &IdsFeatHtAssistBlockPlatformCfgF10Hy, + #endif + #endif +/*---------------------------------------------------------------------------- + * Family 12 feat blocks + * + *---------------------------------------------------------------------------- + */ + #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 + #define OPTION_IDS_FEAT_ECCCTRL_F12 + #define OPTION_IDS_FEAT_CPB_CTRL_F12 + #define OPTION_IDS_FEAT_MEMORY_MAPPING_F12 + #ifdef OPTION_FAMILY12H + #if OPTION_FAMILY12H == TRUE + extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF12; + #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 + #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 &IdsFeatGnbPlatformCfgBlockF12, + + //ECC scrub control + extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF12; + #undef OPTION_IDS_FEAT_ECCCTRL_F12 + #define OPTION_IDS_FEAT_ECCCTRL_F12 &IdsFeatEccCtrlBlockF12, + + #undef OPTION_IDS_FEAT_CPB_CTRL_F12 + extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatCpbCtrlBlockF12; + #define OPTION_IDS_FEAT_CPB_CTRL_F12 &IdsFeatCpbCtrlBlockF12, + + extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryChIntlvPostBeforeBlockF12; + extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF12; + #undef OPTION_IDS_FEAT_MEMORY_MAPPING_F12 + #define OPTION_IDS_FEAT_MEMORY_MAPPING_F12 \ + &IdsFeatMemoryChIntlvPostBeforeBlockF12, \ + &IdsFeatMemoryMappingChIntlvBlockF12, + + #endif + #endif + +/*---------------------------------------------------------------------------- + * Family 14 ON feat blocks + * + *---------------------------------------------------------------------------- + */ + #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 + #ifdef OPTION_FAMILY14H_ON + #if OPTION_FAMILY14H_ON == TRUE + extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF14; + #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 + #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 &IdsFeatGnbPlatformCfgBlockF14, + #endif + #endif + + +/*---------------------------------------------------------------------------- + * Family 15 OR feat blocks + * + *---------------------------------------------------------------------------- + */ + #define OPTION_IDS_FEAT_HTC_CTRL_F15_OR + #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR + #define OPTION_IDS_FEAT_HT_ASSIST_F15_OR + #define OPTION_IDS_FEAT_ECCCTRL_F15_OR + #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR + #ifdef OPTION_FAMILY15H_OR + #if OPTION_FAMILY15H_OR == TRUE + extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF15Or; + extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtcControlLateBlockF15Or; + #undef OPTION_IDS_FEAT_HTC_CTRL_F15_OR + #define OPTION_IDS_FEAT_HTC_CTRL_F15_OR\ + &IdsFeatHtcControlBlockF15Or,\ + &IdsFeatHtcControlLateBlockF15Or, + + extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF15Or; + extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF15Or; + #undef OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR + #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR\ + &IdsFeatMemoryMappingPostBeforeBlockF15Or,\ + &IdsFeatMemoryMappingChIntlvBlockF15Or, + + extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF15Or; + #undef OPTION_IDS_FEAT_HT_ASSIST_F15_OR + #define OPTION_IDS_FEAT_HT_ASSIST_F15_OR\ + &IdsFeatHtAssistBlockPlatformCfgF15Or, + + extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF15Or; + #undef OPTION_IDS_FEAT_ECCCTRL_F15_OR + #define OPTION_IDS_FEAT_ECCCTRL_F15_OR &IdsFeatEccCtrlBlockF15Or, + + extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF15Or; + #undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR + #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR &IdsFeatEccSymbolSizeBlockF15Or, + + #endif + #endif +/*---------------------------------------------------------------------------- + * Family 15 TN feat blocks + * + *---------------------------------------------------------------------------- + */ + #define OPTION_IDS_FEAT_HTC_CTRL_F15_TN + #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN + #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN + #ifdef OPTION_FAMILY15H_TN + #if OPTION_FAMILY15H_TN == TRUE + extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF15Tn; + #undef OPTION_IDS_FEAT_HTC_CTRL_F15_TN + #define OPTION_IDS_FEAT_HTC_CTRL_F15_TN\ + &IdsFeatHtcControlBlockF15Tn, + + extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF15Tn; + extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF15Tn; + #undef OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN + #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN\ + &IdsFeatMemoryMappingPostBeforeBlockF15Tn,\ + &IdsFeatMemoryMappingChIntlvBlockF15Tn, + + extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF15Tn; + #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN + #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN &IdsFeatGnbPlatformCfgBlockF15Tn, + #endif + #endif + + #define OPTION_IDS_FEAT_NV_TO_CMOS + #if IDSOPT_CONTROL_NV_TO_CMOS == TRUE + #undef OPTION_IDS_FEAT_NV_TO_CMOS + extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatNvToCmosSaveBlock; + extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatNvToCmosRestoreBlock; + #define OPTION_IDS_FEAT_NV_TO_CMOS\ + &IdsFeatNvToCmosSaveBlock, \ + &IdsFeatNvToCmosRestoreBlock, + + #endif + CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatUcodeBlock = + { + IDS_FEAT_UCODE_UPDATE, + IDS_ALL_CORES, + IDS_UCODE, + IDS_FAMILY_ALL, + IdsSubUCode + }; + + CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatPowerPolicyBlock = + { + IDS_FEAT_POWER_POLICY, + IDS_ALL_CORES, + IDS_PLATFORMCFG_OVERRIDE, + IDS_FAMILY_ALL, + IdsSubPowerPolicyOverride + }; + + CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatTargetPstateBlock = + { + IDS_FEAT_TARGET_PSTATE, + IDS_BSP_ONLY, + IDS_INIT_LATE_AFTER, + IDS_FAMILY_ALL, + IdsSubTargetPstate + }; + + CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatPostPstateBlock = + { + IDS_FEAT_POSTPSTATE, + IDS_ALL_CORES, + IDS_CPU_Early_Override, + IDS_FAMILY_ALL, + IdsSubPostPState + }; + + //Dram controller Features + CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctAllMemClkBlock = + { + IDS_FEAT_DCT_ALLMEMCLK, + IDS_BSP_ONLY, + IDS_ALL_MEMORY_CLOCK, + IDS_FAMILY_ALL, + IdsSubAllMemClkEn + }; + + CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctGangModeBlock = + { + IDS_FEAT_DCT_GANGMODE, + IDS_BSP_ONLY, + IDS_GANGING_MODE, + IDS_FAMILY_ALL, + IdsSubGangingMode + }; + + CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctBurstLengthBlock = + { + IDS_FEAT_DCT_BURSTLENGTH, + IDS_BSP_ONLY, + IDS_BURST_LENGTH32, + AMD_FAMILY_10, + IdsSubBurstLength32 + }; + + CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownCtrlBlock = + { + IDS_FEAT_DCT_POWERDOWN, + IDS_BSP_ONLY, + IDS_INIT_POST_BEFORE, + IDS_FAMILY_ALL, + IdsSubPowerDownCtrl + }; + + CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctDllShutDownBlock = + { + IDS_FEAT_DCT_DLLSHUTDOWN, + IDS_BSP_ONLY, + IDS_DLL_SHUT_DOWN, + IDS_FAMILY_ALL, + IdsSubDllShutDownSR + }; + + + CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownModeBlock = + { + IDS_FEAT_DCT_POWERDOWN, + IDS_BSP_ONLY, + IDS_POWERDOWN_MODE, + IDS_FAMILY_ALL, + IdsSubPowerDownMode + }; + + CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHdtOutBlock = + { + IDS_FEAT_HDTOUT, + IDS_BSP_ONLY, + IDS_INIT_EARLY_BEFORE, + IDS_FAMILY_ALL, + IdsSubHdtOut + }; + + CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtSettingBlock = + { + IDS_FEAT_HT_SETTING, + IDS_BSP_ONLY, + IDS_HT_CONTROL, + IDS_FAMILY_ALL, + IdsSubHtLinkControl + }; + + CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsContorlFeats[] = + { + &IdsFeatUcodeBlock, + &IdsFeatPowerPolicyBlock, + + &IdsFeatTargetPstateBlock, + + &IdsFeatPostPstateBlock, + + OPTION_IDS_FEAT_NV_TO_CMOS + + OPTION_IDS_FEAT_ECCSYMBOLSIZE + + OPTION_IDS_FEAT_ECCCTRL + + &IdsFeatDctAllMemClkBlock, + + &IdsFeatDctGangModeBlock, + + &IdsFeatDctBurstLengthBlock, + + &IdsFeatDctPowerDownCtrlBlock, + + &IdsFeatDctPowerDownModeBlock, + + &IdsFeatDctPowerDownModeBlock, + + OPTION_IDS_FEAT_HT_ASSIST + + &IdsFeatHdtOutBlock, + + &IdsFeatHtSettingBlock, + + OPTION_IDS_FEAT_GNB_PLATFORMCFG + + OPTION_IDS_FEAT_CPB_CTRL + + OPTION_IDS_FEAT_HTC_CTRL + + OPTION_IDS_FEAT_MEMORY_MAPPING + + OPTION_IDS_EXTEND_FEATS + + NULL + }; + #else + CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsContorlFeats[] = + { + NULL + }; + #endif//IDSOPT_CONTROL_ENABLED + + #define OPTION_IDS_FAM_REGACC_F15TN + #ifdef OPTION_FAMILY15H_TN + #if OPTION_FAMILY15H_TN == TRUE + extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatRegGmmxF15Tn; + #undef OPTION_IDS_FAM_REGACC_F15TN + #define OPTION_IDS_FAM_REGACC_F15TN \ + &IdsFeatRegGmmxF15Tn, + #endif + #endif + + + CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsRegAccessTbl[] = + { + OPTION_IDS_FAM_REGACC_F15TN + NULL + }; + +/*---------------------------------------------------------------------------- + * IDS TRACING SERVICES + * + *---------------------------------------------------------------------------- + */ + #if IDSOPT_TRACING_ENABLED == TRUE + #define IDS_TRACING_CONSOLE_HDTOUT + #define IDS_TRACING_CONSOLE_SERIALPORT + #define IDS_TRACING_CONSOLE_REDIRECT_IO + + #ifdef IDSOPT_TRACING_CONSOLE_HDTOUT + #if IDSOPT_TRACING_CONSOLE_HDTOUT == TRUE + #undef IDS_TRACING_CONSOLE_HDTOUT + extern CONST IDS_DEBUG_PRINT ROMDATA IdsDebugPrintHdtoutInstance; + #define IDS_TRACING_CONSOLE_HDTOUT &IdsDebugPrintHdtoutInstance, + #endif + #endif + + #ifdef IDSOPT_TRACING_CONSOLE_SERIALPORT + #if IDSOPT_TRACING_CONSOLE_SERIALPORT == TRUE + #undef IDS_TRACING_CONSOLE_SERIALPORT + extern CONST IDS_DEBUG_PRINT ROMDATA IdsDebugPrintSerialInstance; + #define IDS_TRACING_CONSOLE_SERIALPORT &IdsDebugPrintSerialInstance, + #endif + #endif + + #ifdef IDSOPT_TRACING_CONSOLE_REDIRECT_IO + #if IDSOPT_TRACING_CONSOLE_REDIRECT_IO == TRUE + #undef IDS_TRACING_CONSOLE_REDIRECT_IO + extern CONST IDS_DEBUG_PRINT ROMDATA IdsDebugPrintRedirectIoInstance; + #define IDS_TRACING_CONSOLE_REDIRECT_IO &IdsDebugPrintRedirectIoInstance, + #endif + #endif + + CONST IDS_DEBUG_PRINT* ROMDATA IdsDebugPrint[] = + { + IDS_TRACING_CONSOLE_SERIALPORT + IDS_TRACING_CONSOLE_HDTOUT + IDS_TRACING_CONSOLE_REDIRECT_IO + NULL + }; + #else + CONST IDS_DEBUG_PRINT* ROMDATA IdsDebugPrint[] = + { + NULL + }; + #endif + +#else + CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsContorlFeats[] = + { + NULL + }; + + CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsRegAccessTbl[] = + { + NULL + }; + + CONST IDS_DEBUG_PRINT* ROMDATA IdsDebugPrint[] = + { + NULL + }; +#endif// IDSOPT_IDS_ENABLED + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionIoCstateInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionIoCstateInstall.h new file mode 100644 index 0000000..d46e5a3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionIoCstateInstall.h @@ -0,0 +1,171 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: IO C-state + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_IO_CSTATE_INSTALL_H_ +#define _OPTION_IO_CSTATE_INSTALL_H_ + +#include "cpuIoCstate.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ + +#define OPTION_IO_CSTATE_FEAT +#define F10_IO_CSTATE_SUPPORT +#define F12_IO_CSTATE_SUPPORT +#define F14_IO_CSTATE_SUPPORT +#define F15_OR_IO_CSTATE_SUPPORT +#define F15_TN_IO_CSTATE_SUPPORT + +#if OPTION_IO_CSTATE == TRUE + #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) + #ifdef OPTION_FAMILY10H + #if OPTION_FAMILY10H == TRUE + #if OPTION_FAMILY10H_PH == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate; + #undef OPTION_IO_CSTATE_FEAT + #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate, + extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F10IoCstateSupport; + #undef F10_IO_CSTATE_SUPPORT + #define F10_IO_CSTATE_SUPPORT {AMD_FAMILY_10_PH, &F10IoCstateSupport}, + #endif + #endif + #endif + + #ifdef OPTION_FAMILY12H + #if OPTION_FAMILY12H == TRUE + #if OPTION_FAMILY12H_LN == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate; + #undef OPTION_IO_CSTATE_FEAT + #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate, + extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F12IoCstateSupport; + #undef F12_IO_CSTATE_SUPPORT + #define F12_IO_CSTATE_SUPPORT {AMD_FAMILY_12_LN, &F12IoCstateSupport}, + #endif + #endif + #endif + + #ifdef OPTION_FAMILY14H + #if OPTION_FAMILY14H == TRUE + #if (OPTION_FAMILY14H_ON == TRUE) + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate; + #undef OPTION_IO_CSTATE_FEAT + #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate, + extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F14IoCstateSupport; + #undef F14_IO_CSTATE_SUPPORT + #define F14_IO_CSTATE_SUPPORT {AMD_FAMILY_14, &F14IoCstateSupport}, + #endif + #endif + #endif + + #ifdef OPTION_FAMILY15H + #if OPTION_FAMILY15H == TRUE + #if OPTION_FAMILY15H_OR == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate; + #undef OPTION_IO_CSTATE_FEAT + #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate, + extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F15OrIoCstateSupport; + #undef F15_OR_IO_CSTATE_SUPPORT + #define F15_OR_IO_CSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrIoCstateSupport}, + #endif + + #if OPTION_FAMILY15H_TN == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate; + #undef OPTION_IO_CSTATE_FEAT + #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate, + extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F15TnIoCstateSupport; + #undef F15_TN_IO_CSTATE_SUPPORT + #define F15_TN_IO_CSTATE_SUPPORT {AMD_FAMILY_15_TN, &F15TnIoCstateSupport}, + #endif + + #endif + #endif + + #endif +#endif + +CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA IoCstateFamilyServiceArray[] = +{ + F10_IO_CSTATE_SUPPORT + F12_IO_CSTATE_SUPPORT + F14_IO_CSTATE_SUPPORT + F15_OR_IO_CSTATE_SUPPORT + F15_TN_IO_CSTATE_SUPPORT + {0, NULL} +}; + +CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA IoCstateFamilyServiceTable = +{ + (sizeof (IoCstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &IoCstateFamilyServiceArray[0] +}; + +#endif // _OPTION_IO_CSTATE_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h new file mode 100644 index 0000000..d41b728 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h @@ -0,0 +1,133 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: L3 Dependent Features + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_L3_FEATURES_INSTALL_H_ +#define _OPTION_L3_FEATURES_INSTALL_H_ + +#include "cpuL3Features.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#define OPTION_L3_FEAT +#define F10_L3_FEAT_SUPPORT +#define F15_OR_L3_FEAT_SUPPORT +#define L3_FEAT_AP_DISABLE_CACHE +#define L3_FEAT_AP_ENABLE_CACHE + +#if (OPTION_HT_ASSIST == TRUE || OPTION_ATM_MODE == TRUE) + #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE) + #ifdef OPTION_FAMILY10H + #if OPTION_FAMILY10H == TRUE + #if OPTION_FAMILY10H_HY == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuL3Features; + #undef OPTION_L3_FEAT + #define OPTION_L3_FEAT &CpuL3Features, + extern CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F10L3Features; + #undef F10_L3_FEAT_SUPPORT + #define F10_L3_FEAT_SUPPORT {AMD_FAMILY_10_HY, &F10L3Features}, + #endif + #endif + #endif + + #ifdef OPTION_FAMILY15H_OR + #if OPTION_FAMILY15H_OR == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuL3Features; + #undef OPTION_L3_FEAT + #define OPTION_L3_FEAT &CpuL3Features, + extern CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F15OrL3Features; + #undef F15_OR_L3_FEAT_SUPPORT + #define F15_OR_L3_FEAT_SUPPORT {AMD_FAMILY_15_OR, &F15OrL3Features}, + #endif + #endif + + #undef AGESA_ENTRY_LATE_RUN_AP_TASK + #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE + #undef L3_FEAT_AP_DISABLE_CACHE + #define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches}, + #undef L3_FEAT_AP_ENABLE_CACHE + #define L3_FEAT_AP_ENABLE_CACHE {AP_LATE_TASK_ENABLE_CACHE, (IMAGE_ENTRY) EnableAllCaches}, + #endif +#endif + +CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA L3FeatureFamilyServiceArray[] = +{ + F10_L3_FEAT_SUPPORT + F15_OR_L3_FEAT_SUPPORT + {0, NULL} +}; +CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA L3FeatureFamilyServiceTable = +{ + (sizeof (L3FeatureFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &L3FeatureFamilyServiceArray[0] +}; + +#endif // _OPTION_L3_FEATURES_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionLowPwrPstateInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionLowPwrPstateInstall.h new file mode 100644 index 0000000..ab36a2d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionLowPwrPstateInstall.h @@ -0,0 +1,115 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: Low Power Pstate for PROCHOT_L Throttling. + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_LOW_PWR_PSTATE_INSTALL_H_ +#define _OPTION_LOW_PWR_PSTATE_INSTALL_H_ + +#include "cpuLowPwrPstate.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT +#define F15_OR_LOW_PWR_PSTATE_SUPPORT + +#if OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT == TRUE + #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) + // Family 15h + #ifdef OPTION_FAMILY15H + #if OPTION_FAMILY15H == TRUE + #if OPTION_FAMILY15H_OR == TRUE + #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE) + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureLowPwrPstate; + #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT + #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT &CpuFeatureLowPwrPstate, + extern CONST LOW_PWR_PSTATE_FAMILY_SERVICES ROMDATA F15OrLowPwrPstateSupport; + #undef F15_OR_LOW_PWR_PSTATE_SUPPORT + #define F15_OR_LOW_PWR_PSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrLowPwrPstateSupport}, + #endif + #endif + #endif + #endif + #endif +#endif + +CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA LowPwrPstateFamilyServiceArray[] = +{ + F15_OR_LOW_PWR_PSTATE_SUPPORT + {0, NULL} +}; + +CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA LowPwrPstateFamilyServiceTable = +{ + (sizeof (LowPwrPstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &LowPwrPstateFamilyServiceArray[0] +}; + +#endif // _OPTION_LOW_PWR_PSTATE_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionMemory.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemory.h new file mode 100644 index 0000000..cf236c3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemory.h @@ -0,0 +1,384 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Memory option API. + * + * Contains structures and values used to control the Memory option code. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: OPTION + * @e $Revision: 64574 $ @e $Date: 2012-01-25 01:01:51 -0600 (Wed, 25 Jan 2012) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _OPTION_MEMORY_H_ +#define _OPTION_MEMORY_H_ + +/* Memory Includes */ +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "ma.h" +#include "mp.h" +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +#define MAX_FF_TYPES 6 ///< Maximum number of DDR Form factors (UDIMMs, RDIMMMs, SODIMMS) supported + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *---------------------------------------------------------------------------------------- + */ + +/* +* STANDARD MEMORY FEATURE FUNCTION POINTER +*/ + +typedef BOOLEAN OPTION_MEM_FEATURE_NB ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +typedef BOOLEAN MEM_TECH_FEAT ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); + +typedef UINT8 MEM_TABLE_FEAT ( + IN OUT MEM_TABLE_ALIAS **MTPtr + ); + +#define MEM_FEAT_BLOCK_NB_STRUCT_VERSION 0x01 + +/** + * MEMORY FEATURE BLOCK - This structure serves as a vector table for standard + * memory feature implementation functions. It contains vectors for all of the + * features that are supported by the various Northbridge devices supported by + * AGESA. + */ +typedef struct _MEM_FEAT_BLOCK_NB { + UINT16 OptMemFeatVersion; ///< Version of memory feature block. + OPTION_MEM_FEATURE_NB *OnlineSpare; ///< Online spare support. + OPTION_MEM_FEATURE_NB *InterleaveBanks; ///< Bank (Chip select) interleaving support. + OPTION_MEM_FEATURE_NB *UndoInterleaveBanks; ///< Undo Bank (Chip Select) interleaving. + OPTION_MEM_FEATURE_NB *CheckInterleaveNodes; ///< Check for Node interleaving support. + OPTION_MEM_FEATURE_NB *InterleaveNodes; ///< Node interleaving support. + OPTION_MEM_FEATURE_NB *InterleaveChannels; ///< Channel interleaving support. + OPTION_MEM_FEATURE_NB *InterleaveRegion; ///< Interleave Region support. + OPTION_MEM_FEATURE_NB *CheckEcc; ///< Check for ECC support. + OPTION_MEM_FEATURE_NB *InitEcc; ///< ECC support. + OPTION_MEM_FEATURE_NB *Training; ///< Choose the type of training (Parallel, standard or hardcoded). + OPTION_MEM_FEATURE_NB *LvDdr3; ///< Low voltage DDR3 dimm support + OPTION_MEM_FEATURE_NB *OnDimmThermal; ///< On-Dimm thermal management + MEM_TECH_FEAT *DramInit; ///< Choose the type of Dram init (hardware based or software based). + OPTION_MEM_FEATURE_NB *ExcludeDIMM; ///< Exclude a dimm. + OPTION_MEM_FEATURE_NB *excel221; + OPTION_MEM_FEATURE_NB *InitCPG; ///< Continuous pattern generation. + OPTION_MEM_FEATURE_NB *InitHwRxEn; ///< Hardware Receiver Enable Training Initilization. +} MEM_FEAT_BLOCK_NB; + +typedef AGESA_STATUS MEM_MAIN_FLOW_CONTROL ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ); + +typedef BOOLEAN OPTION_MEM_FEATURE_MAIN ( + IN MEM_MAIN_DATA_BLOCK *MMPtr + ); + +typedef BOOLEAN MEM_NB_CONSTRUCTOR ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *mmSharedPtr, ///< Pointer to Memory scratchpad + IN UINT8 NodeID + ); + +typedef BOOLEAN MEM_TECH_CONSTRUCTOR ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT MEM_NB_BLOCK *NBPtr + ); + +typedef VOID MEM_INITIALIZER ( + IN OUT MEM_DATA_STRUCT *MemPtr + ); + +typedef AGESA_STATUS MEM_PLATFORM_CFG ( + IN struct _MEM_DATA_STRUCT *MemData, + IN UINT8 SocketID, + IN CH_DEF_STRUCT *CurrentChannel + ); + +typedef BOOLEAN MEM_IDENDIMM_CONSTRUCTOR ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ); + +typedef VOID MEM_TECH_TRAINING_FEAT ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN UINT8 Pass + ); + +typedef BOOLEAN MEM_RESUME_CONSTRUCTOR ( + IN OUT VOID *S3NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ); + +typedef AGESA_STATUS MEM_PLAT_SPEC_CFG ( + IN struct _MEM_DATA_STRUCT *MemData, + IN OUT CH_DEF_STRUCT *CurrentChannel, + IN OUT MEM_PS_BLOCK *PsPtr + ); + +typedef AGESA_STATUS MEM_FLOW_CFG ( + IN OUT MEM_MAIN_DATA_BLOCK *MemData + ); + +#define MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION 0x01 + +/** + * MAIN FEATURE BLOCK - This structure serves as vector table for memory features + * that shared between all northbridge devices. + */ +typedef struct _MEM_FEAT_BLOCK_MAIN { + UINT16 OptMemFeatVersion; ///< Version of main feature block. + OPTION_MEM_FEATURE_MAIN *Training; ///< Training features. + OPTION_MEM_FEATURE_MAIN *ExcludeDIMM; ///< Exclude a dimm. + OPTION_MEM_FEATURE_MAIN *OnlineSpare; ///< On-line spare. + OPTION_MEM_FEATURE_MAIN *InterleaveNodes; ///< Node interleave. + OPTION_MEM_FEATURE_MAIN *InitEcc; ///< Initialize ECC on all nodes if they all support it. + OPTION_MEM_FEATURE_MAIN *MemClr; ///< Memory Clear. + OPTION_MEM_FEATURE_MAIN *MemDmi; ///< Memory DMI Support. + OPTION_MEM_FEATURE_MAIN *excel222; + OPTION_MEM_FEATURE_MAIN *LvDDR3; ///< Low voltage DDR3 support. + OPTION_MEM_FEATURE_MAIN *UmaAllocation; ///< Uma Allocation. + OPTION_MEM_FEATURE_MAIN *MemSave; ///< Memory Context Save + OPTION_MEM_FEATURE_MAIN *MemRestore; ///< Memory Context Restore +} MEM_FEAT_BLOCK_MAIN; + +#define MEM_NB_SUPPORT_STRUCT_VERSION 0x01 +#define MEM_TECH_FEAT_BLOCK_STRUCT_VERSION 0x01 +#define MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION 0x01 +#define MEM_TECH_LRDIMM_STRUCT_VERSION 0x01 +/** + * MEMORY TECHNOLOGY FEATURE BLOCK - This structure serves as a vector table for standard + * memory feature implementation functions. It contains vectors for all of the + * features that are supported by the various Technology features supported by + * AGESA. + */ +typedef struct _MEM_TECH_FEAT_BLOCK { + UINT16 OptMemTechFeatVersion; ///< Version of memory Tech feature block. + MEM_TECH_FEAT *EnterHardwareTraining; ///<Enter HW WL Training + MEM_TECH_FEAT *SwWLTraining; ///<SW Write Levelization training + MEM_TECH_FEAT *HwBasedWLTrainingPart1; ///<HW based write levelization Training Part 1 + MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart1; ///<HW based DQS receiver Enabled Training Part 1 + MEM_TECH_FEAT *HwBasedWLTrainingPart2; ///<HW based write levelization Training Part 2 + MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart2; ///<HW based DQS receiver Enabled Training Part 2 + MEM_TECH_FEAT *TrainExitHwTrn; ///<Exit HW WL Training + MEM_TECH_FEAT *NonOptimizedSWDQSRecEnTrainingPart1; ///< Non-Optimized Software based receiver Enable Training part 1 + MEM_TECH_FEAT *OptimizedSwDqsRecEnTrainingPart1; ///< Optimized Software based receiver Enable Training part 1 + MEM_TECH_FEAT *NonOptimizedSRdWrPosTraining; ///< Non-Optimized Rd Wr Position training + MEM_TECH_FEAT *OptimizedSRdWrPosTraining; ///< Optimized Rd Wr Position training + MEM_TECH_FEAT *MaxRdLatencyTraining; ///< MaxReadLatency Training + MEM_TECH_FEAT *RdPosTraining; ///< HW Rx En Seed Training +} MEM_TECH_FEAT_BLOCK; + +/** + * MEMORY TECHNOLOGY LRDIMM BLOCK - This structure serves as a vector table for standard + * memory feature implementation functions. It contains vectors for all of the + * features that are supported by the various LRDIMM features supported by + * AGESA. + */ +typedef struct _MEM_TECH_LRDIMM { + UINT16 OptMemTechLrdimmVersion; ///< Version of memory Tech feature block. + MEM_TECH_FEAT *MemTInitializeLrdimm; ///< LRDIMM initialization +} MEM_TECH_LRDIMM; +/** + * MEMORY NORTHBRIDGE SUPPORT STRUCT - This structure groups the Northbridge dependent + * options together in a list to provide a single access point for all code to use + * and to ensure that everything corresponding to the same NB type is grouped together. + * + * The Technology Block pointers are not included in this structure because DRAM technology + * needs to be decoupled from the northbridge type. + * + */ +typedef struct _MEM_NB_SUPPORT { + UINT16 MemNBSupportVersion; ///< Version of northbridge support. + MEM_NB_CONSTRUCTOR *MemConstructNBBlock; ///< NorthBridge block constructor. + MEM_INITIALIZER *MemNInitDefaults; ///< Default value initialization for MEM_DATA_STRUCT. + MEM_FEAT_BLOCK_NB *MemFeatBlock; ///< Memory feature block. + MEM_RESUME_CONSTRUCTOR *MemS3ResumeConstructNBBlock; ///< S3 memory initialization northbridge block constructor. + MEM_IDENDIMM_CONSTRUCTOR *MemIdentifyDimmConstruct; ///< Constructor for address to dimm identification. +} MEM_NB_SUPPORT; + +/* + * MEMORY Non-Training FEATURES - This structure serves as a vector table for standard + * memory non-training feature implementation functions. It contains vectors for all of the + * features that are supported by the various Technology devices supported by + * AGESA. + */ + +/** + * MAIN TRAINING SEQUENCE LIST - This structure serves as vector table for memory features + * that shared between all northbridge devices. + */ +typedef struct _MEM_FEAT_TRAIN_SEQ { + UINT16 OptMemTrainingSequenceListVersion; ///< Version of main feature block. + OPTION_MEM_FEATURE_NB *TrainingSequence; ///< Training Sequence function. + OPTION_MEM_FEATURE_NB *TrainingSequenceEnabled; ///< Enable function. + MEM_TECH_FEAT_BLOCK *MemTechFeatBlock; ///< Memory feature block. +} MEM_FEAT_TRAIN_SEQ; + +/** + * PLATFORM SPECIFIC CONFIGURATION BLOCK - This structure groups various PSC table + * entries which are used by PSC engine + */ +typedef struct _MEM_PSC_TABLE_BLOCK { + PSC_TBL_ENTRY **TblEntryOfMaxFreq; ///< Table entry of MaxFreq. + PSC_TBL_ENTRY **TblEntryOfDramTerm; ///< Table entry of Dram Term. + PSC_TBL_ENTRY **TblEntryOfODTPattern; ///< Table entry of ODT Pattern. + PSC_TBL_ENTRY **TblEntryOfSAO; ///< Table entry of Slow access mode, AddrTmg and ODC.. + PSC_TBL_ENTRY **TblEntryOfMR0WR; ///< Table entry of MR0[WR]. + PSC_TBL_ENTRY **TblEntryOfMR0CL; ///< Table entry of MR0[CL]. + PSC_TBL_ENTRY **TblEntryOfRC2IBT; ///< Table entry of RC2 IBT. + PSC_TBL_ENTRY **TblEntryOfRC10OpSpeed; ///< Table entry of RC10[operating speed]. + PSC_TBL_ENTRY **TblEntryOfLRIBT;///< Table entry of LRDIMM IBT + PSC_TBL_ENTRY **TblEntryOfLRNPR; ///< Table entry of LRDIMM F0RC13[NumPhysicalRanks]. + PSC_TBL_ENTRY **TblEntryOfLRNLR; ///< Table entry of LRDIMM F0RC13[NumLogicalRanks]. + PSC_TBL_ENTRY **TblEntryOfGen; ///< Table entry of CLKDis map and CKE, ODT as well as ChipSel tri-state map. + PSC_TBL_ENTRY **excel224; + PSC_TBL_ENTRY **TblEntryOfWLSeed; ///< Table entry of WL seed + PSC_TBL_ENTRY **TblEntryOfHWRxENSeed; ///< Table entry of HW RxEN seed +} MEM_PSC_TABLE_BLOCK; + +typedef BOOLEAN MEM_PSC_FLOW ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN MEM_PSC_TABLE_BLOCK *EntryOfTables + ); + +/** + * PLATFORM SPECIFIC CONFIGURATION FLOW BLOCK - Pointers to the sub-engines of platform + * specific configuration. + */ +typedef struct _MEM_PSC_FLOW_BLOCK { + MEM_PSC_TABLE_BLOCK *EntryOfTables; ///<Entry of NB specific MEM_PSC_TABLE_BLOCK + MEM_PSC_FLOW *MaxFrequency; ///< Sub-engine which performs "Max Frequency" value extraction. + MEM_PSC_FLOW *DramTerm; ///< Sub-engine which performs "Dram Term" value extraction. + MEM_PSC_FLOW *ODTPattern; ///< Sub-engine which performs "ODT Pattern" value extraction. + MEM_PSC_FLOW *SAO; ///< Sub-engine which performs "Slow access mode, AddrTmg and ODC" value extraction. + MEM_PSC_FLOW *MR0WrCL; ///< Sub-engine which performs "MR0[WR] and MR0[CL]" value extraction. + MEM_PSC_FLOW *RC2IBT; ///< Sub-engine "RC2 IBT" value extraction. + MEM_PSC_FLOW *RC10OpSpeed; ///< Sub-engine "RC10[operating speed]" value extraction. + MEM_PSC_FLOW *LRIBT; ///< Sub-engine "LRDIMM IBT" value extraction. + MEM_PSC_FLOW *LRNPR; ///< Sub-engine "LRDIMM F0RC13[NumPhysicalRanks]" value extraction. + MEM_PSC_FLOW *LRNLR; ///< Sub-engine "LRDIMM F0RC13[NumLogicalRanks]" value extraction. + MEM_PSC_FLOW *excel225; + MEM_PSC_FLOW *TrainingSeedVal; ///< Sub-engine for WL and HW RxEn pass1 seed value extraction +} MEM_PSC_FLOW_BLOCK; + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ +/* Feature Default Return */ +BOOLEAN MemFDefRet ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN MemMDefRet ( + IN MEM_MAIN_DATA_BLOCK *MMPtr + ); + +BOOLEAN MemMDefRetFalse ( + IN MEM_MAIN_DATA_BLOCK *MMPtr + ); + +/* Table Feature Default Return */ +UINT8 MemFTableDefRet ( + IN OUT MEM_TABLE_ALIAS **MTPtr + ); +/* S3 Feature Default Return */ +BOOLEAN MemFS3DefConstructorRet ( + IN OUT VOID *S3NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ); + +BOOLEAN MemNIdentifyDimmConstructorRetDef ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ); + +BOOLEAN +MemProcessConditionalOverrides ( + IN PSO_TABLE *PlatformMemoryConfiguration, + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 PsoAction, + IN UINT8 Dimm + ); + +#endif // _OPTION_MEMORY_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryInstall.h new file mode 100644 index 0000000..b8d82aa --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryInstall.h @@ -0,0 +1,4888 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: Memory + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 64574 $ @e $Date: 2012-01-25 01:01:51 -0600 (Wed, 25 Jan 2012) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_MEMORY_INSTALL_H_ +#define _OPTION_MEMORY_INSTALL_H_ + +/* Memory Includes */ +#include "OptionMemory.h" + +/*------------------------------------------------------------------------------- + * This option file is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ + +/*---------------------------------------------------------------------------------- + * FEATURE BLOCK FUNCTIONS + * + * This section defines function names that depend upon options that are selected + * in the platform solution install file. + */ +BOOLEAN MemFDefRet ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + return FALSE; +} + +BOOLEAN MemMDefRet ( + IN MEM_MAIN_DATA_BLOCK *MMPtr + ) +{ + return TRUE; +} + +BOOLEAN MemMDefRetFalse ( + IN MEM_MAIN_DATA_BLOCK *MMPtr + ) +{ + return FALSE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block for dimm identification translator + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in,out] NodeID - ID of current node to construct + * @return TRUE - This is the correct constructor for the targeted node. + * @return FALSE - This isn't the correct constructor for the targeted node. + */ +BOOLEAN MemNIdentifyDimmConstructorRetDef ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + return FALSE; +} +/*---------------------------------------------------------------------------------- + * TABLE FEATURE BLOCK FUNCTIONS + * + * This section defines function names that depend upon options that are selected + * in the platform solution install file. + */ +UINT8 MemFTableDefRet ( + IN OUT MEM_TABLE_ALIAS **MTPtr + ) +{ + return 0; +} +/*---------------------------------------------------------------------------------- + * FEATURE S3 BLOCK FUNCTIONS + * + * This section defines function names that depend upon options that are selected + * in the platform solution install file. + */ +BOOLEAN MemFS3DefConstructorRet ( + IN OUT VOID *S3NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + return TRUE; +} + +#if (OPTION_MEMCTLR_DR == TRUE) + #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) + #if (OPTION_S3_MEM_SUPPORT == TRUE) + extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDr; + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemS3ResumeConstructNBBlockDr + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet + #endif + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet + #endif + #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) + extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDr; + #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorDr + #else + #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorRetDef + #endif +#endif + +#if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE) + #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) + #if (OPTION_S3_MEM_SUPPORT == TRUE) + #if (OPTION_MEMCTLR_Ni == TRUE) + extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockNi; + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemS3ResumeConstructNBBlockNi + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemFS3DefConstructorRet + #endif + #if (OPTION_MEMCTLR_DA == TRUE) + extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDA; + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemS3ResumeConstructNBBlockDA + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet + #endif + #if (OPTION_MEMCTLR_PH == TRUE) + extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockPh; + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemS3ResumeConstructNBBlockPh + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemFS3DefConstructorRet + #endif + #if (OPTION_MEMCTLR_RB == TRUE) + extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockRb; + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemS3ResumeConstructNBBlockRb + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemFS3DefConstructorRet + #endif + #endif + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemFS3DefConstructorRet + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemFS3DefConstructorRet + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemFS3DefConstructorRet + #endif + #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) + extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDA; + #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorDA + extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorRb; + #define MEM_IDENDIMM_RB MemNIdentifyDimmConstructorRb + extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorPh; + #define MEM_IDENDIMM_PH MemNIdentifyDimmConstructorPh + #else + #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorRetDef + #define MEM_IDENDIMM_RB MemNIdentifyDimmConstructorRetDef + #define MEM_IDENDIMM_PH MemNIdentifyDimmConstructorRetDef + #endif +#endif + +#if (OPTION_MEMCTLR_OR == TRUE) + #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) + #if (OPTION_S3_MEM_SUPPORT == TRUE) + extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockOr; + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemS3ResumeConstructNBBlockOr + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet + #endif + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet + #endif + #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) + extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorOr; + #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorOr + #else + #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorRetDef + #endif +#endif + +#if (OPTION_MEMCTLR_HY == TRUE) + #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) + #if (OPTION_S3_MEM_SUPPORT == TRUE) + extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockHy; + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemS3ResumeConstructNBBlockHy + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet + #endif + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet + #endif + #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) + extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorHy; + #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorHy + #else + #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorRetDef + #endif +#endif + +#if (OPTION_MEMCTLR_C32 == TRUE) + #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) + #if (OPTION_S3_MEM_SUPPORT == TRUE) + extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockC32; + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemS3ResumeConstructNBBlockC32 + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet + #endif + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet + #endif + #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) + extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorC32; + #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorC32 + #else + #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorRetDef + #endif +#endif + +#if (OPTION_MEMCTLR_LN == TRUE) + #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) + #if (OPTION_S3_MEM_SUPPORT == TRUE) + extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockLN; + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemS3ResumeConstructNBBlockLN + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemFS3DefConstructorRet + #endif + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemFS3DefConstructorRet + #endif + #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) + extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorLN; + #define MEM_IDENDIMM_LN MemNIdentifyDimmConstructorLN + #else + #define MEM_IDENDIMM_LN MemNIdentifyDimmConstructorRetDef + #endif +#endif + +#if (OPTION_MEMCTLR_ON == TRUE) + #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) + #if (OPTION_S3_MEM_SUPPORT == TRUE) + extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockON; + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemS3ResumeConstructNBBlockON + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemFS3DefConstructorRet + #endif + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemFS3DefConstructorRet + #endif + #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) + extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorON; + #define MEM_IDENDIMM_ON MemNIdentifyDimmConstructorON + #else + #define MEM_IDENDIMM_ON MemNIdentifyDimmConstructorRetDef + #endif +#endif + +#if (OPTION_MEMCTLR_TN == TRUE) + #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) + #if (OPTION_S3_MEM_SUPPORT == TRUE) + extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockTN; + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_TN MemS3ResumeConstructNBBlockTN + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_TN MemFS3DefConstructorRet + #endif + #else + #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_TN MemFS3DefConstructorRet + #endif + #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) + extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorTN; + #define MEM_IDENDIMM_TN MemNIdentifyDimmConstructorTN + #else + #define MEM_IDENDIMM_TN MemNIdentifyDimmConstructorRetDef + #endif +#endif + + + + +/*---------------------------------------------------------------------------------- + * NORTHBRIDGE BLOCK CONSTRUCTOR AND INITIALIZER FUNCTION DEFAULT ASSIGNMENTS + * + *---------------------------------------------------------------------------------- +*/ +#define MEM_NB_SUPPORT_DR +#define MEM_NB_SUPPORT_RB +#define MEM_NB_SUPPORT_DA +#define MEM_NB_SUPPORT_Ni +#define MEM_NB_SUPPORT_PH +#define MEM_NB_SUPPORT_HY +#define MEM_NB_SUPPORT_LN +#define MEM_NB_SUPPORT_OR +#define MEM_NB_SUPPORT_C32 +#define MEM_NB_SUPPORT_ON +#define MEM_NB_SUPPORT_TN +#define MEM_NB_SUPPORT_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0, 0, 0 } + +#if (AGESA_ENTRY_INIT_POST == TRUE) + /*---------------------------------------------------------------------------------- + * FLOW CONTROL FUNCTION + * + * This section selects the function that controls the memory initialization sequence + * based upon the number of processor families that the BIOS will support. + */ + extern MEM_FLOW_CFG MemMFlowDef; + + #if (OPTION_MEMCTLR_DR == TRUE) + extern MEM_FLOW_CFG MemMFlowDr; + #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDr, + #else + #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDef, + #endif + #if (OPTION_MEMCTLR_DA == TRUE) + extern MEM_FLOW_CFG MemMFlowDA; + #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDA, + #else + #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDef, + #endif + #if (OPTION_MEMCTLR_HY == TRUE) + extern MEM_FLOW_CFG MemMFlowHy; + #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowHy, + #else + #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowDef, + #endif + #if (OPTION_MEMCTLR_OR == TRUE) + extern MEM_FLOW_CFG MemMFlowOr; + #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowOr, + #else + #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowDef, + #endif + #if (OPTION_MEMCTLR_LN == TRUE) + extern MEM_FLOW_CFG MemMFlowLN; + #define MEM_MAIN_FLOW_CONTROL_PTR_LN MemMFlowLN, + #else + #define MEM_MAIN_FLOW_CONTROL_PTR_LN MemMFlowDef, + #endif + #if (OPTION_MEMCTLR_C32 == TRUE) + extern MEM_FLOW_CFG MemMFlowC32; + #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowC32, + #else + #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowDef, + #endif + #if (OPTION_MEMCTLR_ON == TRUE) + extern MEM_FLOW_CFG MemMFlowON; + #define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowON, + #else + #define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowDef, + #endif + #if (OPTION_MEMCTLR_Ni == TRUE) + extern MEM_FLOW_CFG MemMFlowDA; + #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDA, + #else + #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDef, + #endif + #if (OPTION_MEMCTLR_RB == TRUE) + extern MEM_FLOW_CFG MemMFlowRb; + #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowRb, + #else + #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowDef, + #endif + #if (OPTION_MEMCTLR_PH == TRUE) + extern MEM_FLOW_CFG MemMFlowPh; + #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowPh, + #else + #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowDef, + #endif + #if (OPTION_MEMCTLR_TN == TRUE) + extern MEM_FLOW_CFG MemMFlowTN; + #define MEM_MAIN_FLOW_CONTROL_PTR_TN MemMFlowTN, + #else + #define MEM_MAIN_FLOW_CONTROL_PTR_TN MemMFlowDef, + #endif + + MEM_FLOW_CFG* memFlowControlInstalled[] = { + MEM_MAIN_FLOW_CONTROL_PTR_Dr + MEM_MAIN_FLOW_CONTROL_PTR_DA + MEM_MAIN_FLOW_CONTROL_PTR_RB + MEM_MAIN_FLOW_CONTROL_PTR_PH + MEM_MAIN_FLOW_CONTROL_PTR_Hy + MEM_MAIN_FLOW_CONTROL_PTR_OR + MEM_MAIN_FLOW_CONTROL_PTR_LN + MEM_MAIN_FLOW_CONTROL_PTR_C32 + MEM_MAIN_FLOW_CONTROL_PTR_ON + MemMFlowDef, + MEM_MAIN_FLOW_CONTROL_PTR_Ni + MEM_MAIN_FLOW_CONTROL_PTR_TN + MemMFlowDef, + MemMFlowDef, + NULL + }; + + #if (OPTION_ONLINE_SPARE == TRUE) + extern OPTION_MEM_FEATURE_MAIN MemMOnlineSpare; + #define MEM_MAIN_FEATURE_ONLINE_SPARE MemMOnlineSpare + extern OPTION_MEM_FEATURE_NB MemFOnlineSpare; + #define MEM_FEATURE_ONLINE_SPARE MemFOnlineSpare + #else + #define MEM_MAIN_FEATURE_ONLINE_SPARE MemMDefRet + #define MEM_FEATURE_ONLINE_SPARE MemFDefRet + #endif + + #if (OPTION_MEM_RESTORE == TRUE) + extern OPTION_MEM_FEATURE_MAIN MemMContextSave; + extern OPTION_MEM_FEATURE_MAIN MemMContextRestore; + #define MEM_MAIN_FEATURE_MEM_SAVE MemMContextSave + #define MEM_MAIN_FEATURE_MEM_RESTORE MemMContextRestore + #else + #define MEM_MAIN_FEATURE_MEM_SAVE MemMDefRet + #define MEM_MAIN_FEATURE_MEM_RESTORE MemMDefRetFalse + #endif + + #if (OPTION_BANK_INTERLEAVE == TRUE) + extern OPTION_MEM_FEATURE_NB MemFInterleaveBanks; + #define MEM_FEATURE_BANK_INTERLEAVE MemFInterleaveBanks + extern OPTION_MEM_FEATURE_NB MemFUndoInterleaveBanks; + #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFUndoInterleaveBanks + #else + #define MEM_FEATURE_BANK_INTERLEAVE MemFDefRet + #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFDefRet + #endif + + #if (OPTION_NODE_INTERLEAVE == TRUE) + extern OPTION_MEM_FEATURE_MAIN MemMInterleaveNodes; + #define MEM_MAIN_FEATURE_NODE_INTERLEAVE MemMInterleaveNodes + extern OPTION_MEM_FEATURE_NB MemFCheckInterleaveNodes; + extern OPTION_MEM_FEATURE_NB MemFInterleaveNodes; + #define MEM_FEATURE_NODE_INTERLEAVE_CHECK MemFCheckInterleaveNodes + #define MEM_FEATURE_NODE_INTERLEAVE MemFInterleaveNodes + #else + #define MEM_FEATURE_NODE_INTERLEAVE_CHECK MemFDefRet + #define MEM_FEATURE_NODE_INTERLEAVE MemFDefRet + #define MEM_MAIN_FEATURE_NODE_INTERLEAVE MemMDefRet + #endif + + #if (OPTION_DCT_INTERLEAVE == TRUE) + extern OPTION_MEM_FEATURE_NB MemFInterleaveChannels; + #define MEM_FEATURE_CHANNEL_INTERLEAVE MemFInterleaveChannels + #else + #define MEM_FEATURE_CHANNEL_INTERLEAVE MemFDefRet + #endif + + #if (OPTION_ECC == TRUE) + extern OPTION_MEM_FEATURE_MAIN MemMEcc; + #define MEM_MAIN_FEATURE_ECC MemMEcc + extern OPTION_MEM_FEATURE_NB MemFCheckECC; + extern OPTION_MEM_FEATURE_NB MemFInitECC; + #define MEM_FEATURE_CK_ECC MemFCheckECC + #define MEM_FEATURE_ECC MemFInitECC + #define MEM_FEATURE_ECCX8 MemMDefRet + #else + #define MEM_MAIN_FEATURE_ECC MemMDefRet + #define MEM_FEATURE_CK_ECC MemFDefRet + #define MEM_FEATURE_ECC MemFDefRet + #define MEM_FEATURE_ECCX8 MemMDefRet + #endif + + + extern OPTION_MEM_FEATURE_MAIN MemMMctMemClr; + #define MEM_MAIN_FEATURE_MEM_CLEAR MemMMctMemClr + + #if (OPTION_DMI == TRUE) + #if (OPTION_DDR3 == TRUE) + extern OPTION_MEM_FEATURE_MAIN MemFDMISupport3; + #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport3 + #else + extern OPTION_MEM_FEATURE_MAIN MemFDMISupport2; + #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport2 + #endif + #else + #define MEM_MAIN_FEATURE_MEM_DMI MemMDefRet + #endif + + + #if (OPTION_DDR3 == TRUE) + extern OPTION_MEM_FEATURE_NB MemFOnDimmThermal; + extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3; + extern OPTION_MEM_FEATURE_NB MemFLvDdr3; + #define MEM_FEATURE_ONDIMMTHERMAL MemFOnDimmThermal + #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3 + #define MEM_FEATURE_LVDDR3 MemFLvDdr3 + #else + #define MEM_FEATURE_ONDIMMTHERMAL MemFDefRet + #define MEM_MAIN_FEATURE_LVDDR3 MemMDefRet + #define MEM_FEATURE_LVDDR3 MemFDefRet + #endif + + extern OPTION_MEM_FEATURE_NB MemFInterleaveRegion; + #define MEM_FEATURE_REGION_INTERLEAVE MemFInterleaveRegion + + extern OPTION_MEM_FEATURE_MAIN MemMUmaAlloc; + #define MEM_MAIN_FEATURE_UMAALLOC MemMUmaAlloc + + #if (OPTION_PARALLEL_TRAINING == TRUE) + extern OPTION_MEM_FEATURE_MAIN MemMParallelTraining; + #define MEM_MAIN_FEATURE_TRAINING MemMParallelTraining + #else + extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; + #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining + #endif + + #if (OPTION_DIMM_EXCLUDE == TRUE) + extern OPTION_MEM_FEATURE_MAIN MemMRASExcludeDIMM; + #define MEM_MAIN_FEATURE_DIMM_EXCLUDE MemMRASExcludeDIMM + extern OPTION_MEM_FEATURE_NB MemFRASExcludeDIMM; + #define MEM_FEATURE_DIMM_EXCLUDE MemFRASExcludeDIMM + #else + #define MEM_FEATURE_DIMM_EXCLUDE MemFDefRet + #define MEM_MAIN_FEATURE_DIMM_EXCLUDE MemMDefRet + #endif + + /*---------------------------------------------------------------------------------- + * TECHNOLOGY BLOCK CONSTRUCTOR FUNCTION ASSIGNMENTS + * + *---------------------------------------------------------------------------------- + */ + #if OPTION_DDR2 == TRUE + extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock2; + #define MEM_TECH_CONSTRUCTOR_DDR2 MemConstructTechBlock2, + #if (OPTION_HW_DRAM_INIT == TRUE) + extern MEM_TECH_FEAT MemTDramInitHw; + #define MEM_TECH_FEATURE_HW_DRAMINIT MemTDramInitHw + #else + #define MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef + #endif + #if (OPTION_SW_DRAM_INIT == TRUE) + #define MEM_TECH_FEATURE_SW_DRAMINIT MemTFeatDef + #else + #define MEM_TECH_FEATURE_SW_DRAMINIT MemTFeatDef + #endif + #else + #define MEM_TECH_CONSTRUCTOR_DDR2 + #endif + #if OPTION_DDR3 == TRUE + extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock3; + #define MEM_TECH_CONSTRUCTOR_DDR3 MemConstructTechBlock3, + #if (OPTION_HW_DRAM_INIT == TRUE) + extern MEM_TECH_FEAT MemTDramInitHw; + #define MEM_TECH_FEATURE_HW_DRAMINIT MemTDramInitHw + #else + #define MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef + #endif + #if (OPTION_SW_DRAM_INIT == TRUE) + #define MEM_TECH_FEATURE_SW_DRAMINIT MemTDramInitSw3 + #else + #define MEM_TECH_FEATURE_SW_DRAMINIT MemTFeatDef + #endif + #else + #define MEM_TECH_CONSTRUCTOR_DDR3 + #endif + + /*--------------------------------------------------------------------------------------------------- + * FEATURE BLOCKS + * + * This section instantiates a feature block structure for each memory controller installed + * by the platform solution install file. + *--------------------------------------------------------------------------------------------------- + */ + + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb; + #endif + extern OPTION_MEM_FEATURE_NB MemFStandardTraining; + + /*--------------------------------------------------------------------------------------------------- + * DEERHOUND FEATURE BLOCK + *--------------------------------------------------------------------------------------------------- + */ + #if (OPTION_MEMCTLR_DR == TRUE) + #if OPTION_DDR2 + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT + #endif + #if OPTION_DDR3 + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT + #endif + + #undef MEM_TECH_FEATURE_CPG + #define MEM_TECH_FEATURE_CPG MemFDefRet + + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #undef MEM_TECH_FEATURE_HWRXEN + #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb + #else + extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; + #undef MEM_TECH_FEATURE_HWRXEN + #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb + #endif + + #undef MEM_MAIN_FEATURE_TRAINING + #undef MEM_FEATURE_TRAINING + extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; + #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining + #define MEM_FEATURE_TRAINING MemFStandardTraining + + MEM_FEAT_BLOCK_NB MemFeatBlockDr = { + MEM_FEAT_BLOCK_NB_STRUCT_VERSION, + MEM_FEATURE_ONLINE_SPARE, + MEM_FEATURE_BANK_INTERLEAVE, + MEM_FEATURE_UNDO_BANK_INTERLEAVE, + MEM_FEATURE_NODE_INTERLEAVE_CHECK, + MEM_FEATURE_NODE_INTERLEAVE, + MEM_FEATURE_CHANNEL_INTERLEAVE, + MemFDefRet, + MEM_FEATURE_CK_ECC, + MEM_FEATURE_ECC, + MEM_FEATURE_TRAINING, + MEM_FEATURE_LVDDR3, + MemFDefRet, + MEM_TECH_FEATURE_DRAMINIT, + MEM_FEATURE_DIMM_EXCLUDE, + MemFDefRet, + MEM_TECH_FEATURE_CPG, + MEM_TECH_FEATURE_HWRXEN + }; + + #undef MEM_NB_SUPPORT_DR + extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDR; + extern MEM_INITIALIZER MemNInitDefaultsDR; + + + #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDR, MemNInitDefaultsDR, &MemFeatBlockDr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR }, + #endif // OPTION_MEMCTRL_DR + + /*--------------------------------------------------------------------------------------------------- + * DASHOUND FEATURE BLOCK + *--------------------------------------------------------------------------------------------------- + */ + #if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE) + #if OPTION_DDR2 + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT + #endif + #if OPTION_DDR3 + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT + #endif + + #undef MEM_TECH_FEATURE_CPG + #define MEM_TECH_FEATURE_CPG MemFDefRet + + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #undef MEM_TECH_FEATURE_HWRXEN + #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb + #else + extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; + #undef MEM_TECH_FEATURE_HWRXEN + #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb + #endif + + #undef MEM_MAIN_FEATURE_TRAINING + #undef MEM_FEATURE_TRAINING + extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; + #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining + #define MEM_FEATURE_TRAINING MemFStandardTraining + + #if (OPTION_MEMCTLR_Ni == TRUE) + MEM_FEAT_BLOCK_NB MemFeatBlockNi = { + MEM_FEAT_BLOCK_NB_STRUCT_VERSION, + MemFDefRet, + MEM_FEATURE_BANK_INTERLEAVE, + MEM_FEATURE_UNDO_BANK_INTERLEAVE, + MemFDefRet, + MemFDefRet, + MEM_FEATURE_CHANNEL_INTERLEAVE, + MEM_FEATURE_REGION_INTERLEAVE, + MEM_FEATURE_CK_ECC, + MEM_FEATURE_ECC, + MEM_FEATURE_TRAINING, + MEM_FEATURE_LVDDR3, + MemFDefRet, + MEM_TECH_FEATURE_DRAMINIT, + MEM_FEATURE_DIMM_EXCLUDE, + MemFDefRet, + MEM_TECH_FEATURE_CPG, + MEM_TECH_FEATURE_HWRXEN + }; + + #undef MEM_NB_SUPPORT_Ni + extern MEM_NB_CONSTRUCTOR MemConstructNBBlockNi; + extern MEM_INITIALIZER MemNInitDefaultsNi; + + #define MEM_NB_SUPPORT_Ni { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockNi, MemNInitDefaultsNi, &MemFeatBlockNi, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni, MEM_IDENDIMM_DA }, + #endif + + #if (OPTION_MEMCTLR_PH == TRUE) + MEM_FEAT_BLOCK_NB MemFeatBlockPh = { + MEM_FEAT_BLOCK_NB_STRUCT_VERSION, + MemFDefRet, + MEM_FEATURE_BANK_INTERLEAVE, + MEM_FEATURE_UNDO_BANK_INTERLEAVE, + MemFDefRet, + MemFDefRet, + MEM_FEATURE_CHANNEL_INTERLEAVE, + MEM_FEATURE_REGION_INTERLEAVE, + MEM_FEATURE_CK_ECC, + MEM_FEATURE_ECC, + MEM_FEATURE_TRAINING, + MEM_FEATURE_LVDDR3, + MemFDefRet, + MEM_TECH_FEATURE_DRAMINIT, + MEM_FEATURE_DIMM_EXCLUDE, + MemFDefRet, + MEM_TECH_FEATURE_CPG, + MEM_TECH_FEATURE_HWRXEN + }; + + #undef MEM_NB_SUPPORT_PH + extern MEM_NB_CONSTRUCTOR MemConstructNBBlockPh; + extern MEM_INITIALIZER MemNInitDefaultsPh; + + #define MEM_NB_SUPPORT_PH { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockPh, MemNInitDefaultsPh, &MemFeatBlockPh, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH, MEM_IDENDIMM_PH }, + #endif + + #if (OPTION_MEMCTLR_RB == TRUE) + MEM_FEAT_BLOCK_NB MemFeatBlockRb = { + MEM_FEAT_BLOCK_NB_STRUCT_VERSION, + MemFDefRet, + MEM_FEATURE_BANK_INTERLEAVE, + MEM_FEATURE_UNDO_BANK_INTERLEAVE, + MemFDefRet, + MemFDefRet, + MEM_FEATURE_CHANNEL_INTERLEAVE, + MEM_FEATURE_REGION_INTERLEAVE, + MEM_FEATURE_CK_ECC, + MEM_FEATURE_ECC, + MEM_FEATURE_TRAINING, + MEM_FEATURE_LVDDR3, + MemFDefRet, + MEM_TECH_FEATURE_DRAMINIT, + MEM_FEATURE_DIMM_EXCLUDE, + MemFDefRet, + MEM_TECH_FEATURE_CPG, + MEM_TECH_FEATURE_HWRXEN + }; + + #undef MEM_NB_SUPPORT_RB + extern MEM_NB_CONSTRUCTOR MemConstructNBBlockRb; + extern MEM_INITIALIZER MemNInitDefaultsRb; + + #define MEM_NB_SUPPORT_RB { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockRb, MemNInitDefaultsRb, &MemFeatBlockRb, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB, MEM_IDENDIMM_RB }, + #endif + + #if (OPTION_MEMCTLR_DA == TRUE) + MEM_FEAT_BLOCK_NB MemFeatBlockDA = { + MEM_FEAT_BLOCK_NB_STRUCT_VERSION, + MemFDefRet, + MEM_FEATURE_BANK_INTERLEAVE, + MEM_FEATURE_UNDO_BANK_INTERLEAVE, + MemFDefRet, + MemFDefRet, + MEM_FEATURE_CHANNEL_INTERLEAVE, + MEM_FEATURE_REGION_INTERLEAVE, + MEM_FEATURE_CK_ECC, + MEM_FEATURE_ECC, + MEM_FEATURE_TRAINING, + MEM_FEATURE_LVDDR3, + MemFDefRet, + MEM_TECH_FEATURE_DRAMINIT, + MEM_FEATURE_DIMM_EXCLUDE, + MemFDefRet, + MEM_TECH_FEATURE_CPG, + MEM_TECH_FEATURE_HWRXEN + }; + + #undef MEM_NB_SUPPORT_DA + extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDA; + extern MEM_INITIALIZER MemNInitDefaultsDA; + + #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDA, MemNInitDefaultsDA, &MemFeatBlockDA, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA }, + #endif + #endif // OPTION_MEMCTRL_DA + + /*--------------------------------------------------------------------------------------------------- + * HYDRA FEATURE BLOCK + *--------------------------------------------------------------------------------------------------- + */ + #if (OPTION_MEMCTLR_HY == TRUE) + #if OPTION_DDR2 + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT + #endif + #if OPTION_DDR3 + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT + #endif + + #undef MEM_TECH_FEATURE_CPG + #define MEM_TECH_FEATURE_CPG MemFDefRet + + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #undef MEM_TECH_FEATURE_HWRXEN + #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb + #else + extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; + #undef MEM_TECH_FEATURE_HWRXEN + #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb + #endif + + + #undef MEM_MAIN_FEATURE_TRAINING + #undef MEM_FEATURE_TRAINING + extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; + #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining + #define MEM_FEATURE_TRAINING MemFStandardTraining + + MEM_FEAT_BLOCK_NB MemFeatBlockHy = { + MEM_FEAT_BLOCK_NB_STRUCT_VERSION, + MEM_FEATURE_ONLINE_SPARE, + MEM_FEATURE_BANK_INTERLEAVE, + MEM_FEATURE_UNDO_BANK_INTERLEAVE, + MEM_FEATURE_NODE_INTERLEAVE_CHECK, + MEM_FEATURE_NODE_INTERLEAVE, + MEM_FEATURE_CHANNEL_INTERLEAVE, + MemFDefRet, + MEM_FEATURE_CK_ECC, + MEM_FEATURE_ECC, + MEM_FEATURE_TRAINING, + MEM_FEATURE_LVDDR3, + MEM_FEATURE_ONDIMMTHERMAL, + MEM_TECH_FEATURE_DRAMINIT, + MEM_FEATURE_DIMM_EXCLUDE, + MemFDefRet, + MEM_TECH_FEATURE_CPG, + MEM_TECH_FEATURE_HWRXEN + }; + + #undef MEM_NB_SUPPORT_HY + extern MEM_NB_CONSTRUCTOR MemConstructNBBlockHY; + extern MEM_INITIALIZER MemNInitDefaultsHY; + #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockHY, MemNInitDefaultsHY, &MemFeatBlockHy, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY }, + #endif // OPTION_MEMCTRL_HY + /*--------------------------------------------------------------------------------------------------- + * LLANO FEATURE BLOCK + *--------------------------------------------------------------------------------------------------- + */ + #if (OPTION_MEMCTLR_LN == TRUE) + #if OPTION_DDR2 + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT + #endif + #if OPTION_DDR3 + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT + #endif + + #if (OPTION_EARLY_SAMPLES == TRUE) + extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportLN; + #define MEM_EARLY_SAMPLE_SUPPORT MemNInitEarlySampleSupportLN + #else + #define MEM_EARLY_SAMPLE_SUPPORT MemFDefRet + #endif + + #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE) + extern OPTION_MEM_FEATURE_NB MemNInitCPGClientNb; + #undef MEM_TECH_FEATURE_CPG + #define MEM_TECH_FEATURE_CPG MemNInitCPGClientNb + #else + #undef MEM_TECH_FEATURE_CPG + #define MEM_TECH_FEATURE_CPG MemFDefRet + #endif + + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #undef MEM_TECH_FEATURE_HWRXEN + #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb + #else + extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; + #undef MEM_TECH_FEATURE_HWRXEN + #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb + #endif + + #undef MEM_MAIN_FEATURE_TRAINING + #undef MEM_FEATURE_TRAINING + extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; + #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining + #define MEM_FEATURE_TRAINING MemFStandardTraining + + MEM_FEAT_BLOCK_NB MemFeatBlockLn = { + MEM_FEAT_BLOCK_NB_STRUCT_VERSION, + MemFDefRet, + MEM_FEATURE_BANK_INTERLEAVE, + MEM_FEATURE_UNDO_BANK_INTERLEAVE, + MemFDefRet, + MemFDefRet, + MEM_FEATURE_CHANNEL_INTERLEAVE, + MEM_FEATURE_REGION_INTERLEAVE, + MEM_FEATURE_CK_ECC, + MemFDefRet, + MEM_FEATURE_TRAINING, + MEM_FEATURE_LVDDR3, + MEM_FEATURE_ONDIMMTHERMAL, + MEM_TECH_FEATURE_DRAMINIT, + MEM_FEATURE_DIMM_EXCLUDE, + MEM_EARLY_SAMPLE_SUPPORT, + MEM_TECH_FEATURE_CPG, + MEM_TECH_FEATURE_HWRXEN + }; + #undef MEM_NB_SUPPORT_LN + extern MEM_NB_CONSTRUCTOR MemConstructNBBlockLN; + extern MEM_INITIALIZER MemNInitDefaultsLN; + #define MEM_NB_SUPPORT_LN { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockLN, MemNInitDefaultsLN, &MemFeatBlockLn, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN, MEM_IDENDIMM_LN }, + + #endif // OPTION_MEMCTRL_LN + + /*--------------------------------------------------------------------------------------------------- + * ONTARIO FEATURE BLOCK + *--------------------------------------------------------------------------------------------------- + */ + #if (OPTION_MEMCTLR_ON == TRUE) + #if OPTION_DDR2 + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT + #endif + #if OPTION_DDR3 + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT + #endif + + #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE) + extern OPTION_MEM_FEATURE_NB MemNInitCPGClientNb; + #undef MEM_TECH_FEATURE_CPG + #define MEM_TECH_FEATURE_CPG MemNInitCPGClientNb + #else + #undef MEM_TECH_FEATURE_CPG + #define MEM_TECH_FEATURE_CPG MemFDefRet + #endif + + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #undef MEM_TECH_FEATURE_HWRXEN + #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb + #else + extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; + #undef MEM_TECH_FEATURE_HWRXEN + #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb + #endif + + #undef MEM_MAIN_FEATURE_TRAINING + #undef MEM_FEATURE_TRAINING + extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; + #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining + #define MEM_FEATURE_TRAINING MemFStandardTraining + + #if (OPTION_EARLY_SAMPLES == TRUE) + extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportON; + #define MEM_EARLY_SAMPLE_SUPPORT MemNInitEarlySampleSupportON + #else + #define MEM_EARLY_SAMPLE_SUPPORT MemFDefRet + #endif + + MEM_FEAT_BLOCK_NB MemFeatBlockOn = { + MEM_FEAT_BLOCK_NB_STRUCT_VERSION, + MemFDefRet, + MEM_FEATURE_BANK_INTERLEAVE, + MEM_FEATURE_UNDO_BANK_INTERLEAVE, + MemFDefRet, + MemFDefRet, + MemFDefRet, + MemFDefRet, + MemFDefRet, + MemFDefRet, + MEM_FEATURE_TRAINING, + MEM_FEATURE_LVDDR3, + MEM_FEATURE_ONDIMMTHERMAL, + MEM_TECH_FEATURE_DRAMINIT, + MEM_FEATURE_DIMM_EXCLUDE, + MEM_EARLY_SAMPLE_SUPPORT, + MEM_TECH_FEATURE_CPG, + MEM_TECH_FEATURE_HWRXEN + }; + + #undef MEM_NB_SUPPORT_ON + extern MEM_NB_CONSTRUCTOR MemConstructNBBlockON; + extern MEM_INITIALIZER MemNInitDefaultsON; + #define MEM_NB_SUPPORT_ON { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockON, MemNInitDefaultsON, &MemFeatBlockOn, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON, MEM_IDENDIMM_ON }, + + #endif // OPTION_MEMCTRL_ON + + + + /*--------------------------------------------------------------------------------------------------- + * OROCHI FEATURE BLOCK + *--------------------------------------------------------------------------------------------------- + */ + #if (OPTION_MEMCTLR_OR == TRUE) + #if OPTION_DDR2 + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT + #endif + #if OPTION_DDR3 + #undef MEM_MAIN_FEATURE_LVDDR3 + extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3PerformanceEnhPre; + #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3PerformanceEnhPre + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT + #endif + + #if (OPTION_G34_SOCKET_SUPPORT || OPTION_C32_SOCKET_SUPPORT) + #undef MEM_FEATURE_REGION_INTERLEAVE + #define MEM_FEATURE_REGION_INTERLEAVE MemFDefRet + #endif + + #if (OPTION_EARLY_SAMPLES == TRUE) + extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportOr; + #define MEM_EARLY_SAMPLE_SUPPORT MemNInitEarlySampleSupportOr + #else + #define MEM_EARLY_SAMPLE_SUPPORT MemFDefRet + #endif + + #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE) + extern OPTION_MEM_FEATURE_NB MemNInitCPGUnb; + #undef MEM_TECH_FEATURE_CPG + #define MEM_TECH_FEATURE_CPG MemNInitCPGUnb + #else + #undef MEM_TECH_FEATURE_CPG + #define MEM_TECH_FEATURE_CPG MemFDefRet + #endif + + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #undef MEM_TECH_FEATURE_HWRXEN + #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb + #else + extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; + #undef MEM_TECH_FEATURE_HWRXEN + #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb + #endif + + + #undef MEM_MAIN_FEATURE_TRAINING + #undef MEM_FEATURE_TRAINING + #if (OPTION_RDDQS_2D_TRAINING == TRUE) + extern OPTION_MEM_FEATURE_MAIN MemMStandardTrainingUsingAdjacentDies; + #define MEM_MAIN_FEATURE_TRAINING MemMStandardTrainingUsingAdjacentDies + #else + extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; + #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining + #endif + #define MEM_FEATURE_TRAINING MemFStandardTraining + + MEM_FEAT_BLOCK_NB MemFeatBlockOr = { + MEM_FEAT_BLOCK_NB_STRUCT_VERSION, + MEM_FEATURE_ONLINE_SPARE, + MEM_FEATURE_BANK_INTERLEAVE, + MEM_FEATURE_UNDO_BANK_INTERLEAVE, + MEM_FEATURE_NODE_INTERLEAVE_CHECK, + MEM_FEATURE_NODE_INTERLEAVE, + MEM_FEATURE_CHANNEL_INTERLEAVE, + MEM_FEATURE_REGION_INTERLEAVE, + MEM_FEATURE_CK_ECC, + MEM_FEATURE_ECC, + MEM_FEATURE_TRAINING, + MEM_FEATURE_LVDDR3, + MEM_FEATURE_ONDIMMTHERMAL, + MEM_TECH_FEATURE_DRAMINIT, + MEM_FEATURE_DIMM_EXCLUDE, + MEM_EARLY_SAMPLE_SUPPORT, + MEM_TECH_FEATURE_CPG, + MEM_TECH_FEATURE_HWRXEN + }; + + #undef MEM_NB_SUPPORT_OR + extern MEM_NB_CONSTRUCTOR MemConstructNBBlockOR; + extern MEM_INITIALIZER MemNInitDefaultsOR; + #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockOR, MemNInitDefaultsOR, &MemFeatBlockOr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR }, + #endif // OPTION_MEMCTRL_OR + + /*--------------------------------------------------------------------------------------------------- + * C32 FEATURE BLOCK + *--------------------------------------------------------------------------------------------------- + */ + #if (OPTION_MEMCTLR_C32 == TRUE) + #if OPTION_DDR2 + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT + #endif + #if OPTION_DDR3 + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT + #endif + + #undef MEM_TECH_FEATURE_CPG + #define MEM_TECH_FEATURE_CPG MemFDefRet + + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #undef MEM_TECH_FEATURE_HWRXEN + #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb + #else + extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; + #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb + #endif + + #undef MEM_MAIN_FEATURE_TRAINING + #undef MEM_FEATURE_TRAINING + #if (OPTION_MEMCTLR_OR == TRUE) + #if (OPTION_RDDQS_2D_TRAINING == TRUE) + extern OPTION_MEM_FEATURE_MAIN MemMStandardTrainingUsingAdjacentDies; + #define MEM_MAIN_FEATURE_TRAINING MemMStandardTrainingUsingAdjacentDies + #else + extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; + #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining + #endif + #else + extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; + #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining + #endif + #define MEM_FEATURE_TRAINING MemFStandardTraining + + MEM_FEAT_BLOCK_NB MemFeatBlockC32 = { + MEM_FEAT_BLOCK_NB_STRUCT_VERSION, + MEM_FEATURE_ONLINE_SPARE, + MEM_FEATURE_BANK_INTERLEAVE, + MEM_FEATURE_UNDO_BANK_INTERLEAVE, + MEM_FEATURE_NODE_INTERLEAVE_CHECK, + MEM_FEATURE_NODE_INTERLEAVE, + MEM_FEATURE_CHANNEL_INTERLEAVE, + MemFDefRet, + MEM_FEATURE_CK_ECC, + MEM_FEATURE_ECC, + MEM_FEATURE_TRAINING, + MEM_FEATURE_LVDDR3, + MEM_FEATURE_ONDIMMTHERMAL, + MEM_TECH_FEATURE_DRAMINIT, + MEM_FEATURE_DIMM_EXCLUDE, + MemFDefRet, + MEM_TECH_FEATURE_CPG, + MEM_TECH_FEATURE_HWRXEN + }; + + #undef MEM_NB_SUPPORT_C32 + extern MEM_NB_CONSTRUCTOR MemConstructNBBlockC32; + extern MEM_INITIALIZER MemNInitDefaultsC32; + #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockC32, MemNInitDefaultsC32, &MemFeatBlockC32, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 }, + #endif // OPTION_MEMCTRL_C32 + + /*--------------------------------------------------------------------------------------------------- + * TRINITY FEATURE BLOCK + *--------------------------------------------------------------------------------------------------- + */ + #if (OPTION_MEMCTLR_TN == TRUE) + #if OPTION_DDR2 + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT + #endif + #if OPTION_DDR3 + #undef MEM_MAIN_FEATURE_LVDDR3 + extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3PerformanceEnhPre; + #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3PerformanceEnhPre + #undef MEM_TECH_FEATURE_DRAMINIT + #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT + #endif + + #define MEM_EARLY_SAMPLE_SUPPORT MemFDefRet + + #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE) + extern OPTION_MEM_FEATURE_NB MemNInitCPGUnb; + #undef MEM_TECH_FEATURE_CPG + #define MEM_TECH_FEATURE_CPG MemNInitCPGUnb + #else + #undef MEM_TECH_FEATURE_CPG + #define MEM_TECH_FEATURE_CPG MemFDefRet + #endif + + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #undef MEM_TECH_FEATURE_HWRXEN + #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb + #else + extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; + #undef MEM_TECH_FEATURE_HWRXEN + #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb + #endif + + + #undef MEM_MAIN_FEATURE_TRAINING + #undef MEM_FEATURE_TRAINING + //extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; + #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining + #define MEM_FEATURE_TRAINING MemFStandardTraining + + MEM_FEAT_BLOCK_NB MemFeatBlockTN = { + MEM_FEAT_BLOCK_NB_STRUCT_VERSION, + MEM_FEATURE_ONLINE_SPARE, + MEM_FEATURE_BANK_INTERLEAVE, + MEM_FEATURE_UNDO_BANK_INTERLEAVE, + MemFDefRet, + MemFDefRet, + MEM_FEATURE_CHANNEL_INTERLEAVE, + MEM_FEATURE_REGION_INTERLEAVE, + MEM_FEATURE_CK_ECC, + MEM_FEATURE_ECC, + MEM_FEATURE_TRAINING, + MEM_FEATURE_LVDDR3, + MEM_FEATURE_ONDIMMTHERMAL, + MEM_TECH_FEATURE_DRAMINIT, + MEM_FEATURE_DIMM_EXCLUDE, + MEM_EARLY_SAMPLE_SUPPORT, + MEM_TECH_FEATURE_CPG, + MEM_TECH_FEATURE_HWRXEN + }; + + #undef MEM_NB_SUPPORT_TN + extern MEM_NB_CONSTRUCTOR MemConstructNBBlockTN; + extern MEM_INITIALIZER MemNInitDefaultsTN; + #define MEM_NB_SUPPORT_TN { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockTN, MemNInitDefaultsTN, &MemFeatBlockTN, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_TN, MEM_IDENDIMM_TN }, + #endif // OPTION_MEMCTRL_TN + + + + /*--------------------------------------------------------------------------------------------------- + * MAIN FEATURE BLOCK + *--------------------------------------------------------------------------------------------------- + */ + MEM_FEAT_BLOCK_MAIN MemFeatMain = { + MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION, + MEM_MAIN_FEATURE_TRAINING, + MEM_MAIN_FEATURE_DIMM_EXCLUDE, + MEM_MAIN_FEATURE_ONLINE_SPARE, + MEM_MAIN_FEATURE_NODE_INTERLEAVE, + MEM_MAIN_FEATURE_ECC, + MEM_MAIN_FEATURE_MEM_CLEAR, + MEM_MAIN_FEATURE_MEM_DMI, + MemMDefRet, + MEM_MAIN_FEATURE_LVDDR3, + MEM_MAIN_FEATURE_UMAALLOC, + MEM_MAIN_FEATURE_MEM_SAVE, + MEM_MAIN_FEATURE_MEM_RESTORE + }; + + + /*--------------------------------------------------------------------------------------------------- + * Technology Training SPECIFIC CONFIGURATION + * + * + *--------------------------------------------------------------------------------------------------- + */ + #define MEM_TECH_TRAINING_FEAT_NULL_TERNMIATOR 0 + #if OPTION_MEMCTLR_DR + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr; + #if OPTION_DDR2 + #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1 + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2 + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTFeatDef + #endif + #endif + #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1 + #else + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #endif + #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #else + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #endif + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #endif + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #else + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #endif + #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency + #else + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef + #endif + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Dr = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR2, + TECH_TRAIN_SW_WL_DDR2, + TECH_TRAIN_HW_WL_P1_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_HW_WL_P2_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, + TECH_TRAIN_EXIT_HW_TRN_DDR2, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, + TECH_TRAIN_MAX_RD_LAT_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2, + NULL + }; + extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb; + #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb + extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb; + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR2Dr }, + #else + #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef + #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #if OPTION_DDR3 + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining + #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 + #else + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #endif + #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #else + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #endif + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1 + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2 + #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) + #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTRdPosWithRxEnDlySeeds3 + #else + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #else + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 + #else + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 + #else + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency + #else + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #endif + #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr; + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Dr = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR3, + TECH_TRAIN_SW_WL_DDR3, + TECH_TRAIN_HW_WL_P1_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_HW_WL_P2_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, + TECH_TRAIN_EXIT_HW_TRN_DDR3, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_MAX_RD_LAT_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, + MemTFeatDef + }; + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR3Dr }, + #else + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + + #if (OPTION_MEMCTLR_DA || OPTION_MEMCTLR_Ni || OPTION_MEMCTLR_PH || OPTION_MEMCTLR_RB) + #if OPTION_DDR2 + #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1 + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2 + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTFeatDef + #endif + #endif + #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1 + #else + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #endif + #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #else + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #endif + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #endif + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #else + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #endif + #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency + #else + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef + #endif + MEM_TECH_FEAT_BLOCK omi1867 = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR2, + TECH_TRAIN_SW_WL_DDR2, + TECH_TRAIN_HW_WL_P1_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_HW_WL_P2_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, + TECH_TRAIN_EXIT_HW_TRN_DDR2, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, + TECH_TRAIN_MAX_RD_LAT_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2, + NULL + }; + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2PH = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR2, + TECH_TRAIN_SW_WL_DDR2, + TECH_TRAIN_HW_WL_P1_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_HW_WL_P2_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, + TECH_TRAIN_EXIT_HW_TRN_DDR2, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, + TECH_TRAIN_MAX_RD_LAT_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2, + NULL + }; + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Rb = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR2, + TECH_TRAIN_SW_WL_DDR2, + TECH_TRAIN_HW_WL_P1_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_HW_WL_P2_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, + TECH_TRAIN_EXIT_HW_TRN_DDR2, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, + TECH_TRAIN_MAX_RD_LAT_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2, + NULL + }; + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Ni = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR2, + TECH_TRAIN_SW_WL_DDR2, + TECH_TRAIN_HW_WL_P1_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_HW_WL_P2_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, + TECH_TRAIN_EXIT_HW_TRN_DDR2, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, + TECH_TRAIN_MAX_RD_LAT_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2, + NULL + }; + extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb; + #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb + extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb; + #if (OPTION_MEMCTLR_DA) + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDA + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceDA, &omi1867 }, + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #if (OPTION_MEMCTLR_PH) + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequencePh + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequencePh, &memTechTrainingFeatSequenceDDR2PH }, + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #if (OPTION_MEMCTLR_RB) + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceRb + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceRb, &memTechTrainingFeatSequenceDDR2Rb }, + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + + #if (OPTION_MEMCTLR_Ni) + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceNi + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceNi, &memTechTrainingFeatSequenceDDR2Ni }, + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #else + #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef + #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #if OPTION_DDR3 + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining + #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 + #else + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #endif + #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #else + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #endif + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 + #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 + #endif + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 + #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 + #endif + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) + #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #else + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 + #else + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 + #else + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency + #else + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #endif + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3DA = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR3, + TECH_TRAIN_SW_WL_DDR3, + TECH_TRAIN_HW_WL_P1_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_HW_WL_P2_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, + TECH_TRAIN_EXIT_HW_TRN_DDR3, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_MAX_RD_LAT_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, + NULL + }; + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Ph = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR3, + TECH_TRAIN_SW_WL_DDR3, + TECH_TRAIN_HW_WL_P1_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_HW_WL_P2_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, + TECH_TRAIN_EXIT_HW_TRN_DDR3, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_MAX_RD_LAT_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, + NULL + }; + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Rb = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR3, + TECH_TRAIN_SW_WL_DDR3, + TECH_TRAIN_HW_WL_P1_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_HW_WL_P2_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, + TECH_TRAIN_EXIT_HW_TRN_DDR3, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_MAX_RD_LAT_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, + NULL + }; + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Ni = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR3, + TECH_TRAIN_SW_WL_DDR3, + TECH_TRAIN_HW_WL_P1_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_HW_WL_P2_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, + TECH_TRAIN_EXIT_HW_TRN_DDR3, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_MAX_RD_LAT_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, + + }; + #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb + #if (OPTION_MEMCTLR_DA) + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDA; + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDA, &memTechTrainingFeatSequenceDDR3DA }, + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #if (OPTION_MEMCTLR_PH) + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequencePh; + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequencePh, &memTechTrainingFeatSequenceDDR3Ph }, + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #if (OPTION_MEMCTLR_RB) + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceRb; + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceRb, &memTechTrainingFeatSequenceDDR3Rb }, + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #if (OPTION_MEMCTLR_Ni) + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceNi; + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceNi, &memTechTrainingFeatSequenceDDR3Ni }, + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #else + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + + #if OPTION_MEMCTLR_HY + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceHy; + #if OPTION_DDR2 + #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1 + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2 + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTFeatDef + #endif + #endif + #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1 + #else + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #endif + #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #else + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #endif + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #endif + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #else + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #endif + #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency + #else + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef + #endif + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Hy = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR2, + TECH_TRAIN_SW_WL_DDR2, + TECH_TRAIN_HW_WL_P1_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_HW_WL_P2_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, + TECH_TRAIN_EXIT_HW_TRN_DDR2, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, + TECH_TRAIN_MAX_RD_LAT_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2, + NULL + }; + extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb; + #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb + extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb; + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceHy, &memTechTrainingFeatSequenceDDR2Hy }, + #else + #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef + #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #if OPTION_DDR3 + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining + #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 + #else + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #endif + #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #else + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #endif + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 + #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 + #endif + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 + #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 + #endif + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) + #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #else + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 + #else + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 + #else + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency + #else + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #endif + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Hy = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR3, + TECH_TRAIN_SW_WL_DDR3, + TECH_TRAIN_HW_WL_P1_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_HW_WL_P2_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, + TECH_TRAIN_EXIT_HW_TRN_DDR3, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_MAX_RD_LAT_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, + NULL + }; + #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceHy, &memTechTrainingFeatSequenceDDR3Hy }, + #else + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + + #if OPTION_MEMCTLR_C32 + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceC32; + #if OPTION_DDR2 + #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1 + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2 + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1 + #else + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #endif + #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #else + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #endif + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #endif + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #else + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #endif + #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency + #else + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef + #endif + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2C32 = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR2, + TECH_TRAIN_SW_WL_DDR2, + TECH_TRAIN_HW_WL_P1_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_HW_WL_P2_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, + TECH_TRAIN_EXIT_HW_TRN_DDR2, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, + TECH_TRAIN_MAX_RD_LAT_DDR2, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2, + NULL + }; + extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb; + #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb + extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb; + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceC32, &memTechTrainingFeatSequenceDDR2C32 }, + #else + #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef + #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #if OPTION_DDR3 + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining + #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 + #else + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #endif + #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #else + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #endif + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 + #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 + #endif + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 + #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 + #endif + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #else + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 + #else + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 + #else + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency + #else + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #endif + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3C32 = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR3, + TECH_TRAIN_SW_WL_DDR3, + TECH_TRAIN_HW_WL_P1_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_HW_WL_P2_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, + TECH_TRAIN_EXIT_HW_TRN_DDR3, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_MAX_RD_LAT_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, + NULL + }; + #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceC32, &memTechTrainingFeatSequenceDDR3C32 }, + #else + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + + + #if OPTION_MEMCTLR_LN + #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef + #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceLN; + #if OPTION_DDR3 + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTrainingClient3 + #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 + #else + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #endif + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 + #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 + #endif + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1 + #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 + #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 + #endif + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2 + #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) + #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTRdPosWithRxEnDlySeeds3 + #else + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #else + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 + #else + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 + #else + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency + #else + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #endif + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3LN = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR3, + TECH_TRAIN_SW_WL_DDR3, + TECH_TRAIN_HW_WL_P1_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_HW_WL_P2_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, + TECH_TRAIN_EXIT_HW_TRN_DDR3, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_MAX_RD_LAT_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, + NULL + }; + #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceLN, &memTechTrainingFeatSequenceDDR3LN }, + #else + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + + + #if OPTION_MEMCTLR_OR + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceOr; + #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef + #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #if OPTION_DDR3 + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining + #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 + #else + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #endif + #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #else + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #endif + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 + #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 + #endif + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1 + #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 + #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 + #endif + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2 + #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) + #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTRdPosWithRxEnDlySeeds3 + #else + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #else + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #else + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 + #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #else + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #undef TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency + #else + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #endif + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3OR = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR3, + TECH_TRAIN_SW_WL_DDR3, + TECH_TRAIN_HW_WL_P1_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_HW_WL_P2_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, + TECH_TRAIN_EXIT_HW_TRN_DDR3, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_MAX_RD_LAT_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, + NULL + }; + #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceOr, &memTechTrainingFeatSequenceDDR3OR }, + #else + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + + + #if OPTION_MEMCTLR_ON + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceON; + #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef + #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #if OPTION_DDR3 + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTrainingClient3 + #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 + #else + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #endif + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1 + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2 + #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) + #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTRdPosWithRxEnDlySeeds3 + #else + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #else + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 + #else + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 + #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 + #else + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency + #else + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #endif + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3ON = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR3, + TECH_TRAIN_SW_WL_DDR3, + TECH_TRAIN_HW_WL_P1_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_HW_WL_P2_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, + TECH_TRAIN_EXIT_HW_TRN_DDR3, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_MAX_RD_LAT_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, + NULL + }; + #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceON, &memTechTrainingFeatSequenceDDR3ON }, + #else + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + + #if OPTION_MEMCTLR_TN + extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceTN; + #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef + #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_TN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #if OPTION_DDR3 + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining + #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 + #else + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #endif + #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #else + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #endif + #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) + #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 + #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 + #endif + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1 + #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 + #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 + #endif + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2 + #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) + #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 + extern MEM_TECH_FEAT MemNRdPosTrnTN; + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemNRdPosTrnTN + #else + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #else + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect + #else + #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef + #endif + #endif + #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #else + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 + #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #else + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #endif + #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #undef TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 + #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw + #else + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #endif + #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency + #else + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #endif + MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3TN = { + MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, + TECH_TRAIN_ENTER_HW_TRN_DDR3, + TECH_TRAIN_SW_WL_DDR3, + TECH_TRAIN_HW_WL_P1_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_HW_WL_P2_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, + TECH_TRAIN_EXIT_HW_TRN_DDR3, + TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, + TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, + TECH_TRAIN_MAX_RD_LAT_DDR3, + TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, + + }; + #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_TN {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceTN, &memTechTrainingFeatSequenceDDR3TN }, + #else + #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 + #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef + #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 + #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef + #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef + #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef + #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_TN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + #else + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_TN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_TN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, + #endif + + + + #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0 } + MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = { + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_TN + MEM_TECH_ENABLE_TRAINING_SEQUENCE_END + }; + + MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB + MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_TN + MEM_TECH_ENABLE_TRAINING_SEQUENCE_END + }; + /*--------------------------------------------------------------------------------------------------- + * NB TRAINING FLOW CONTROL + * + * + *--------------------------------------------------------------------------------------------------- + */ + OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = { // Training flow control + NB_TRAIN_FLOW_DDR2, + NB_TRAIN_FLOW_DDR3, + }; + /*--------------------------------------------------------------------------------------------------- + * TECHNOLOGY BLOCK + * + * + *--------------------------------------------------------------------------------------------------- + */ + MEM_TECH_CONSTRUCTOR* memTechInstalled[] = { // Types of technology installed + MEM_TECH_CONSTRUCTOR_DDR2 + MEM_TECH_CONSTRUCTOR_DDR3 + NULL + }; + /*--------------------------------------------------------------------------------------------------- + * PLATFORM SPECIFIC BLOCK FORM FACTOR DEFINITION + * + * + *--------------------------------------------------------------------------------------------------- + */ + #if OPTION_MEMCTLR_HY + #if OPTION_UDIMMS + #if OPTION_DDR2 + #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef, + #else + #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef, + #endif + #if OPTION_DDR3 + #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUHy3, + #else + #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef, + #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUDef, + #endif + #if OPTION_RDIMMS + #if OPTION_DDR2 + #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef, + #else + #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef, + #endif + #if OPTION_DDR3 + #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsRHy3, + #else + #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef, + #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsUDef, + #endif + #if OPTION_SODIMMS + #if OPTION_DDR2 + #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef, + #else + #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef, + #endif + #if OPTION_DDR3 + #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsSHy3, + #else + #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef, + #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef, + #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef, + #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef, + #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsUDef, + #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsUDef, + #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUDef, + #endif + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = { + PLAT_SP_HY_FF_UDIMM2 + PLAT_SP_HY_FF_RDIMM2 + PLAT_SP_HY_FF_SDIMM2 + PLAT_SP_HY_FF_UDIMM3 + PLAT_SP_HY_FF_RDIMM3 + PLAT_SP_HY_FF_SDIMM3 + }; + + #if OPTION_MEMCTLR_DR + #if OPTION_UDIMMS + #if OPTION_DDR2 + extern MEM_PLAT_SPEC_CFG MemPConstructPsUDr2; + #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDr2, + #else + #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDef, + #endif + #if OPTION_DDR3 + #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDr3, + #else + #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDef, + #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDef, + #endif + #if OPTION_RDIMMS + #if OPTION_DDR2 + extern MEM_PLAT_SPEC_CFG MemPConstructPsRDr2; + #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsRDr2, + #else + #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsUDef, + #endif + #if OPTION_DDR3 + #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsRDr3, + #else + #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsUDef, + #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsUDef, + #endif + #if OPTION_SODIMMS + #if OPTION_DDR2 + #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef, + #else + #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef, + #endif + #if OPTION_DDR3 + #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsSDr3, + #else + #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef, + #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef, + #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsUDef, + #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDef, + #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsUDef, + #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsUDef, + #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDef, + #endif + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDR[MAX_FF_TYPES] = { + PLAT_SP_DR_FF_UDIMM2 + PLAT_SP_DR_FF_RDIMM2 + PLAT_SP_DR_FF_SDIMM2 + PLAT_SP_DR_FF_UDIMM3 + PLAT_SP_DR_FF_RDIMM3 + PLAT_SP_DR_FF_SDIMM3 + }; + + #if (OPTION_MEMCTLR_DA == TRUE) + #if OPTION_UDIMMS + #if OPTION_DDR2 + #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef, + #else + #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef, + #endif + #if OPTION_DDR3 + #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDA3, + #else + #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef, + #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDef, + #endif + #if OPTION_RDIMMS + #if OPTION_DDR2 + #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef, + #else + #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef, + #endif + #if OPTION_DDR3 + #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef, + #else + #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef, + #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef, + #endif + #if OPTION_SODIMMS + #if OPTION_DDR2 + #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsSDA2, + #else + #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsUDef, + #endif + #if OPTION_DDR3 + #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsSDA3, + #else + #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsUDef, + #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsUDef, + #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef, + #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef, + #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsUDef, + #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef, + #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDef, + #endif + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = { + PLAT_SP_DA_FF_UDIMM2 + PLAT_SP_DA_FF_RDIMM2 + PLAT_SP_DA_FF_SDIMM2 + PLAT_SP_DA_FF_UDIMM3 + PLAT_SP_DA_FF_RDIMM3 + PLAT_SP_DA_FF_SDIMM3 + }; + + #if (OPTION_MEMCTLR_Ni == TRUE) + #define PLAT_SP_NI_FF_SDIMM2 MemPConstructPsUDef, + #define PLAT_SP_NI_FF_RDIMM2 MemPConstructPsUDef, + #define PLAT_SP_NI_FF_UDIMM2 MemPConstructPsUDef, + #define PLAT_SP_NI_FF_SDIMM3 MemPConstructPsSNi3, + #define PLAT_SP_NI_FF_RDIMM3 MemPConstructPsUDef, + #define PLAT_SP_NI_FF_UDIMM3 MemPConstructPsUNi3, + #else + #define PLAT_SP_NI_FF_SDIMM2 MemPConstructPsUDef, + #define PLAT_SP_NI_FF_RDIMM2 MemPConstructPsUDef, + #define PLAT_SP_NI_FF_UDIMM2 MemPConstructPsUDef, + #define PLAT_SP_NI_FF_SDIMM3 MemPConstructPsUDef, + #define PLAT_SP_NI_FF_RDIMM3 MemPConstructPsUDef, + #define PLAT_SP_NI_FF_UDIMM3 MemPConstructPsUDef, + #endif + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES] = { + PLAT_SP_NI_FF_UDIMM2 + PLAT_SP_NI_FF_RDIMM2 + PLAT_SP_NI_FF_SDIMM2 + PLAT_SP_NI_FF_UDIMM3 + PLAT_SP_NI_FF_RDIMM3 + PLAT_SP_NI_FF_SDIMM3 + }; + + #if (OPTION_MEMCTLR_PH == TRUE) + #define PLAT_SP_PH_FF_SDIMM2 MemPConstructPsUDef, + #define PLAT_SP_PH_FF_RDIMM2 MemPConstructPsUDef, + #define PLAT_SP_PH_FF_UDIMM2 MemPConstructPsUDef, + #define PLAT_SP_PH_FF_SDIMM3 MemPConstructPsSPh3, + #define PLAT_SP_PH_FF_RDIMM3 MemPConstructPsUDef, + #define PLAT_SP_PH_FF_UDIMM3 MemPConstructPsUPh3, + #else + #define PLAT_SP_PH_FF_SDIMM2 MemPConstructPsUDef, + #define PLAT_SP_PH_FF_RDIMM2 MemPConstructPsUDef, + #define PLAT_SP_PH_FF_UDIMM2 MemPConstructPsUDef, + #define PLAT_SP_PH_FF_SDIMM3 MemPConstructPsUDef, + #define PLAT_SP_PH_FF_RDIMM3 MemPConstructPsUDef, + #define PLAT_SP_PH_FF_UDIMM3 MemPConstructPsUDef, + #endif + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES] = { + PLAT_SP_PH_FF_UDIMM2 + PLAT_SP_PH_FF_RDIMM2 + PLAT_SP_PH_FF_SDIMM2 + PLAT_SP_PH_FF_UDIMM3 + PLAT_SP_PH_FF_RDIMM3 + PLAT_SP_PH_FF_SDIMM3 + }; + + #if (OPTION_MEMCTLR_RB == TRUE) + #define PLAT_SP_RB_FF_SDIMM2 MemPConstructPsUDef, + #define PLAT_SP_RB_FF_RDIMM2 MemPConstructPsUDef, + #define PLAT_SP_RB_FF_UDIMM2 MemPConstructPsUDef, + #define PLAT_SP_RB_FF_SDIMM3 MemPConstructPsSRb3, + #define PLAT_SP_RB_FF_RDIMM3 MemPConstructPsUDef, + #define PLAT_SP_RB_FF_UDIMM3 MemPConstructPsURb3, + #else + #define PLAT_SP_RB_FF_SDIMM2 MemPConstructPsUDef, + #define PLAT_SP_RB_FF_RDIMM2 MemPConstructPsUDef, + #define PLAT_SP_RB_FF_UDIMM2 MemPConstructPsUDef, + #define PLAT_SP_RB_FF_SDIMM3 MemPConstructPsUDef, + #define PLAT_SP_RB_FF_RDIMM3 MemPConstructPsUDef, + #define PLAT_SP_RB_FF_UDIMM3 MemPConstructPsUDef, + #endif + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES] = { + PLAT_SP_RB_FF_UDIMM2 + PLAT_SP_RB_FF_RDIMM2 + PLAT_SP_RB_FF_SDIMM2 + PLAT_SP_RB_FF_UDIMM3 + PLAT_SP_RB_FF_RDIMM3 + PLAT_SP_RB_FF_SDIMM3 + }; + + #if OPTION_MEMCTLR_LN + #if OPTION_UDIMMS + #if OPTION_DDR3 + #define PLAT_SP_LN_FF_UDIMM3 MemPConstructPsULN3, + #else + #define PLAT_SP_LN_FF_UDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_LN_FF_UDIMM3 MemPConstructPsUDef, + #endif + #if OPTION_SODIMMS + #if OPTION_DDR3 + #define PLAT_SP_LN_FF_SDIMM3 MemPConstructPsSLN3, + #else + #define PLAT_SP_LN_FF_SDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_LN_FF_SDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_LN_FF_SDIMM3 MemPConstructPsUDef, + #define PLAT_SP_LN_FF_UDIMM3 MemPConstructPsUDef, + #endif + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledLN[] = { + PLAT_SP_LN_FF_SDIMM3 + PLAT_SP_LN_FF_UDIMM3 + NULL + }; + + #if OPTION_MEMCTLR_C32 + #if OPTION_UDIMMS + #if OPTION_DDR2 + #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef, + #else + #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef, + #endif + #if OPTION_DDR3 + #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUC32_3, + #else + #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef, + #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUDef, + #endif + #if OPTION_RDIMMS + #if OPTION_DDR2 + #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef, + #else + #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef, + #endif + #if OPTION_DDR3 + #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsRC32_3, + #else + #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef, + #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsUDef, + #endif + #if OPTION_SODIMMS + #define PLAT_SP_C32_FF_SDIMM2 MemPConstructPsUDef, + #define PLAT_SP_C32_FF_SDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_C32_FF_SDIMM2 MemPConstructPsUDef, + #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef, + #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef, + #define PLAT_SP_C32_FF_SDIMM3 MemPConstructPsUDef, + #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsUDef, + #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUDef, + #endif + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = { + PLAT_SP_C32_FF_UDIMM2 + PLAT_SP_C32_FF_RDIMM2 + PLAT_SP_C32_FF_SDIMM2 + PLAT_SP_C32_FF_UDIMM3 + PLAT_SP_C32_FF_RDIMM3 + PLAT_SP_C32_FF_SDIMM3 + }; + + #if OPTION_MEMCTLR_ON + #if OPTION_UDIMMS + #if OPTION_DDR3 + #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUON3, + #else + #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUDef, + #endif + #if OPTION_SODIMMS + #if OPTION_DDR3 + #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsSON3, + #else + #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsUDef, + #endif + #else + #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsUDef, + #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUDef, + #endif + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[] = { + PLAT_SP_ON_FF_SDIMM3 + PLAT_SP_ON_FF_UDIMM3 + NULL + }; + + /*--------------------------------------------------------------------------------------------------- + * PLATFORM-SPECIFIC CONFIGURATION + * + * + *--------------------------------------------------------------------------------------------------- + */ + + #if OPTION_MEMCTLR_DR + #if OPTION_UDIMMS + #if OPTION_DDR2 + #define PSC_DR_UDIMM_DDR2 //MemAGetPsCfgUDr2 + #else + #define PSC_DR_UDIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_DR_UDIMM_DDR3 MemAGetPsCfgUDr3, + #else + #define PSC_DR_UDIMM_DDR3 + #endif + #endif + #if OPTION_RDIMMS + #if OPTION_DDR2 + #define PSC_DR_RDIMM_DDR2 MemAGetPsCfgRDr2, + #else + #define PSC_DR_RDIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_DR_RDIMM_DDR3 MemAGetPsCfgRDr3, + #else + #define PSC_DR_RDIMM_DDR3 + #endif + #endif + #if OPTION_SODIMMS + #if OPTION_DDR2 + #define PSC_DR_SODIMM_DDR2 //MemAGetPsCfgSDr2 + #else + #define PSC_DR_SODIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_DR_SODIMM_DDR3 //MemAGetPsCfgSDr3 + #else + #define PSC_DR_SODIMM_DDR3 + #endif + #endif + #endif + + #if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE) + #if OPTION_MEMCTLR_Ni + #define PSC_NI_UDIMM_DDR2 + #define PSC_NI_UDIMM_DDR3 MemAGetPsCfgUNi3, + #define PSC_NI_RDIMM_DDR2 + #define PSC_NI_RDIMM_DDR3 + #define PSC_NI_SODIMM_DDR2 + #define PSC_NI_SODIMM_DDR3 MemAGetPsCfgSNi3, + #endif + #if OPTION_MEMCTLR_PH + #define PSC_PH_UDIMM_DDR2 + #define PSC_PH_UDIMM_DDR3 MemAGetPsCfgUPh3, + #define PSC_PH_RDIMM_DDR2 + #define PSC_PH_RDIMM_DDR3 + #define PSC_PH_SODIMM_DDR2 + #define PSC_PH_SODIMM_DDR3 MemAGetPsCfgSPh3, + #endif + #if OPTION_MEMCTLR_RB + #define PSC_RB_UDIMM_DDR2 + #define PSC_RB_UDIMM_DDR3 MemAGetPsCfgURb3, + #define PSC_RB_RDIMM_DDR2 + #define PSC_RB_RDIMM_DDR3 + #define PSC_RB_SODIMM_DDR2 + #define PSC_RB_SODIMM_DDR3 MemAGetPsCfgSRb3, + #endif + #if OPTION_MEMCTLR_DA + #if OPTION_UDIMMS + #if OPTION_DDR2 + #define PSC_DA_UDIMM_DDR2 //MemAGetPsCfgUDr2 + #else + #define PSC_DA_UDIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_DA_UDIMM_DDR3 MemAGetPsCfgUDA3, + #else + #define PSC_DA_UDIMM_DDR3 + #endif + #endif + #if OPTION_RDIMMS + #if OPTION_DDR2 + #define PSC_DA_RDIMM_DDR2 + #else + #define PSC_DA_RDIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_DA_RDIMM_DDR3 + #else + #define PSC_DA_RDIMM_DDR3 + #endif + #endif + #if OPTION_SODIMMS + #if OPTION_DDR2 + #define PSC_DA_SODIMM_DDR2 MemAGetPsCfgSDA2, + #else + #define PSC_DA_SODIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_DA_SODIMM_DDR3 MemAGetPsCfgSDA3, + #else + #define PSC_DA_SODIMM_DDR3 + #endif + #endif + #endif + #endif + + #if OPTION_MEMCTLR_HY + #if OPTION_UDIMMS + #if OPTION_DDR2 + #define PSC_HY_UDIMM_DDR2 //MemAGetPsCfgUDr2, + #else + #define PSC_HY_UDIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_HY_UDIMM_DDR3 MemAGetPsCfgUHy3, + #else + #define PSC_HY_UDIMM_DDR3 + #endif + #endif + #if OPTION_RDIMMS + #if OPTION_DDR2 + #define PSC_HY_RDIMM_DDR2 + #else + #define PSC_HY_RDIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_HY_RDIMM_DDR3 MemAGetPsCfgRHy3, + #else + #define PSC_HY_RDIMM_DDR3 + #endif + #endif + #if OPTION_SODIMMS + #if OPTION_DDR2 + #define PSC_HY_SODIMM_DDR2 //MemAGetPsCfgSHy2, + #else + #define PSC_HY_SODIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_HY_SODIMM_DDR3 //MemAGetPsCfgSHy3, + #else + #define PSC_HY_SODIMM_DDR3 + #endif + #endif + #endif + + #if OPTION_MEMCTLR_C32 + #if OPTION_UDIMMS + #if OPTION_DDR2 + #define PSC_C32_UDIMM_DDR2 //MemAGetPsCfgUDr2, + #else + #define PSC_C32_UDIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_C32_UDIMM_DDR3 MemAGetPsCfgUC32_3, + #else + #define PSC_C32_UDIMM_DDR3 + #endif + #endif + #if OPTION_RDIMMS + #if OPTION_DDR2 + #define PSC_C32_RDIMM_DDR2 + #else + #define PSC_C32_RDIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_C32_RDIMM_DDR3 MemAGetPsCfgRC32_3, + #else + #define PSC_C32_RDIMM_DDR3 + #endif + #endif + #if OPTION_SODIMMS + #if OPTION_DDR2 + #define PSC_C32_SODIMM_DDR2 //MemAGetPsCfgSC32_2, + #else + #define PSC_C32_SODIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_C32_SODIMM_DDR3 //MemAGetPsCfgSC32_3, + #else + #define PSC_C32_SODIMM_DDR3 + #endif + #endif + #endif + + #if OPTION_MEMCTLR_LN + #if OPTION_UDIMMS + #if OPTION_DDR2 + #define PSC_LN_UDIMM_DDR2 //MemAGetPsCfgULN2, + #else + #define PSC_LN_UDIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_LN_UDIMM_DDR3 MemAGetPsCfgULN3, + #else + #define PSC_LN_UDIMM_DDR3 + #endif + #endif + #if OPTION_RDIMMS + #if OPTION_DDR2 + #define PSC_LN_RDIMM_DDR2 + #else + #define PSC_LN_RDIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_LN_RDIMM_DDR3 //MemAGetPsCfgRLN3, + #else + #define PSC_LN_RDIMM_DDR3 + #endif + #endif + #if OPTION_SODIMMS + #if OPTION_DDR2 + #define PSC_LN_SODIMM_DDR2 //MemAGetPsCfgSLN2, + #else + #define PSC_LN_SODIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_LN_SODIMM_DDR3 MemAGetPsCfgSLN3, + #else + #define PSC_LN_SODIMM_DDR3 + #endif + #endif + #endif + + #if OPTION_MEMCTLR_OR + #if OPTION_UDIMMS + #if OPTION_DDR2 + #define PSC_OR_UDIMM_DDR2 //MemAGetPsCfgUOr2, + #else + #define PSC_OR_UDIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_OR_UDIMM_DDR3 //MemAGetPsCfgUOr3, + #else + #define PSC_OR_UDIMM_DDR3 + #endif + #endif + #if OPTION_RDIMMS + #if OPTION_DDR2 + #define PSC_OR_RDIMM_DDR2 + #else + #define PSC_OR_RDIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_OR_RDIMM_DDR3 //MemAGetPsCfgROr3, + #else + #define PSC_OR_RDIMM_DDR3 + #endif + #endif + #if OPTION_SODIMMS + #if OPTION_DDR2 + #define PSC_OR_SODIMM_DDR2 //MemAGetPsCfgSOr2, + #else + #define PSC_OR_SODIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_OR_SODIMM_DDR3 //MemAGetPsCfgSOr3, + #else + #define PSC_OR_SODIMM_DDR3 + #endif + #endif + #endif + + #if OPTION_MEMCTLR_ON + #if OPTION_UDIMMS + #if OPTION_DDR2 + #define PSC_ON_UDIMM_DDR2 //MemAGetPsCfgUON2, + #else + #define PSC_ON_UDIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_ON_UDIMM_DDR3 MemAGetPsCfgUON3, + #else + #define PSC_ON_UDIMM_DDR3 + #endif + #endif + #if OPTION_RDIMMS + #if OPTION_DDR2 + #define PSC_ON_RDIMM_DDR2 + #else + #define PSC_ON_RDIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_ON_RDIMM_DDR3 //MemAGetPsCfgRON3, + #else + #define PSC_ON_RDIMM_DDR3 + #endif + #endif + #if OPTION_SODIMMS + #if OPTION_DDR2 + #define PSC_ON_SODIMM_DDR2 //MemAGetPsCfgSON2, + #else + #define PSC_ON_SODIMM_DDR2 + #endif + #if OPTION_DDR3 + #define PSC_ON_SODIMM_DDR3 MemAGetPsCfgSON3, + #else + #define PSC_ON_SODIMM_DDR3 + #endif + #endif + #endif + + /*---------------------------------------------------------------------- + * DEFAULT PSCFG DEFINITIONS + * + *---------------------------------------------------------------------- + */ + + #ifndef PSC_DR_UDIMM_DDR2 + #define PSC_DR_UDIMM_DDR2 + #endif + #ifndef PSC_DR_RDIMM_DDR2 + #define PSC_DR_RDIMM_DDR2 + #endif + #ifndef PSC_DR_SODIMM_DDR2 + #define PSC_DR_SODIMM_DDR2 + #endif + #ifndef PSC_DR_UDIMM_DDR3 + #define PSC_DR_UDIMM_DDR3 + #endif + #ifndef PSC_DR_RDIMM_DDR3 + #define PSC_DR_RDIMM_DDR3 + #endif + #ifndef PSC_DR_SODIMM_DDR3 + #define PSC_DR_SODIMM_DDR3 + #endif + #ifndef PSC_RB_UDIMM_DDR2 + #define PSC_RB_UDIMM_DDR2 + #endif + #ifndef PSC_RB_RDIMM_DDR2 + #define PSC_RB_RDIMM_DDR2 + #endif + #ifndef PSC_RB_SODIMM_DDR2 + #define PSC_RB_SODIMM_DDR2 + #endif + #ifndef PSC_RB_UDIMM_DDR3 + #define PSC_RB_UDIMM_DDR3 + #endif + #ifndef PSC_RB_RDIMM_DDR3 + #define PSC_RB_RDIMM_DDR3 + #endif + #ifndef PSC_RB_SODIMM_DDR3 + #define PSC_RB_SODIMM_DDR3 + #endif + #ifndef PSC_DA_UDIMM_DDR2 + #define PSC_DA_UDIMM_DDR2 + #endif + #ifndef PSC_DA_RDIMM_DDR2 + #define PSC_DA_RDIMM_DDR2 + #endif + #ifndef PSC_DA_SODIMM_DDR2 + #define PSC_DA_SODIMM_DDR2 + #endif + #ifndef PSC_DA_UDIMM_DDR3 + #define PSC_DA_UDIMM_DDR3 + #endif + #ifndef PSC_DA_RDIMM_DDR3 + #define PSC_DA_RDIMM_DDR3 + #endif + #ifndef PSC_DA_SODIMM_DDR3 + #define PSC_DA_SODIMM_DDR3 + #endif + #ifndef PSC_NI_UDIMM_DDR2 + #define PSC_NI_UDIMM_DDR2 + #endif + #ifndef PSC_NI_RDIMM_DDR2 + #define PSC_NI_RDIMM_DDR2 + #endif + #ifndef PSC_NI_SODIMM_DDR2 + #define PSC_NI_SODIMM_DDR2 + #endif + #ifndef PSC_NI_UDIMM_DDR3 + #define PSC_NI_UDIMM_DDR3 + #endif + #ifndef PSC_NI_RDIMM_DDR3 + #define PSC_NI_RDIMM_DDR3 + #endif + #ifndef PSC_NI_SODIMM_DDR3 + #define PSC_NI_SODIMM_DDR3 + #endif + #ifndef PSC_PH_UDIMM_DDR2 + #define PSC_PH_UDIMM_DDR2 + #endif + #ifndef PSC_PH_RDIMM_DDR2 + #define PSC_PH_RDIMM_DDR2 + #endif + #ifndef PSC_PH_SODIMM_DDR2 + #define PSC_PH_SODIMM_DDR2 + #endif + #ifndef PSC_PH_UDIMM_DDR3 + #define PSC_PH_UDIMM_DDR3 + #endif + #ifndef PSC_PH_RDIMM_DDR3 + #define PSC_PH_RDIMM_DDR3 + #endif + #ifndef PSC_PH_SODIMM_DDR3 + #define PSC_PH_SODIMM_DDR3 + #endif + #ifndef PSC_HY_UDIMM_DDR2 + #define PSC_HY_UDIMM_DDR2 + #endif + #ifndef PSC_HY_RDIMM_DDR2 + #define PSC_HY_RDIMM_DDR2 + #endif + #ifndef PSC_HY_SODIMM_DDR2 + #define PSC_HY_SODIMM_DDR2 + #endif + #ifndef PSC_HY_UDIMM_DDR3 + #define PSC_HY_UDIMM_DDR3 + #endif + #ifndef PSC_HY_RDIMM_DDR3 + #define PSC_HY_RDIMM_DDR3 + #endif + #ifndef PSC_HY_SODIMM_DDR3 + #define PSC_HY_SODIMM_DDR3 + #endif + #ifndef PSC_LN_UDIMM_DDR2 + #define PSC_LN_UDIMM_DDR2 + #endif + #ifndef PSC_LN_RDIMM_DDR2 + #define PSC_LN_RDIMM_DDR2 + #endif + #ifndef PSC_LN_SODIMM_DDR2 + #define PSC_LN_SODIMM_DDR2 + #endif + #ifndef PSC_LN_UDIMM_DDR3 + #define PSC_LN_UDIMM_DDR3 + #endif + #ifndef PSC_LN_RDIMM_DDR3 + #define PSC_LN_RDIMM_DDR3 + #endif + #ifndef PSC_LN_SODIMM_DDR3 + #define PSC_LN_SODIMM_DDR3 + #endif + #ifndef PSC_OR_UDIMM_DDR2 + #define PSC_OR_UDIMM_DDR2 + #endif + #ifndef PSC_OR_RDIMM_DDR2 + #define PSC_OR_RDIMM_DDR2 + #endif + #ifndef PSC_OR_SODIMM_DDR2 + #define PSC_OR_SODIMM_DDR2 + #endif + #ifndef PSC_OR_UDIMM_DDR3 + #define PSC_OR_UDIMM_DDR3 + #endif + #ifndef PSC_OR_RDIMM_DDR3 + #define PSC_OR_RDIMM_DDR3 + #endif + #ifndef PSC_OR_SODIMM_DDR3 + #define PSC_OR_SODIMM_DDR3 + #endif + #ifndef PSC_C32_UDIMM_DDR3 + #define PSC_C32_UDIMM_DDR3 + #endif + #ifndef PSC_C32_RDIMM_DDR3 + #define PSC_C32_RDIMM_DDR3 + #endif + #ifndef PSC_ON_UDIMM_DDR2 + #define PSC_ON_UDIMM_DDR2 + #endif + #ifndef PSC_ON_RDIMM_DDR2 + #define PSC_ON_RDIMM_DDR2 + #endif + #ifndef PSC_ON_SODIMM_DDR2 + #define PSC_ON_SODIMM_DDR2 + #endif + #ifndef PSC_ON_UDIMM_DDR3 + #define PSC_ON_UDIMM_DDR3 + #endif + #ifndef PSC_ON_RDIMM_DDR3 + #define PSC_ON_RDIMM_DDR3 + #endif + #ifndef PSC_ON_SODIMM_DDR3 + #define PSC_ON_SODIMM_DDR3 + #endif + + MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = { + PSC_DR_UDIMM_DDR2 + PSC_DR_RDIMM_DDR2 + PSC_DR_SODIMM_DDR2 + PSC_DR_UDIMM_DDR3 + PSC_DR_RDIMM_DDR3 + PSC_DR_SODIMM_DDR3 + PSC_RB_UDIMM_DDR3 + PSC_RB_SODIMM_DDR3 + PSC_DA_SODIMM_DDR2 + PSC_DA_UDIMM_DDR3 + PSC_DA_SODIMM_DDR3 + PSC_NI_UDIMM_DDR3 + PSC_NI_SODIMM_DDR3 + PSC_PH_UDIMM_DDR3 + PSC_PH_SODIMM_DDR3 + PSC_HY_UDIMM_DDR3 + PSC_HY_RDIMM_DDR3 + PSC_HY_SODIMM_DDR3 + PSC_LN_UDIMM_DDR3 + PSC_LN_RDIMM_DDR3 + PSC_LN_SODIMM_DDR3 + PSC_OR_UDIMM_DDR3 + PSC_OR_RDIMM_DDR3 + PSC_OR_SODIMM_DDR3 + PSC_C32_UDIMM_DDR3 + PSC_C32_RDIMM_DDR3 + PSC_ON_UDIMM_DDR3 + PSC_ON_RDIMM_DDR3 + PSC_ON_SODIMM_DDR3 + NULL + }; + CONST UINTN SIZE_OF_PLATFORM = (sizeof (memPlatformTypeInstalled) / sizeof (MEM_PLATFORM_CFG*)); + //remove warning#if SIZE_OF_PLATFORM > MAX_PLATFORM_TYPES + // #error Size of memPlatformTypeInstalled array larger than MAX_PLATFORM_TYPES + //#endif + + /*--------------------------------------------------------------------------------------------------- + * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION + * + * + *--------------------------------------------------------------------------------------------------- + */ + #define MEM_PSC_FLOW_BLOCK_END NULL + #define PSC_TBL_END NULL + #define MEM_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue + + #if OPTION_MEMCTLR_OR + #if OPTION_UDIMMS + #if OPTION_AM3_SOCKET_SUPPORT + extern PSC_TBL_ENTRY MaxFreqTblEntUAM3; + #define PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 &MaxFreqTblEntUAM3, + extern PSC_TBL_ENTRY DramTermTblEntUAM3; + #define PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 &DramTermTblEntUAM3, + extern PSC_TBL_ENTRY OdtPat1DTblEntUAM3; + #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 &OdtPat1DTblEntUAM3, + extern PSC_TBL_ENTRY OdtPat2DTblEntUAM3; + #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 &OdtPat2DTblEntUAM3, + extern PSC_TBL_ENTRY OdtPat3DTblEntUAM3; + #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 &OdtPat3DTblEntUAM3, + extern PSC_TBL_ENTRY SAOTblEntUAM3; + #define PSC_TBL_OR_UDIMM3_SAO_AM3 &SAOTblEntUAM3, + extern PSC_TBL_ENTRY ClkDisMapEntUAM3; + #define PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 &ClkDisMapEntUAM3, + extern PSC_TBL_ENTRY S2DTblEntUAM3; + #define PSC_TBL_OR_UDIMM3_S2D_AM3 &S2DTblEntUAM3, + extern PSC_TBL_ENTRY WLPass1SeedEntUAM3; + #define PSC_TBL_OR_UDIMM3_WL_SEED_AM3 &WLPass1SeedEntUAM3, + extern PSC_TBL_ENTRY HWRxEnPass1SeedEntUAM3; + #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_AM3 &HWRxEnPass1SeedEntUAM3, + #endif + #if OPTION_C32_SOCKET_SUPPORT + extern PSC_TBL_ENTRY MaxFreqTblEntUC32; + #define PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 &MaxFreqTblEntUC32, + extern PSC_TBL_ENTRY DramTermTblEntUC32; + #define PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 &DramTermTblEntUC32, + extern PSC_TBL_ENTRY OdtPat1DTblEntUC32; + #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 &OdtPat1DTblEntUC32, + extern PSC_TBL_ENTRY OdtPat2DTblEntUC32; + #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 &OdtPat2DTblEntUC32, + extern PSC_TBL_ENTRY OdtPat3DTblEntUC32; + #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 &OdtPat3DTblEntUC32, + extern PSC_TBL_ENTRY SAOTblEntUC32; + #define PSC_TBL_OR_UDIMM3_SAO_C32 &SAOTblEntUC32, + extern PSC_TBL_ENTRY ClkDisMapEntUC32; + #define PSC_TBL_OR_UDIMM3_CLK_DIS_C32 &ClkDisMapEntUC32, + extern PSC_TBL_ENTRY ClkDisMap3DEntUC32; + #define PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 &ClkDisMap3DEntUC32, + extern PSC_TBL_ENTRY S2DTblEntUC32; + #define PSC_TBL_OR_UDIMM3_S2D_C32 &S2DTblEntUC32, + extern PSC_TBL_ENTRY WLPass1SeedEntUC32; + #define PSC_TBL_OR_UDIMM3_WL_SEED_C32 &WLPass1SeedEntUC32, + extern PSC_TBL_ENTRY HWRxEnPass1SeedEntUC32; + #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_C32 &HWRxEnPass1SeedEntUC32, + #endif + #if OPTION_G34_SOCKET_SUPPORT + extern PSC_TBL_ENTRY MaxFreqTblEntUG34; + #define PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 &MaxFreqTblEntUG34, + extern PSC_TBL_ENTRY DramTermTblEntUG34; + #define PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 &DramTermTblEntUG34, + extern PSC_TBL_ENTRY OdtPat1DTblEntUG34; + #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 &OdtPat1DTblEntUG34, + extern PSC_TBL_ENTRY OdtPat2DTblEntUG34; + #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 &OdtPat2DTblEntUG34, + extern PSC_TBL_ENTRY OdtPat3DTblEntUG34; + #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 &OdtPat3DTblEntUG34, + extern PSC_TBL_ENTRY SAOTblEntUG34; + #define PSC_TBL_OR_UDIMM3_SAO_G34 &SAOTblEntUG34, + extern PSC_TBL_ENTRY ClkDisMapEntUG34; + #define PSC_TBL_OR_UDIMM3_CLK_DIS_G34 &ClkDisMapEntUG34, + extern PSC_TBL_ENTRY S2DTblEntUG34; + #define PSC_TBL_OR_UDIMM3_S2D_G34 &S2DTblEntUG34, + extern PSC_TBL_ENTRY WLPass1SeedEntUG34; + #define PSC_TBL_OR_UDIMM3_WL_SEED_G34 &WLPass1SeedEntUG34, + extern PSC_TBL_ENTRY HWRxEnPass1SeedEntUG34; + #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_G34 &HWRxEnPass1SeedEntUG34, + #endif + #endif + #if OPTION_RDIMMS + #if OPTION_C32_SOCKET_SUPPORT + extern PSC_TBL_ENTRY MaxFreqTblEntRC32; + #define PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 &MaxFreqTblEntRC32, + extern PSC_TBL_ENTRY DramTermTblEntRC32; + #define PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 &DramTermTblEntRC32, + extern PSC_TBL_ENTRY OdtPat1DTblEntRC32; + #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 &OdtPat1DTblEntRC32, + extern PSC_TBL_ENTRY OdtPat2DTblEntRC32; + #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 &OdtPat2DTblEntRC32, + extern PSC_TBL_ENTRY OdtPat3DTblEntRC32; + #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 &OdtPat3DTblEntRC32, + extern PSC_TBL_ENTRY SAOTblEntRC32; + #define PSC_TBL_OR_RDIMM3_SAO_C32 &SAOTblEntRC32, + extern PSC_TBL_ENTRY RC2IBTTblEntRC32; + #define PSC_TBL_OR_RDIMM3_RC2IBT_C32 &RC2IBTTblEntRC32, + extern PSC_TBL_ENTRY RC10OpSpdTblEntRC32; + #define PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 &RC10OpSpdTblEntRC32, + extern PSC_TBL_ENTRY ClkDisMapEntRC32; + #define PSC_TBL_OR_RDIMM3_CLK_DIS_C32 &ClkDisMapEntRC32, + extern PSC_TBL_ENTRY S2DTblEntRC32; + #define PSC_TBL_OR_RDIMM3_S2D_C32 &S2DTblEntRC32, + extern PSC_TBL_ENTRY WLPass1SeedEntRC32; + #define PSC_TBL_OR_RDIMM3_WL_SEED_C32 &WLPass1SeedEntRC32, + extern PSC_TBL_ENTRY HWRxEnPass1SeedEntRC32; + #define PSC_TBL_OR_RDIMM3_HWRXEN_SEED_C32 &HWRxEnPass1SeedEntRC32, + #endif + #if OPTION_G34_SOCKET_SUPPORT + extern PSC_TBL_ENTRY MaxFreqTblEntRG34; + #define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 &MaxFreqTblEntRG34, + extern PSC_TBL_ENTRY DramTermTblEntRG34; + #define PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 &DramTermTblEntRG34, + extern PSC_TBL_ENTRY OdtPat1DTblEntRG34; + #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 &OdtPat1DTblEntRG34, + extern PSC_TBL_ENTRY OdtPat2DTblEntRG34; + #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 &OdtPat2DTblEntRG34, + extern PSC_TBL_ENTRY OdtPat3DTblEntRG34; + #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 &OdtPat3DTblEntRG34, + extern PSC_TBL_ENTRY SAOTblEntRG34; + #define PSC_TBL_OR_RDIMM3_SAO_G34 &SAOTblEntRG34, + extern PSC_TBL_ENTRY RC2IBTTblEntRG34; + #define PSC_TBL_OR_RDIMM3_RC2IBT_G34 &RC2IBTTblEntRG34, + extern PSC_TBL_ENTRY RC10OpSpdTblEntRG34; + #define PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 &RC10OpSpdTblEntRG34, + extern PSC_TBL_ENTRY ClkDisMapEntRG34; + #define PSC_TBL_OR_RDIMM3_CLK_DIS_G34 &ClkDisMapEntRG34, + extern PSC_TBL_ENTRY S2DTblEntRG34; + #define PSC_TBL_OR_RDIMM3_S2D_G34 &S2DTblEntRG34, + extern PSC_TBL_ENTRY WLPass1SeedEntRG34; + #define PSC_TBL_OR_RDIMM3_WL_SEED_G34 &WLPass1SeedEntRG34, + extern PSC_TBL_ENTRY HWRxEnPass1SeedEntRG34; + #define PSC_TBL_OR_RDIMM3_HWRXEN_SEED_G34 &HWRxEnPass1SeedEntRG34, + #endif + #endif + //#if OPTION_SODIMMS + //#endif + #if OPTION_LRDIMMS + // #if OPTION_C32_SOCKET_SUPPORT + // extern PSC_TBL_ENTRY MaxFreqTblEntLRC32; + // #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 &MaxFreqTblEntLRC32, + // extern PSC_TBL_ENTRY DramTermTblEntLRC32; + // #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 &DramTermTblEntLRC32, + // extern PSC_TBL_ENTRY OdtPat1DTblEntRC32; + // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 &OdtPat1DTblEntLRC32, + // extern PSC_TBL_ENTRY OdtPat2DTblEntRC32; + // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32 &OdtPat2DTblEntLRC32, + // extern PSC_TBL_ENTRY OdtPat3DTblEntRC32; + // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 &OdtPat3DTblEntLRC32, + // extern PSC_TBL_ENTRY SAOTblEntRC32; + // #define PSC_TBL_OR_LRDIMM3_SAO_C32 &SAOTblEntLRC32, + // extern PSC_TBL_ENTRY IBTTblEntLRC32; + // #define PSC_TBL_OR_LRDIMM3_IBT_C32 &IBTTblEntLRC32, + // extern PSC_TBL_ENTRY ClkDisMapEntLRC32; + // #define PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 &ClkDisMapEntLRC32, + // extern PSC_TBL_ENTRY S2DTblEntLRC32; + // #define PSC_TBL_OR_LRDIMM3_S2D_C32 &S2DTblEntLRC32, + // #endif + #if OPTION_G34_SOCKET_SUPPORT + extern PSC_TBL_ENTRY MaxFreqTblEntLRG34; + #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 &MaxFreqTblEntLRG34, + extern PSC_TBL_ENTRY DramTermTblEntLRG34; + #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 &DramTermTblEntLRG34, + extern PSC_TBL_ENTRY OdtPat1DTblEntLRG34; + #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 &OdtPat1DTblEntLRG34, + extern PSC_TBL_ENTRY OdtPat2DTblEntLRG34; + #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34 &OdtPat2DTblEntLRG34, + extern PSC_TBL_ENTRY OdtPat3DTblEntLRG34; + #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 &OdtPat3DTblEntLRG34, + extern PSC_TBL_ENTRY SAOTblEntLRG34; + #define PSC_TBL_OR_LRDIMM3_SAO_G34 &SAOTblEntLRG34, + extern PSC_TBL_ENTRY IBTTblEntLRG34; + #define PSC_TBL_OR_LRDIMM3_IBT_G34 &IBTTblEntLRG34, + extern PSC_TBL_ENTRY ClkDisMapEntLRG34; + #define PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 &ClkDisMapEntLRG34, + extern PSC_TBL_ENTRY S2DTblEntLRG34; + #define PSC_TBL_OR_LRDIMM3_S2D_G34 &S2DTblEntLRG34, + extern PSC_TBL_ENTRY WLPass1SeedEntLRG34; + #define PSC_TBL_OR_LRDIMM3_WL_SEED_G34 &WLPass1SeedEntLRG34, + extern PSC_TBL_ENTRY HWRxEnPass1SeedEntLRG34; + #define PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_G34 &HWRxEnPass1SeedEntLRG34, + #endif + #endif + extern PSC_TBL_ENTRY MR0WrTblEntry; + #define PSC_TBL_OR_MR0_WR &MR0WrTblEntry, + extern PSC_TBL_ENTRY MR0CLTblEntry; + #define PSC_TBL_OR_MR0_CL &MR0CLTblEntry, + extern PSC_TBL_ENTRY OrDdr3CKETriEnt; + #define PSC_TBL_OR_CKE_TRI &OrDdr3CKETriEnt, + extern PSC_TBL_ENTRY OrDdr3ODTTri3DEnt; + #define PSC_TBL_OR_ODT_TRI_3D &OrDdr3ODTTri3DEnt, + extern PSC_TBL_ENTRY OrDdr3ODTTriEnt; + #define PSC_TBL_OR_ODT_TRI &OrDdr3ODTTriEnt, + extern PSC_TBL_ENTRY OrUDdr3CSTriEnt; + #define PSC_TBL_OR_UDIMM3_CS_TRI &OrUDdr3CSTriEnt, + extern PSC_TBL_ENTRY OrDdr3CSTriEnt; + #define PSC_TBL_OR_CS_TRI &OrDdr3CSTriEnt, + extern PSC_TBL_ENTRY OrLRDdr3ODTTri3DEnt; + #define PSC_TBL_OR_LRDIMM3_ODT_TRI_3D &OrLRDdr3ODTTri3DEnt, + extern PSC_TBL_ENTRY OrLRDdr3ODTTriEnt; + #define PSC_TBL_OR_LRDIMM3_ODT_TRI &OrLRDdr3ODTTriEnt, + + #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 + #define PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 + #endif + #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 + #define PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 + #endif + #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 + #define PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 + #endif + #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 + #define PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 + #endif + #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 + #define PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 + #endif + #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 + #define PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 + #endif + #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 + #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 + #endif + #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 + #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 + #endif + #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 + #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 + #endif + #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 + #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 + #endif + #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 + #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 + #endif + #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 + #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 + #endif + #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 + #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 + #endif + #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 + #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 + #endif + #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 + #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 + #endif + #ifndef PSC_TBL_OR_UDIMM3_SAO_AM3 + #define PSC_TBL_OR_UDIMM3_SAO_AM3 + #endif + #ifndef PSC_TBL_OR_UDIMM3_SAO_C32 + #define PSC_TBL_OR_UDIMM3_SAO_C32 + #endif + #ifndef PSC_TBL_OR_UDIMM3_SAO_G34 + #define PSC_TBL_OR_UDIMM3_SAO_G34 + #endif + #ifndef PSC_TBL_OR_UDIMM3_S2D_AM3 + #define PSC_TBL_OR_UDIMM3_S2D_AM3 + #endif + #ifndef PSC_TBL_OR_UDIMM3_S2D_C32 + #define PSC_TBL_OR_UDIMM3_S2D_C32 + #endif + #ifndef PSC_TBL_OR_UDIMM3_S2D_G34 + #define PSC_TBL_OR_UDIMM3_S2D_G34 + #endif + #ifndef PSC_TBL_OR_UDIMM3_WL_SEED_AM3 + #define PSC_TBL_OR_UDIMM3_WL_SEED_AM3 + #endif + #ifndef PSC_TBL_OR_UDIMM3_WL_SEED_C32 + #define PSC_TBL_OR_UDIMM3_WL_SEED_C32 + #endif + #ifndef PSC_TBL_OR_UDIMM3_WL_SEED_G34 + #define PSC_TBL_OR_UDIMM3_WL_SEED_G34 + #endif + #ifndef PSC_TBL_OR_UDIMM3_HWRXEN_SEED_AM3 + #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_AM3 + #endif + #ifndef PSC_TBL_OR_UDIMM3_HWRXEN_SEED_C32 + #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_C32 + #endif + #ifndef PSC_TBL_OR_UDIMM3_HWRXEN_SEED_G34 + #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_G34 + #endif + #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3 + #define PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3 + #endif + #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 + #define PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 + #endif + #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 + #define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 + #endif + #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3 + #define PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3 + #endif + #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 + #define PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 + #endif + #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 + #define PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 + #endif + #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 + #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 + #endif + #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 + #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 + #endif + #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 + #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 + #endif + #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3 + #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3 + #endif + #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 + #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 + #endif + #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 + #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 + #endif + #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 + #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 + #endif + #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 + #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 + #endif + #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 + #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 + #endif + #ifndef PSC_TBL_OR_RDIMM3_SAO_AM3 + #define PSC_TBL_OR_RDIMM3_SAO_AM3 + #endif + #ifndef PSC_TBL_OR_RDIMM3_SAO_C32 + #define PSC_TBL_OR_RDIMM3_SAO_C32 + #endif + #ifndef PSC_TBL_OR_RDIMM3_SAO_G34 + #define PSC_TBL_OR_RDIMM3_SAO_G34 + #endif + #ifndef PSC_TBL_OR_RDIMM3_S2D_AM3 + #define PSC_TBL_OR_RDIMM3_S2D_AM3 + #endif + #ifndef PSC_TBL_OR_RDIMM3_S2D_C32 + #define PSC_TBL_OR_RDIMM3_S2D_C32 + #endif + #ifndef PSC_TBL_OR_RDIMM3_S2D_G34 + #define PSC_TBL_OR_RDIMM3_S2D_G34 + #endif + #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_AM3 + #define PSC_TBL_OR_RDIMM3_RC2IBT_AM3 + #endif + #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_C32 + #define PSC_TBL_OR_RDIMM3_RC2IBT_C32 + #endif + #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_G34 + #define PSC_TBL_OR_RDIMM3_RC2IBT_G34 + #endif + #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3 + #define PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3 + #endif + #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 + #define PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 + #endif + #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 + #define PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 + #endif + #ifndef PSC_TBL_OR_RDIMM3_WL_SEED_AM3 + #define PSC_TBL_OR_RDIMM3_WL_SEED_AM3 + #endif + #ifndef PSC_TBL_OR_RDIMM3_WL_SEED_C32 + #define PSC_TBL_OR_RDIMM3_WL_SEED_C32 + #endif + #ifndef PSC_TBL_OR_RDIMM3_WL_SEED_G34 + #define PSC_TBL_OR_RDIMM3_WL_SEED_G34 + #endif + #ifndef PSC_TBL_OR_RDIMM3_HWRXEN_SEED_AM3 + #define PSC_TBL_OR_RDIMM3_HWRXEN_SEED_AM3 + #endif + #ifndef PSC_TBL_OR_RDIMM3_HWRXEN_SEED_C32 + #define PSC_TBL_OR_RDIMM3_HWRXEN_SEED_C32 + #endif + #ifndef PSC_TBL_OR_RDIMM3_HWRXEN_SEED_G34 + #define PSC_TBL_OR_RDIMM3_HWRXEN_SEED_G34 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 + #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 + #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 + #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 + #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 + #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 + #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32 + #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34 + #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 + #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 + #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_SAO_C32 + #define PSC_TBL_OR_LRDIMM3_SAO_C32 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_SAO_G34 + #define PSC_TBL_OR_LRDIMM3_SAO_G34 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_S2D_C32 + #define PSC_TBL_OR_LRDIMM3_S2D_C32 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_S2D_G34 + #define PSC_TBL_OR_LRDIMM3_S2D_G34 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_IBT_C32 + #define PSC_TBL_OR_LRDIMM3_IBT_C32 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_IBT_G34 + #define PSC_TBL_OR_LRDIMM3_IBT_G34 + #endif + #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 + #define PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 + #endif + #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_C32 + #define PSC_TBL_OR_UDIMM3_CLK_DIS_C32 + #endif + #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 + #define PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 + #endif + #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_G34 + #define PSC_TBL_OR_UDIMM3_CLK_DIS_G34 + #endif + #ifndef PSC_TBL_OR_RDIMM3_CLK_DIS_C32 + #define PSC_TBL_OR_RDIMM3_CLK_DIS_C32 + #endif + #ifndef PSC_TBL_OR_RDIMM3_CLK_DIS_G34 + #define PSC_TBL_OR_RDIMM3_CLK_DIS_G34 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 + #define PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 + #define PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_WL_SEED_AM3 + #define PSC_TBL_OR_LRDIMM3_WL_SEED_AM3 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_WL_SEED_C32 + #define PSC_TBL_OR_LRDIMM3_WL_SEED_C32 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_WL_SEED_G34 + #define PSC_TBL_OR_LRDIMM3_WL_SEED_G34 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_AM3 + #define PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_AM3 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_C32 + #define PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_C32 + #endif + #ifndef PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_G34 + #define PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_G34 + #endif + + + PSC_TBL_ENTRY* memPSCTblMaxFreqArrayOR[] = { + PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 + PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 + PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 + PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3 + PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 + PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 + PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 + PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 + PSC_TBL_END + }; + + PSC_TBL_ENTRY* memPSCTblDramTermArrayOR[] = { + PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 + PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 + PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 + PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3 + PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 + PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 + PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 + PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 + PSC_TBL_END + }; + + PSC_TBL_ENTRY* memPSCTblODTPatArrayOR[] = { + PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 + PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 + PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 + PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 + PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3 + PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 + PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 + PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 + PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 + PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 + PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 + PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 + PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 + PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32 + PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 + PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 + PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 + PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 + PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 + PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 + PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 + PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 + PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34 + PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 + PSC_TBL_END + }; + + PSC_TBL_ENTRY* memPSCTblSAOArrayOR[] = { + PSC_TBL_OR_UDIMM3_SAO_AM3 + PSC_TBL_OR_UDIMM3_SAO_C32 + PSC_TBL_OR_UDIMM3_SAO_G34 + PSC_TBL_OR_RDIMM3_SAO_AM3 + PSC_TBL_OR_RDIMM3_SAO_C32 + PSC_TBL_OR_RDIMM3_SAO_G34 + PSC_TBL_OR_LRDIMM3_SAO_C32 + PSC_TBL_OR_LRDIMM3_SAO_G34 + PSC_TBL_END + }; + + PSC_TBL_ENTRY* memPSCTblS2DArrayOR[] = { + PSC_TBL_OR_UDIMM3_S2D_AM3 + PSC_TBL_OR_UDIMM3_S2D_C32 + PSC_TBL_OR_UDIMM3_S2D_G34 + PSC_TBL_OR_RDIMM3_S2D_AM3 + PSC_TBL_OR_RDIMM3_S2D_C32 + PSC_TBL_OR_RDIMM3_S2D_G34 + PSC_TBL_OR_LRDIMM3_S2D_C32 + PSC_TBL_OR_LRDIMM3_S2D_G34 + PSC_TBL_END + }; + + PSC_TBL_ENTRY* memPSCTblMR0WRArrayOR[] = { + PSC_TBL_OR_MR0_WR + PSC_TBL_END + }; + + PSC_TBL_ENTRY* memPSCTblMR0CLArrayOR[] = { + PSC_TBL_OR_MR0_CL + PSC_TBL_END + }; + + PSC_TBL_ENTRY* memPSCTblRC2IBTArrayOR[] = { + PSC_TBL_OR_RDIMM3_RC2IBT_AM3 + PSC_TBL_OR_RDIMM3_RC2IBT_C32 + PSC_TBL_OR_RDIMM3_RC2IBT_G34 + PSC_TBL_END + }; + + PSC_TBL_ENTRY* memPSCTblRC10OPSPDArrayOR[] = { + PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3 + PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 + PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 + PSC_TBL_END + }; + + PSC_TBL_ENTRY* memPSCTblLRIBTArrayOR[] = { + PSC_TBL_OR_LRDIMM3_IBT_C32 + PSC_TBL_OR_LRDIMM3_IBT_G34 + PSC_TBL_END + }; + + PSC_TBL_ENTRY* memPSCTblGenArrayOR[] = { + PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 + PSC_TBL_OR_UDIMM3_CLK_DIS_C32 + PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 + PSC_TBL_OR_UDIMM3_CLK_DIS_G34 + PSC_TBL_OR_RDIMM3_CLK_DIS_C32 + PSC_TBL_OR_RDIMM3_CLK_DIS_G34 + PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 + PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 + PSC_TBL_OR_CKE_TRI + PSC_TBL_OR_ODT_TRI_3D + PSC_TBL_OR_ODT_TRI + PSC_TBL_OR_LRDIMM3_ODT_TRI_3D + PSC_TBL_OR_LRDIMM3_ODT_TRI + PSC_TBL_OR_UDIMM3_CS_TRI + PSC_TBL_OR_CS_TRI + PSC_TBL_END + }; + + PSC_TBL_ENTRY* memPSCTblWLSeedArrayOR[] = { + PSC_TBL_OR_UDIMM3_WL_SEED_AM3 + PSC_TBL_OR_UDIMM3_WL_SEED_C32 + PSC_TBL_OR_UDIMM3_WL_SEED_G34 + PSC_TBL_OR_RDIMM3_WL_SEED_AM3 + PSC_TBL_OR_RDIMM3_WL_SEED_C32 + PSC_TBL_OR_RDIMM3_WL_SEED_G34 + PSC_TBL_OR_LRDIMM3_WL_SEED_AM3 + PSC_TBL_OR_LRDIMM3_WL_SEED_C32 + PSC_TBL_OR_LRDIMM3_WL_SEED_G34 + PSC_TBL_END + }; + + PSC_TBL_ENTRY* memPSCTblHWRxEnSeedArrayOR[] = { + PSC_TBL_OR_UDIMM3_HWRXEN_SEED_AM3 + PSC_TBL_OR_UDIMM3_HWRXEN_SEED_C32 + PSC_TBL_OR_UDIMM3_HWRXEN_SEED_G34 + PSC_TBL_OR_RDIMM3_HWRXEN_SEED_AM3 + PSC_TBL_OR_RDIMM3_HWRXEN_SEED_C32 + PSC_TBL_OR_RDIMM3_HWRXEN_SEED_G34 + PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_AM3 + PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_C32 + PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_G34 + PSC_TBL_END + }; + + MEM_PSC_TABLE_BLOCK memPSCTblBlockOr = { + (PSC_TBL_ENTRY **)&memPSCTblMaxFreqArrayOR, + (PSC_TBL_ENTRY **)&memPSCTblDramTermArrayOR, + (PSC_TBL_ENTRY **)&memPSCTblODTPatArrayOR, + (PSC_TBL_ENTRY **)&memPSCTblSAOArrayOR, + (PSC_TBL_ENTRY **)&memPSCTblMR0WRArrayOR, + (PSC_TBL_ENTRY **)&memPSCTblMR0CLArrayOR, + (PSC_TBL_ENTRY **)&memPSCTblRC2IBTArrayOR, + (PSC_TBL_ENTRY **)&memPSCTblRC10OPSPDArrayOR, + (PSC_TBL_ENTRY **)&memPSCTblLRIBTArrayOR, + NULL, + NULL, + (PSC_TBL_ENTRY **)&memPSCTblGenArrayOR, + (PSC_TBL_ENTRY **)&memPSCTblS2DArrayOR, + (PSC_TBL_ENTRY **)&memPSCTblWLSeedArrayOR, + (PSC_TBL_ENTRY **)&memPSCTblHWRxEnSeedArrayOR + }; + + extern MEM_PSC_FLOW MemPGetMaxFreqSupported; + #define PSC_FLOW_OR_MAX_FREQ MemPGetMaxFreqSupported + extern MEM_PSC_FLOW MemPGetRttNomWr; + #define PSC_FLOW_OR_DRAM_TERM MemPGetRttNomWr + extern MEM_PSC_FLOW MemPGetODTPattern; + #define PSC_FLOW_OR_ODT_PATTERN MemPGetODTPattern + extern MEM_PSC_FLOW MemPGetSAO; + #define PSC_FLOW_OR_SAO MemPGetSAO + extern MEM_PSC_FLOW MemPGetMR0WrCL; + #define PSC_FLOW_OR_MR0_WRCL MemPGetMR0WrCL + extern MEM_PSC_FLOW MemPGetTrainingSeeds; + #define PSC_FLOW_OR_SEED MemPGetTrainingSeeds + #if OPTION_RDIMMS + extern MEM_PSC_FLOW MemPGetRC2IBT; + #define PSC_FLOW_OR_RC2_IBT MemPGetRC2IBT + extern MEM_PSC_FLOW MemPGetRC10OpSpd; + #define PSC_FLOW_OR_RC10_OPSPD MemPGetRC10OpSpd + #endif + #if OPTION_LRDIMMS + extern MEM_PSC_FLOW MemPGetLRIBT; + #define PSC_FLOW_OR_LR_IBT MemPGetLRIBT + extern MEM_PSC_FLOW MemPGetLRNPR; + #define PSC_FLOW_OR_LR_NPR MemPGetLRNPR + extern MEM_PSC_FLOW MemPGetLRNLR; + #define PSC_FLOW_OR_LR_NLR MemPGetLRNLR + #endif + #ifndef PSC_FLOW_OR_MAX_FREQ + #define PSC_FLOW_OR_MAX_FREQ MEM_PSC_FLOW_DEFTRUE + #endif + #ifndef PSC_FLOW_OR_DRAM_TERM + #define PSC_FLOW_OR_DRAM_TERM MEM_PSC_FLOW_DEFTRUE + #endif + #ifndef PSC_FLOW_OR_ODT_PATTERN + #define PSC_FLOW_OR_ODT_PATTERN MEM_PSC_FLOW_DEFTRUE + #endif + #ifndef PSC_FLOW_OR_SAO + #define PSC_FLOW_OR_SAO MEM_PSC_FLOW_DEFTRUE + #endif + #ifndef PSC_FLOW_OR_MR0_WRCL + #define PSC_FLOW_OR_MR0_WRCL MEM_PSC_FLOW_DEFTRUE + #endif + #ifndef PSC_FLOW_OR_RC2_IBT + #define PSC_FLOW_OR_RC2_IBT MEM_PSC_FLOW_DEFTRUE + #endif + #ifndef PSC_FLOW_OR_RC10_OPSPD + #define PSC_FLOW_OR_RC10_OPSPD MEM_PSC_FLOW_DEFTRUE + #endif + #ifndef PSC_FLOW_OR_LR_IBT + #define PSC_FLOW_OR_LR_IBT MEM_PSC_FLOW_DEFTRUE + #endif + #ifndef PSC_FLOW_OR_LR_NPR + #define PSC_FLOW_OR_LR_NPR MEM_PSC_FLOW_DEFTRUE + #endif + #ifndef PSC_FLOW_OR_LR_NLR + #define PSC_FLOW_OR_LR_NLR MEM_PSC_FLOW_DEFTRUE + #endif + #ifndef PSC_FLOW_OR_S2D + #define PSC_FLOW_OR_S2D MEM_PSC_FLOW_DEFTRUE + #endif + #ifndef PSC_FLOW_OR_SEED + #define PSC_FLOW_OR_SEED MEM_PSC_FLOW_DEFTRUE + #endif + + MEM_PSC_FLOW_BLOCK memPlatSpecFlowOR = { + &memPSCTblBlockOr, + PSC_FLOW_OR_MAX_FREQ, + PSC_FLOW_OR_DRAM_TERM, + PSC_FLOW_OR_ODT_PATTERN, + PSC_FLOW_OR_SAO, + PSC_FLOW_OR_MR0_WRCL, + PSC_FLOW_OR_RC2_IBT, + PSC_FLOW_OR_RC10_OPSPD, + PSC_FLOW_OR_LR_IBT, + PSC_FLOW_OR_LR_NPR, + PSC_FLOW_OR_LR_NLR, + PSC_FLOW_OR_S2D, + PSC_FLOW_OR_SEED + }; + #define MEM_PSC_FLOW_BLOCK_OR &memPlatSpecFlowOR, + #else + #define MEM_PSC_FLOW_BLOCK_OR + #endif + + #define PSC_TBL_TN_UDIMM3_S2D_FM2 + #define PSC_TBL_TN_SODIMM3_S2D_FS1 + #define PSC_TBL_TN_SODIMM3_S2D_FP2 + #define PSC_TBL_TN_SODIMM3_S2D_FM2 + #if OPTION_MEMCTLR_TN + #if OPTION_FS1_SOCKET_SUPPORT + extern PSC_TBL_ENTRY TNClkDisMapEntSOFS1; + #define PSC_TBL_TN_CLK_DIS_FS1 &TNClkDisMapEntSOFS1, + extern PSC_TBL_ENTRY TNSODdr3ODTTriEntFS1; + #define PSC_TBL_TN_ODT_TRI_FS1 &TNSODdr3ODTTriEntFS1, + extern PSC_TBL_ENTRY TNSODdr3CSTriEntFS1; + #define PSC_TBL_TN_CS_TRI_FS1 &TNSODdr3CSTriEntFS1, + #endif + #if OPTION_FM2_SOCKET_SUPPORT + extern PSC_TBL_ENTRY TNClkDisMapEntUFM2; + #define PSC_TBL_TN_CLK_DIS_FM2 &TNClkDisMapEntUFM2, + extern PSC_TBL_ENTRY TNUDdr3ODTTriEntFM2; + #define PSC_TBL_TN_ODT_TRI_FM2 &TNUDdr3ODTTriEntFM2, + extern PSC_TBL_ENTRY TNUDdr3CSTriEntFM2; + #define PSC_TBL_TN_CS_TRI_FM2 &TNUDdr3CSTriEntFM2, + #endif + #if OPTION_FP2_SOCKET_SUPPORT + extern PSC_TBL_ENTRY TNClkDisMapEntSOFP2; + #define PSC_TBL_TN_CLK_DIS_FP2 &TNClkDisMapEntSOFP2, + extern PSC_TBL_ENTRY TNSODdr3ODTTriEntFP2; + #define PSC_TBL_TN_ODT_TRI_FP2 &TNSODdr3ODTTriEntFP2, + extern PSC_TBL_ENTRY TNSODdr3CSTriEntFP2; + #define PSC_TBL_TN_CS_TRI_FP2 &TNSODdr3CSTriEntFP2, + #endif + #if OPTION_UDIMMS + extern PSC_TBL_ENTRY TNMaxFreqTblEntU; + #define PSC_TBL_TN_UDIMM3_MAX_FREQ &TNMaxFreqTblEntU, + extern PSC_TBL_ENTRY TNDramTermTblEntU; + #define PSC_TBL_TN_UDIMM3_DRAM_TERM &TNDramTermTblEntU, + extern PSC_TBL_ENTRY TNSAOTblEntU3; + #define PSC_TBL_TN_UDIMM3_SAO &TNSAOTblEntU3, + #undef PSC_TBL_TN_UDIMM3_S2D_FM2 + extern PSC_TBL_ENTRY ex891_1 ; + #define PSC_TBL_TN_UDIMM3_S2D_FM2 &ex891_1 , + #endif + #if OPTION_SODIMMS + #if OPTION_FS1_SOCKET_SUPPORT + extern PSC_TBL_ENTRY TNSAOTblEntSO3; + #define PSC_TBL_TN_SODIMM3_SAO &TNSAOTblEntSO3, + extern PSC_TBL_ENTRY TNDramTermTblEntSO; + #define PSC_TBL_TN_SODIMM3_DRAM_TERM &TNDramTermTblEntSO, + extern PSC_TBL_ENTRY TNMaxFreqTblEntSO; + #define PSC_TBL_TN_SODIMM3_MAX_FREQ &TNMaxFreqTblEntSO, + #undef PSC_TBL_TN_SODIMM3_S2D_FS1 + #define PSC_TBL_TN_SODIMM3_S2D_FS1 + #endif + #if OPTION_FM2_SOCKET_SUPPORT + extern PSC_TBL_ENTRY TNSAOTblEntSO3; + #define PSC_TBL_TN_SODIMM3_SAO &TNSAOTblEntSO3, + extern PSC_TBL_ENTRY TNDramTermTblEntSO; + #define PSC_TBL_TN_SODIMM3_DRAM_TERM &TNDramTermTblEntSO, + extern PSC_TBL_ENTRY TNMaxFreqTblEntSO; + #define PSC_TBL_TN_SODIMM3_MAX_FREQ &TNMaxFreqTblEntSO, + #undef PSC_TBL_TN_SODIMM3_S2D_FM2 + extern PSC_TBL_ENTRY ex891_1 ; + #define PSC_TBL_TN_SODIMM3_S2D_FM2 &ex891_1 , + #endif + #if OPTION_FP2_SOCKET_SUPPORT + extern PSC_TBL_ENTRY TNSAOTblEntSODWNSO3; + #define PSC_TBL_TN_SODWN_SODIMM3_SAO &TNSAOTblEntSODWNSO3, + extern PSC_TBL_ENTRY TNDramTermTblEntSODWNSO; + #define PSC_TBL_TN_SODWN_SODIMM3_DRAM_TERM &TNDramTermTblEntSODWNSO, + extern PSC_TBL_ENTRY TNMaxFreqTblEntSODWNSO; + #define PSC_TBL_TN_SODWN_SODIMM3_MAX_FREQ &TNMaxFreqTblEntSODWNSO, + #undef PSC_TBL_TN_SODIMM3_S2D_FP2 + #define PSC_TBL_TN_SODIMM3_S2D_FP2 + #endif + #endif + extern PSC_TBL_ENTRY TNMR0WrTblEntry; + extern PSC_TBL_ENTRY TNMR0CLTblEntry; + extern PSC_TBL_ENTRY TNDdr3CKETriEnt; + extern PSC_TBL_ENTRY TNOdtPatTblEnt; + + + #ifndef PSC_TBL_TN_SODIMM3_MAX_FREQ + #define PSC_TBL_TN_SODIMM3_MAX_FREQ + #endif + #ifndef PSC_TBL_TN_SODWN_SODIMM3_MAX_FREQ + #define PSC_TBL_TN_SODWN_SODIMM3_MAX_FREQ + #endif + #ifndef PSC_TBL_TN_UDIMM3_MAX_FREQ + #define PSC_TBL_TN_UDIMM3_MAX_FREQ + #endif + #ifndef PSC_TBL_TN_UDIMM3_DRAM_TERM + #define PSC_TBL_TN_UDIMM3_DRAM_TERM + #endif + #ifndef PSC_TBL_TN_SODIMM3_DRAM_TERM + #define PSC_TBL_TN_SODIMM3_DRAM_TERM + #endif + #ifndef PSC_TBL_TN_SODWN_SODIMM3_DRAM_TERM + #define PSC_TBL_TN_SODWN_SODIMM3_DRAM_TERM + #endif + #ifndef PSC_TBL_TN_SODIMM3_SAO + #define PSC_TBL_TN_SODIMM3_SAO + #endif + #ifndef PSC_TBL_TN_SODWN_SODIMM3_SAO + #define PSC_TBL_TN_SODWN_SODIMM3_SAO + #endif + #ifndef PSC_TBL_TN_UDIMM3_SAO + #define PSC_TBL_TN_UDIMM3_SAO + #endif + #ifndef PSC_TBL_TN_CLK_DIS_FM2 + #define PSC_TBL_TN_CLK_DIS_FM2 + #endif + #ifndef PSC_TBL_TN_ODT_TRI_FM2 + #define PSC_TBL_TN_ODT_TRI_FM2 + #endif + #ifndef PSC_TBL_TN_CS_TRI_FM2 + #define PSC_TBL_TN_CS_TRI_FM2 + #endif + #ifndef PSC_TBL_TN_CLK_DIS_FS1 + #define PSC_TBL_TN_CLK_DIS_FS1 + #endif + #ifndef PSC_TBL_TN_ODT_TRI_FS1 + #define PSC_TBL_TN_ODT_TRI_FS1 + #endif + #ifndef PSC_TBL_TN_CS_TRI_FS1 + #define PSC_TBL_TN_CS_TRI_FS1 + #endif + #ifndef PSC_TBL_TN_CLK_DIS_FP2 + #define PSC_TBL_TN_CLK_DIS_FP2 + #endif + #ifndef PSC_TBL_TN_ODT_TRI_FP2 + #define PSC_TBL_TN_ODT_TRI_FP2 + #endif + #ifndef PSC_TBL_TN_CS_TRI_FP2 + #define PSC_TBL_TN_CS_TRI_FP2 + #endif + + PSC_TBL_ENTRY* memPSCTblMaxFreqArrayTN[] = { + PSC_TBL_TN_SODIMM3_MAX_FREQ + PSC_TBL_TN_SODWN_SODIMM3_MAX_FREQ + PSC_TBL_TN_UDIMM3_MAX_FREQ + PSC_TBL_END + }; + + PSC_TBL_ENTRY* memPSCTblDramTermArrayTN[] = { + PSC_TBL_TN_UDIMM3_DRAM_TERM + PSC_TBL_TN_SODIMM3_DRAM_TERM + PSC_TBL_TN_SODWN_SODIMM3_DRAM_TERM + PSC_TBL_END + }; + + PSC_TBL_ENTRY* memPSCTblODTPatArrayTN[] = { + &TNOdtPatTblEnt, + PSC_TBL_END + }; + + PSC_TBL_ENTRY* memPSCTblSAOArrayTN[] = { + PSC_TBL_TN_SODIMM3_SAO + PSC_TBL_TN_SODWN_SODIMM3_SAO + PSC_TBL_TN_UDIMM3_SAO + PSC_TBL_END + }; + + PSC_TBL_ENTRY* memPSCTblMR0WRArrayTN[] = { + &TNMR0WrTblEntry, + PSC_TBL_END + }; + + PSC_TBL_ENTRY* memPSCTblMR0CLArrayTN[] = { + &TNMR0CLTblEntry, + PSC_TBL_END + }; + + PSC_TBL_ENTRY* memPSCTblGenArrayTN[] = { + &TNDdr3CKETriEnt, + PSC_TBL_TN_CLK_DIS_FM2 + PSC_TBL_TN_ODT_TRI_FM2 + PSC_TBL_TN_CS_TRI_FM2 + PSC_TBL_TN_CLK_DIS_FS1 + PSC_TBL_TN_ODT_TRI_FS1 + PSC_TBL_TN_CS_TRI_FS1 + PSC_TBL_TN_CLK_DIS_FP2 + PSC_TBL_TN_ODT_TRI_FP2 + PSC_TBL_TN_CS_TRI_FP2 + PSC_TBL_END + }; + + PSC_TBL_ENTRY* memPSCTblS2DArrayTN[] = { + PSC_TBL_TN_UDIMM3_S2D_FM2 + PSC_TBL_TN_SODIMM3_S2D_FS1 + PSC_TBL_TN_SODIMM3_S2D_FP2 + PSC_TBL_TN_SODIMM3_S2D_FM2 + PSC_TBL_END + }; + + MEM_PSC_TABLE_BLOCK memPSCTblBlockTN = { + (PSC_TBL_ENTRY **)&memPSCTblMaxFreqArrayTN, + (PSC_TBL_ENTRY **)&memPSCTblDramTermArrayTN, + (PSC_TBL_ENTRY **)&memPSCTblODTPatArrayTN, + (PSC_TBL_ENTRY **)&memPSCTblSAOArrayTN, + (PSC_TBL_ENTRY **)&memPSCTblMR0WRArrayTN, + (PSC_TBL_ENTRY **)&memPSCTblMR0CLArrayTN, + NULL, + NULL, + NULL, + NULL, + NULL, + (PSC_TBL_ENTRY **)&memPSCTblGenArrayTN, + (PSC_TBL_ENTRY **)&memPSCTblS2DArrayTN, + NULL, + NULL + }; + + extern MEM_PSC_FLOW MemPGetMaxFreqSupported; + extern MEM_PSC_FLOW MemPGetRttNomWr; + extern MEM_PSC_FLOW MemPGetODTPattern; + extern MEM_PSC_FLOW MemPGetSAO; + extern MEM_PSC_FLOW MemPGetMR0WrCL; + + MEM_PSC_FLOW_BLOCK memPlatSpecFlowTN = { + &memPSCTblBlockTN, + MemPGetMaxFreqSupported, + MemPGetRttNomWr, + MemPGetODTPattern, + MemPGetSAO, + MemPGetMR0WrCL, + MEM_PSC_FLOW_DEFTRUE, + MEM_PSC_FLOW_DEFTRUE, + MEM_PSC_FLOW_DEFTRUE, + MEM_PSC_FLOW_DEFTRUE, + MEM_PSC_FLOW_DEFTRUE, + MEM_PSC_FLOW_DEFTRUE, + MEM_PSC_FLOW_DEFTRUE + }; + #define MEM_PSC_FLOW_BLOCK_TN &memPlatSpecFlowTN, + #else + #define MEM_PSC_FLOW_BLOCK_TN + #endif + + + MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = { + MEM_PSC_FLOW_BLOCK_OR + MEM_PSC_FLOW_BLOCK_TN + MEM_PSC_FLOW_BLOCK_END + }; + + /*--------------------------------------------------------------------------------------------------- + * + * LRDIMM CONTROL + * + *--------------------------------------------------------------------------------------------------- + */ + #if (OPTION_LRDIMMS == TRUE) + #if ((OPTION_MEMCTLR_OR == TRUE) + #define MEM_TECH_FEATURE_LRDIMM_INIT &MemTLrdimmConstructor3 + #else //#if ((OPTION_MEMCTLR_OR == FALSE) + #define MEM_TECH_FEATURE_LRDIMM_INIT MemTFeatDef + #endif + #else //#if (OPTION_LRDIMMS == FALSE) + #define MEM_TECH_FEATURE_LRDIMM_INIT MemTFeatDef + #endif + MEM_TECH_LRDIMM memLrdimmSupported = { + MEM_TECH_LRDIMM_STRUCT_VERSION, + MEM_TECH_FEATURE_LRDIMM_INIT + }; +#else + /*--------------------------------------------------------------------------------------------------- + * MAIN FLOW CONTROL + * + * + *--------------------------------------------------------------------------------------------------- + */ + MEM_FLOW_CFG* memFlowControlInstalled[] = { + NULL + }; + /*--------------------------------------------------------------------------------------------------- + * NB TRAINING FLOW CONTROL + * + * + *--------------------------------------------------------------------------------------------------- + */ + OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = { // Training flow control + NULL + }; + /*--------------------------------------------------------------------------------------------------- + * DEFAULT TECHNOLOGY BLOCK + * + * + *--------------------------------------------------------------------------------------------------- + */ + MEM_TECH_CONSTRUCTOR* memTechInstalled[] = { // Types of technology installed + NULL + }; + + /*--------------------------------------------------------------------------------------------------- + * DEFAULT TECHNOLOGY MAP + * + * + *--------------------------------------------------------------------------------------------------- + */ + UINT8 MemoryTechnologyMap[MAX_SOCKETS_SUPPORTED] = {0, 0, 0, 0, 0, 0, 0, 0}; + + /*--------------------------------------------------------------------------------------------------- + * DEFAULT MAIN FEATURE BLOCK + *--------------------------------------------------------------------------------------------------- + */ + MEM_FEAT_BLOCK_MAIN MemFeatMain = { + NULL + }; + + /*--------------------------------------------------------------------------------------------------- + * DEFAULT NORTHBRIDGE SUPPORT LIST + * + * + *--------------------------------------------------------------------------------------------------- + */ + #if (OPTION_MEMCTLR_DR == TRUE) + #undef MEM_NB_SUPPORT_DR + #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR }, + #endif + #if (OPTION_MEMCTLR_RB == TRUE) + #undef MEM_NB_SUPPORT_RB + #define MEM_NB_SUPPORT_RB { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB, MEM_IDENDIMM_RB }, + #endif + #if (OPTION_MEMCTLR_DA == TRUE) + #undef MEM_NB_SUPPORT_DA + #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA }, + #endif + #if (OPTION_MEMCTLR_PH == TRUE) + #undef MEM_NB_SUPPORT_PH + #define MEM_NB_SUPPORT_PH { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH, MEM_IDENDIMM_PH }, + #endif + #if (OPTION_MEMCTLR_HY == TRUE) + #undef MEM_NB_SUPPORT_HY + #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY }, + #endif + #if (OPTION_MEMCTLR_C32 == TRUE) + #undef MEM_NB_SUPPORT_C32 + #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 }, + #endif + #if (OPTION_MEMCTLR_LN == TRUE) + #undef MEM_NB_SUPPORT_LN + #define MEM_NB_SUPPORT_LN { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN, MEM_IDENDIMM_LN }, + #endif + #if (OPTION_MEMCTLR_ON == TRUE) + #undef MEM_NB_SUPPORT_ON + #define MEM_NB_SUPPORT_ON { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON, MEM_IDENDIMM_ON }, + #endif + #if (OPTION_MEMCTLR_OR == TRUE) + #undef MEM_NB_SUPPORT_OR + #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR }, + #endif + #if (OPTION_MEMCTLR_TN == TRUE) + #undef MEM_NB_SUPPORT_TN + #define MEM_NB_SUPPORT_TN { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_TN, MEM_IDENDIMM_TN }, + #endif + /*--------------------------------------------------------------------------------------------------- + * DEFAULT Technology Training + * + * + *--------------------------------------------------------------------------------------------------- + */ + #if OPTION_DDR2 + MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2 = { + NULL + }; + MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = { + NULL + }; + #endif + #if OPTION_DDR3 + MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR3 = { + NULL + }; + MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { + NULL + }; + #endif + /*--------------------------------------------------------------------------------------------------- + * DEFAULT Platform Specific list + * + * + *--------------------------------------------------------------------------------------------------- + */ + #if (OPTION_MEMCTLR_DR == TRUE) + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDr[MAX_FF_TYPES] = { + NULL + }; + #endif + #if (OPTION_MEMCTLR_RB == TRUE) + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES] = { + NULL + }; + #endif + #if (OPTION_MEMCTLR_DA == TRUE) + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = { + NULL + }; + #endif + #if (OPTION_MEMCTLR_Ni == TRUE) + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES] = { + NULL + }; + #endif + #if (OPTION_MEMCTLR_PH == TRUE) + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES] = { + NULL + }; + #endif + #if (OPTION_MEMCTLR_LN == TRUE) + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledLN[MAX_FF_TYPES] = { + NULL + }; + #endif + #if (OPTION_MEMCTLR_HY == TRUE) + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = { + NULL + }; + #endif + #if (OPTION_MEMCTLR_OR == TRUE) + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledOr[MAX_FF_TYPES] = { + NULL + }; + #endif + #if (OPTION_MEMCTLR_C32 == TRUE) + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = { + NULL + }; + #endif + #if (OPTION_MEMCTLR_ON == TRUE) + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[MAX_FF_TYPES] = { + NULL + }; + #endif + /*---------------------------------------------------------------------- + * DEFAULT PSCFG DEFINITIONS + * + *---------------------------------------------------------------------- + */ + MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = { + NULL + }; + + /*---------------------------------------------------------------------- + * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION + * + *---------------------------------------------------------------------- + */ + MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = { + NULL + }; + + MEM_TECH_LRDIMM memLrdimmSupported = { + MEM_TECH_LRDIMM_STRUCT_VERSION, + NULL + }; +#endif + +/*--------------------------------------------------------------------------------------------------- + * NORTHBRIDGE SUPPORT LIST + * + * + *--------------------------------------------------------------------------------------------------- + */ +MEM_NB_SUPPORT memNBInstalled[] = { + MEM_NB_SUPPORT_RB + MEM_NB_SUPPORT_DA + MEM_NB_SUPPORT_Ni + MEM_NB_SUPPORT_PH + MEM_NB_SUPPORT_HY + MEM_NB_SUPPORT_LN + MEM_NB_SUPPORT_OR + MEM_NB_SUPPORT_C32 + MEM_NB_SUPPORT_ON + MEM_NB_SUPPORT_TN + MEM_NB_SUPPORT_END +}; + +#endif // _OPTION_MEMORY_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryRecovery.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryRecovery.h new file mode 100644 index 0000000..73e55ff --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryRecovery.h @@ -0,0 +1,89 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Memory option API. + * + * Contains structures and values used to control the Memory option code. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: OPTION + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _OPTION_MEMORY_RECOVERY_H_ +#define _OPTION_MEMORY_RECOVERY_H_ + +#include "mm.h" +#include "mn.h" +#include "mt.h" + +typedef BOOLEAN MEM_REC_NB_CONSTRUCTOR ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ); + +typedef VOID MEM_REC_TECH_CONSTRUCTOR ( + IN OUT MEM_TECH_BLOCK *TechPtr, + IN OUT MEM_NB_BLOCK *NBPtr + ); + +#endif // _OPTION_MEMORY_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryRecoveryInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryRecoveryInstall.h new file mode 100644 index 0000000..13c8755 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryRecoveryInstall.h @@ -0,0 +1,419 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: Memory + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_MEMORY_RECOVERY_INSTALL_H_ +#define _OPTION_MEMORY_RECOVERY_INSTALL_H_ + +#if (AGESA_ENTRY_INIT_RECOVERY == TRUE) + + #if (OPTION_MEMCTLR_DR == TRUE) + extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockDR; + #define MEM_REC_NB_SUPPORT_DR MemRecConstructNBBlockDR, + #else + #define MEM_REC_NB_SUPPORT_DR + #endif + #if (OPTION_MEMCTLR_RB == TRUE) + extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockRb; + #define MEM_REC_NB_SUPPORT_RB MemRecConstructNBBlockRb, + #else + #define MEM_REC_NB_SUPPORT_RB + #endif + #if (OPTION_MEMCTLR_DA == TRUE) + extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockDA; + #define MEM_REC_NB_SUPPORT_DA MemRecConstructNBBlockDA, + #else + #define MEM_REC_NB_SUPPORT_DA + #endif + #if (OPTION_MEMCTLR_NI == TRUE) + extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockNi; + #define MEM_REC_NB_SUPPORT_NI MemRecConstructNBBlockNi, + #else + #define MEM_REC_NB_SUPPORT_NI + #endif + #if (OPTION_MEMCTLR_PH == TRUE) + extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockPh; + #define MEM_REC_NB_SUPPORT_PH MemRecConstructNBBlockPh, + #else + #define MEM_REC_NB_SUPPORT_PH + #endif + #if (OPTION_MEMCTLR_HY == TRUE) + extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockHY; + #define MEM_REC_NB_SUPPORT_HY MemRecConstructNBBlockHY, + #else + #define MEM_REC_NB_SUPPORT_HY + #endif + #if (OPTION_MEMCTLR_C32 == TRUE) + extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockC32; + #define MEM_REC_NB_SUPPORT_C32 MemRecConstructNBBlockC32, + #else + #define MEM_REC_NB_SUPPORT_C32 + #endif + #if (OPTION_MEMCTLR_LN == TRUE) + extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockLN; + #define MEM_REC_NB_SUPPORT_LN MemRecConstructNBBlockLN, + #else + #define MEM_REC_NB_SUPPORT_LN + #endif + #if (OPTION_MEMCTLR_OR == TRUE) + extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockOr; + #define MEM_REC_NB_SUPPORT_OR MemRecConstructNBBlockOr, + #else + #define MEM_REC_NB_SUPPORT_OR + #endif + #if (OPTION_MEMCTLR_ON == TRUE) + extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockON; + #define MEM_REC_NB_SUPPORT_ON MemRecConstructNBBlockON, + #else + #define MEM_REC_NB_SUPPORT_ON + #endif + #if (OPTION_MEMCTLR_TN == TRUE) + extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockTN; + #define MEM_REC_NB_SUPPORT_TN MemRecConstructNBBlockTN, + #else + #define MEM_REC_NB_SUPPORT_TN + #endif + + MEM_REC_NB_CONSTRUCTOR* MemRecNBInstalled[] = { + MEM_REC_NB_SUPPORT_DR + MEM_REC_NB_SUPPORT_RB + MEM_REC_NB_SUPPORT_DA + MEM_REC_NB_SUPPORT_PH + MEM_REC_NB_SUPPORT_HY + MEM_REC_NB_SUPPORT_C32 + MEM_REC_NB_SUPPORT_LN + MEM_REC_NB_SUPPORT_OR + MEM_REC_NB_SUPPORT_ON + MEM_REC_NB_SUPPORT_NI + MEM_REC_NB_SUPPORT_TN + NULL + }; + + #define MEM_REC_TECH_CONSTRUCTOR_DDR2 + #if (OPTION_DDR3 == TRUE) + extern MEM_REC_TECH_CONSTRUCTOR MemRecConstructTechBlock3; + #define MEM_REC_TECH_CONSTRUCTOR_DDR3 MemRecConstructTechBlock3, + #else + #define MEM_REC_TECH_CONSTRUCTOR_DDR3 + #endif + + MEM_REC_TECH_CONSTRUCTOR* MemRecTechInstalled[] = { + MEM_REC_TECH_CONSTRUCTOR_DDR3 + MEM_REC_TECH_CONSTRUCTOR_DDR2 + NULL + }; + + #if OPTION_MEMCTLR_DR + #define PSC_REC_DR_UDIMM_DDR2 + #define PSC_REC_DR_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb, + #define PSC_REC_DR_RDIMM_DDR2 + #define PSC_REC_DR_RDIMM_DDR3 MemRecNGetPsCfgRDIMM3Nb, + #define PSC_REC_DR_SODIMM_DDR2 + #define PSC_REC_DR_SODIMM_DDR3 MemRecNGetPsCfgSODIMM3Nb, + #endif + #if ((OPTION_MEMCTLR_DA == TRUE) || (OPTION_MEMCTLR_Ni == TRUE) || (OPTION_MEMCTLR_PH == TRUE) || (OPTION_MEMCTLR_RB == TRUE)) + #define PSC_REC_DA_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb, + #define PSC_REC_DA_SODIMM_DDR2 + #define PSC_REC_DA_SODIMM_DDR3 MemRecNGetPsCfgSODIMM3Nb, + #endif + #if OPTION_MEMCTLR_HY + #define PSC_REC_HY_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb, + #define PSC_REC_HY_RDIMM_DDR3 MemRecNGetPsCfgRDIMM3Nb, + #endif + #if OPTION_MEMCTLR_C32 + #define PSC_REC_C32_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb, + #define PSC_REC_C32_RDIMM_DDR3 MemRecNGetPsCfgRDIMM3Nb, + #endif + #if OPTION_MEMCTLR_OR + #define PSC_REC_OR_UDIMM_DDR3 //MemRecNGetPsCfgUDIMM3OR, + #define PSC_REC_OR_RDIMM_DDR3 //MemRecNGetPsCfgRDIMM3OR, + #endif + #if OPTION_MEMCTLR_TN + #define PSC_REC_OR_UDIMM_DDR3 //MemRecNGetPsCfgUDIMM3OR, + #define PSC_REC_OR_RDIMM_DDR3 //MemRecNGetPsCfgRDIMM3OR, + #endif + + #ifndef PSC_REC_DR_UDIMM_DDR2 + #define PSC_REC_DR_UDIMM_DDR2 + #endif + #ifndef PSC_REC_DR_UDIMM_DDR3 + #define PSC_REC_DR_UDIMM_DDR3 + #endif + #ifndef PSC_REC_DR_RDIMM_DDR2 + #define PSC_REC_DR_RDIMM_DDR2 + #endif + #ifndef PSC_REC_DR_RDIMM_DDR3 + #define PSC_REC_DR_RDIMM_DDR3 + #endif + #ifndef PSC_REC_DR_SODIMM_DDR2 + #define PSC_REC_DR_SODIMM_DDR2 + #endif + #ifndef PSC_REC_DR_SODIMM_DDR3 + #define PSC_REC_DR_SODIMM_DDR3 + #endif + #ifndef PSC_REC_DA_UDIMM_DDR3 + #define PSC_REC_DA_UDIMM_DDR3 + #endif + #ifndef PSC_REC_DA_SODIMM_DDR2 + #define PSC_REC_DA_SODIMM_DDR2 + #endif + #ifndef PSC_REC_DA_SODIMM_DDR3 + #define PSC_REC_DA_SODIMM_DDR3 + #endif + #ifndef PSC_REC_HY_UDIMM_DDR3 + #define PSC_REC_HY_UDIMM_DDR3 + #endif + #ifndef PSC_REC_HY_RDIMM_DDR3 + #define PSC_REC_HY_RDIMM_DDR3 + #endif + #ifndef PSC_REC_C32_UDIMM_DDR3 + #define PSC_REC_C32_UDIMM_DDR3 + #endif + #ifndef PSC_REC_C32_RDIMM_DDR3 + #define PSC_REC_C32_RDIMM_DDR3 + #endif + #ifndef PSC_REC_OR_UDIMM_DDR3 + #define PSC_REC_OR_UDIMM_DDR3 + #endif + #ifndef PSC_REC_OR_RDIMM_DDR3 + #define PSC_REC_OR_RDIMM_DDR3 + #endif + + MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[] = { + PSC_REC_DR_UDIMM_DDR2 + PSC_REC_DR_RDIMM_DDR2 + PSC_REC_DR_SODIMM_DDR2 + PSC_REC_DR_UDIMM_DDR3 + PSC_REC_DR_RDIMM_DDR3 + PSC_REC_DR_SODIMM_DDR3 + PSC_REC_DA_SODIMM_DDR2 + PSC_REC_DA_UDIMM_DDR3 + PSC_REC_DA_SODIMM_DDR3 + PSC_REC_HY_UDIMM_DDR3 + PSC_REC_HY_RDIMM_DDR3 + PSC_REC_C32_UDIMM_DDR3 + PSC_REC_C32_RDIMM_DDR3 + PSC_REC_OR_UDIMM_DDR3 + PSC_REC_OR_RDIMM_DDR3 + NULL + }; + + /*--------------------------------------------------------------------------------------------------- + * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION + * + * + *--------------------------------------------------------------------------------------------------- + */ + #define MEM_PSC_REC_FLOW_BLOCK_END NULL + #define PSC_REC_TBL_END NULL + #define MEM_REC_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) MemRecDefTrue + + #if OPTION_MEMCTLR_TN + #if OPTION_UDIMMS + extern PSC_TBL_ENTRY RecTNDramTermTblEntU; + #define PSC_REC_TBL_TN_UDIMM3_DRAM_TERM &RecTNDramTermTblEntU, + extern PSC_TBL_ENTRY RecTNSAOTblEntU3; + #define PSC_REC_TBL_TN_UDIMM3_SAO &RecTNSAOTblEntU3, + #endif + #if OPTION_SODIMMS + extern PSC_TBL_ENTRY RecTNSAOTblEntSO3; + #define PSC_REC_TBL_TN_SODIMM3_SAO &RecTNSAOTblEntSO3, + extern PSC_TBL_ENTRY RecTNDramTermTblEntSO; + #define PSC_REC_TBL_TN_SODIMM3_DRAM_TERM &RecTNDramTermTblEntSO, + #endif + extern PSC_TBL_ENTRY RecTNMR0WrTblEntry; + extern PSC_TBL_ENTRY RecTNMR0CLTblEntry; + extern PSC_TBL_ENTRY RecTNDdr3CKETriEnt; + extern PSC_TBL_ENTRY RecTNOdtPatTblEnt; + + #ifndef PSC_REC_TBL_TN_UDIMM3_DRAM_TERM + #define PSC_REC_TBL_TN_UDIMM3_DRAM_TERM + #endif + #ifndef PSC_REC_TBL_TN_SODIMM3_DRAM_TERM + #define PSC_REC_TBL_TN_SODIMM3_DRAM_TERM + #endif + #ifndef PSC_REC_TBL_TN_SODIMM3_SAO + #define PSC_REC_TBL_TN_SODIMM3_SAO + #endif + #ifndef PSC_REC_TBL_TN_UDIMM3_SAO + #define PSC_REC_TBL_TN_UDIMM3_SAO + #endif + + PSC_TBL_ENTRY* memRecPSCTblDramTermArrayTN[] = { + PSC_REC_TBL_TN_UDIMM3_DRAM_TERM + PSC_REC_TBL_TN_SODIMM3_DRAM_TERM + PSC_REC_TBL_END + }; + + PSC_TBL_ENTRY* memRecPSCTblODTPatArrayTN[] = { + &RecTNOdtPatTblEnt, + PSC_REC_TBL_END + }; + + PSC_TBL_ENTRY* memRecPSCTblSAOArrayTN[] = { + PSC_REC_TBL_TN_SODIMM3_SAO + PSC_REC_TBL_TN_UDIMM3_SAO + PSC_REC_TBL_END + }; + + PSC_TBL_ENTRY* memRecPSCTblMR0WRArrayTN[] = { + &RecTNMR0WrTblEntry, + PSC_REC_TBL_END + }; + + PSC_TBL_ENTRY* memRecPSCTblMR0CLArrayTN[] = { + &RecTNMR0CLTblEntry, + PSC_REC_TBL_END + }; + + MEM_PSC_TABLE_BLOCK memRecPSCTblBlockTN = { + NULL, + (PSC_TBL_ENTRY **)&memRecPSCTblDramTermArrayTN, + (PSC_TBL_ENTRY **)&memRecPSCTblODTPatArrayTN, + (PSC_TBL_ENTRY **)&memRecPSCTblSAOArrayTN, + (PSC_TBL_ENTRY **)&memRecPSCTblMR0WRArrayTN, + (PSC_TBL_ENTRY **)&memRecPSCTblMR0CLArrayTN, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL + }; + extern MEM_PSC_FLOW MemPRecGetRttNomWr; + #define PSC_REC_FLOW_TN_DRAM_TERM MemPRecGetRttNomWr + extern MEM_PSC_FLOW MemPRecGetODTPattern; + #define PSC_REC_FLOW_TN_ODT_PATTERN MemPRecGetODTPattern + extern MEM_PSC_FLOW MemPRecGetSAO; + #define PSC_REC_FLOW_TN_SAO MemPRecGetSAO + extern MEM_PSC_FLOW MemPRecGetMR0WrCL; + #define PSC_REC_FLOW_TN_MR0_WRCL MemPRecGetMR0WrCL + + MEM_PSC_FLOW_BLOCK memRecPlatSpecFlowTN = { + &memRecPSCTblBlockTN, + MEM_REC_PSC_FLOW_DEFTRUE, + PSC_REC_FLOW_TN_DRAM_TERM, + PSC_REC_FLOW_TN_ODT_PATTERN, + PSC_REC_FLOW_TN_SAO, + PSC_REC_FLOW_TN_MR0_WRCL, + MEM_REC_PSC_FLOW_DEFTRUE, + MEM_REC_PSC_FLOW_DEFTRUE, + MEM_REC_PSC_FLOW_DEFTRUE, + MEM_REC_PSC_FLOW_DEFTRUE, + MEM_REC_PSC_FLOW_DEFTRUE, + MEM_REC_PSC_FLOW_DEFTRUE + }; + #define MEM_PSC_REC_FLOW_BLOCK_TN &memRecPlatSpecFlowTN, + #else + #define MEM_PSC_REC_FLOW_BLOCK_TN + #endif + + MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[] = { + MEM_PSC_REC_FLOW_BLOCK_TN + MEM_PSC_REC_FLOW_BLOCK_END + }; + +#else + /*--------------------------------------------------------------------------------------------------- + * DEFAULT TECHNOLOGY BLOCK + * + * + *--------------------------------------------------------------------------------------------------- + */ + MEM_TECH_CONSTRUCTOR* MemRecTechInstalled[] = { // Types of technology installed + NULL + }; + /*--------------------------------------------------------------------------------------------------- + * DEFAULT NORTHBRIDGE SUPPORT LIST + * + * + *--------------------------------------------------------------------------------------------------- + */ + MEM_REC_NB_CONSTRUCTOR* MemRecNBInstalled[] = { + NULL + }; + /*---------------------------------------------------------------------- + * DEFAULT PSCFG DEFINITIONS + * + *---------------------------------------------------------------------- + */ + MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[] = { + NULL + }; + /*---------------------------------------------------------------------- + * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION + * + *---------------------------------------------------------------------- + */ + MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[] = { + NULL + }; +#endif +#endif // _OPTION_MEMORY_RECOVERY_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionMmioMapInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionMmioMapInstall.h new file mode 100644 index 0000000..c6fff06 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionMmioMapInstall.h @@ -0,0 +1,109 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: MMIO map manager + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_MMIO_MAP_INSTALL_H_ +#define _OPTION_MMIO_MAP_INSTALL_H_ + +#include "mmioMapManager.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ + +#define F15_MMIO_MAP_SUPPORT + +#if ((AGESA_ENTRY_INIT_ENV == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) + // Family 15h + #ifdef OPTION_FAMILY15H + #if OPTION_FAMILY15H == TRUE + extern CONST MMIO_MAP_FAMILY_SERVICES ROMDATA F15MmioMapSupport; + #undef F15_MMIO_MAP_SUPPORT + #define F15_MMIO_MAP_SUPPORT {(AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , &F15MmioMapSupport}, + #endif + #endif + +#endif + + + +CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA MmioMapFamilyServiceArray[] = +{ + F15_MMIO_MAP_SUPPORT + {0, NULL} +}; + +CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA MmioMapFamilyServiceTable = +{ + (sizeof (MmioMapFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &MmioMapFamilyServiceArray[0] +}; + +#endif // _OPTION_MMIO_MAP_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionMsgBasedC1eInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionMsgBasedC1eInstall.h new file mode 100644 index 0000000..5673726 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionMsgBasedC1eInstall.h @@ -0,0 +1,143 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: Message-Based C1e + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_MSG_BASED_C1E_INSTALL_H_ +#define _OPTION_MSG_BASED_C1E_INSTALL_H_ + +#include "cpuMsgBasedC1e.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#define OPTION_MSG_BASED_C1E_FEAT +#define F10_MSG_BASED_C1E_SUPPORT +#define F15_OR_MSG_BASED_C1E_SUPPORT +#if OPTION_MSG_BASED_C1E == TRUE + #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) + + #ifdef OPTION_FAMILY10H + #if OPTION_FAMILY10H == TRUE + #if OPTION_FAMILY10H_HY == TRUE + #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE) + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e; + #undef OPTION_MSG_BASED_C1E_FEAT + #define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e, + #endif + #endif + #endif + #endif + + #ifdef OPTION_FAMILY15H_OR + #if OPTION_FAMILY15H_OR == TRUE + #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE) + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e; + #undef OPTION_MSG_BASED_C1E_FEAT + #define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e, + #endif + #endif + #endif + + #ifdef OPTION_FAMILY10H + #if OPTION_FAMILY10H == TRUE + #if OPTION_FAMILY10H_HY == TRUE + #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE) + extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F10MsgBasedC1e; + #undef F10_MSG_BASED_C1E_SUPPORT + #define F10_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_10_HY, &F10MsgBasedC1e}, + #endif + #endif + #endif + #endif + + #ifdef OPTION_FAMILY15H_OR + #if OPTION_FAMILY15H_OR == TRUE + #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE) + extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F15OrMsgBasedC1e; + #undef F15_OR_MSG_BASED_C1E_SUPPORT + #define F15_OR_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_15_OR, &F15OrMsgBasedC1e}, + #endif + #endif + #endif + + CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA MsgBasedC1eFamilyServiceArray[] = + { + F10_MSG_BASED_C1E_SUPPORT + F15_OR_MSG_BASED_C1E_SUPPORT + {0, NULL} + }; + CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA MsgBasedC1eFamilyServiceTable = + { + (sizeof (MsgBasedC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &MsgBasedC1eFamilyServiceArray[0] + }; + #endif +#endif +#endif // _OPTION_MSG_BASED_C1E_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionMultiSocket.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionMultiSocket.h new file mode 100644 index 0000000..40f1a21 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionMultiSocket.h @@ -0,0 +1,242 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Multi-socket option API. + * + * Contains structures and values used to control the multi-socket option code. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: OPTION + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _OPTION_MULTISOCKET_H_ +#define _OPTION_MULTISOCKET_H_ + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *---------------------------------------------------------------------------------------- + */ + +/** + * This function loops through all possible socket locations, gathering the number + * of power management steps each populated socket requires, and returns the + * highest number. + * + * @param[out] NumSystemSteps Maximum number of system steps required + * @param[in] StdHeader Config handle for library and services + * + */ +typedef VOID OPTION_MULTISOCKET_PM_STEPS ( + OUT UINT8 *NumSystemSteps, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * This function loops through all possible socket locations, starting core 0 of + * each populated socket to perform the passed in AP_TASK. After starting all + * other core 0s, the BSC will perform the AP_TASK as well. This must be run by + * the system BSC only. + * + * @param[in] TaskPtr Function descriptor + * @param[in] StdHeader Config handle for library and services + * @param[in] ConfigParams AMD entry point's CPU parameter structure + * + * @return The most severe error code from AP_TASK + * + */ +typedef AGESA_STATUS OPTION_MULTISOCKET_PM_CORE0_TASK ( + IN VOID *TaskPtr, + IN AMD_CONFIG_PARAMS *StdHeader, + IN VOID *ConfigParams + ); + +/** + * This function loops through all possible socket locations, comparing the + * maximum NB frequencies to determine the slowest. This function also + * determines if all coherent NB frequencies are equivalent. + * + * @param[in] NbPstate NB P-state number to check (0 = fastest) + * @param[in] PlatformConfig Platform profile/build option config structure. + * @param[out] SystemNbCofNumerator NB frequency numerator for the system in MHz + * @param[out] SystemNbCofDenominator NB frequency denominator for the system + * @param[out] SystemNbCofsMatch Whether or not all NB frequencies are equivalent + * @param[out] NbPstateIsEnabledOnAllCPUs Whether or not NbPstate is valid on all CPUs + * @param[in] StdHeader Config handle for library and services + * + * @retval TRUE At least one processor has NbPstate enabled. + * @retval FALSE NbPstate is disabled on all CPUs + */ +typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF ( + IN UINT32 NbPstate, + IN PLATFORM_CONFIGURATION *PlatformConfig, + OUT UINT32 *SystemNbCofNumerator, + OUT UINT32 *SystemNbCofDenominator, + OUT BOOLEAN *SystemNbCofsMatch, + OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * This function loops through all possible socket locations, checking whether + * any populated sockets require NB COF VID programming. + * + * @param[in] StdHeader Config handle for library and services + * + */ +typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF_UPDATE ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * This function loops through all possible socket locations, collecting any + * power management initialization errors that may have occurred. These errors + * are transferred from the core 0s of the socket in which the errors occurred + * to the BSC's heap. The BSC's heap is then searched for the most severe error + * that occurred, and returns it. This function must be called by the BSC only. + * + * @param[in] StdHeader Config handle for library and services + * + */ +typedef AGESA_STATUS OPTION_MULTISOCKET_PM_GET_EVENTS ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * This function loops through all possible socket locations and Nb Pstates, + * comparing the NB frequencies to determine the slowest NB P0 and NB Pmin in + * the system. + * + * @param[in] PlatformConfig Platform profile/build option config structure. + * @param[out] MinSysNbFreq NB frequency numerator for the system in MHz + * @param[out] MinP0NbFreq NB frequency numerator for P0 in MHz + * @param[in] StdHeader Config handle for library and services + */ +typedef VOID OPTION_MULTISOCKET_PM_NB_MIN_COF ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + OUT UINT32 *MinSysNbFreq, + OUT UINT32 *MinP0NbFreq, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * This function returns the current running core's PCI Config Space address. + * + * @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0) + * @param[in] StdHeader Header for library and services. + */ +typedef BOOLEAN OPTION_MULTISOCKET_GET_PCI_ADDRESS ( + OUT PCI_ADDR *PciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * This function writes to all nodes on the executing core's socket. + * + * @param[in] PciAddress The Function and Register to update + * @param[in] Mask The bitwise AND mask to apply to the current register value + * @param[in] Data The bitwise OR mask to apply to the current register value + * @param[in] StdHeader Header for library and services. + * + */ +typedef VOID OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI ( + IN PCI_ADDR *PciAddress, + IN UINT32 Mask, + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#define MULTISOCKET_STRUCT_VERSION 0x01 + +/** + * Provide build configuration of cpu multi-socket or single socket support. + * + */ +typedef struct { + UINT16 OptMultiSocketVersion; ///< Table version + OPTION_MULTISOCKET_PM_STEPS *GetNumberOfSystemPmSteps; ///< Method: Get number of power mgt tasks + OPTION_MULTISOCKET_PM_CORE0_TASK *BscRunCodeOnAllSystemCore0s; ///< Method: Perform tasks on Core 0 of each processor + OPTION_MULTISOCKET_PM_NB_COF *GetSystemNbPstateSettings; ///< Method: Find the Northbridge frequency for the specified Nb Pstate in the system. + OPTION_MULTISOCKET_PM_NB_COF_UPDATE *GetSystemNbCofVidUpdate; ///< Method: Determine if any Northbridges in the system need to update their COF/VID. + OPTION_MULTISOCKET_PM_GET_EVENTS *BscRetrievePmEarlyInitErrors; ///< Method: Gathers error information from all Core 0s. + OPTION_MULTISOCKET_PM_NB_MIN_COF *GetMinNbCof; ///< Method: Get the minimum system and minimum P0 Northbridge frequency. + OPTION_MULTISOCKET_GET_PCI_ADDRESS *GetCurrPciAddr; ///< Method: Get PCI Config Space Address for the current running core. + OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI *ModifyCurrSocketPci; ///< Method: Writes to all nodes on the executing core's socket. +} OPTION_MULTISOCKET_CONFIGURATION; + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ + + +#endif // _OPTION_MULTISOCKET_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionMultiSocketInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionMultiSocketInstall.h new file mode 100644 index 0000000..e78abb0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionMultiSocketInstall.h @@ -0,0 +1,131 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: Multiple Socket Support + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_MULTISOCKET_INSTALL_H_ +#define _OPTION_MULTISOCKET_INSTALL_H_ + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#ifndef OPTION_MULTISOCKET + #error BLDOPT: Option not defined: "OPTION_MULTISOCKET" +#endif + +#if OPTION_MULTISOCKET == TRUE + OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrMulti; + #define GET_NUM_PM_STEPS GetNumberOfSystemPmStepsPtrMulti + OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sMulti; + #define CORE0_PM_TASK RunCodeOnAllSystemCore0sMulti + OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofMulti; + #define GET_SYS_NB_COF GetSystemNbCofMulti + OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti; + #define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti + OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsMulti; + #define GET_EARLY_PM_ERRORS GetEarlyPmErrorsMulti + OPTION_MULTISOCKET_PM_NB_MIN_COF GetMinNbCofMulti; + #define GET_MIN_NB_COF GetMinNbCofMulti + OPTION_MULTISOCKET_GET_PCI_ADDRESS GetCurrPciAddrMulti; + #define GET_PCI_ADDRESS GetCurrPciAddrMulti + OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciMulti; + #define MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciMulti +#else + OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrSingle; + #define GET_NUM_PM_STEPS GetNumberOfSystemPmStepsPtrSingle + OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sSingle; + #define CORE0_PM_TASK RunCodeOnAllSystemCore0sSingle + OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofSingle; + #define GET_SYS_NB_COF GetSystemNbCofSingle + OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle; + #define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle + OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsSingle; + #define GET_EARLY_PM_ERRORS GetEarlyPmErrorsSingle + OPTION_MULTISOCKET_PM_NB_MIN_COF GetMinNbCofSingle; + #define GET_MIN_NB_COF GetMinNbCofSingle + OPTION_MULTISOCKET_GET_PCI_ADDRESS GetCurrPciAddrSingle; + #define GET_PCI_ADDRESS GetCurrPciAddrSingle + OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciSingle; + #define MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciSingle +#endif + +/* Declare the instance of the multisocket option configuration structure */ +OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration = { + MULTISOCKET_STRUCT_VERSION, + GET_NUM_PM_STEPS, + CORE0_PM_TASK, + GET_SYS_NB_COF, + GET_SYS_NB_COF_UPDATE, + GET_EARLY_PM_ERRORS, + GET_MIN_NB_COF, + GET_PCI_ADDRESS, + MODIFY_CURR_SOCKET_PCI +}; + +#endif // _OPTION_MULTISOCKET_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionPreserveMailboxInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionPreserveMailboxInstall.h new file mode 100644 index 0000000..a9d16d5 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionPreserveMailboxInstall.h @@ -0,0 +1,149 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: Preserve Mailbox + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_PRESERVE_MAILBOX_INSTALL_H_ +#define _OPTION_PRESERVE_MAILBOX_INSTALL_H_ + +#include "PreserveMailbox.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#define OPTION_PRESERVE_MAILBOX_FEAT +#define F10_PRESERVE_MAILBOX_SUPPORT +#define F15_PRESERVE_MAILBOX_SUPPORT + +#if ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE)) + #if ((OPTION_FAMILY10H == TRUE) || ((OPTION_FAMILY15H == TRUE) && ((OPTION_FAMILY15H_OR == TRUE)))) + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePreserveAroundMailbox; + #undef OPTION_PRESERVE_MAILBOX_FEAT + #define OPTION_PRESERVE_MAILBOX_FEAT &CpuFeaturePreserveAroundMailbox, + #endif + #if OPTION_FAMILY10H == TRUE + CONST PRESERVE_MAILBOX_FAMILY_REGISTER ROMDATA F10PreserveMailboxRegisters [] = { + { + MAKE_SBDFO (0, 0, 0, 3, 0x168), + 0x00000FFF + }, + { + MAKE_SBDFO (0, 0, 0, 3, 0x170), + 0x00000FFF + }, + { + ILLEGAL_SBDFO, + 0 + } + }; + CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F10PreserveMailboxServices = { + 0, + TRUE, + (PRESERVE_MAILBOX_FAMILY_REGISTER *)&F10PreserveMailboxRegisters + }; + #undef F10_PRESERVE_MAILBOX_SUPPORT + #define F10_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_10, &F10PreserveMailboxServices}, + #endif + #if (OPTION_FAMILY15H == TRUE) && (OPTION_FAMILY15H_OR == TRUE) + CONST PRESERVE_MAILBOX_FAMILY_REGISTER ROMDATA F15PreserveMailboxRegisters [] = { + { + MAKE_SBDFO (0, 0, 0, 3, 0x168), + 0x00000FFF + }, + { + MAKE_SBDFO (0, 0, 0, 3, 0x170), + 0x00000FFF + }, + { + ILLEGAL_SBDFO, + 0 + } + }; + CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F15PreserveMailboxServices = { + 0, + TRUE, + (PRESERVE_MAILBOX_FAMILY_REGISTER *)&F15PreserveMailboxRegisters + }; + #undef F15_PRESERVE_MAILBOX_SUPPORT + #define F15_PRESERVE_MAILBOX_SUPPORT {(AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , &F15PreserveMailboxServices}, + #endif + CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PreserveMailboxFamilyServiceArray[] = + { + F10_PRESERVE_MAILBOX_SUPPORT + F15_PRESERVE_MAILBOX_SUPPORT + {0, NULL} + }; + CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PreserveMailboxFamilyServiceTable = + { + (sizeof (PreserveMailboxFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &PreserveMailboxFamilyServiceArray[0] + }; +#endif + +#endif // _OPTION_PRESERVE_MAILBOX_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionPsiInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionPsiInstall.h new file mode 100644 index 0000000..31cd671 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionPsiInstall.h @@ -0,0 +1,113 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: Power Status Indicator (PSI). + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_PSI_INSTALL_H_ +#define _OPTION_PSI_INSTALL_H_ + +#include "cpuPsi.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#define OPTION_CPU_PSI_FEAT +#define F15_TN_PSI_SUPPORT + +#if OPTION_CPU_PSI == TRUE + #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) + // Family 15h + #ifdef OPTION_FAMILY15H + #if OPTION_FAMILY15H == TRUE + #if OPTION_FAMILY15H_TN == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePsi; + #undef OPTION_CPU_PSI_FEAT + #define OPTION_CPU_PSI_FEAT &CpuFeaturePsi, + extern CONST PSI_FAMILY_SERVICES ROMDATA F15TnPsiSupport; + #undef F15_TN_PSI_SUPPORT + #define F15_TN_PSI_SUPPORT {AMD_FAMILY_15_TN, &F15TnPsiSupport}, + #endif + #endif + #endif + #endif +#endif + +CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PsiFamilyServiceArray[] = +{ + F15_TN_PSI_SUPPORT + {0, NULL} +}; + +CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PsiFamilyServiceTable = +{ + (sizeof (PsiFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &PsiFamilyServiceArray[0] +}; + +#endif // _OPTION_PSI_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionPstate.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionPstate.h new file mode 100644 index 0000000..ddc1f31 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionPstate.h @@ -0,0 +1,142 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD ACPI PState option API. + * + * Contains structures and values used to control the PStates option code. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: OPTION + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _OPTION_PSTATE_H_ +#define _OPTION_PSTATE_H_ + +#include "cpuPstateTables.h" + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *---------------------------------------------------------------------------------------- + */ + +typedef AGESA_STATUS OPTION_SSDT_FEATURE ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT VOID **AcpiPstatePtr + ); + +typedef UINT32 OPTION_ACPI_FEATURE ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PSTATE_LEVELING *PStateLevelingBuffer, + IN OUT VOID **AcpiPStatePtr, + IN UINT8 LocalApicId, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef AGESA_STATUS OPTION_PSTATE_GATHER ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr + ); + +typedef AGESA_STATUS OPTION_PSTATE_LEVELING ( + IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#define PSTATE_STRUCT_VERSION 0x01 + +/// Indirection vectors for POST/PEI PState code +typedef struct { + UINT16 OptPstateVersion; ///< revision of this structure + OPTION_PSTATE_GATHER *PstateGather; ///< vector for data gathering routine + OPTION_PSTATE_LEVELING *PstateLeveling; ///< vector for leveling routine +} OPTION_PSTATE_POST_CONFIGURATION; + +/// Indirection vectors for LATE/DXE PState code +typedef struct { + UINT16 OptPstateVersion; ///< revision of this structure + OPTION_SSDT_FEATURE *SsdtFeature; ///< vector for routine to generate SSDT + OPTION_ACPI_FEATURE *PstateFeature; ///< vector for routine to generate ACPI PState Objects + OPTION_ACPI_FEATURE *CstateFeature; ///< vector for routine to generate ACPI CState Objects + BOOLEAN CfgPstatePpc; ///< boolean for creating _PPC method + BOOLEAN CfgPstatePct; ///< boolean for creating _PCT method + BOOLEAN CfgPstatePsd; ///< boolean for creating _PSD method + BOOLEAN CfgPstatePss; ///< boolean for creating _PSS method + BOOLEAN CfgPstateXpss; ///< boolean for creating _XPSS method +} OPTION_PSTATE_LATE_CONFIGURATION; + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ + +#endif // _OPTION_PSTATE_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateHpcModeInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateHpcModeInstall.h new file mode 100644 index 0000000..b42531f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateHpcModeInstall.h @@ -0,0 +1,112 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: Pstate HPC mode. + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_PSTATE_HPC_MODE_INSTALL_H_ +#define _OPTION_PSTATE_HPC_MODE_INSTALL_H_ + +#include "cpuPstateHpcMode.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#define OPTION_CPU_PSTATE_HPC_MODE_FEAT +#define F15_PSTATE_HPC_MODE_SUPPORT + +#if (AGESA_ENTRY_INIT_POST == TRUE) + // Family 15h + #ifdef OPTION_FAMILY15H + #if OPTION_FAMILY15H == TRUE + // Orochi + #if (OPTION_FAMILY15H_OR == TRUE) + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePstateHpcMode; + #undef OPTION_CPU_PSTATE_HPC_MODE_FEAT + #define OPTION_CPU_PSTATE_HPC_MODE_FEAT &CpuFeaturePstateHpcMode, + extern CONST PSTATE_HPC_MODE_FAMILY_SERVICES ROMDATA F15PstateHpcSupport; + #undef F15_PSTATE_HPC_MODE_SUPPORT + #define F15_PSTATE_HPC_MODE_SUPPORT {AMD_FAMILY_15_OR, &F15PstateHpcSupport}, + #endif + #endif + #endif +#endif + +CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PstateHpcModeFamilyServiceArray[] = +{ + F15_PSTATE_HPC_MODE_SUPPORT + {0, NULL} +}; + +CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PstateHpcModeFamilyServiceTable = +{ + (sizeof (PstateHpcModeFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &PstateHpcModeFamilyServiceArray[0] +}; + +#endif // _OPTION_PSTATE_HPC_MODE_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateInstall.h new file mode 100644 index 0000000..1e44bc2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionPstateInstall.h @@ -0,0 +1,281 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: PState + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_PSTATE_INSTALL_H_ +#define _OPTION_PSTATE_INSTALL_H_ + +#include "cpuPstateTables.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ + +#define F10_PSTATE_SERVICE_SUPPORT +#define F12_PSTATE_SERVICE_SUPPORT +#define F14_PSTATE_SERVICE_SUPPORT +#define F15_OR_PSTATE_SERVICE_SUPPORT +#define F15_TN_PSTATE_SERVICE_SUPPORT + + +#if ((AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE)) + // + //Define Pstate CPU Family service + // + #ifdef OPTION_FAMILY10H + #if OPTION_FAMILY10H == TRUE + extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F10PstateServices; + #undef F10_PSTATE_SERVICE_SUPPORT + #define F10_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_10, &F10PstateServices}, + #endif + #endif + + #ifdef OPTION_FAMILY12H + #if OPTION_FAMILY12H == TRUE + extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F12PstateServices; + #undef F12_PSTATE_SERVICE_SUPPORT + #define F12_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_12, &F12PstateServices}, + #endif + #endif + + #ifdef OPTION_FAMILY14H + #if OPTION_FAMILY14H == TRUE + extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F14PstateServices; + #undef F14_PSTATE_SERVICE_SUPPORT + #define F14_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_14, &F14PstateServices}, + #endif + #endif + + #ifdef OPTION_FAMILY15H + #if OPTION_FAMILY15H == TRUE + #ifdef OPTION_FAMILY15H_OR + #if OPTION_FAMILY15H_OR == TRUE + extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15OrPstateServices; + #undef F15_OR_PSTATE_SERVICE_SUPPORT + #define F15_OR_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15_OR, &F15OrPstateServices}, + #endif + #endif + #ifdef OPTION_FAMILY15H_TN + #if OPTION_FAMILY15H_TN == TRUE + extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15TnPstateServices; + #undef F15_TN_PSTATE_SERVICE_SUPPORT + #define F15_TN_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15_TN, &F15TnPstateServices}, + #endif + #endif + #endif + #endif + // + //Define ACPI Pstate objects. + // + #ifndef OPTION_ACPI_PSTATES + #error BLDOPT: Option not defined: "OPTION_ACPI_PSTATES" + #endif + #if (OPTION_ACPI_PSTATES == TRUE) + OPTION_SSDT_FEATURE GenerateSsdt; + #define USER_SSDT_MAIN GenerateSsdt + #ifndef OPTION_MULTISOCKET + #error BLDOPT: Option not defined: "OPTION_MULTISOCKET" + #endif + + OPTION_ACPI_FEATURE CreatePStateAcpiTables; + OPTION_PSTATE_GATHER PStateGatherMain; + #if ((OPTION_MULTISOCKET == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE)) + OPTION_PSTATE_LEVELING PStateLevelingMain; + #define USER_PSTATE_OPTION_LEVEL PStateLevelingMain + #else + OPTION_PSTATE_LEVELING PStateLevelingStub; + #define USER_PSTATE_OPTION_LEVEL PStateLevelingStub + #endif + #if AGESA_ENTRY_INIT_LATE == TRUE + #define USER_PSTATE_OPTION_MAIN CreatePStateAcpiTables + #else + OPTION_ACPI_FEATURE CreateAcpiTablesStub; + #define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub + #endif + #if AGESA_ENTRY_INIT_POST == TRUE + #define USER_PSTATE_OPTION_GATHER PStateGatherMain + #else + OPTION_PSTATE_GATHER PStateGatherStub; + #define USER_PSTATE_OPTION_GATHER PStateGatherStub + #endif + #if CFG_ACPI_PSTATES_PPC == TRUE + #define USER_PSTATE_CFG_PPC TRUE + #else + #define USER_PSTATE_CFG_PPC FALSE + #endif + #if CFG_ACPI_PSTATES_PCT == TRUE + #define USER_PSTATE_CFG_PCT TRUE + #else + #define USER_PSTATE_CFG_PCT FALSE + #endif + #if CFG_ACPI_PSTATES_PSD == TRUE + #define USER_PSTATE_CFG_PSD TRUE + #else + #define USER_PSTATE_CFG_PSD FALSE + #endif + #if CFG_ACPI_PSTATES_PSS == TRUE + #define USER_PSTATE_CFG_PSS TRUE + #else + #define USER_PSTATE_CFG_PSS FALSE + #endif + #if CFG_ACPI_PSTATES_XPSS == TRUE + #define USER_PSTATE_CFG_XPSS TRUE + #else + #define USER_PSTATE_CFG_XPSS FALSE + #endif + + #if OPTION_IO_CSTATE == TRUE + OPTION_ACPI_FEATURE CreateCStateAcpiTables; + #define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables + #else + OPTION_ACPI_FEATURE CreateAcpiTablesStub; + #define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub + #endif + #else + OPTION_SSDT_FEATURE GenerateSsdtStub; + OPTION_ACPI_FEATURE CreateAcpiTablesStub; + OPTION_PSTATE_GATHER PStateGatherStub; + OPTION_PSTATE_LEVELING PStateLevelingStub; + #define USER_SSDT_MAIN GenerateSsdtStub + #define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub + #define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub + #define USER_PSTATE_OPTION_GATHER PStateGatherStub + #define USER_PSTATE_OPTION_LEVEL PStateLevelingStub + #define USER_PSTATE_CFG_PPC FALSE + #define USER_PSTATE_CFG_PCT FALSE + #define USER_PSTATE_CFG_PSD FALSE + #define USER_PSTATE_CFG_PSS FALSE + #define USER_PSTATE_CFG_XPSS FALSE + + // If ACPI Objects are disabled for PStates, we still need to check + // whether ACPI Objects are enabled for CStates + #if OPTION_IO_CSTATE == TRUE + OPTION_SSDT_FEATURE GenerateSsdt; + OPTION_PSTATE_GATHER PStateGatherMain; + OPTION_ACPI_FEATURE CreateCStateAcpiTables; + #undef USER_SSDT_MAIN + #define USER_SSDT_MAIN GenerateSsdt + #undef USER_PSTATE_OPTION_GATHER + #define USER_PSTATE_OPTION_GATHER PStateGatherMain + #undef USER_CSTATE_OPTION_MAIN + #define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables + #endif + #endif +#else + OPTION_SSDT_FEATURE GenerateSsdtStub; + OPTION_ACPI_FEATURE CreateAcpiTablesStub; + OPTION_PSTATE_GATHER PStateGatherStub; + OPTION_PSTATE_LEVELING PStateLevelingStub; + #define USER_SSDT_MAIN GenerateSsdtStub + #define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub + #define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub + #define USER_PSTATE_OPTION_GATHER PStateGatherStub + #define USER_PSTATE_OPTION_LEVEL PStateLevelingStub + #define USER_PSTATE_CFG_PPC FALSE + #define USER_PSTATE_CFG_PCT FALSE + #define USER_PSTATE_CFG_PSD FALSE + #define USER_PSTATE_CFG_PSS FALSE + #define USER_PSTATE_CFG_XPSS FALSE +#endif + +/* Declare the instance of the PSTATE option configuration structure */ +OPTION_PSTATE_POST_CONFIGURATION OptionPstatePostConfiguration = { + PSTATE_STRUCT_VERSION, + USER_PSTATE_OPTION_GATHER, + USER_PSTATE_OPTION_LEVEL +}; + +OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration = { + PSTATE_STRUCT_VERSION, + USER_SSDT_MAIN, + USER_PSTATE_OPTION_MAIN, + USER_CSTATE_OPTION_MAIN, + USER_PSTATE_CFG_PPC, + USER_PSTATE_CFG_PCT, + USER_PSTATE_CFG_PSD, + USER_PSTATE_CFG_PSS, + USER_PSTATE_CFG_XPSS +}; + +CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PstateCpuFamilyServiceArray[] = +{ + F10_PSTATE_SERVICE_SUPPORT + F12_PSTATE_SERVICE_SUPPORT + F14_PSTATE_SERVICE_SUPPORT + F15_OR_PSTATE_SERVICE_SUPPORT + F15_TN_PSTATE_SERVICE_SUPPORT + {0, NULL} +}; +CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PstateFamilyServiceTable = +{ + (sizeof (PstateCpuFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &PstateCpuFamilyServiceArray[0] +}; +#endif // _OPTION_PSTATE_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionS3ScriptInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionS3ScriptInstall.h new file mode 100644 index 0000000..40d95e1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionS3ScriptInstall.h @@ -0,0 +1,118 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: S3SCRIPT + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_S3SCRIPT_INSTALL_H_ +#define _OPTION_S3SCRIPT_INSTALL_H_ + +#include "S3SaveState.h" +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#ifndef OPTION_S3SCRIPT + #define OPTION_S3SCRIPT FALSE //if not define assume PI not use script +#endif + +#if (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) + #if OPTION_S3SCRIPT == TRUE + #define P_S3_SCRIPT_INIT S3ScriptInitState + #endif +#endif + +#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE + #if OPTION_S3SCRIPT == TRUE + #define P_S3_SCRIPT_RESTORE S3ScriptRestoreState + #endif +#endif + +#ifndef P_S3_SCRIPT_INIT + #define P_S3_SCRIPT_INIT S3ScriptInitStateStub +#endif + +#ifndef P_S3_SCRIPT_RESTORE + #define P_S3_SCRIPT_RESTORE S3ScriptInitStateStub + #undef GNB_S3_DISPATCH_FUNCTION_TABLE +#endif + +#ifndef GNB_S3_DISPATCH_FUNCTION_TABLE + #define GNB_S3_DISPATCH_FUNCTION_TABLE +#endif + +/* Declare the instance of the S3SCRIPT option configuration structure */ +S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration = { + P_S3_SCRIPT_INIT, + P_S3_SCRIPT_RESTORE +}; + +S3_DISPATCH_FUNCTION_ENTRY S3DispatchFunctionTable [] = { + GNB_S3_DISPATCH_FUNCTION_TABLE + {0, NULL} +}; +#endif // _OPTION_S3SCRIPT_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionSlit.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionSlit.h new file mode 100644 index 0000000..0e42ad0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionSlit.h @@ -0,0 +1,123 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD SLIT option API. + * + * Contains structures and values used to control the SLIT option code. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: OPTION + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _OPTION_SLIT_H_ +#define _OPTION_SLIT_H_ + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *---------------------------------------------------------------------------------------- + */ + +/** + * Create the ACPI System Locality Distance Information Table. + * + */ +typedef AGESA_STATUS OPTION_SLIT_FEATURE ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT VOID **SlitPtr + ); + +/** + * Clean up DRAM used during SLIT creation. + * + */ +typedef AGESA_STATUS OPTION_SLIT_RELEASE_BUFFER ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +#define SLIT_STRUCT_VERSION 0x01 + +/// The Option Configuration of SLIT +typedef struct { + UINT16 OptSlitVersion; ///< The version number of SLIT + OPTION_SLIT_FEATURE *SlitFeature; ///< The Option Feature of SLIT + OPTION_SLIT_RELEASE_BUFFER *SlitReleaseBuffer; ///< Release buffer +} OPTION_SLIT_CONFIGURATION; + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ + + +#endif // _OPTION_SLIT_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionSlitInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionSlitInstall.h new file mode 100644 index 0000000..08ca7b7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionSlitInstall.h @@ -0,0 +1,106 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: SLIT + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_SLIT_INSTALL_H_ +#define _OPTION_SLIT_INSTALL_H_ + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#if AGESA_ENTRY_INIT_LATE == TRUE + #ifndef OPTION_SLIT + #error BLDOPT: Option not defined: "OPTION_SLIT" + #endif + #if OPTION_SLIT == TRUE + OPTION_SLIT_FEATURE GetAcpiSlitMain; + OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBuffer; + #define USER_SLIT_OPTION GetAcpiSlitMain + #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBuffer + #else + OPTION_SLIT_FEATURE GetAcpiSlitStub; + OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub; + #define USER_SLIT_OPTION GetAcpiSlitStub + #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub + #endif +#else + OPTION_SLIT_FEATURE GetAcpiSlitStub; + OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub; + #define USER_SLIT_OPTION GetAcpiSlitStub + #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub +#endif +/* Declare the instance of the SLIT option configuration structure */ +OPTION_SLIT_CONFIGURATION OptionSlitConfiguration = { + SLIT_STRUCT_VERSION, + USER_SLIT_OPTION, + USER_SLIT_RELEASE_BUFFER +}; + +#endif // _OPTION_SLIT_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionSrat.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionSrat.h new file mode 100644 index 0000000..92984a7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionSrat.h @@ -0,0 +1,109 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD SRAT option API. + * + * Contains structures and values used to control the SRAT option code. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: OPTION + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _OPTION_SRAT_H_ +#define _OPTION_SRAT_H_ + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *---------------------------------------------------------------------------------------- + */ + +typedef AGESA_STATUS OPTION_SRAT_FEATURE ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT VOID **SratPtr + ); + +#define SRAT_STRUCT_VERSION 0x01 + +/// The Option Configuration of SRAT +typedef struct { + UINT16 OptSratVersion; ///< The version number of SRAT + OPTION_SRAT_FEATURE *SratFeature; ///< The Option Feature of SRAT +} OPTION_SRAT_CONFIGURATION; + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ + + +#endif // _OPTION_SRAT_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionSratInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionSratInstall.h new file mode 100644 index 0000000..75bd741 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionSratInstall.h @@ -0,0 +1,100 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: SRAT + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_SRAT_INSTALL_H_ +#define _OPTION_SRAT_INSTALL_H_ + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#if AGESA_ENTRY_INIT_LATE == TRUE + #ifndef OPTION_SRAT + #error BLDOPT: Option not defined: "OPTION_SRAT" + #endif + #if OPTION_SRAT == TRUE + OPTION_SRAT_FEATURE GetAcpiSratMain; + #define USER_SRAT_OPTION GetAcpiSratMain + #else + OPTION_SRAT_FEATURE GetAcpiSratStub; + #define USER_SRAT_OPTION GetAcpiSratStub + #endif +#else + OPTION_SRAT_FEATURE GetAcpiSratStub; + #define USER_SRAT_OPTION GetAcpiSratStub +#endif + +/* Declare the instance of the WHEA option configuration structure */ +OPTION_SRAT_CONFIGURATION OptionSratConfiguration = { + SRAT_STRUCT_VERSION, + USER_SRAT_OPTION +}; + +#endif // _OPTION_WHEA_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionSwC1eInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionSwC1eInstall.h new file mode 100644 index 0000000..1d740d6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionSwC1eInstall.h @@ -0,0 +1,107 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: SW C1e + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_SW_C1E_INSTALL_H_ +#define _OPTION_SW_C1E_INSTALL_H_ + +#include "cpuSwC1e.h" + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#define OPTION_SW_C1E_FEAT +#define F10_SW_C1E_SUPPORT +#if AGESA_ENTRY_INIT_EARLY == TRUE + #ifdef OPTION_FAMILY10H + #if OPTION_FAMILY10H == TRUE + #if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE) + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureSwC1e; + #undef OPTION_SW_C1E_FEAT + #define OPTION_SW_C1E_FEAT &CpuFeatureSwC1e, + extern CONST SW_C1E_FAMILY_SERVICES ROMDATA F10SwC1e; + #undef F10_SW_C1E_SUPPORT + #define F10_SW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10SwC1e}, + #endif + #endif + #endif + CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA SwC1eFamilyServiceArray[] = + { + F10_SW_C1E_SUPPORT + {0, NULL} + }; + CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA SwC1eFamilyServiceTable = + { + (sizeof (SwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), + &SwC1eFamilyServiceArray[0] + }; +#endif + +#endif // _OPTION_SW_C1E_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionWhea.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionWhea.h new file mode 100644 index 0000000..2a7855d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionWhea.h @@ -0,0 +1,110 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD WHEA option API. + * + * Contains structures and values used to control the WHEA option code. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: OPTION + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _OPTION_WHEA_H_ +#define _OPTION_WHEA_H_ + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *---------------------------------------------------------------------------------------- + */ + +typedef AGESA_STATUS OPTION_WHEA_FEATURE ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT VOID **WheaMcePtr, + IN OUT VOID **WheaCmcPtr + ); + +#define WHEA_STRUCT_VERSION 0x01 + +/// The Option Configuration of WHEA +typedef struct { + UINT16 OptWheaVersion; ///< The version number of WHEA + OPTION_WHEA_FEATURE *WheaFeature; ///< The Option Feature of WHEA +} OPTION_WHEA_CONFIGURATION; + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ + + +#endif // _OPTION_WHEA_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionWheaInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionWheaInstall.h new file mode 100644 index 0000000..fdaabb7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionWheaInstall.h @@ -0,0 +1,101 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build option: WHEA + * + * Contains AMD AGESA install macros and test conditions. Output is the + * defaults tables reflecting the User's build options selection. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Options + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _OPTION_WHEA_INSTALL_H_ +#define _OPTION_WHEA_INSTALL_H_ + +/* This option is designed to be included into the platform solution install + * file. The platform solution install file will define the options status. + * Check to validate the definition + */ +#if AGESA_ENTRY_INIT_LATE == TRUE + #ifndef OPTION_WHEA + #error BLDOPT: Option not defined: "OPTION_WHEA" + #endif + #if OPTION_WHEA == TRUE + OPTION_WHEA_FEATURE GetAcpiWheaMain; + #define USER_WHEA_OPTION GetAcpiWheaMain + #else + OPTION_WHEA_FEATURE GetAcpiWheaStub; + #define USER_WHEA_OPTION GetAcpiWheaStub + #endif + +#else + OPTION_WHEA_FEATURE GetAcpiWheaStub; + #define USER_WHEA_OPTION GetAcpiWheaStub +#endif + +/* Declare the instance of the WHEA option configuration structure */ +OPTION_WHEA_CONFIGURATION OptionWheaConfiguration = { + WHEA_STRUCT_VERSION, + USER_WHEA_OPTION +}; + +#endif // _OPTION_WHEA_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/Options.h b/src/vendorcode/amd/agesa/f15tn/Include/Options.h new file mode 100644 index 0000000..64ba0bb --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/Options.h @@ -0,0 +1,124 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AGESA options structures + * + * Contains options control structures for the AGESA build options + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + + +#ifndef _OPTIONS_H_ +#define _OPTIONS_H_ + +/** + * Provide topology limits for loops and runtime, based on supported families. + */ +typedef struct { + UINT32 PlatformNumberOfSockets; ///< The limit to the number of processors based on + ///< supported families and other build options. + UINT32 PlatformNumberOfModules; ///< The limit to the number of modules in a processor, based + ///< on supported families. +} OPTIONS_CONFIG_TOPOLOGY; + +/** + * Dispatch Table. + * + * The push high dispatcher uses this table to find what entries are currently in the build image. + */ +typedef struct { + UINT32 FunctionId; ///< The function id specified. + IMAGE_ENTRY EntryPoint; ///< The corresponding entry point to call. +} DISPATCH_TABLE; + +#ifdef BLDCFG_PLATFORM_POWER_POLICY_MODE + #define CFG_PLATFORM_POWER_POLICY_MODE (BLDCFG_PLATFORM_POWER_POLICY_MODE) +#else + #define CFG_PLATFORM_POWER_POLICY_MODE (Performance) +#endif + +#ifdef BLDCFG_PCI_MMIO_BASE + #define CFG_PCI_MMIO_BASE (BLDCFG_PCI_MMIO_BASE) +#else + #define CFG_PCI_MMIO_BASE (0) +#endif + +#ifdef BLDCFG_PCI_MMIO_SIZE + #define CFG_PCI_MMIO_SIZE (BLDCFG_PCI_MMIO_SIZE) +#else + #define CFG_PCI_MMIO_SIZE (0) +#endif + +#ifdef BLDCFG_AP_MTRR_SETTINGS_LIST + #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST) +#else + #define CFG_AP_MTRR_SETTINGS_LIST (NULL) +#endif + +#ifdef BLDCFG_IOMMU_EXCLUSION_RANGE_LIST + #define CFG_IOMMU_EXCLUSION_RANGE_LIST (BLDCFG_IOMMU_EXCLUSION_RANGE_LIST) +#else + #define CFG_IOMMU_EXCLUSION_RANGE_LIST (NULL) +#endif + +#endif // _OPTIONS_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionsHt.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionsHt.h new file mode 100644 index 0000000..a4021fc --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionsHt.h @@ -0,0 +1,136 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD HyperTransport option API. + * + * Contains option pre-compile logic. This file is used by the options + * installer and internally by the HT code initializers. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: OPTION + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _OPTION_HT_H_ +#define _OPTION_HT_H_ + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *---------------------------------------------------------------------------------------- + */ + +/** + * Provide HT build option results + */ +typedef struct { + CONST BOOLEAN IsUsingRecoveryHt; ///< Manual BUID Swap List processing should assume that HT Recovery was used. + CONST BOOLEAN IsSetHtCrcFlood; ///< Enable setting of HT CRC Flood. + ///< Build-time only customizable - @BldCfgItem{BLDCFG_SET_HTCRC_SYNC_FLOOD} + CONST BOOLEAN IsUsingUnitIdClumping; ///< Enable automatically HT Spec compliant Unit Id Clumping. + ///< Build-time only customizable - @BldCfgItem{BLDCFG_USE_UNIT_ID_CLUMPING} + CONST AMD_HT_INTERFACE *HtOptionPlatformDefaults; ///< A set of build time options for HT constructor. + CONST VOID *HtOptionInternalInterface; ///< Use this internal interface initializer. + CONST VOID *HtOptionInternalFeatures; ///< Use this internal feature set initializer. + CONST VOID *HtOptionFamilyNorthbridgeList; ///< Use this list of northbridge initializers. + CONST UINT8 *CONST *HtOptionBuiltinTopologies; ///< Use this list of built-in topologies. +} OPTION_HT_CONFIGURATION; + +typedef AGESA_STATUS +F_OPTION_HT_INIT_RESET ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface + ); + +typedef F_OPTION_HT_INIT_RESET *PF_OPTION_HT_INIT_RESET; + +typedef AGESA_STATUS +F_OPTION_HT_RESET_CONSTRUCTOR ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface + ); + +typedef F_OPTION_HT_RESET_CONSTRUCTOR *PF_OPTION_HT_RESET_CONSTRUCTOR; + +/** + * Provide HT reset initialization build option results + */ +typedef struct { + PF_OPTION_HT_INIT_RESET HtInitReset; ///< Method: HT reset initialization. + PF_OPTION_HT_RESET_CONSTRUCTOR HtResetConstructor; ///< Method: HT reset initialization. +} OPTION_HT_INIT_RESET; + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ + +#endif // _OPTION_HT_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionsPage.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionsPage.h new file mode 100644 index 0000000..b161754 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionsPage.h @@ -0,0 +1,402 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Create outline and references for Build Configuration and Options Component mainpage documentation. + * + * Design guides, maintenance guides, and general documentation, are + * collected using this file onto the documentation mainpage. + * This file contains doxygen comment blocks, only. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Documentation + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/** + * @page optionmain Build Configuration and Options Documentation + * + * Additional documentation for the Build Configuration and Options component consists of + * + * - Introduction and Overview to Build Options + * - @subpage platforminstall "Platform Build Options" + * - @subpage bldcfg "Build Configuration Item Cross Reference" + * - @subpage examplecustomizations "Customization Examples" + * - Maintenance Guides: + * - For debug of the Options system, use compiler options + * @n <tt> /P /EP /C /FAs </tt> @n + * PreProcessor output is produced in an .i file in the directory where the project + * file is located. + * - Design Guides: + * - add here >>> + * + */ + +/** + * @page platforminstall Platform Build Options. + * + * Build options are boolean constants. The purpose of build options is to remove code + * from the build to reduce the overall code size present in the ROM image. Unless + * otherwise specified, the default action is to include all options. If a build option is + * not specifically listed as disabled, then it is included into the build. + * + * The documented build options are imported from a user controlled file for + * processing. The build options for all platform solutions are listed below: + * + * @anchor BLDOPT_REMOVE_UDIMMS_SUPPORT + * @li @e BLDOPT_REMOVE_UDIMMS_SUPPORT @n + * If unbuffered DIMMs are NOT expected to be required in the system, the code that + * handles unbuffered DIMMs can be removed from the build. + * + * @anchor BLDOPT_REMOVE_RDIMMS_SUPPORT + * @li @e BLDOPT_REMOVE_RDIMMS_SUPPORT @n + * If registered DIMMs are NOT expected to be required in the system, the code + * that handles registered DIMMs can be removed from the build. + * + * @anchor BLDOPT_REMOVE_LRDIMMS_SUPPORT + * @li @e BLDOPT_REMOVE_LRDIMMS_SUPPORT @n + * If Load Reduced DIMMs are NOT expected to be required in the system, the code + * that handles Load Reduced DIMMs can be removed from the build. + * + * @note The above three options operate independently from each other; however, at + * least one of the unbuffered , registered or load reduced DIMM options must be present in the build. + * + * @anchor BLDOPT_REMOVE_ECC_SUPPORT + * @li @e BLDOPT_REMOVE_ECC_SUPPORT @n + * Use this option to remove the code for Error Checking & Correction. + * + * @anchor BLDOPT_REMOVE_BANK_INTERLEAVE + * @li @e BLDOPT_REMOVE_BANK_INTERLEAVE @n + * Interleaving is a mechanism to do performance fine tuning. This option + * interleaves memory between banks on a DIMM. + * + * @anchor BLDOPT_REMOVE_DCT_INTERLEAVE + * @li @e BLDOPT_REMOVE_DCT_INTERLEAVE @n + * Interleaving is a mechanism to do performance fine tuning. This option + * interleaves memory from two DRAM controllers. + * + * @anchor BLDOPT_REMOVE_NODE_INTERLEAVE + * @li @e BLDOPT_REMOVE_NODE_INTERLEAVE @n + * Interleaving is a mechanism to do performance fine tuning. This option + * interleaves memory from two HyperTransport nodes. + * + * @anchor BLDOPT_REMOVE_PARALLEL_TRAINING + * @li @e BLDOPT_REMOVE_PARALLEL_TRAINING @n + * For multi-socket systems, training memory in parallel can reduce the time + * needed to boot. + * + * @anchor BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT + * @li @e BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT @n + * Online Spare support is removed by this option. + * + * @anchor BLDOPT_REMOVE_MULTISOCKET_SUPPORT + * @li @e BLDOPT_REMOVE_MULTISOCKET_SUPPORT @n + * Many systems use only a single socket and may benefit in code space to remove + * this code. However, certain processors have multiple HyperTransport nodes + * within a single socket. For these processors, the multi-node support is + * required and this option has no effect. + * + * @anchor BLDOPT_REMOVE_ACPI_PSTATES + * @li @e BLDOPT_REMOVE_ACPI_PSTATES @n + * This option removes the code that generates the ACPI tables used in power + * management. + * + * @anchor BLDCFG_PSTATE_HPC_MODE + * @li @e BLDCFG_PSTATE_HPC_MODE @n + * This option enables PStates high performance computing mode (HPC mode) + * + * + * @anchor BLDOPT_REMOVE_SRAT + * @li @e BLDOPT_REMOVE_SRAT @n + * This option removes the code that generates the SRAT tables used in performance + * tuning. + * + * @anchor BLDOPT_REMOVE_SLIT + * @li @e BLDOPT_REMOVE_SLIT @n + * This option removes the code that generates the SLIT tables used in performance + * tuning. + * + * @anchor BLDOPT_REMOVE_WHEA + * @li @e BLDOPT_REMOVE_WHEA @n + * This option removes the code that generates the WHEA tables used in error + * handling and reporting. + * + * @anchor BLDOPT_REMOVE_DMI + * @li @e BLDOPT_REMOVE_DMI @n + * This option removes the code that generates the DMI tables used in system + * management. + * + * @anchor BLDOPT_REMOVE_DQS_TRAINING + * @li @e BLDOPT_REMOVE_DQS_TRAINING @n + * This option removes the code used in memory performance tuning. + * + * + * @anchor BLDOPT_REMOVE_HT_ASSIST + * @li @e BLDOPT_REMOVE_HT_ASSIST @n + * This option removes the code which implements the HT Assist feature. + * + * @anchor BLDOPT_REMOVE_ATM_MODE + * @li @e BLDOPT_REMOVE_ATM_MODE @n + * This option removes the code which implements the ATM feature. + * + * @anchor BLDOPT_REMOVE_MSG_BASED_C1E + * @li @e BLDOPT_REMOVE_MSG_BASED_C1E @n + * This option removes the code which implements the Message Based C1e feature. + * + * @anchor BLDOPT_REMOVE_C6_STATE + * @li @e BLDOPT_REMOVE_C6_STATE @n + * This option removes the code which implements the C6 C-state feature. + * + * @anchor BLDOPT_REMOVE_MEM_RESTORE_SUPPORT + * @li @e BLDOPT_REMOVE_MEM_RESTORE_SUPPORT @n + * This option removes the memory context restore feature. + * + * @anchor BLDOPT_REMOVE_FAMILY_10_SUPPORT + * @li @e BLDOPT_REMOVE_FAMILY_10_SUPPORT @n + * If the package contains support for family 10h processors, remove that support. + * + * @anchor BLDOPT_REMOVE_FAMILY_12_SUPPORT + * @li @e BLDOPT_REMOVE_FAMILY_12_SUPPORT @n + * If the package contains support for family 10h processors, remove that support. + * + * @anchor BLDOPT_REMOVE_FAMILY_14_SUPPORT + * @li @e BLDOPT_REMOVE_FAMILY_14_SUPPORT @n + * If the package contains support for family 14h processors, remove that support. + * + * @anchor BLDOPT_REMOVE_FAMILY_15_SUPPORT + * @li @e BLDOPT_REMOVE_FAMILY_15_SUPPORT @n + * If the package contains support for family 15h processors, remove that support. + * + * @anchor BLDOPT_REMOVE_AM3_SOCKET_SUPPORT + * @li @e BLDOPT_REMOVE_AM3_SOCKET_SUPPORT @n + * This option removes the code which implements support for processors packaged for AM3 sockets. + * + * @anchor BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT + * @li @e BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT @n + * This option removes the code which implements support for processors packaged for ASB2 sockets. + * + * @anchor BLDOPT_REMOVE_C32_SOCKET_SUPPORT + * @li @e BLDOPT_REMOVE_C32_SOCKET_SUPPORT @n + * This option removes the code which implements support for processors packaged for C32 sockets. + * + * @anchor BLDOPT_REMOVE_FM1_SOCKET_SUPPORT + * @li @e BLDOPT_REMOVE_FM1_SOCKET_SUPPORT @n + * This option removes the code which implements support for processors packaged for FM1 sockets. + * + * @anchor BLDOPT_REMOVE_FP1_SOCKET_SUPPORT + * @li @e BLDOPT_REMOVE_FP1_SOCKET_SUPPORT @n + * This option removes the code which implements support for processors packaged for FP1 sockets. + * + * @anchor BLDOPT_REMOVE_FS1_SOCKET_SUPPORT + * @li @e BLDOPT_REMOVE_FS1_SOCKET_SUPPORT @n + * This option removes the code which implements support for processors packaged for FS1 sockets. + * + * @anchor BLDOPT_REMOVE_FT1_SOCKET_SUPPORT + * @li @e BLDOPT_REMOVE_FT1_SOCKET_SUPPORT @n + * This option removes the code which implements support for processors packaged for FT1 sockets. + * + * @anchor BLDOPT_REMOVE_G34_SOCKET_SUPPORT + * @li @e BLDOPT_REMOVE_G34_SOCKET_SUPPORT @n + * This option removes the code which implements support for processors packaged for G34 sockets. + * + * @anchor BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT + * @li @e BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT @n + * This option removes the code which implements support for processors packaged for S1G3 sockets. + * + * @anchor BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT + * @li @e BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT @n + * This option removes the code which implements support for processors packaged for S1G4 sockets. + */ + +/** + * @page examplecustomizations Customization Examples + * + * The Addendum <plat>Options.c file for each platform contains the minimum required + * customizations for that platform. That is, it contains settings which would be needed + * to boot a SimNow! bsd for that platform. + * However, each individual product based on that platform will have customizations necessary for + * that hardware. Since the actual customizations needed vary so much, they are not included in + * the <plat>Options.c. This section provides examples of useful customizations that you can use or + * modify to suit your needs. + * + * @par + * + * Source for the examples shown can be found at Addendum\Examples. @n + * + * - @ref DeemphasisExamples "Deemphasis List Examples" + * - @ref FrequencyLimitExamples "Frequency Limit Examples" + * - @ref PerfPerWattHt "A performance-per-watt optimization Example" + * + * @anchor DeemphasisExamples + * @par Deemphasis List Examples + * + * These examples customize PLATFORM_CONFIGURATION.PlatformDeemphasisList. + * Source for the deemphasis list examples can be found in DeemphasisExamples.c. @n + * @dontinclude DeemphasisExamples.c + * <ul> + * <li> + * The following deemphasis list provides an example for a 2P MCM Max Performance configuration. + * High Speed HT frequencies are supported. There is only one non-coherent chain. Note the technique of + * putting specified link matches before all uses of match any. It often works well to specify the non-coherent links + * and use match any for the coherent links. + * @skip DinarDeemphasisList + * @until { + * The non-coherent chain can run up to 2600 MHz. The chain is located on Socket 0, package Link 2. + * @until { + * @line } + * @line { + * @line } + * The coherent links can run up to 3200 MHz. + * @until HT_FREQUENCY_MAX + * @line } + * end of list: + * @until } + * Make this list the build time customized deemphasis list. + * @line define + * + * </li><li> + * + * The following deemphasis list provides an example for a 4P MCM Max Performance configuration. + * This system has a backplane with connectors for CPU cards and an IO board. So trace lengths are long. + * There can be one to four IO Chains, depending on the IO board. + * @skipline DoubloonDeemphasisList + * @until DoubloonDeemphasisList + * + * </li><li> + * + * The following deemphasis list further illustrates complex coherent system deemphasis. This is the same + * Dinar system as in an earlier example, but this time all the coherent links are explicitly customized (as + * might be needed if each link has unique characterization). For this example, we skip the non-coherent chains. + * (A real system would have to include them, see example above.) + * @skip DinarPerLinkDeemphasisList + * @until { + * Provide deemphasis settings for the 16 bit, ganged, links, Socket 0 links 0, 1 and Socket 1 links 1 and 2. + * Provide entries to customize all HT3 frequencies at which the links may run. This example covers all HT3 speeds. + * @until { + * @until DcvLevelMinus6 + * @until DcvLevelMinus6 + * @until DcvLevelMinus6 + * @until DcvLevelMinus6 + * Link 3 on both sockets connects different internal die: sublink 0 connects the internal node zeroes, and + * sublink 1 connects the internal node ones. So the link is unganged and both sublinks must be specifically + * customized. + * @until { + * @until DcvLevelMinus6 + * @until DcvLevelMinus6 + * @until DcvLevelMinus6 + * @until DcvLevelMinus6 + * end of list: + * @until define + * + * </ul> + * + * @anchor FrequencyLimitExamples + * @par Frequency Limit Examples + * + * These examples customize AMD_HT_INTERFACE.CpuToCpuPcbLimitsList and AMD_HT_INTERFACE.IoPcbLimitsList. + * Source for the frequency limit examples can be found in FrequencyLimitExamples.c. @n + * @dontinclude FrequencyLimitExamples.c + * <ul> + * <li> + * The following list provides an example for limiting all coherent links to non-extended frequencies, + * that is, to 2600 MHz or less. + * @skipline NonExtendedCpuToCpuLimitList + * @until { + * Provide the limit customization. Match links from any socket, any package link, to any socket, any package link. Width is not limited. + * @until HT_FREQUENCY_LIMIT_2600M + * End of list: + * @until ; + * Customize the build to use this cpu to cpu frequency limit. + * @until NonExtendedCpuToCpuLimitList + * @n </li> + * <li> + * The following list provides an example for limiting all coherent links to HT 1 frequencies, + * that is, to 1000 MHz or less. This is sometimes useful for test and debug. + * @skipline Ht1CpuToCpuLimitList + * @until Ht1CpuToCpuLimitList + * @n </li> + * <li> + * The following list provides an example for limiting all non-coherent links to 2400 MHz or less. + * The chain is matched by host processor Socket and package Link. The depth can be used to select a particular device + * to device link on the chain. In this example, the chain consists of a single cave device and depth can be set to match any. + * @skipline No2600MhzIoLimitList + * @until No2600MhzIoLimitList + * @n </li> + * <li> + * The following list provides an example for limiting all non-coherent links to the minimum HT 3 frequency, + * that is, to 1200 MHz or less. This can be useful for test and debug. + * @skipline MinHt3IoLimitList + * @until MinHt3IoLimitList + * @n </li> + * + * </ul> + * + * @anchor PerfPerWattHt + * @par Performance-per-Watt Optimization Example + * + * This example customizes AMD_HT_INTERFACE.SkipRegangList. + * Source for the Performance-per-watt Optimization example can be found in PerfPerWatt.c. @n + * @dontinclude PerfPerWatt.c + * To implement a performance-per-watt optimization for MCM processors, use the skip regang structure shown. @n + * @skipline PerfPerWatt + * @until PerfPerWatt + * + */ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h new file mode 100644 index 0000000..84fc4bd --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h @@ -0,0 +1,3254 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build options for a combination of package type, processor, and features. + * + * This file generates the defaults tables for the all platform solution + * combinations. The documented build options are imported from a user + * controlled file for processing. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e $Revision: 65065 $ @e $Date: 2012-02-07 01:26:53 -0600 (Tue, 07 Feb 2012) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +/***************************************************************************** + * + * Start processing the user options: First, set default settings + * + ****************************************************************************/ + +/* Available options for image builds. + * + * As part of the image build for each image, define the options below to select the + * AGESA entry points included in that image. Turn these on in your option c file, not + * here. + */ +// #define AGESA_ENTRY_INIT_RESET TRUE +// #define AGESA_ENTRY_INIT_RECOVERY TRUE +// #define AGESA_ENTRY_INIT_EARLY TRUE +// #define AGESA_ENTRY_INIT_POST TRUE +// #define AGESA_ENTRY_INIT_ENV TRUE +// #define AGESA_ENTRY_INIT_MID TRUE +// #define AGESA_ENTRY_INIT_LATE TRUE +// #define AGESA_ENTRY_INIT_S3SAVE TRUE +// #define AGESA_ENTRY_INIT_RESUME TRUE +// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE + +/* Defaults for private/internal build control settings */ +/* Available options for image builds. + * + * As part of the image build for each image, define the options below to select the + * AGESA entry points included in that image. + */ + +VOLATILE AMD_MODULE_HEADER mCpuModuleID = { + //ModuleHeaderSignature + // Remove 'DOM$' as temp solution before update BinUtil.exe , + Int32FromChar ('0', '0', '0', '0'), + //ModuleIdentifier[8] + AGESA_ID, + //ModuleVersion[12] + AGESA_VERSION_STRING, + //ModuleDispatcher + NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher), + //NextBlock + NULL +}; + +/* Process user desired AGESA entry points */ +#ifndef AGESA_ENTRY_INIT_RESET + #define AGESA_ENTRY_INIT_RESET FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_RECOVERY + #define AGESA_ENTRY_INIT_RECOVERY FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_EARLY + #define AGESA_ENTRY_INIT_EARLY FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_POST + #define AGESA_ENTRY_INIT_POST FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_ENV + #define AGESA_ENTRY_INIT_ENV FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_MID + #define AGESA_ENTRY_INIT_MID FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_LATE + #define AGESA_ENTRY_INIT_LATE FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_S3SAVE + #define AGESA_ENTRY_INIT_S3SAVE FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_RESUME + #define AGESA_ENTRY_INIT_RESUME FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_LATE_RESTORE + #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES + #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE +#endif + +/* Default the late AP entry point to off. It can be enabled + by any family that may need the late AP functionality, or + by any feature code that may need it. The IBVs no longer + have control over this entry point. */ +#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK + #undef AGESA_ENTRY_LATE_RUN_AP_TASK +#endif +#define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE + + + +/* Process solution defined socket / family installations + * + * As part of the release package for each image, define the options below to select the + * AGESA processor support included in that image. + */ + +/* Default sockets to off */ +#define OPTION_G34_SOCKET_SUPPORT FALSE +#define OPTION_C32_SOCKET_SUPPORT FALSE +#define OPTION_S1G3_SOCKET_SUPPORT FALSE +#define OPTION_S1G4_SOCKET_SUPPORT FALSE +#define OPTION_ASB2_SOCKET_SUPPORT FALSE +#define OPTION_FS1_SOCKET_SUPPORT FALSE +#define OPTION_FM1_SOCKET_SUPPORT FALSE +#define OPTION_FM2_SOCKET_SUPPORT FALSE +#define OPTION_FP1_SOCKET_SUPPORT FALSE +#define OPTION_FP2_SOCKET_SUPPORT FALSE +#define OPTION_FT1_SOCKET_SUPPORT FALSE +#define OPTION_AM3_SOCKET_SUPPORT FALSE + +/* Default families to off */ +#define OPTION_FAMILY10H FALSE +#define OPTION_FAMILY12H FALSE +#define OPTION_FAMILY14H FALSE +#define OPTION_FAMILY15H FALSE +#define OPTION_FAMILY15H_MODEL_0x FALSE +#define OPTION_FAMILY15H_MODEL_1x FALSE + + +/* Enable the appropriate socket support */ +#ifdef INSTALL_G34_SOCKET_SUPPORT + #if INSTALL_G34_SOCKET_SUPPORT == TRUE + #undef OPTION_G34_SOCKET_SUPPORT + #define OPTION_G34_SOCKET_SUPPORT TRUE + #endif +#endif + +#ifdef INSTALL_C32_SOCKET_SUPPORT + #if INSTALL_C32_SOCKET_SUPPORT == TRUE + #undef OPTION_C32_SOCKET_SUPPORT + #define OPTION_C32_SOCKET_SUPPORT TRUE + #endif +#endif + +#ifdef INSTALL_S1G3_SOCKET_SUPPORT + #if INSTALL_S1G3_SOCKET_SUPPORT == TRUE + #undef OPTION_S1G3_SOCKET_SUPPORT + #define OPTION_S1G3_SOCKET_SUPPORT TRUE + #endif +#endif + +#ifdef INSTALL_S1G4_SOCKET_SUPPORT + #if INSTALL_S1G4_SOCKET_SUPPORT == TRUE + #undef OPTION_S1G4_SOCKET_SUPPORT + #define OPTION_S1G4_SOCKET_SUPPORT TRUE + #endif +#endif + +#ifdef INSTALL_ASB2_SOCKET_SUPPORT + #if INSTALL_ASB2_SOCKET_SUPPORT == TRUE + #undef OPTION_ASB2_SOCKET_SUPPORT + #define OPTION_ASB2_SOCKET_SUPPORT TRUE + #endif +#endif + +#ifdef INSTALL_FS1_SOCKET_SUPPORT + #if INSTALL_FS1_SOCKET_SUPPORT == TRUE + #undef OPTION_FS1_SOCKET_SUPPORT + #define OPTION_FS1_SOCKET_SUPPORT TRUE + #endif +#endif + + +#ifdef INSTALL_FM1_SOCKET_SUPPORT + #if INSTALL_FM1_SOCKET_SUPPORT == TRUE + #undef OPTION_FM1_SOCKET_SUPPORT + #define OPTION_FM1_SOCKET_SUPPORT TRUE + #endif +#endif + +#ifdef INSTALL_FM2_SOCKET_SUPPORT + #if INSTALL_FM2_SOCKET_SUPPORT == TRUE + #undef OPTION_FM2_SOCKET_SUPPORT + #define OPTION_FM2_SOCKET_SUPPORT TRUE + #endif +#endif + + +#ifdef INSTALL_FP1_SOCKET_SUPPORT + #if INSTALL_FP1_SOCKET_SUPPORT == TRUE + #undef OPTION_FP1_SOCKET_SUPPORT + #define OPTION_FP1_SOCKET_SUPPORT TRUE + #endif +#endif + +#ifdef INSTALL_FP2_SOCKET_SUPPORT + #if INSTALL_FP2_SOCKET_SUPPORT == TRUE + #undef OPTION_FP2_SOCKET_SUPPORT + #define OPTION_FP2_SOCKET_SUPPORT TRUE + #endif +#endif + +#ifdef INSTALL_FT1_SOCKET_SUPPORT + #if INSTALL_FT1_SOCKET_SUPPORT == TRUE + #undef OPTION_FT1_SOCKET_SUPPORT + #define OPTION_FT1_SOCKET_SUPPORT TRUE + #endif +#endif + + +#ifdef INSTALL_AM3_SOCKET_SUPPORT + #if INSTALL_AM3_SOCKET_SUPPORT == TRUE + #undef OPTION_AM3_SOCKET_SUPPORT + #define OPTION_AM3_SOCKET_SUPPORT TRUE + #endif +#endif + + +/* Enable the appropriate family support */ +// F10 is supported in G34, C32, S1g4, ASB2, S1g3, & AM3 +#ifdef INSTALL_FAMILY_10_SUPPORT + #if INSTALL_FAMILY_10_SUPPORT == TRUE + #undef OPTION_FAMILY10H + #define OPTION_FAMILY10H TRUE + #endif +#endif + +// F12 is supported in FP1, FS1, & FM1 +#ifdef INSTALL_FAMILY_12_SUPPORT + #if INSTALL_FAMILY_12_SUPPORT == TRUE + #undef OPTION_FAMILY12H + #define OPTION_FAMILY12H TRUE + #endif +#endif + +#ifdef INSTALL_FAMILY_14_SUPPORT + #if INSTALL_FAMILY_14_SUPPORT == TRUE + #undef OPTION_FAMILY14H + #define OPTION_FAMILY14H TRUE + #endif +#endif + +// F15_0x is supported in G34, C32, & AM3 +#ifdef INSTALL_FAMILY_15_MODEL_0x_SUPPORT + #if INSTALL_FAMILY_15_MODEL_0x_SUPPORT == TRUE + #undef OPTION_FAMILY15H + #define OPTION_FAMILY15H TRUE + #undef OPTION_FAMILY15H_MODEL_0x + #define OPTION_FAMILY15H_MODEL_0x TRUE + #endif +#endif + +// F15_1x is supported in FS1r2, FM2, & FP2 +#ifdef INSTALL_FAMILY_15_MODEL_1x_SUPPORT + #if INSTALL_FAMILY_15_MODEL_1x_SUPPORT == TRUE + #undef OPTION_FAMILY15H + #define OPTION_FAMILY15H TRUE + #undef OPTION_FAMILY15H_MODEL_1x + #define OPTION_FAMILY15H_MODEL_1x TRUE + #endif +#endif + + +/* Turn off families not required by socket designations */ +#if (OPTION_FAMILY10H == TRUE) + #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_S1G3_SOCKET_SUPPORT == FALSE) && (OPTION_S1G4_SOCKET_SUPPORT == FALSE) && (OPTION_ASB2_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE) + #undef OPTION_FAMILY10H + #define OPTION_FAMILY10H FALSE + #endif +#endif + +#if (OPTION_FAMILY12H == TRUE) + #if (OPTION_FS1_SOCKET_SUPPORT == FALSE) && (OPTION_FM1_SOCKET_SUPPORT == FALSE) && (OPTION_FP1_SOCKET_SUPPORT == FALSE) + #undef OPTION_FAMILY12H + #define OPTION_FAMILY12H FALSE + #endif +#endif + +#if (OPTION_FAMILY14H == TRUE) + #if (OPTION_FT1_SOCKET_SUPPORT == FALSE) + #undef OPTION_FAMILY14H + #define OPTION_FAMILY14H FALSE + #endif +#endif + +#if (OPTION_FAMILY15H_MODEL_0x == TRUE) + #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE) + #undef OPTION_FAMILY15H_MODEL_0x + #define OPTION_FAMILY15H_MODEL_0x FALSE + #endif +#endif + +#if (OPTION_FAMILY15H_MODEL_1x == TRUE) + #if (OPTION_FS1_SOCKET_SUPPORT == FALSE) && (OPTION_FM2_SOCKET_SUPPORT == FALSE) && (OPTION_FP2_SOCKET_SUPPORT == FALSE) + #undef OPTION_FAMILY15H_MODEL_1x + #define OPTION_FAMILY15H_MODEL_1x FALSE + #endif +#endif + + +#if (OPTION_FAMILY15H_MODEL_0x == FALSE) && (OPTION_FAMILY15H_MODEL_1x == FALSE) + #undef OPTION_FAMILY15H + #define OPTION_FAMILY15H FALSE +#endif + + +/* Check for invalid combinations of socket/family */ +#if (OPTION_G34_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H_MODEL_0x == FALSE) + #error No G34 supported families included in the build + #endif +#endif + +#if (OPTION_C32_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H_MODEL_0x == FALSE) + #error No C32 supported families included in the build + #endif +#endif + +#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY10H == FALSE) + #error No S1G3 supported families included in the build + #endif +#endif + +#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY10H == FALSE) + #error No S1G4 supported families included in the build + #endif +#endif + +#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY10H == FALSE) + #error No ASB2 supported families included in the build + #endif +#endif + +#if (OPTION_FS1_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY12H == FALSE) && (OPTION_FAMILY15H_MODEL_1x == FALSE) + #error No FS1 supported families included in the build + #endif +#endif + + +#if (OPTION_FM1_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY12H == FALSE) + #error No FM1 supported families included in the build + #endif +#endif + +#if (OPTION_FM2_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY15H_MODEL_1x == FALSE) + #error No FM2 supported families included in the build + #endif +#endif + + +#if (OPTION_FP1_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY12H == FALSE) + #error No FP1 supported families included in the build + #endif +#endif + +#if (OPTION_FP2_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY15H_MODEL_1x == FALSE) + #error No FP2 supported families included in the build + #endif +#endif + +#if (OPTION_FT1_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY14H == FALSE) + #error No FT1 supported families included in the build + #endif +#endif + + +#if (OPTION_AM3_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H_MODEL_0x == FALSE) + #error No AM3 supported families included in the build + #endif +#endif + + +/* Process AGESA private data + * + * Turn on appropriate CPU models and memory controllers, + * as well as some other memory controls. + */ + +/* Default all models to off */ +#define OPTION_FAMILY10H_BL FALSE +#define OPTION_FAMILY10H_DA FALSE +#define OPTION_FAMILY10H_HY FALSE +#define OPTION_FAMILY10H_PH FALSE +#define OPTION_FAMILY10H_RB FALSE +#define OPTION_FAMILY12H_LN FALSE +#define OPTION_FAMILY14H_ON FALSE +#define OPTION_FAMILY15H_OR FALSE +#define OPTION_FAMILY15H_TN FALSE +#define OPTION_FAMILY15H_UNKNOWN FALSE + +/* Default all memory controllers to off */ +#define OPTION_MEMCTLR_DR FALSE +#define OPTION_MEMCTLR_HY FALSE +#define OPTION_MEMCTLR_OR FALSE +#define OPTION_MEMCTLR_C32 FALSE +#define OPTION_MEMCTLR_DA FALSE +#define OPTION_MEMCTLR_LN FALSE +#define OPTION_MEMCTLR_ON FALSE +#define OPTION_MEMCTLR_Ni FALSE +#define OPTION_MEMCTLR_PH FALSE +#define OPTION_MEMCTLR_RB FALSE +#define OPTION_MEMCTLR_TN FALSE + +/* Default all memory controls to off */ +#define OPTION_HW_WRITE_LEV_TRAINING FALSE +#define OPTION_SW_WRITE_LEV_TRAINING FALSE +#define OPTION_CONTINOUS_PATTERN_GENERATION FALSE +#define OPTION_HW_DQS_REC_EN_TRAINING FALSE +#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING FALSE +#define OPTION_OPT_SW_DQS_REC_EN_TRAINING FALSE +#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING FALSE +#define OPTION_OPT_SW_RD_WR_POS_TRAINING FALSE +#define OPTION_MAX_RD_LAT_TRAINING FALSE +#define OPTION_HW_DRAM_INIT FALSE +#define OPTION_SW_DRAM_INIT FALSE +#define OPTION_S3_MEM_SUPPORT FALSE +#define OPTION_ADDR_TO_CS_TRANSLATOR FALSE +#define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE +#define OPTION_PRE_MEM_INIT FALSE +#define OPTION_POST_MEM_INIT FALSE + +/* Defaults for public user options */ +#define OPTION_UDIMMS FALSE +#define OPTION_RDIMMS FALSE +#define OPTION_SODIMMS FALSE +#define OPTION_LRDIMMS FALSE +#define OPTION_DDR2 FALSE +#define OPTION_DDR3 FALSE +#define OPTION_ECC FALSE +#define OPTION_BANK_INTERLEAVE FALSE +#define OPTION_DCT_INTERLEAVE FALSE +#define OPTION_NODE_INTERLEAVE FALSE +#define OPTION_PARALLEL_TRAINING FALSE +#define OPTION_ONLINE_SPARE FALSE +#define OPTION_MEM_RESTORE FALSE +#define OPTION_DIMM_EXCLUDE FALSE + +/* Default all CPU controls to off */ +#define OPTION_MULTISOCKET FALSE +#define OPTION_SRAT FALSE +#define OPTION_SLIT FALSE +#define OPTION_HT_ASSIST FALSE +#define OPTION_ATM_MODE FALSE +#define OPTION_CPU_CORELEVLING FALSE +#define OPTION_MSG_BASED_C1E FALSE +#define OPTION_CPU_CFOH FALSE +#define OPTION_C6_STATE FALSE +#define OPTION_IO_CSTATE FALSE +#define OPTION_CPB FALSE +#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE +#define OPTION_CPU_PSTATE_HPC_MODE FALSE +#define OPTION_CPU_APM FALSE +#define OPTION_CPU_PSI FALSE +#define OPTION_CPU_HTC FALSE +#define OPTION_S3SCRIPT FALSE +#define OPTION_GFX_RECOVERY FALSE + +/* Default FCH controls to off */ +#define FCH_SUPPORT FALSE + +/* Enable all private controls based on socket/family enables */ +#if (OPTION_G34_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY10H == TRUE) + #undef OPTION_FAMILY10H_HY + #define OPTION_FAMILY10H_HY TRUE + #undef OPTION_MEMCTLR_HY + #define OPTION_MEMCTLR_HY TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING + #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_MULTISOCKET + #define OPTION_MULTISOCKET TRUE + #undef OPTION_SRAT + #define OPTION_SRAT TRUE + #undef OPTION_SLIT + #define OPTION_SLIT TRUE + #undef OPTION_HT_ASSIST + #define OPTION_HT_ASSIST TRUE + #undef OPTION_CPU_CORELEVLING + #define OPTION_CPU_CORELEVLING TRUE + #undef OPTION_MSG_BASED_C1E + #define OPTION_MSG_BASED_C1E TRUE + #undef OPTION_CPU_CFOH + #define OPTION_CPU_CFOH TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_RDIMMS + #define OPTION_RDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_ECC + #define OPTION_ECC TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE TRUE + #undef OPTION_NODE_INTERLEAVE + #define OPTION_NODE_INTERLEAVE TRUE + #undef OPTION_PARALLEL_TRAINING + #define OPTION_PARALLEL_TRAINING TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_ONLINE_SPARE + #define OPTION_ONLINE_SPARE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif + #if (OPTION_FAMILY15H_MODEL_0x == TRUE) + #undef OPTION_FAMILY15H_OR + #define OPTION_FAMILY15H_OR TRUE + #undef OPTION_FAMILY15H_UNKNOWN + #define OPTION_FAMILY15H_UNKNOWN TRUE + #undef OPTION_MEMCTLR_OR + #define OPTION_MEMCTLR_OR TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_CONTINOUS_PATTERN_GENERATION + #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE + #undef OPTION_HW_DQS_REC_EN_TRAINING + #define OPTION_HW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING + #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE + #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING + #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_MULTISOCKET + #define OPTION_MULTISOCKET TRUE + #undef OPTION_C6_STATE + #define OPTION_C6_STATE TRUE + #undef OPTION_IO_CSTATE + #define OPTION_IO_CSTATE TRUE + #undef OPTION_CPB + #define OPTION_CPB TRUE + #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT + #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE + #undef OPTION_CPU_APM + #define OPTION_CPU_APM TRUE + #undef OPTION_SRAT + #define OPTION_SRAT TRUE + #undef OPTION_SLIT + #define OPTION_SLIT TRUE + #undef OPTION_HT_ASSIST + #define OPTION_HT_ASSIST TRUE + #undef OPTION_ATM_MODE + #define OPTION_ATM_MODE TRUE + #undef OPTION_CPU_CORELEVLING + #define OPTION_CPU_CORELEVLING TRUE + #undef OPTION_MSG_BASED_C1E + #define OPTION_MSG_BASED_C1E TRUE + #undef OPTION_CPU_CFOH + #define OPTION_CPU_CFOH TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_RDIMMS + #define OPTION_RDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_LRDIMMS + #define OPTION_LRDIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_ECC + #define OPTION_ECC TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE TRUE + #undef OPTION_NODE_INTERLEAVE + #define OPTION_NODE_INTERLEAVE TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_ONLINE_SPARE + #define OPTION_ONLINE_SPARE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif +#endif + +#if (OPTION_C32_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY10H == TRUE) + #undef OPTION_FAMILY10H_HY + #define OPTION_FAMILY10H_HY TRUE + #undef OPTION_MEMCTLR_C32 + #define OPTION_MEMCTLR_C32 TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING + #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_ADDR_TO_CS_TRANSLATOR + #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE + #undef OPTION_MULTISOCKET + #define OPTION_MULTISOCKET TRUE + #undef OPTION_SRAT + #define OPTION_SRAT TRUE + #undef OPTION_SLIT + #define OPTION_SLIT TRUE + #undef OPTION_HT_ASSIST + #define OPTION_HT_ASSIST TRUE + #undef OPTION_CPU_CORELEVLING + #define OPTION_CPU_CORELEVLING TRUE + #undef OPTION_MSG_BASED_C1E + #define OPTION_MSG_BASED_C1E TRUE + #undef OPTION_CPU_CFOH + #define OPTION_CPU_CFOH TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_RDIMMS + #define OPTION_RDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_ECC + #define OPTION_ECC TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE TRUE + #undef OPTION_NODE_INTERLEAVE + #define OPTION_NODE_INTERLEAVE TRUE + #undef OPTION_PARALLEL_TRAINING + #define OPTION_PARALLEL_TRAINING TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_ONLINE_SPARE + #define OPTION_ONLINE_SPARE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif + #if (OPTION_FAMILY15H_MODEL_0x == TRUE) + #undef OPTION_FAMILY15H_OR + #define OPTION_FAMILY15H_OR TRUE + #undef OPTION_FAMILY15H_UNKNOWN + #define OPTION_FAMILY15H_UNKNOWN TRUE + #undef OPTION_MEMCTLR_OR + #define OPTION_MEMCTLR_OR TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_CONTINOUS_PATTERN_GENERATION + #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE + #undef OPTION_HW_DQS_REC_EN_TRAINING + #define OPTION_HW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING + #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE + #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING + #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_ADDR_TO_CS_TRANSLATOR + #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE + #undef OPTION_MULTISOCKET + #define OPTION_MULTISOCKET TRUE + #undef OPTION_C6_STATE + #define OPTION_C6_STATE TRUE + #undef OPTION_IO_CSTATE + #define OPTION_IO_CSTATE TRUE + #undef OPTION_CPB + #define OPTION_CPB TRUE + #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT + #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE + #undef OPTION_CPU_APM + #define OPTION_CPU_APM TRUE + #undef OPTION_SRAT + #define OPTION_SRAT TRUE + #undef OPTION_SLIT + #define OPTION_SLIT TRUE + #undef OPTION_HT_ASSIST + #define OPTION_HT_ASSIST TRUE + #undef OPTION_ATM_MODE + #define OPTION_ATM_MODE TRUE + #undef OPTION_CPU_CORELEVLING + #define OPTION_CPU_CORELEVLING TRUE + #undef OPTION_MSG_BASED_C1E + #define OPTION_MSG_BASED_C1E TRUE + #undef OPTION_CPU_CFOH + #define OPTION_CPU_CFOH TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_RDIMMS + #define OPTION_RDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_LRDIMMS + #define OPTION_LRDIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_ECC + #define OPTION_ECC TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE TRUE + #undef OPTION_NODE_INTERLEAVE + #define OPTION_NODE_INTERLEAVE TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_ONLINE_SPARE + #define OPTION_ONLINE_SPARE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif +#endif + +#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY10H == TRUE) + #undef OPTION_FAMILY10H_BL + #define OPTION_FAMILY10H_BL TRUE + #undef OPTION_FAMILY10H_DA + #define OPTION_FAMILY10H_DA TRUE + #undef OPTION_MEMCTLR_DA + #define OPTION_MEMCTLR_DA TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING + #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_CPU_CORELEVLING + #define OPTION_CPU_CORELEVLING TRUE + #undef OPTION_CPU_CFOH + #define OPTION_CPU_CFOH TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_ECC + #define OPTION_ECC TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE TRUE + #undef OPTION_NODE_INTERLEAVE + #define OPTION_NODE_INTERLEAVE TRUE + #undef OPTION_PARALLEL_TRAINING + #define OPTION_PARALLEL_TRAINING TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_ONLINE_SPARE + #define OPTION_ONLINE_SPARE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif +#endif + +#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY10H == TRUE) + #undef OPTION_FAMILY10H_BL + #define OPTION_FAMILY10H_BL TRUE + #undef OPTION_FAMILY10H_DA + #define OPTION_FAMILY10H_DA TRUE + #undef OPTION_MEMCTLR_DA + #define OPTION_MEMCTLR_DA TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING + #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_CPU_CORELEVLING + #define OPTION_CPU_CORELEVLING TRUE + #undef OPTION_CPU_CFOH + #define OPTION_CPU_CFOH TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_ECC + #define OPTION_ECC TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE TRUE + #undef OPTION_NODE_INTERLEAVE + #define OPTION_NODE_INTERLEAVE TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif +#endif + +#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY10H == TRUE) + #undef OPTION_FAMILY10H_BL + #define OPTION_FAMILY10H_BL TRUE + #undef OPTION_FAMILY10H_DA + #define OPTION_FAMILY10H_DA TRUE + #undef OPTION_MEMCTLR_Ni + #define OPTION_MEMCTLR_Ni TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING + #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_CPU_CORELEVLING + #define OPTION_CPU_CORELEVLING TRUE + #undef OPTION_CPU_CFOH + #define OPTION_CPU_CFOH TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_ECC + #define OPTION_ECC TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE TRUE + #undef OPTION_NODE_INTERLEAVE + #define OPTION_NODE_INTERLEAVE TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif +#endif + +#if (OPTION_FS1_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY12H == TRUE) + #undef OPTION_FAMILY12H_LN + #define OPTION_FAMILY12H_LN TRUE + #undef OPTION_MEMCTLR_LN + #define OPTION_MEMCTLR_LN TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_CONTINOUS_PATTERN_GENERATION + #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE + #undef OPTION_HW_DQS_REC_EN_TRAINING + #define OPTION_HW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING + #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_GFX_RECOVERY + #define OPTION_GFX_RECOVERY TRUE + #undef OPTION_C6_STATE + #define OPTION_C6_STATE TRUE + #undef OPTION_IO_CSTATE + #define OPTION_IO_CSTATE TRUE + #undef OPTION_CPB + #define OPTION_CPB TRUE + #undef OPTION_S3SCRIPT + #define OPTION_S3SCRIPT TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif + #if (OPTION_FAMILY15H_MODEL_1x == TRUE) + #undef FCH_SUPPORT + #define FCH_SUPPORT TRUE + #undef OPTION_FAMILY15H_TN + #define OPTION_FAMILY15H_TN TRUE + #undef OPTION_MEMCTLR_TN + #define OPTION_MEMCTLR_TN TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_CONTINOUS_PATTERN_GENERATION + #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE + #undef OPTION_HW_DQS_REC_EN_TRAINING + #define OPTION_HW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING + #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_GFX_RECOVERY + #define OPTION_GFX_RECOVERY TRUE + #undef OPTION_CPU_CORELEVLING + #define OPTION_CPU_CORELEVLING TRUE + #undef OPTION_C6_STATE + #define OPTION_C6_STATE TRUE + #undef OPTION_IO_CSTATE + #define OPTION_IO_CSTATE TRUE + #undef OPTION_CPB + #define OPTION_CPB TRUE + #undef OPTION_CPU_PSI + #define OPTION_CPU_PSI TRUE + #undef OPTION_CPU_HTC + #define OPTION_CPU_HTC TRUE + #undef OPTION_S3SCRIPT + #define OPTION_S3SCRIPT TRUE + #undef OPTION_CPU_CFOH + #define OPTION_CPU_CFOH TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif +#endif + +#if (OPTION_FM1_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY12H == TRUE) + #undef OPTION_FAMILY12H_LN + #define OPTION_FAMILY12H_LN TRUE + #undef OPTION_MEMCTLR_LN + #define OPTION_MEMCTLR_LN TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_CONTINOUS_PATTERN_GENERATION + #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE + #undef OPTION_HW_DQS_REC_EN_TRAINING + #define OPTION_HW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING + #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_GFX_RECOVERY + #define OPTION_GFX_RECOVERY TRUE + #undef OPTION_C6_STATE + #define OPTION_C6_STATE TRUE + #undef OPTION_IO_CSTATE + #define OPTION_IO_CSTATE TRUE + #undef OPTION_CPB + #define OPTION_CPB TRUE + #undef OPTION_S3SCRIPT + #define OPTION_S3SCRIPT TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif +#endif + +#if (OPTION_FM2_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY15H_MODEL_1x == TRUE) + #undef FCH_SUPPORT + #define FCH_SUPPORT TRUE + #undef OPTION_FAMILY15H_TN + #define OPTION_FAMILY15H_TN TRUE + #undef OPTION_MEMCTLR_TN + #define OPTION_MEMCTLR_TN TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_CONTINOUS_PATTERN_GENERATION + #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE + #undef OPTION_HW_DQS_REC_EN_TRAINING + #define OPTION_HW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING + #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_GFX_RECOVERY + #define OPTION_GFX_RECOVERY TRUE + #undef OPTION_CPU_HTC + #define OPTION_CPU_HTC TRUE + #undef OPTION_CPU_CORELEVLING + #define OPTION_CPU_CORELEVLING TRUE + #undef OPTION_C6_STATE + #define OPTION_C6_STATE TRUE + #undef OPTION_IO_CSTATE + #define OPTION_IO_CSTATE TRUE + #undef OPTION_CPB + #define OPTION_CPB TRUE + #undef OPTION_CPU_PSI + #define OPTION_CPU_PSI TRUE + #undef OPTION_S3SCRIPT + #define OPTION_S3SCRIPT TRUE + #undef OPTION_CPU_CFOH + #define OPTION_CPU_CFOH TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif +#endif + +#if (OPTION_FP1_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY12H == TRUE) + #undef OPTION_FAMILY12H_LN + #define OPTION_FAMILY12H_LN TRUE + #undef OPTION_MEMCTLR_LN + #define OPTION_MEMCTLR_LN TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_CONTINOUS_PATTERN_GENERATION + #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE + #undef OPTION_HW_DQS_REC_EN_TRAINING + #define OPTION_HW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING + #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_ADDR_TO_CS_TRANSLATOR + #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE + #undef OPTION_GFX_RECOVERY + #define OPTION_GFX_RECOVERY TRUE + #undef OPTION_C6_STATE + #define OPTION_C6_STATE TRUE + #undef OPTION_IO_CSTATE + #define OPTION_IO_CSTATE TRUE + #undef OPTION_CPB + #define OPTION_CPB TRUE + #undef OPTION_S3SCRIPT + #define OPTION_S3SCRIPT TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_ONLINE_SPARE + #define OPTION_ONLINE_SPARE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif +#endif + +#if (OPTION_FP2_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY15H_MODEL_1x == TRUE) + #undef FCH_SUPPORT + #define FCH_SUPPORT TRUE + #undef OPTION_FAMILY15H_TN + #define OPTION_FAMILY15H_TN TRUE + #undef OPTION_MEMCTLR_TN + #define OPTION_MEMCTLR_TN TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_CONTINOUS_PATTERN_GENERATION + #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE + #undef OPTION_HW_DQS_REC_EN_TRAINING + #define OPTION_HW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING + #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_ADDR_TO_CS_TRANSLATOR + #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE + #undef OPTION_GFX_RECOVERY + #define OPTION_GFX_RECOVERY TRUE + #undef OPTION_CPU_HTC + #define OPTION_CPU_HTC TRUE + #undef OPTION_CPU_CORELEVLING + #define OPTION_CPU_CORELEVLING TRUE + #undef OPTION_C6_STATE + #define OPTION_C6_STATE TRUE + #undef OPTION_IO_CSTATE + #define OPTION_IO_CSTATE TRUE + #undef OPTION_CPB + #define OPTION_CPB TRUE + #undef OPTION_CPU_PSI + #define OPTION_CPU_PSI TRUE + #undef OPTION_S3SCRIPT + #define OPTION_S3SCRIPT TRUE + #undef OPTION_CPU_CFOH + #define OPTION_CPU_CFOH TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif +#endif + +#if (OPTION_FT1_SOCKET_SUPPORT == TRUE) + #if (OPTION_FT1_T_SOCKET_SUPPORT == TRUE) + #undef FCH_SUPPORT + #define FCH_SUPPORT TRUE + #endif + #if (OPTION_FAMILY14H == TRUE) + #if (OPTION_FAMILY14H_FCH == TRUE) + #undef FCH_SUPPORT + #define FCH_SUPPORT TRUE + #endif + #undef OPTION_FAMILY14H_ON + #define OPTION_FAMILY14H_ON TRUE + #undef OPTION_MEMCTLR_ON + #define OPTION_MEMCTLR_ON TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_CONTINOUS_PATTERN_GENERATION + #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_HW_DQS_REC_EN_TRAINING + #define OPTION_HW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING + #define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_GFX_RECOVERY + #define OPTION_GFX_RECOVERY TRUE + #undef OPTION_C6_STATE + #define OPTION_C6_STATE TRUE + #undef OPTION_IO_CSTATE + #define OPTION_IO_CSTATE TRUE + #undef OPTION_CPB + #define OPTION_CPB TRUE + #undef OPTION_S3SCRIPT + #define OPTION_S3SCRIPT TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif +#endif + + +#if (OPTION_AM3_SOCKET_SUPPORT == TRUE) + #if (OPTION_FAMILY10H == TRUE) + #undef OPTION_FAMILY10H_BL + #define OPTION_FAMILY10H_BL TRUE + #undef OPTION_FAMILY10H_DA + #define OPTION_FAMILY10H_DA TRUE + #undef OPTION_FAMILY10H_PH + #define OPTION_FAMILY10H_PH TRUE + #undef OPTION_FAMILY10H_RB + #define OPTION_FAMILY10H_RB TRUE + #undef OPTION_MEMCTLR_RB + #define OPTION_MEMCTLR_RB TRUE + #undef OPTION_MEMCTLR_DA + #define OPTION_MEMCTLR_DA TRUE + #undef OPTION_MEMCTLR_PH + #define OPTION_MEMCTLR_PH TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING + #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_CPU_CORELEVLING + #define OPTION_CPU_CORELEVLING TRUE + #undef OPTION_CPU_CFOH + #define OPTION_CPU_CFOH TRUE + #undef OPTION_IO_CSTATE + #define OPTION_IO_CSTATE TRUE + #undef OPTION_CPB + #define OPTION_CPB TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_ECC + #define OPTION_ECC TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE TRUE + #undef OPTION_NODE_INTERLEAVE + #define OPTION_NODE_INTERLEAVE TRUE + #undef OPTION_PARALLEL_TRAINING + #define OPTION_PARALLEL_TRAINING TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_ONLINE_SPARE + #define OPTION_ONLINE_SPARE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif + #if (OPTION_FAMILY15H_MODEL_0x == TRUE) + #undef OPTION_FAMILY15H_OR + #define OPTION_FAMILY15H_OR TRUE + #undef OPTION_FAMILY15H_UNKNOWN + #define OPTION_FAMILY15H_UNKNOWN TRUE + #undef OPTION_MEMCTLR_OR + #define OPTION_MEMCTLR_OR TRUE + #undef OPTION_HW_WRITE_LEV_TRAINING + #define OPTION_HW_WRITE_LEV_TRAINING TRUE + #undef OPTION_CONTINOUS_PATTERN_GENERATION + #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE + #undef OPTION_HW_DQS_REC_EN_TRAINING + #define OPTION_HW_DQS_REC_EN_TRAINING TRUE + #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING + #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE + #undef OPTION_OPT_SW_RD_WR_POS_TRAINING + #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE + #undef OPTION_MAX_RD_LAT_TRAINING + #define OPTION_MAX_RD_LAT_TRAINING TRUE + #undef OPTION_SW_DRAM_INIT + #define OPTION_SW_DRAM_INIT TRUE + #undef OPTION_C6_STATE + #define OPTION_C6_STATE TRUE + #undef OPTION_IO_CSTATE + #define OPTION_IO_CSTATE TRUE + #undef OPTION_CPB + #define OPTION_CPB TRUE + #undef OPTION_CPU_APM + #define OPTION_CPU_APM TRUE + #undef OPTION_S3_MEM_SUPPORT + #define OPTION_S3_MEM_SUPPORT TRUE + #undef OPTION_ADDR_TO_CS_TRANSLATOR + #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE + #undef OPTION_ATM_MODE + #define OPTION_ATM_MODE TRUE + #undef OPTION_CPU_CORELEVLING + #define OPTION_CPU_CORELEVLING TRUE + #undef OPTION_CPU_CFOH + #define OPTION_CPU_CFOH TRUE + #undef OPTION_MSG_BASED_C1E + #define OPTION_MSG_BASED_C1E TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS TRUE + #undef OPTION_RDIMMS + #define OPTION_RDIMMS TRUE + #undef OPTION_LRDIMMS + #define OPTION_LRDIMMS TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 TRUE + #undef OPTION_ECC + #define OPTION_ECC TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE TRUE + #undef OPTION_NODE_INTERLEAVE + #define OPTION_NODE_INTERLEAVE TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE TRUE + #undef OPTION_ONLINE_SPARE + #define OPTION_ONLINE_SPARE TRUE + #undef OPTION_DIMM_EXCLUDE + #define OPTION_DIMM_EXCLUDE TRUE + #endif +#endif + + + + +#if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) || (OPTION_FAMILY15H_TN == TRUE) + #undef GNB_SUPPORT + #define GNB_SUPPORT TRUE +#endif + +#define OPTION_ACPI_PSTATES TRUE +#define OPTION_WHEA TRUE +#define OPTION_DMI TRUE +#define OPTION_EARLY_SAMPLES FALSE +#define CFG_ACPI_PSTATES_PPC TRUE +#define CFG_ACPI_PSTATES_PCT TRUE +#define CFG_ACPI_PSTATES_PSD TRUE +#define CFG_ACPI_PSTATES_PSS TRUE +#define CFG_ACPI_PSTATES_XPSS TRUE +#define CFG_ACPI_PSTATE_PSD_INDPX FALSE +#define CFG_VRM_HIGH_SPEED_ENABLE FALSE +#define CFG_VRM_NB_HIGH_SPEED_ENABLE FALSE +#define OPTION_ALIB TRUE +/*--------------------------------------------------------------------------- + * Processing the options: Second, process the user's selections + *--------------------------------------------------------------------------*/ +#ifdef BLDOPT_REMOVE_DDR3_SUPPORT + #if BLDOPT_REMOVE_DDR3_SUPPORT == TRUE + #undef OPTION_DDR3 + #define OPTION_DDR3 FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT + #if BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE + #undef OPTION_MULTISOCKET + #define OPTION_MULTISOCKET FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_ECC_SUPPORT + #if BLDOPT_REMOVE_ECC_SUPPORT == TRUE + #undef OPTION_ECC + #define OPTION_ECC FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT + #if BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE + #undef OPTION_UDIMMS + #define OPTION_UDIMMS FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT + #if BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE + #undef OPTION_RDIMMS + #define OPTION_RDIMMS FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT + #if BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE + #undef OPTION_SODIMMS + #define OPTION_SODIMMS FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_LRDIMMS_SUPPORT + #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE + #undef OPTION_LRDIMMS + #define OPTION_LRDIMMS FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE + #if BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE + #undef OPTION_BANK_INTERLEAVE + #define OPTION_BANK_INTERLEAVE FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE + #if BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE + #undef OPTION_DCT_INTERLEAVE + #define OPTION_DCT_INTERLEAVE FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE + #if BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE + #undef OPTION_NODE_INTERLEAVE + #define OPTION_NODE_INTERLEAVE FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING + #if BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE + #undef OPTION_PARALLEL_TRAINING + #define OPTION_PARALLEL_TRAINING FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT + #if BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE + #undef OPTION_ONLINE_SPARE + #define OPTION_ONLINE_SPARE FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT + #if BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE + #undef OPTION_MEM_RESTORE + #define OPTION_MEM_RESTORE FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING + #if BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING == TRUE + #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING + #define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_ACPI_PSTATES + #if BLDOPT_REMOVE_ACPI_PSTATES == TRUE + #undef OPTION_ACPI_PSTATES + #define OPTION_ACPI_PSTATES FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_SRAT + #if BLDOPT_REMOVE_SRAT == TRUE + #undef OPTION_SRAT + #define OPTION_SRAT FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_SLIT + #if BLDOPT_REMOVE_SLIT == TRUE + #undef OPTION_SLIT + #define OPTION_SLIT FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_WHEA + #if BLDOPT_REMOVE_WHEA == TRUE + #undef OPTION_WHEA + #define OPTION_WHEA FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_DMI + #if BLDOPT_REMOVE_DMI == TRUE + #undef OPTION_DMI + #define OPTION_DMI FALSE + #endif +#endif +#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR + #if BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE + #undef OPTION_ADDR_TO_CS_TRANSLATOR + #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE + #endif +#endif + +#ifdef BLDOPT_REMOVE_HT_ASSIST + #if BLDOPT_REMOVE_HT_ASSIST == TRUE + #undef OPTION_HT_ASSIST + #define OPTION_HT_ASSIST FALSE + #endif +#endif + +#ifdef BLDOPT_REMOVE_ATM_MODE + #if BLDOPT_REMOVE_ATM_MODE == TRUE + #undef OPTION_ATM_MODE + #define OPTION_ATM_MODE FALSE + #endif +#endif + +#ifdef BLDOPT_REMOVE_MSG_BASED_C1E + #if BLDOPT_REMOVE_MSG_BASED_C1E == TRUE + #undef OPTION_MSG_BASED_C1E + #define OPTION_MSG_BASED_C1E FALSE + #endif +#endif + +#ifdef BLDOPT_REMOVE_C6_STATE + #if BLDOPT_REMOVE_C6_STATE == TRUE + #undef OPTION_C6_STATE + #define OPTION_C6_STATE FALSE + #endif +#endif + +#ifdef BLDOPT_REMOVE_GFX_RECOVERY + #if BLDOPT_REMOVE_GFX_RECOVERY == TRUE + #undef OPTION_GFX_RECOVERY + #define OPTION_GFX_RECOVERY FALSE + #endif +#endif + + +#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC + #if BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE + #undef CFG_ACPI_PSTATES_PPC + #define CFG_ACPI_PSTATES_PPC FALSE + #endif +#endif + +#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT + #if BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE + #undef CFG_ACPI_PSTATES_PCT + #define CFG_ACPI_PSTATES_PCT FALSE + #endif +#endif + +#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD + #if BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE + #undef CFG_ACPI_PSTATES_PSD + #define CFG_ACPI_PSTATES_PSD FALSE + #endif +#endif + +#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS + #if BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE + #undef CFG_ACPI_PSTATES_PSS + #define CFG_ACPI_PSTATES_PSS FALSE + #endif +#endif + +#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS + #if BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE + #undef CFG_ACPI_PSTATES_XPSS + #define CFG_ACPI_PSTATES_XPSS FALSE + #endif +#endif + +#ifdef BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT + #if BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT == TRUE + #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT + #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE + #endif +#endif + +#ifdef BLDCFG_PSTATE_HPC_MODE + #if BLDCFG_PSTATE_HPC_MODE == TRUE + #undef OPTION_CPU_PSTATE_HPC_MODE + #define OPTION_CPU_PSTATE_HPC_MODE TRUE + #endif +#endif + +#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT + #if BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE + #undef CFG_ACPI_PSTATE_PSD_INDPX + #define CFG_ACPI_PSTATE_PSD_INDPX TRUE + #endif +#endif + +#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE + #if BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE + #undef CFG_VRM_HIGH_SPEED_ENABLE + #define CFG_VRM_HIGH_SPEED_ENABLE TRUE + #endif +#endif + +#ifdef BLDCFG_VRM_NB_HIGH_SPEED_ENABLE + #if BLDCFG_VRM_NB_HIGH_SPEED_ENABLE == TRUE + #undef CFG_VRM_NB_HIGH_SPEED_ENABLE + #define CFG_VRM_NB_HIGH_SPEED_ENABLE TRUE + #endif +#endif + +#ifdef BLDCFG_STARTING_BUSNUM + #define CFG_STARTING_BUSNUM (BLDCFG_STARTING_BUSNUM) +#else + #define CFG_STARTING_BUSNUM (0) +#endif + +#ifdef BLDCFG_AMD_PLATFORM_TYPE + #define CFG_AMD_PLATFORM_TYPE BLDCFG_AMD_PLATFORM_TYPE +#else + #define CFG_AMD_PLATFORM_TYPE 0 +#endif + +CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; + +#ifdef BLDCFG_MAXIMUM_BUSNUM + #define CFG_MAXIMUM_BUSNUM (BLDCFG_MAXIMUM_BUSNUM) +#else + #define CFG_MAXIMUM_BUSNUM (0xF8) +#endif + +#ifdef BLDCFG_ALLOCATED_BUSNUM + #define CFG_ALLOCATED_BUSNUM (BLDCFG_ALLOCATED_BUSNUM) +#else + #define CFG_ALLOCATED_BUSNUM (0x20) +#endif + +#ifdef BLDCFG_BUID_SWAP_LIST + #define CFG_BUID_SWAP_LIST (BLDCFG_BUID_SWAP_LIST) +#else + #define CFG_BUID_SWAP_LIST (NULL) +#endif + +#ifdef BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST + #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST) +#else + #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (NULL) +#endif + +#ifdef BLDCFG_HTFABRIC_LIMITS_LIST + #define CFG_HTFABRIC_LIMITS_LIST (BLDCFG_HTFABRIC_LIMITS_LIST) +#else + #define CFG_HTFABRIC_LIMITS_LIST (NULL) +#endif + +#ifdef BLDCFG_HTCHAIN_LIMITS_LIST + #define CFG_HTCHAIN_LIMITS_LIST (BLDCFG_HTCHAIN_LIMITS_LIST) +#else + #define CFG_HTCHAIN_LIMITS_LIST (NULL) +#endif + +#ifdef BLDCFG_BUS_NUMBERS_LIST + #define CFG_BUS_NUMBERS_LIST (BLDCFG_BUS_NUMBERS_LIST) +#else + #define CFG_BUS_NUMBERS_LIST (NULL) +#endif + +#ifdef BLDCFG_IGNORE_LINK_LIST + #define CFG_IGNORE_LINK_LIST (BLDCFG_IGNORE_LINK_LIST) +#else + #define CFG_IGNORE_LINK_LIST (NULL) +#endif + +#ifdef BLDCFG_LINK_SKIP_REGANG_LIST + #define CFG_LINK_SKIP_REGANG_LIST (BLDCFG_LINK_SKIP_REGANG_LIST) +#else + #define CFG_LINK_SKIP_REGANG_LIST (NULL) +#endif + +#ifdef BLDCFG_SET_HTCRC_SYNC_FLOOD + #define CFG_SET_HTCRC_SYNC_FLOOD (BLDCFG_SET_HTCRC_SYNC_FLOOD) +#else + #define CFG_SET_HTCRC_SYNC_FLOOD (FALSE) +#endif + +#ifdef BLDCFG_USE_UNIT_ID_CLUMPING + #define CFG_USE_UNIT_ID_CLUMPING (BLDCFG_USE_UNIT_ID_CLUMPING) +#else + #define CFG_USE_UNIT_ID_CLUMPING (FALSE) +#endif + +#ifdef BLDCFG_ADDITIONAL_TOPOLOGIES_LIST + #define CFG_ADDITIONAL_TOPOLOGIES_LIST (BLDCFG_ADDITIONAL_TOPOLOGIES_LIST) +#else + #define CFG_ADDITIONAL_TOPOLOGIES_LIST (NULL) +#endif + +#ifdef BLDCFG_USE_HT_ASSIST + #define CFG_USE_HT_ASSIST (BLDCFG_USE_HT_ASSIST) +#else + #define CFG_USE_HT_ASSIST (TRUE) +#endif + +#ifdef BLDCFG_USE_ATM_MODE + #define CFG_USE_ATM_MODE (BLDCFG_USE_ATM_MODE) +#else + #define CFG_USE_ATM_MODE (TRUE) +#endif + +#ifdef BLDCFG_PLATFORM_CONTROL_FLOW_MODE + #define CFG_PLATFORM_CONTROL_FLOW_MODE (BLDCFG_PLATFORM_CONTROL_FLOW_MODE) +#else + #define CFG_PLATFORM_CONTROL_FLOW_MODE (Nfcm) +#endif + +#ifdef BLDCFG_PERFORMANCE_HARDWARE_PREFETCHER + #define CFG_PERFORMANCE_HARDWARE_PREFETCHER (BLDCFG_PERFORMANCE_HARDWARE_PREFETCHER) +#else + #define CFG_PERFORMANCE_HARDWARE_PREFETCHER (HARDWARE_PREFETCHER_AUTO) +#endif + +#ifdef BLDCFG_PERFORMANCE_SOFTWARE_PREFETCHES + #define CFG_PERFORMANCE_SOFTWARE_PREFETCHES (BLDCFG_PERFORMANCE_SOFTWARE_PREFETCHES) +#else + #define CFG_PERFORMANCE_SOFTWARE_PREFETCHES (SOFTWARE_PREFETCHES_AUTO) +#endif + +#ifdef BLDCFG_PERFORMANCE_DRAM_PREFETCHER + #define CFG_PERFORMANCE_DRAM_PREFETCHER (BLDCFG_PERFORMANCE_DRAM_PREFETCHER) +#else + #define CFG_PERFORMANCE_DRAM_PREFETCHER (DRAM_PREFETCHER_AUTO) +#endif + +#ifdef BLDCFG_PLATFORM_DEEMPHASIS_LIST + #define CFG_PLATFORM_DEEMPHASIS_LIST (BLDCFG_PLATFORM_DEEMPHASIS_LIST) +#else + #define CFG_PLATFORM_DEEMPHASIS_LIST (NULL) +#endif + +#ifdef BLDCFG_VRM_ADDITIONAL_DELAY + #define CFG_VRM_ADDITIONAL_DELAY (BLDCFG_VRM_ADDITIONAL_DELAY) +#else + #define CFG_VRM_ADDITIONAL_DELAY (0) +#endif + +#ifdef BLDCFG_VRM_CURRENT_LIMIT + #define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT +#else + #define CFG_VRM_CURRENT_LIMIT 0 +#endif + +#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD + #define CFG_VRM_LOW_POWER_THRESHOLD BLDCFG_VRM_LOW_POWER_THRESHOLD +#else + #define CFG_VRM_LOW_POWER_THRESHOLD 0 +#endif + +#ifdef BLDCFG_VRM_SLEW_RATE + #define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE +#else + #define CFG_VRM_SLEW_RATE DFLT_VRM_SLEW_RATE +#endif + +#ifdef BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT + #ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT + #error BLDCFG: BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT is defined. Deprecated BLDCFG_VRM_INRUSH_CURRENT_LIMIT should not be defined. + #endif + #define CFG_VRM_MAXIMUM_CURRENT_LIMIT BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT +#else + #ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT + #define CFG_VRM_MAXIMUM_CURRENT_LIMIT BLDCFG_VRM_INRUSH_CURRENT_LIMIT + #else + #define CFG_VRM_MAXIMUM_CURRENT_LIMIT (0) + #endif +#endif + +#ifdef BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT + #ifdef BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT + #error BLDCFG: BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT is defined. Deprecated BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT should not be defined. + #endif + #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT +#else + #ifdef BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT + #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT + #else + #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT (0) + #endif +#endif + +#ifdef BLDCFG_VRM_SVI_OCP_LEVEL + #define CFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_SVI_OCP_LEVEL +#else + #define CFG_VRM_SVI_OCP_LEVEL 0 +#endif + +#ifdef BLDCFG_VRM_NB_SVI_OCP_LEVEL + #define CFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_SVI_OCP_LEVEL +#else + #define CFG_VRM_NB_SVI_OCP_LEVEL 0 +#endif + +#ifdef BLDCFG_VRM_NB_ADDITIONAL_DELAY + #define CFG_VRM_NB_ADDITIONAL_DELAY (BLDCFG_VRM_NB_ADDITIONAL_DELAY) +#else + #define CFG_VRM_NB_ADDITIONAL_DELAY (0) +#endif + +#ifdef BLDCFG_VRM_NB_CURRENT_LIMIT + #define CFG_VRM_NB_CURRENT_LIMIT BLDCFG_VRM_NB_CURRENT_LIMIT +#else + #define CFG_VRM_NB_CURRENT_LIMIT (0) +#endif + +#ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD + #define CFG_VRM_NB_LOW_POWER_THRESHOLD BLDCFG_VRM_NB_LOW_POWER_THRESHOLD +#else + #define CFG_VRM_NB_LOW_POWER_THRESHOLD (0) +#endif + +#ifdef BLDCFG_VRM_NB_SLEW_RATE + #define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE +#else + #define CFG_VRM_NB_SLEW_RATE DFLT_VRM_SLEW_RATE +#endif + +#ifdef BLDCFG_PLAT_NUM_IO_APICS + #define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS +#else + #define CFG_PLAT_NUM_IO_APICS 0 +#endif + +#ifdef BLDCFG_MEM_INIT_PSTATE + #define CFG_MEM_INIT_PSTATE BLDCFG_MEM_INIT_PSTATE +#else + #define CFG_MEM_INIT_PSTATE 0 +#endif + +#ifdef BLDCFG_PLATFORM_C1E_MODE + #define CFG_C1E_MODE BLDCFG_PLATFORM_C1E_MODE +#else + #define CFG_C1E_MODE C1eModeDisabled +#endif + +#ifdef BLDCFG_PLATFORM_C1E_OPDATA + #define CFG_C1E_OPDATA BLDCFG_PLATFORM_C1E_OPDATA +#else + #define CFG_C1E_OPDATA 0 +#endif + +#ifdef BLDCFG_PLATFORM_C1E_OPDATA1 + #define CFG_C1E_OPDATA1 BLDCFG_PLATFORM_C1E_OPDATA1 +#else + #define CFG_C1E_OPDATA1 0 +#endif + +#ifdef BLDCFG_PLATFORM_C1E_OPDATA2 + #define CFG_C1E_OPDATA2 BLDCFG_PLATFORM_C1E_OPDATA2 +#else + #define CFG_C1E_OPDATA2 0 +#endif + +#ifdef BLDCFG_PLATFORM_C1E_OPDATA3 + #define CFG_C1E_OPDATA3 BLDCFG_PLATFORM_C1E_OPDATA3 +#else + #define CFG_C1E_OPDATA3 0 +#endif + +#ifdef BLDCFG_PLATFORM_CSTATE_MODE + #define CFG_CSTATE_MODE BLDCFG_PLATFORM_CSTATE_MODE +#else + #define CFG_CSTATE_MODE CStateModeC6 +#endif + +#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA + #define CFG_CSTATE_OPDATA BLDCFG_PLATFORM_CSTATE_OPDATA +#else + #define CFG_CSTATE_OPDATA 0 +#endif + +#ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS + #define CFG_CSTATE_IO_BASE_ADDRESS BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS +#else + #define CFG_CSTATE_IO_BASE_ADDRESS 0 +#endif + +#ifdef BLDCFG_PLATFORM_CPB_MODE + #define CFG_CPB_MODE BLDCFG_PLATFORM_CPB_MODE +#else + #define CFG_CPB_MODE CpbModeAuto +#endif + +#ifdef BLDCFG_CORE_LEVELING_MODE + #define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE +#else + #define CFG_CORE_LEVELING_MODE 0 +#endif + +#ifdef BLDCFG_AMD_PSTATE_CAP_VALUE + #define CFG_AMD_PSTATE_CAP_VALUE BLDCFG_AMD_PSTATE_CAP_VALUE +#else + #define CFG_AMD_PSTATE_CAP_VALUE 0 +#endif + +#ifdef BLDCFG_HEAP_DRAM_ADDRESS + #define CFG_HEAP_DRAM_ADDRESS BLDCFG_HEAP_DRAM_ADDRESS +#else + #define CFG_HEAP_DRAM_ADDRESS AMD_HEAP_RAM_ADDRESS +#endif + +#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT + #define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT +#else + #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY +#endif + +#ifdef BLDCFG_MEMORY_MODE_UNGANGED + #define CFG_MEMORY_MODE_UNGANGED BLDCFG_MEMORY_MODE_UNGANGED +#else + #define CFG_MEMORY_MODE_UNGANGED TRUE +#endif + +#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE + #define CFG_MEMORY_QUAD_RANK_CAPABLE BLDCFG_MEMORY_QUAD_RANK_CAPABLE +#else + #define CFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#endif + +#ifdef BLDCFG_MEMORY_QUADRANK_TYPE + #define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE +#else + #define CFG_MEMORY_QUADRANK_TYPE DFLT_MEMORY_QUADRANK_TYPE +#endif + +#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE + #define CFG_MEMORY_RDIMM_CAPABLE BLDCFG_MEMORY_RDIMM_CAPABLE +#else + #define CFG_MEMORY_RDIMM_CAPABLE TRUE +#endif + +#ifdef BLDCFG_MEMORY_LRDIMM_CAPABLE + #define CFG_MEMORY_LRDIMM_CAPABLE BLDCFG_MEMORY_LRDIMM_CAPABLE +#else + #define CFG_MEMORY_LRDIMM_CAPABLE TRUE +#endif + +#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE + #define CFG_MEMORY_UDIMM_CAPABLE BLDCFG_MEMORY_UDIMM_CAPABLE +#else + #define CFG_MEMORY_UDIMM_CAPABLE TRUE +#endif + +#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE + #define CFG_MEMORY_SODIMM_CAPABLE BLDCFG_MEMORY_SODIMM_CAPABLE +#else + #define CFG_MEMORY_SODIMM_CAPABLE FALSE +#endif + +#ifdef BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB + #define CFG_LIMIT_MEMORY_TO_BELOW_1TB BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB +#else + #define CFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE +#endif + +#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING + #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING +#else + #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#endif + +#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING + #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING +#else + #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#endif + +#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING + #define CFG_MEMORY_CHANNEL_INTERLEAVING BLDCFG_MEMORY_CHANNEL_INTERLEAVING +#else + #define CFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#endif + +#ifdef BLDCFG_MEMORY_POWER_DOWN + #define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN +#else + #define CFG_MEMORY_POWER_DOWN FALSE +#endif + +#ifdef BLDCFG_POWER_DOWN_MODE + #define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE +#else + #define CFG_POWER_DOWN_MODE POWER_DOWN_MODE_AUTO +#endif + +#ifdef BLDCFG_ONLINE_SPARE + #define CFG_ONLINE_SPARE BLDCFG_ONLINE_SPARE +#else + #define CFG_ONLINE_SPARE FALSE +#endif + +#ifdef BLDCFG_MEMORY_PARITY_ENABLE + #define CFG_MEMORY_PARITY_ENABLE BLDCFG_MEMORY_PARITY_ENABLE +#else + #define CFG_MEMORY_PARITY_ENABLE FALSE +#endif + +#ifdef BLDCFG_BANK_SWIZZLE + #define CFG_BANK_SWIZZLE BLDCFG_BANK_SWIZZLE +#else + #define CFG_BANK_SWIZZLE TRUE +#endif + +#ifdef BLDCFG_TIMING_MODE_SELECT + #define CFG_TIMING_MODE_SELECT BLDCFG_TIMING_MODE_SELECT +#else + #define CFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#endif + +#ifdef BLDCFG_MEMORY_CLOCK_SELECT + #define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT +#else + #define CFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY +#endif + +#ifdef BLDCFG_DQS_TRAINING_CONTROL + #define CFG_DQS_TRAINING_CONTROL BLDCFG_DQS_TRAINING_CONTROL +#else + #define CFG_DQS_TRAINING_CONTROL TRUE +#endif + +#ifdef BLDCFG_IGNORE_SPD_CHECKSUM + #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM +#else + #define CFG_IGNORE_SPD_CHECKSUM FALSE +#endif + +#ifdef BLDCFG_USE_BURST_MODE + #define CFG_USE_BURST_MODE BLDCFG_USE_BURST_MODE +#else + #define CFG_USE_BURST_MODE FALSE +#endif + +#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON + #define CFG_MEMORY_ALL_CLOCKS_ON BLDCFG_MEMORY_ALL_CLOCKS_ON +#else + #define CFG_MEMORY_ALL_CLOCKS_ON FALSE +#endif + +#ifdef BLDCFG_ENABLE_ECC_FEATURE + #define CFG_ENABLE_ECC_FEATURE BLDCFG_ENABLE_ECC_FEATURE +#else + #define CFG_ENABLE_ECC_FEATURE TRUE +#endif + +#ifdef BLDCFG_ECC_REDIRECTION + #define CFG_ECC_REDIRECTION BLDCFG_ECC_REDIRECTION +#else + #define CFG_ECC_REDIRECTION FALSE +#endif + +#ifdef BLDCFG_SCRUB_DRAM_RATE + #define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE +#else + #define CFG_SCRUB_DRAM_RATE DFLT_SCRUB_DRAM_RATE +#endif + +#ifdef BLDCFG_SCRUB_L2_RATE + #define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE +#else + #define CFG_SCRUB_L2_RATE DFLT_SCRUB_L2_RATE +#endif + +#ifdef BLDCFG_SCRUB_L3_RATE + #define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE +#else + #define CFG_SCRUB_L3_RATE DFLT_SCRUB_L3_RATE +#endif + +#ifdef BLDCFG_SCRUB_IC_RATE + #define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE +#else + #define CFG_SCRUB_IC_RATE DFLT_SCRUB_IC_RATE +#endif + +#ifdef BLDCFG_SCRUB_DC_RATE + #define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE +#else + #define CFG_SCRUB_DC_RATE DFLT_SCRUB_DC_RATE +#endif + +#ifdef BLDCFG_ECC_SYNC_FLOOD + #define CFG_ECC_SYNC_FLOOD BLDCFG_ECC_SYNC_FLOOD +#else + #define CFG_ECC_SYNC_FLOOD TRUE +#endif + +#ifdef BLDCFG_ECC_SYMBOL_SIZE + #define CFG_ECC_SYMBOL_SIZE BLDCFG_ECC_SYMBOL_SIZE +#else + #define CFG_ECC_SYMBOL_SIZE 0 +#endif + +#ifdef BLDCFG_1GB_ALIGN + #define CFG_1GB_ALIGN BLDCFG_1GB_ALIGN +#else + #define CFG_1GB_ALIGN FALSE +#endif + +#ifdef BLDCFG_UMA_ALLOCATION_MODE + #define CFG_UMA_MODE BLDCFG_UMA_ALLOCATION_MODE +#else + #define CFG_UMA_MODE UMA_AUTO +#endif + +#ifdef BLDCFG_FORCE_TRAINING_MODE + #define CFG_FORCE_TRAIN_MODE BLDCFG_FORCE_TRAINING_MODE +#else + #define CFG_FORCE_TRAIN_MODE FORCE_TRAIN_AUTO +#endif + +#ifdef BLDCFG_UMA_ALLOCATION_SIZE + #define CFG_UMA_SIZE BLDCFG_UMA_ALLOCATION_SIZE +#else + #define CFG_UMA_SIZE 0 +#endif + +#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT + #define CFG_UMA_ABOVE4G BLDCFG_UMA_ABOVE4G_SUPPORT +#else + #define CFG_UMA_ABOVE4G FALSE +#endif + +#ifdef BLDCFG_UMA_ALIGNMENT + #define CFG_UMA_ALIGNMENT BLDCFG_UMA_ALIGNMENT +#else + #define CFG_UMA_ALIGNMENT NO_UMA_ALIGNED +#endif + +#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB + #define CFG_PROCESSOR_SCOPE_IN_SB BLDCFG_PROCESSOR_SCOPE_IN_SB +#else + #define CFG_PROCESSOR_SCOPE_IN_SB FALSE +#endif + +#ifdef BLDCFG_S3_LATE_RESTORE + #define CFG_S3_LATE_RESTORE BLDCFG_S3_LATE_RESTORE +#else + #define CFG_S3_LATE_RESTORE TRUE +#endif + +#ifdef BLDCFG_USE_32_BYTE_REFRESH + #define CFG_USE_32_BYTE_REFRESH (BLDCFG_USE_32_BYTE_REFRESH) +#else + #define CFG_USE_32_BYTE_REFRESH (FALSE) +#endif + +#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY + #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY) +#else + #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (FALSE) +#endif + +#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0 + #define CFG_PROCESSOR_SCOPE_NAME0 BLDCFG_PROCESSOR_SCOPE_NAME0 +#else + #define CFG_PROCESSOR_SCOPE_NAME0 SCOPE_NAME_VALUE +#endif + +#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1 + #define CFG_PROCESSOR_SCOPE_NAME1 BLDCFG_PROCESSOR_SCOPE_NAME1 +#else + #define CFG_PROCESSOR_SCOPE_NAME1 SCOPE_NAME_VALUE1 +#endif + +#ifdef BLDCFG_CFG_GNB_HD_AUDIO + #define CFG_GNB_HD_AUDIO BLDCFG_CFG_GNB_HD_AUDIO +#else + #define CFG_GNB_HD_AUDIO TRUE +#endif + +#ifdef BLDCFG_CFG_ABM_SUPPORT + #define CFG_ABM_SUPPORT BLDCFG_CFG_ABM_SUPPORT +#else + #define CFG_ABM_SUPPORT FALSE +#endif + +#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE + #define CFG_DYNAMIC_REFRESH_RATE BLDCFG_CFG_DYNAMIC_REFRESH_RATE +#else + #define CFG_DYNAMIC_REFRESH_RATE 0 +#endif + +#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL + #define CFG_LCD_BACK_LIGHT_CONTROL BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL +#else + #define CFG_LCD_BACK_LIGHT_CONTROL 0 +#endif + +#ifdef BLDCFG_STEREO_3D_PINOUT + #define CFG_GNB_STEREO_3D_PINOUT BLDCFG_STEREO_3D_PINOUT +#else + #define CFG_GNB_STEREO_3D_PINOUT 0 +#endif + +#ifdef BLDCFG_REMOTE_DISPLAY_SUPPORT + #define CFG_GNB_REMOTE_DISPLAY_SUPPORT BLDCFG_REMOTE_DISPLAY_SUPPORT +#else + #define CFG_GNB_REMOTE_DISPLAY_SUPPORT FALSE +#endif + +// Define pin configuration for SYNCFLOOD +// Default to FALSE (Use pin as SYNCFLOOD) +#ifdef BLDCFG_USE_SYNCFLOOD_AS_NMI + #define CFG_GNB_SYNCFLOOD_PIN_AS_NMI BLDCFG_USE_SYNCFLOOD_AS_NMI +#else + #define CFG_GNB_SYNCFLOOD_PIN_AS_NMI FALSE +#endif + +#ifdef BLDCFG_GNB_THERMAL_SENSOR_CORRECTION + #define CFG_GNB_THERMAL_SENSOR_CORRECTION BLDCFG_GNB_THERMAL_SENSOR_CORRECTION +#else + #define CFG_GNB_THERMAL_SENSOR_CORRECTION 0 +#endif + +#ifdef BLDCFG_IGPU_SUBSYSTEM_ID + #define CFG_GNB_IGPU_SSID BLDCFG_IGPU_SUBSYSTEM_ID +#else + #define CFG_GNB_IGPU_SSID 0 +#endif + +#ifdef BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID + #define CFG_GNB_HDAUDIO_SSID BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID +#else + #define CFG_GNB_HDAUDIO_SSID 0 +#endif + +#ifdef BLDCFG_IGPU_ENABLE_DISABLE_POLICY + #define CFG_IGPU_ENABLE_DISABLE_POLICY BLDCFG_IGPU_ENABLE_DISABLE_POLICY +#else + #define CFG_IGPU_ENABLE_DISABLE_POLICY IGPU_DISABLE_AUTO +#endif + +#ifdef BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID + #define CFG_GNB_PCIE_SSID BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID +#else + #define CFG_GNB_PCIE_SSID 0x12341022ul +#endif + +#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM + #define CFG_GFX_LVDS_SPREAD_SPECTRUM BLDCFG_GFX_LVDS_SPREAD_SPECTRUM +#else + #define CFG_GFX_LVDS_SPREAD_SPECTRUM 0 +#endif + +#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE + #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE +#else + #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE 0 +#endif + +#ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM + #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM +#else + #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM 0 +#endif + +#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS + #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS +#else + #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000ul +#endif + +#ifdef BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE + #define CFG_ENABLE_EXTERNAL_VREF BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE +#else + #define CFG_ENABLE_EXTERNAL_VREF FALSE +#endif + + +#ifdef BLDOPT_REMOVE_ALIB + #if BLDOPT_REMOVE_ALIB == TRUE + #undef OPTION_ALIB + #define OPTION_ALIB FALSE + #else + #undef OPTION_ALIB + #define OPTION_ALIB TRUE + #endif +#endif + +#ifdef BLDOPT_REMOVE_FCH_COMPONENT + #if BLDOPT_REMOVE_FCH_COMPONENT == TRUE + #undef FCH_SUPPORT + #define FCH_SUPPORT FALSE + #endif +#endif + +#ifdef BLDCFG_IOMMU_SUPPORT + #define CFG_IOMMU_SUPPORT BLDCFG_IOMMU_SUPPORT +#else + #define CFG_IOMMU_SUPPORT TRUE +#endif + +#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE + #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE +#else + #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE 0 +#endif + +#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL + #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL +#else + #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL 0 +#endif + +#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON + #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON +#else + #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON 0 +#endif + +#ifdef BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE + #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE +#else + #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE 0 +#endif + +#ifdef BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY + #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY +#else + #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY 0 +#endif + +#ifdef BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON + #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON +#else + #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 0 +#endif + +#ifdef BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL + #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL +#else + #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 0 +#endif + +#ifdef BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ + #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ +#else + #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ 0 +#endif + +#ifdef BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE + #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE +#else + #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE 0 +#endif + + +// BLDCFG_LVDS_24BBP_PANEL_MODE +// This specifies the LVDS 24 BBP mode. +// 0 - Use LDI mode (default). +// 1 - Use FPDI mode. +#ifdef BLDCFG_LVDS_24BBP_PANEL_MODE + #define CFG_LVDS_24BBP_PANEL_MODE BLDCFG_LVDS_24BBP_PANEL_MODE +#else + #define CFG_LVDS_24BBP_PANEL_MODE 0 +#endif + +#ifdef BLDCFG_LVDS_MISC_888_FPDI_MODE + #define CFG_LVDS_MISC_888_FPDI_MODE BLDCFG_LVDS_MISC_888_FPDI_MODE +#else + #define CFG_LVDS_MISC_888_FPDI_MODE FALSE +#endif + +#ifdef BLDCFG_LVDS_MISC_DL_CH_SWAP + #define CFG_LVDS_MISC_DL_CH_SWAP BLDCFG_LVDS_MISC_DL_CH_SWAP +#else + #define CFG_LVDS_MISC_DL_CH_SWAP FALSE +#endif + +#ifdef BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW + #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW +#else + #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW FALSE +#endif + +#ifdef BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW + #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW +#else + #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW FALSE +#endif + +#ifdef BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW + #define CFG_LVDS_MISC_BLON_ACTIVE_LOW BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW +#else + #define CFG_LVDS_MISC_BLON_ACTIVE_LOW FALSE +#endif + +#ifdef BLDCFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE + #define CFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE BLDCFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE +#else + #define CFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE FALSE +#endif + +#ifdef BLDCFG_LVDS_MISC_VOLT_ADJUSTMENT + #define CFG_LVDS_MISC_VOLT_ADJUSTMENT BLDCFG_LVDS_MISC_VOLT_ADJUSTMENT +#else + #define CFG_LVDS_MISC_VOLT_ADJUSTMENT 0 +#endif + +#ifdef BLDCFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE + #define CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE BLDCFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE +#else + #define CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE FALSE +#endif + +/*--------------------------------------------------------------------------- + * Processing the options: Third, perform the option cross checks + *--------------------------------------------------------------------------*/ +// Assure that at least one type of memory support is included +#if OPTION_UDIMMS == FALSE + #if OPTION_RDIMMS == FALSE + #if OPTION_SODIMMS == FALSE + #if OPTION_LRDIMMS == FALSE + #error BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT or BLDOPT_REMOVE_LRDIMMS_SUPPORT must be FALSE. + #endif + #endif + #endif +#endif +// Ensure at least one dimm type is capable +#if CFG_MEMORY_RDIMM_CAPABLE == FALSE + #if CFG_MEMORY_UDIMM_CAPABLE == FALSE + #if CFG_MEMORY_SODIMM_CAPABLE == FALSE + #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE + #error BLDCFG: No dimm type is capable + #endif + #endif + #endif +#endif +// Check LRDIMM CODE and LRDIMM CFG item +#if CFG_MEMORY_LRDIMM_CAPABLE == FALSE + #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE + #error Warning: LRDIMM capability is false, but LRIDMM support code included + #endif +#endif +// Turn off multi-socket based features if only one node... +#if OPTION_MULTISOCKET == FALSE + #undef OPTION_PARALLEL_TRAINING + #define OPTION_PARALLEL_TRAINING FALSE + #undef OPTION_NODE_INTERLEAVE + #define OPTION_NODE_INTERLEAVE FALSE +#endif +// Ensure the frequency limit is valid +#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR2133_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 1066) + #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1866_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 933) + #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800) + #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 667) + #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 533) + #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 400) + #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 333) + #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 266) + #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 200) + #error BLDCFG: Unsupported memory bus frequency + #endif + #endif + #endif + #endif + #endif + #endif + #endif + #endif +#endif +// Ensure timing mode is valid +#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC + #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED + #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO + #error BLDCFG: Invalid timing mode is set + #endif + #endif +#endif +// Ensure the scrub rate is valid +#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF)) + #error BLDCFG: Unsupported dram scrub rate set +#endif +#if CFG_SCRUB_L2_RATE > 0x16 + #error BLDCFG: Unsupported L2 scrubber rate set +#endif +#if CFG_SCRUB_L3_RATE > 0x16 + #error BLDCFG: unsupported L3 scrubber rate set +#endif +#if CFG_SCRUB_IC_RATE > 0x16 + #error BLDCFG: Unsupported Instruction cache scrub rate set +#endif +#if CFG_SCRUB_DC_RATE > 0x16 + #error BLDCFG: Unsupported Dcache scrub rate set +#endif +// Ensure Quad rank dimm type is valid +#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED + #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED + #error BLDCFG: Invalid quad rank dimm type set + #endif +#endif +// Ensure ECC symbol size is valid +#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG + #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4 + #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8 + #error BLDCFG: Invalid Ecc symbol size set + #endif + #endif +#endif +// Ensure power down mode is valid +#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT + #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL + #error BLDCFG: Invalid power down mode set + #endif +#endif + +/***************************************************************************** + * + * Process the option logic, setting local control variables + * + ****************************************************************************/ +#if OPTION_ACPI_PSTATES == TRUE + #define OPTFCN_ACPI_TABLES CreateAcpiTablesMain + #define OPTFCN_GATHER_DATA PStateGatherData + #if OPTION_MULTISOCKET == TRUE + #define OPTFCN_PSTATE_LEVELING PStateLeveling + #else + #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess + #endif +#else + #define OPTFCN_ACPI_TABLES CommonReturnAgesaSuccess + #define OPTFCN_GATHER_DATA CommonReturnAgesaSuccess + #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess +#endif + + +/***************************************************************************** + * + * Include the structure definitions for the defaults table structures + * + ****************************************************************************/ +#include "Options.h" +#include "OptionCpuFamiliesInstall.h" +#include "OptionsHt.h" +#include "OptionHtInstall.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "OptionMemoryInstall.h" +#include "OptionMemoryRecovery.h" +#include "OptionMemoryRecoveryInstall.h" +#include "OptionCpuFeaturesInstall.h" +#include "OptionDmi.h" +#include "OptionDmiInstall.h" +#include "OptionPstate.h" +#include "OptionPstateInstall.h" +#include "OptionWhea.h" +#include "OptionWheaInstall.h" +#include "OptionSrat.h" +#include "OptionSratInstall.h" +#include "OptionSlit.h" +#include "OptionSlitInstall.h" +#include "OptionMultiSocket.h" +#include "OptionMultiSocketInstall.h" +#include "OptionIdsInstall.h" +#include "OptionGfxRecovery.h" +#include "OptionGfxRecoveryInstall.h" +#include "OptionGnb.h" +#include "OptionGnbInstall.h" +#include "OptionS3ScriptInstall.h" +#include "OptionFchInstall.h" +#include "OptionMmioMapInstall.h" + + +/***************************************************************************** + * + * Generate the output structures (defaults tables) + * + ****************************************************************************/ + +FCH_PLATFORM_POLICY FchUserOptions = { + CFG_SMBUS0_BASE_ADDRESS, // CfgSmbus0BaseAddress + CFG_SMBUS1_BASE_ADDRESS, // CfgSmbus1BaseAddress + CFG_SIO_PME_BASE_ADDRESS, // CfgSioPmeBaseAddress + CFG_ACPI_PM1_EVT_BLOCK_ADDRESS, // CfgAcpiPm1EvtBlkAddr + CFG_ACPI_PM1_CNT_BLOCK_ADDRESS, // CfgAcpiPm1CntBlkAddr + CFG_ACPI_PM_TMR_BLOCK_ADDRESS, // CfgAcpiPmTmrBlkAddr + CFG_ACPI_CPU_CNT_BLOCK_ADDRESS, // CfgCpuControlBlkAddr + CFG_ACPI_GPE0_BLOCK_ADDRESS, // CfgAcpiGpe0BlkAddr + CFG_SMI_CMD_PORT_ADDRESS, // CfgSmiCmdPortAddr + CFG_ACPI_PMA_CNTBLK_ADDRESS, // CfgAcpiPmaCntBlkAddr + CFG_GEC_SHADOW_ROM_BASE, // CfgGecShadowRomBase + CFG_WATCHDOG_TIMER_BASE, // CfgWatchDogTimerBase + CFG_SPI_ROM_BASE_ADDRESS, // CfgSpiRomBaseAddress + CFG_HPET_BASE_ADDRESS, // CfgHpetBaseAddress + 0, + CFG_SMBUS_SSID, // CfgSmbusSsid + CFG_IDE_SSID, // CfgIdeSsid + CFG_SATA_AHCI_SSID, // CfgSataAhciSsid + CFG_SATA_IDE_SSID, // CfgSataIdeSsid + CFG_SATA_RAID5_SSID, // CfgSataRaid5Ssid + CFG_SATA_RAID_SSID, // CfgSataRaidSsid + CFG_EHCI_SSID, // CfgEhcidSsid + CFG_OHCI_SSID, // CfgOhcidSsid + CFG_LPC_SSID, // CfgLpcSsid + CFG_SD_SSID, // CfgSdSsid + CFG_XHCI_SSID, // CfgXhciSsid + CFG_FCH_PORT80_BEHIND_PCIB, // CfgFchPort80BehindPcib + CFG_FCH_ENABLE_ACPI_SLEEP_TRAP, // CfgFchEnableAcpiSleepTrap + CFG_FCH_GPP_LINK_CONFIG, // CfgFchGppLinkConfig + CFG_FCH_GPP_PORT0_PRESENT, // CfgFchGppPort0Present + CFG_FCH_GPP_PORT1_PRESENT, // CfgFchGppPort1Present + CFG_FCH_GPP_PORT2_PRESENT, // CfgFchGppPort2Present + CFG_FCH_GPP_PORT3_PRESENT, // CfgFchGppPort3Present + CFG_FCH_GPP_PORT0_HOTPLUG, // CfgFchGppPort0HotPlug + CFG_FCH_GPP_PORT1_HOTPLUG, // CfgFchGppPort1HotPlug + CFG_FCH_GPP_PORT2_HOTPLUG, // CfgFchGppPort2HotPlug + CFG_FCH_GPP_PORT3_HOTPLUG, // CfgFchGppPort3HotPlug + + CFG_FCH_ESATA_PORT_BITMAP, // CfgFchEsataPortBitMap + CFG_FCH_IR_PIN_CONTROL, // CfgFchIrPinControl + CFG_FCH_SD_CLOCK_CONTROL, // CfgFchSdClockControl + CFG_FCH_SCI_MAP_LIST, // *CfgFchSciMapControl + CFG_FCH_SATA_PHY_LIST, // *CfgFchSataPhyControl + CFG_FCH_GPIO_CONTROL_LIST // *CfgFchGpioControl +}; + +BUILD_OPT_CFG UserOptions = { + { // AGESA version string + AGESA_CODE_SIGNATURE, // code header Signature + AGESA_PACKAGE_STRING, // 8 character ID + AGESA_VERSION_STRING, // 12 character version string + 0 // null string terminator + }, + //Build Option Area + OPTION_UDIMMS, //UDIMMS + OPTION_RDIMMS, //RDIMMS + OPTION_LRDIMMS, //LRDIMMS + OPTION_ECC, //ECC + OPTION_BANK_INTERLEAVE, //BANK_INTERLEAVE + OPTION_DCT_INTERLEAVE, //DCT_INTERLEAVE + OPTION_NODE_INTERLEAVE, //NODE_INTERLEAVE + OPTION_PARALLEL_TRAINING, //PARALLEL_TRAINING + OPTION_ONLINE_SPARE, //ONLINE_SPARE + OPTION_MEM_RESTORE, //MEM CONTEXT RESTORE + OPTION_MULTISOCKET, //MULTISOCKET + OPTION_ACPI_PSTATES, //ACPI_PSTATES + OPTION_CPU_PSTATE_HPC_MODE, //High Preformace Computing (HPC) mode + FALSE, + FALSE, + OPTION_SRAT, //SRAT + OPTION_SLIT, //SLIT + OPTION_WHEA, //WHEA + OPTION_DMI, //DMI + OPTION_EARLY_SAMPLES, //EARLY_SAMPLES + OPTION_ADDR_TO_CS_TRANSLATOR, //ADDR_TO_CS_TRANSLATOR + + //Build Configuration Area + CFG_PCI_MMIO_BASE, + CFG_PCI_MMIO_SIZE, + { + // CoreVrm + { + CFG_VRM_CURRENT_LIMIT, // VrmCurrentLimit + CFG_VRM_LOW_POWER_THRESHOLD, // VrmLowPowerThershold + CFG_VRM_SLEW_RATE, // VrmSlewRate + CFG_VRM_ADDITIONAL_DELAY, // VrmAdditionalDelay + CFG_VRM_HIGH_SPEED_ENABLE, // VrmHiSpeedEnable + CFG_VRM_MAXIMUM_CURRENT_LIMIT, // VrmInrushCurrentLimit + CFG_VRM_SVI_OCP_LEVEL // VrmSviOcpLevel + }, + // NbVrm + { + CFG_VRM_NB_CURRENT_LIMIT, // VrmNbCurrentLimit + CFG_VRM_NB_LOW_POWER_THRESHOLD, // VrmNbLowPowerThershold + CFG_VRM_NB_SLEW_RATE, // VrmNbSlewRate + CFG_VRM_NB_ADDITIONAL_DELAY, // VrmNbAdditionalDelay + CFG_VRM_NB_HIGH_SPEED_ENABLE, // VrmNbHiSpeedEnable + CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT, // VrmNbInrushCurrentLimit + CFG_VRM_NB_SVI_OCP_LEVEL // VrmNbSviOcpLevel + } + }, + CFG_PLAT_NUM_IO_APICS, //PlatformApicIoNumber + CFG_MEM_INIT_PSTATE, //MemoryInitPstate + CFG_C1E_MODE, //C1eMode + CFG_C1E_OPDATA, //C1ePlatformData + CFG_C1E_OPDATA1, //C1ePlatformData1 + CFG_C1E_OPDATA2, //C1ePlatformData2 + CFG_C1E_OPDATA3, //C1ePlatformData3 + CFG_CSTATE_MODE, //CStateMode + CFG_CSTATE_OPDATA, //CStatePlatformData + CFG_CSTATE_IO_BASE_ADDRESS, //CStateIoBaseAddress + CFG_CPB_MODE, //CpbMode + LOW_POWER_PSTATE_FOR_PROCHOT_AUTO, //Low power Pstate for PROCHOT, it's always set to 'AUTO' + CFG_CORE_LEVELING_MODE, //CoreLevelingCofig + { + CFG_PLATFORM_CONTROL_FLOW_MODE, // The platform's control flow mode. + CFG_USE_HT_ASSIST, // CfgUseHtAssist + CFG_USE_ATM_MODE, // CfgUseAtmMode + CFG_USE_32_BYTE_REFRESH, // Display Refresh uses 32 byte packets. + CFG_USE_VARIABLE_MCT_ISOC_PRIORITY, // The Memory controller will be set to Variable Isoc Priority. + // ADVANCED_PERFORMANCE_PROFILE + { + CFG_PERFORMANCE_HARDWARE_PREFETCHER, // Hardware prefetcher mode + CFG_PERFORMANCE_SOFTWARE_PREFETCHES, // Software prefetcher mode + CFG_PERFORMANCE_DRAM_PREFETCHER // Dram prefetcher mode + }, + CFG_PLATFORM_POWER_POLICY_MODE // The platform's power policy mode. + }, + (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST, // Deemphasis settings + CFG_AMD_PLATFORM_TYPE, //AmdPlatformType + CFG_AMD_PSTATE_CAP_VALUE, // Amd pstate ceiling enabling deck + + CFG_MEMORY_BUS_FREQUENCY_LIMIT, // CfgMemoryBusFrequencyLimit + CFG_MEMORY_MODE_UNGANGED, // CfgMemoryModeUnganged + CFG_MEMORY_QUAD_RANK_CAPABLE, // CfgMemoryQuadRankCapable + CFG_MEMORY_QUADRANK_TYPE, // CfgMemoryQuadrankType + CFG_MEMORY_RDIMM_CAPABLE, // CfgMemoryRDimmCapable + CFG_MEMORY_LRDIMM_CAPABLE, // CfgMemoryLRDimmCapable + CFG_MEMORY_UDIMM_CAPABLE, // CfgMemoryUDimmCapable + CFG_MEMORY_SODIMM_CAPABLE, // CfgMemorySodimmCapable + CFG_LIMIT_MEMORY_TO_BELOW_1TB, // CfgLimitMemoryToBelow1Tb + CFG_MEMORY_ENABLE_BANK_INTERLEAVING, // CfgMemoryEnableBankInterleaving + CFG_MEMORY_ENABLE_NODE_INTERLEAVING, // CfgMemoryEnableNodeInterleaving + CFG_MEMORY_CHANNEL_INTERLEAVING, // CfgMemoryChannelInterleaving + CFG_MEMORY_POWER_DOWN, // CfgMemoryPowerDown + CFG_POWER_DOWN_MODE, // CfgPowerDownMode + CFG_ONLINE_SPARE, // CfgOnlineSpare + CFG_MEMORY_PARITY_ENABLE, // CfgMemoryParityEnable + CFG_BANK_SWIZZLE, // CfgBankSwizzle + CFG_TIMING_MODE_SELECT, // CfgTimingModeSelect + CFG_MEMORY_CLOCK_SELECT, // CfgMemoryClockSelect + CFG_DQS_TRAINING_CONTROL, // CfgDqsTrainingControl + CFG_IGNORE_SPD_CHECKSUM, // CfgIgnoreSpdChecksum + CFG_USE_BURST_MODE, // CfgUseBurstMode + CFG_MEMORY_ALL_CLOCKS_ON, // CfgMemoryAllClocksOn + CFG_ENABLE_ECC_FEATURE, // CfgEnableEccFeature + CFG_ECC_REDIRECTION, // CfgEccRedirection + CFG_SCRUB_DRAM_RATE, // CfgScrubDramRate + CFG_SCRUB_L2_RATE, // CfgScrubL2Rate + CFG_SCRUB_L3_RATE, // CfgScrubL3Rate + CFG_SCRUB_IC_RATE, // CfgScrubIcRate + CFG_SCRUB_DC_RATE, // CfgScrubDcRate + CFG_ECC_SYNC_FLOOD, // CfgEccSyncFlood + CFG_ECC_SYMBOL_SIZE, // CfgEccSymbolSize + CFG_HEAP_DRAM_ADDRESS, // CfgHeapDramAddress + CFG_1GB_ALIGN, // CfgNodeMem1GBAlign + CFG_S3_LATE_RESTORE, // CfgS3LateRestore + CFG_ACPI_PSTATE_PSD_INDPX, // CfgAcpiPstateIndependent + (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList + CFG_UMA_MODE, // CfgUmaMode + CFG_UMA_SIZE, // CfgUmaSize + CFG_UMA_ABOVE4G, // CfgUmaAbove4G + CFG_UMA_ALIGNMENT, // CfgUmaAlignment + CFG_PROCESSOR_SCOPE_IN_SB, // CfgProcessorScopeInSb + CFG_PROCESSOR_SCOPE_NAME0, // CfgProcessorScopeName0 + CFG_PROCESSOR_SCOPE_NAME1, // CfgProcessorScopeName1 + CFG_GNB_HD_AUDIO, // CfgGnbHdAudio + CFG_ABM_SUPPORT, // CfgAbmSupport + CFG_DYNAMIC_REFRESH_RATE, // CfgDynamicRefreshRate + CFG_LCD_BACK_LIGHT_CONTROL, // CfgLcdBackLightControl + CFG_GNB_STEREO_3D_PINOUT, // CfgGnb3dStereoPinIndex + CFG_TEMP_PCIE_MMIO_BASE_ADDRESS, // CfgTempPcieMmioBaseAddress + CFG_GNB_IGPU_SSID, // CfgGnbIGPUSSID + CFG_GNB_HDAUDIO_SSID, // CfgGnbHDAudioSSID + CFG_GNB_PCIE_SSID, // CfgGnbPcieSSID + CFG_GFX_LVDS_SPREAD_SPECTRUM, // CfgLvdsSpreadSpectrum + CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE, // CfgLvdsSpreadSpectrumRate + + &FchUserOptions, // FchBldCfg + + CFG_IOMMU_SUPPORT, // CfgIommuSupport + CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE, // CfgLvdsPowerOnSeqDigonToDe + CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL, // CfgLvdsPowerOnSeqDeToVaryBl + CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON, // CfgLvdsPowerOnSeqDeToDigon + CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE, // CfgLvdsPowerOnSeqVaryBlToDe + CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY,// CfgLvdsPowerOnSeqOnToOffDelay + CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON,// CfgLvdsPowerOnSeqVaryBlToBlon + CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL,// CfgLvdsPowerOnSeqBlonToVaryBl + CFG_LVDS_MAX_PIXEL_CLOCK_FREQ, // CfgLvdsMaxPixelClockFreq + CFG_LCD_BIT_DEPTH_CONTROL_VALUE, // CfgLcdBitDepthControlValue + CFG_LVDS_24BBP_PANEL_MODE, // CfgLvds24bbpPanelMode + {{ + CFG_LVDS_MISC_888_FPDI_MODE, // CfgLvdsMiscControl + CFG_LVDS_MISC_DL_CH_SWAP, // CfgLvdsMiscControl + CFG_LVDS_MISC_VSYNC_ACTIVE_LOW, // CfgLvdsMiscControl + CFG_LVDS_MISC_HSYNC_ACTIVE_LOW, // CfgLvdsMiscControl + CFG_LVDS_MISC_BLON_ACTIVE_LOW, // CfgLvdsMiscControl + CFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE, // CfgLvdsMiscControl + }}, + CFG_PCIE_REFCLK_SPREAD_SPECTRUM, // CfgPcieRefClkSpreadSpectrum + CFG_ENABLE_EXTERNAL_VREF, // CfgExternalVrefCtlFeature + CFG_FORCE_TRAIN_MODE, // CfgForceTrainMode + CFG_GNB_REMOTE_DISPLAY_SUPPORT, // CfgGnbRemoteDisplaySupport + (IOMMU_EXCLUSION_RANGE_DESCRIPTOR *) CFG_IOMMU_EXCLUSION_RANGE_LIST, // CfgIvrsExclusionRangeList + CFG_GNB_SYNCFLOOD_PIN_AS_NMI, // CfgGnbSyncFloodPinAsNmi + CFG_IGPU_ENABLE_DISABLE_POLICY, // CfgIgpuEnableDisablePolicy + CFG_GNB_THERMAL_SENSOR_CORRECTION, // CfgGnbSwTjOffset + CFG_LVDS_MISC_VOLT_ADJUSTMENT, // CfgLvdsMiscVoltAdjustment + {{ + 0, // Reserved + CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE, // CfgDisplayMiscControl.VbiosFastBootEn + 0, // Reserved + }}, + 0, //reserved... +}; + +CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] = +{ + #if AGESA_ENTRY_INIT_RESET == TRUE + { AMD_INIT_RESET, + sizeof (AMD_RESET_PARAMS), + (PF_AGESA_FUNCTION) AmdInitResetConstructor, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_RESET_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_RECOVERY == TRUE + { AMD_INIT_RECOVERY, + sizeof (AMD_RECOVERY_PARAMS), + (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_POST_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_EARLY == TRUE + { AMD_INIT_EARLY, + sizeof (AMD_EARLY_PARAMS), + (PF_AGESA_FUNCTION) AmdInitEarlyInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_EARLY_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_ENV == TRUE + { AMD_INIT_ENV, + sizeof (AMD_ENV_PARAMS), + (PF_AGESA_FUNCTION) AmdInitEnvInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_ENV_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_LATE == TRUE + { AMD_INIT_LATE, + sizeof (AMD_LATE_PARAMS), + (PF_AGESA_FUNCTION) AmdInitLateInitializer, + (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor, + AMD_INIT_LATE_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_MID == TRUE + { AMD_INIT_MID, + sizeof (AMD_MID_PARAMS), + (PF_AGESA_FUNCTION) AmdInitMidInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_MID_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_POST == TRUE + { AMD_INIT_POST, + sizeof (AMD_POST_PARAMS), + (PF_AGESA_FUNCTION) AmdInitPostInitializer, + (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor, + AMD_INIT_POST_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_RESUME == TRUE + { AMD_INIT_RESUME, + sizeof (AMD_RESUME_PARAMS), + (PF_AGESA_FUNCTION) AmdInitResumeInitializer, + (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor, + AMD_INIT_RESUME_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE + { AMD_S3LATE_RESTORE, + sizeof (AMD_S3LATE_PARAMS), + (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_S3_LATE_RESTORE_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_S3SAVE == TRUE + { AMD_S3_SAVE, + sizeof (AMD_S3SAVE_PARAMS), + (PF_AGESA_FUNCTION) AmdS3SaveInitializer, + (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor, + AMD_S3_SAVE_HANDLE + }, + #endif + + #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE + { AMD_LATE_RUN_AP_TASK, + sizeof (AP_EXE_PARAMS), + (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_LATE_RUN_AP_TASK_HANDLE + }, + #endif + { 0, 0, NULL, NULL, 0 } +}; + +CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0]))); + +CONST DISPATCH_TABLE ROMDATA DispatchTable[] = +{ + { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct }, + { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct }, + + #if AGESA_ENTRY_INIT_RESET == TRUE + { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset }, + #endif + + #if AGESA_ENTRY_INIT_RECOVERY == TRUE + { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery }, + #endif + + #if AGESA_ENTRY_INIT_EARLY == TRUE + { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly }, + #endif + + #if AGESA_ENTRY_INIT_POST == TRUE + { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost }, + #endif + + #if AGESA_ENTRY_INIT_ENV == TRUE + { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv }, + #endif + + #if AGESA_ENTRY_INIT_MID == TRUE + { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid }, + #endif + + #if AGESA_ENTRY_INIT_LATE == TRUE + { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate }, + #endif + + #if AGESA_ENTRY_INIT_S3SAVE == TRUE + { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save }, + #endif + + #if AGESA_ENTRY_INIT_RESUME == TRUE + { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume }, + #endif + + #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE + { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore }, + #endif + + #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE + { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId }, + { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress }, + { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore }, + { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog }, + { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm }, + { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize }, + #endif + + #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE + { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask }, + #endif + { 0, NULL } +}; + +CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] = +{ + IDS_LATE_RUN_AP_TASK + // Get DMI info + CPU_DMI_AP_GET_TYPE4_TYPE7 + // Probe filter enable + L3_FEAT_AP_DISABLE_CACHE + L3_FEAT_AP_ENABLE_CACHE + // Cpu Late Init + CPU_LATE_INIT_AP_TASK + { 0, NULL } +}; + +#if AGESA_ENTRY_INIT_EARLY == TRUE + #if IDSOPT_IDS_ENABLED == TRUE + #if IDSOPT_TRACING_ENABLED == TRUE + #define MAKE_DBG_STR(x, y) MAKE_AS_A_STRING(x : y) + CONST CHAR8 *BldOptDebugOutput[] = { + #if IDS_TRACE_SHOW_BLD_OPT_CFG == TRUE + //Build Option Area + MAKE_DBG_STR (\nOptUDIMM, OPTION_UDIMMS) + MAKE_DBG_STR (\nOptRDIMM, OPTION_RDIMMS) + MAKE_DBG_STR (\nOptLRDIMM, OPTION_LRDIMMS) + MAKE_DBG_STR (\nOptECC, OPTION_ECC) + MAKE_DBG_STR (\nOptCsIntlv, OPTION_BANK_INTERLEAVE) + MAKE_DBG_STR (\nOptDctIntlv, OPTION_DCT_INTERLEAVE) + MAKE_DBG_STR (\nOptNodeIntlv, OPTION_NODE_INTERLEAVE) + //MAKE_DBG_STR (\nOptParallelTraining, OPTION_PARALLEL_TRAINING) + MAKE_DBG_STR (\nOptOnlineSpare, OPTION_ONLINE_SPARE) + MAKE_DBG_STR (\nOptAddr2CsTranslator, OPTION_ADDR_TO_CS_TRANSLATOR) + MAKE_DBG_STR (\nOptMemRestore, OPTION_MEM_RESTORE) + MAKE_DBG_STR (\nOptMultiSocket, OPTION_MULTISOCKET) + MAKE_DBG_STR (\nOptPstates, OPTION_ACPI_PSTATES) + MAKE_DBG_STR (\nOptSRAT, OPTION_SRAT) + MAKE_DBG_STR (\nOptSLIT, OPTION_SLIT) + MAKE_DBG_STR (\nOptWHEA, OPTION_WHEA) + MAKE_DBG_STR (\nOptDMI, OPTION_DMI) + MAKE_DBG_STR (\nOptEarlySamples, OPTION_EARLY_SAMPLES), + + //Build Configuration Area + // CoreVrm + MAKE_DBG_STR (\nVrmCurrentLimit , CFG_VRM_CURRENT_LIMIT) + MAKE_DBG_STR (\nVrmLowPowerThreshold , CFG_VRM_LOW_POWER_THRESHOLD) + MAKE_DBG_STR (\nVrmSlewRate , CFG_VRM_SLEW_RATE) + MAKE_DBG_STR (\nVrmAdditionalDelay , CFG_VRM_ADDITIONAL_DELAY) + MAKE_DBG_STR (\nVrmHiSpeedEnable , CFG_VRM_HIGH_SPEED_ENABLE) + MAKE_DBG_STR (\nVrmInrushCurrentLimit, CFG_VRM_MAXIMUM_CURRENT_LIMIT) + MAKE_DBG_STR (\nVrmSviOcpLevel, CFG_VRM_SVI_OCP_LEVEL) + // NbVrm + MAKE_DBG_STR (\nNbVrmCurrentLimit , CFG_VRM_NB_CURRENT_LIMIT) + MAKE_DBG_STR (\nNbVrmLowPowerThreshold , CFG_VRM_NB_LOW_POWER_THRESHOLD) + MAKE_DBG_STR (\nNbVrmSlewRate , CFG_VRM_NB_SLEW_RATE) + MAKE_DBG_STR (\nNbVrmAdditionalDelay , CFG_VRM_NB_ADDITIONAL_DELAY) + MAKE_DBG_STR (\nNbVrmHiSpeedEnable , CFG_VRM_NB_HIGH_SPEED_ENABLE) + MAKE_DBG_STR (\nNbVrmInrushCurrentLimit, CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT), + MAKE_DBG_STR (\nNbVrmSviOcpLevel, CFG_VRM_NB_SVI_OCP_LEVEL) + + MAKE_DBG_STR (\nNumIoApics , CFG_PLAT_NUM_IO_APICS) + MAKE_DBG_STR (\nMemInitPstate , CFG_MEM_INIT_PSTATE) + MAKE_DBG_STR (\nC1eMode , CFG_C1E_MODE) + MAKE_DBG_STR (\nC1eOpData , CFG_C1E_OPDATA) + MAKE_DBG_STR (\nC1eOpdata1 , CFG_C1E_OPDATA1) + MAKE_DBG_STR (\nC1eOpdata2 , CFG_C1E_OPDATA2) + MAKE_DBG_STR (\nC1eOpdata3 , CFG_C1E_OPDATA3) + MAKE_DBG_STR (\nCStateMode , CFG_CSTATE_MODE) + MAKE_DBG_STR (\nCStateOpData , CFG_CSTATE_OPDATA) + MAKE_DBG_STR (\nCStateIoBaseAddr , CFG_CSTATE_IO_BASE_ADDRESS) + MAKE_DBG_STR (\nCpbMode , CFG_CPB_MODE) + MAKE_DBG_STR (\nCoreLevelingMode , CFG_CORE_LEVELING_MODE), + + MAKE_DBG_STR (\nControlFlowMode , CFG_PLATFORM_CONTROL_FLOW_MODE) + MAKE_DBG_STR (\nUseHtAssist , CFG_USE_HT_ASSIST) + MAKE_DBG_STR (\nUseAtmMode , CFG_USE_ATM_MODE) + MAKE_DBG_STR (\nUse32ByteRefresh , CFG_USE_32_BYTE_REFRESH) + MAKE_DBG_STR (\nUseVarMctIsocPriority , CFG_USE_VARIABLE_MCT_ISOC_PRIORITY) + MAKE_DBG_STR (\nPowerPolicy , CFG_PLATFORM_POWER_POLICY_MOD) + + MAKE_DBG_STR (\nDeemphasisList , CFG_PLATFORM_DEEMPHASIS_LIST) + + MAKE_DBG_STR (\nPciMmioAddr , CFG_PCI_MMIO_BASE) + MAKE_DBG_STR (\nPciMmioSize , CFG_PCI_MMIO_SIZE) + MAKE_DBG_STR (\nPlatformType , CFG_AMD_PLATFORM_TYPE) + MAKE_DBG_STR (\nPstateCapValue , CFG_AMD_PSTATE_CAP_VALUE), + + MAKE_DBG_STR (\nMemBusFreqLimit , CFG_MEMORY_BUS_FREQUENCY_LIMIT) + MAKE_DBG_STR (\nTimingModeSelect , CFG_TIMING_MODE_SELECT) + MAKE_DBG_STR (\nMemoryClockSelect , CFG_MEMORY_CLOCK_SELECT) + + MAKE_DBG_STR (\nMemUnganged , CFG_MEMORY_MODE_UNGANGED) + MAKE_DBG_STR (\nQRCap , CFG_MEMORY_QUAD_RANK_CAPABLE) + MAKE_DBG_STR (\nQRType , CFG_MEMORY_QUADRANK_TYPE) + MAKE_DBG_STR (\nRDimmCap , CFG_MEMORY_RDIMM_CAPABLE) + MAKE_DBG_STR (\nLRDimmCap , CFG_MEMORY_LRDIMM_CAPABLE) + MAKE_DBG_STR (\nUDimmCap , CFG_MEMORY_UDIMM_CAPABLE) + MAKE_DBG_STR (\nSODimmCap , CFG_MEMORY_SODIMM_CAPABLE) + MAKE_DBG_STR (\nDqsTrainingControl , CFG_DQS_TRAINING_CONTROL) + MAKE_DBG_STR (\nIgnoreSpdChecksum , CFG_IGNORE_SPD_CHECKSUM) + MAKE_DBG_STR (\nUseBurstMode , CFG_USE_BURST_MODE) + MAKE_DBG_STR (\nAllMemClkOn , CFG_MEMORY_ALL_CLOCKS_ON), + + MAKE_DBG_STR (\nPowerDownEn , CFG_MEMORY_POWER_DOWN) + MAKE_DBG_STR (\nPowerDownMode , CFG_POWER_DOWN_MODE) + MAKE_DBG_STR (\nOnlineSpare , CFG_ONLINE_SPARE) + MAKE_DBG_STR (\nAddrParityEn , CFG_MEMORY_PARITY_ENABLE) + MAKE_DBG_STR (\nBankSwizzle , CFG_BANK_SWIZZLE) + MAKE_DBG_STR (\nLimitBelow1TB , CFG_LIMIT_MEMORY_TO_BELOW_1TB) + MAKE_DBG_STR (\nCsIntlvEn , CFG_MEMORY_ENABLE_BANK_INTERLEAVING) + MAKE_DBG_STR (\nNodeIntlvEn , CFG_MEMORY_ENABLE_NODE_INTERLEAVING) + MAKE_DBG_STR (\nDctIntlvEn , CFG_MEMORY_CHANNEL_INTERLEAVING), + + MAKE_DBG_STR (\nUmaMode , CFG_UMA_MODE) + MAKE_DBG_STR (\nUmaSize , CFG_UMA_SIZE) + MAKE_DBG_STR (\nUmaAbove4G , CFG_UMA_ABOVE4G) + MAKE_DBG_STR (\nUmaAlignment , CFG_UMA_ALIGNMENT) + + MAKE_DBG_STR (\nEccEn , CFG_ENABLE_ECC_FEATURE) + MAKE_DBG_STR (\nEccRedirect , CFG_ECC_REDIRECTION) + MAKE_DBG_STR (\nScrubDramRate , CFG_SCRUB_DRAM_RATE) + MAKE_DBG_STR (\nScrubL2Rate , CFG_SCRUB_L2_RATE) + MAKE_DBG_STR (\nScrubL3Rate , CFG_SCRUB_L3_RATE) + MAKE_DBG_STR (\nScrubIcRate , CFG_SCRUB_IC_RATE) + MAKE_DBG_STR (\nScrubDcRate , CFG_SCRUB_DC_RATE) + MAKE_DBG_STR (\nEccSyncFlood , CFG_ECC_SYNC_FLOOD) + MAKE_DBG_STR (\nEccSymbolSize , CFG_ECC_SYMBOL_SIZE) + MAKE_DBG_STR (\nHeapDramAddress , CFG_HEAP_DRAM_ADDRESS) + MAKE_DBG_STR (\nNodeMem1GBAlign , CFG_1GB_ALIGN), + + MAKE_DBG_STR (\nS3LateRestore , CFG_S3_LATE_RESTORE) + MAKE_DBG_STR (\nAcpiPstateIndependent , CFG_ACPI_PSTATE_PSD_INDPX) + + MAKE_DBG_STR (\nApMtrrSettingsList , CFG_AP_MTRR_SETTINGS_LIST) + + MAKE_DBG_STR (\nProcessorScopeInSb , CFG_PROCESSOR_SCOPE_IN_SB) + MAKE_DBG_STR (\nProcessorScopeName0 , CFG_PROCESSOR_SCOPE_NAME0) + MAKE_DBG_STR (\nProcessorScopeName1 , CFG_PROCESSOR_SCOPE_NAME1) + MAKE_DBG_STR (\nGnbHdAudio , CFG_GNB_HD_AUDIO) + MAKE_DBG_STR (\nAbmSupport , CFG_ABM_SUPPORT) + MAKE_DBG_STR (\nDynamicRefreshRate , CFG_DYNAMIC_REFRESH_RATE) + MAKE_DBG_STR (\nLcdBackLightControl , CFG_LCD_BACK_LIGHT_CONTROL) + MAKE_DBG_STR (\nGnb3dStereoPinIndex , CFG_GNB_STEREO_3D_PINOUT) + MAKE_DBG_STR (\nTempPcieMmioBaseAddress, CFG_TEMP_PCIE_MMIO_BASE_ADDRESS), + MAKE_DBG_STR (\nCfgGnbIGPUSSID , CFG_GNB_IGPU_SSID) + MAKE_DBG_STR (\nCfgGnbHDAudioSSID , CFG_GNB_HDAUDIO_SSID) + MAKE_DBG_STR (\nCfgGnbPcieSSID , CFG_GNB_PCIE_SSID) + MAKE_DBG_STR (\nCfgIommuSupport , CFG_IOMMU_SUPPORT) + MAKE_DBG_STR (\nCfgLvdsSpreadSpectrum , CFG_GFX_LVDS_SPREAD_SPECTRUM) + MAKE_DBG_STR (\nCfgLvdsSpreadSpectrumRate , CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE) + MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDigonToDe , CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE) + MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDeToVaryBl , CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL) + MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDeToDigon , CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON) + MAKE_DBG_STR (\nCfgLvdsPowerOnSeqVaryBlToDe , CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE) + MAKE_DBG_STR (\nCfgLvdsPowerOnSeqOnToOffDelay , CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY) + MAKE_DBG_STR (\nCfgLvdsPowerOnSeqVaryBlToBlon , CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON) + MAKE_DBG_STR (\nCfgLvdsPowerOnSeqBlonToVaryBl , CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL) + MAKE_DBG_STR (\nCfgLvdsMaxPixelClockFreq , CFG_LVDS_MAX_PIXEL_CLOCK_FREQ) + MAKE_DBG_STR (\nCfgLcdBitDepthControlValue , CFG_LCD_BIT_DEPTH_CONTROL_VALUE) + MAKE_DBG_STR (\nCfgLvds24bbpPanelMode , CFG_LVDS_24BBP_PANEL_MODE), + MAKE_DBG_STR (\nCfgLvdsMiscControl.FpdiMode , CFG_LVDS_MISC_888_FPDI_MODE), + MAKE_DBG_STR (\nCfgLvdsMiscControl.DlChSwap , CFG_LVDS_MISC_DL_CH_SWAP), + MAKE_DBG_STR (\nCfgLvdsMiscControl.VsyncActiveLow , CFG_LVDS_MISC_VSYNC_ACTIVE_LOW), + MAKE_DBG_STR (\nCfgLvdsMiscControl.HsyncActiveLow , CFG_LVDS_MISC_HSYNC_ACTIVE_LOW), + MAKE_DBG_STR (\nCfgLvdsMiscControl.BLONActiveLow , CFG_LVDS_MISC_BLON_ACTIVE_LOW), + MAKE_DBG_STR (\nCfgPcieRefClkSpreadSpectrum , CFG_PCIE_REFCLK_SPREAD_SPECTRUM), + MAKE_DBG_STR (\nCfgExtVref , CFG_ENABLE_EXTERNAL_VREF), + MAKE_DBG_STR (\nCfgForceTrainMode , CFG_FORCE_TRAIN_MODE), + MAKE_DBG_STR (\nCfgGnbRemoteDisplaySupport , CFG_GNB_REMOTE_DISPLAY_CONFIG), + MAKE_DBG_STR (\nCfgIvrsExclusionRangeList , CFG_IOMMU_EXCLUSION_RANGE_LIST), + MAKE_DBG_STR (\nCfgGnbSyncFloodPinAsNmi , CFG_GNB_SYNCFLOOD_PIN_AS_NMI), + MAKE_DBG_STR (\nCfgIgpuEnableDisablePolicy , CFG_IGPU_ENABLE_DISABLE_POLICY), + MAKE_DBG_STR (\nCfgGnbSwTjOffset , CFG_GNB_THERMAL_SENSOR_CORRECTION), + MAKE_DBG_STR (\nCfgDisplayMiscControl.VbiosFastBootEn , CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE), + #endif + NULL + }; + #endif + #endif +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Include/PlatformMemoryConfiguration.h b/src/vendorcode/amd/agesa/f15tn/Include/PlatformMemoryConfiguration.h new file mode 100644 index 0000000..c583ebe --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/PlatformMemoryConfiguration.h @@ -0,0 +1,529 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Platform Specific Memory Configuration + * + * Contains Definitions and Macros for control of AGESA Memory code on a per platform basis + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: OPTION + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _PLATFORM_MEMORY_CONFIGURATION_H_ +#define _PLATFORM_MEMORY_CONFIGURATION_H_ + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ +#ifndef PSO_ENTRY + #define PSO_ENTRY UINT8 +#endif + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *---------------------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------------------- + * PLATFORM SPECIFIC MEMORY DEFINITIONS + *---------------------------------------------------------------------------------------- + */ +/// +/// Memory Speed and DIMM Population Masks +/// +///< DDR Speed Masks +///< Specifies the DDR Speed on a memory channel +/// +#define ANY_SPEED 0xFFFFFFFFul +#define DDR400 ((UINT32) 1 << (DDR400_FREQUENCY / 66)) +#define DDR533 ((UINT32) 1 << (DDR533_FREQUENCY / 66)) +#define DDR667 ((UINT32) 1 << (DDR667_FREQUENCY / 66)) +#define DDR800 ((UINT32) 1 << (DDR800_FREQUENCY / 66)) +#define DDR1066 ((UINT32) 1 << (DDR1066_FREQUENCY / 66)) +#define DDR1333 ((UINT32) 1 << (DDR1333_FREQUENCY / 66)) +#define DDR1600 ((UINT32) 1 << (DDR1600_FREQUENCY / 66)) +#define DDR1866 ((UINT32) 1 << (DDR1866_FREQUENCY / 66)) +#define DDR2133 ((UINT32) 1 << (DDR2133_FREQUENCY / 66)) +#define DDR2400 ((UINT32) 1 << (DDR2400_FREQUENCY / 66)) +/// +///< DIMM POPULATION MASKS +///< Specifies the DIMM Population on a channel (can be added together to specify configuration). +///< ex. SR_DIMM0 + SR_DIMM1 : Single Rank Dimm in slot 0 AND Slot 1 +///< SR_DIMM0 + DR_DIMM0 + SR_DIMM1 +DR_DIMM1 : Single OR Dual rank in Slot 0 AND Single OR Dual rank in Slot 1 +/// +#define ANY_ 0xFF ///< Any dimm configuration the current channel +#define SR_DIMM0 0x0001 ///< Single rank dimm in slot 0 on the current channel +#define SR_DIMM1 0x0010 ///< Single rank dimm in slot 1 on the current channel +#define SR_DIMM2 0x0100 ///< Single rank dimm in slot 2 on the current channel +#define SR_DIMM3 0x1000 ///< Single rank dimm in slot 3 on the current channel +#define DR_DIMM0 0x0002 ///< Dual rank dimm in slot 0 on the current channel +#define DR_DIMM1 0x0020 ///< Dual rank dimm in slot 1 on the current channel +#define DR_DIMM2 0x0200 ///< Dual rank dimm in slot 2 on the current channel +#define DR_DIMM3 0x2000 ///< Dual rank dimm in slot 3 on the current channel +#define QR_DIMM0 0x0004 ///< Quad rank dimm in slot 0 on the current channel +#define QR_DIMM1 0x0040 ///< Quad rank dimm in slot 1 on the current channel +#define QR_DIMM2 0x0400 ///< Quad rank dimm in slot 2 on the current channel +#define QR_DIMM3 0x4000 ///< Quad rank dimm in slot 3 on the current channel +#define LR_DIMM0 0x0001 ///< Lrdimm in slot 0 on the current channel +#define LR_DIMM1 0x0010 ///< Lrdimm in slot 1 on the current channel +#define LR_DIMM2 0x0100 ///< Lrdimm in slot 2 on the current channel +#define LR_DIMM3 0x1000 ///< Lrdimm in slot 3 on the current channel +#define ANY_DIMM0 0x000F ///< Any Dimm combination in slot 0 on the current channel +#define ANY_DIMM1 0x00F0 ///< Any Dimm combination in slot 1 on the current channel +#define ANY_DIMM2 0x0F00 ///< Any Dimm combination in slot 2 on the current channel +#define ANY_DIMM3 0xF000 ///< Any Dimm combination in slot 3 on the current channel +/// +///< CS POPULATION MASKS +///< Specifies the CS Population on a channel (can be added together to specify configuration). +///< ex. CS0 + CS1 : CS0 and CS1 apply to the setting +/// +#define CS_ANY_ 0xFF ///< Any CS configuration +#define CS0_ 0x01 ///< CS0 bit map mask +#define CS1_ 0x02 ///< CS1 bit map mask +#define CS2_ 0x04 ///< CS2 bit map mask +#define CS3_ 0x08 ///< CS3 bit map mask +#define CS4_ 0x10 ///< CS4 bit map mask +#define CS5_ 0x20 ///< CS5 bit map mask +#define CS6_ 0x40 ///< CS6 bit map mask +#define CS7_ 0x80 ///< CS7 bit map mask +/// +///< Number of Dimms on the current channel +///< This is a mask used to indicate the number of dimms in a channel +///< They can be added to indicate multiple conditions (i.e 1 OR 2 Dimms) +/// +#define ANY_NUM 0xFF ///< Any number of Dimms +#define NO_DIMM 0x00 ///< No Dimms present +#define ONE_DIMM 0x01 ///< One dimm Poulated on the current channel +#define TWO_DIMM 0x02 ///< Two dimms Poulated on the current channel +#define THREE_DIMM 0x04 ///< Three dimms Poulated on the current channel +#define FOUR_DIMM 0x08 ///< Four dimms Poulated on the current channel + +/// +///< DIMM VOLTAGE MASKS +/// +#define VOLT_ANY_ 0xFF ///< Any voltage configuration +#define VOLT1_5_ 0x01 ///< Voltage 1.5V bit map mask +#define VOLT1_35_ 0x02 ///< Voltage 1.35V bit map mask +#define VOLT1_25_ 0x04 ///< Voltage 1.25V bit map mask + +// +// < Not applicable +// +#define NA_ 0 ///< Not applicable + +/*---------------------------------------------------------------------------------------- + * + * Platform Specific Override Definitions for Socket, Channel and Dimm + * This indicates where a platform override will be applied. + * + *---------------------------------------------------------------------------------------- + */ +/// +///< SOCKET MASKS +///< Indicates associated processor sockets to apply override settings +/// +#define ANY_SOCKET 0xFF ///< Apply to all sockets +#define SOCKET0 0x01 ///< Apply to socket 0 +#define SOCKET1 0x02 ///< Apply to socket 1 +#define SOCKET2 0x04 ///< Apply to socket 2 +#define SOCKET3 0x08 ///< Apply to socket 3 +#define SOCKET4 0x10 ///< Apply to socket 4 +#define SOCKET5 0x20 ///< Apply to socket 5 +#define SOCKET6 0x40 ///< Apply to socket 6 +#define SOCKET7 0x80 ///< Apply to socket 7 +/// +///< CHANNEL MASKS +///< Indicates Memory channels where override should be applied +/// +#define ANY_CHANNEL 0xFF ///< Apply to all Memory channels +#define CHANNEL_A 0x01 ///< Apply to Channel A +#define CHANNEL_B 0x02 ///< Apply to Channel B +#define CHANNEL_C 0x04 ///< Apply to Channel C +#define CHANNEL_D 0x08 ///< Apply to Channel D +/// +/// DIMM MASKS +/// Indicates Dimm Slots where override should be applied +/// +#define ALL_DIMMS 0xFF ///< Apply to all dimm slots +#define DIMM0 0x01 ///< Apply to Dimm Slot 0 +#define DIMM1 0x02 ///< Apply to Dimm Slot 1 +#define DIMM2 0x04 ///< Apply to Dimm Slot 2 +#define DIMM3 0x08 ///< Apply to Dimm Slot 3 +/// +/// REGISTER ACCESS MASKS +/// Not supported as an at this time +/// +#define ACCESS_NB0 0x0 +#define ACCESS_NB1 0x1 +#define ACCESS_NB2 0x2 +#define ACCESS_NB3 0x3 +#define ACCESS_NB4 0x4 +#define ACCESS_PHY 0x5 +#define ACCESS_DCT_XT 0x6 +/*---------------------------------------------------------------------------------------- + * + * Platform Specific Overriding Table Definitions + * + *---------------------------------------------------------------------------------------- + */ + +#define PSO_END 0 ///< Table End +#define PSO_CKE_TRI 1 ///< CKE Tristate Map +#define PSO_ODT_TRI 2 ///< ODT Tristate Map +#define PSO_CS_TRI 3 ///< CS Tristate Map +#define PSO_MAX_DIMMS 4 ///< Max Dimms per channel +#define PSO_CLK_SPEED 5 ///< Clock Speed +#define PSO_DIMM_TYPE 6 ///< Dimm Type +#define PSO_MEMCLK_DIS 7 ///< MEMCLK Disable Map +#define PSO_MAX_CHNLS 8 ///< Max Channels per Socket +#define PSO_BUS_SPEED 9 ///< Max Memory Bus Speed +#define PSO_MAX_CHIPSELS 10 ///< Max Chipsel per Channel +#define PSO_MEM_TECH 11 ///< Channel Memory Type +#define PSO_WL_SEED 12 ///< DDR3 Write Levelization Seed delay +#define PSO_RXEN_SEED 13 ///< Hardwared based RxEn seed +#define PSO_NO_LRDIMM_CS67_ROUTING 14 ///< CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs +#define PSO_SOLDERED_DOWN_SODIMM_TYPE 15 ///< Soldered down SODIMM type +#define PSO_LVDIMM_VOLT1_5_SUPPORT 16 ///< Force LvDimm voltage to 1.5V +#define PSO_MIN_RD_WR_DATAEYE_WIDTH 17 ///< Min RD/WR dataeye width +#define PSO_CPU_FAMILY_TO_OVERRIDE 18 ///< CPU family signature to tell following PSO macros are CPU family dependent +#define PSO_MAX_SOLDERED_DOWN_DIMMS 19 ///< Max Soldered-down Dimms per channel +#define PSO_MEMORY_POWER_POLICY 20 ///< Memory power policy override + +/*---------------------------------- + * CONDITIONAL PSO SPECIFIC ENTRIES + *---------------------------------*/ +// Condition Types +#define CONDITIONAL_PSO_MIN 100 ///< Start of Conditional Entry Types +#define PSO_CONDITION_AND 100 ///< And Block - Start of Conditional block +#define PSO_CONDITION_LOC 101 ///< Location - Specify Socket, Channel, Dimms to be affected +#define PSO_CONDITION_SPD 102 ///< SPD - Specify a specific SPD value on a Dimm on the channel +#define PSO_CONDITION_REG 103 // Reserved +#define PSO_CONDITION_MAX 103 ///< End Of Condition Entry Types +// Action Types +#define PSO_ACTION_MIN 120 ///< Start of Action Entry Types +#define PSO_ACTION_ODT 120 ///< ODT values to override +#define PSO_ACTION_ADDRTMG 121 ///< Address/Timing values to override +#define PSO_ACTION_ODCCONTROL 122 ///< ODC Control values to override +#define PSO_ACTION_SLEWRATE 123 ///< Slew Rate value to override +#define PSO_ACTION_REG 124 // Reserved +#define PSO_ACTION_SPEEDLIMIT 125 ///< Memory Bus speed Limit based on configuration +#define PSO_ACTION_MAX 125 ///< End of Action Entry Types +#define CONDITIONAL_PSO_MAX 139 ///< End of Conditional Entry Types + +/*---------------------------------- + * TABLE DRIVEN PSO SPECIFIC ENTRIES + *---------------------------------*/ +// Condition descriptor +#define PSO_TBLDRV_CONFIG 200 ///< Configuration Descriptor + +// Overriding entry types +#define PSO_TBLDRV_START 210 ///< Start of Table Driven Overriding Entry Types +#define PSO_TBLDRV_SPEEDLIMIT 210 ///< Speed Limit +#define PSO_TBLDRV_ODT_RTTNOM 211 ///< RttNom +#define PSO_TBLDRV_ODT_RTTWR 212 ///< RttWr +#define PSO_TBLDRV_ODTPATTERN 213 ///< Odt Patterns +#define PSO_TBLDRV_ADDRTMG 214 ///< Address/Timing values +#define PSO_TBLDRV_ODCCTRL 215 ///< ODC Control values +#define PSO_TBLDRV_SLOWACCMODE 216 ///< Slow Access Mode +#define PSO_TBLDRV_MR0_CL 217 ///< MR0[CL] +#define PSO_TBLDRV_MR0_WR 218 ///< MR0[WR] +#define PSO_TBLDRV_RC2_IBT 219 ///< RC2[IBT] +#define PSO_TBLDRV_RC10_OPSPEED 220 ///< RC10[Opearting Speed] +#define PSO_TBLDRV_LRDIMM_IBT 221 ///< LrDIMM IBT +#define PSO_TBLDRV_INVALID_TYPE 223 ///< Invalid Type +#define PSO_TBLDRV_END 223 ///< End of Table Driven Overriding Entry Types + +/*---------------------------------------------------------------------------------------- + * CONDITIONAL OVERRIDE TABLE MACROS + *---------------------------------------------------------------------------------------- + */ +#define CPU_FAMILY_TO_OVERRIDE(CpuFamilyRevision) \ + PSO_CPU_FAMILY_TO_OVERRIDE, 4, \ + ((CpuFamilyRevision) & 0x0FF), (((CpuFamilyRevision) >> 8)& 0x0FF), (((CpuFamilyRevision) >> 16)& 0x0FF), (((CpuFamilyRevision) >> 24)& 0x0FF) + +#define MEMCLK_DIS_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \ + PSO_MEMCLK_DIS, 11, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map \ + , Bit7Map + +#define CKE_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map) \ + PSO_CKE_TRI, 5, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map + +#define ODT_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \ + PSO_ODT_TRI, 7, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map + +#define CS_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \ + PSO_CS_TRI, 11, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map + +#define NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) \ + PSO_MAX_DIMMS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfDimmSlotsPerChannel + +#define NUMBER_OF_SOLDERED_DOWN_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfSolderedDownDimmsPerChannel) \ + PSO_MAX_SOLDERED_DOWN_DIMMS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfSolderedDownDimmsPerChannel + +#define NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) \ + PSO_MAX_CHIPSELS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfChipSelectsPerChannel + +#define NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) \ + PSO_MAX_CHNLS, 4, SocketID, ANY_CHANNEL, ALL_DIMMS, NumberOfChannelsPerSocket + +#define OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, TimingMode, BusSpeed) \ + PSO_BUS_SPEED, 11, SocketID, ChannelID, ALL_DIMMS, TimingMode, (TimingMode >> 8), (TimingMode >> 16), (TimingMode >> 24), \ + BusSpeed, (BusSpeed >> 8), (BusSpeed >> 16), (BusSpeed >> 24) + +#define DRAM_TECHNOLOGY(SocketID, MemTechType) \ + PSO_MEM_TECH, 7, SocketID, ANY_CHANNEL, ALL_DIMMS, MemTechType, (MemTechType >> 8), (MemTechType >> 16), (MemTechType >> 24) + +#define WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \ + Byte6Seed, Byte7Seed, ByteEccSeed) \ + PSO_WL_SEED, 12, SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \ + Byte6Seed, Byte7Seed, ByteEccSeed + +#define HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \ + Byte6Seed, Byte7Seed, ByteEccSeed) \ + PSO_RXEN_SEED, 21, SocketID, ChannelID, DimmID, Byte0Seed, (Byte0Seed >> 8), Byte1Seed, (Byte1Seed >> 8), Byte2Seed, (Byte2Seed >> 8), \ + Byte3Seed, (Byte3Seed >> 8), Byte4Seed, (Byte4Seed >> 8), Byte5Seed, (Byte5Seed >> 8), Byte6Seed, (Byte6Seed >> 8), \ + Byte7Seed, (Byte7Seed >> 8), ByteEccSeed, (ByteEccSeed >> 8) + +#define NO_LRDIMM_CS67_ROUTING(SocketID, ChannelID) \ + PSO_NO_LRDIMM_CS67_ROUTING, 4, SocketID, ChannelID, ALL_DIMMS, TRUE + +#define SOLDERED_DOWN_SODIMM_TYPE(SocketID, ChannelID) \ + PSO_SOLDERED_DOWN_SODIMM_TYPE, 4, SocketID, ChannelID, ALL_DIMMS, TRUE + +#define LVDIMM_FORCE_VOLT1_5_FOR_D0 \ + PSO_LVDIMM_VOLT1_5_SUPPORT, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, TRUE + +#define MIN_RD_WR_DATAEYE_WIDTH(SocketID, ChannelID, MinRdDataeyeWidth, MinWrDataeyeWidth) \ + PSO_MIN_RD_WR_DATAEYE_WIDTH, 5, SocketID, ChannelID, ALL_DIMMS, MinRdDataeyeWidth, MinWrDataeyeWidth + +#define MEMORY_POWER_POLICY_OVERRIDE(PowerPolicy) \ + PSO_MEMORY_POWER_POLICY, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, PowerPolicy + +/*---------------------------------------------------------------------------------------- + * CONDITIONAL OVERRIDE TABLE MACROS + *---------------------------------------------------------------------------------------- + */ +#define CONDITION_AND \ + PSO_CONDITION_AND, 0 + +#define COND_LOC(SocketMsk, ChannelMsk, DimmMsk) \ + PSO_CONDITION_LOC, 3, SocketMsk, ChannelMsk, DimmMsk + +#define COND_SPD(Byte, Mask, Value) \ + PSO_CONDITION_SPD, 3, Byte, Mask, Value + +#define COND_REG(Access, Offset, Mask, Value) \ + PSO_CONDITION_REG, 11, Access, (Offset & 0x0FF), (Offset >> 8), \ + ((Mask) & 0x0FF), (((Mask) >> 8) & 0x0FF), (((Mask) >> 16) & 0x0FF), (((Mask) >> 24) & 0x0FF), \ + ((Value) & 0x0FF), (((Value) >> 8) & 0x0FF), (((Value) >> 16) & 0x0FF), (((Value) >> 24) & 0x0FF) + +#define ACTION_ODT(Frequency, Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt) \ + PSO_ACTION_ODT, 9, \ + ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), ((Frequency >> 24)& 0x0FF), \ + Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt + +#define ACTION_ADDRTMG(Frequency, DimmConfig, AddrTmg) \ + PSO_ACTION_ADDRTMG, 10, \ + ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ + ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \ + (AddrTmg & 0x0FF), ((AddrTmg >> 8)& 0x0FF), ((AddrTmg >> 16)& 0x0FF), ((AddrTmg >> 24)& 0x0FF) + +#define ACTION_ODCCTRL(Frequency, DimmConfig, OdcCtrl) \ + PSO_ACTION_ODCCONTROL, 10, \ + ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ + ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \ + (OdcCtrl & 0x0FF), ((OdcCtrl >> 8)& 0x0FF), ((OdcCtrl >> 16)& 0x0FF), ((OdcCtrl >> 24)& 0x0FF) + +#define ACTION_SLEWRATE(Frequency, DimmConfig, SlewRate) \ + PSO_ACTION_SLEWRATE, 10, \ + ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ + ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \ + (SlewRate & 0x0FF), ((SlewRate >> 8)& 0x0FF), ((SlewRate >> 16)& 0x0FF), ((SlewRate >> 24)& 0x0FF) + +#define ACTION_SPEEDLIMIT(DimmConfig, Dimms, SpeedLimit15, SpeedLimit135, SpeedLimit125) \ + PSO_ACTION_SPEEDLIMIT, 9, \ + ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), Dimms, \ + (SpeedLimit15 & 0x0FF), ((SpeedLimit15 >> 8)& 0x0FF), \ + (SpeedLimit135 & 0x0FF), ((SpeedLimit135 >> 8)& 0x0FF), \ + (SpeedLimit125 & 0x0FF), ((SpeedLimit125 >> 8)& 0x0FF) + +/*---------------------------------------------------------------------------------------- + * END OF CONDITIONAL OVERRIDE TABLE MACROS + *---------------------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------------------- + * TABLE DRIVEN OVERRIDE MACROS + *---------------------------------------------------------------------------------------- + */ +/// Configuration sub-descriptors +typedef enum { + CONFIG_GENERAL, ///< CONFIG_GENERAL + CONFIG_SPEEDLIMIT, ///< CONFIG_SPEEDLIMIT + CONFIG_RC2IBT, ///< CONFIG_RC2IBT + CONFIG_DONT_CARE, ///< CONFIG_DONT_CARE +} Config_Type; + +// ==================== +// Configuration Macros +// ==================== +#define TBLDRV_CONFIG_TO_OVERRIDE(DimmPerCH, Frequency, DimmVolt, DimmConfig) \ + PSO_TBLDRV_CONFIG, 9, \ + CONFIG_GENERAL, \ + DimmPerCH, DimmVolt, \ + ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ + ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF) + +#define TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE(DimmPerCH, Dimms, NumOfSR, NumOfDR, NumOfQR, NumOfLRDimm) \ + PSO_TBLDRV_CONFIG, 7, \ + CONFIG_SPEEDLIMIT, \ + DimmPerCH, Dimms, NumOfSR, NumOfDR, NumOfQR, NumOfLRDimm + +#define TBLDRV_RC2IBT_CONFIG_TO_OVERRIDE(DimmPerCH, Frequency, DimmVolt, DimmConfig, NumOfReg) \ + PSO_TBLDRV_CONFIG, 10, \ + CONFIG_RC2IBT, \ + DimmPerCH, DimmVolt, \ + ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ + ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \ + NumOfReg + +//================== +// Overriding Macros +//================== +#define TBLDRV_CONFIG_ENTRY_SPEEDLIMIT(SpeedLimit1_5, SpeedLimit1_35, SpeedLimit1_25) \ + PSO_TBLDRV_SPEEDLIMIT, 6, \ + (SpeedLimit1_5 & 0x0FF), ((SpeedLimit1_5 >> 8)& 0x0FF), \ + (SpeedLimit1_35 & 0x0FF), ((SpeedLimit1_35 >> 8)& 0x0FF), \ + (SpeedLimit1_25 & 0x0FF), ((SpeedLimit1_25 >> 8)& 0x0FF) + +#define TBLDRV_CONFIG_ENTRY_ODT_RTTNOM(TgtCS, RttNom) \ + PSO_TBLDRV_ODT_RTTNOM, 2, \ + TgtCS, RttNom + +#define TBLDRV_CONFIG_ENTRY_ODT_RTTWR(TgtCS, RttWr) \ + PSO_TBLDRV_ODT_RTTWR, 2, \ + TgtCS, RttWr + +#define TBLDRV_CONFIG_ENTRY_ODTPATTERN(RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow) \ + PSO_TBLDRV_ODTPATTERN, 16, \ + ((RdODTCSHigh) & 0x0FF), (((RdODTCSHigh) >> 8)& 0x0FF), (((RdODTCSHigh) >> 16)& 0x0FF), (((RdODTCSHigh) >> 24)& 0x0FF), \ + ((RdODTCSLow) & 0x0FF), (((RdODTCSLow) >> 8)& 0x0FF), (((RdODTCSLow) >> 16)& 0x0FF), (((RdODTCSLow) >> 24)& 0x0FF), \ + ((WrODTCSHigh) & 0x0FF), (((WrODTCSHigh) >> 8)& 0x0FF), (((WrODTCSHigh) >> 16)& 0x0FF), (((WrODTCSHigh) >> 24)& 0x0FF), \ + ((WrODTCSLow) & 0x0FF), (((WrODTCSLow) >> 8)& 0x0FF), (((WrODTCSLow) >> 16)& 0x0FF), (((WrODTCSLow) >> 24)& 0x0FF) + +#define TBLDRV_CONFIG_ENTRY_ADDRTMG(AddrTmg) \ + PSO_TBLDRV_ADDRTMG, 4, \ + ((AddrTmg) & 0x0FF), (((AddrTmg) >> 8)& 0x0FF), (((AddrTmg) >> 16)& 0x0FF), (((AddrTmg) >> 24)& 0x0FF) + +#define TBLDRV_CONFIG_ENTRY_ODCCTRL(OdcCtrl) \ + PSO_TBLDRV_ODCCTRL, 4, \ + ((OdcCtrl) & 0x0FF), (((OdcCtrl) >> 8)& 0x0FF), (((OdcCtrl) >> 16)& 0x0FF), (((OdcCtrl) >> 24)& 0x0FF) + +#define TBLDRV_CONFIG_ENTRY_SLOWACCMODE(SlowAccMode) \ + PSO_TBLDRV_SLOWACCMODE, 1, \ + SlowAccMode + +#define TBLDRV_CONFIG_ENTRY_RC2_IBT(TgtDimm, IBT) \ + PSO_TBLDRV_RC2_IBT, 2, \ + TgtDimm, IBT + +#define TBLDRV_OVERRIDE_MR0_CL(RegValOfTcl, MR0CL13, MR0CL0) \ + PSO_TBLDRV_CONFIG, 1, \ + CONFIG_DONT_CARE, \ + PSO_TBLDRV_MR0_CL, 3, \ + RegValOfTcl, MR0CL13, MR0CL0 + +#define TBLDRV_OVERRIDE_MR0_WR(RegValOfTwr, MR0WR) \ + PSO_TBLDRV_CONFIG, 1, \ + CONFIG_DONT_CARE, \ + PSO_TBLDRV_MR0_WR, 2, \ + RegValOfTwr, MR0WR + +#define TBLDRV_OVERRIDE_RC10_OPSPEED(Frequency, MR10OPSPEED) \ + PSO_TBLDRV_CONFIG, 1, \ + CONFIG_DONT_CARE, \ + PSO_TBLDRV_RC10_OPSPEED, 5, \ + ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ + MR10OPSPEED + +#define TBLDRV_CONFIG_ENTRY_LRDMM_IBT(F0RC8, F1RC0, F1RC1, F1RC2) \ + PSO_TBLDRV_LRDIMM_IBT, 4, \ + F0RC8, F1RC0, F1RC1, F1RC2 + + +//============================ +// Macros for removing entries +//============================ +#define INVALID_CONFIG_FLAG 0x8000 + +#define TBLDRV_INVALID_CONFIG \ + PSO_TBLDRV_INVALID_TYPE, 0 + +/*---------------------------------------------------------------------------------------- + * END OF TABLE DRIVEN OVERRIDE MACROS + *---------------------------------------------------------------------------------------- + */ + +#endif // _PLATFORM_MEMORY_CONFIGURATION_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/Topology.h b/src/vendorcode/amd/agesa/f15tn/Include/Topology.h new file mode 100644 index 0000000..582abd4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/Topology.h @@ -0,0 +1,189 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Topology interface definitions. + * + * Contains AMD AGESA internal interface for topology related data which + * is consumed by code other than HyperTransport init (and produced by + * HyperTransport init.) + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _TOPOLOGY_H_ +#define _TOPOLOGY_H_ + +// Defines for limiting data structure maximum allocation and limit checking. +#define MAX_NODES 8 +#define MAX_SOCKETS MAX_NODES +#define MAX_DIES 2 + +// Defines useful with package link +#define HT_LIST_MATCH_INTERNAL_LINK_0 0xFA +#define HT_LIST_MATCH_INTERNAL_LINK_1 0xFB +#define HT_LIST_MATCH_INTERNAL_LINK_2 0xFC + +/** + * Hop Count Table. + * This is a heap data structure. The Hops array is filled as a size x size matrix. + * The unused space, if any, is all at the end. + */ +typedef struct { + UINT8 Size; ///< The row and column size of actual hop count data */ + UINT8 Hops[MAX_NODES * MAX_NODES]; ///< Room for a dynamic two dimensional array of [size][size] */ +} HOP_COUNT_TABLE; + +/** + * Socket and Module to Node Map Item. + * Provide the Node Id and core id range for each module in each processor. + */ +typedef struct { + UINT8 Node; ///< The module's Node id. + UINT8 LowCore; ///< The lowest processor core id for this module. + UINT8 HighCore; ///< The highest processor core id for this module. + UINT8 EnabledComputeUnits; ///< The value of Enabled for this processor module. + UINT8 DualCoreComputeUnits; ///< The value of DualCore for this processor module. +} SOCKET_DIE_TO_NODE_ITEM; + +/** + * Socket and Module to Node Map. + * This type is a pointer to the actual map, it can be used for a struct item or + * for typecasting a heap buffer pointer. + */ +typedef SOCKET_DIE_TO_NODE_ITEM (*SOCKET_DIE_TO_NODE_MAP)[MAX_SOCKETS][MAX_DIES]; + +/** + * Node id to Socket Die Map Item. + */ +typedef struct { + UINT8 Socket; ///< socket of the processor containing the Node. + UINT8 Die; ///< the module in the processor which is Node. +} NODE_TO_SOCKET_DIE_ITEM; + +/** + * Node id to Socket Die Map. + */ +typedef NODE_TO_SOCKET_DIE_ITEM (*NODE_TO_SOCKET_DIE_MAP)[MAX_NODES]; + +/** + * Provide AP core with socket and node context at start up. + * This information is posted to the AP cores using a register as a mailbox. + */ +typedef struct { + UINT32 Node:4; ///< The node id of Core's node. + UINT32 Socket:4; ///< The socket of this Core's node. + UINT32 Module:2; ///< The internal module number for Core's node. + UINT32 ModuleType:2; ///< Single Module = 0, Multi-module = 1. + UINT32 :20; ///< Reserved +} AP_MAIL_INFO_FIELDS; + +/** + * AP info fields can be written and read to a register. + */ +typedef union { + UINT32 Info; ///< Just a number for register access, or opaque passing. + AP_MAIL_INFO_FIELDS Fields; ///< access to the info fields. +} AP_MAIL_INFO; + +/** + * Provide AP core with system degree and system core number at start up. + * This information is posted to the AP cores using a register as a mailbox. + */ +typedef struct { + UINT32 SystemDegree:3; ///< The number of connected links + UINT32 :3; ///< Reserved + UINT32 HeapIndex:6; ///< The zero-based system core number + UINT32 :20; ///< Reserved +} AP_MAIL_EXT_INFO_FIELDS; + +/** + * AP info fields can be written and read to a register. + */ +typedef union { + UINT32 Info; ///< Just a number for register access, or opaque passing. + AP_MAIL_EXT_INFO_FIELDS Fields; ///< access to the info fields. +} AP_MAIL_EXT_INFO; + +/** + * AP Info mailbox set. + */ +typedef struct { + AP_MAIL_INFO ApMailInfo; ///< The AP mail info + AP_MAIL_EXT_INFO ApMailExtInfo; ///< The extended AP mail info +} AP_MAILBOXES; + +/** + * Provide a northbridge to package mapping for link assignments. + * + */ +typedef struct { + UINT8 Link; ///< The Node's link + UINT8 Module; ///< The internal module position of Node + UINT8 PackageLink; ///< The corresponding package link +} PACKAGE_HTLINK_MAP_ITEM; + +/** + * A Processor's complete set of link assignments + */ +typedef PACKAGE_HTLINK_MAP_ITEM (*PACKAGE_HTLINK_MAP)[]; + +#endif // _TOPOLOGY_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Include/VirgoInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/VirgoInstall.h new file mode 100644 index 0000000..eeb9dd3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/VirgoInstall.h @@ -0,0 +1,171 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build options for a Virgo platform solution + * + * This file generates the defaults tables for the "Virgo" platform solution + * set of processors. The documented build options are imported from a user + * controlled file for processing. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e $Revision: 65876 $ @e $Date: 2012-02-26 21:30:10 -0600 (Sun, 26 Feb 2012) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "CommonReturns.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterface.h" + +/***************************************************************************** + * Define the RELEASE VERSION string + * + * The Release Version string should identify the next planned release. + * When a branch is made in preparation for a release, the release manager + * should change/confirm that the branch version of this file contains the + * string matching the desired version for the release. The trunk version of + * the file should always contain a trailing 'X'. This will make sure that a + * development build from trunk will not be confused for a released version. + * The release manager will need to remove the trailing 'X' and update the + * version string as appropriate for the release. The trunk copy of this file + * should also be updated/incremented for the next expected version, + trailing 'X' + ****************************************************************************/ + // This is the delivery package title, "TrinyPI " + // This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'T', 'r', 'i', 'n', 'y', 'P', 'I', ' '} + + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '2', ' ', ' ', ' ', ' '} + + +// The Virgo solution is defined to be family 0x15 models 0x10 - 0x1F in the FM2 socket. +#define INSTALL_FM2_SOCKET_SUPPORT TRUE +#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE + + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) + + +#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 +#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 +#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 +#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 +#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 +#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 +#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 +#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x420 +#define DFLT_SPI_BASE_ADDRESS 0xFEC10000ul +#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0ul +#define DFLT_HPET_BASE_ADDRESS 0xFED00000ul +#define DFLT_SMI_CMD_PORT 0xB0 +#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 +#define DFLT_GEC_BASE_ADDRESS 0xFED61000ul +#define DFLT_SMBUS_SSID 0x780B1022ul +#define DFLT_IDE_SSID 0x780C1022ul +#define DFLT_SATA_AHCI_SSID 0x78011022ul +#define DFLT_SATA_IDE_SSID 0x78001022ul +#define DFLT_SATA_RAID5_SSID 0x78031022ul +#define DFLT_SATA_RAID_SSID 0x78021022ul +#define DFLT_EHCI_SSID 0x78081022ul +#define DFLT_OHCI_SSID 0x78071022ul +#define DFLT_LPC_SSID 0x780E1022ul +#define DFLT_SD_SSID 0x78061022ul +#define DFLT_XHCI_SSID 0x78121022ul +#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE +#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +#define DFLT_FCH_GPP_LINK_CONFIG PortA4 +#define DFLT_FCH_GPP_PORT0_PRESENT FALSE +#define DFLT_FCH_GPP_PORT1_PRESENT FALSE +#define DFLT_FCH_GPP_PORT2_PRESENT FALSE +#define DFLT_FCH_GPP_PORT3_PRESENT FALSE +#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE + +#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT + #error BLDCFG: BLDCFG_VRM_INRUSH_CURRENT_LIMIT is deprecated. Use BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT instead. +#endif + +#ifdef BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT + #error BLDCFG: BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT is deprecated. Use BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT instead. +#endif + +// Instantiate all solution relevant data. +#include "PlatformInstall.h" + diff --git a/src/vendorcode/amd/agesa/f15tn/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/f15tn/Include/gcc-intrin.h new file mode 100644 index 0000000..ea80746 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Include/gcc-intrin.h @@ -0,0 +1,624 @@ +/* + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if defined (__GNUC__) + +/* I/O intrin functions. */ +static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned short Port) +{ + unsigned char value; + + __asm__ __volatile__ ( + "in %%dx, %%al" + : "=a" (value) + : "d" (Port) + ); + + return value; +} + +static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigned short Port) +{ + unsigned short value; + + __asm__ __volatile__ ( + "in %%dx, %%ax" + : "=a" (value) + : "d" (Port) + ); + + return value; +} + +static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigned short Port) +{ + unsigned long value; + + __asm__ __volatile__ ( + "in %%dx, %%eax" + : "=a" (value) + : "d" (Port) + ); + return value; + +} + +static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short Port,unsigned char Data) +{ + __asm__ __volatile__ ( + "out %%al, %%dx" + : + : "a" (Data), "d" (Port) + ); +} + +static __inline__ __attribute__((always_inline)) void __outword(unsigned short Port,unsigned short Data) +{ + __asm__ __volatile__ ( + "out %%ax, %%dx" + : + : "a" (Data), "d" (Port) + ); +} + +static __inline__ __attribute__((always_inline)) void __outdword(unsigned short Port,unsigned long Data) +{ + __asm__ __volatile__ ( + "out %%eax, %%dx" + : + : "a" (Data), "d" (Port) + ); +} + +static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count) +{ + __asm__ __volatile__ ( + "cld ; rep ; insb " + : "=D" (Buffer), "=c" (Count) + : "d"(Port), "0"(Buffer), "1" (Count) + ); +} + +static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count) +{ + __asm__ __volatile__ ( + "cld ; rep ; insw " + : "=D" (Buffer), "=c" (Count) + : "d"(Port), "0"(Buffer), "1" (Count) + ); +} + +static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count) +{ + __asm__ __volatile__ ( + "cld ; rep ; insl " + : "=D" (Buffer), "=c" (Count) + : "d"(Port), "0"(Buffer), "1" (Count) + ); +} + +static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count) +{ + __asm__ __volatile__ ( + "cld ; rep ; outsb " + : "=S" (Buffer), "=c" (Count) + : "d"(Port), "0"(Buffer), "1" (Count) + ); +} + +static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count) +{ + __asm__ __volatile__ ( + "cld ; rep ; outsw " + : "=S" (Buffer), "=c" (Count) + : "d"(Port), "0"(Buffer), "1" (Count) + ); +} + +static __inline__ __attribute__((always_inline)) void __outdwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count) +{ + __asm__ __volatile__ ( + "cld ; rep ; outsl " + : "=S" (Buffer), "=c" (Count) + : "d"(Port), "0"(Buffer), "1" (Count) + ); +} + +static __inline__ __attribute__((always_inline)) unsigned long __readdr0(void) +{ + unsigned long value; + __asm__ __volatile__ ( + "mov %%dr0, %[value]" + : [value] "=a" (value) + ); + return value; +} + +static __inline__ __attribute__((always_inline)) unsigned long __readdr1(void) +{ + unsigned long value; + __asm__ __volatile__ ( + "mov %%dr1, %[value]" + : [value] "=a" (value) + ); + return value; +} + +static __inline__ __attribute__((always_inline)) unsigned long __readdr2(void) +{ + unsigned long value; + __asm__ __volatile__ ( + "mov %%dr2, %[value]" + : [value] "=a" (value) + ); + return value; +} + +static __inline__ __attribute__((always_inline)) unsigned long __readdr3(void) +{ + unsigned long value; + __asm__ __volatile__ ( + "mov %%dr3, %[value]" + : [value] "=a" (value) + ); + return value; +} + +static __inline__ __attribute__((always_inline)) unsigned long __readdr7(void) +{ + unsigned long value; + __asm__ __volatile__ ( + "mov %%dr7, %[value]" + : [value] "=a" (value) + ); + return value; +} + +static __inline__ __attribute__((always_inline)) unsigned long __readdr(unsigned long reg) +{ + switch (reg){ + case 0: + return __readdr0 (); + break; + + case 1: + return __readdr1 (); + break; + + case 2: + return __readdr2 (); + break; + + case 3: + return __readdr3 (); + break; + + case 7: + return __readdr7 (); + break; + + default: + return -1; + } +} + +static __inline__ __attribute__((always_inline)) void __writedr0(unsigned long Data) +{ + __asm__ __volatile__ ( + "mov %%eax, %%dr0" + : + : "a" (Data) + ); +} + +static __inline__ __attribute__((always_inline)) void __writedr1(unsigned long Data) +{ + __asm__ __volatile__ ( + "mov %%eax, %%dr1" + : + : "a" (Data) + ); +} + +static __inline__ __attribute__((always_inline)) void __writedr2(unsigned long Data) +{ + __asm__ __volatile__ ( + "mov %%eax, %%dr2" + : + : "a" (Data) + ); +} + +static __inline__ __attribute__((always_inline)) void __writedr3(unsigned long Data) +{ + __asm__ __volatile__ ( + "mov %%eax, %%dr3" + : + : "a" (Data) + ); +} + +static __inline__ __attribute__((always_inline)) void __writedr7(unsigned long Data) +{ + __asm__ __volatile__ ( + "mov %%eax, %%dr7" + : + : "a" (Data) + ); +} + +static __inline__ __attribute__((always_inline)) void __writedr(unsigned long reg, unsigned long Data) +{ + switch (reg){ + case 0: + __writedr0 (Data); + break; + + case 1: + __writedr1 (Data); + break; + + case 2: + __writedr2 (Data); + break; + + case 3: + __writedr3 (Data); + break; + + case 7: + __writedr7 (Data); + break; + + default: + ; + } +} + +static __inline__ __attribute__((always_inline)) unsigned long __readcr0(void) +{ + unsigned long value; + __asm__ __volatile__ ( + "mov %%cr0, %[value]" + : [value] "=a" (value)); + return value; +} + +static __inline__ __attribute__((always_inline)) unsigned long __readcr2(void) +{ + unsigned long value; + __asm__ __volatile__ ( + "mov %%cr2, %[value]" + : [value] "=a" (value)); + return value; +} + +static __inline__ __attribute__((always_inline)) unsigned long __readcr3(void) +{ + unsigned long value; + __asm__ __volatile__ ( + "mov %%cr3, %[value]" + : [value] "=a" (value)); + return value; +} + +static __inline__ __attribute__((always_inline)) unsigned long __readcr4(void) +{ + unsigned long value; + __asm__ __volatile__ ( + "mov %%cr4, %[value]" + : [value] "=a" (value)); + return value; +} + +static __inline__ __attribute__((always_inline)) unsigned long __readcr8(void) +{ + unsigned long value; + __asm__ __volatile__ ( + "mov %%cr8, %[value]" + : [value] "=a" (value)); + return value; +} + +static __inline__ __attribute__((always_inline)) unsigned long __readcr(unsigned long reg) +{ + switch (reg){ + case 0: + return __readcr0 (); + break; + + case 2: + return __readcr2 (); + break; + + case 3: + return __readcr3 (); + break; + + case 4: + return __readcr4 (); + break; + + case 8: + return __readcr8 (); + break; + + default: + return -1; + } +} + +static __inline__ __attribute__((always_inline)) void __writecr0(unsigned long Data) +{ + __asm__ __volatile__ ( + "mov %%eax, %%cr0" + : + : "a" (Data) + ); +} + +static __inline__ __attribute__((always_inline)) void __writecr2(unsigned long Data) +{ + __asm__ __volatile__ ( + "mov %%eax, %%cr2" + : + : "a" (Data) + ); +} + +static __inline__ __attribute__((always_inline)) void __writecr3(unsigned long Data) +{ + __asm__ __volatile__ ( + "mov %%eax, %%cr3" + : + : "a" (Data) + ); +} + +static __inline__ __attribute__((always_inline)) void __writecr4(unsigned long Data) +{ + __asm__ __volatile__ ( + "mov %%eax, %%cr4" + : + : "a" (Data) + ); +} + +static __inline__ __attribute__((always_inline)) void __writecr8(unsigned long Data) +{ + __asm__ __volatile__ ( + "mov %%eax, %%cr8" + : + : "a" (Data) + ); +} + +static __inline__ __attribute__((always_inline)) void __writecr(unsigned long reg, unsigned long Data) +{ + switch (reg){ + case 0: + __writecr0 (Data); + break; + + case 2: + __writecr2 (Data); + break; + + case 3: + __writecr3 (Data); + break; + + case 4: + __writecr4 (Data); + break; + + case 8: + __writecr8 (Data); + break; + + default: + ; + } +} + +static __inline__ __attribute__((always_inline)) UINT64 __readmsr(UINT32 msr) +{ + UINT64 retval; + __asm__ __volatile__( + "rdmsr\n\t" + : "=A" (retval) + : "c" (msr) + ); + return retval; +} + +static __inline__ __attribute__((always_inline)) void __writemsr (UINT32 msr, UINT64 Value) +{ + __asm__ __volatile__ ( + "wrmsr\n\t" + : + : "c" (msr), "A" (Value) + ); +} + +static __inline__ __attribute__((always_inline)) UINT64 __rdtsc(void) +{ + UINT64 retval; + __asm__ __volatile__ ( + "rdtsc" + : "=A" (retval)); + return retval; +} + +static __inline__ __attribute__((always_inline)) void __cpuid(int CPUInfo[], const int InfoType) +{ + __asm__ __volatile__( + "cpuid" + :"=a" (CPUInfo[0]), "=b" (CPUInfo[1]), "=c" (CPUInfo[2]), "=d" (CPUInfo[3]) + : "a" (InfoType) + ); +} + +static __inline__ __attribute__((always_inline)) void _disable(void) +{ + __asm__ __volatile__ ("cli"); +} + +static __inline__ __attribute__((always_inline)) void _enable(void) +{ + __asm__ __volatile__ ("sti"); +} + +static __inline__ __attribute__((always_inline)) void __halt(void) +{ + __asm__ __volatile__ ("hlt"); +} + +static __inline__ __attribute__((always_inline)) void __debugbreak(void) +{ + __asm__ __volatile__ ("int3"); +} + +static __inline__ __attribute__((always_inline)) void __wbinvd(void) +{ + __asm__ __volatile__ ("wbinvd"); +} + +static __inline__ __attribute__((always_inline)) void __lidt(void *Source) +{ + __asm__ __volatile__("lidt %0" : : "m"(*(short*)Source)); +} + +static __inline__ __attribute__((always_inline)) void __writefsbyte(const unsigned long Offset, const unsigned char Data) +{ + __asm__("movb %b[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data)); +} + +static __inline__ __attribute__((always_inline)) void __writefsword(const unsigned long Offset, const unsigned short Data) +{ + __asm__("movw %w[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data)); +} + +static __inline__ __attribute__((always_inline)) void __writefsdword(const unsigned long Offset, const unsigned long Data) +{ + __asm__("movl %k[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data)); +} + +static __inline__ __attribute__((always_inline)) unsigned char __readfsbyte(const unsigned long Offset) +{ + unsigned char value; + __asm__("movb %%fs:%a[Offset], %b[value]" : [value] "=q" (value) : [Offset] "irm" (Offset)); + return value; +} + +static __inline__ __attribute__((always_inline)) unsigned short __readfsword(const unsigned long Offset) +{ + unsigned short value; + __asm__("movw %%fs:%a[Offset], %w[value]" : [value] "=q" (value) : [Offset] "irm" (Offset)); + return value; +} + +static __inline__ __attribute__((always_inline)) unsigned long long __readfsdword(unsigned long long Offset) +{ + unsigned long long value; + __asm__("movl %%fs:%a[Offset], %k[value]" : [value] "=q" (value) : [Offset] "irm" (Offset)); + return value; +} + +#ifdef __SSE3__ +typedef long long __v2di __attribute__ ((__vector_size__ (16))); +typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); + +static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs2 (void *__A, __m128i __B) +{ + __asm__(".byte 0x64"); // fs prefix + __builtin_ia32_movntdq ((__v2di *)__A, (__v2di)__B); +} + +static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs (void *__A, void *__B) +{ + __m128i data; + data = (__m128i) __builtin_ia32_lddqu ((char const *)__B); + _mm_stream_si128_fs2 (__A, data); +} + +static __inline__ __attribute__((always_inline)) void _mm_clflush_fs (void *__A) +{ + __asm__(".byte 0x64"); // fs prefix + __builtin_ia32_clflush (__A); +} + +static __inline __attribute__(( __always_inline__)) void _mm_mfence (void) +{ + __builtin_ia32_mfence (); +} + +static __inline __attribute__(( __always_inline__)) void _mm_sfence (void) +{ + __builtin_ia32_sfence (); +} +#endif + +static __inline__ __attribute__((always_inline)) void __stosb(unsigned char *dest, unsigned char data, size_t count) +{ + __asm__ __volatile__ ( + "cld ; rep ; stosb " + : "=D" (dest), "=c" (count) + : "a"(data), "0"(dest), "1" (count) + ); +} + +static __inline__ __attribute__((always_inline)) void __movsb(unsigned char *dest, unsigned char *data, size_t count) +{ + __asm__ __volatile__ ( + "cld ; rep ; movsb " + : "=D" (dest), "=S"(data), "=c" (count) + : "S"(data), "0"(dest), "1" (count) + ); +} + +static __inline__ __attribute__((always_inline)) +void debug_point ( unsigned short Port, unsigned long Data ) +{ + __outdword (Port, Data); + __asm__ __volatile__ (".word 0xfeeb"); + +} + +static __inline__ __attribute__((always_inline)) +void delay_point ( unsigned short Port, unsigned long Data, unsigned long delayTime ) +{ + UINTN Index; + Index = 0; + __outdword (Port, Data); + while (Index < delayTime * 600000) { + __outdword (0xE0, 0); + Index ++; + } +} +#endif // defined (__GNUC__) diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/PlatformMemoryConfiguration.inc b/src/vendorcode/amd/agesa/f15tn/Legacy/PlatformMemoryConfiguration.inc new file mode 100644 index 0000000..30767b0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Legacy/PlatformMemoryConfiguration.inc @@ -0,0 +1,715 @@ +; **************************************************************************** +; * +; * @file +; * +; * AMD Platform Specific Memory Configuration +; * +; * Contains AMD AGESA Memory Configuration Override Interface +; * +; * @xrefitem bom "File Content Label" "Release Content" +; * @e project: AGESA +; * @e sub-project: Include +; * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ +; +; **************************************************************************** +; * +; * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; * +; * AMD is granting you permission to use this software (the Materials) +; * pursuant to the terms and conditions of your Software License Agreement +; * with AMD. This header does *NOT* give you permission to use the Materials +; * or any rights under AMD's intellectual property. Your use of any portion +; * of these Materials shall constitute your acceptance of those terms and +; * conditions. If you do not agree to the terms and conditions of the Software +; * License Agreement, please do not use any portion of these Materials. +; * +; * CONFIDENTIALITY: The Materials and all other information, identified as +; * confidential and provided to you by AMD shall be kept confidential in +; * accordance with the terms and conditions of the Software License Agreement. +; * +; * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; * +; * AMD does not assume any responsibility for any errors which may appear in +; * the Materials or any other related information provided to you by AMD, or +; * result from use of the Materials or any related information. +; * +; * You agree that you will not reverse engineer or decompile the Materials. +; * +; * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; * further information, software, technical information, know-how, or show-how +; * available to you. Additionally, AMD retains the right to modify the +; * Materials at any time, without notice, and is not obligated to provide such +; * modified Materials to you. +; * +; * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; * subject to the restrictions as set forth in FAR 52.227-14 and +; * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; * Government constitutes acknowledgement of AMD's proprietary rights in them. +; * +; * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; * direct product thereof will be exported directly or indirectly, into any +; * country prohibited by the United States Export Administration Act and the +; * regulations thereunder, without the required authorization from the U.S. +; * government nor will be used for any purpose prohibited by the same. +; * +; ************************************************************************** +IFNDEF PSO_ENTRY + PSO_ENTRY TEXTEQU <UINT8>; < Platform Configuration Table Entry +ENDIF +; ***************************************************************************************** +; * +; * PLATFORM SPECIFIC MEMORY DEFINITIONS +; * +; ***************************************************************************************** +; */ +; +; < Memory Speed and DIMM Population Masks +; +; < DDR Speed Masks +; +ANY_SPEED EQU 0FFFFFFFFh +DDR400 EQU ( 1 SHL (DDR400_FREQUENCY / 66)) +DDR533 EQU ( 1 SHL (DDR533_FREQUENCY / 66)) +DDR667 EQU ( 1 SHL (DDR667_FREQUENCY / 66)) +DDR800 EQU ( 1 SHL (DDR800_FREQUENCY / 66)) +DDR1066 EQU ( 1 SHL (DDR1066_FREQUENCY / 66)) +DDR1333 EQU ( 1 SHL (DDR1333_FREQUENCY / 66)) +DDR1600 EQU ( 1 SHL (DDR1600_FREQUENCY / 66)) +DDR1866 EQU ( 1 SHL (DDR1866_FREQUENCY / 66)) +DDR2133 EQU ( 1 SHL (DDR2133_FREQUENCY / 66)) +DDR2400 EQU ( 1 SHL (DDR2400_FREQUENCY / 66)) +; < +; < DIMM POPULATION MASKS +; +ANY_ EQU 0FFh +SR_DIMM0 EQU 0001h +SR_DIMM1 EQU 0010h +SR_DIMM2 EQU 0100h +SR_DIMM3 EQU 1000h +DR_DIMM0 EQU 0002h +DR_DIMM1 EQU 0020h +DR_DIMM2 EQU 0200h +DR_DIMM3 EQU 2000h +QR_DIMM0 EQU 0004h +QR_DIMM1 EQU 0040h +QR_DIMM2 EQU 0400h +QR_DIMM3 EQU 4000h +LR_DIMM0 EQU 0001h +LR_DIMM1 EQU 0010h +LR_DIMM2 EQU 0100h +LR_DIMM3 EQU 1000h +ANY_DIMM0 EQU 000Fh +ANY_DIMM1 EQU 00F0h +ANY_DIMM2 EQU 0F00h +ANY_DIMM3 EQU 0F000h +; < +; < CS POPULATION MASKS +; +CS_ANY_ EQU 0FFh +CS0_ EQU 01h +CS1_ EQU 02h +CS2_ EQU 04h +CS3_ EQU 08h +CS4_ EQU 10h +CS5_ EQU 20h +CS6_ EQU 40h +CS7_ EQU 80h +; +; Number of Dimms +; +ANY_NUM EQU 0FFh +NO_DIMM EQU 00h +ONE_DIMM EQU 01h +TWO_DIMM EQU 02h +THREE_DIMM EQU 04h +FOUR_DIMM EQU 08h +; +; DIMM VOLTAGE MASK +; +VOLT_ANY_ EQU 0FFh +VOLT1_5_ EQU 01h +VOLT1_35_ EQU 02h +VOLT1_25_ EQU 04h +; +; NOT APPLICIABLE +; +NA_ EQU 00h +; ***************************************************************************************** +; * +; * Platform Specific Override Definitions for Socket, Channel and Dimm +; * This indicates where a platform override will be applied. +; * +; ***************************************************************************************** +; +; SOCKET MASKS +; +ANY_SOCKET EQU 0FFh +SOCKET0 EQU 01h +SOCKET1 EQU 02h +SOCKET2 EQU 04h +SOCKET3 EQU 08h +SOCKET4 EQU 10h +SOCKET5 EQU 20h +SOCKET6 EQU 40h +SOCKET7 EQU 80h +; +; CHANNEL MASKS +; +ANY_CHANNEL EQU 0FFh +CHANNEL_A EQU 01h +CHANNEL_B EQU 02h +CHANNEL_C EQU 04h +CHANNEL_D EQU 08h +; +; DIMM MASKS +; +ALL_DIMMS EQU 0FFh +DIMM0 EQU 01h +DIMM1 EQU 02h +DIMM2 EQU 04h +DIMM3 EQU 08h +; +; REGISTER ACCESS MASKS +; +ACCESS_NB0 EQU 0h +ACCESS_NB1 EQU 01h +ACCESS_NB2 EQU 02h +ACCESS_NB3 EQU 03h +ACCESS_NB4 EQU 04h +ACCESS_PHY EQU 05h +ACCESS_DCT_XT EQU 06h +; ***************************************************************************************** +; * +; * Platform Specific Overriding Table Definitions +; * +; ***************************************************************************************** +PSO_END EQU 0 ; < Table End +PSO_CKE_TRI EQU 1 ; < CKE Tristate Map +PSO_ODT_TRI EQU 2 ; < ODT Tristate Map +PSO_CS_TRI EQU 3 ; < CS Tristate Map +PSO_MAX_DIMMS EQU 4 ; < Max Dimms per channel +PSO_CLK_SPEED EQU 5 ; < Clock Speed +PSO_DIMM_TYPE EQU 6 ; < Dimm Type +PSO_MEMCLK_DIS EQU 7 ; < MEMCLK Disable Map +PSO_MAX_CHNLS EQU 8 ; < Max Channels per Socket +PSO_BUS_SPEED EQU 9 ; < Max Memory Bus Speed +PSO_MAX_CHIPSELS EQU 10 ; < Max Chipsel per Channel +PSO_MEM_TECH EQU 11 ; < Channel Memory Type +PSO_WL_SEED EQU 12 ; < DDR3 Write Levelization Seed delay +PSO_RXEN_SEED EQU 13 ; < Hardwared based RxEn seed +PSO_NO_LRDIMM_CS67_ROUTING EQU 14 ; < CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs +PSO_SOLDERED_DOWN_SODIMM_TYPE EQU 15 ; < Soldered down SODIMM type +PSO_LVDIMM_VOLT1_5_SUPPORT EQU 16 ; < Force LvDimm voltage to 1.5V +PSO_MIN_RD_WR_DATAEYE_WIDTH EQU 17 ; < Min RD/WR dataeye width +PSO_CPU_FAMILY_TO_OVERRIDE EQU 18 ; < CPU family signature to tell following PSO macros are CPU family dependent +PSO_MAX_SOLDERED_DOWN_DIMMS EQU 19 ; < Max Soldered-down Dimms per channel +PSO_MEMORY_POWER_POLICY EQU 20 ; < Memory power policy override +; ********************************** +; * CONDITIONAL PSO SPECIFIC ENTRIES +; ********************************** +; Condition Types +CONDITIONAL_PSO_MIN EQU 100 ; < Start of Conditional Entry Types +PSO_CONDITION_AND EQU 100 ; < And Block - Start of Conditional block +PSO_CONDITION_LOC EQU 101 ; < Location - Specify Socket, Channel, Dimms to be affected +PSO_CONDITION_SPD EQU 102 ; < SPD - Specify a specific SPD value on a Dimm on the channel +PSO_CONDITION_REG EQU 103 ; Reserved +PSO_CONDITION_MAX EQU 103 ; < End Of Condition Entry Types +; Action Types +PSO_ACTION_MIN EQU 120 ; < Start of Action Entry Types +PSO_ACTION_ODT EQU 120 ; < ODT values to override +PSO_ACTION_ADDRTMG EQU 121 ; < Address/Timing values to override +PSO_ACTION_ODCCONTROL EQU 122 ; < ODC Control values to override +PSO_ACTION_SLEWRATE EQU 123 ; < Slew Rate value to override +PSO_ACTION_REG EQU 124 ; Reserved +PSO_ACTION_SPEEDLIMIT EQU 125 ; < Memory Bus speed Limit based on configuration +PSO_ACTION_MAX EQU 125 ; < End of Action Entry Types +CONDITIONAL_PSO_MAX EQU 139 ; < End of Conditional Entry Types +; ********************************** +; * TABLE DRIVEN PSO SPECIFIC ENTRIES +; ********************************** +; Condition descriptor +PSO_TBLDRV_CONFIG EQU 200 ; < Configuration Descriptor + +; Overriding entry types +PSO_TBLDRV_START EQU 210 ; < Start of Table Driven Overriding Entry Types +PSO_TBLDRV_SPEEDLIMIT EQU 210 ; < Speed Limit +PSO_TBLDRV_ODT_RTTNOM EQU 211 ; < RttNom +PSO_TBLDRV_ODT_RTTWR EQU 212 ; < RttWr +PSO_TBLDRV_ODTPATTERN EQU 213 ; < Odt Patterns +PSO_TBLDRV_ADDRTMG EQU 214 ; < Address/Timing values +PSO_TBLDRV_ODCCTRL EQU 215 ; < ODC Control values +PSO_TBLDRV_SLOWACCMODE EQU 216 ; < Slow Access Mode +PSO_TBLDRV_MR0_CL EQU 217 ; < MR0[CL] +PSO_TBLDRV_MR0_WR EQU 218 ; < MR0[WR] +PSO_TBLDRV_RC2_IBT EQU 219 ; < RC2[IBT] +PSO_TBLDRV_RC10_OPSPEED EQU 220 ; < RC10[Opearting Speed] +PSO_TBLDRV_LRDIMM_IBT EQU 221 ; < LrDIMM IBT +;del PSO_TBLDRV_2D_TRAINING EQU 222 ; < 2D training +PSO_TBLDRV_INVALID_TYPE EQU 223 ; < Invalid Type +PSO_TBLDRV_END EQU 223 ; < End of Table Driven Overriding Entry Types + + +; ***************************************************************************************** +; * +; * CONDITIONAL OVERRIDE TABLE MACROS +; * +; ***************************************************************************************** +CPU_FAMILY_TO_OVERRIDE MACRO CpuFamilyRevision:REQ + DB PSO_CPU_FAMILY_TO_OVERRIDE + DB 4 + DD CpuFamilyRevision +ENDM + +MEMCLK_DIS_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ + DB PSO_MEMCLK_DIS + DB 11 + DB SocketID + DB ChannelID + DB ALL_DIMMS + DB Bit0Map + DB Bit1Map + DB Bit2Map + DB Bit3Map + DB Bit4Map + DB Bit5Map + DB Bit6Map + DB Bit7Map +ENDM + +CKE_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ + DB PSO_CKE_TRI + DB 5 + DB SocketID + DB ChannelID + DB ALL_DIMMS + DB Bit0Map + DB Bit1Map +ENDM + +ODT_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ + DB PSO_ODT_TRI + DB 7 + DB SocketID + DB ChannelID + DB ALL_DIMMS + DB Bit0Map + DB Bit1Map + DB Bit2Map + DB Bit3Map +ENDM + +CS_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ + DB PSO_CS_TRI + DB 11 + DB SocketID + DB ChannelID + DB ALL_DIMMS + DB Bit0Map + DB Bit1Map + DB Bit2Map + DB Bit3Map + DB Bit4Map + DB Bit5Map + DB Bit6Map + DB Bit7Map +ENDM + +NUMBER_OF_DIMMS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfDimmSlotsPerChannel:REQ + DB PSO_MAX_DIMMS + DB 4 + DB SocketID + DB ChannelID + DB ALL_DIMMS + DB NumberOfDimmSlotsPerChannel +ENDM + +NUMBER_OF_SOLDERED_DOWN_DIMMS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfSolderedDownDimmsPerChannel:REQ + DB PSO_MAX_SOLDERED_DOWN_DIMMS + DB 4 + DB SocketID + DB ChannelID + DB ALL_DIMMS + DB NumberOfSolderedDownDimmsPerChannel +ENDM + +NUMBER_OF_CHIP_SELECTS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfChipSelectsPerChannel:REQ + DB PSO_MAX_CHIPSELS + DB 4 + DB SocketID + DB ChannelID + DB ALL_DIMMS + DB NumberOfChipSelectsPerChannel +ENDM + +NUMBER_OF_CHANNELS_SUPPORTED MACRO SocketID:REQ, NumberOfChannelsPerSocket:REQ + DB PSO_MAX_CHNLS + DB 4 + DB SocketID + DB ANY_CHANNEL + DB ALL_DIMMS + DB NumberOfChannelsPerSocket +ENDM + +OVERRIDE_DDR_BUS_SPEED MACRO SocketID:REQ, ChannelID:REQ, TimingMode:REQ, BusSpeed:REQ + PSO_BUS_SPEED + DB 11 + DB SocketID + DB ChannelID + DB ALL_DIMMS + DD TimingMode + DD BusSpeed +ENDM + +DRAM_TECHNOLOGY MACRO SocketID:REQ, MemTechType:REQ + DB PSO_MEM_TECH + DB 7 + DB SocketID + DB ANY_CHANNEL + DB ALL_DIMMS + DD MemTechType +ENDM + +WRITE_LEVELING_SEED MACRO SocketID:REQ, ChannelID:REQ, DimmID:REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \ +Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ + DB PSO_WL_SEED + DB 12 + DB SocketID + DB ChannelID + DB DimmID + DB Byte0Seed + DB Byte1Seed + DB Byte2Seed + DB Byte3Seed + DB Byte4Seed + DB Byte5Seed + DB Byte6Seed + DB Byte7Seed + DB ByteEccSeed +ENDM + +HW_RXEN_SEED MACRO SocketID:REQ, ChannelID:REQ, DimmID: REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \ +Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ + DB PSO_RXEN_SEED + DB 21 + DB SocketID + DB ChannelID + DB DimmID + DW Byte0Seed + DW Byte1Seed + DW Byte2Seed + DW Byte3Seed + DW Byte4Seed + DW Byte5Seed + DW Byte6Seed + DW Byte7Seed + DW ByteEccSeed +ENDM + +NO_LRDIMM_CS67_ROUTING MACRO SocketID:REQ, ChannelID:REQ + DB PSO_NO_LRDIMM_CS67_ROUTING + DB 4 + DB SocketID + DB ChannelID + DB ALL_DIMMS + DB 1 +ENDM + +SOLDERED_DOWN_SODIMM_TYPE MACRO SocketID:REQ, ChannelID:REQ + DB PSO_SOLDERED_DOWN_SODIMM_TYPE + DB 4 + DB SocketID + DB ChannelID + DB ALL_DIMMS + DB 1 +ENDM + +LVDIMM_FORCE_VOLT1_5_FOR_D0 MACRO + DB PSO_LVDIMM_VOLT1_5_SUPPORT + DB 4 + DB ANY_SOCKET + DB ANY_CHANNEL + DB ALL_DIMMS + DB 1 +ENDM + +MIN_RD_WR_DATAEYE_WIDTH MACRO SocketID:REQ, ChannelID:REQ, MinRdDataeyeWidth:REQ, MinWrDataeyeWidth:REQ + DB PSO_MIN_RD_WR_DATAEYE_WIDTH + DB 5 + DB SocketID + DB ChannelID + DB ALL_DIMMS + DB MinRdDataeyeWidth + DB MinWrDataeyeWidth +ENDM + +MEMORY_POWER_POLICY_OVERRIDE MACRO PowerPolicy:REQ + DB PSO_MEMORY_POWER_POLICY + DB 4 + DB ANY_SOCKET + DB ANY_CHANNEL + DB ALL_DIMMS + DB PowerPolicy +ENDM +; ***************************************************************************************** +; * +; * CONDITIONAL OVERRIDE TABLE MACROS +; * +; ***************************************************************************************** +CONDITION_AND MACRO + DB PSO_CONDITION_AND + DB 0 +ENDM + +COND_LOC MACRO SocketMsk:REQ, ChannelMsk:REQ, DimmMsk:REQ + DB PSO_CONDITION_LOC + DB 3 + DB SocketMsk + DB ChannelMsk + DB DimmMsk +ENDM + +COND_SPD MACRO Byte:REQ, Mask:REQ, Value:REQ + DB PSO_CONDITION_SPD + DB 3 + DB Byte + DB Mask + DB Value +ENDM + +COND_REG MACRO Access:REQ, Offset:REQ, Mask:REQ, Value:REQ + DB PSO_CONDITION_REG + DB 11 + DB Access + DW Offset + DD Mask + DD Value +ENDM + +ACTION_ODT MACRO Frequency:REQ, Dimms:REQ, QrDimms:REQ, DramOdt:REQ, QrDramOdt:REQ, DramDynOdt:REQ + DB PSO_ACTION_ODT + DB 9 + DD Frequency + DB Dimms + DB QrDimms + DB DramOdt + DB QrDramOdt + DB DramDynOdt +ENDM + +ACTION_ADDRTMG MACRO Frequency:REQ, DimmConfig:REQ, AddrTmg:REQ + DB PSO_ACTION_ADDRTMG + DB 10 + DD Frequency + DW DimmConfig + DD AddrTmg +ENDM + +ACTION_ODCCTRL MACRO Frequency:REQ, DimmConfig:REQ, OdcCtrl:REQ + DB PSO_ACTION_ODCCONTROL + DB 10 + DD Frequency + DW DimmConfig + DD OdcCtrl +ENDM + +ACTION_SLEWRATE MACRO Frequency:REQ, DimmConfig:REQ, SlewRate:REQ + DB PSO_ACTION_SLEWRATE + DB 10 + DD Frequency + DW DimmConfig + DD SlewRate +ENDM + +ACTION_SPEEDLIMIT MACRO DimmConfig:REQ, Dimms:REQ, SpeedLimit15:REQ, SpeedLimit135:REQ, SpeedLimit125:REQ + DB PSO_ACTION_SPEEDLIMIT + DB 9 + DW DimmConfig + DB Dimms + DW SpeedLimit15 + DW SpeedLimit135 + DW SpeedLimit125 +ENDM + +; ***************************************************************************************** +; * +; * END OF CONDITIONAL OVERRIDE TABLE MACROS +; * +; ***************************************************************************************** +; ***************************************************************************************** +; * +; * TABLE DRIVEN OVERRIDE MACROS +; * +; ***************************************************************************************** +; Configuration sub-descriptors +CONFIG_GENERAL EQU 0 +CONFIG_SPEEDLIMIT EQU 1 +CONFIG_RC2IBT EQU 2 +CONFIG_DONT_CARE EQU 3 +Config_Type TEXTEQU <DWORD> +; +; Configuration Macros +; +TBLDRV_CONFIG_TO_OVERRIDE MACRO DimmPerCH:REQ, Frequency:REQ, DimmVolt:REQ, DimmConfig:REQ + DB PSO_TBLDRV_CONFIG + DB 9 + DB CONFIG_GENERAL + DB DimmPerCH + DB DimmVolt + DD Frequency + DW DimmConfig +ENDM + +TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE MACRO DimmPerCH:REQ, Dimms:REQ, NumOfSR:REQ, NumOfDR:REQ, NumOfQR:REQ, NumOfLRDimm:REQ + DB PSO_TBLDRV_CONFIG + DB 7 + DB CONFIG_SPEEDLIMIT + DB DimmPerCH + DB Dimms + DB NumOfSR + DB NumOfDR + DB NumOfQR + DB NumOfLRDimm +ENDM + +TBLDRV_RC2IBT_CONFIG_TO_OVERRIDE MACRO DimmPerCH:REQ, Frequency:REQ, DimmVolt:REQ, DimmConfig:REQ, NumOfReg:REQ + DB PSO_TBLDRV_CONFIG + DB 10 + DB CONFIG_RC2IBT + DB DimmPerCH + DB DimmVolt + DD Frequency + DW DimmConfig + DB NumOfReg +ENDM +; +; Overriding Macros +; +TBLDRV_CONFIG_ENTRY_SPEEDLIMIT MACRO SpeedLimit1_5:REQ, SpeedLimit1_35:REQ, SpeedLimit1_25:REQ + DB PSO_TBLDRV_SPEEDLIMIT + DB 6 + DW SpeedLimit1_5 + DW SpeedLimit1_35 + DW SpeedLimit1_25 +ENDM + +TBLDRV_CONFIG_ENTRY_ODT_RTTNOM MACRO TgtCS:REQ, RttNom:REQ + DB PSO_TBLDRV_ODT_RTTNOM + DB 2 + DB TgtCS + DB RttNom +ENDM + +TBLDRV_CONFIG_ENTRY_ODT_RTTWR MACRO TgtCS:REQ, RttWr:REQ + DB PSO_TBLDRV_ODT_RTTWR + DB 2 + DB TgtCS + DB RttWr +ENDM + +TBLDRV_CONFIG_ENTRY_ODTPATTERN MACRO RdODTCSHigh:REQ, RdODTCSLow:REQ, WrODTCSHigh:REQ, WrODTCSLow:REQ + DB PSO_TBLDRV_ODTPATTERN + DB 16 + DD RdODTCSHigh + DD RdODTCSLow + DD WrODTCSHigh + DD WrODTCSLow +ENDM + +TBLDRV_CONFIG_ENTRY_ADDRTMG MACRO AddrTmg:REQ + DB PSO_TBLDRV_ADDRTMG + DB 4 + DD AddrTmg +ENDM + +TBLDRV_CONFIG_ENTRY_ODCCTRL MACRO OdcCtrl:REQ + DB PSO_TBLDRV_ODCCTRL + DB 4 + DD OdcCtrl +ENDM + +TBLDRV_CONFIG_ENTRY_SLOWACCMODE MACRO SlowAccMode:REQ + DB PSO_TBLDRV_SLOWACCMODE + DB 1 + DB SlowAccMode +ENDM + +TBLDRV_CONFIG_ENTRY_RC2_IBT MACRO TgtDimm:REQ, IBT:REQ + DB PSO_TBLDRV_RC2_IBT + DB 2 + DB TgtDimm + DB IBT +ENDM + +TBLDRV_OVERRIDE_MR0_CL MACRO RegValOfTcl:REQ, MR0CL13:REQ, MR0CL0:REQ + DB PSO_TBLDRV_CONFIG + DB 1 + DB CONFIG_DONT_CARE + DB PSO_TBLDRV_MR0_CL + DB 3 + DB RegValOfTcl + DB MR0CL13 + DB MR0CL0 +ENDM + +TBLDRV_OVERRIDE_MR0_WR MACRO RegValOfTwr:REQ, MR0WR:REQ + DB PSO_TBLDRV_CONFIG + DB 1 + DB CONFIG_DONT_CARE + DB PSO_TBLDRV_MR0_WR + DB 2 + DB RegValOfTcl + DB MR0WR +ENDM + +TBLDRV_OVERRIDE_RC10_OPSPEED MACRO Frequency:REQ, MR10OPSPEED:REQ + DB PSO_TBLDRV_CONFIG + DB 1 + DB CONFIG_DONT_CARE + DB PSO_TBLDRV_RC10_OPSPEED + DB 5 + DD Frequency + DB MR10OPSPEED +ENDM + +TBLDRV_CONFIG_ENTRY_LRDMM_IBT MACRO F0RC8:REQ, F1RC0:REQ, F1RC1:REQ, F1RC2:REQ + DB PSO_TBLDRV_LRDIMM_IBT + DB 4 + DB F0RC8 + DB F1RC0 + DB F1RC1 + DB F1RC2 +ENDM + +;del TBLDRV_CONFIG_ENTRY_2D_TRAINING MACRO Training2dMode:REQ +;del DB PSO_TBLDRV_2D_TRAINING +;del DB 1 +;del DB Training2dMode +;del ENDM + +; +; Macros for removing entries +; +INVALID_CONFIG_FLAG EQU 8000h + +TBLDRV_INVALID_CONFIG MACRO + DB PSO_TBLDRV_INVALID_TYPE + DB 0 +ENDM +; ***************************************************************************************** +; * +; * END OF TABLE DRIVEN OVERRIDE MACROS +; * +; ***************************************************************************************** diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/Dispatcher.c b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/Dispatcher.c new file mode 100644 index 0000000..49f305b --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/Dispatcher.c @@ -0,0 +1,185 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD binary block interface + * + * Contains the block entry function dispatcher + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Legacy + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * *************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Dispatcher.h" +#include "Options.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE LEGACY_PROC_DISPATCHER_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern CONST DISPATCH_TABLE DispatchTable[]; +extern AMD_MODULE_HEADER mCpuModuleID; + +/*---------------------------------------------------------------------------------------*/ +/** + * The Dispatcher is the entry point into the AGESA software. It takes a function + * number as entry parameter in order to invoke the published function + * + * @param[in,out] ConfigPtr + * + * @return AGESA Status. + * + */ +AGESA_STATUS +CALLCONV +AmdAgesaDispatcher ( + IN OUT VOID *ConfigPtr + ) +{ + AGESA_STATUS Status; + IMAGE_ENTRY ImageEntry; + MODULE_ENTRY ModuleEntry; + DISPATCH_TABLE *Entry; + UINT32 ImageStart; + UINT32 ImageEnd; + AMD_IMAGE_HEADER* AltImagePtr; + + Status = AGESA_UNSUPPORTED; + ImageEntry = NULL; + ModuleEntry = NULL; + ImageStart = 0xFFF00000; + ImageEnd = 0xFFFFFFFF; + AltImagePtr = NULL; + + Entry = (DISPATCH_TABLE *) DispatchTable; + while (Entry->FunctionId != 0) { + if ((((AMD_CONFIG_PARAMS *) ConfigPtr)->Func) == Entry->FunctionId) { + Status = Entry->EntryPoint (ConfigPtr); + break; + } + Entry++; + } + + // 2. Try next dispatcher if possible, and we have not already got status back + if ((mCpuModuleID.NextBlock != NULL) && (Status == AGESA_UNSUPPORTED)) { + ModuleEntry = (MODULE_ENTRY) /* (UINT64) */ mCpuModuleID.NextBlock->ModuleDispatcher; + if (ModuleEntry != NULL) { + Status = (*ModuleEntry) (ConfigPtr); + } + } + + // 3. If not this image specific function, see if we can find alternative image instead + if (Status == AGESA_UNSUPPORTED) { + if ((((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr != 0xFFFFFFFF ) || (((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr != 0)) { + ImageStart = ((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr; + ImageEnd = ImageStart + 4; + // Locate/test image base that matches this component + AltImagePtr = LibAmdLocateImage ((VOID *) /* (UINT64) */ImageStart, (VOID *) /* (UINT64) */ImageEnd, 4096, (CHAR8 *) AGESA_ID); + if (AltImagePtr != NULL) { + //Invoke alternative Image + ImageEntry = (IMAGE_ENTRY) (/* (UINT64) */ AltImagePtr + AltImagePtr->EntryPointAddress); + Status = (*ImageEntry) (ConfigPtr); + } + } + } + + return (Status); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * The host environment interface of callout. + * + * @param[in] Func + * @param[in] Data + * @param[in,out] ConfigPtr + * + * @return The AGESA Status returned from the callout. + * + */ +AGESA_STATUS +CALLCONV +AmdAgesaCallout ( + IN UINT32 Func, + IN UINT32 Data, + IN OUT VOID *ConfigPtr + ) +{ + UINT32 Result; + Result = AGESA_UNSUPPORTED; + if (((AMD_CONFIG_PARAMS *) ConfigPtr)->CalloutPtr == NULL) { + return Result; + } + + Result = (((AMD_CONFIG_PARAMS *) ConfigPtr)->CalloutPtr) (Func, Data, ConfigPtr); + return (Result); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/agesaCallouts.c b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/agesaCallouts.c new file mode 100644 index 0000000..48f85a6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/agesaCallouts.c @@ -0,0 +1,487 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU AGESA Callout Functions + * + * Contains code to set / get useful platform information. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Common + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * AMD Generic Encapsulated Software Architecture + * + * Description: agesaCallouts.c - AGESA Call out functions + * + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "Dispatcher.h" +#include "cpuServices.h" +#include "Ids.h" +#include "Filecode.h" +#include "FchPlatform.h" +#define FILECODE LEGACY_PROC_AGESACALLOUTS_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S - (AGESA ONLY) + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------*/ +/** + * + * Call the host environment interface to do the warm or cold reset. + * + * @param[in] ResetType Warm or Cold Reset is requested + * @param[in,out] StdHeader Config header + * + */ +VOID +AgesaDoReset ( + IN UINTN ResetType, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + WARM_RESET_REQUEST Request; + + // Clear warm request bit and set state bits to the current post stage + GetWarmResetFlag (StdHeader, &Request); + Request.RequestBit = FALSE; + Request.StateBits = Request.PostStage; + SetWarmResetFlag (StdHeader, &Request); + + Status = AmdAgesaCallout (AGESA_DO_RESET, (UINT32)ResetType, (VOID *) StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * + * Call the host environment interface to allocate buffer in main system memory. + * + * @param[in] FcnData + * @param[in,out] AllocParams Heap manager parameters + * + * @return The AGESA Status returned from the callout. + * + */ +AGESA_STATUS +AgesaAllocateBuffer ( + IN UINTN FcnData, + IN OUT AGESA_BUFFER_PARAMS *AllocParams + ) +{ + AGESA_STATUS Status; + + Status = AmdAgesaCallout (AGESA_ALLOCATE_BUFFER, (UINT32)FcnData, (VOID *) AllocParams); + + return Status; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Call the host environment interface to deallocate buffer in main system memory. + * + * @param[in] FcnData + * @param[in,out] DeallocParams Heap Manager parameters + * + * @return The AGESA Status returned from the callout. + */ +AGESA_STATUS +AgesaDeallocateBuffer ( + IN UINTN FcnData, + IN OUT AGESA_BUFFER_PARAMS *DeallocParams + ) +{ + AGESA_STATUS Status; + + Status = AmdAgesaCallout (AGESA_DEALLOCATE_BUFFER, (UINT32)FcnData, (VOID *) DeallocParams); + + return Status; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * + * Call the host environment interface to Locate buffer Pointer in main system memory + * + * @param[in] FcnData + * @param[in,out] LocateParams Heap manager parameters + * + * @return The AGESA Status returned from the callout. + * + */ +AGESA_STATUS +AgesaLocateBuffer ( + IN UINTN FcnData, + IN OUT AGESA_BUFFER_PARAMS *LocateParams + ) +{ + AGESA_STATUS Status; + + Status = AmdAgesaCallout (AGESA_LOCATE_BUFFER, (UINT32)FcnData, (VOID *) LocateParams); + + return Status; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Call the host environment interface to launch APs + * + * @param[in] ApicIdOfCore + * @param[in,out] LaunchApParams + * + * @return The AGESA Status returned from the callout. + * + */ +AGESA_STATUS +AgesaRunFcnOnAp ( + IN UINTN ApicIdOfCore, + IN AP_EXE_PARAMS *LaunchApParams + ) +{ + AGESA_STATUS Status; + + Status = AmdAgesaCallout (AGESA_RUNFUNC_ONAP, (UINT32)ApicIdOfCore, (VOID *) LaunchApParams); + + return Status; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Call the host environment interface to read an SPD's content. + * + * @param[in] FcnData + * @param[in,out] ReadSpd + * + * @return The AGESA Status returned from the callout. + * + */ +AGESA_STATUS +AgesaReadSpd ( + IN UINTN FcnData, + IN OUT AGESA_READ_SPD_PARAMS *ReadSpd + ) +{ + AGESA_STATUS Status; + + Status = AmdAgesaCallout (AGESA_READ_SPD, (UINT32)FcnData, ReadSpd); + + return Status; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Call the host environment interface to read an SPD's content. + * + * @param[in] FcnData + * @param[in,out] ReadSpd + * + * @return The AGESA Status returned from the callout. + * + */ +AGESA_STATUS +AgesaReadSpdRecovery ( + IN UINTN FcnData, + IN OUT AGESA_READ_SPD_PARAMS *ReadSpd + ) +{ + AGESA_STATUS Status; + + Status = AmdAgesaCallout (AGESA_READ_SPD_RECOVERY, (UINT32)FcnData, ReadSpd); + + return Status; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Call the host environment interface to provide a user hook opportunity. + * + * @param[in] FcnData + * @param[in,out] MemData + * + * @return The AGESA Status returned from the callout. + * + */ +AGESA_STATUS +AgesaHookBeforeDramInitRecovery ( + IN UINTN FcnData, + IN OUT MEM_DATA_STRUCT *MemData + ) +{ + AGESA_STATUS Status; + + Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, (UINT32)FcnData, MemData); + + return Status; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Call the host environment interface to provide a user hook opportunity. + * + * @param[in] SocketIdModuleId - (SocketID << 8) | ModuleId + * @param[in,out] MemData + * + * @return The AGESA Status returned from the callout. + * + */ +AGESA_STATUS +AgesaHookBeforeDramInit ( + IN UINTN SocketIdModuleId, + IN OUT MEM_DATA_STRUCT *MemData + ) +{ + AGESA_STATUS Status; + + Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DRAM_INIT, (UINT32)SocketIdModuleId, MemData); + + return Status; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Call the host environment interface to provide a user hook opportunity. + * + * @param[in] SocketIdModuleId - (SocketID << 8) | ModuleId + * @param[in,out] MemData + * + * @return The AGESA Status returned from the callout. + * + */ +AGESA_STATUS +AgesaHookBeforeDQSTraining ( + IN UINTN SocketIdModuleId, + IN OUT MEM_DATA_STRUCT *MemData + ) +{ + AGESA_STATUS Status; + + Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DQS_TRAINING, (UINT32)SocketIdModuleId, MemData); + + return Status; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Call the host environment interface to provide a user hook opportunity. + * + * @param[in] FcnData + * @param[in,out] MemData + * + * @return The AGESA Status returned from the callout. + * + */ +AGESA_STATUS +AgesaHookBeforeExitSelfRefresh ( + IN UINTN FcnData, + IN OUT MEM_DATA_STRUCT *MemData + ) +{ + AGESA_STATUS Status; + + Status = AmdAgesaCallout (AGESA_HOOKBEFORE_EXIT_SELF_REF, (UINT32)FcnData, MemData); + + return Status; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Call the host environment interface to provide a user hook opportunity. + * + * @param[in] Data + * @param[in,out] IdsCalloutData + * + * @return The AGESA Status returned from the callout. + * + */ + + +AGESA_STATUS +AgesaGetIdsData ( + IN UINTN Data, + IN OUT IDS_CALLOUT_STRUCT *IdsCalloutData + ) +{ + AGESA_STATUS Status; + + Status = AmdAgesaCallout (AGESA_GET_IDS_INIT_DATA, (UINT32)Data, IdsCalloutData); + + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIE slot reset control + * + * + * + * @param[in] FcnData Function data + * @param[in] ResetInfo Reset information + * @retval Status Agesa status + */ + +AGESA_STATUS +AgesaPcieSlotResetControl ( + IN UINTN FcnData, + IN PCIe_SLOT_RESET_INFO *ResetInfo + ) +{ + AGESA_STATUS Status; + Status = AmdAgesaCallout (AGESA_GNB_PCIE_SLOT_RESET, (UINT32) FcnData, ResetInfo); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get VBIOS image + * + * + * + * @param[in] FcnData Function data + * @param[in] VbiosImageInfo VBIOS image info + * @retval Status Agesa status + */ + +AGESA_STATUS +AgesaGetVbiosImage ( + IN UINTN FcnData, + IN OUT GFX_VBIOS_IMAGE_INFO *VbiosImageInfo + ) +{ + AGESA_STATUS Status; + Status = AmdAgesaCallout (AGESA_GNB_GFX_GET_VBIOS_IMAGE, (UINT32) FcnData, VbiosImageInfo); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * OEM callout function for FCH data override + * + * + * @param[in] FchData FCH data pointer + * @retval Status This feature is not supported + */ + +AGESA_STATUS +AgesaFchOemCallout ( + IN VOID *FchData + ) +{ + AGESA_STATUS Status; Status = AmdAgesaCallout(AGESA_FCH_OEM_CALLOUT, (UINT32)FchData, ((FCH_DATA_BLOCK *)FchData)->StdHeader); return Status; //return AGESA_UNSUPPORTED; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * + * @param[in] SocketIdModuleId - (SocketID << 8) | ModuleId + * @param[in,out] MemData + * + * @return The AGESA Status returned from the callout. + * + */ +AGESA_STATUS +excel331 ( + IN UINTN SocketIdModuleId, + IN OUT MEM_DATA_STRUCT *MemData + ) +{ + AGESA_STATUS Status; + + Status = AmdAgesaCallout (0x00028146ul , (UINT32)SocketIdModuleId, MemData); + + return Status; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/arch2008.asm b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/arch2008.asm new file mode 100644 index 0000000..daa7c0a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/arch2008.asm @@ -0,0 +1,2702 @@ +;***************************************************************************** +; AMD Generic Encapsulated Software Architecture +; +; Workfile: arch2008.asm $Revision: 63425 $ $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ +; +; Description: ARCH2008.ASM - AGESA Architecture 2008 Wrapper Template +; +;***************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;***************************************************************************** + + .XLIST + INCLUDE agesa.inc + INCLUDE acwrapg.inc ; Necessary support file as part of wrapper, including but not limited to segment start/end macros. + INCLUDE acwrap.inc ; IBVs may specify host BIOS-specific include files required when building. + INCLUDE cpcarmac.inc + INCLUDE bridge32.inc + .LIST + .586p + .mmx + + +;---------------------------------------------------------------------------- +; Local definitions +;---------------------------------------------------------------------------- + +sOemCallout STRUCT + FuncName DD ? ; Call out function name + FuncPtr DW ? ; Call out function pointer +sOemCallout ENDS + +sOemEventHandler STRUCT + ClassCode DD ? ; AGESA event log sub-class code + FuncPtr DW ? ; Event handler function pointer +sOemEventHandler ENDS + +;; A typical legacy BIOS implementation may require the E000 and F000 segments +;; to be cached. +EXE_CACHE_REGION_BASE_0 EQU 0E0000h +EXE_CACHE_REGION_SIZE_0 EQU 20000h + +;; In this sample implementation, the B1 and B2 images are placed next to each +;; other in the BIOS ROM to help with the maximization of cached code. +EXE_CACHE_REGION_BASE_1 EQU AGESA_B1_ADDRESS +EXE_CACHE_REGION_SIZE_1 EQU 40000h + +;; The third region is not needed in our example. +EXE_CACHE_REGION_BASE_2 EQU 0 +EXE_CACHE_REGION_SIZE_2 EQU 0 + + +;---------------------------------------------------------------------------- +; PERSISTENT SEGMENT +; This segment is required to be present throughout all BIOS execution. +;---------------------------------------------------------------------------- + +AMD_PERSISTENT_START + + +;---------------------------------------------------------------------------- +; Instantiate the global descriptor table +;---------------------------------------------------------------------------- + +AMD_BRIDGE_32_GDT AMD_GDT ; Instantiate the global descriptor table + ; required by the push-high mechanism. + + +;---------------------------------------------------------------------------- +; Declare the external routines required in the persistent segment +;---------------------------------------------------------------------------- + +;+------------------------------------------------------------------------- +; +; AmdDfltRet +; +; Entry: +; None +; +; Exit: +; None +; +; Modified: +; None +; +; Purpose: +; Near stub procedure. Simply perform a retn instruction. +; +EXTERN AmdDfltRet:NEAR + + +;+------------------------------------------------------------------------- +; +; AmdDfltRetFar +; +; Entry: +; None +; +; Exit: +; None +; +; Modified: +; None +; +; Purpose: +; Far stub procedure. Simply perform a retf instruction. +; +EXTERN AmdDfltRetFar:FAR + + +;---------------------------------------------------------------------------- +; Declare the optional external routines in the persistent segment +;---------------------------------------------------------------------------- + +;+--------------------------------------------------------------------------- +; +; myModuleTypeMismatchHandler (Example) +; +; Entry: +; ESI - Pointer to the EVENT_PARAMS structure of the failure. +; [ESI].DataParam1 - Socket +; [ESI].DataParam2 - DCT +; [ESI].DataParam3 - Channel +; [ESI].DataParam4 - 0x00000000 +; +; Exit: +; None +; +; Modified: +; None +; +; Purpose: +; This procedure can be used to react to a memory module type +; mismatch error discovered by the AGESA code. Actions taken +; may include, but are not limited to: +; Logging the event to NV for display later +; Reset, excluding the mismatch on subsequent reboot +; Do nothing +; +; Dependencies: +; None +; +EXTERN myModuleTypeMismatchHandler(AmdDfltRet):NEAR + +;+--------------------------------------------------------------------------- +; +; oemPlatformConfigInit (Optional) +; +; Entry: +; EDI - 32-bit flat pointer to the PLATFORM_CONFIGURATION to be +; passed in to the next AGESA entry point. +; +; typedef struct { +; IN PERFORMANCE_PROFILE PlatformProfile; +; IN CPU_HT_DEEMPHASIS_LEVEL *PlatformDeemphasisList; +; IN UINT8 CoreLevelingMode; +; IN PLATFORM_C1E_MODES C1eMode; +; IN UINT32 C1ePlatformData; +; IN UINT32 C1ePlatformData1; +; IN UINT32 C1ePlatformData2; +; IN UINT32 C1ePlatformData3; +; IN BOOLEAN UserOptionDmi; +; IN BOOLEAN UserOptionPState; +; IN BOOLEAN UserOptionSrat; +; IN BOOLEAN UserOptionSlit; +; IN BOOLEAN UserOptionWhea; +; IN UINT32 PowerCeiling; +; IN BOOLEAN PstateIndependent; +; } PLATFORM_CONFIGURATION; +; +; typedef struct { +; IN UINT8 Socket; +; IN UINT8 Link; +; IN UINT8 LoFreq; +; IN UINT8 HighFreq; +; IN PLATFORM_DEEMPHASIS_LEVEL ReceiverDeemphasis; +; IN PLATFORM_DEEMPHASIS_LEVEL DcvDeemphasis; +; } CPU_HT_DEEMPHASIS_LEVEL; +; +; typedef struct { +; IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode; +; IN BOOLEAN UseHtAssist; +; IN BOOLEAN UseAtmMode; +; IN BOOLEAN Use32ByteRefresh; +; IN BOOLEAN UseVariableMctIsocPriority; +; } PERFORMANCE_PROFILE; +; +; Exit: +; None +; +; Modified: +; None +; +; Purpose: +; Provide a single hook routine to modify the parameters of a +; PLATFORM_CONFIGURATION structure before any entry point that +; has such a structure as an input. +; +; Dependencies: +; None +; +; Example: +; If your platform is running in UMA mode, the following code +; may be added: +; mov (PLATFORM_CONFIGURATION PTR [edi]).PlatformProfile.PlatformControlFlowMode, UmaDr +; +EXTERN oemPlatformConfigInit(AmdDfltRetFar):FAR + +;+--------------------------------------------------------------------------- +; +; oemCallout (Optional) +; +; Entry: +; ECX - Callout function number +; EDX - Function-specific UINTN +; ESI - Pointer to function specific data +; +; Exit: +; EAX - Contains the AGESA_STATUS return code. +; +; Modified: +; None +; +; Purpose: +; The default call out router function which resides in the same +; segment as the push-high bridge code. +; +; Dependencies: +; None +; +EXTERN oemCallout(AmdDfltRet):NEAR + + +;---------------------------------------------------------------------------- +; Define the sample wrapper routines for the persistent segment +;---------------------------------------------------------------------------- + +;+--------------------------------------------------------------------------- +; +; AmdBridge32 +; +; Entry: +; EDX - A Real Mode FAR pointer using seg16:Offset16 format that +; points to a local host environment call-out router. If +; this pointer is not equal to zero, then this pointer is +; used as the call-out router instead of the standard +; OemCallout. This may be useful when the call-out router +; is not located in the same segment as the AmdBridge32 and +; AmdCallout16 routines. +; ESI - A Flat Mode pointer (32-bit address) that points to the +; configuration block (AMD_CONFIG_PARAMS) for the AGESA +; software function. +; +; Exit: +; EAX - Contains the AGESA_STATUS return code. +; +; Modified: +; None +; +; Purpose: +; Execute an AGESA software function through the Push-High interface. +; +; Dependencies: +; This procedure requires a stack. The host environment must use the +; provided service function to establish the stack environment prior +; to making the call to this procedure. +; +AmdBridge32 PROC FAR PUBLIC + AMD_BRIDGE_32 AMD_GDT ; use the macro for the body + ret +AmdBridge32 ENDP + + +;+--------------------------------------------------------------------------- +; +; AmdEnableStack +; +; Entry: +; BX - Return address +; +; Exit: +; EAX - Contains the AGESA_STATUS return code. +; SS:ESP - Points to the private stack location for this processor core. +; ECX - Upon success, contains this processor core's stack size in bytes. +; +; Modified: +; EAX, ECX, EDX, EDI, ESI, ESP, DS, ES +; +; Purpose: +; This procedure is used to establish the stack within the host environment. +; +; Dependencies: +; The host environment must use this procedure and not rely on any other +; sources to create the stack region. +; +AmdEnableStack PROC NEAR PUBLIC + AMD_ENABLE_STACK + ;; EAX = AGESA_SUCCESS, The stack space has been allocated for this core. + ;; EAX = AGESA_WARNING, The stack has already been set up. SS:ESP is set + ;; to stack top, and ECX is the stack size in bytes. + jmp bx +AmdEnableStack ENDP + + +;+--------------------------------------------------------------------------- +; +; AmdDisableStack +; +; Entry: +; BX - Return address +; +; Exit: +; EAX - Contains the AGESA_STATUS return code. +; +; Modified: +; EAX, ECX, EDX, ESI, ESP +; +; Purpose: +; This procedure is used to remove the pre-memory stack from within the +; host environment. +; The exit state for the BSP is described as follows: +; Memory region 00000-9FFFF MTRRS are set as WB memory. +; Processor Cache is enabled (CD bit is cleared). +; MTRRs used for execution cache are kept. +; Cache content is flushed (invalidated without write-back). +; Any family-specific clean-up done. +; The exit state for the APs is described as follows: +; Memory region 00000-9FFFF MTRRS are set as WB memory. +; Memory region A0000-DFFFF MTRRS are set as UC IO. +; Memory region E0000-FFFFF MTRRS are set as UC memory. +; MTRRs used for execution cache are cleared. +; Processor Cache is disabled (CD bit is set). +; Top-of-Memory (TOM) set to the system top of memory as determined +; by the memory initialization routines. +; System lock command is enabled. +; Any family-specific clean-up done. +; +; Dependencies: +; The host environment must use this procedure and not rely on any other +; sources to break down the stack region. +; If executing in 16-bit code, the host environment must establish the +; "Big Real" mode of 32-bit addressing of data. +; +AmdDisableStack PROC NEAR PUBLIC + AMD_DISABLE_STACK + ;; EAX = AGESA_SUCCESS, The stack space has been disabled for this core. + jmp bx +AmdDisableStack ENDP + + +;+--------------------------------------------------------------------------- +; +; AmdCallout16 +; +; Entry: +; [esp+8] - Func +; [esp+12] - Data +; [esp+16] - Configuration Block +; [esp+4] - Return address to AGESA +; +; Exit: +; EAX - Contains the AGESA_STATUS return code. +; +; Modified: +; None +; +; Purpose: +; Execute callback from the push-high interface. +; +; Dependencies: +; None +; +AmdCallout16 PROC FAR PUBLIC ; declare the procedure + AMD_CALLOUT_16 oemCallout ; use the macro for the body + ret +AmdCallout16 ENDP + + +;+--------------------------------------------------------------------------- +; +; AmdProcessAgesaErrors (Optional) +; +; Entry: +; AL - Heap status of the AGESA entry point that was just invoked. +; EBX - AGESA image base address. +; EDX - Segment / Offset of the appropriate callout router function. +; +; Exit: +; None +; +; Modified: +; None +; +; Purpose: +; This procedure is used to handle any errors that may have occurred +; during an AGESA entry point. +; +; Dependencies: +; None +; +AmdProcessAgesaErrors PROC FAR PUBLIC + LOCAL localCpuInterfaceBlock:EVENT_PARAMS + + pushad + xor edi, edi + mov di, ss + shl edi, 4 + lea esi, localCpuInterfaceBlock + add esi, edi + + ; Fill default config block + mov (EVENT_PARAMS PTR [esi]).StdHeader.Func, AMD_READ_EVENT_LOG + mov (EVENT_PARAMS PTR [esi]).StdHeader.ImageBasePtr, ebx + mov (EVENT_PARAMS PTR [esi]).StdHeader.AltImageBasePtr, 0 + mov (EVENT_PARAMS PTR [esi]).StdHeader.HeapStatus, al + mov edi, SEG AmdCallout16 + shl edi, 4 + add edi, OFFSET AmdCallout16 + mov (EVENT_PARAMS PTR [esi]).StdHeader.CalloutPtr, edi + + ; Flush the event log searching for, and handling all monitored events + xor eax, eax + .while (eax == 0) + push edx + call AmdBridge32 + pop edx + .if (eax == AGESA_SUCCESS) + mov eax, (EVENT_PARAMS PTR [esi]).EventInfo + .if (eax != 0) + lea di, cs:AgesaEventTable + +loopThruTable: + cmp di, OFFSET cs:AgesaEventTableEnd + jae unhandledEvent + + cmp eax, cs:[di].sOemEventHandler.ClassCode + je FoundMatch + add di, SIZEOF sOemEventHandler + jmp loopThruTable + +FoundMatch: + mov bx, cs:[di].sOemEventHandler.FuncPtr + call bx + +unhandledEvent: + xor eax, eax + .else + mov al, 1 + .endif + .endif + .endw + popad + ret + +AmdProcessAgesaErrors ENDP + + +;---------------------------------------------------------------------------- +; Define the error handler table +;---------------------------------------------------------------------------- + +AgesaEventTable LABEL BYTE + ;; Add entries as desired + ;;--------- + ;; EXAMPLE + ;;--------- + sOemEventHandler <MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM, OFFSET myModuleTypeMismatchHandler> +AgesaEventTableEnd LABEL BYTE + + +AMD_PERSISTENT_END + + + + +;---------------------------------------------------------------------------- +; RECOVERY SEGMENT +; This segment resides in the classic 'boot-block,' and is used +; for recovery. +;---------------------------------------------------------------------------- + +AMD_RECOVERY_START + + +;---------------------------------------------------------------------------- +; Declare the external routines required in the recovery segment +;---------------------------------------------------------------------------- + +;+--------------------------------------------------------------------------- +; +; myReadSPDRecovery (Required for proper recovery mode operation) +; +; Entry: +; ESI - Pointer to an AGESA_READ_SPD_PARAMS structure. +; +; typedef struct { +; IN OUT AMD_CONFIG_PARAMS StdHeader; +; IN UINT8 SocketId; +; IN UINT8 MemChannelId; +; IN UINT8 DimmId; +; IN OUT UINT8 *Buffer; +; IN OUT MEM_DATA_STRUCT *MemData; +; } AGESA_READ_SPD_PARAMS; +; +; Exit: +; EAX - Contains the AGESA_STATUS return code. +; AGESA_SUCCESS Indicates the SPD block for the indicated +; DIMM was read successfully. +; AGESA_BOUNDS_CHK The specified DIMM is not present. +; AGESA_UNSUPPORTED This is a required function, so this +; value being returned causes a critical +; error response value from the AGESA +; software function and no memory initialized. +; AGESA_ERROR The DIMM SPD read process has generated +; communication errors. +; +; Modified: +; None +; +; Purpose: +; This call out reads a block of memory SPD data and places it +; into the provided buffer. +; +; Dependencies: +; None +; +EXTERN myReadSPDRecovery:NEAR + + +;---------------------------------------------------------------------------- +; Define the sample wrapper routines for the recovery segment +;---------------------------------------------------------------------------- + +;+--------------------------------------------------------------------------- +; +; AmdInitResetWrapper +; +; Entry: +; DS - 0000 with 4 gigabyte access +; ES - 0000 with 4 gigabyte access +; +; Exit: +; None +; +; Modified: +; None +; +; Purpose: +; A minimal initialization of the processor core is performed. This +; procedure must be called by all processor cores. The code path +; separates the BSP from the APs and performs a separate and appropriate +; list of tasks for each class of core. +; For the BSP, the following actions are performed: +; Internal heap sub-system initialization +; Primary non-coherent HyperTransportT link initialization +; Return to the host environment to test for Recovery Mode. +; The AP processor cores do not participate in the recovery process. +; However, they execute this routine after being released to execute +; by the BSP during the main boot process. Their actions include the +; following: +; Internal heap sub-system initialization +; Proceed to a wait loop waiting for commands from the BSP +; +; For the cache regions, up to three regions of execution cache can be +; allocated following the following rules: +; 1. Once a region is allocated, it cannot be de-allocated. However, it +; can be expanded. +; 2. At most, two of the three regions can be located above 1 MByte. A +; region failing this rule is ignored. +; 3. All region addresses must be at or above the 0x000D0000 linear +; address. A region failing this rule is ignored. +; 4. The address is aligned on a 32-KByte boundary. Starting addresses +; is rounded down to the nearest 32-Kbyte boundary. +; 5. The execution cache size must be a multiple of 32 KByte. Size is +; rounded up to the next multiple of 32 KByte. +; 6. A region must not span either the 1-MByte boundary or the 4-GByte +; boundary. Allocated size is truncated to not span the boundary. +; 7. The granted cached execution regions, address, and size are calculated +; based on the available cache resources of the processor core. +; Allocations are made up to the limit of cache available on the +; installed processor. +; Warning: Enabling instruction cache outside of this interface can cause +; data corruption. +; +; Dependencies: +; This procedure is expected to be executed soon after a system reset +; for the main boot path or resume path of execution. +; +; This procedure requires a stack. +; +; Because the heap system is not yet operational at the point of the +; interface call, the host environment must allocate the storage for +; the AMD_RESET_PARAMS structure before making the first call to +; AmdCreateStruct. This is the ByHost method of allocation. +; +AmdInitResetWrapper PROC NEAR PUBLIC + local localCfgBlock:AMD_INTERFACE_PARAMS + local localResetParams:AMD_RESET_PARAMS + + pushad + + ; Prepare for the call to initialize the input parameters for AmdInitReset + xor eax, eax + mov ax, ss + shl eax, 4 + lea esi, localCfgBlock + add esi, eax + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B1_ADDRESS + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0 + mov edx, SEG AmdCallout16 + shl edx, 4 + add edx, OFFSET AmdCallout16 + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx + + ; Use the 'ByHost' allocation method because the heap has not been initialized as of yet. + mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RESET + mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, ByHost + mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, sizeof AMD_RESET_PARAMS + lea edx, localResetParams + add edx, eax + push edx + mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr, edx + mov dx, SEG AmdCalloutRouterRecovery + shl edx, 16 + mov dx, OFFSET AmdCalloutRouterRecovery + push edx + call AmdBridge32 + pop edx + pop esi + + ; The structure has been initialized. Now modify the default settings as desired. + + ; Allocate the execution cache to maximize the amount of code in ROM that is cached. + ; Placing the B1 and B2 images near one another is a good way to ensure the AGESA code + ; is cached. + mov (AMD_RESET_PARAMS ptr [esi]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_0 + mov (AMD_RESET_PARAMS ptr [esi]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_0 + mov (AMD_RESET_PARAMS ptr [esi + sizeof EXECUTION_CACHE_REGION]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_1 + mov (AMD_RESET_PARAMS ptr [esi + sizeof EXECUTION_CACHE_REGION]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_1 + mov (AMD_RESET_PARAMS ptr [esi + (2 * sizeof EXECUTION_CACHE_REGION)]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_2 + mov (AMD_RESET_PARAMS ptr [esi + (2 * sizeof EXECUTION_CACHE_REGION)]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_2 + + ; Call in to the AmdInitReset entry point + push edx + call AmdBridge32 + pop edx + + ;; EAX = AGESA_STATUS + ;; AGESA_SUCCESS Early initialization completed successfully. + ;; AGESA_WARNING One or more of the execution cache allocation + ;; rules were violated, but an adjustment was made + ;; and space was allocated. + ;; AGESA_ERROR One or more of the execution cache allocation rules + ;; were violated, which resulted in a requested cache + ;; region to not be allocated. + ;; The storage space allocated for the AMD_RESET_PARAMS + ;; structure is insufficient. + + .if (eax != AGESA_SUCCESS) + mov al, (AMD_RESET_PARAMS ptr [esi]).StdHeader.HeapStatus + mov ebx, AGESA_B1_ADDRESS + call AmdProcessAgesaErrors + .endif + + + ;; Here are what the MTRRs should look like based off of the CacheRegions specified above: + + ;; Fixed-Range MTRRs + ;; Name Address Value + ;; ---------------- -------- ---------------- + ;; MTRRfix4k_E0000 0000026C 0505050505050505 + ;; MTRRfix4k_E8000 0000026D 0505050505050505 + ;; MTRRfix4k_F0000 0000026E 0505050505050505 + ;; MTRRfix4k_F8000 0000026F 0505050505050505 + ;; MTRRdefType 000002FF 0000000000000C00 + ;; + ;; Variable-Range MTRRs and IO Range + ;; MTRRphysBase(n) MTRRphysMask(n) + ;; ----------------- ----------------- + ;; n=0 0000000000000000 0000000000000000 + ;; n=1 0000000000000000 0000000000000000 + ;; n=2 0000000000000000 0000000000000000 + ;; n=3 0000000000000000 0000000000000000 + ;; n=4 0000000000000000 0000000000000000 + ;; n=5 Heap Base (Varies by core) 0000FFFFFFFF0800 + ;; n=6 AGESA_B1_ADDRESS | 6 0000FFFFFFFC0800 + ;; n=7 0000000000000000 0000000000000000 + + + ;; Because the allocation method is 'ByHost,' the call to AMD_RELEASE_STRUCT is + ;; not necessary. Stack space reclamation is left up to the host BIOS. + + popad + ret + + +AmdInitResetWrapper ENDP + + +;+--------------------------------------------------------------------------- +; +; AmdInitRecoveryWrapper +; +; Entry: +; DS - 0000 with 4 gigabyte access +; ES - 0000 with 4 gigabyte access +; +; Exit: +; None +; +; Modified: +; None +; +; Purpose: +; Perform a minimum initialization of the processor and memory to +; support a recovery mode flash ROM update. +; For the BSP, the following actions are performed: +; Configuration of CPU core for recovery process +; Minimal initialization of some memory +; The AP processor cores do not participate in the recovery process. +; No actions or tasks are performed by the AP cores for this time point. +; +; Dependencies: +; This procedure requires a stack. The host environment must use one of +; the provided service functions to establish the stack environment prior +; to making the call to this procedure. +; +AmdInitRecoveryWrapper PROC NEAR PUBLIC + local localCfgBlock:AMD_INTERFACE_PARAMS + + pushad + + ; Prepare for the call to create and initialize the input parameters for AmdInitRecovery + xor eax, eax + mov ax, ss + shl eax, 4 + lea esi, localCfgBlock + add esi, eax + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B1_ADDRESS + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0 + mov edx, SEG AmdCallout16 + shl edx, 4 + add edx, OFFSET AmdCallout16 + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx + + mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RECOVERY + mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap + mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0 + push esi + mov dx, SEG AmdCalloutRouterRecovery + shl edx, 16 + mov dx, OFFSET AmdCalloutRouterRecovery + push edx + call AmdBridge32 + pop edx + + mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr + + ; The structure has been initialized. Now modify the default settings as desired. + + + ; Call in to the AmdInitRecovery entry point + push edx + call AmdBridge32 + pop edx + + ;; EAX = AGESA_STATUS + ;; AGESA_SUCCESS The function has completed successfully. + ;; AGESA_WARNING One or more of the allocation rules were violated, + ;; but an adjustment was made and space was allocated. + ;; AGESA_ERROR One or more of the allocation rules were violated, + ;; which resulted in a requested cache region to not be + ;; allocated. + ;; AGESA_FATAL No memory was found in the system. + + .if (eax != AGESA_SUCCESS) + mov al, (AMD_RECOVERY_PARAMS ptr [esi]).StdHeader.HeapStatus + mov ebx, AGESA_B1_ADDRESS + call AmdProcessAgesaErrors + .endif + + ; Allow AGESA to free the space used by AmdInitRecovery + pop esi + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT + call AmdBridge32 + + popad + ret +AmdInitRecoveryWrapper ENDP + + +;+--------------------------------------------------------------------------- +; +; AmdCalloutRouterRecovery +; +; Entry: +; ECX - Callout function number +; EDX - Function-specific UINTN +; ESI - Pointer to function specific data +; +; Exit: +; EAX - Contains the AGESA_STATUS return code. +; +; Modified: +; None +; +; Purpose: +; The call out router function for AmdInitReset and +; AmdInitRecovery. +; +; Dependencies: +; None +; +AmdCalloutRouterRecovery PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES + xor ax, ax + mov ds, ax + mov es, ax + lea di, cs:CalloutRouterTableRecovery + mov eax, AGESA_UNSUPPORTED + +loopThruTable: + cmp di, OFFSET cs:CalloutRouterTableRecoveryEnd + jae amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED + cmp ecx, cs:[di].sOemCallout.FuncName + je FoundMatch + add di, SIZEOF sOemCallout + jmp loopThruTable + +FoundMatch: + mov bx, cs:[di].sOemCallout.FuncPtr + call bx + +amdCpuCalloutExit: + ret +AmdCalloutRouterRecovery ENDP + + +;---------------------------------------------------------------------------- +; Define the callout dispatch table for the recovery segment +;---------------------------------------------------------------------------- + +CalloutRouterTableRecovery LABEL BYTE + ;; Standard B1 implementations only need the SPD reader call out function to be implemented. + sOemCallout <AGESA_READ_SPD, OFFSET myReadSPDRecovery> +CalloutRouterTableRecoveryEnd LABEL BYTE + + +AMD_RECOVERY_END + + + +;---------------------------------------------------------------------------- +; PRE-MEMORY SEGMENT +; This segment must be uncompressed in the ROM image. +;---------------------------------------------------------------------------- + +AMD_PREMEM_START + + +;---------------------------------------------------------------------------- +; Declare the external routines required in the recovery segment +;---------------------------------------------------------------------------- + +;+--------------------------------------------------------------------------- +; +; myReadSPDPremem (Required) +; +; Entry: +; ESI - Pointer to an AGESA_READ_SPD_PARAMS structure +; +; typedef struct { +; IN OUT AMD_CONFIG_PARAMS StdHeader; +; IN UINT8 SocketId; +; IN UINT8 MemChannelId; +; IN UINT8 DimmId; +; IN OUT UINT8 *Buffer; +; IN OUT MEM_DATA_STRUCT *MemData; +; } AGESA_READ_SPD_PARAMS; +; +; Exit: +; EAX - Contains the AGESA_STATUS return code. +; AGESA_SUCCESS Indicates the SPD block for the indicated +; DIMM was read successfully. +; AGESA_BOUNDS_CHK The specified DIMM is not present. +; AGESA_UNSUPPORTED This is a required function, so this +; value being returned causes a critical +; error response value from the AGESA +; software function and no memory initialized. +; AGESA_ERROR The DIMM SPD read process has generated +; communication errors. +; +; Modified: +; None +; +; Purpose: +; This call out reads a block of memory SPD data and places it +; into the provided buffer. +; +; Dependencies: +; None +; +EXTERN myReadSPDPremem:NEAR + +;+------------------------------------------------------------------------- +; +; AmdDfltRetPremem +; +; Entry: +; None +; +; Exit: +; None +; +; Modified: +; None +; +; Purpose: +; Near stub procedure in the prememory segment. Simply perform a +; retn instruction. +; +EXTERN AmdDfltRetPremem:NEAR + +;+--------------------------------------------------------------------------- +; +; myDoReset (Required) +; +; Entry: +; EDX - Reset type +; 1 - Warm reset whenever +; 2 - Cold reset whenever +; 3 - Warm reset immediately +; 4 - Cold reset immediately +; ESI - Pointer to an AMD_CONFIG_PARAMS structure. +; +; Exit: +; EAX - Contains the AGESA_STATUS return code. +; AGESA_SUCCESS The function has completed successfully. +; AGESA_UNSUPPORTED This is a required function, so this +; value being returned causes a critical +; error response value from the AGESA +; software function. +; +; Modified: +; None +; +; Purpose: +; This host environment function must initiate the specified type +; of system reset. +; +; Implementation of this function by the host environment is +; REQUIRED. Some host environments may record this as a request +; allowing other elements in the system to perform some additional +; tasks before the actual reset is issued. +; +; Dependencies: +; The AMD processor contains 3 bits (BiosRstDet[2:0]) in a PCI +; register (F0x6C Link Initialization Control Register) that +; indicate the reset status. These bits are reserved for use by +; the AGESA software and should not be modified by the host +; environment. +; +EXTERN myDoReset:NEAR + + +;+--------------------------------------------------------------------------- +; +; myGetNonVolatileS3Context (Required for proper S3 operation) +; +; Entry: +; None +; +; Exit: +; EBX - Pointer to the non-volatile S3 context block +; ECX - Size in bytes of the non-volatile S3 context block +; +; Modified: +; None +; +; Purpose: +; The host environment must return the pointer to the data +; saved during the mySaveNonVolatileS3Context routine. +; +; Dependencies: +; None +; +EXTERN myGetNonVolatileS3Context:NEAR + + +;---------------------------------------------------------------------------- +; Declare the optional external routines in the prememory segment +;---------------------------------------------------------------------------- + +;+--------------------------------------------------------------------------- +; +; myAgesaHookBeforeExitSelfRefresh (Optional) +; +; Entry: +; Prior to this hook, AGESA will display - AGESA_TESTPOINT - 44h +; ESI - Pointer to a data structure containing the memory information +; +; Exit: +; After returning control to AGESA, AGESA will display: - AGESA_TESTPOINT - 45h +; EAX - Contains the AGESA_STATUS return code +; AGESA_SUCCESS The function has completed successfully +; AGESA_UNSUPPORTED This function is not implemented by the host environment +; AGESA_WARNING A non-critical issue has occued in the host environment +; +; Modified: +; None +; +; Purpose: +; General purpose hook called before the exiting self refresh +; This procedure is called once per channel +; +; Implementation of this function is optional for the host environment +; This call-out is an opportunity for the host environment to make dynamic +; modifications to the memory timing settings specific to the board or host +; environment before exiting self refresh on S3 resume +; +; Dependencies: +; This procedure is called before the exit self refresh bit is set in the resume +; sequence. The host environment must initiate the OS restart process. This procedure +; requires a stack. The host environment must establish the stack environment prior +; to making the call to this procedure +; +EXTERN myAgesaHookBeforeExitSelfRefresh(AmdDfltRetPremem):NEAR + + +;+--------------------------------------------------------------------------- +; +; myHookBeforeDramInit (Optional) +; +; Entry: +; Prior to this hook, AGESA will display - AGESA_TESTPOINT - 40h +; ESI - Pointer to a data structure containing the memory information +; +; Exit: +; After returning control to AGESA, AGESA will display - AGESA_TESTPOINT - 41h +; EAX - Contains the AGESA_STATUS return code. +; AGESA_SUCCESS The function has completed successfully. +; AGESA_UNSUPPORTED This function is not implemented by the host environment +; +; Modified: +; None +; +; Purpose: +; General-purpose hook called before the DRAM_Init bit is set. Called +; once per MCT +; +; Implementation of this function is optional for the host environment +; This call-out is an opportunity for the host environment to make +; dynamic modifications to the memory timing settings specific to the +; board or host environment +; +; Dependencies: +; None +; +EXTERN myHookBeforeDramInit(AmdDfltRetPremem):NEAR + + +;+--------------------------------------------------------------------------- +; +; myHookBeforeDQSTraining (Optional) +; +; Entry: +; Prior to this hook, AGESA will display - AGESA_TESTPOINT - 42h +; ESI - Pointer to a data structure containing the memory information. +; +; Exit: +; After returning control to AGESA, AGESA will display - AGESA_TESTPOINT - 43h +; EAX - Contains the AGESA_STATUS return code. +; AGESA_SUCCESS The function has completed successfully. +; AGESA_UNSUPPORTED This function is not implemented by the +; host environment. +; +; Modified: +; None +; +; Purpose: +; General-purpose hook called just before the memory training processes +; begin. Called once per MCT. +; +; Implementation of this function is optional for the host environment. +; This call-out is an opportunity for the host environment to make +; dynamic modifications to the memory timing settings specific to the +; board or host environment. +; +; The host environment may also use this call-out for some board- +; specific features that should be activated at this time point, +; such as: +; Low voltage DIMMs-the host environment should set the recommended +; voltages found in the memory data structure for each memory +; channel. This needs to occur before training begins. +; +; Dependencies: +; None +; +EXTERN myHookBeforeDQSTraining(AmdDfltRetPremem):NEAR + + +;---------------------------------------------------------------------------- +; Define the sample wrapper routines for the prememory segment +;---------------------------------------------------------------------------- + +;+--------------------------------------------------------------------------- +; +; AmdInitEarlyWrapper +; +; Entry: +; On Entry to "AmdInitEarly" AGESA will display AGESA_TESTPOINT - C4h +; DS - 0000 with 4 gigabyte access +; ES - 0000 with 4 gigabyte access +; +; Exit: +; On Exit from "AmdInitEarly" AGESA will display AGESA_TESTPOINT - C5h +; None +; +; Modified: +; None +; +; Purpose: +; A full initialization of the processor is performed. Action details +; differ for the BSP and AP processor cores. +; For the BSP, the following actions are performed: +; Full HyperTransportT link initialization, coherent and non-coherent +; Processor register loading +; Microcode patch load +; Errata workaround processing +; Launch all processor cores +; Configure the processor power management capabilities +; Request a warm reset if needed +; For the AP, the following actions are performed: +; Processor register loading +; Microcode patch load +; Errata workaround processing +; Configure the processor power management capabilities +; +; Dependencies: +; This procedure is expected to be called before main memory initialization +; and before the system warm reset. Prior to this, the basic configuration +; done by the AmdInitReset routine must be completed. +; +; This procedure requires a stack. The host environment must use one of the +; provided service functions to establish the stack environment prior to +; making the call to this procedure. +; +; The processes performed at this time point require communication between +; processor cores. +; +; The host environment must recognize that all processor cores are running +; in parallel and avoid activities that might interfere with the core-to-core +; communication, such as modifying the MTRR settings or writing to the APIC +; registers. +; +AmdInitEarlyWrapper PROC NEAR PUBLIC + local localCfgBlock:AMD_INTERFACE_PARAMS + + pushad + + ; Prepare for the call to create and initialize the input parameters for AmdInitEarly + xor eax, eax + mov ax, ss + shl eax, 4 + lea esi, localCfgBlock + add esi, eax + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0 + mov edx, SEG AmdCallout16 + shl edx, 4 + add edx, OFFSET AmdCallout16 + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx + + mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_EARLY + mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap + mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0 + push esi + mov dx, SEG AmdCalloutRouterPremem + shl edx, 16 + mov dx, OFFSET AmdCalloutRouterPremem + push edx + call AmdBridge32 + pop edx + + mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr + + ; The structure has been initialized. Now modify the default settings as desired. + + mov edi, esi + add edi, (SIZEOF AMD_CONFIG_PARAMS + (3 * (SIZEOF EXECUTION_CACHE_REGION))) + call oemPlatformConfigInit + + ; Call in to the AmdInitEarly entry point + push edx + call AmdBridge32 + pop edx + + ;; EAX = AGESA_STATUS + ;; AGESA_SUCCESS The function has completed successfully. + ;; AGESA_ALERT An HyperTransportT link CRC error was observed. + ;; AGESA_WARNING One of more of the allocation rules were violated, + ;; but an adjustment was made and space was allocated. + ;; Or a HyperTransport device does not have the expected + ;; capabilities, or unusable redundant HyperTransport + ;; links were found. + ;; AGESA_ERROR One or more of the allocation rules were violated, which + ;; resulted in a requested cache region to not be allocated. + ;; Or, a HyperTransport device failed to initialize. + ;; AGESA_CRITICAL An illegal or unsupported mixture of processor types was + ;; found, or the processors installed were found to have an + ;; insufficient MP capability rating for this platform. + + .if (eax != AGESA_SUCCESS) + mov al, (AMD_EARLY_PARAMS ptr [esi]).StdHeader.HeapStatus + mov ebx, AGESA_B2_ADDRESS + call AmdProcessAgesaErrors + .endif + + ; Allow AGESA to free the space used by AmdInitEarly + pop esi + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT + call AmdBridge32 + + + popad + ret +AmdInitEarlyWrapper ENDP + + +;+--------------------------------------------------------------------------- +; +; AmdInitPostWrapper +; +; Entry: +; On Entry to "AmdInitPost" AGESA will display AGESA_TESTPOINT - C6h +; DS - 0000 with 4 gigabyte access +; ES - 0000 with 4 gigabyte access +; +; Exit: +; On Exit from "AmdInitPost" AGESA will display AGESA_TESTPOINT - C7h +; None +; +; Modified: +; None +; +; Purpose: +; The main system memory is located, initialized, and brought on-line. +; The processor(s) are prepared for full operation and control by the +; host environment. Action details differ for the BSP and AP processor +; cores. +; For the BSP, the following actions are performed: +; Full memory initialization and configuration. BSP is the master for +; this process and may delegate some tasks to APs. +; AP collection of data for use later. +; Transfer the HOBs including the artifact data out of the pre-memory +; cache storage into a temporary holding buffer in the main memory. +; Check the BIST status of the BSP +; Shut down the APs. +; Prepare for the host environment to begin main boot activity. +; Disable the pre-memory stack. +; For the APs, the following actions are performed: +; Report core identity information. +; Execute indicated memory initialization processes as directed. +; Check the BIST status of the AP +; Disable the pre-memory stack. +; Prepare to halt, giving control to host environment. +; The entire range of system memory is enabled for Write-Back cache. +; The fixed MTRRs and the variable MTRRs[7:6] are not changed in order +; to leave in place any flash ROM region currently set for Write-Protect +; execution cache. +; +; Dependencies: +; This procedure is called after the host environment has determined that +; a normal boot to operating system should be performed after any system +; warm reset is completed and after the configuration done by AmdInitEarly +; has completed. +; +; This procedure requires a stack. The host environment must use one of the +; provided service functions to establish the stack environment prior to +; making the call to this procedure. +; +; The processes performed at this time point require communication between +; processor cores. The host environment must recognize that all processor +; cores are running in parallel and avoid activities that might interfere +; with the core-to-core communication, such as modifying the MTRR settings +; or writing to the APIC registers. +; +AmdInitPostWrapper PROC NEAR PUBLIC + local localCfgBlock:AMD_INTERFACE_PARAMS + + pushad + + ; Prepare for the call to create and initialize the input parameters for AmdInitPost + xor eax, eax + mov ax, ss + shl eax, 4 + lea esi, localCfgBlock + add esi, eax + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0 + mov edx, SEG AmdCallout16 + shl edx, 4 + add edx, OFFSET AmdCallout16 + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx + + mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_POST + mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap + mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0 + push esi + mov dx, SEG AmdCalloutRouterPremem + shl edx, 16 + mov dx, OFFSET AmdCalloutRouterPremem + push edx + call AmdBridge32 + pop edx + + mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr + + ; The structure has been initialized. Now modify the default settings as desired. + + mov edi, esi + add edi, SIZEOF AMD_CONFIG_PARAMS + call oemPlatformConfigInit + + ; Call in to the AmdInitPost entry point + push edx + call AmdBridge32 + pop edx + + ;; EAX = AGESA_STATUS + ;; AGESA_SUCCESS The function has completed successfully. + ;; AGESA_ALERT A BIST error was found on one of the cores. + ;; AGESA_WARNING HT Assist feature is running sub-optimally. + ;; AGESA_FATAL Memory initialization failed. + + .if (eax != AGESA_SUCCESS) + mov al, (AMD_POST_PARAMS ptr [esi]).StdHeader.HeapStatus + mov ebx, AGESA_B2_ADDRESS + call AmdProcessAgesaErrors + .endif + + ; Allow AGESA to free the space used by AmdInitPost + pop esi + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT + call AmdBridge32 + + + popad + ret +AmdInitPostWrapper ENDP + + +;+--------------------------------------------------------------------------- +; +; AmdInitResumeWrapper +; +; Entry: +; On Entry to "AmdInitResume" AGESA will display AGESA_TESTPOINT - D0h +; DS - 0000 with 4 gigabyte access +; ES - 0000 with 4 gigabyte access +; +; Exit: +; On Exit from "AmdInitResume" AGESA will display AGESA_TESTPOINT - D1h +; None +; +; Modified: +; None +; +; Purpose: +; This procedure initializes or re-initializes the silicon components +; for the resume boot path. For the processor, main memory is brought +; out of self-refresh mode. This procedure will use the context data +; in the NvStorage area of the input structure to re-start the main +; memory. The host environment must fill the AMD_S3_PARAMS NvStorage +; and VolatileStorage pointers and related size elements to describe +; the location of the context data. Note that for this procedure, the +; two data areas do not need to be contained in one buffer zone, they +; can be anywhere in the accessible memory address space. If the host +; environment uses a non-volatile storage device accessed on the system +; address bus such as flashROM, then the context data does not need to +; be moved prior to this call. If the host environment uses a non- +; volatile storage device not located on the system address bus (e.g. +; CMOS or SSEPROM) then the host environment must transfer the context +; data to a buffer in main memory prior to calling this procedure. +; +; Dependencies: +; The host environment must have determined that the system should take +; the resume path prior to calling this procedure. The configuration +; done by AmdInitEarly and any necessary warm reset must be complete. +; After this procedure, execution proceeds to general system restoration. +; +; This procedure requires a stack. The host environment must use one of +; the provided service functions to establish the stack environment prior +; to making the call to this procedure. +; +AmdInitResumeWrapper PROC NEAR PUBLIC + local localCfgBlock:AMD_INTERFACE_PARAMS + + pushad + + ; Prepare for the call to create and initialize the input parameters for AmdInitResume + xor eax, eax + mov ax, ss + shl eax, 4 + lea esi, localCfgBlock + add esi, eax + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0 + mov edx, SEG AmdCallout16 + shl edx, 4 + add edx, OFFSET AmdCallout16 + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx + + mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RESUME + mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap + mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0 + push esi + mov dx, SEG AmdCalloutRouterPremem + shl edx, 16 + mov dx, OFFSET AmdCalloutRouterPremem + push edx + call AmdBridge32 + pop edx + + mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr + + ; The structure has been initialized. Now modify the default settings as desired. + + mov edi, esi + add edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS) + call oemPlatformConfigInit + + call myGetNonVolatileS3Context + mov (AMD_RESUME_PARAMS ptr [esi]).S3DataBlock.NvStorage, ebx + mov (AMD_RESUME_PARAMS ptr [esi]).S3DataBlock.NvStorageSize, ecx + + ; Call in to the AmdInitResume entry point + push edx + call AmdBridge32 + pop edx + + ;; EAX = AGESA_STATUS + ;; AGESA_SUCCESS Re-initialization has been completed successfully. + .if (eax != AGESA_SUCCESS) + mov al, (AMD_RESUME_PARAMS ptr [esi]).StdHeader.HeapStatus + mov ebx, AGESA_B2_ADDRESS + call AmdProcessAgesaErrors + .endif + + + ; Allow AGESA to free the space used by AmdInitResume + pop esi + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT + call AmdBridge32 + + + popad + ret +AmdInitResumeWrapper ENDP + + +;+--------------------------------------------------------------------------- +; +; AmdCalloutRouterPremem +; +; Entry: +; ECX - Callout function number +; EDX - Function-specific UINTN +; ESI - Pointer to function specific data +; +; Exit: +; EAX - Contains the AGESA_STATUS return code. +; +; Modified: +; None +; +; Purpose: +; The call out router function for AmdInitEarly, +; AmdInitPost, and AmdInitResume. +; +; Dependencies: +; None +; +AmdCalloutRouterPremem PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES + xor ax, ax + mov ds, ax + mov es, ax + lea di, cs:CalloutRouterTablePremem + mov eax, AGESA_UNSUPPORTED + +loopThruTable: + cmp di, OFFSET cs:CalloutRouterTablePrememEnd + jae amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED + cmp ecx, cs:[di].sOemCallout.FuncName + je FoundMatch + add di, SIZEOF sOemCallout + jmp loopThruTable + +FoundMatch: + mov bx, cs:[di].sOemCallout.FuncPtr + call bx + +amdCpuCalloutExit: + ret +AmdCalloutRouterPremem ENDP + + +;---------------------------------------------------------------------------- +; Define the callout dispatch table for the prememory segment +;---------------------------------------------------------------------------- + +CalloutRouterTablePremem LABEL BYTE + ;; Add entries as desired. + sOemCallout <AGESA_READ_SPD, OFFSET myReadSPDPremem> + sOemCallout <AGESA_HOOKBEFORE_DRAM_INIT, OFFSET myHookBeforeDramInit> + sOemCallout <AGESA_HOOKBEFORE_DQS_TRAINING, OFFSET myHookBeforeDQSTraining> + sOemCallout <AGESA_HOOKBEFORE_EXIT_SELF_REF, OFFSET myAgesaHookBeforeExitSelfRefresh> + sOemCallout <AGESA_DO_RESET, OFFSET myDoReset> +;del sOemCallout <AGESA_EXTERNAL_2D_TRAIN_VREF_CHANGE, OFFSET my2DTrainVrefChange> +CalloutRouterTablePrememEnd LABEL BYTE + + + +AMD_PREMEM_END + + +;---------------------------------------------------------------------------- +; POST SEGMENT +; This segment may be decompressed and run from system RAM. +;---------------------------------------------------------------------------- + +AMD_POST_START + + +;---------------------------------------------------------------------------- +; Declare the external routines required in the POST segment +;---------------------------------------------------------------------------- + +;+--------------------------------------------------------------------------- +; +; myAllocateBuffer (Required) +; +; Entry: +; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E2h +; ESI - Pointer to an AGESA_BUFFER_PARAMS structure. +; +; typedef struct { +; IN OUT AMD_CONFIG_PARAMS StdHeader; +; IN UINT32 BufferLength; +; IN UINT32 BufferHandle; +; OUT VOID *BufferPointer; +; } AGESA_BUFFER_PARAMS; +; +; Exit: +; After this hook, AGESA will display - AGESA_TESTPOINT - E3h +; EAX - Contains the AGESA_STATUS return code. +; AGESA_SUCCESS The requested size of memory has been +; successfully allocated. +; AGESA_UNSUPPORTED This is a required function, so this +; value being returned causes a critical +; error response value from the AGESA +; software function. +; AGESA_ERROR Less than the requested amount of memory +; was allocated. +; +; Modified: +; EAX +; +; Purpose: +; This function is used after main memory has been initialized +; and the host environment has taken control of memory allocation. +; This function must allocate a buffer of the requested size or +; larger. This function is required to be implemented by the host +; environment. +; +; Dependencies: +; The following call-outs must work together in the host system. +; Parameters of the same name have the same function and must be +; treated the same in each function: +; AgesaAllocateBuffer +; AgesaDeallocateBuffer +; AgesaLocateBuffer +; AgesaRunFcnOnAp +; The host environment may need to reserve a location in the buffer +; to store any host environment specific value(s). The returned +; pointer must not include this reserved space. The host environment +; on the AgesaDeallocateBuffer call needs to account for the reserved +; space. This reserved space may be an identifier or the "handle" +; used to identify the specific memory block. +; +EXTERN myAllocateBuffer:NEAR + +;+--------------------------------------------------------------------------- +; +; myDeallocateBuffer (Required) +; +; Entry: +; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E4h +; ESI - Pointer to an AGESA_BUFFER_PARAMS structure. +; +; typedef struct { +; IN OUT AMD_CONFIG_PARAMS StdHeader; +; IN UINT32 BufferLength; +; IN UINT32 BufferHandle; +; OUT VOID *BufferPointer; +; } AGESA_BUFFER_PARAMS; +; +; Exit: +; After this hook, AGESA will display - AGESA_TESTPOINT - E5h +; EAX - Contains the AGESA_STATUS return code. +; AGESA_SUCCESS The function has completed successfully. +; AGESA_BOUNDS_CHK The BufferHandle is invalid. The AGESA +; software continues with its function. +; AGESA_UNSUPPORTED This is a required function, so this +; value being returned causes a critical +; error response value from the AGESA +; software function. +; +; Modified: +; EAX +; +; Purpose: +; This function is used after main memory has been initialized +; and the host environment has taken control of memory allocation. +; This function releases a valid working buffer. This function is +; required for the host environment to implement. +; +; Dependencies: +; The following call-outs must work together in the host system. +; Parameters of the same name have the same function and must be +; treated the same in each function: +; AgesaAllocateBuffer +; AgesaDeallocateBuffer +; AgesaLocateBuffer +; AgesaRunFcnOnAp +; +EXTERN myDeallocateBuffer:NEAR + +;+--------------------------------------------------------------------------- +; +; myLocateBuffer (Required) +; +; Entry: +; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E6h +; ESI - Pointer to an AGESA_BUFFER_PARAMS structure. +; +; typedef struct { +; IN OUT AMD_CONFIG_PARAMS StdHeader; +; IN UINT32 BufferLength; +; IN UINT32 BufferHandle; +; OUT VOID *BufferPointer; +; } AGESA_BUFFER_PARAMS; +; +; Exit: +; After this hook, AGESA will display - AGESA_TESTPOINT - E7h +; EAX - Contains the AGESA_STATUS return code. +; AGESA_SUCCESS The function has completed successfully. +; AGESA_BOUNDS_CHK The presented handle is invalid or the +; buffer could not be located. +; +; Modified: +; EAX +; +; Purpose: +; This function is used after main memory has been initialized +; and the host environment has taken control of memory allocation. +; This function must locate the buffer related to the indicated +; handle and return the address of the buffer and its length. +; This function is required to be implemented in the host +; environment. +; +; Dependencies: +; The following call-outs must work together in the host system. +; Parameters of the same name have the same function and must be +; treated the same in each function: +; AgesaAllocateBuffer +; AgesaDeallocateBuffer +; AgesaLocateBuffer +; AgesaRunFcnOnAp +; +EXTERN myLocateBuffer:NEAR + + +;+--------------------------------------------------------------------------- +; +; myRunFuncOnAp (Required) +; +; Entry: +; EDX - Local APIC ID of the target core. +; +; Exit: +; None +; +; Modified: +; None +; +; Purpose: +; The host environment must route execution to the target AP and +; have that AP call the AmdLateRunApTaskWrapper routine defined +; above. +; +; Dependencies: +; None +; +EXTERN myRunFuncOnAp:NEAR + +;+--------------------------------------------------------------------------- +; +; mySaveNonVolatileS3Context (Required for proper S3 operation) +; +; Entry: +; EBX - Pointer to the non-volatile S3 context block +; ECX - Size in bytes of the non-volatile S3 context block +; +; Exit: +; None +; +; Modified: +; None +; +; Purpose: +; The host environment must save the non-volatile data to an area +; that will not lose context while in the ACPI S3 sleep state, but +; cannot be placed in system RAM. This data will need to be +; available during the call to AmdInitResume. +; +; Dependencies: +; None +; +EXTERN mySaveNonVolatileS3Context:NEAR + +;+--------------------------------------------------------------------------- +; +; mySaveVolatileS3Context (Required for proper S3 operation) +; +; Entry: +; EBX - Pointer to the volatile S3 context block +; ECX - Size in bytes of the volatile S3 context block +; +; Exit: +; None +; +; Modified: +; None +; +; Purpose: +; The host environment must save the volatile data to an area +; that will not lose context while in the ACPI S3 sleep state. +; This data will need to be available during the call to +; AmdS3LateRestore. +; +; Dependencies: +; None +; +EXTERN mySaveVolatileS3Context:NEAR + +;+--------------------------------------------------------------------------- +; +; myGetVolatileS3Context (Required for proper S3 operation) +; +; Entry: +; None +; +; Exit: +; EBX - Pointer to the volatile S3 context block +; ECX - Size in bytes of the volatile S3 context block +; +; Modified: +; None +; +; Purpose: +; The host environment must return the pointer to the data +; saved during the mySaveVolatileS3Context routine. +; +; Dependencies: +; None +; +EXTERN myGetVolatileS3Context:NEAR + + +;---------------------------------------------------------------------------- +; Define the sample wrapper routines for the POST segment +;---------------------------------------------------------------------------- + +;+--------------------------------------------------------------------------- +; +; AmdInitEnvWrapper +; +; Entry: +; On Entry to "AmdInitEnv" AGESA will display AGESA_TESTPOINT - C8h +; DS - 0000 with 4 gigabyte access +; ES - 0000 with 4 gigabyte access +; +; Exit: +; On Exit from "AmdInitEnv" AGESA will display AGESA_TESTPOINT - C9h +; None +; +; Modified: +; None +; +; Purpose: +; This procedure uses the AgesaAllocateBuffer call-out to acquire +; permanent buffer space for the UEFI Hand-Off Blocks (HOBs). This +; is also known as, or includes, artifact data being used by the +; AGESA software. Upon entry to this procedure, the data is being +; held in a temporary memory location and it must be moved to a +; location controlled and protected by the host environment. +; +; These actions are performed by the BSP. The APs are not assigned +; any tasks at this time point. +; +; Dependencies: +; This procedure must be called after full memory is initialized and +; the host environment has taken control of main memory allocation. +; This procedure should be called before the PCI enumeration takes +; place and as soon as possible after the host environment memory +; allocation sub-system has started. +; +; This procedure requires a stack. The host environment must use one +; of the provided service functions to establish the stack environment +; prior to making the call to this procedure. +; +AmdInitEnvWrapper PROC NEAR PUBLIC + local localCfgBlock:AMD_INTERFACE_PARAMS + + pushad + + ; Prepare for the call to create and initialize the input parameters for AmdInitEnv + xor eax, eax + mov ax, ss + shl eax, 4 + lea esi, localCfgBlock + add esi, eax + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0 + mov edx, SEG AmdCallout16 + shl edx, 4 + add edx, OFFSET AmdCallout16 + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx + + mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_ENV + mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram + mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0 + push esi + mov dx, SEG AmdCalloutRouterPost + shl edx, 16 + mov dx, OFFSET AmdCalloutRouterPost + push edx + call AmdBridge32 + pop edx + + mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr + + ; The structure has been initialized. Now modify the default settings as desired. + + mov edi, esi + add edi, SIZEOF AMD_CONFIG_PARAMS + call oemPlatformConfigInit + + ; Call in to the AmdInitEnv entry point + push edx + call AmdBridge32 + pop edx + + ;; EAX = AGESA_STATUS + ;; AGESA_SUCCESS The function has completed successfully. + ;; AGESA_ERROR The artifact data could not be found or the host + ;; environment failed to allocate sufficient buffer space. + + .if (eax != AGESA_SUCCESS) + mov al, (AMD_ENV_PARAMS ptr [esi]).StdHeader.HeapStatus + mov ebx, AGESA_B2_ADDRESS + call AmdProcessAgesaErrors + .endif + + ; Allow AGESA to free the space used by AmdInitEnv + pop esi + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT + call AmdBridge32 + + + popad + ret +AmdInitEnvWrapper ENDP + + +;+--------------------------------------------------------------------------- +; +; AmdInitMidWrapper +; +; Entry: +; On Entry to "AmdInitMid" AGESA will display AGESA_TESTPOINT - CAh +; DS - 0000 with 4 gigabyte access +; ES - 0000 with 4 gigabyte access +; +; Exit: +; On Exit from "AmdInitMid" AGESA will display AGESA_TESTPOINT - CBh +; None +; +; Modified: +; None +; +; Purpose: +; This procedure call performs special configuration requirements for +; the graphics display hardware. +; +; These actions are performed by the BSP. The APs are not assigned any +; tasks at this time point. +; +; Dependencies: +; This procedure must be called after PCI enumeration has allocated +; resources, but before the video BIOS call is performed. +; +; This procedure requires a stack. The host environment must use one +; of the provided service functions to establish the stack environment +; prior to making the call to this procedure. +; +AmdInitMidWrapper PROC NEAR PUBLIC + local localCfgBlock:AMD_INTERFACE_PARAMS + + pushad + + ; Prepare for the call to create and initialize the input parameters for AmdInitMid + xor eax, eax + mov ax, ss + shl eax, 4 + lea esi, localCfgBlock + add esi, eax + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0 + mov edx, SEG AmdCallout16 + shl edx, 4 + add edx, OFFSET AmdCallout16 + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx + + mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_MID + mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram + mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0 + push esi + mov dx, SEG AmdCalloutRouterPost + shl edx, 16 + mov dx, OFFSET AmdCalloutRouterPost + push edx + call AmdBridge32 + pop edx + + mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr + + ; The structure has been initialized. Now modify the default settings as desired. + + mov edi, esi + add edi, SIZEOF AMD_CONFIG_PARAMS + call oemPlatformConfigInit + + ; Call in to the AmdInitMid entry point + push edx + call AmdBridge32 + pop edx + + ;; EAX = AGESA_STATUS + ;; AGESA_SUCCESS The function has completed successfully. + + .if (eax != AGESA_SUCCESS) + mov al, (AMD_MID_PARAMS ptr [esi]).StdHeader.HeapStatus + mov ebx, AGESA_B2_ADDRESS + call AmdProcessAgesaErrors + .endif + + ; Allow AGESA to free the space used by AmdInitMid + pop esi + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT + call AmdBridge32 + + + popad + ret + +AmdInitMidWrapper ENDP + + +;+--------------------------------------------------------------------------- +; +; AmdInitLateWrapper +; +; Entry: +; On Entry to "AmdInitLate" AGESA will display AGESA_TESTPOINT - CCh +; DS - 0000 with 4 gigabyte access +; ES - 0000 with 4 gigabyte access +; +; Exit: +; On Exit from "AmdInitLate" AGESA will display AGESA_TESTPOINT - CDh +; None +; +; Modified: +; None +; +; Purpose: +; The main purpose of this function is to generate informational +; data tables used by the operating system. The individual tables +; can be selected for generation through the user selection entries +; on the input parameters. +; +; This routine uses the Call-Out AgesaAllocateBuffer to allocate a +; buffer of the proper size to contain the data. +; +; The code path separates the BSP from the APs and perform a separate +; and appropriate list of tasks for each class of core. +; For the BSP, the following actions are performed: +; Allocate buffer space for the tables. +; Generate the table contents. +; Make sure that the CPU is in a known good power state before +; proceeding to boot the OS. +; For the APs, the following actions are performed: +; Final register settings preparing for entry to OS. +; Establish the final PState for entry to OS. +; +; Dependencies: +; This routine is expected to be executed late in the boot sequence +; after main memory has been initialized, after PCI enumeration has +; completed, after the host environment ACPI sub-system has started, +; after the host environment has taken control of the APs, but just +; before the start of OS boot. +; +; The host environment must provide the required call-outs listed in +; the "Required Call-Out Procedures" section of the AGESA interface +; specification to provide the buffer space in main memory and execute +; code on the APs. The host environment must register the created ACPI +; table in the main ACPI pointer tables. This may require moving the +; generated tables to another location in memory. +; +; This procedure requires a stack. The host environment must establish +; the stack environment prior to making the call to this procedure. +; Some functions depend upon the preservation of the heap data across +; the shift from pre-memory environment to a post-memory environment. +; If that data was not preserved, then those functions cannot complete +; and an error is returned. +; +AmdInitLateWrapper PROC NEAR PUBLIC + local localCfgBlock:AMD_INTERFACE_PARAMS + + pushad + + ; Prepare for the call to create and initialize the input parameters for AmdInitLate + xor eax, eax + mov ax, ss + shl eax, 4 + lea esi, localCfgBlock + add esi, eax + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0 + mov edx, SEG AmdCallout16 + shl edx, 4 + add edx, OFFSET AmdCallout16 + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx + + mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_LATE + mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram + mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0 + push esi + mov dx, SEG AmdCalloutRouterPost + shl edx, 16 + mov dx, OFFSET AmdCalloutRouterPost + push edx + call AmdBridge32 + pop edx + + mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr + + ; The structure has been initialized. Now modify the default settings as desired. + + mov edi, esi + add edi, SIZEOF AMD_CONFIG_PARAMS + call oemPlatformConfigInit + + ; Call in to the AmdInitLate entry point + push edx + call AmdBridge32 + pop edx + + ;; EAX = AGESA_STATUS + ;; AGESA_SUCCESS The function has completed successfully. + ;; AGESA_ALERT + ;; AGESA_ERROR The system could not allocate the needed amount of + ;; buffer space; or could not locate the artifact data block in + ;; memory. Likely cause: the host environment may not have preserved + ;; the data properly. + + .if (eax != AGESA_SUCCESS) + mov al, (AMD_LATE_PARAMS ptr [esi]).StdHeader.HeapStatus + mov ebx, AGESA_B2_ADDRESS + call AmdProcessAgesaErrors + .endif + + push es + mov ax, SEG AmdAcpiSratPointer + mov es, ax + + mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiSrat + mov es:AmdAcpiSratPointer, ebx + mov eax, DWORD PTR [ebx + 4] + mov es:AmdAcpiSratSize, eax + + mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiSlit + mov es:AmdAcpiSlitPointer, ebx + mov eax, DWORD PTR [ebx + 4] + mov es:AmdAcpiSlitSize, eax + + mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiPState + mov es:AmdAcpiSsdtPointer, ebx + mov eax, DWORD PTR [ebx + 4] + mov es:AmdAcpiSsdtSize, eax + + xor eax, eax + + mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiWheaMce + mov es:AmdAcpiWheaMcePointer, ebx + mov ax, WORD PTR [ebx] + mov es:AmdAcpiWheaMceSize, eax + + mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiWheaMce + mov es:AmdAcpiWheaCmcPointer, ebx + mov ax, WORD PTR [ebx] + mov es:AmdAcpiWheaCmcSize, eax + + mov eax, (AMD_LATE_PARAMS ptr [esi]).DmiTable + mov es:AmdDmiInfoPointer, eax + pop es + + + ; Allow AGESA to free the space used by AmdInitLate + pop esi + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT + call AmdBridge32 + + popad + ret + +AmdInitLateWrapper ENDP + + +;+--------------------------------------------------------------------------- +; +; AmdS3SaveWrapper +; +; Entry: +; On Entry to "AmdS3Save" AGESA will display AGESA_TESTPOINT - CEh +; DS - 0000 with 4 gigabyte access +; ES - 0000 with 4 gigabyte access +; +; Exit: +; On Entry to "AmdS3Save" AGESA will display AGESA_TESTPOINT - CFh +; None +; +; Modified: +; None +; +; Purpose: +; This procedure saves critical registers and/or configuration +; information for preservation across a system suspend mode. All +; actions needed to prepare the processor for suspend mode is +; performed, however this procedure does NOT initiate the suspend +; process. The host environment is expected to perform that duty. +; +; These actions are performed by the BSP. The APs are not assigned +; any tasks at this time point. +; +; The initializer routine will NULL out the save area pointers and +; sizes. This procedure will determine the size of storage needed +; for all the processor context, and make a call out to the environment +; for allocation of one buffer to store all of the data. Upon exit, the +; pointers and sizes within the AMD_S3_PARAMS structure will be updated +; with the appropriate addresses within the buffer that was allocated. +; The host environment is expected to then transfer the data pointed to +; by NvStorage to a non-volatile storage area, and the data pointed to +; by VolatileStorage to either a non-volatile storage area or system +; RAM that retains its content across suspend. +; +; Dependencies: +; The host environment must initiate the suspend process. +; +; This procedure requires a stack. The host environment must establish +; the stack environment prior to making the call to this procedure. +; +AmdS3SaveWrapper PROC NEAR PUBLIC + local localCfgBlock:AMD_INTERFACE_PARAMS + + pushad + + ; Prepare for the call to create and initialize the input parameters for AmdS3Save + xor eax, eax + mov ax, ss + shl eax, 4 + lea esi, localCfgBlock + add esi, eax + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0 + mov edx, SEG AmdCallout16 + shl edx, 4 + add edx, OFFSET AmdCallout16 + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx + + mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_S3_SAVE + mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram + mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0 + push esi + mov dx, SEG AmdCalloutRouterPost + shl edx, 16 + mov dx, OFFSET AmdCalloutRouterPost + push edx + call AmdBridge32 + pop edx + + mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr + + ; The structure has been initialized. Now modify the default settings as desired. + + mov edi, esi + add edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS) + call oemPlatformConfigInit + + ; Call in to the AmdS3Save entry point + push edx + call AmdBridge32 + pop edx + + ;; EAX = AGESA_STATUS + ;; AGESA_SUCCESS All suspend duties have been completed successfully. + + .if (eax != AGESA_SUCCESS) + mov al, (AMD_S3SAVE_PARAMS ptr [esi]).StdHeader.HeapStatus + mov ebx, AGESA_B2_ADDRESS + call AmdProcessAgesaErrors + .endif + + mov ecx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.NvStorageSize + .if (ecx != 0) + mov ebx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.NvStorage + call mySaveNonVolatileS3Context + .endif + + mov ecx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.VolatileStorageSize + .if (ecx != 0) + mov ebx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.VolatileStorage + call mySaveVolatileS3Context + .endif + + ; Allow AGESA to free the space used by AmdS3Save + pop esi + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT + call AmdBridge32 + + popad + ret + +AmdS3SaveWrapper ENDP + + +;+--------------------------------------------------------------------------- +; +; AmdS3LateRestoreWrapper +; +; Entry: +; On Entry to "AmdS3LateRestore" AGESA will display AGESA_TESTPOINT - D2h +; DS - 0000 with 4 gigabyte access +; ES - 0000 with 4 gigabyte access +; +; Exit: +; On Exit from "AmdS3LateRestore" AGESA will display AGESA_TESTPOINT - D3h +; None +; +; Modified: +; None +; +; Purpose: +; This procedure restores the processor state, reloads critical +; silicon component registers, and performs any re-initialization +; required by the silicon. This procedure will use the context data +; in the VolatileStorage area of the input structure to restore the +; processor registers. +; +; The host environment must fill the AMD_S3_PARAMS NvStorage and +; VolatileStorage pointers and related size elements to describe +; the location of the context data. Note that for this procedure, +; the two data areas do not need to be contained in one buffer zone, +; they can be anywhere in the accessible memory address space. If +; the host environment uses a non-volatile storage device accessed +; on the system address bus such as flashROM, then the context data +; does not need to be moved prior to this call. If the host +; environment uses a non-volatile storage device not located on the +; system address bus (e.g. CMOS or SSEPROM) then the host environment +; must transfer the context data to a buffer in main memory prior to +; calling this procedure. +; +; These actions are performed by the BSP. The APs are not assigned +; any tasks at this time point. +; +; Dependencies: +; This procedure is called late in the resume sequence, after the +; PCI control space is restored and just before resuming operating +; system execution. +; +; The host environment must initiate the OS restart process. +; +; This procedure requires a stack. The host environment must establish +; the stack environment prior to making the call to this procedure. +; +AmdS3LateRestoreWrapper PROC NEAR PUBLIC + local localCfgBlock:AMD_INTERFACE_PARAMS + + pushad + + ; Prepare for the call to create and initialize the input parameters for AmdS3LateRestore + xor eax, eax + mov ax, ss + shl eax, 4 + lea esi, localCfgBlock + add esi, eax + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0 + mov edx, SEG AmdCallout16 + shl edx, 4 + add edx, OFFSET AmdCallout16 + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx + + mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_S3LATE_RESTORE + mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram + mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0 + push esi + mov dx, SEG AmdCalloutRouterPost + shl edx, 16 + mov dx, OFFSET AmdCalloutRouterPost + push edx + call AmdBridge32 + pop edx + + mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr + + ; The structure has been initialized. Now modify the default settings as desired. + + mov edi, esi + add edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS) + call oemPlatformConfigInit + + call myGetVolatileS3Context + mov (AMD_S3LATE_PARAMS ptr [esi]).S3DataBlock.VolatileStorage, ebx + mov (AMD_S3LATE_PARAMS ptr [esi]).S3DataBlock.VolatileStorageSize, ecx + + ; Call in to the AmdS3LateRestore entry point + push edx + call AmdBridge32 + pop edx + + ;; EAX = AGESA_STATUS + ;; AGESA_SUCCESS All resume processes have been completed successfully. + + .if (eax != AGESA_SUCCESS) + mov al, (AMD_S3LATE_PARAMS ptr [esi]).StdHeader.HeapStatus + mov ebx, AGESA_B2_ADDRESS + call AmdProcessAgesaErrors + .endif + + ; Allow AGESA to free the space used by AmdS3LateRestore + pop esi + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT + call AmdBridge32 + + popad + ret +AmdS3LateRestoreWrapper ENDP + + +;+--------------------------------------------------------------------------- +; +; AmdLateRunApTaskWrapper +; +; Entry: +; Prior to this hook, AGESA will display - AGESA_TESTPOINT - D4h +; DS - 0000 with 4 gigabyte access +; ES - 0000 with 4 gigabyte access +; +; Exit: +; After this hook, AGESA will display - AGESA_TESTPOINT - D5h +; None +; +; Modified: +; None +; +; Purpose: +; This entry point is tightly connected with the "AgesaRunFcnOnAp" +; call out. The AGESA software will call the call-out "AgesaRunFcnOnAp"; +; the host environment will then call this entry point to have the AP +; execute the requested function. This is needed late in the Post and +; Resume branches for running an AP task since the AGESA software has +; relinquished control of the APs to the host environment. +; +; Dependencies: +; The host environment must implement the"AgesaRunFcnOnAp" call-out +; and route execution to the target AP. +; +AmdLateRunApTaskWrapper PROC NEAR PUBLIC + local localCfgBlock:AMD_INTERFACE_PARAMS + + pushad + + ; Prepare for the call to create and initialize the input parameters for AmdLateRunApTask + xor eax, eax + mov ax, ss + shl eax, 4 + lea esi, localCfgBlock + add esi, eax + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0 + mov edx, SEG AmdCallout16 + shl edx, 4 + add edx, OFFSET AmdCallout16 + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx + + mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_LATE_RUN_AP_TASK + mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram + mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0 + push esi + mov dx, SEG AmdCalloutRouterPost + shl edx, 16 + mov dx, OFFSET AmdCalloutRouterPost + push edx + call AmdBridge32 + pop edx + + mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr + + ; The structure has been initialized. Now modify the default settings as desired. + + push es + mov ax, SEG AmdRunCodeOnApDataPointer + mov es, ax + mov eax, es:AmdRunCodeOnApDataPointer + mov (AP_EXE_PARAMS PTR [esi]).RelatedDataBlock, eax + mov eax, es:AmdRunCodeOnApDataSize + mov (AP_EXE_PARAMS PTR [esi]).RelatedBlockLength, eax + mov eax, es:AmdRunCodeOnApFunction + mov (AP_EXE_PARAMS PTR [esi]).FunctionNumber, eax + pop es + + ; Call in to the AmdLateRunApTask dispatcher + push edx + call AmdBridge32 + pop edx + + ;; EAX = AGESA_STATUS + push es + mov bx, SEG AmdRunCodeOnApStatus + mov es, bx + mov es:AmdRunCodeOnApStatus, eax + pop es + + ; Allow AGESA to free the space used by AmdLateRunApTask + pop esi + mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT + call AmdBridge32 + + popad + ret + +AmdLateRunApTaskWrapper ENDP + + +;+--------------------------------------------------------------------------- +; +; AmdRunFuncOnAp (Required) +; +; Entry: +; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E8h +; EDX - Local APIC ID of the target core. +; ESI - Pointer to an AP_EXE_PARAMS structure. +; +; typedef struct { +; IN OUT AMD_CONFIG_PARAMS StdHeader; +; IN UINT32 FunctionNumber; +; IN VOID *RelatedDataBlock; +; IN UINT32 RelatedDataBlockLength; +; } AP_EXE_PARAMS; +; +; Exit: +; After this hook, AGESA will display - AGESA_TESTPOINT - E9h +; EAX - Contains the AGESA_STATUS return code. +; AGESA_SUCCESS The function has completed successfully. +; AGESA_UNSUPPORTED This is a required function, so this value +; being returned causes a critical error +; response value from the AGESAT software +; function and no memory initialized. +; AGESA_WARNING The AP did not respond. +; +; Modified: +; EAX +; +; Purpose: +; This function is used after main memory has been initialized +; and the host environment has taken control of AP task dispatching. +; This function must cause the indicated function code to be executed +; upon the specified Application Processor. This procedure must be +; executed in 32-bit mode. This function is required to be implemented +; in the host environment. +; +; Dependencies: +; The host environment must route execution to the target AP and +; have that AP call the"AmdLateRunApTask" entry point. +; +AmdRunFuncOnAp PROC NEAR PUBLIC + + push es + mov ax, SEG AmdRunCodeOnApDataPointer + mov es, ax + mov eax, (AP_EXE_PARAMS PTR [esi]).RelatedDataBlock + mov es:AmdRunCodeOnApDataPointer, eax + mov eax, (AP_EXE_PARAMS PTR [esi]).RelatedBlockLength + mov es:AmdRunCodeOnApDataSize, eax + mov eax, (AP_EXE_PARAMS PTR [esi]).FunctionNumber + mov es:AmdRunCodeOnApFunction, eax + mov eax, AGESA_UNSUPPORTED + mov es:AmdRunCodeOnApStatus, eax + pop es + + call myRunFuncOnAp + + push es + mov ax, SEG AmdRunCodeOnApStatus + mov es, ax + mov eax, es:AmdRunCodeOnApStatus + pop es + ret +AmdRunFuncOnAp ENDP + + + +;+--------------------------------------------------------------------------- +; +; AmdCalloutRouterPost +; +; Entry: +; ECX - Callout function number +; EDX - Function-specific UINTN +; ESI - Pointer to function specific data +; +; Exit: +; EAX - Contains the AGESA_STATUS return code. +; +; Modified: +; None +; +; Purpose: +; The call out router function for AmdInitEnv, +; AmdInitMid, AmdInitLate, AmdS3Save, and +; AmdS3LateRestore. +; +; Dependencies: +; None +; +AmdCalloutRouterPost PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES + xor ax, ax + mov ds, ax + mov es, ax + lea di, cs:CalloutRouterTablePost + mov eax, AGESA_UNSUPPORTED + +loopThruTable: + cmp di, OFFSET cs:CalloutRouterTablePostEnd + jae amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED + cmp ecx, cs:[di].sOemCallout.FuncName + je FoundMatch + add di, SIZEOF sOemCallout + jmp loopThruTable + +FoundMatch: + mov bx, cs:[di].sOemCallout.FuncPtr + call bx + +amdCpuCalloutExit: + ret +AmdCalloutRouterPost ENDP + + +;---------------------------------------------------------------------------- +; Define the callout dispatch table for the POST segment +;---------------------------------------------------------------------------- + +CalloutRouterTablePost LABEL BYTE + ;; Add entries as desired. + sOemCallout <AGESA_ALLOCATE_BUFFER, OFFSET myAllocateBuffer> + sOemCallout <AGESA_DEALLOCATE_BUFFER, OFFSET myDeallocateBuffer> + sOemCallout <AGESA_LOCATE_BUFFER, OFFSET myLocateBuffer> + sOemCallout <AGESA_RUNFUNC_ONAP, OFFSET AmdRunFuncOnAp> +CalloutRouterTablePostEnd LABEL BYTE + +AMD_POST_END + + +;---------------------------------------------------------------------------- +; CPU DATA SEGMENT +; This segment must be writable, and present at the time that +; AmdInitLate is run. +;---------------------------------------------------------------------------- + +CPU_DATASEG_START + + ;; Data used to store pointers for later use by the host environment. + PUBLIC AmdAcpiSratPointer + PUBLIC AmdAcpiSratSize + PUBLIC AmdAcpiSlitPointer + PUBLIC AmdAcpiSlitSize + PUBLIC AmdAcpiSsdtPointer + PUBLIC AmdAcpiSsdtSize + PUBLIC AmdAcpiWheaMcePointer + PUBLIC AmdAcpiWheaMceSize + PUBLIC AmdAcpiWheaCmcPointer + PUBLIC AmdAcpiWheaCmcSize + PUBLIC AmdDmiInfoPointer + AmdAcpiSratPointer DWORD ? + AmdAcpiSratSize DWORD ? + AmdAcpiSlitPointer DWORD ? + AmdAcpiSlitSize DWORD ? + AmdAcpiSsdtPointer DWORD ? + AmdAcpiSsdtSize DWORD ? + AmdAcpiWheaMcePointer DWORD ? + AmdAcpiWheaMceSize DWORD ? + AmdAcpiWheaCmcPointer DWORD ? + AmdAcpiWheaCmcSize DWORD ? + AmdDmiInfoPointer DWORD ? + + ;; Data used for communication between the AP and the BSP. + PUBLIC AmdRunCodeOnApDataPointer + PUBLIC AmdRunCodeOnApDataSize + PUBLIC AmdRunCodeOnApFunction + PUBLIC AmdRunCodeOnApStatus + AmdRunCodeOnApDataPointer DWORD ? + AmdRunCodeOnApDataSize DWORD ? + AmdRunCodeOnApFunction DWORD ? + AmdRunCodeOnApStatus DWORD ? + +CPU_DATASEG_END + + +END diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c new file mode 100644 index 0000000..3c5b5a0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c @@ -0,0 +1,419 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Hob Transfer functions. + * + * Contains code that copy Heap to temp memory or main memory. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "GeneralServices.h" +#include "cpuServices.h" +#include "cpuCacheInit.h" +#include "cpuFamilyTranslation.h" +#include "heapManager.h" +#include "cpuLateInit.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE LEGACY_PROC_HOBTRANSFER_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P U B L I C F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * CopyHeapToTempRamAtPost + * + * This function copies BSP heap content to RAM + * + * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. + * + * @retval AGESA_STATUS + * + */ +AGESA_STATUS +CopyHeapToTempRamAtPost ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 *BaseAddressInCache; + UINT8 *BaseAddressInTempMem; + UINT8 *Source; + UINT8 *Destination; + UINT8 AlignTo16ByteInCache; + UINT8 AlignTo16ByteInTempMem; + UINT8 Ignored; + UINT32 SizeOfNodeData; + UINT32 TotalSize; + UINT32 HeapRamFixMtrr; + UINT32 HeapRamVariableMtrr; + UINT32 HeapInCacheOffset; + UINT64 MsrData; + UINT64 VariableMtrrBase; + UINT64 VariableMtrrMask; + UINTN AmdHeapRamAddress; + AGESA_STATUS IgnoredStatus; + BUFFER_NODE *HeapInCache; + BUFFER_NODE *HeapInTempMem; + HEAP_MANAGER *HeapManagerInCache; + HEAP_MANAGER *HeapManagerInTempMem; + CACHE_INFO *CacheInfoPtr; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + AmdHeapRamAddress = (UINTN) UserOptions.CfgHeapDramAddress; + // + //If the user define address above 1M, Mem Init has already set + //whole available memory as WB cacheable. + // + if (AmdHeapRamAddress < 0x100000) { + // Region below 1MB + // Fixed MTTR region + // turn on modification bit + LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); + MsrData |= 0x80000; + LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); + + if (AmdHeapRamAddress >= 0xC0000) { + // + // 0xC0000 ~ 0xFFFFF + // + HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX4k_C0000 + (((AmdHeapRamAddress >> 16) & 0x3) * 2)); + MsrData = AMD_MTRR_FIX4K_UC_DRAM; + LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader); + LibAmdMsrWrite ((HeapRamFixMtrr + 1), &MsrData, StdHeader); + } else if (AmdHeapRamAddress >= 0x80000) { + // + // 0x80000~0xBFFFF + // + HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX16k_80000 + ((AmdHeapRamAddress >> 17) & 0x1)); + MsrData = AMD_MTRR_FIX16K_UC_DRAM; + LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader); + } else { + // + // 0x0 ~ 0x7FFFF + // + LibAmdMsrRead (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader); + MsrData = MsrData & (~(0xFF << (8 * ((AmdHeapRamAddress >> 16) & 0x7)))); + MsrData = MsrData | (AMD_MTRR_FIX64K_UC_DRAM << (8 * ((AmdHeapRamAddress >> 16) & 0x7))); + LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader); + } + + // Turn on MTTR enable bit and turn off modification bit + LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); + MsrData |= 0x40000; + MsrData &= 0xFFFFFFFFFFF7FFFF; + LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); + } else { + // Region above 1MB + // Variable MTTR region + // Get family specific cache Info + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader); + + // Find an empty MTRRphysBase/MTRRphysMask + for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE; + HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0; + HeapRamVariableMtrr--) { + LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader); + LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader); + if ((VariableMtrrBase == 0) && (VariableMtrrMask == 0)) { + break; + } + } + if (HeapRamVariableMtrr < AMD_MTRR_VARIABLE_BASE0) { + // All variable MTRR is used. + ASSERT (FALSE); + } + + // Set variable MTRR base and mask + // If the address ranges of two or more MTRRs overlap + // and if at least one of the memory types is UC, the UC memory type is used. + VariableMtrrBase = (UINT64) (AmdHeapRamAddress & CacheInfoPtr->HeapBaseMask); + VariableMtrrMask = CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK; + LibAmdMsrWrite (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader); + LibAmdMsrWrite ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader); + } + // Copying Heap content + if (IsBsp (StdHeader, &IgnoredStatus)) { + TotalSize = sizeof (HEAP_MANAGER); + SizeOfNodeData = 0; + AlignTo16ByteInTempMem = 0; + BaseAddressInCache = (UINT8 *) (UINT32)StdHeader->HeapBasePtr; + HeapManagerInCache = (HEAP_MANAGER *) BaseAddressInCache; + HeapInCacheOffset = HeapManagerInCache->FirstActiveBufferOffset; + HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset); + + BaseAddressInTempMem = (UINT8 *) (UINTN) UserOptions.CfgHeapDramAddress; + HeapManagerInTempMem = (HEAP_MANAGER *) BaseAddressInTempMem; + HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize); + + // copy heap from cache to temp memory. + // only heap with persist great than HEAP_LOCAL_CACHE will be copied. + // Note: Only copy heap with persist greater than HEAP_LOCAL_CACHE. + while (HeapInCacheOffset != AMD_HEAP_INVALID_HEAP_OFFSET) { + if (HeapInCache->Persist > HEAP_LOCAL_CACHE) { + AlignTo16ByteInCache = HeapInCache->PadSize; + AlignTo16ByteInTempMem = (UINT8) ((0x10 - (((UINTN) (VOID *) HeapInTempMem + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF); + SizeOfNodeData = HeapInCache->BufferSize - AlignTo16ByteInCache; + TotalSize = (UINT32) (TotalSize + sizeof (BUFFER_NODE) + SizeOfNodeData + AlignTo16ByteInTempMem); + Source = (UINT8 *) HeapInCache + sizeof (BUFFER_NODE) + AlignTo16ByteInCache; + Destination = (UINT8 *) HeapInTempMem + sizeof (BUFFER_NODE) + AlignTo16ByteInTempMem; + LibAmdMemCopy (HeapInTempMem, HeapInCache, sizeof (BUFFER_NODE), StdHeader); + LibAmdMemCopy (Destination, Source, SizeOfNodeData, StdHeader); + HeapInTempMem->OffsetOfNextNode = TotalSize; + HeapInTempMem->BufferSize = SizeOfNodeData + AlignTo16ByteInTempMem; + HeapInTempMem->PadSize = AlignTo16ByteInTempMem; + HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize); + } + HeapInCacheOffset = HeapInCache->OffsetOfNextNode; + HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset); + } + // initialize heap manager + if (TotalSize == sizeof (HEAP_MANAGER)) { + // heap is empty + HeapManagerInTempMem->UsedSize = sizeof (HEAP_MANAGER); + HeapManagerInTempMem->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET; + HeapManagerInTempMem->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER); + } else { + // heap is NOT empty + HeapManagerInTempMem->UsedSize = TotalSize; + HeapManagerInTempMem->FirstActiveBufferOffset = sizeof (HEAP_MANAGER); + HeapManagerInTempMem->FirstFreeSpaceOffset = TotalSize; + HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize - SizeOfNodeData - AlignTo16ByteInTempMem - sizeof (BUFFER_NODE)); + HeapInTempMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; + HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize); + } + // heap signature + HeapManagerInCache->Signature = 0x00000000; + HeapManagerInTempMem->Signature = HEAP_SIGNATURE_VALID; + // Free space node + HeapInTempMem->BufferSize = (UINT32) (AMD_HEAP_SIZE_PER_CORE - TotalSize); + HeapInTempMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; + } + return AGESA_SUCCESS; +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * CopyHeapToMainRamAtPost + * + * This function copies Temp Ram heap content to Main Ram + * + * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. + * + * @retval AGESA_STATUS + * + */ +AGESA_STATUS +CopyHeapToMainRamAtPost ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 *BaseAddressInTempMem; + UINT8 *BaseAddressInMainMem; + UINT8 *Source; + UINT8 *Destination; + UINT8 AlignTo16ByteInTempMem; + UINT8 AlignTo16ByteInMainMem; + UINT8 Ignored; + UINT32 SizeOfNodeData; + UINT32 TotalSize; + UINT32 HeapInTempMemOffset; + UINT32 HeapRamVariableMtrr; + UINT64 VariableMtrrBase; + UINT64 VariableMtrrMask; + AGESA_STATUS IgnoredStatus; + BUFFER_NODE *HeapInTempMem; + BUFFER_NODE *HeapInMainMem; + HEAP_MANAGER *HeapManagerInTempMem; + HEAP_MANAGER *HeapManagerInMainMem; + AGESA_BUFFER_PARAMS AgesaBuffer; + CACHE_INFO *CacheInfoPtr; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + if (IsBsp (StdHeader, &IgnoredStatus)) { + TotalSize = sizeof (HEAP_MANAGER); + SizeOfNodeData = 0; + AlignTo16ByteInMainMem = 0; + BaseAddressInTempMem = (UINT8 *)(UINT32) StdHeader->HeapBasePtr; + HeapManagerInTempMem = (HEAP_MANAGER *)(UINT32) StdHeader->HeapBasePtr; + HeapInTempMemOffset = HeapManagerInTempMem->FirstActiveBufferOffset; + HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset); + + AgesaBuffer.StdHeader = *StdHeader; + AgesaBuffer.BufferHandle = AMD_HEAP_IN_MAIN_MEMORY_HANDLE; + AgesaBuffer.BufferLength = AMD_HEAP_SIZE_PER_CORE; + if (AgesaAllocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) { + return AGESA_ERROR; + } + BaseAddressInMainMem = (UINT8 *) AgesaBuffer.BufferPointer; + HeapManagerInMainMem = (HEAP_MANAGER *) BaseAddressInMainMem; + HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize); + LibAmdMemFill (BaseAddressInMainMem, 0x00, AMD_HEAP_SIZE_PER_CORE, StdHeader); + // copy heap from temp memory to main memory. + // only heap with persist great than HEAP_TEMP_MEM will be copied. + // Note: Only copy heap buffers with persist greater than HEAP_TEMP_MEM. + while (HeapInTempMemOffset != AMD_HEAP_INVALID_HEAP_OFFSET) { + if (HeapInTempMem->Persist > HEAP_TEMP_MEM) { + AlignTo16ByteInTempMem = HeapInTempMem->PadSize; + AlignTo16ByteInMainMem = (UINT8) ((0x10 - (((UINTN) (VOID *) HeapInMainMem + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF); + SizeOfNodeData = HeapInTempMem->BufferSize - AlignTo16ByteInTempMem; + TotalSize = (UINT32) (TotalSize + sizeof (BUFFER_NODE) + SizeOfNodeData + AlignTo16ByteInMainMem); + Source = (UINT8 *) HeapInTempMem + sizeof (BUFFER_NODE) + AlignTo16ByteInTempMem; + Destination = (UINT8 *) HeapInMainMem + sizeof (BUFFER_NODE) + AlignTo16ByteInMainMem; + LibAmdMemCopy (HeapInMainMem, HeapInTempMem, sizeof (BUFFER_NODE), StdHeader); + LibAmdMemCopy (Destination, Source, SizeOfNodeData, StdHeader); + HeapInMainMem->OffsetOfNextNode = TotalSize; + HeapInMainMem->BufferSize = SizeOfNodeData + AlignTo16ByteInMainMem; + HeapInMainMem->PadSize = AlignTo16ByteInMainMem; + HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize); + } + HeapInTempMemOffset = HeapInTempMem->OffsetOfNextNode; + HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset); + } + // initialize heap manager + if (TotalSize == sizeof (HEAP_MANAGER)) { + // heap is empty + HeapManagerInMainMem->UsedSize = sizeof (HEAP_MANAGER); + HeapManagerInMainMem->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET; + HeapManagerInMainMem->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER); + } else { + // heap is NOT empty + HeapManagerInMainMem->UsedSize = TotalSize; + HeapManagerInMainMem->FirstActiveBufferOffset = sizeof (HEAP_MANAGER); + HeapManagerInMainMem->FirstFreeSpaceOffset = TotalSize; + HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize - SizeOfNodeData - AlignTo16ByteInMainMem - sizeof (BUFFER_NODE)); + HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; + HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize); + } + // heap signature + HeapManagerInTempMem->Signature = 0x00000000; + HeapManagerInMainMem->Signature = HEAP_SIGNATURE_VALID; + // Free space node + HeapInMainMem->BufferSize = AMD_HEAP_SIZE_PER_CORE - TotalSize; + HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; + } + // if address of heap in temp memory is above 1M, then we must used one variable MTRR. + if ( (UINTN) StdHeader->HeapBasePtr >= 0x100000) { + // Find out which variable MTRR was used in CopyHeapToTempRamAtPost. + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader); + for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE; + HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0; + HeapRamVariableMtrr--) { + LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader); + LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader); + if ((VariableMtrrBase == (UINT64) (UINTN) (StdHeader->HeapBasePtr & CacheInfoPtr->HeapBaseMask)) && + (VariableMtrrMask == (UINT64) (CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK))) { + break; + } + } + if (HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0) { + // Clear variable MTRR which set in CopyHeapToTempRamAtPost. + VariableMtrrBase = 0; + VariableMtrrMask = 0; + LibAmdMsrWrite (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader); + LibAmdMsrWrite ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader); + } + } + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/agesa.inc b/src/vendorcode/amd/agesa/f15tn/Legacy/agesa.inc new file mode 100644 index 0000000..14c15d2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Legacy/agesa.inc @@ -0,0 +1,3116 @@ +; **************************************************************************** +; * +; * @file +; * +; * Agesa structures and definitions +; * +; * Contains AMD AGESA core interface +; * +; * @xrefitem bom "File Content Label" "Release Content" +; * @e project: AGESA +; * @e sub-project: Include +; * @e $Revision: 64574 $ @e $Date: 2012-01-25 01:01:51 -0600 (Wed, 25 Jan 2012) $ +; +; **************************************************************************** +; * +; * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; * +; * AMD is granting you permission to use this software (the Materials) +; * pursuant to the terms and conditions of your Software License Agreement +; * with AMD. This header does *NOT* give you permission to use the Materials +; * or any rights under AMD's intellectual property. Your use of any portion +; * of these Materials shall constitute your acceptance of those terms and +; * conditions. If you do not agree to the terms and conditions of the Software +; * License Agreement, please do not use any portion of these Materials. +; * +; * CONFIDENTIALITY: The Materials and all other information, identified as +; * confidential and provided to you by AMD shall be kept confidential in +; * accordance with the terms and conditions of the Software License Agreement. +; * +; * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; * +; * AMD does not assume any responsibility for any errors which may appear in +; * the Materials or any other related information provided to you by AMD, or +; * result from use of the Materials or any related information. +; * +; * You agree that you will not reverse engineer or decompile the Materials. +; * +; * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; * further information, software, technical information, know-how, or show-how +; * available to you. Additionally, AMD retains the right to modify the +; * Materials at any time, without notice, and is not obligated to provide such +; * modified Materials to you. +; * +; * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; * subject to the restrictions as set forth in FAR 52.227-14 and +; * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; * Government constitutes acknowledgement of AMD's proprietary rights in them. +; * +; * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; * direct product thereof will be exported directly or indirectly, into any +; * country prohibited by the United States Export Administration Act and the +; * regulations thereunder, without the required authorization from the U.S. +; * government nor will be used for any purpose prohibited by the same. +; * +; ************************************************************************** + +INCLUDE amd.inc +UINT64 TEXTEQU <QWORD> +UINT32 TEXTEQU <DWORD> +UINT16 TEXTEQU <WORD> +UINT8 TEXTEQU <BYTE> +CHAR8 TEXTEQU <BYTE> +BOOLEAN TEXTEQU <BYTE> +POINTER TEXTEQU <DWORD> + + ; AGESA Types and Definitions + + + + ; AGESA BASIC CALLOUTS + AGESA_MEM_RELEASE EQU 00028000h + + ; AGESA ADVANCED CALLOUTS, Processor + AGESA_CHECK_UMA EQU 00028100h + AGESA_DO_RESET EQU 00028101h + AGESA_ALLOCATE_BUFFER EQU 00028102h + AGESA_DEALLOCATE_BUFFER EQU 00028103h + AGESA_LOCATE_BUFFER EQU 00028104h + AGESA_RUNFUNC_ONAP EQU 00028105h + + ; AGESA ADVANCED CALLOUTS, HyperTransport + + ; AGESA ADVANCED CALLOUTS, Memory + AGESA_READ_SPD EQU 00028140h + AGESA_HOOKBEFORE_DRAM_INIT EQU 00028141h + AGESA_HOOKBEFORE_DQS_TRAINING EQU 00028142h + AGESA_READ_SPD_RECOVERY EQU 00028143h + AGESA_HOOKBEFORE_EXIT_SELF_REF EQU 00028144h + AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY EQU 00028145h +;del AGESA_EXTERNAL_2D_TRAIN_VREF_CHANGE EQU 00028146h + + ; AGESA IDS CALLOUTS + AGESA_GET_IDS_INIT_DATA EQU 00028200h + + ; AGESA GNB CALLOUTS + AGESA_GNB_PCIE_SLOT_RESET EQU 00028301h + AGESA_GNB_GFX_GET_VBIOS_IMAGE EQU 00028302h + + ; AGESA FCH CALLOUTS + AGESA_FCH_OEM_CALLOUT EQU 00028401h + +; ------------------------------------------------------------------------ + + ; HyperTransport Interface + + + +; ----------------------------------------------------------------------------- + ; HT DEFINITIONS AND MACROS + +; ----------------------------------------------------------------------------- + + + ; Width equates for call backs + HT_WIDTH_8_BITS EQU 8 + HT_WIDTH_16_BITS EQU 16 + HT_WIDTH_4_BITS EQU 4 + HT_WIDTH_2_BITS EQU 2 + HT_WIDTH_NO_LIMIT EQU HT_WIDTH_16_BITS + + ; Frequency Limit equates for call backs which take a frequency supported mask. + HT_FREQUENCY_LIMIT_200M EQU 1 + HT_FREQUENCY_LIMIT_400M EQU 7 + HT_FREQUENCY_LIMIT_600M EQU 1Fh + HT_FREQUENCY_LIMIT_800M EQU 3Fh + HT_FREQUENCY_LIMIT_1000M EQU 7Fh + HT_FREQUENCY_LIMIT_HT1_ONLY EQU 7Fh + HT_FREQUENCY_LIMIT_1200M EQU 0FFh + HT_FREQUENCY_LIMIT_1400M EQU 1FFh + HT_FREQUENCY_LIMIT_1600M EQU 3FFh + HT_FREQUENCY_LIMIT_1800M EQU 7FFh + HT_FREQUENCY_LIMIT_2000M EQU 0FFFh + HT_FREQUENCY_LIMIT_2200M EQU 1FFFh + HT_FREQUENCY_LIMIT_2400M EQU 3FFFh + HT_FREQUENCY_LIMIT_2600M EQU 7FFFh + HT_FREQUENCY_LIMIT_2800M EQU 27FFFh + HT_FREQUENCY_LIMIT_3000M EQU 67FFFh + HT_FREQUENCY_LIMIT_3200M EQU 0E7FFFh + HT_FREQUENCY_LIMIT_3600M EQU 1E7FFFh + HT_FREQUENCY_LIMIT_MAX EQU HT_FREQUENCY_LIMIT_3600M + HT_FREQUENCY_NO_LIMIT EQU 0FFFFFFFFh + + ; Unit ID Clumping special values + HT_CLUMPING_DISABLE EQU 00000000h + HT_CLUMPING_NO_LIMIT EQU 0FFFFFFFFh + + HT_LIST_TERMINAL EQU 0FFh + HT_LIST_MATCH_ANY EQU 0FEh + HT_LIST_MATCH_INTERNAL_LINK EQU 0FDh + + ; Event Notify definitions + + ; Event definitions. + + ; Coherent subfunction events + HT_EVENT_COH_EVENTS EQU 10001000h + HT_EVENT_COH_NO_TOPOLOGY EQU 10011000h + HT_EVENT_COH_OBSOLETE000 EQU 10021000h + HT_EVENT_COH_PROCESSOR_TYPE_MIX EQU 10031000h + HT_EVENT_COH_NODE_DISCOVERED EQU 10041000h + HT_EVENT_COH_MPCAP_MISMATCH EQU 10051000h + + ; Non-coherent subfunction events + HT_EVENT_NCOH_EVENTS EQU 10002000h + HT_EVENT_NCOH_BUID_EXCEED EQU 10012000h + HT_EVENT_NCOH_OBSOLETE000 EQU 10022000h + HT_EVENT_NCOH_BUS_MAX_EXCEED EQU 10032000h + HT_EVENT_NCOH_CFG_MAP_EXCEED EQU 10042000h + HT_EVENT_NCOH_DEVICE_FAILED EQU 10052000h + HT_EVENT_NCOH_AUTO_DEPTH EQU 10062000h + + ; Optimization subfunction events + HT_EVENT_OPT_EVENTS EQU 10003000h + HT_EVENT_OPT_REQUIRED_CAP_RETRY EQU 10013000h + HT_EVENT_OPT_REQUIRED_CAP_GEN3 EQU 10023000h + HT_EVENT_OPT_UNUSED_LINKS EQU 10033000h + HT_EVENT_OPT_LINK_PAIR_EXCEED EQU 10043000h + + ; HW Fault events + HT_EVENT_HW_EVENTS EQU 10004000h + HT_EVENT_HW_SYNCFLOOD EQU 10014000h + HT_EVENT_HW_HTCRC EQU 10024000h + + ; The Recovery HT component uses 0x10005000 for events. + ; For consistency, we avoid that range here. + + HT_MAX_NC_BUIDS EQU 32 +; ---------------------------------------------------------------------------- + ; HT TYPEDEFS, STRUCTURES, ENUMS + +; ---------------------------------------------------------------------------- +MATCHED EQU 0 ; < The link matches the requested customization. +POWERED_OFF EQU 1 ; < Power the link off. +UNMATCHED EQU 2 ; < The link should be processed according to normal defaults. +MaxFinalLinkState EQU 3 ; < Not a final link state, use for limit checking. +FINAL_LINK_STATE TEXTEQU <DWORD> + + ; Swap a device from its current id to a new one. + +BUID_SWAP_ITEM STRUCT + FromId UINT8 ? ; < The device responding to FromId, + ToId UINT8 ? ; < will be moved to ToId. +BUID_SWAP_ITEM ENDS + + + ; Each Non-coherent chain may have a list of device swaps. After performing the swaps, + ; the final in order list of device ids is provided. (There can be more swaps than devices.) + ; The unused entries in both are filled with 0xFF. + +BUID_SWAP_LIST STRUCT + Swaps BUID_SWAP_ITEM (HT_MAX_NC_BUIDS) DUP ({}) ; < The BUID Swaps to perform + FinalIds UINT8 (HT_MAX_NC_BUIDS) DUP (?) ; < The ordered final BUIDs, resulting from the swaps +BUID_SWAP_LIST ENDS + + + ; Control Manual Initialization of Non-Coherent Chains + + ; This interface is checked every time a non-coherent chain is + ; processed. BUID assignment may be controlled explicitly on a + ; non-coherent chain. Provide a swap list. Swaps controls the + ; BUID assignment and FinalIds provides the device to device + ; Linking. Device orientation can be detected automatically, or + ; explicitly. See interface documentation for more details. + + ; If a manual swap list is not supplied, + ; automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially + ; based on each device's unit count. + +MANUAL_BUID_SWAP_LIST STRUCT + ; Match fields + Socket UINT8 ? ; < The Socket on which this chain is located + Link UINT8 ? ; < The Link on the host for this chain + ; Override fields + SwapList BUID_SWAP_LIST {} ; < The swap list +MANUAL_BUID_SWAP_LIST ENDS + + + ; Override options for DEVICE_CAP_OVERRIDE. + + ; Specify which override actions should be performed. For Checks, 1 means to check the item + ; and 0 means to skip the check. For the override options, 1 means to apply the override and + ; 0 means to ignore the override. + +DEVICE_CAP_OVERRIDE_OPTIONS STRUCT + IsCheckDevVenId UINT32 ? +; IN UINT32 IsCheckDevVenId:1; ; < Check Match on Device/Vendor id +; IN UINT32 IsCheckRevision:1; ; < Check Match on device Revision +; IN UINT32 IsOverrideWidthIn:1; ; < Override Width In +; IN UINT32 IsOverrideWidthOut:1; ; < Override Width Out +; IN UINT32 IsOverrideFreq:1; ; < Override Frequency +; IN UINT32 IsOverrideClumping:1; ; < Override Clumping +; IN UINT32 IsDoCallout:1; ; < Make the optional callout +DEVICE_CAP_OVERRIDE_OPTIONS ENDS + + ; Override capabilities of a device. + + ; This interface is checked once for every Link on every IO device. + ; Provide the width and frequency capability if needed for this device. + ; This is used along with device capabilities, the limit interfaces, and northbridge + ; limits to compute the default settings. The components of the device's PCI config + ; address are provided, so its settings can be consulted if need be. + ; The optional callout is a catch all. + +DEVICE_CAP_OVERRIDE STRUCT + ; Match fields + HostSocket UINT8 ? ; < The Socket on which this chain is located. + HostLink UINT8 ? ; < The Link on the host for this chain. + Depth UINT8 ? ; < The Depth in the I/O chain from the Host. + DevVenId UINT32 ? ; < The Device's PCI Vendor + Device ID (offset 0x00). + Revision UINT8 ? ; < The Device's PCI Revision field (offset 0x08). + Link UINT8 ? ; < The Device's Link number (0 or 1). + Options DEVICE_CAP_OVERRIDE_OPTIONS {} ; < The options for this device override. + ; Override fields + LinkWidthIn UINT8 ? ; < modify to change the Link Width In. + LinkWidthOut UINT8 ? ; < modify to change the Link Width Out. + FreqCap UINT32 ? ; < modify to change the Link's frequency capability. + Clumping UINT32 ? ; < modify to change Unit ID clumping support. + Callout CALLOUT_ENTRY ? ; < optional call for really complex cases, or NULL. +DEVICE_CAP_OVERRIDE ENDS + + ; Callout param struct for override capabilities of a device. + + ; If the optional callout is implemented this param struct is passed to it. + +DEVICE_CAP_CALLOUT_PARAMS STRUCT + StdHeader AMD_CONFIG_PARAMS {} ; < The header + ; Match fields + HostSocket UINT8 ? ; < The Socket on which this chain is located. + HostLink UINT8 ? ; < The Link on the host for this chain. + Depth UINT8 ? ; < The Depth in the I/O chain from the Host. + DevVenId UINT32 ? ; < The Device's PCI Vendor + Device ID (offset 0x00). + Revision UINT8 ? ; < The Device's PCI Revision field (offset 0x08). + Link UINT8 ? ; < The Device's Link number (0 or 1). + PciAddress PCI_ADDR {} ; < The Device's PCI Address. + ; Override fields + LinkWidthIn POINTER ? ; < modify to change the Link Width In. + LinkWidthOut POINTER ? ; < modify to change the Link Width Out. + FreqCap POINTER ? ; < modify to change the Link's frequency capability. + Clumping POINTER ? ; < modify to change Unit ID clumping support. +DEVICE_CAP_CALLOUT_PARAMS ENDS + + ; Limits for CPU to CPU Links. + + ; For each coherent connection this interface is checked once. + ; Provide the frequency and width if needed for this Link (usually based on board + ; restriction). This is used with CPU device capabilities and northbridge limits + ; to compute the default settings. + +CPU_TO_CPU_PCB_LIMITS STRUCT + ; Match fields + SocketA UINT8 ? ; < One Socket on which this Link is located + LinkA UINT8 ? ; < The Link on this Node + SocketB UINT8 ? ; < The other Socket on which this Link is located + LinkB UINT8 ? ; < The Link on that Node + ; Limit fields + ABLinkWidthLimit UINT8 ? ; < modify to change the Link Width A->B + BALinkWidthLimit UINT8 ? ; < modify to change the Link Width B-<A + PcbFreqCap UINT32 ? ; < modify to change the Link's frequency capability +CPU_TO_CPU_PCB_LIMITS ENDS + + ; Get limits for non-coherent Links. + + ; For each non-coherent connection this interface is checked once. + ; Provide the frequency and width if needed for this Link (usually based on board + ; restriction). This is used with device capabilities, device overrides, and northbridge limits + ; to compute the default settings. + +IO_PCB_LIMITS STRUCT + ; Match fields + HostSocket UINT8 ? ; < The Socket on which this Link is located + HostLink UINT8 ? ; < The Link about to be initialized + Depth UINT8 ? ; < The Depth in the I/O chain from the Host + ; Limit fields + DownstreamLinkWidthLimit UINT8 ? ; < modify to change the Link Width going away from processor + UpstreamLinkWidthLimit UINT8 ? ; < modify to change the Link Width moving toward processor + PcbFreqCap UINT32 ? ; < modify to change the Link's frequency capability +IO_PCB_LIMITS ENDS + + ; Manually control bus number assignment. + + ; This interface is checked every time a non-coherent chain is processed. + ; If a system can not use the auto Bus numbering feature for non-coherent chain bus + ; assignments, this interface can provide explicit control. For each chain, provide + ; the bus number range to use. + +OVERRIDE_BUS_NUMBERS STRUCT + ; Match fields + Socket UINT8 ? ; < The Socket on which this chain is located + Link UINT8 ? ; < The Link on the host for this chain + ; Override fields + SecBus UINT8 ? ; < Secondary Bus number for this non-coherent chain + SubBus UINT8 ? ; < Subordinate Bus number +OVERRIDE_BUS_NUMBERS ENDS + + + ; Ignore a Link. + + ; This interface is checked every time a coherent Link is found and then every + ; time a non-coherent Link from a CPU is found. + ; Any coherent or non-coherent Link from a CPU can be ignored and not used + ; for discovery or initialization. Useful for connection based systems. + ; (Note: not checked for IO device to IO Device Links.) + +IGNORE_LINK STRUCT + ; Match fields + Socket UINT8 ? ; < The Socket on which this Link is located + Link UINT8 ? ; < The Link about to be initialized + ; Customization fields + LinkState FINAL_LINK_STATE ? ; < The link may be left unitialized, or powered off. +IGNORE_LINK ENDS + + + ; Skip reganging of subLinks. + + ; This interface is checked whenever two subLinks are both connected to the same CPUs. + ; Normally, unganged sublinks between the same two CPUs are reganged. + ; Provide a matching structure to leave the Links unganged. + +SKIP_REGANG STRUCT + ; Match fields + SocketA UINT8 ? ; < One Socket on which this Link is located + LinkA UINT8 ? ; < The Link on this Node + SocketB UINT8 ? ; < The other Socket on which this Link is located + LinkB UINT8 ? ; < The Link on that Node + ; Customization fields + LinkState FINAL_LINK_STATE ? ; < The paired sublink may be active, or powered off. +SKIP_REGANG ENDS + + ; The System Socket layout, which sockets are physically connected. + + ; The hardware method for Socket naming is preferred. Use this software method only + ; if required. + +SYSTEM_PHYSICAL_SOCKET_MAP STRUCT + CurrentSocket UINT8 ? ; < The socket from which this connection originates. + CurrentLink UINT8 ? ; < The Link from the source socket connects to another socket. + TargetSocket UINT8 ? ; < The target socket which is connected on that link. +SYSTEM_PHYSICAL_SOCKET_MAP ENDS + +; ---------------------------------------------------------------------------- + + ; This is the input structure for AmdHtInitialize. + +AMD_HT_INTERFACE STRUCT + ; Basic level customization + AutoBusStart UINT8 ? ; < For automatic bus number assignment, starting bus number usually zero. + AutoBusMax UINT8 ? ; < For automatic bus number assignment, do not assign above max. + AutoBusIncrement UINT8 ? ; < For automatic bus number assignment, each chain gets this many busses. + + ; Advanced Level Customization + ManualBuidSwapList POINTER ? ; < Provide Manual Swap List, if any. + DeviceCapOverrideList POINTER ? ; < Provide Device Overrides, if any. + CpuToCpuPcbLimitsList POINTER ? ; < Provide CPU PCB Limits, if any. + IoPcbLimitsList POINTER ? ; < Provide IO PCB Limits, if any. + OverrideBusNumbersList POINTER ? ; < Provide manual Bus Number assignment, if any. + ; < Use either auto bus numbering or override bus + ; < numbers, not both. + + IgnoreLinkList POINTER ? ; < Provide links to ignore, if any. + SkipRegangList POINTER ? ; < Provide links to remain unganged, if any. + + ; Expert Level Customization + Topolist POINTER ? ; < Use this topology list in addition to the built in, if not NULL. + SystemPhysicalSocketMap POINTER ? + ; < The hardware socket naming method is preferred, + ; < If it can't be used, this provides a software method. +AMD_HT_INTERFACE ENDS + +; ----------------------------------------------------------------------------- + + ; HT Recovery Interface + + + +; ----------------------------------------------------------------------------- +; * HT Recovery DEFINITIONS AND MACROS +; * +; *----------------------------------------------------------------------------- +; + + ; BBHT subfunction events + HT_EVENT_BB_EVENTS EQU 10005000h + HT_EVENT_BB_BUID_EXCEED EQU 10015000h + HT_EVENT_BB_DEVICE_FAILED EQU 10055000h + HT_EVENT_BB_AUTO_DEPTH EQU 10065000h + +; ---------------------------------------------------------------------------- +; * HT Recovery TYPEDEFS, STRUCTURES, ENUMS +; * +; *---------------------------------------------------------------------------- +; + + + ; The Interface structure to Recovery HT. + +AMD_HT_RESET_INTERFACE STRUCT + ManualBuidSwapList POINTER ? ; < Option to manually control SB link init + Depth UINT32 ? ; < If auto init was used this is set to the depth of the chain, + ; < else, for manual init unmodified. +AMD_HT_RESET_INTERFACE ENDS + + +;----------------------------------------------------------------------------- +; FCH DEFINITIONS AND MACROS +; +;----------------------------------------------------------------------------- + +; Configuration values for SdConfig + SdDisable EQU 0 ; Disabled + SdAmda EQU 1 ; AMDA, set 24,18,16, default + SdDma EQU 2 ; DMA clear 24, 16, set 18 + SdPio EQU 3 ; PIO clear 24,18,16 +SD_MODE TEXTEQU <DWORD> + +; Configuration values for SdClockControl + Sd50MhzTraceCableLengthWithinSixInches EQU 4 ; 50Mhz, default + Sd40MhzTraceCableLengthSix2ElevenInches EQU 6 ; 40Mhz + Sd25MhzTraceCableLengthEleven2TwentyfourInches EQU 7 ; 25Mhz +SD_CLOCK_CONTROL TEXTEQU <DWORD> + +;del ; Configuration values for AzaliaController +;del AzAuto EQU 0 ; Auto - Detect Azalia controller automatically +;del AzDisable EQU 1 ; Diable - Disable Azalia controller +;del AzEnable EQU 2 ; Enable - Enable Azalia controller +HDA_CONFIG TEXTEQU <DWORD> + +; Configuration values for IrConfig + IrDisable EQU 0 ; Disable + IrRxTx0 EQU 1 ; Rx and Tx0 + IrRxTx1 EQU 2 ; Rx and Tx1 + IrRxTx0Tx1 EQU 3 ; Rx and both Tx0,Tx1 +IR_CONFIG TEXTEQU <DWORD> + +; Configuration values for SataClass + SataNativeIde EQU 0 ; Native IDE mode + SataRaid EQU 1 ; RAID mode + SataAhci EQU 2 ; AHCI mode + SataLegacyIde EQU 3 ; Legacy IDE mode + SataIde2Ahci EQU 4 ; IDE->AHCI mode + SataAhci7804 EQU 5 ; AHCI mode as 7804 ID (AMD driver) + SataIde2Ahci7804 EQU 6 ; IDE->AHCI mode as 7804 ID (AMD driver) +SATA_CLASS TEXTEQU <DWORD> + +; Configuration values for GppLinkConfig + PortA4 EQU 0 ; 4:0:0:0 + PortA2B2 EQU 2 ; 2:2:0:0 + PortA2B1C1 EQU 3 ; 2:1:1:0 + PortA1B1C1D1 EQU 4 ; 1:1:1:1 +GPP_LINKMODE TEXTEQU <DWORD> + +; Configuration values for FchPowerFail + AlwaysOff EQU 0 ; Always power off after power resumes + AlwaysOn EQU 1 ; Always power on after power resumes + UsePrevious EQU 3 ; Resume to same setting when power fails +POWER_FAIL TEXTEQU <DWORD> + +; Configuration values for SATA Link Speed + Gen1 EQU 1 ; SATA port GEN1 speed + Gen2 EQU 2 ; SATA port GEN2 speed + Gen3 EQU 3 ; SATA port GEN3 speed +SATA_SPEED TEXTEQU <DWORD> + +; Configuration values for GPIO function + Function0 EQU 0 ; GPIO Function 1 + Function1 EQU 1 ; GPIO Function 1 + Function2 EQU 2 ; GPIO Function 2 + Function3 EQU 3 ; GPIO Function 3 +GPIO_FUN TEXTEQU <DWORD> + +; Configuration values for GPIO_CFG + OwnedByEc EQU 1 ; This bit can only be written by EC + OwnedByHost EQU 2 ; This bit can only be written by host (BIOS) + Sticky EQU 4 ; If set, [6:3] are sticky + PullUpB EQU 8 ; 0: Pullup enable; 1: Pullup disabled + PullDown EQU 16 ; 0: Pulldown disabled; 1: Pulldown enable + GpioOutEnB EQU 32 ; 0: Output enable; 1: Output disable + GpioOut EQU 64 ; Output state when GpioOutEnB is 0 + GpioIn EQU 128 ; This bit is read only - current pin state +CFG_BYTE TEXTEQU <DWORD> + +; FCH GPIO CONTROL +GPIO_CONTROL STRUCT + GpioPin UINT8 ? ; Gpio Pin, valid range: 0-67, 128-150, 160-228 + PinFunction GPIO_FUN ? ; Multi-function selection + CfgByte CFG_BYTE ? ; GPIO Register value +GPIO_CONTROL ENDS + +; FCH SCI MAP CONTROL +SCI_MAP_CONTROL STRUCT + InputPin UINT8 ? ; Input Pin, valid range 0-63 + GpeMap UINT8 ? ; Gpe Map, valid range 0-31 +SCI_MAP_CONTROL ENDS + +; FCH SATA PHY CONTROL +SATA_PHY_CONTROL STRUCT + CommonPhy BOOLEAN ? ; Common PHY or not + Gen SATA_SPEED ? ; SATA speed + Port UINT8 ? ; Port number, valid range: 0-7 + PhyData UINT32 ? ; SATA PHY data, valid range: 0-0xFFFFFFFF +SATA_PHY_CONTROL ENDS + +; +; FCH Component Data Structure in InitReset stage +; +FCH_RESET_INTERFACE STRUCT + UmiGen2 BOOLEAN ? ; Enable Gen2 data rate of UMI + ; FALSE - Disable Gen2 + ; TRUE - Enable Gen2 + + SataEnable BOOLEAN ? ; SATA controller function + ; FALSE - SATA controller is disabled + ; TRUE - SATA controller is enabled + + IdeEnable BOOLEAN ? ; SATA IDE controller mode enabled/disabled + ; FALSE - IDE controller is disabled + ; TRUE - IDE controller is enabled + + GppEnable BOOLEAN ? ; Master switch of GPP function + ; FALSE - GPP disabled + ; TRUE - GPP enabled + + Xhci0Enable BOOLEAN ? ; XHCI0 controller function + ; FALSE - XHCI0 controller disabled + ; TRUE - XHCI0 controller enabled + + Xhci1Enable BOOLEAN ? ; XHCI1 controller function + ; FALSE - XHCI1 controller disabled + ; TRUE - XHCI1 controller enabled + +FCH_RESET_INTERFACE ENDS + + +; +; FCH Component Data Structure from InitEnv stage +; +FCH_INTERFACE STRUCT + SdConfig SD_MODE ? ; Secure Digital (SD) controller mode +;del AzaliaController HDA_CONFIG ? ; Azalia HD Audio Controller + IrConfig IR_CONFIG ? ; Infrared (IR) Configuration + UmiGen2 BOOLEAN ? ; Enable Gen2 data rate of UMI + ; FALSE - Disable Gen2 + ; TRUE - Enable Gen2 + SataClass SATA_CLASS ? ; SATA controller mode + SataEnable BOOLEAN ? ; SATA controller function + ; FALSE - SATA controller is disabled + ; TRUE - SATA controller is enabled + IdeEnable BOOLEAN ? ; SATA IDE controller mode enabled/disabled + ; FALSE - IDE controller is disabled + ; TRUE - IDE controller is enabled + SataIdeMode BOOLEAN ? ; Native mode of SATA IDE controller + ; FALSE - Legacy IDE mode + ; TRUE - Native IDE mode + Ohci1Enable BOOLEAN ? ; OHCI controller #1 Function + ; FALSE - OHCI1 is disabled + ; TRUE - OHCI1 is enabled + Ohci2Enable BOOLEAN ? ; OHCI controller #2 Function + ; FALSE - OHCI2 is disabled + ; TRUE - OHCI2 is enabled + Ohci3Enable BOOLEAN ? ; OHCI controller #3 Function + ; FALSE - OHCI3 is disabled + ; TRUE - OHCI3 is enabled + Ohci4Enable BOOLEAN ? ; OHCI controller #4 Function + ; FALSE - OHCI4 is disabled + ; TRUE - OHCI4 is enabled + XhciSwitch BOOLEAN ? ; XHCI controller Function + ; FALSE - XHCI is disabled + ; TRUE - XHCI is enabled + GppEnable BOOLEAN ? ; Master switch of GPP function + ; FALSE - GPP disabled + ; TRUE - GPP enabled + FchPowerFail POWER_FAIL ? ; FCH power failure option +FCH_INTERFACE ENDS + + +; --------------------------------------------------------------------------- +; CPU Feature related info +; --------------------------------------------------------------------------- + ; Build Configuration values for BLDCFG_PLATFORM_C1E_MODE + C1eModeDisabled EQU 0 ; < Disabled + C1eModeAuto EQU 1 ; < Auto mode enables the best C1e method for the + ; < currently installed processor + C1eModeHardware EQU 2 ; < Hardware method + C1eModeMsgBased EQU 3 ; < Message-based method + C1eModeSoftwareDeprecated EQU 4 ; < Deprecated software SMI method + C1eModeHardwareSoftwareDeprecated EQU 5 ; < Hardware or Deprecated software SMI method + MaxC1eMode EQU 6 ; < Not a valid value, used for verifying input +PLATFORM_C1E_MODES TEXTEQU <DWORD> + + ; Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE + CStateModeDisabled EQU 0 ; < Disabled + CStateModeC6 EQU 1 ; < C6 State + MaxCStateMode EQU 2 ; < Not a valid value, used for verifying input +PLATFORM_CSTATE_MODES TEXTEQU <DWORD> + + ; Build Configuration values for BLDCFG_PLATFORM_CPB_MODE + CpbModeAuto EQU 0 ; < Auto + CpbModeDisabled EQU 1 ; < Disabled + MaxCpbMode EQU 2 ; < Not a valid value, used for verifying input +PLATFORM_CPB_MODES TEXTEQU <DWORD> + + ; Build Configuration values for BLDCFG_LOW_POWER_PSTATE_FOR_PROCHOT_MODE + LOW_POWER_PSTATE_FOR_PROCHOT_AUTO EQU 0 ; < Auto + LOW_POWER_PSTATE_FOR_PROCHOT_DISABLE EQU 1 ; < Disabled + MAX_LOW_POWER_PSTATE_FOR_PROCHOT_MODE EQU 2 ; < Not a valid value, used for verifying input +PLATFORM_LOW_POWER_PSTATE_MODES TEXTEQU <DWORD> + +;---------------------------------------------------------------------------- +; GNB PCIe configuration info +;---------------------------------------------------------------------------- + +GNB_EVENT_INVALID_CONFIGURATION EQU 20010000h ; User configuration invalid +GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION EQU 20010001h ; Requested lane allocation for PCIe port can not be supported +GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION EQU 20010002h ; Requested incorrect PCIe port device address +GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION EQU 20010003h ; Incorrect parameter in DDI link configuration +GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION EQU 20010004h ; Invalid with for PCIe port or DDI link +GNB_EVENT_INVALID_LANES_CONFIGURATION EQU 20010005h ; Lane double subscribe lanes +GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION EQU 20010006h ; Requested lane allocation for DDI link(s) can not be supported +GNB_EVENT_LINK_TRAINING_FAIL EQU 20020000h ; PCIe Link training fail +GNB_EVENT_BROKEN_LANE_RECOVERY EQU 20030000h ; Broken lane workaround applied to recover link training +GNB_EVENT_GEN2_SUPPORT_RECOVERY EQU 20040000h ; Scale back to GEN1 to recover link training + +DESCRIPTOR_TERMINATE_LIST EQU 80000000h +DESCRIPTOR_IGNORE EQU 40000000h + +; PCIe link initialization + +EndpointDetect EQU 0 ;Detect endpoint presence +EndpointNotPresent EQU 1 ;Endpoint not present (or connected). Used in case there is alternative way to determine + ;if device present on board or in slot. For example GPIO can be used to determine device presence. +PCIE_ENDPOINT_STATUS TEXTEQU <DWORD> + +PCIe_PORT_MISC_CONTROL STRUCT + LinkComplianceMode UINT8 ? + ;IN UINT8 LinkComplianceMode :1; ;< Force port into compliance mode (device will not be trained, port output compliance pattern) +PCIe_PORT_MISC_CONTROL ENDS + +APIC_DEVICE_INFO STRUCT + GroupMap UINT8 ? ; < Group mapping for slot or endpoint device (connected to PCIE port) interrupts . + ; 0 - IGNORE THIS STRUCTURE and use recommended settings + ; 1 - mapped to Grp 0 (Interrupts 0..3 of IO APIC redirection table) + ; 2 - mapped to Grp 1 (Interrupts 4..7 of IO APIC redirection table) + ; ... + ; 8 - mapped to Grp 7 (Interrupts 28..31 of IO APIC redirection table) + Swizzle UINT8 ? ;< Swizzle interrupt in the Group. + ; 0 - ABCD + ; 1 - BCDA + ; 2 - CDAB + ; 3 - DABC + BridgeInt UINT8 ? ; < IOAPIC redirection table entry for PCIE bridge interrupt + ; 0 - Entry 0 of IO APIC redirection table + ; 1 - Entry 1 of IO APIC redirection table + ; ... + ; 31 - Entry 31 of IO APIC redirection table +APIC_DEVICE_INFO ENDS + +PCIe_PORT_DATA STRUCT + PortPresent UINT8 ? ; < Enable PCIe port for initialization. + ChannelType UINT8 ? ; < Channel type. + ; 0 - "lowLoss", + ; 1 - "highLoss", + ; 2 - "mob0db", + ; 3 - "mob3db", + ; 4 - "extnd6db" + ; 5 - "extnd8db" + ; + DeviceNumber UINT8 ? ; < Device number for port. Available device numbers may very on different CPUs. + FunctionNumber UINT8 ? ; < Reserved for future use + LinkSpeedCapability UINT8 ? ; < Advertised Gen Capability + ; 0 - Maximum supported by silicon + ; 1 - Gen1 + ; 2 - Gen2 + ; 3 - Gen3 + ; + LinkAspm UINT8 ? ; < ASPM control. (see OemPcieLinkAspm for additional option to control ASPM) + ; 0 - Disabled + ; 1 - L0s only + ; 2 - L1 only + ; 2 - L0s and L1 + ; + LinkHotplug UINT8 ? ; < Hotplug control. + ; 0 - Disabled + ; 1 - Basic + ; 2 - Server + ; 3 - Enhanced + ; + ResetId UINT8 ? ; < Arbitrary number greater than 0 assigned by platform firmware for GPIO + ; identification which control reset for given port. + ; Each port with unique GPIO should have unique ResetId assigned. + ; All ports use same GPIO to control reset should have same ResetId assigned. + ; see AgesaPcieSlotResetControl + ; + MiscControls PCIe_PORT_MISC_CONTROL {} ; < Misc extended controls + ApicDeviceInfo APIC_DEVICE_INFO {} ; < IOAPIC device programming info + EndpointStatus PCIE_ENDPOINT_STATUS ? ; < PCIe endpoint status +PCIe_PORT_DATA ENDS + +;DDI channel lane mapping + +CHANNEL_MAPPING STRUCT ; + Lane0 UINT8 ? ; + ;IN UINT8 Lane0 :2; ; + ;IN UINT8 Lane1 :2; ///< Lane 1 mapping (see "Lane 0 mapping") + ;IN UINT8 Lane2 :2; ///< Lane 2 mapping (see "Lane 0 mapping") + ;IN UINT8 Lane3 :2; ///< Lane 3 mapping (see "Lane 0 mapping") +CHANNEL_MAPPING ENDS ; + +CONN_CHANNEL_MAPPING UNION + ChannelMappingValue UINT8 ? ; < Raw lane mapping + ChannelMapping CHANNEL_MAPPING {} ; +CONN_CHANNEL_MAPPING ENDS ; + +; DDI Configuration +PCIe_DDI_DATA STRUCT + ConnectorType UINT8 ? ; < Display Connector Type + ; 0 - DP + ; 1 - eDP + ; 2 - Single Link DVI + ; 3 - Dual Link DVI + ; 4 - HDMI + ; 5 - Travis DP-to-VGA + ; 6 - Travis DP-to-LVDS + ; 7 - Hudson-2 NutMeg DP-to-VGA + ; 8 - Single Link DVI-I + ; 9 - CRT (VGA) + ; 10 - LVDS + ; 11 - VBIOS auto detect connector type + AuxIndex UINT8 ? ; < Indicates which AUX or DDC Line is used + ; 0 - AUX1 + ; 1 - AUX2 + ; 2 - AUX3 + ; 3 - AUX4 + ; 4 - AUX5 + ; 5 - AUX6 + ; + HdpIndex UINT8 ? ; < Indicates which HDP pin is used + ; 0 - HDP1 + ; 1 - HDP2 + ; 2 - HDP3 + ; 3 - HDP4 + ; 4 - HDP5 + ; 5 - HDP6 + Mapping CONN_CHANNEL_MAPPING (2) DUP ({}) ;< Set specific mapping of lanes to connector pins + ;Mapping[0] define mapping for group of 4 lanes starting at PCIe_ENGINE_DATA.StartLane + ;Mapping[1] define mapping for group of 4 lanes ending at PCIe_ENGINE_DATA.EndLane (only + ;applicable for Dual DDI link) + ;if Mapping[x] set to 0 than default mapping assumed + LanePnInversionMask UINT8 ? ; < Specifies whether to invert the state of P and N for each lane. Each bit represents a PCIe lane on the DDI port + ; 0 - Do not invert (default) + ; 1 - Invert P and N on this lane + Flags UINT8 ? ; < Capabilities flags + ; Flags bit[0] DDI_DATA_FLAGS_DP1_1_ONLY Selects downgrade PHY link to DP1.1 + ; Flags bit[7:1] Reserved + ; +PCIe_DDI_DATA ENDS + + +; Engine Configuration +PCIe_ENGINE_DATA STRUCT + EngineType UINT8 ? ; < Engine type + ; 0 - Ignore engine configuration + ; 1 - PCIe port + ; 2 - DDI + StartLane UINT16 ? ; < Start lane number (in reversed configuration StartLane > EndLane). + EndLane UINT16 ? ; < End lane number (in reversed configuration StartLane > EndLane). +PCIe_ENGINE_DATA ENDS + +; PCIe port descriptor +PCIe_PORT_DESCRIPTOR STRUCT + Flags UINT32 ? ; < Descriptor flags + ; Bit31 - last descriptor in complex + EngineData PCIe_ENGINE_DATA {} ; < Engine data + Port PCIe_PORT_DATA {} ; < PCIe port specific configuration info +PCIe_PORT_DESCRIPTOR ENDS + +; DDI descriptor +PCIe_DDI_DESCRIPTOR STRUCT + Flags UINT32 ? ; < Descriptor flags + EngineData PCIe_ENGINE_DATA {} ; < Engine data + Ddi PCIe_DDI_DATA {} ; < DDI port specific configuration info +PCIe_DDI_DESCRIPTOR ENDS + +; Slot Reset Info +PCIe_SLOT_RESET_INFO STRUCT + StdHeader AMD_CONFIG_PARAMS {} ; < AGESA Standard Header + ResetId UINT8 ? ; < Slot reset ID as specified in PCIe_PORT_DESCRIPTOR + ResetControl UINT8 ? ; < Reset control as defined by PCIE_RESET_CONTROL +PCIe_SLOT_RESET_INFO ENDS + +GFX_VBIOS_IMAGE_FLAG_SPECIAL_POST EQU 001h + +; VBIOS image info +GFX_VBIOS_IMAGE_INFO STRUCT + StdHeader AMD_CONFIG_PARAMS {} ; < Standard configuration header + ImagePtr POINTER ? ; < Pointer to VBIOS image + GfxPciAddress PCI_ADDR {} ; < PCI address of integrated graphics controller + Flags UINT32 ? ; < BIT[0] - special repost requred +GFX_VBIOS_IMAGE_INFO ENDS + +; PCIe Complex descriptor +PCIe_COMPLEX_DESCRIPTOR STRUCT + Flags UINT32 ? ; < Descriptor flags + ; Bit31 - last descriptor in topology + ; + ; + SocketId UINT32 ? ; < Socket Id + PciePortList POINTER ? ;< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). + DdiLinkList POINTER ? ;< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). + Reserved POINTER ? ;< Reserved for future use +PCIe_COMPLEX_DESCRIPTOR ENDS + + AssertSlotReset EQU 0 + DeassertSlotReset EQU 1 +PCIE_RESET_CONTROL TEXTEQU <DWORD> + + PcieUnusedEngine EQU 0 + PciePortEngine EQU 1 + PcieDdiEngine EQU 2 + MaxPcieEngine EQU 3 ; < Not a valid value, used for verifying input +PCIE_ENGINE_TYPE TEXTEQU <DWORD> + + PcieGenMaxSupported EQU 0 + PcieGen1 EQU 1 + PcieGen2 EQU 2 + PcieGen3 EQU 3 + MaxPcieGen EQU 4 ; < Not a valid value, used for verifying input +PCIE_LINK_SPEED_CAP TEXTEQU <DWORD> + + PsppDisabled EQU 0 + PsppPerformance EQU 1 + PsppBalanceHigh EQU 2 + PsppBalanceLow EQU 3 + PsppPowerSaving EQU 4 + MaxPspp EQU 5 ; < Not a valid value, used for verifying input +PCIE_PSPP_POLICY TEXTEQU <DWORD> + + ConnectorTypeDP EQU 0 + ConnectorTypeEDP EQU 1 + ConnectorTypeSingleLinkDVI EQU 2 + ConnectorTypeDualLinkDVI EQU 3 + ConnectorTypeHDMI EQU 4 + ConnectorTypeTravisDpToVga EQU 5 + ConnectorTypeTravisDpToLvds EQU 6 + ConnectorTypeNutmegDpToVga EQU 7 + ConnectorTypeSingleLinkDviI EQU 8 + ConnectorTypeCrt EQU 9 + ConnectorTypeLvds EQU 10 + ConnectorTypeEDPToLvds EQU 11 + ConnectorTypeEDPToRealtecLvds EQU 12 + ConnectorTypeAutoDetect EQU 13 + MaxConnectorType EQU 14 ; < Not a valid value, used for verifying input +PCIE_CONNECTOR_TYPE TEXTEQU <DWORD> + + ChannelTypeLowLoss EQU 0 + ChannelTypeHighLoss EQU 1 + ChannelTypeMob0db EQU 2 + ChannelTypeMob3db EQU 3 + ChannelTypeExt6db EQU 4 + ChannelTypeExt8db EQU 5 + MaxChannelType EQU 6 ; < Not a valid value, used for verifying input +PCIE_CHANNEL_TYPE TEXTEQU <DWORD> + + AspmDisabled EQU 0 + AspmL0s EQU 1 + AspmL1 EQU 2 + AspmL0sL1 EQU 3 + MaxAspm EQU 4 ; < Not a valid value, used for verifying input +PCIE_ASPM_TYPE TEXTEQU <DWORD> + + HotplugDisabled EQU 0 + HotplugBasic EQU 1 + HotplugServer EQU 2 + HotplugEnhanced EQU 3 + HotplugInboard EQU 4 + MaxHotplug EQU 5 ; < Not a valid value, used for verifying input +PCIE_HOTPLUG_TYPE TEXTEQU <DWORD> + + PortDisabled EQU 0 + PortEnabled EQU 1 +PCIE_PORT_ENABLE TEXTEQU <DWORD> + + Aux1 EQU 0 + Aux2 EQU 1 + Aux3 EQU 2 + Aux4 EQU 3 + Aux5 EQU 4 + Aux6 EQU 5 + MaxAux EQU 6 ; < Not a valid value, used for verifying input +PCIE_AUX_TYPE TEXTEQU <DWORD> + + Hdp1 EQU 0 + Hdp2 EQU 1 + Hdp3 EQU 2 + Hdp4 EQU 3 + Hdp5 EQU 4 + Hdp6 EQU 5 + MaxHdp EQU 6 ; < Not a valid value, used for verifying input +PCIE_HDP_TYPE TEXTEQU <DWORD> + +;PCIe_DDI_DATA.Flags definitions +DDI_DATA_FLAGS_DP1_1_ONLY EQU 01h ; < BIT[0] Selects downgrade PHY link to DP1.1 + +;IOMMU requestor ID +IOMMU_REQUESTOR_ID STRUCT + Bus UINT16 ? ; <[15:8] - Bus number, [7:3] - Device number, [2:0] - Function number +IOMMU_REQUESTOR_ID ENDS + +;IVMD exclusion range descriptor +IOMMU_EXCLUSION_RANGE_DESCRIPTOR STRUCT + Flags UINT32 ? ; Descriptor flags + ; @li @b Flags[31] - Terminate descriptor array. + ; @li @b Flags[30] - Ignore descriptor. + RequestorIdStart IOMMU_REQUESTOR_ID {} ; Requestor ID start + RequestorIdEnd IOMMU_REQUESTOR_ID {} ; Requestor ID end (use same as start for single ID) + RangeBaseAddress UINT64 ? ; Phisical base address of exclusion range + RangeLength UINT64 ? ; Length of exclusion range in bytes +IOMMU_EXCLUSION_RANGE_DESCRIPTOR ENDS + +;---------------------------------------------------------------------------- +; GNB configuration info +;---------------------------------------------------------------------------- +; + +; LVDS Misc Control Field +LVDS_MISC_CONTROL_FIELD STRUCT + FpdiMode UINT8 ? + ;IN UINT8 FpdiMode:1; + ;IN UINT8 DlChSwap:1; + ;IN UINT8 VsyncActiveLow:1; + ;IN UINT8 HsyncActiveLow:1; + ;IN UINT8 BLONActiveLow:1; + ;IN UINT8 TravisLvdsVolOverwriteEn:1; + ;IN UINT8 Reserved:2; +LVDS_MISC_CONTROL_FIELD ENDS + +; LVDS Misc Control +LVDS_MISC_CONTROL UNION + Field LVDS_MISC_CONTROL_FIELD {} + Value UINT8 ? +LVDS_MISC_CONTROL ENDS + +; Display Misc Control Field +DISPLAY_MISC_CONTROL_FIELD STRUCT + Reserved1 UINT8 ? + ;IN UINT8 Reserved1:3; + ;IN UINT8 VbiosFastBootEn:1; + ;IN UINT8 Reserved2:4; +DISPLAY_MISC_CONTROL_FIELD ENDS + +; Display Misc Control +DISPLAY_MISC_CONTROL UNION + Field DISPLAY_MISC_CONTROL_FIELD {} + Value UINT8 ? +DISPLAY_MISC_CONTROL ENDS + +; Configuration settings for GNB. +GNB_POST_CONFIGURATION STRUCT + IgpuEnableDisablePolicy UINT8 ? ; This item defines the iGPU Enable/Disable policy + ; @li 0 = Auto - use existing default - + ; @li 1 = Disable iGPU if any PCIe/PCI graphics card present +GNB_POST_CONFIGURATION ENDS + + IGPU_DISABLE_AUTO EQU 0 ; Auto setting - disable iGPU if ANY PCI graphics or non-AMD PCIe graphics + IGPU_DISABLE_ANY_PCIE EQU 1 ; Disable iGPU if any PCI or PCIE graphics card is present + + +; Configuration settings for GNB. +GNB_ENV_CONFIGURATION STRUCT + Gnb3dStereoPinIndex UINT8 ? ;< 3D Stereo Pin ID. + ; @li 0 = Stereo 3D is disabled (default). + ; @li 1 = Use processor pin HPD1. + ; @li 2 = Use processor pin HPD2 + ; @li 3 = Use processor pin HPD3 + ; @li 4 = Use processor pin HPD4 + ; @li 5 = Use processor pin HPD5 + ; @li 6 = Use processor pin HPD6 + IommuSupport BOOLEAN ? ; IOMMU support. + ; TRUE = Disable and hide IOMMU device. + ; FLASE = Initialize IOMMU subsystem. Generate ACPI IVRS table. + LvdsSpreadSpectrum UINT16 ? ; Spread spectrum value in 0.01 % + LvdsSpreadSpectrumRate UINT16 ? ; Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz + LvdsPowerOnSeqDigonToDe UINT8 ? ; This item configures panel initialization timing. + LvdsPowerOnSeqDeToVaryBl UINT8 ? ; This item configures panel initialization timing. + LvdsPowerOnSeqDeToDigon UINT8 ? ; This item configures panel initialization timing. + LvdsPowerOnSeqVaryBlToDe UINT8 ? ; This item configures panel initialization timing. + LvdsPowerOnSeqOnToOffDelay UINT8 ? ; This item configures panel initialization timing. + LvdsPowerOnSeqVaryBlToBlon UINT8 ? ; This item configures panel initialization timing. + LvdsPowerOnSeqBlonToVaryBl UINT8 ? ; This item configures panel initialization timing. + LvdsMaxPixelClockFreq UINT16 ? ; This item configures the maximum pixel clock frequency supported. + LcdBitDepthControlValue UINT32 ? ; This item configures the LCD bit depth control settings. + Lvds24bbpPanelMode UINT8 ? ; This item configures the LVDS 24 BBP mode. + LvdsMiscControl LVDS_MISC_CONTROL {} ; This item configures LVDS swap/Hsync/Vsync/BLON + PcieRefClkSpreadSpectrum UINT16 ? ; Spread spectrum value in 0.01 % + GnbRemoteDisplaySupport BOOLEAN ? ; This item enables Wireless Display Support + LvdsMiscVoltAdjustment UINT8 ? ; Travis register LVDS_CTRL_4 to adjust LVDS output voltage + DisplayMiscControl DISPLAY_MISC_CONTROL {} ; This item configures display misc control +GNB_ENV_CONFIGURATION ENDS + +; Configuration settings for GNB. +GNB_MID_CONFIGURATION STRUCT + iGpuVgaMode UINT8 ? ; < VGA resourses decoding configuration for iGPU + ; < @li 0 = iGPU decode all VGA resourses (must be promary VGA adapter) + ; < @li 1 = iGPU will not decode any VGA resourses (must be secondary graphics adapter) +GNB_MID_CONFIGURATION ENDS + +; GNB configuration info +GNB_CONFIGURATION STRUCT + PcieComplexList POINTER ? ; Pointer to array of PCIe_COMPLEX_DESCRIPTOR structures describe PCIe topology on each processor package or NULL. + ; Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST + ; + ; + ; + ; Topology organization definition assume PCIe_COMPLEX_DESCRIPTOR defined first following + ; PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR for given PCIe_COMPLEX_DESCRIPTOR + ; defined in arbitrary sequence: + ; Example of topology definition for single socket system: + ; PlatfromTopology LABEL DWORD + ; + ; Port0_2 PCIe_PORT_DESCRIPTOR <>; + ; Port0_3 PCIe_PORT_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST> ; + ; ... + ; Ddi0_A PCIe_DDI_DESCRIPTOR <>; + ; Ddi0_B PCIe_DDI_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST,>; + ; ... + ; Cpu0 PCIe_COMPLEX_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST, 0, Port0_2, Ddi0_A> + ; + ; + PsppPolicy UINT8 ? ;< PSPP (PCIe Speed Power Policy) + ; @li @b 0 - Disabled + ; @li @b 1 - Performance + ; @li @b 2 - Balance-High + ; @li @b 3 - Balance-Low + ; @li @b 4 - Power Saving + ; +GNB_CONFIGURATION ENDS + +; --------------------------------------------------------------------------- + +; MEMORY-SPECIFIC DATA STRUCTURES + +; --------------------------------------------------------------------------- + + + ; AGESA MAXIMIUM VALUES + + ; These Max values are used to define array sizes and associated loop + ; counts in the code. They reflect the maximum values that AGESA + ; currently supports and does not necessarily reflect the hardware + ; capabilities of configuration. + + + MAX_SOCKETS_SUPPORTED EQU 8 ; < Max number of sockets in system + MAX_CHANNELS_PER_SOCKET EQU 4 ; < Max Channels per sockets + MAX_DIMMS_PER_CHANNEL EQU 4 ; < Max DIMMs on a memory channel (independent of platform) + NUMBER_OF_DELAY_TABLES EQU 9 ; < Number of tables defined in CH_DEF_STRUCT. + ; < Eg: UINT16 *RcvEnDlys; + ; < UINT8 *WrDqsDlys; + ; < UINT8 *RdDqsDlys; + ; < UINT8 *WrDatDlys; + ; < UINT8 *RdDqsMinDlys; + ; < UINT8 *RdDqsMaxDlys; + ; < UINT8 *WrDatMinDlys; + ; < UINT8 *WrDatMaxDlys; + NUMBER_OF_FAILURE_MASK_TABLES EQU 1 ; < Number of failure mask tables + MAX_PLATFORM_TYPES EQU 16 ; < Platform types per system + + MCT_TRNG_KEEPOUT_START EQU 00004000h ; < base [39:8] + MCT_TRNG_KEEPOUT_END EQU 00007FFFh ; < base [39:8] + + UMA_ATTRIBUTE_INTERLEAVE EQU 80000000h ; < Uma Region is interleaved + UMA_ATTRIBUTE_ON_DCT0 EQU 40000000h ; < UMA resides on memory that belongs to DCT0 + UMA_ATTRIBUTE_ON_DCT1 EQU 20000000h ; < UMA resides on memory that belongs to DCT1 + + PSO_TABLE TEXTEQU <UINT8>; < Platform Configuration Table + + ; AGESA DEFINITIONS + + ; Many of these are derived from the platform and hardware specific definitions + + ; EccSymbolSize override value + ECCSYMBOLSIZE_USE_BKDG EQU 0 ; < Use BKDG Recommended Value + ECCSYMBOLSIZE_FORCE_X4 EQU 4 ; < Force to x4 + ECCSYMBOLSIZE_FORCE_X8 EQU 8 ; < Force to x8 + ; CPU Package Type + PT_L1 EQU 0 ; < L1 Package type + PT_M2 EQU 1 ; < AM Package type + PT_S1 EQU 2 ; < S1 Package type + + ; Structures use to pass system Logical CPU-ID +CPU_LOGICAL_ID STRUCT + Family UINT64 ? ; < Indicates logical ID Family + Revision UINT64 ? ; < Indicates logical ID Family +CPU_LOGICAL_ID ENDS + + ; Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE + + AMD_PLATFORM_SERVER EQU 8000h ; < Server + AMD_PLATFORM_DESKTOP EQU 10000h ; < Desktop + AMD_PLATFORM_MOBILE EQU 20000h ; < Mobile +AMD_PLATFORM_TYPE TEXTEQU <DWORD> + + ; Dram technology type + + DDR2_TECHNOLOGY EQU 0 ; < DDR2 technology + DDR3_TECHNOLOGY EQU 1 ; < DDR3 technology +TECHNOLOGY_TYPE TEXTEQU <DWORD> + + ; Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT + + DDR400_FREQUENCY EQU 200 ; < DDR 400 + DDR533_FREQUENCY EQU 266 ; < DDR 533 + DDR667_FREQUENCY EQU 333 ; < DDR 667 + DDR800_FREQUENCY EQU 400 ; < DDR 800 + DDR1066_FREQUENCY EQU 533 ; < DDR 1066 + DDR1333_FREQUENCY EQU 667 ; < DDR 1333 + DDR1600_FREQUENCY EQU 800 ; < DDR 1600 + DDR1866_FREQUENCY EQU 933 ; < DDR 1866 + DDR2100_FREQUENCY EQU 1050 ; < DDR 2100 + DDR2133_FREQUENCY EQU 1066 ; < DDR 2133 + DDR2400_FREQUENCY EQU 1200 ; < DDR 2400 + UNSUPPORTED_DDR_FREQUENCY EQU 1201 ; < Highest limit of DDR frequency +MEMORY_BUS_SPEED TEXTEQU <DWORD> + + ; Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE + + QUADRANK_REGISTERED EQU 0 + QUADRANK_UNBUFFERED EQU 1 +QUANDRANK_TYPE TEXTEQU <DWORD> + + ; Build Configuration values for BLDCFG_TIMING_MODE_SELECT + + TIMING_MODE_AUTO EQU 0 ; < Use best rate possible + TIMING_MODE_LIMITED EQU 1 ; < Set user top limit + TIMING_MODE_SPECIFIC EQU 2 ; < Set user specified speed +USER_MEMORY_TIMING_MODE TEXTEQU <DWORD> + + ; Build Configuration values for BLDCFG_POWER_DOWN_MODE + + POWER_DOWN_BY_CHANNEL EQU 0 + POWER_DOWN_BY_CHIP_SELECT EQU 1 + POWER_DOWN_AUTO EQU 2 +POWER_DOWN_MODE TEXTEQU <DWORD> + + ; Low voltage support + + VOLT_INITIAL EQU 0 ; < Initial value for VDDIO + VOLT1_5 EQU 1 ; < 1.5 Volt + VOLT1_35 EQU 2 ; < 1.35 Volt + VOLT1_25 EQU 3 ; < 1.25 Volt + VOLT_UNSUPPORTED EQU 0FFh ; < No common voltage found +DIMM_VOLTAGE TEXTEQU <DWORD> + + ; UMA Mode + + UMA_NONE EQU 0 ; < UMA None + UMA_SPECIFIED EQU 1 ; < UMA Specified + UMA_AUTO EQU 2 ; < UMA Auto +UMA_MODE TEXTEQU <DWORD> + + ; Force Training Mode + +;del FORCE_TRAIN_1D EQU 0 ; < 1D Training only + FORCE_TRAIN_2D EQU 1 ; < 2D Training only + FORCE_TRAIN_AUTO EQU 2 ; < Auto - 1D or 2D depending on configuration +FORCE_TRAIN_MODE TEXTEQU <DWORD> + +; The possible DRAM prefetch mode settings. + DRAM_PREFETCHER_AUTO EQU 0 ; Use the recommended setting for the processor. In most cases, the recommended setting is enabled. + DISABLE_DRAM_PREFETCH_FOR_IO EQU 1 ; Disable DRAM prefetching for I/O requests only. + DISABLE_DRAM_PREFETCH_FOR_CPU EQU 2 ; Disable DRAM prefetching for requests from processor cores only. + DISABLE_DRAM_PREFETCHER EQU 3 ; Disable DRAM prefetching. + MAX_DRAM_FREFETCH_MODE EQU 4 ; Not a DRAM prefetch mode, use for limit checking. +DRAM_PREFETCH_MODE TEXTEQU <DWORD> + + ; Build Configuration values for BLDCFG_UMA_ALIGNMENT + + NO_UMA_ALIGNED EQU 00FFFFFFh + UMA_4MB_ALIGNED EQU 00FFFFC0h + UMA_128MB_ALIGNED EQU 00FFF800h + UMA_256MB_ALIGNED EQU 00FFF000h + UMA_512MB_ALIGNED EQU 00FFE000h +UMA_ALIGNMENT TEXTEQU <DWORD> + ; =============================================================================== + ; Global MCT Configuration Status Word (GStatus) + ; =============================================================================== + + GsbMTRRshort EQU 0 ; < Ran out of MTRRs while mapping memory + GsbAllECCDimms EQU 1 ; < All banks of all Nodes are ECC capable + GsbDramECCDis EQU 2 ; < Dram ECC requested but not enabled. + GsbSoftHole EQU 3 ; < A Node Base gap was created + GsbHWHole EQU 4 ; < A HW dram remap was created + GsbNodeIntlv EQU 5 ; < Node Memory interleaving was enabled + GsbSpIntRemapHole EQU 6 ; < Special condition for Node Interleave and HW remapping + GsbEnDIMMSpareNW EQU 7 ; < Indicates that DIMM Spare can be used without a warm reset + + GsbEOL EQU 8 ; < End of list +GLOBAL_STATUS_FIELD TEXTEQU <DWORD> + +; =============================================================================== + ; Local Error Status (DIE_STRUCT.ErrStatus[31:0]) +; =============================================================================== + + EsbNoDimms EQU 0 ; < No DIMMs + EsbSpdChkSum EQU 1 ; < SPD Checksum fail + EsbDimmMismatchM EQU 2 ; < dimm module type(buffer) mismatch + EsbDimmMismatchT EQU 3 ; < dimm CL/T mismatch + EsbDimmMismatchO EQU 4 ; < dimm organization mismatch (128-bit) + EsbNoTrcTrfc EQU 5 ; < SPD missing Trc or Trfc info + EsbNoCycTime EQU 6 ; < SPD missing byte 23 or 25 + EsbBkIntDis EQU 7 ; < Bank interleave requested but not enabled + EsbDramECCDis EQU 8 ; < Dram ECC requested but not enabled + EsbSpareDis EQU 9 ; < Online spare requested but not enabled + EsbMinimumMode EQU 10 ; < Running in Minimum Mode + EsbNoRcvrEn EQU 11 ; < No DQS Receiver Enable pass window found + EsbSmallRcvr EQU 12 ; < DQS Rcvr En pass window too small (far right of dynamic range) + EsbNoDqsPos EQU 13 ; < No DQS-DQ passing positions + EsbSmallDqs EQU 14 ; < DQS-DQ passing window too small + EsbDCBKScrubDis EQU 15 ; < DCache scrub requested but not enabled + + EsbEMPNotSupported EQU 16 ; < Processor is not capable for EMP. + EsbEMPConflict EQU 17 ; < EMP requested but cannot be enabled since + ; < channel interleaving, bank interleaving, or bank swizzle is enabled. + EsbEMPDis EQU 18 ; < EMP requested but cannot be enabled since + ; < memory size of each DCT is not a power of two. + + EsbEOL EQU 19 ; < End of list +ERROR_STATUS_FIELD TEXTEQU <DWORD> + +; =============================================================================== + ; Local Configuration Status (DIE_STRUCT.Status[31:0]) +; =============================================================================== + + SbRegistered EQU 0 ; < All DIMMs are Registered + SbEccDimms EQU 1 ; < All banks ECC capable + SbParDimms EQU 2 ; < All banks Addr/CMD Parity capable + SbDiagClks EQU 3 ; < Jedec ALL slots clock enable diag mode + Sb128bitmode EQU 4 ; < DCT in 128-bit mode operation + Sb64MuxedMode EQU 5 ; < DCT in 64-bit mux'ed mode. + Sb2TMode EQU 6 ; < 2T CMD timing mode is enabled. + SbSWNodeHole EQU 7 ; < Remapping of Node Base on this Node to create a gap. + SbHWHole EQU 8 ; < Memory Hole created on this Node using HW remapping. + SbOver400Mhz EQU 9 ; < DCT freq greater than or equal to 400MHz flag + SbDQSPosPass2 EQU 10 ; < Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz + SbDQSRcvLimit EQU 11 ; < Used for DQSRcvEnTrain to know we have reached the upper bound. + SbExtConfig EQU 12 ; < Indicate the default setting for extended PCI configuration support + SbLrdimms EQU 13 ; < All DIMMs are LRDIMMs + SbEOL EQU 14 ; < End of list +LOCAL_STATUS_FIELD TEXTEQU <DWORD> + + +; < CPU MSR Register definitions ------------------------------------------ + SYS_CFG EQU 0C0010010h + TOP_MEM EQU 0C001001Ah + TOP_MEM2 EQU 0C001001Dh + HWCR EQU 0C0010015h + NB_CFG EQU 0C001001Fh + + FS_BASE EQU 0C0000100h + IORR0_BASE EQU 0C0010016h + IORR0_MASK EQU 0C0010017h + BU_CFG EQU 0C0011023h + BU_CFG2 EQU 0C001102Ah + COFVID_STAT EQU 0C0010071h + TSC EQU 10h + +; =============================================================================== + ; SPD Data for each DIMM +; =============================================================================== +SPD_DEF_STRUCT STRUCT + DimmPresent BOOLEAN ? ; < Indicates that the DIMM is present and Data is valid + Data UINT8 (256) DUP (?) ; < Buffer for 256 Bytes of SPD data from DIMM +SPD_DEF_STRUCT ENDS + +; =============================================================================== + ; Channel Definition Structure + ; This data structure defines entries that are specific to the channel initialization +; =============================================================================== +CH_DEF_STRUCT STRUCT + ChannelID UINT8 ? ; < Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D) + TechType TECHNOLOGY_TYPE ? ; < Technology type of this channel + ChDimmPresent UINT8 ? ; < For each bit n 0..7, 1 = DIMM n is present. + ; < DIMM# Select Signal + ; < 0 MA0_CS_L[0, 1] + ; < 1 MB0_CS_L[0, 1] + ; < 2 MA1_CS_L[0, 1] + ; < 3 MB1_CS_L[0, 1] + ; < 4 MA2_CS_L[0, 1] + ; < 5 MB2_CS_L[0, 1] + ; < 6 MA3_CS_L[0, 1] + ; < 7 MB3_CS_L[0, 1] + + DCTPtr POINTER ? ; < Pointer to the DCT data of this channel. + MCTPtr POINTER ? ; < Pointer to the node data of this channel. + SpdPtr POINTER ? ; < Pointer to the SPD data for this channel. (Setup by NB Constructor) + DimmSpdPtr POINTER (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Array of pointers to + ; < SPD Data for each Dimm. (Setup by Tech Block Constructor) + ChDimmValid UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is valid and is/will be configured where 4..7 are reserved. + RegDimmPresent UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is a registered DIMM where 4..7 are reserved. + LrDimmPresent UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved. + SODimmPresent UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is a SO-DIMM where 4..7 are reserved. + Loads UINT8 ? ; < Number of devices loading bus + Dimms UINT8 ? ; < Number of DIMMs loading Channel + Ranks UINT8 ? ; < Number of ranks loading Channel DATA + SlowMode BOOLEAN ? ; < 1T or 2T CMD mode (slow access mode) + ; < FALSE = 1T + ; < TRUE = 2T + ; < The following pointers will be pointed to dynamically allocated buffers. + ; < Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below. + ; < Example: If DIMM and Byte based training, then + ; < XX is a value in Hex + ; < BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE + ; < Row1 - Logical DIMM0 XX XX XX XX XX XX XX XX XX + ; < Row2 - Logical DIMM1 XX XX XX XX XX XX XX XX XX + RcvEnDlys POINTER ? ; < DQS Receiver Enable Delays + WrDqsDlys POINTER ? ; < Write DQS delays (only valid for DDR3) + RdDqsDlys POINTER ? ; < Read Dqs delays + WrDatDlys POINTER ? ; < Write Data delays + RdDqs2dDlys POINTER ? ; < 2d Read DQS data + RdDqsMinDlys POINTER ? ; < Minimum Window for Read DQS + RdDqsMaxDlys POINTER ? ; < Maximum Window for Read DQS + WrDatMinDlys POINTER ? ; < Minimum Window for Write data + WrDatMaxDlys POINTER ? ; < Maximum Window for Write data + RcvEnDlysMemPs1 POINTER ? ; < DQS Receiver Enable Delays for Memory Pstate 1 + WrDqsDlysMemPs1 POINTER ? ; < Write DQS delays for Memory Pstate 1 (only valid for DDR3) + RdDqsDlysMemPs1 POINTER ? ; < Read Dqs delays for Memory Pstate 1 + WrDatDlysMemPs1 POINTER ? ; < Write Data delays for Memory Pstate 1 + RdDqs2dDlysMemPs1 POINTER ? ; < 2d Read DQS data for Memory Pstate 1 + RdDqsMinDlysMemPs1 POINTER ? ; < Minimum Window for Read DQS for Memory Pstate 1 + RdDqsMaxDlysMemPs1 POINTER ? ; < Maximum Window for Read DQS for Memory Pstate 1 + WrDatMinDlysMemPs1 POINTER ? ; < Minimum Window for Write data for Memory Pstate 1 + WrDatMaxDlysMemPs1 POINTER ? ; < Maximum Window for Write data for Memory Pstate 1 + RowCount UINT8 ? ; < Number of rows of the allocated buffer. + ColumnCount UINT8 ? ; < Number of columns of the allocated buffer. + + FailingBitMask POINTER ? ; < Table of masks to Track Failing bits + FailingBitMaskMemPs1 POINTER ? ; < Table of masks to Track Failing bits for Memory Pstate 1 + DctOdcCtl UINT32 ? ; < Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h) + DctAddrTmg UINT32 ? ; < Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h) + PhyRODTCSLow UINT32 ? ; < Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h) + PhyRODTCSHigh UINT32 ? ; < Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h) + PhyWODTCSLow UINT32 ? ; < Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h) + PhyWODTCSHigh UINT32 ? ; < Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183) + PhyWLODT UINT8 (4) DUP (?) ; < Write Levelization ODT Pattern for Dimm 0-3 or CS 0-7(see BKDG FN2:Offset 9Ch, index 0x8[11:8]) + DctEccDqsLike UINT16 ? ; < DCT DQS ECC UINT8 like... + DctEccDqsScale UINT8 ? ; < DCT DQS ECC UINT8 scale + PtrPatternBufA UINT16 ? ; < Ptr on stack to aligned DQS testing pattern + PtrPatternBufB UINT16 ? ; < Ptr on stack to aligned DQS testing pattern + ByteLane UINT8 ? ; < Current UINT8 Lane (0..7) + Direction UINT8 ? ; < Current DQS-DQ training write direction (0=read, 1=write) + Pattern UINT8 ? ; < Current pattern + DqsDelay UINT8 ? ; < Current DQS delay value + HostBiosSrvc1 UINT16 ? ; < UINT16 sized general purpose field for use by host BIOS. Scratch space. + HostBiosSrvc2 UINT32 ? ; < UINT32 sized general purpose field for use by host BIOS. Scratch space. + DctMaxRdLat UINT16 (4) DUP (?) ; < Max Read Latency (ns) for the DCT + ; < DctMaxRdLat [i] is for NBPstate i DIMMValidCh UINT8 ? ; < DIMM# in CH + DIMMValidCh UINT8 ? ; < DIMM# in CH + MaxCh UINT8 ? ; < Max number of CH in system + Dct UINT8 ? ; < Dct pointer + WrDatGrossH UINT8 ? ; < Write Data Gross delay high value + DqsRcvEnGrossL UINT8 ? ; < DQS Receive Enable Gross Delay low + + TrwtWB UINT8 ? ; < Non-SPD timing value for TrwtWB + CurrRcvrDctADelay UINT8 ? ; < for keep current RcvrEnDly + T1000 UINT16 ? ; < get the T1000 figure (cycle time (ns) * 1K) + DqsRcvEnPass UINT8 ? ; < for TrainRcvrEn UINT8 lane pass flag + DqsRcvEnSaved UINT8 ? ; < for TrainRcvrEn UINT8 lane saved flag + SeedPass1Remainder UINT8 ? ; < for Phy assisted DQS receiver enable training + + ClToNbFlag UINT8 ? ; < is used to restore ClLinesToNbDis bit after memory + NodeSysBase UINT32 ? ; < for channel interleave usage + RefRawCard UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Array of rawcards detected + CtrlWrd02 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 2 values per DIMM + CtrlWrd03 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 3 values per DIMM + CtrlWrd04 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 4 values per DIMM + CtrlWrd05 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 5 values per DIMM + CtrlWrd08 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 8 values per DIMM + + CsPresentDCT UINT16 ? ; < For each bit n 0..7, 1 = Chip-select n is present + DimmMirrorPresent UINT8 ? ; < For each bit n 0..7, 1 = DIMM n is OnDimmMirror capable + DimmSpdCse UINT8 ? ; < For each bit n 0..7, 1 = DIMM n SPD checksum error + DimmExclude UINT8 ? ; < For each bit n 0..7, 1 = DIMM n gets excluded + DimmYr06 UINT8 ? ; < Bitmap indicating which Dimms have a manufacturer's year code <= 2006 + DimmWk2406 UINT8 ? ; < Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June) + DimmPlPresent UINT8 ? ; < Bitmap indicating that Planar (1) or Stacked (0) Dimms are present. + DimmQrPresent UINT8 ? ; < QuadRank DIMM present? + DimmDrPresent UINT8 ? ; < Bitmap indicating that Dual Rank Dimms are present + DimmSRPresent UINT8 ? ; < Bitmap indicating that Single Rank Dimms are present + Dimmx4Present UINT8 ? ; < For each bit n 0..3, 1 = DIMM n contains x4 data devices. where 4..7 are reserved. + Dimmx8Present UINT8 ? ; < For each bit n 0..3, 1 = DIMM n contains x8 data devices. where 4..7 are reserved. + Dimmx16Present UINT8 ? ; < For each bit n 0..3, 1 = DIMM n contains x16 data devices. where 4..7 are reserved. + LrdimmPhysicalRanks UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Number of Physical Ranks for LRDIMMs + LrDimmLogicalRanks UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Number of LRDIMM Logical ranks in this configuration + LrDimmRankMult UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Rank Multipication factor per dimm. + DimmNibbleAccess UINT8 ? ; < For each bit n 0..3, 1 = DIMM n will use nibble signaling. Where 4..7 are reserved. + MemClkDisMap POINTER ? ; < This pointer will be set to point to an array that describes + ; < the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will + ; < base on this array to disable unused MemClk to save power. + ; < + ; < The array must have 8 entries. Each entry, which associates with + ; < one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to. + ; < Example: + ; < BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package + ; < is like below: + ; < Bit AM3/S1g3 pin name + ; < 0 M[B,A]_CLK_H/L[0] + ; < 1 M[B,A]_CLK_H/L[1] + ; < 2 M[B,A]_CLK_H/L[2] + ; < 3 M[B,A]_CLK_H/L[3] + ; < 4 M[B,A]_CLK_H/L[4] + ; < 5 M[B,A]_CLK_H/L[5] + ; < 6 M[B,A]_CLK_H/L[6] + ; < 7 M[B,A]_CLK_H/L[7] + ; < And platform has the following routing: + ; < CS0 M[B,A]_CLK_H/L[4] + ; < CS1 M[B,A]_CLK_H/L[2] + ; < CS2 M[B,A]_CLK_H/L[3] + ; < CS3 M[B,A]_CLK_H/L[5] + ; < Then MemClkDisMap should be pointed to the following array: + ; < CLK_2 CLK_3 CLK_4 CLK_5 + ; < 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00 + ; < Each entry of the array is the bitmask of 8 chip selects. + + CKETriMap POINTER ? ; < This pointer will be set to point to an array that describes + ; < the routing of CKE pins to the DIMMs' ranks. + ; < The array must have 2 entries. Each entry, which associates with + ; < one CKE pin, is a bitmap of 8 CS that that CKE is routed to. + ; < AGESA will base on this array to disable unused CKE pins to save power. + + ODTTriMap POINTER ? ; < This pointer will be set to point to an array that describes + ; < the routing of ODT pins to the DIMMs' ranks. + ; < The array must have 4 entries. Each entry, which associates with + ; < one ODT pin, is a bitmap of 8 CS that that ODT is routed to. + ; < AGESA will base on this array to disable unused ODT pins to save power. + + ChipSelTriMap POINTER ? ; < This pointer will be set to point to an array that describes + ; < the routing of chip select pins to the DIMMs' ranks. + ; < The array must have 8 entries. Each entry is a bitmap of 8 CS. + ; < AGESA will base on this array to disable unused Chip select pins to save power. + + ExtendTmp BOOLEAN ? ; < If extended temperature is supported on all dimms on a channel. + + MaxVref UINT8 ? ; < Maximum Vref Value for channel + + Reserved UINT8 (100) DUP (?) ; < Reserved +CH_DEF_STRUCT ENDS + +; =============================================================================== + ; DCT Channel Timing Parameters + ; This data structure sets timings that are specific to the channel +; =============================================================================== +CH_TIMING_STRUCT STRUCT + DctDimmValid UINT16 ? ; < For each bit n 0..3, 1=DIMM n is valid and is/will be configured where 4..7 are reserved. + DimmMirrorPresent UINT16 ? ; < For each bit n 0..3, 1=DIMM n is OnDimmMirror capable where 4..7 are reserved. + DimmSpdCse UINT16 ? ; < For each bit n 0..3, 1=DIMM n SPD checksum error where 4..7 are reserved. + DimmExclude UINT16 ? ; < For each bit n 0..3, 1 = DIMM n gets excluded because of no common voltage is found + CsPresent UINT16 ? ; < For each bit n 0..7, 1=Chip-select n is present + CsEnabled UINT16 ? ; < For each bit n 0..7, 1=Chip-select n is enabled + CsTestFail UINT16 ? ; < For each bit n 0..7, 1=Chip-select n is present but disabled + CsTrainFail UINT16 ? ; < Bitmap showing which chipselects failed training + DIMM1KPage UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains 1K page devices. where 4..7 are reserved. + DimmQrPresent UINT16 ? ; < QuadRank DIMM present? + DimmDrPresent UINT16 ? ; < Bitmap indicating that Dual Rank Dimms are present + DimmSRPresent UINT8 ? ; < Bitmap indicating that Single Rank Dimms are present + Dimmx4Present UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains x4 data devices. where 4..7 are reserved. + Dimmx8Present UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains x8 data devices. where 4..7 are reserved. + Dimmx16Present UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains x16 data devices. where 4..7 are reserved. + + DIMMTrcd UINT16 ? ; < Minimax Trcd*40 (ns) of DIMMs + DIMMTrp UINT16 ? ; < Minimax Trp*40 (ns) of DIMMs + DIMMTrtp UINT16 ? ; < Minimax Trtp*40 (ns) of DIMMs + DIMMTras UINT16 ? ; < Minimax Tras*40 (ns) of DIMMs + DIMMTrc UINT16 ? ; < Minimax Trc*40 (ns) of DIMMs + DIMMTwr UINT16 ? ; < Minimax Twr*40 (ns) of DIMMs + DIMMTrrd UINT16 ? ; < Minimax Trrd*40 (ns) of DIMMs + DIMMTwtr UINT16 ? ; < Minimax Twtr*40 (ns) of DIMMs + DIMMTfaw UINT16 ? ; < Minimax Tfaw*40 (ns) of DIMMs + TargetSpeed UINT16 ? ; < Target DRAM bus speed in MHz + Speed UINT16 ? ; < DRAM bus speed in MHz + ; < 400 (MHz) + ; < 533 (MHz) + ; < 667 (MHz) + ; < 800 (MHz) + ; < and so on... + CasL UINT8 ? ; < CAS latency DCT setting (busclocks) + Trcd UINT8 ? ; < DCT Trcd (busclocks) + Trp UINT8 ? ; < DCT Trp (busclocks) + Trtp UINT8 ? ; < DCT Trtp (busclocks) + Tras UINT8 ? ; < DCT Tras (busclocks) + Trc UINT8 ? ; < DCT Trc (busclocks) + Twr UINT8 ? ; < DCT Twr (busclocks) + Trrd UINT8 ? ; < DCT Trrd (busclocks) + Twtr UINT8 ? ; < DCT Twtr (busclocks) + Tfaw UINT8 ? ; < DCT Tfaw (busclocks) + Trfc0 UINT8 ? ; < DCT Logical DIMM0 Trfc + ; < 0 = 75ns (for 256Mb devs) + ; < 1 = 105ns (for 512Mb devs) + ; < 2 = 127.5ns (for 1Gb devs) + ; < 3 = 195ns (for 2Gb devs) + ; < 4 = 327.5ns (for 4Gb devs) + Trfc1 UINT8 ? ; < DCT Logical DIMM1 Trfc (see Trfc0 for format) + Trfc2 UINT8 ? ; < DCT Logical DIMM2 Trfc (see Trfc0 for format) + Trfc3 UINT8 ? ; < DCT Logical DIMM3 Trfc (see Trfc0 for format) + DctMemSize UINT32 ? ; < Base[47:16], total DRAM size controlled by this DCT. + SlowMode BOOLEAN ? ; < 1T or 2T CMD mode (slow access mode) + ; < FALSE = 1T + ; < TRUE = 2T + TrwtTO UINT8 ? ; < DCT TrwtTO (busclocks) + Twrrd UINT8 ? ; < DCT Twrrd (busclocks) + Twrwr UINT8 ? ; < DCT Twrwr (busclocks) + Trdrd UINT8 ? ; < DCT Trdrd (busclocks) + TrwtWB UINT8 ? ; < DCT TrwtWB (busclocks) + TrdrdSD UINT8 ? ; < DCT TrdrdSD (busclocks) + TwrwrSD UINT8 ? ; < DCT TwrwrSD (busclocks) + TwrrdSD UINT8 ? ; < DCT TwrrdSD (busclocks) + MaxRdLat UINT16 ? ; < Max Read Latency + WrDatGrossH UINT8 ? ; < Temporary variables must be removed + DqsRcvEnGrossL UINT8 ? ; < Temporary variables must be removed +CH_TIMING_STRUCT ENDS + +; =============================================================================== + ; Data for each DCT + ; This data structure defines data used to configure each DRAM controller +; =============================================================================== +DCT_STRUCT STRUCT + Dct UINT8 ? ; < Current Dct + Timings CH_TIMING_STRUCT {} ; < Channel Timing structure + TimingsMemPs1 POINTER ? ; < Pointed to channel timing structure for Memory Pstate 1 + ChData POINTER ? ; < Pointed to a dynamically allocated array of Channel structures + ChannelCount UINT8 ? ; < Number of channel per this DCT + BkIntDis BOOLEAN ? ; < Bank interleave requested but not enabled on current DCT +DCT_STRUCT ENDS + + +; =============================================================================== + ; Data Structure defining each Die + ; This data structure contains information that is used to configure each Die +; =============================================================================== +DIE_STRUCT STRUCT + + ; Advanced: + + NodeId UINT8 ? ; < Node ID of current controller + SocketId UINT8 ? ; < Socket ID of this Die + DieId UINT8 ? ; < ID of this die relative to the socket + PciAddr PCI_ADDR {} ; < Pci bus and device number of this controller. + ErrCode AGESA_STATUS ? ; < Current error condition of Node + ; < 0x0 = AGESA_SUCCESS + ; < 0x1 = AGESA_UNSUPPORTED + ; < 0x2 = AGESA_BOUNDS_CHK + ; < 0x3 = AGESA_ALERT + ; < 0x4 = AGESA_WARNING + ; < 0x5 = AGESA_ERROR + ; < 0x6 = AGESA_CRITICAL + ; < 0x7 = AGESA_FATAL + ; < + ErrStatus BOOLEAN (EsbEOL) DUP (?) ; < Error Status bit Field + Status BOOLEAN (SbEOL) DUP (?) ; < Status bit Field + NodeMemSize UINT32 ? ; < Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node. + NodeSysBase UINT32 ? ; < Base[47:16] (system address) DRAM base address of this Node. + NodeHoleBase UINT32 ? ; < If not zero, Base[47:16] (system address) of dram hole for HW remapping. Dram hole exists on this Node + NodeSysLimit UINT32 ? ; < Base[47:16] (system address) DRAM limit address of this Node. + DimmPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is present. + ; < DIMM# Select Signal + ; < 0 MA0_CS_L[0, 1] + ; < 1 MB0_CS_L[0, 1] + ; < 2 MA1_CS_L[0, 1] + ; < 3 MB1_CS_L[0, 1] + ; < 4 MA2_CS_L[0, 1] + ; < 5 MB2_CS_L[0, 1] + ; < 6 MA3_CS_L[0, 1] + ; < 7 MB3_CS_L[0, 1] + DimmValid UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is valid and is / will be configured + RegDimmPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is registered DIMM + LrDimmPresent UINT32 ? ; < For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved. + DimmEccPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is ECC capable. + DimmParPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable. + DimmTrainFail UINT16 ? ; < Bitmap showing which dimms failed training + ChannelTrainFail UINT16 ? ; < Bitmap showing the channel information about failed Chip Selects + ; < 0 in any bit field indicates Channel 0 + ; < 1 in any bit field indicates Channel 1 + Dct UINT8 ? ; < Need to be removed + ; < DCT pointer + GangedMode BOOLEAN ? ; < Ganged mode + ; < 0 = disabled + ; < 1 = enabled + LogicalCpuid CPU_LOGICAL_ID {} ; < The logical CPUID of the node + HostBiosSrvc1 UINT16 ? ; < UINT16 sized general purpose field for use by host BIOS. Scratch space. + HostBiosSrvc2 UINT32 ? ; < UINT32 sized general purpose field for use by host BIOS. Scratch space. + MLoad UINT8 ? ; < Need to be removed + ; < Number of devices loading MAA bus + MaxAsyncLat UINT8 ? ; < Legacy wrapper + ChbD3Rcvrdly UINT8 ? ; < Legacy wrapper + ChaMaxRdLat UINT16 ? ; < Max Read Latency (ns) for DCT 0 + ChbD3BcRcvrdly UINT8 ? ; < CHB DIMM 3 Check UINT8 Receiver Enable Delay + + DctData POINTER ? ; < Pointed to a dynamically allocated array of DCT_STRUCTs + DctCount UINT8 ? ; < Number of DCTs per this Die + Reserved UINT8 (16) DUP (?) ; < Reserved +DIE_STRUCT ENDS + +; ********************************************************************* +; * S3 Support structure +; ********************************************************************* + ; AmdInitResume, AmdS3LateRestore, and AmdS3Save param structure +AMD_S3_PARAMS STRUCT + Signature UINT32 ? ; < "ASTR" for AMD Suspend-To-RAM + Version UINT16 ? ; < S3 Params version number + Flags UINT32 ? ; < Indicates operation + NvStorage POINTER ? ; < Pointer to memory critical save state data + NvStorageSize UINT32 ? ; < Size in bytes of the NvStorage region + VolatileStorage POINTER ? ; < Pointer to remaining AMD save state data + VolatileStorageSize UINT32 ? ; < Size in bytes of the VolatileStorage region +AMD_S3_PARAMS ENDS + +; =============================================================================== + ; MEM_PARAMETER_STRUCT + ; This data structure is used to pass wrapper parameters to the memory configuration code +; =============================================================================== +MEM_PARAMETER_STRUCT STRUCT + + ; Basic (Return parameters) + ; (This section contains the outbound parameters from the memory init code) + + GStatus BOOLEAN (GsbEOL) DUP (?) ; < Global Status bitfield + HoleBase UINT32 ? ; < If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping. + Sub4GCacheTop UINT32 ? ; < If not zero, the 32-bit top of cacheable memory. + Sub1THoleBase UINT32 ? ; < If not zero Base[47:16] (system address) of sub 1TB dram hole. + SysLimit UINT32 ? ; < Limit[47:16] (system address) + DDR3Voltage DIMM_VOLTAGE ? ; < Find support voltage and send back to platform BIOS. +;del ExternalVrefValue UINT8 ? ; < Target reference voltage for external Vref for 2D training + MemData POINTER ? ; < Pointer to MEM_DATA_STRUCT + ; Advanced (Optional parameters) + ; Optional (all defaults values will be initialized by the + ; 'AmdMemInitDataStructDef' based on AMD defaults. It is up + ; to the IBV/OEM to change the defaults after initialization + ; but prior to the main entry to the memory code): + + ; Memory Map/Mgt. + + BottomIo UINT16 ? ; < Bottom of 32-bit IO space (8-bits) + ; < NV_BOTTOM_IO[7:0]=Addr[31:24] + MemHoleRemapping BOOLEAN ? ; < Memory Hole Remapping (1-bit) + ; < FALSE = disable + ; < TRUE = enable + LimitMemoryToBelow1Tb BOOLEAN ? ; < Limit memory address space to below 1 TB + ; < FALSE = disable + ; < TRUE = enable + ; Dram Timing + + UserTimingMode USER_MEMORY_TIMING_MODE ? ; < User Memclock Mode + + MemClockValue MEMORY_BUS_SPEED ? ; < Memory Clock Value + + ; Dram Configuration + + EnableBankIntlv BOOLEAN ? ; < Dram Bank (chip-select) Interleaving (1-bit) + ; < FALSE =disable (AMD default) + ; < TRUE =enable + EnableNodeIntlv BOOLEAN ? ; < Node Memory Interleaving (1-bit) + ; < FALSE = disable (AMD default) + ; < TRUE = enable + EnableChannelIntlv BOOLEAN ? ; < Channel Interleaving (1-bit) + ; < FALSE = disable (AMD default) + ; < TRUE = enable + ; ECC + + EnableEccFeature BOOLEAN ? ; < enable ECC error to go into MCE + ; < FALSE = disable (AMD default) + ; < TRUE = enable + ; Dram Power + + EnablePowerDown BOOLEAN ? ; < CKE based power down mode (1-bit) + ; < FALSE =disable (AMD default) + ; < TRUE =enable + ; Online Spare + + EnableOnLineSpareCtl BOOLEAN ? ; < Chip Select Spare Control bit 0: + ; < FALSE = disable Spare (AMD default) + ; < TRUE = enable Spare + TableBasedAlterations POINTER ? ; < Point to an array of data bytes describing desired modifications to register settings. + + PlatformMemoryConfiguration POINTER ? + ; < Points to a table that contains platform specific settings + ; < (i.e. MemClk routing, the number of DIMM slots per channel,...) + ; < AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that + ; < contains default conservative settings. Platform BIOS can either tweak + ; < DefaultPlatformMemoryConfiguration or reassign this pointer to its own table. + ; < + EnableParity BOOLEAN ? ; < Parity control + ; < TRUE = enable + ; < FALSE = disable (AMD default) + EnableBankSwizzle BOOLEAN ? ; < BankSwizzle control + ; < FALSE = disable + ; < TRUE = enable (AMD default) + EnableMemClr BOOLEAN ? ; < Memory Clear functionality control + ; < FALSE = disable + ; < TRUE = enable (AMD default) + ; Uma Configuration + + UmaMode UMA_MODE ? ; < Uma Mode + ; < 0 = None + ; < 1 = Specified + ; < 2 = Auto + UmaSize UINT32 ? ; < The size of shared graphics dram (16-bits) + ; < NV_UMA_Size[31:0]=Addr[47:16] + ; < + UmaBase UINT32 ? ; < The allocated Uma base address (32-bits) + ; < NV_UMA_Base[31:0]=Addr[47:16] + ; < + + ; Memory Restore Feature + + MemRestoreCtl BOOLEAN ? ; < Memory context restore control + ; < FALSE = perform memory init as normal (AMD default) + ; < TRUE = restore memory context and skip training. This requires + ; < MemContext is valid before AmdInitPost + SaveMemContextCtl BOOLEAN ? ; < Control switch to save memory context at the end of MemAuto + ; < TRUE = AGESA will setup MemContext block before exit AmdInitPost + ; < FALSE = AGESA will not setup MemContext block. Platform is + ; < expected to call S3Save later in POST if it wants to + ; < use memory context restore feature. + MemContext AMD_S3_PARAMS {} ; < Memory context block describes the data that platform needs to + ; < save and restore for memory context restore feature to work. + ; < It uses the subset of S3Save block to save/restore. Hence platform + ; < may save only S3 block and uses it for both S3 resume and + ; < memory context restore. + ; < - If MemRestoreCtl is TRUE, platform needs to pass in MemContext + ; < before AmdInitPost. + ; < - If SaveMemContextCtl is TRUE, platform needs to save MemContext + ; < right after AmdInitPost. + ExternalVrefCtl BOOLEAN ? ; < Control the use of external Vref + ; < TRUE = AGESA will use the function defined in "AGESA_EXTERNAL_2D_TRAIN_VREF_CHANGE" in function list + ; < to change the vref + ; < FALSE = AGESA will will use the internal vref control. + ForceTrainMode FORCE_TRAIN_MODE ? ; < Training Mode + ; < 0 = Force 1D Training for all configurations + ; < 1 = Force 2D Training for all configurations + ; < 2 = Auto - AGESA will control 1D or 2D +MEM_PARAMETER_STRUCT ENDS + + +; =============================================================================== + ; Function definition + ; This data structure passes function pointers to the memory configuration code. + ; The wrapper can use this structure with customized versions +; ================================================================================ +MEM_FUNCTION_STRUCT STRUCT + + ; PUBLIC required Internal functions + + amdMemGetPsCfgU POINTER ? ; < Proc for Unbuffered DIMMs, platform specific + amdMemGetPsCfgR POINTER ? ; < Proc for Registered DIMMs, platform specific + + ; PUBLIC optional functions + + amdMemEccInit POINTER ? ; < NB proc for ECC feature + amdMemChipSelectInterleaveInit POINTER ? ; < NB proc for CS interleave feature + amdMemDctInterleavingInit POINTER ? ; < NB proc for Channel interleave feature + amdMemMctInterleavingInit POINTER ? ; < NB proc for Node interleave feature + amdMemParallelTraining POINTER ? ; < NB proc for parallel training feature + amdMemEarlySampleSupport POINTER ? ; < NB code for early sample support feature + amdMemMultiPartInitSupport POINTER ? ; < NB code for 'multi-part' + amdMemOnlineSpareSupport POINTER ? ; < NB code for On-Line Spare feature + amdMemUDimmInit POINTER ? ; < NB code for UDIMMs + amdMemRDimmInit POINTER ? ; < NB code for RDIMMs + amdMemLrDimmInit POINTER ? ; < NB code for LRDIMMs + Reserved UINT32 (100) DUP (?) ; < Reserved for later function definition +MEM_FUNCTION_STRUCT ENDS + +; =============================================================================== + ; Socket Structure + +; =============================================================================== +MEM_SOCKET_STRUCT STRUCT + ChannelPtr POINTER (MAX_CHANNELS_PER_SOCKET) DUP (?) ; < Pointers to each channels training data + + TimingsPtr POINTER (MAX_CHANNELS_PER_SOCKET) DUP (?) ; < Pointers to each channels timing data + +MEM_SOCKET_STRUCT ENDS + +; =============================================================================== + ; MEM_DATA_STRUCT +; =============================================================================== +MEM_DATA_STRUCT STRUCT + StdHeader AMD_CONFIG_PARAMS {} ; < AGESA Standard Header + + ParameterListPtr POINTER ? ; < List of input Parameters + + FunctionList MEM_FUNCTION_STRUCT {} ; < List of function Pointers + + GetPlatformCfg POINTER (MAX_PLATFORM_TYPES) DUP (?) ; < look-up platform info + + ErrorHandling POINTER ? ; < Error Handling + + ; SocketList is a shortcut for IBVs to retrieve training + ; and timing data for each channel indexed by socket/channel, + ; eliminating their need to parse die/dct/channel etc. + ; It contains pointers to the populated data structures for + ; each channel and skips the channel structures that are + ; unpopulated. In the case of channels sharing the same DCT, + ; the pTimings pointers will point to the same DCT Timing data. + + SocketList MEM_SOCKET_STRUCT (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Socket list for memory code + + DiesPerSystem POINTER ? ; < Pointed to an array of DIE_STRUCTs + DieCount UINT8 ? ; < Number of MCTs in the system. + + SpdDataStructure POINTER ? ; < Pointer to SPD Data structure + + PlatFormConfig POINTER ? ; < Pointer to Platform profile/build option config structure + + IsFlowControlSupported BOOLEAN ? ; < Indicates if flow control is supported + + TscRate UINT32 ? ; < The rate at which the TSC increments in megahertz. + +MEM_DATA_STRUCT ENDS + +; =============================================================================== +; UMA_INFO_STRUCT +; =============================================================================== +UMA_INFO STRUCT + UmaBase UINT64 ? ; < UmaBase[63:0] = Addr[63:0] + UmaSize UINT32 ? ; < UmaSize[31:0] = Addr[31:0] + UmaAttributes UINT32 ? ; < Indicate the attribute of Uma + UmaMode UINT8 ? ; < Indicate the mode of Uma + MemClock UINT16 ? ; < Indicate memory running speed in MHz + Reserved UINT8 (3) DUP (?) ; < Reserved for future usage +UMA_INFO ENDS + +; =============================================================================== +; Bitfield for ID +; =============================================================================== +ID_FIELD STRUCT + SocketId UINT16 ? +; OUT UINT16 SocketId:8; ; < Socket ID +; OUT UINT16 ModuleId:8; ; < Module ID +ID_FIELD ENDS + +; =============================================================================== +; Union for ID of socket and module that will be passed out in call out +; =============================================================================== +ID_INFO UNION + IdField ID_FIELD {} ; < Bitfield for ID + IdInformation UINT16 ? ; < ID information for call out +ID_INFO ENDS + + ; AGESA MEMORY ERRORS + + ; AGESA_ALERT Memory Errors +MEM_ALERT_USER_TMG_MODE_OVERRULED EQU 04010000h ; < TIMING_MODE_SPECIFIC is requested but + ; < cannot be applied to current configurations. +MEM_ALERT_ORG_MISMATCH_DIMM EQU 04010100h ; < DIMM organization miss-match +MEM_ALERT_BK_INT_DIS EQU 04010200h ; < Bank interleaving disable for internal issue + + ; AGESA_ERROR Memory Errors +MEM_ERROR_NO_DQS_POS_RD_WINDOW EQU 04010300h ; < No DQS Position window for RD DQS +MEM_ERROR_SMALL_DQS_POS_RD_WINDOW EQU 04020300h ; < Small DQS Position window for RD DQS +MEM_ERROR_NO_DQS_POS_WR_WINDOW EQU 04030300h ; < No DQS Position window for WR DQS +MEM_ERROR_SMALL_DQS_POS_WR_WINDOW EQU 04040300h ; < Small DQS Position window for WR DQS +MEM_ERROR_ECC_DIS EQU 04010400h ; < ECC has been disabled as a result of an internal issue +MEM_ERROR_DIMM_SPARING_NOT_ENABLED EQU 04010500h ; < DIMM sparing has not been enabled for an internal issues +MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE EQU 04050300h ; < Receive Enable value is too large +MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW EQU 04060300h ; < There is no DQS receiver enable window +MEM_ERROR_DRAM_ENABLED_TIME_OUT EQU 04010600h ; < Time out when polling DramEnabled bit +MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT EQU 04010700h ; < Time out when polling DctAccessDone bit +MEM_ERROR_SEND_CTRL_WORD_TIME_OUT EQU 04010800h ; < Time out when polling SendCtrlWord bit +MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT EQU 04010900h ; < Time out when polling PrefDramTrainMode bit +MEM_ERROR_ENTER_SELF_REF_TIME_OUT EQU 04010A00h ; < Time out when polling EnterSelfRef bit +MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT EQU 04010B00h ; < Time out when polling FreqChgInProg bit +MEM_ERROR_EXIT_SELF_REF_TIME_OUT EQU 04020A00h ; < Time out when polling ExitSelfRef bit +MEM_ERROR_SEND_MRS_CMD_TIME_OUT EQU 04010C00h ; < Time out when polling SendMrsCmd bit +MEM_ERROR_SEND_ZQ_CMD_TIME_OUT EQU 04010D00h ; < Time out when polling SendZQCmd bit +MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT EQU 04010E00h ; < Time out when polling DctExtraAccessDone bit +MEM_ERROR_MEM_CLR_BUSY_TIME_OUT EQU 04010F00h ; < Time out when polling MemClrBusy bit +MEM_ERROR_MEM_CLEARED_TIME_OUT EQU 04020F00h ; < Time out when polling MemCleared bit +MEM_ERROR_FLUSH_WR_TIME_OUT EQU 04011000h ; < Time out when polling FlushWr bit +MEM_ERROR_NBPSTATE_TRANSITION_TIME_OUT EQU 04012600h ; < Time out when polling CurNBPstate bit +MEM_ERROR_MAX_LAT_NO_WINDOW EQU 04070300h ; < Fail to find pass during Max Rd Latency training +MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL EQU 04080300h ; < Fail to launch training code on an AP +MEM_ERROR_PARALLEL_TRAINING_TIME_OUT EQU 04090300h ; < Fail to finish parallel training +MEM_ERROR_NO_ADDRESS_MAPPING EQU 04011100h ; < No address mapping found for a dimm +MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT EQU 040A0300h ; < There is no DQS receiver enable window and the value is equal to the largest value +MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE EQU 040B0300h ; < Receive Enable value is too large and is 1 less than limit +MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR EQU 04011200h ; < SPD Checksum error for NV_SPDCHK_RESTRT +MEM_ERROR_NO_CHIPSELECT EQU 04011300h ; < No chipselects found +MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM EQU 04011500h ; < Unbuffered dimm is not supported at 333MHz +MEM_ERROR_WL_PRE_OUT_OF_RANGE EQU 040C0300h ; < Returned PRE value during write levelization was out of range +MEM_ERROR_NO_2D_RDDQS_WINDOW EQU 040D0300h ; < No 2D RdDqs Window +MEM_ERROR_NO_2D_RDDQS_HEIGHT EQU 040E0300h ; < No 2D RdDqs Height +MEM_ERROR_2D_DQS_ERROR EQU 040F0300h ; < 2D RdDqs Error +MEM_ERROR_INVALID_2D_RDDQS_VALUE EQU 04022400h ; < 2d RdDqs invalid value found +MEM_ERROR_2D_DQS_VREF_MARGIN_ERROR EQU 04023400h ; < 2d RdDqs Vef Margin error found +MEM_ERROR_LR_IBT_NOT_FOUND EQU 04013500h ; < No LR dimm IBT value is found +MEM_ERROR_MR0_NOT_FOUND EQU 04023500h ; < No MR0 value is found +MEM_ERROR_ODT_PATTERN_NOT_FOUND EQU 04033500h ; < No odt pattern value is found +MEM_ERROR_RC2_IBT_NOT_FOUND EQU 04043500h ; < No RC2 IBT value is found +MEM_ERROR_RC10_OP_SPEED_NOT_FOUND EQU 04053500h ; < No RC10 op speed is found +MEM_ERROR_RTT_NOT_FOUND EQU 04063500h ; < No RTT value is found +MEM_ERROR_P2D_NOT_FOUND EQU 04073500h ; < No 2D training config value is found +MEM_ERROR_SAO_NOT_FOUND EQU 04083500h ; < No slow access mode, Address timing and Output driver compensation value is found +MEM_ERROR_CLK_DIS_MAP_NOT_FOUND EQU 04093500h ; < No CLK disable map is found +MEM_ERROR_CKE_TRI_MAP_NOT_FOUND EQU 040A3500h ; < No CKE tristate map is found +MEM_ERROR_ODT_TRI_MAP_NOT_FOUND EQU 040B3500h ; < No ODT tristate map is found +MEM_ERROR_CS_TRI_MAP_NOT_FOUND EQU 040C3500h ; < No CS tristate map is found +MEM_ERROR_TRAINING_SEED_NOT_FOUND EQU 040D3500h ; < No training seed is found + + ; AGESA_WARNING Memory Errors + MEM_WARNING_UNSUPPORTED_QRDIMM EQU 04011600h ; < QR DIMMs detected but not supported + MEM_WARNING_UNSUPPORTED_UDIMM EQU 04021600h ; < U DIMMs detected but not supported + MEM_WARNING_UNSUPPORTED_SODIMM EQU 04031600h ; < SO-DIMMs detected but not supported + MEM_WARNING_UNSUPPORTED_X4DIMM EQU 04041600h ; < x4 DIMMs detected but not supported + MEM_WARNING_UNSUPPORTED_RDIMM EQU 04051600h ; < R DIMMs detected but not supported + MEM_WARNING_UNSUPPORTED_LRDIMM EQU 04061600h ; < LR DIMMs detected but not supported + + MEM_WARNING_EMP_NOT_SUPPORTED EQU 04011700h ; < Processor is not capable for EMP + MEM_WARNING_EMP_CONFLICT EQU 04021700h ; < EMP cannot be enabled if channel interleaving, + ; < bank interleaving, or bank swizzle is enabled. + MEM_WARNING_EMP_NOT_ENABLED EQU 04031700h ; < Memory size is not power of two. + MEM_WARNING_ECC_DIS EQU 04041700h ; < ECC has been disabled as a result of an internal issue + MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED EQU 04011800h ; < Performance has been enabled, but battery life is preferred. + MEM_WARNING_NO_SPDTRC_FOUND EQU 04011900h ; < No Trc timing value found in SPD of a dimm. + MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED EQU 04012000h ; < Node Interleaveing Requested, but could not be enabled + MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED EQU 04012100h ; < Channel Interleaveing Requested, but could not be enabled + MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED EQU 04012200h ; < Bank Interleaveing Requested, but could not be enabled + MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED EQU 04012300h ; < Voltage 1.35 determined, but could not be supported + MEM_WARNING_INITIAL_DDR3VOLT_NONZERO EQU 04012400h ; < DDR3 voltage initial value is not 0 + MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO EQU 04012500h ; < Cannot find a commonly supported VDDIO + + ; AGESA_FATAL Memory Errors + MEM_ERROR_MINIMUM_MODE EQU 04011A00h ; < Running in minimum mode + MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM EQU 04011B00h ; < DIMM modules are miss-matched + MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM EQU 04011C00h ; < No DIMMs have been found on system + MEM_ERROR_MISMATCH_DIMM_CLOCKS EQU 04011D00h ; < DIMM clocks miss-matched + MEM_ERROR_NO_CYC_TIME EQU 04011E00h ; < No cycle time found + MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS EQU 04011F00h ; < Heap allocation error with dynamic storing of trained timings + MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs EQU 04021F00h ; < Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT + MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV EQU 04031F00h ; < Heap allocation error with REMOTE_TRAINING_ENV + MEM_ERROR_HEAP_ALLOCATE_FOR_SPD EQU 04041F00h ; < Heap allocation error for SPD data + MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA EQU 04051F00h ; < Heap allocation error for RECEIVED_DATA during parallel training + MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS EQU 04061F00h ; < Heap allocation error for S3 "SPECIAL_CASE_REGISTER" + MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA EQU 04071F00h ; < Heap allocation error for Training Data + MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK EQU 04081F00h ; < Heap allocation error for DIMM Identify "MEM_NB_BLOCK + MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM EQU 04022300h ; < No Constructor for DIMM Identify + MEM_ERROR_VDDIO_UNSUPPORTED EQU 04022500h ; < VDDIO of the dimms on the board is not supported + MEM_ERROR_HEAP_ALLOCATE_FOR_2D EQU 040B1F00h ; < Heap allocation error for 2D training data + MEM_ERROR_HEAP_DEALLOCATE_FOR_2D EQU 040C1F00h ; < Heap de-allocation error for 2D training data + + ; AGESA_CRITICAL Memory Errors + MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3 EQU 04091F00h ; < Heap allocation error for DMI table for DDR3 + MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2 EQU 040A1F00h ; < Heap allocation error for DMI table for DDR2 + MEM_ERROR_UNSUPPORTED_DIMM_CONFIG EQU 04011400h ; < Dimm population is not supported + MEM_ERROR_HEAP_ALLOCATE_FOR_CRAT_MEM_AFFINITY EQU 040D1F00h ;< Heap allocation error for CRAT memory affinity info + +; ---------------------------------------------------------------------------- +; * +; * END OF MEMORY-SPECIFIC DATA STRUCTURES +; * +; *---------------------------------------------------------------------------- +; + + +; ---------------------------------------------------------------------------- +; * +; * CPU RELATED DEFINITIONS +; * +; *---------------------------------------------------------------------------- +; + +; CPU Event definitions. + +; Defines used to filter CPU events based on functional blocks +CPU_EVENT_PM_EVENT_MASK EQU 0FF00FF00h +CPU_EVENT_PM_EVENT_CLASS EQU 008000400h + +;================================================================ +; CPU General events +; Heap allocation (AppFunction = 01h) +CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT EQU 008000100h +CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED EQU 008010100h +CPU_ERROR_HEAP_IS_FULL EQU 008020100h +CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED EQU 008030100h +CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT EQU 008040100h +; BrandId (AppFunction = 02h) +CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE EQU 008000200h +; Micro code patch (AppFunction = 03h) +CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED EQU 008000300h +; Power management (AppFunction = 04h) +CPU_EVENT_PM_PSTATE_OVERCURRENT EQU 008000400h +CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT EQU 008010400h +CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE EQU 008020400h +CPU_ERROR_PM_NB_PSTATE_MISMATCH EQU 008030400h +; Other CPU events (AppFunction = 05h) +CPU_EVENT_BIST_ERROR EQU 008000500h +CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY EQU 008010500h +CPU_EVENT_STACK_REENTRY EQU 008020500h +CPU_EVENT_CORE_NOT_IDENTIFIED EQU 008030500h +;================================================================= +; CPU Feature events +; Execution cache (AppFunction = 21h) +; AGESA_CACHE_SIZE_REDUCED 2101 +; AGESA_CACHE_REGIONS_ACROSS_1MB 2102 +; AGESA_CACHE_REGIONS_ACROSS_4GB 2103 +; AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 2104 +; AGESA_CACHE_START_ADDRESS_LESS_D0000 2105 +; AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 2106 +; AGESA_DEALLOCATE_CACHE_REGIONS 2107 +CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR EQU 008002100h +; Core Leveling (AppFunction = 22h) +CPU_WARNING_ADJUSTED_LEVELING_MODE EQU 008002200h +; HT Assist (AppFunction = 23h) +CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG EQU 008002300h + +; CPU Build Configuration structures and definitions + +; Build Configuration values for BLDGCFG_AP_MTRR_SETTINGS +AP_MTRR_SETTINGS STRUCT + MsrAddr UINT32 ? ; < Fixed-Sized MTRR address + MsrData UINT64 ? ; < MTRR Settings +AP_MTRR_SETTINGS ENDS + +AMD_AP_MTRR_FIX64k_00000 EQU 000000250h +AMD_AP_MTRR_FIX16k_80000 EQU 000000258h +AMD_AP_MTRR_FIX16k_A0000 EQU 000000259h +AMD_AP_MTRR_FIX4k_C0000 EQU 000000268h +AMD_AP_MTRR_FIX4k_C8000 EQU 000000269h +AMD_AP_MTRR_FIX4k_D0000 EQU 00000026Ah +AMD_AP_MTRR_FIX4k_D8000 EQU 00000026Bh +AMD_AP_MTRR_FIX4k_E0000 EQU 00000026Ch +AMD_AP_MTRR_FIX4k_E8000 EQU 00000026Dh +AMD_AP_MTRR_FIX4k_F0000 EQU 00000026Eh +AMD_AP_MTRR_FIX4k_F8000 EQU 00000026Fh +CPU_LIST_TERMINAL EQU 0FFFFFFFFh + +; *********************************************************************** +; * +; * AGESA interface Call-Out function parameter structures +; * +; ********************************************************************** + + ; Parameters structure for interface call-out AgesaAllocateBuffer +AGESA_BUFFER_PARAMS STRUCT + StdHeader AMD_CONFIG_PARAMS {} ; < Standard header + BufferLength UINT32 ? ; < Size of buffer to allocate + BufferHandle UINT32 ? ; < Identifier or name for the buffer + BufferPointer POINTER ? ; < location of the created buffer +AGESA_BUFFER_PARAMS ENDS + + ; Parameters structure for interface call-out AgesaRunCodeOnAp +AP_EXE_PARAMS STRUCT + StdHeader AMD_CONFIG_PARAMS {} ; < Standard header + FunctionNumber UINT32 ? ; < Index of the procedure to execute + RelatedDataBlock POINTER ? ; < Location of data structure the procedure will use + RelatedBlockLength UINT32 ? ; < Size of the related data block +AP_EXE_PARAMS ENDS + + ; Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery +AGESA_READ_SPD_PARAMS STRUCT + StdHeader AMD_CONFIG_PARAMS {} ; < standard header + SocketId UINT8 ? ; < Address of SPD - socket ID + MemChannelId UINT8 ? ; < Address of SPD - memory channel ID + DimmId UINT8 ? ; < Address of SPD - DIMM ID + Buffer POINTER ? ; < Location where to place the SPD content + MemData POINTER ? ; < Location of the MemData structure, for reference +AGESA_READ_SPD_PARAMS ENDS + + ; Buffer Handles + AMD_DMI_INFO_BUFFER_HANDLE EQU 000D000h ; < Assign 0x000D000 buffer handle to DMI function + AMD_PSTATE_DATA_BUFFER_HANDLE EQU 000D001h ; < Assign 0x000D001 buffer handle to Pstate data + AMD_PSTATE_ACPI_BUFFER_HANDLE EQU 000D002h ; < Assign 0x000D002 buffer handle to Pstate table + AMD_BRAND_ID_BUFFER_HANDLE EQU 000D003h ; < Assign 0x000D003 buffer handle to Brand ID + AMD_ACPI_SLIT_BUFFER_HANDLE EQU 000D004h ; < Assign 0x000D004 buffer handle to SLIT function + AMD_SRAT_INFO_BUFFER_HANDLE EQU 000D005h ; < Assign 0x000D005 buffer handle to SRAT function + AMD_WHEA_BUFFER_HANDLE EQU 000D006h ; < Assign 0x000D006 buffer handle to WHEA function + AMD_S3_INFO_BUFFER_HANDLE EQU 000D007h ; < Assign 0x000D007 buffer handle to S3 function + AMD_S3_NB_INFO_BUFFER_HANDLE EQU 000D008h ; < Assign 0x000D008 buffer handle to S3 NB device info + AMD_ACPI_ALIB_BUFFER_HANDLE EQU 000D009h ; < Assign 0x000D009 buffer handle to ALIB SSDT table + AMD_ACPI_IVRS_BUFFER_HANDLE EQU 000D00Ah ; < Assign 0x000D00A buffer handle to IOMMU IVRS table + AMD_CRAT_INFO_BUFFER_HANDLE EQU 000D00Bh ; < Assign 0x000D00B buffer handle to CRAT function + AMD_ACPI_CDIT_BUFFER_HANDLE EQU 000D00Ch ; < Assign 0x000D00C buffer handle to CDIT function +AMD_BUFFER_HANDLE TEXTEQU <DWORD> +; *********************************************************************** +; * +; * AGESA interface Call-Out function prototypes +; * +; ********************************************************************** + +; *********************************************************************** +; * +; * AGESA interface structure definition and function prototypes +; * +; ********************************************************************** + +; ********************************************************************* +; * Platform Configuration: The parameters in boot branch function +; ********************************************************************* + +; The possible platform control flow settings. + Nfcm EQU 0 ; < Normal Flow Control Mode. + UmaDr EQU 1 ; < UMA using Display Refresh flow control. + UmaIfcm EQU 2 ; < UMA using Isochronous Flow Control. + Ifcm EQU 3 ; < Isochronous Flow Control Mode (other than for UMA). + Iommu EQU 4 ; < An IOMMU is in use in the system. + MaxControlFlow EQU 5 ; < Not a control flow mode, use for limit checking. +PLATFORM_CONTROL_FLOW TEXTEQU <DWORD> + +; Platform Deemphasis Levels. + DeemphasisLevelNone EQU 0 ; < No Deemphasis. + DeemphasisLevelMinus3 EQU 1 ; < Minus 3 db deemphasis. + DeemphasisLevelMinus6 EQU 2 ; < Minus 6 db deemphasis. + DeemphasisLevelMinus8 EQU 3 ; < Minus 8 db deemphasis. + DeemphasisLevelMinus11 EQU 4 ; < Minus 11 db deemphasis. + DeemphasisLevelMinus11pre8 EQU 5 ; < Minus 11, Minus 8 precursor db deemphasis. + DcvLevelNone EQU 16 ; < No DCV Deemphasis. + DcvLevelMinus2 EQU 17 ; < Minus 2 db DCV deemphasis. + DcvLevelMinus3 EQU 18 ; < Minus 3 db DCV deemphasis. + DcvLevelMinus5 EQU 19 ; < Minus 5 db DCV deemphasis. + DcvLevelMinus6 EQU 20 ; < Minus 6 db DCV deemphasis. + DcvLevelMinus7 EQU 21 ; < Minus 7 db DCV deemphasis. + DcvLevelMinus8 EQU 22 ; < Minus 8 db DCV deemphasis. + DcvLevelMinus9 EQU 23 ; < Minus 9 db DCV deemphasis. + DcvLevelMinus11 EQU 24 ; < Minus 11 db DCV deemphasis. + MaxPlatformDeemphasisLevel EQU 25 ; < Not a deemphasis level, use for limit checking. +PLATFORM_DEEMPHASIS_LEVEL TEXTEQU <DWORD> + +; Provide Deemphasis Levels for HT Links. +; +; For each CPU to CPU or CPU to IO device HT link, the list of Deemphasis Levels will +; be checked for a match. The item matches for a Socket, Link if the link frequency is +; is in the inclusive range HighFreq:LoFreq. +; AGESA does not set deemphasis in IO devices, only in processors. + +CPU_HT_DEEMPHASIS_LEVEL STRUCT + ; Match fields + Socket UINT8 ? ; < One Socket on which this Link is located + Link UINT8 ? ; < The Link on this Processor. + LoFreq UINT8 ? ; < If the link is set to this frequency or greater, apply these levels, and + HighFreq UINT8 ? ; < If the link is set to this frequency or less, apply these levels. + ; Value fields + ReceiverDeemphasis PLATFORM_DEEMPHASIS_LEVEL ? ; < The deemphasis level for this link + DcvDeemphasis PLATFORM_DEEMPHASIS_LEVEL ? ; < The DCV, or far transmitter deemphasis level. +CPU_HT_DEEMPHASIS_LEVEL ENDS + +; The possible hardware prefetch mode settings. + HARDWARE_PREFETCHER_AUTO EQU 0 ; Use the recommended setting for the processor. In most cases, the recommended setting is enabled. + DISABLE_L1_PREFETCHER EQU 1 ; Use the recommended settings for the hardware prefetcher, but disable L1 prefetching. + DISABLE_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES EQU 2 ; Use the recommended setting for the hardware prefetcher, but disable training on software prefetches. + DISABLE_L1_PREFETCHER_AND_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES EQU 3 ; Use the recommended settings for the hardware prefetcher, but disable both the L1 prefetcher and training on software prefetches. + DISABLE_HARDWARE_PREFETCH EQU 4 ; Disable hardware prefetching. + MAX_HARDWARE_PREFETCH_MODE EQU 5 ; Not a hardware prefetch mode, use for limit checking. +HARDWARE_PREFETCH_MODE TEXTEQU <DWORD> + +; The possible software prefetch mode settings. + SOFTWARE_PREFETCHES_AUTO EQU 0 ; Use the recommended setting for the processor. In most cases, the recommended setting is enabled. + DISABLE_SOFTWARE_PREFETCHES EQU 1 ; Disable software prefetches (convert software prefetch instructions to NOP). + MAX_SOFTWARE_PREFETCH_MODE EQU 2 ; Not a software prefetch mode, use for limit checking. +SOFTWARE_PREFETCH_MODE TEXTEQU <DWORD> + +; Advanced performance tunings, prefetchers. +; These settings provide for performance tuning to optimize for specific workloads. +ADVANCED_PERFORMANCE_PROFILE STRUCT + HardwarePrefetchMode HARDWARE_PREFETCH_MODE ? ; This value provides for advanced performance tuning by controlling the hardware prefetcher setting. + SoftwarePrefetchMode SOFTWARE_PREFETCH_MODE ? ; This value provides for advanced performance tuning by controlling the software prefetch instructions. + DramPrefetchMode DRAM_PREFETCH_MODE ? ; This value provides for advanced performance tuning by controlling the DRAM prefetcher setting. +ADVANCED_PERFORMANCE_PROFILE ENDS + +; The possible platform power policy settings. + Performance EQU 0 ; < Optimize for performance. + BatteryLife EQU 1 ; < Optimize for battery life. + MaxPowerPolicy EQU 2 ; < Not a power policy mode, use for limit checking. +PLATFORM_POWER_POLICY TEXTEQU <DWORD> + +; Platform performance settings for optimized settings. +; Several configuration settings for the processor depend upon other parts and +; general designer choices for the system. The determination of these data points +; is not standard for all platforms, so the host environment needs to provide these +; to specify how the system is to be configured. +PERFORMANCE_PROFILE STRUCT + PlatformControlFlowMode PLATFORM_CONTROL_FLOW ? ; < The platform's control flow mode for optimum platform performance. + UseHtAssist BOOLEAN ? ; < HyperTransport link traffic optimization. + UseAtmMode BOOLEAN ? ; < HyperTransport link traffic optimization. + Use32ByteRefresh BOOLEAN ? ; < Display Refresh traffic generates 32 byte requests. + UseVariableMctIsocPriority BOOLEAN ? ; < The Memory controller will be set to Variable Isoc Priority. + AdvancedPerformanceProfile ADVANCED_PERFORMANCE_PROFILE {} ; < The advanced platform performance settings. + PlatformPowerPolicy PLATFORM_POWER_POLICY ? ; < The platform's desired power policy +PERFORMANCE_PROFILE ENDS + +; Platform settings that describe the voltage regulator modules of the system. +; Many power management settings are dependent upon the characteristics of the +; on-board voltage regulator module (VRM). The host environment needs to provide +; these to specify how the system is to be configured. +PLATFORM_VRM_CONFIGURATION STRUCT + CurrentLimit UINT32 ? ; < Vrm Current Limit. + LowPowerThreshold UINT32 ? ; < Vrm Low Power Threshold. + SlewRate UINT32 ? ; < Vrm Slew Rate. + AdditionalDelay UINT32 ? ; < Vrm Additional Delay. + HiSpeedEnable BOOLEAN ? ; < Select high speed VRM. + InrushCurrentLimit UINT32 ? ; < Vrm Inrush Current Limit. + SviOcpLevel UINT32 ? ; < Vrm SVI OCP Level. +PLATFORM_VRM_CONFIGURATION ENDS + +; The VRM types to characterize. + CoreVrm EQU 0 ; < VDD plane. + NbVrm EQU 1 ; < VDDNB plane. + MaxVrmType EQU 2 ; < Not a valid VRM type, use for limit checking. +PLATFORM_VRM_TYPE TEXTEQU <DWORD> + +; FCH Platform Configuration Policy +FCH_PLATFORM_POLICY STRUCT + CfgSmbus0BaseAddress UINT16 ? ; SMBUS0 Controller Base Address + CfgSmbus1BaseAddress UINT16 ? ; SMBUS1 Controller Base Address + CfgSioPmeBaseAddress UINT16 ? ; I/O base address for LPC I/O target range + CfgAcpiPm1EvtBlkAddr UINT16 ? ; I/O base address of ACPI power management Event Block + CfgAcpiPm1CntBlkAddr UINT16 ? ; I/O base address of ACPI power management Control Block + CfgAcpiPmTmrBlkAddr UINT16 ? ; I/O base address of ACPI power management Timer Block + CfgCpuControlBlkAddr UINT16 ? ; I/O base address of ACPI power management CPU Control Block + CfgAcpiGpe0BlkAddr UINT16 ? ; I/O base address of ACPI power management General Purpose Event Block + CfgSmiCmdPortAddr UINT16 ? ; I/O base address of ACPI SMI Command Block + CfgAcpiPmaCntBlkAddr UINT16 ? ; I/O base address of ACPI power management additional control block + CfgGecShadowRomBase UINT32 ? ; 32-bit base address to the GEC shadow ROM + CfgWatchDogTimerBase UINT32 ? ; Watchdog Timer base address + CfgSpiRomBaseAddress UINT32 ? ; Base address for the SPI ROM controller + CfgHpetBaseAddress UINT32 ? ; HPET MMIO base address +;del CfgAzaliaSsid UINT32 ? ; Subsystem ID of HD Audio controller + CfgSmbusSsid UINT32 ? ; Subsystem ID of SMBUS controller + CfgIdeSsid UINT32 ? ; Subsystem ID of IDE controller + CfgSataAhciSsid UINT32 ? ; Subsystem ID of SATA controller in AHCI mode + CfgSataIdeSsid UINT32 ? ; Subsystem ID of SATA controller in IDE mode + CfgSataRaid5Ssid UINT32 ? ; Subsystem ID of SATA controller in RAID5 mode + CfgSataRaidSsid UINT32 ? ; Subsystem ID of SATA controller in RAID mode + CfgEhciSsid UINT32 ? ; Subsystem ID of EHCI + CfgOhciSsid UINT32 ? ; Subsystem ID of OHCI + CfgLpcSsid UINT32 ? ; Subsystem ID of LPC ISA Bridge + CfgSdSsid UINT32 ? ; Subsystem ID of SecureDigital controller + CfgXhciSsid UINT32 ? ; Subsystem ID of XHCI + CfgFchPort80BehindPcib BOOLEAN ? ; Is port80 cycle going to the PCI bridge + CfgFchEnableAcpiSleepTrap BOOLEAN ? ; ACPI sleep SMI enable/disable + CfgFchGppLinkConfig GPP_LINKMODE ? ; FCH GPP link configuration + CfgFchGppPort0Present BOOLEAN ? ; Is FCH GPP port 0 present + CfgFchGppPort1Present BOOLEAN ? ; Is FCH GPP port 1 present + CfgFchGppPort2Present BOOLEAN ? ; Is FCH GPP port 2 present + CfgFchGppPort3Present BOOLEAN ? ; Is FCH GPP port 3 present + CfgFchGppPort0HotPlug BOOLEAN ? ; Is FCH GPP port 0 hotplug capable + CfgFchGppPort1HotPlug BOOLEAN ? ; Is FCH GPP port 1 hotplug capable + CfgFchGppPort2HotPlug BOOLEAN ? ; Is FCH GPP port 2 hotplug capable + CfgFchGppPort3HotPlug BOOLEAN ? ; Is FCH GPP port 3 hotplug capable + + CfgFchEsataPortBitMap UINT8 ? ; ESATA Port definition, eg: [0]=1, means port 0 is ESATA capable + CfgFchIrPinControl UINT8 ? ; Register bitfield describing Infrared Pin Control: + CfgFchSdClockControl SD_CLOCK_CONTROL ? ; FCH SD Clock Control + CfgFchSciMapControl POINTER ? ; FCH SCI Mapping Control + CfgFchSataPhyControl POINTER ? ; FCH SATA PHY Control + CfgFchGpioControl POINTER ? ; FCH GPIO Control +FCH_PLATFORM_POLICY ENDS + + +; Build Option/Configuration Boolean Structure +BUILD_OPT_CFG STRUCT + ; Build Option Area + VersionString AMD_CODE_HEADER {} ; < AMD embedded code version string + OptionUDimms BOOLEAN ? ; < UDIMMS + OptionRDimms BOOLEAN ? ; < RDIMMS + OptionLrDimms BOOLEAN ? ; < LRDIMMS + OptionEcc BOOLEAN ? ; < ECC + OptionBankInterleave BOOLEAN ? ; < BANK_INTERLEAVE + OptionDctInterleave BOOLEAN ? ; < DCT_INTERLEAVE + OptionNodeInterleave BOOLEAN ? ; < NODE_INTERLEAVE + OptionParallelTraining BOOLEAN ? ; < PARALLEL_TRAINING + OptionOnlineSpare BOOLEAN ? ; < ONLINE_SPARE + OptionMemRestore BOOLEAN ? ; < MEM CONTEXT RESTORE + OptionMultisocket BOOLEAN ? ; < MULTISOCKET + OptionAcpiPstates BOOLEAN ? ; < ACPI_PSTATES + OptionPStatesInHpcMode BOOLEAN ? ; < PSTATES_HPC_MODE + OptionCrat BOOLEAN ? ; < CRAT + OptionCdit BOOLEAN ? ; < CDIT + OptionSrat BOOLEAN ? ; < SRAT + OptionSlit BOOLEAN ? ; < SLIT + OptionWhea BOOLEAN ? ; < WHEA + OptionDmi BOOLEAN ? ; < DMI + OptionEarlySamples BOOLEAN ? ; < EARLY_SAMPLES + OptionAddrToCsTranslator BOOLEAN ? ; < ADDR_TO_CS_TRANSLATOR + + ; Build Configuration Area + CfgPciMmioAddress UINT64 ? ; < PciMmioBase + CfgPciMmioSize UINT32 ? ; < PciMmioSize + CfgPlatVrmCfg PLATFORM_VRM_CONFIGURATION (MaxVrmType) DUP ({}) ; < Several configuration settings for the voltage regulator modules. + CfgPlatNumIoApics UINT32 ? ; < PlatformApicIoNumber + CfgMemInitPstate UINT32 ? ; < MemoryInitPstate + CfgPlatformC1eMode PLATFORM_C1E_MODES ? ; < PlatformC1eMode + CfgPlatformC1eOpData UINT32 ? ; < PlatformC1eOpData + CfgPlatformC1eOpData1 UINT32 ? ; < PlatformC1eOpData1 + CfgPlatformC1eOpData2 UINT32 ? ; < PlatformC1eOpData2 + CfgPlatformC1eOpData3 UINT32 ? ; < PlatformC1eOpData3 + CfgPlatformCStateMode PLATFORM_CSTATE_MODES ? ; < PlatformCStateMode + CfgPlatformCStateOpData UINT32 ? ; < PlatformCStateOpData + CfgPlatformCStateIoBaseAddress UINT16 ? ; < PlatformCStateIoBaseAddress + CfgPlatformCpbMode PLATFORM_CPB_MODES ? ; < PlatformCpbMode + CfgLowPowerPstateForProcHot PLATFORM_LOW_POWER_PSTATE_MODES ? ; < Low power Pstate for PROCHOT mode + CfgCoreLevelingMode UINT32 ? ; < CoreLevelingCofig + CfgPerformanceProfile PERFORMANCE_PROFILE {} ; < The platform's control flow mode and platform performance settings. + CfgPlatformDeemphasisList POINTER ? ; < HT Deemphasis + CfgAmdPlatformType UINT32 ? ; < AmdPlatformType + CfgAmdPstateCapValue UINT32 ? ; < Amd pstate ceiling enabling deck + + CfgMemoryBusFrequencyLimit MEMORY_BUS_SPEED ? ; < Memory Bus Frequency Limit + CfgMemoryModeUnganged BOOLEAN ? ; < Memory Mode Unganged + CfgMemoryQuadRankCapable BOOLEAN ? ; < Memory Quad Rank Capable + CfgMemoryQuadrankType QUANDRANK_TYPE ? ; < Memory Quadrank Type + CfgMemoryRDimmCapable BOOLEAN ? ; < Memory RDIMM Capable + CfgMemoryLRDimmCapable BOOLEAN ? ; < Memory LRDIMM Capable + CfgMemoryUDimmCapable BOOLEAN ? ; < Memory UDIMM Capable + CfgMemorySODimmCapable BOOLEAN ? ; < Memory SODimm Capable + CfgLimitMemoryToBelow1Tb BOOLEAN ? ; < Limit memory address space to below 1TB + CfgMemoryEnableBankInterleaving BOOLEAN ? ; < Memory Enable Bank Interleaving + CfgMemoryEnableNodeInterleaving BOOLEAN ? ; < Memory Enable Node Interleaving + CfgMemoryChannelInterleaving BOOLEAN ? ; < Memory Channel Interleaving + CfgMemoryPowerDown BOOLEAN ? ; < Memory Power Down + CfgPowerDownMode POWER_DOWN_MODE ? ; < Power Down Mode + CfgOnlineSpare BOOLEAN ? ; < Online Spare + CfgMemoryParityEnable BOOLEAN ? ; < Memory Parity Enable + CfgBankSwizzle BOOLEAN ? ; < Bank Swizzle + CfgTimingModeSelect USER_MEMORY_TIMING_MODE ? ; < Timing Mode Select + CfgMemoryClockSelect MEMORY_BUS_SPEED ? ; < Memory Clock Select + CfgDqsTrainingControl BOOLEAN ? ; < Dqs Training Control + CfgIgnoreSpdChecksum BOOLEAN ? ; < Ignore Spd Checksum + CfgUseBurstMode BOOLEAN ? ; < Use Burst Mode + CfgMemoryAllClocksOn BOOLEAN ? ; < Memory All Clocks On + CfgEnableEccFeature BOOLEAN ? ; < Enable ECC Feature + CfgEccRedirection BOOLEAN ? ; < ECC Redirection + CfgScrubDramRate UINT16 ? ; < Scrub Dram Rate + CfgScrubL2Rate UINT16 ? ; < Scrub L2Rate + CfgScrubL3Rate UINT16 ? ; < Scrub L3Rate + CfgScrubIcRate UINT16 ? ; < Scrub Ic Rate + CfgScrubDcRate UINT16 ? ; < Scrub Dc Rate + CfgEccSyncFlood BOOLEAN ? ; < ECC Sync Flood + CfgEccSymbolSize UINT16 ? ; < ECC Symbol Size + CfgHeapDramAddress UINT64 ? ; < Heap contents will be temporarily stored in this address during the transition + CfgNodeMem1GBAlign BOOLEAN ? ; < Node Mem 1GB boundary Alignment + CfgS3LateRestore BOOLEAN ? ; < S3 Late Restore + CfgAcpiPstateIndependent BOOLEAN ? ; < PSD method dependent/Independent + CfgApMtrrSettingsList POINTER ? ; < The AP's MTRR settings before final halt + CfgUmaMode UMA_MODE ? ; < Uma Mode + CfgUmaSize UINT32 ? ; < Uma Size [31:0]=Addr[47:16] + CfgUmaAbove4G BOOLEAN ? ; < Uma Above 4G Support + CfgUmaAlignment UMA_ALIGNMENT ? ; < Uma alignment + CfgProcessorScopeInSb BOOLEAN ? ; < ACPI Processor Object in _SB scope + CfgProcessorScopeName0 CHAR8 ? ; < OEM specific 1st character of processor scope name. + CfgProcessorScopeName1 CHAR8 ? ; < OEM specific 2nd character of processor scope name. + CfgGnbHdAudio UINT8 ? ; < Gnb HD Audio Enable + CfgAbmSupport UINT8 ? ; < ABM support + CfgDynamicRefreshRate UINT8 ? ; < Dynamic refresh rate + CfgLcdBackLightControl UINT16 ? ; < Lcd back light control + CfgGnb3dStereoPinIndex UINT8 ? ; < 3D Stereo Pin ID + CfgTempPcieMmioBaseAddress UINT32 ? ; < Temp pcie MMIO base address + CfgGnbIGPUSSID UINT32 ? ; < Gnb internal GPU SSID + CfgGnbHDAudioSSID UINT32 ? ; < Gnb HD Audio SSID + CfgGnbPcieSSID UINT32 ? ; < Gnb PCIe SSID + CfgLvdsSpreadSpectrum UINT16 ? ; < Lvds Spread Spectrum. Build-time customizable only + CfgLvdsSpreadSpectrumRate UINT16 ? ; < Lvds Spread Spectrum Rate. Build-time customizable only + FchBldCfg POINTER ? ; < FCH platform build configuration policy + CfgIommuSupport BOOLEAN ? ; IOMMU support + CfgLvdsPowerOnSeqDigonToDe UINT8 ? ; Panel initialization timing + CfgLvdsPowerOnSeqDeToVaryBl UINT8 ? ; Panel initialization timing + CfgLvdsPowerOnSeqDeToDigon UINT8 ? ; Panel initialization timing + CfgLvdsPowerOnSeqVaryBlToDe UINT8 ? ; Panel initialization timing + CfgLvdsPowerOnSeqOnToOffDelay UINT8 ? ; Panel initialization timing + CfgLvdsPowerOnSeqVaryBlToBlon UINT8 ? ; Panel initialization timing + CfgLvdsPowerOnSeqBlonToVaryBl UINT8 ? ; Panel initialization timing + CfgLvdsMaxPixelClockFreq UINT16 ? ; The maximum pixel clock frequency supported + CfgLcdBitDepthControlValue UINT32 ? ; The LCD bit depth control settings + CfgLvds24bbpPanelMode UINT8 ? ; The LVDS 24 BBP mode + CfgLvdsMiscControl LVDS_MISC_CONTROL {}; THe LVDS Misc control + CfgPcieRefClkSpreadSpectrum UINT16 ? ; PCIe Reference Clock Spread Spectrum + CfgExternalVrefCtlFeature BOOLEAN ? ; External Vref control + CfgForceTrainMode FORCE_TRAIN_MODE ? ; < Force Train Mode + CfgGnbRemoteDisplaySupport BOOLEAN ? ; Wireless Display Support + CfgIvrsExclusionRangeList POINTER ? ; IOMMU Exclusion Range List + CfgGnbSyncFloodPinAsNmi BOOLEAN ? ; Define function of NMI_SYNCFLOOD as NMI + CfgIgpuEnableDisablePolicy UINT8 ? ; This item defines the iGPU Enable/Disable policy + CfgGnbSwTjOffset UINT8 ? ; Software-writeable TjOffset + CfgLvdsMiscVoltAdjustment UINT8 ? ; Travis register LVDS_CTRL_4 to adjust LVDS output voltage + CfgDisplayMiscControl DISPLAY_MISC_CONTROL {}; The Display Misc control + Reserved BOOLEAN ? ; < reserved... +BUILD_OPT_CFG ENDS + + ; A structure containing platform specific operational characteristics. This + ; structure is initially populated by the initializer with a copy of the same + ; structure that was created at build time using the build configuration controls. +PLATFORM_CONFIGURATION STRUCT + PlatformProfile PERFORMANCE_PROFILE {} ; < Several configuration settings for the processor. + PlatformDeemphasisList POINTER ? ; < Deemphasis levels for the platform's HT links. + CoreLevelingMode UINT8 ? ; < Indicates how to balance the number of cores per processor. + C1eMode PLATFORM_C1E_MODES ? ; < Specifies the method of C1e enablement - Disabled, HW, or message based. + C1ePlatformData UINT32 ? ; < If C1eMode is HW, specifies the P_LVL3 I/O port of the platform. + C1ePlatformData1 UINT32 ? ; < If C1eMode is SW, specifies the address of chipset's SMI command port. + C1ePlatformData2 UINT32 ? ; < If C1eMode is SW, specifies the unique number used by the SMI handler to identify SMI source. + C1ePlatformData3 UINT32 ? ; < If C1eMode is Auto, specifies the P_LVL3 I/O port of the platform for HW C1e + CStateMode PLATFORM_CSTATE_MODES ? ; < Specifies the method of C-State enablement - Disabled, or C6. + CStatePlatformData UINT32 ? ; < This element specifies some pertinent data needed for the operation of the Cstate feature + ; < If CStateMode is CStateModeC6, this item is reserved + CStateIoBaseAddress UINT16 ? ; < This item specifies a free block of 8 consecutive bytes of I/O ports that + ; < can be used to allow the CPU to enter Cstates. + CpbMode PLATFORM_CPB_MODES ? ; < Specifies the method of core performance boost enablement - Disabled, or Auto. + UserOptionDmi BOOLEAN ? ; < When set to TRUE, the DMI data table is generated. + UserOptionPState BOOLEAN ? ; < When set to TRUE, the PState data tables are generated. + UserOptionCrat BOOLEAN ? ; < When set to TRUE, the CRAT data table is generated. + UserOptionCdit BOOLEAN ? ; < When set to TRUE, the CDIT data table is generated. + UserOptionSrat BOOLEAN ? ; < When set to TRUE, the SRAT data table is generated. + UserOptionSlit BOOLEAN ? ; < When set to TRUE, the SLIT data table is generated. + UserOptionWhea BOOLEAN ? ; < When set to TRUE, the WHEA data table is generated. + LowPowerPstateForProcHot PLATFORM_LOW_POWER_PSTATE_MODES ? ; < Specifies the method of low power Pstate for PROCHOT enablement - Disabled, or Auto. + PowerCeiling UINT32 ? ; < P-State Ceiling Enabling Deck - Max power milli-watts. + ForcePstateIndependent BOOLEAN ? ; < P-State _PSD independence or dependence. + PStatesInHpcMode BOOLEAN ? ; < High performance computing (HPC) mode + NumberOfIoApics UINT32 ? ; < Number of I/O APICs in the system + VrmProperties PLATFORM_VRM_CONFIGURATION (MaxVrmType) DUP ({}) ; < Several configuration settings for the voltage regulator modules. + ProcessorScopeInSb BOOLEAN ? ; < ACPI Processor Object in _SB scope + ProcessorScopeName0 CHAR8 ? ; < OEM specific 1st character of processor scope name. + ProcessorScopeName1 CHAR8 ? ; < OEM specific 2nd character of processor scope name. + GnbHdAudio UINT8 ? ; < Control GFX HD Audio controller(Used for HDMI and DP display output), + ; < essentially it enables function 1 of graphics device. + ; < @li 0 = HD Audio disable + ; < @li 1 = HD Audio enable + AbmSupport UINT8 ? ; < Automatic adjust LVDS/eDP Back light level support.It is + ; < characteristic specific to display panel which used by platform design. + ; < @li 0 = ABM support disabled + ; < @li 1 = ABM support enabled + DynamicRefreshRate UINT8 ? ; < Adjust refresh rate on LVDS/eDP. + LcdBackLightControl UINT16 ? ; < The PWM frequency to LCD backlight control. + ; < If equal to 0 backlight not controlled by iGPU. +PLATFORM_CONFIGURATION ENDS + + +; ********************************************************************* +; * Structures for: AmdInitLate +; ********************************************************************* + PROC_VERSION_LENGTH EQU 48 + MAX_DIMMS_PER_SOCKET EQU 16 + PROC_MANU_LENGTH EQU 29 + + ; Interface Parameter Structures + ; DMI Type4 - Processor ID +TYPE4_PROC_ID STRUCT + ProcIdLsd UINT32 ? ; < Lower half of 64b ID + ProcIdMsd UINT32 ? ; < Upper half of 64b ID +TYPE4_PROC_ID ENDS + + ; DMI Type 4 - Processor information +TYPE4_DMI_INFO STRUCT + T4ProcType UINT8 ? ; < CPU Type + T4ProcFamily UINT8 ? ; < Family 1 + T4ProcId TYPE4_PROC_ID {} ; < Id + T4Voltage UINT8 ? ; < Voltage + T4ExternalClock UINT16 ? ; < External clock + T4MaxSpeed UINT16 ? ; < Max speed + T4CurrentSpeed UINT16 ? ; < Current speed + T4Status UINT8 ? ; < Status + T4ProcUpgrade UINT8 ? ; < Up grade + T4CoreCount UINT8 ? ; < Core count + T4CoreEnabled UINT8 ? ; < Core Enable + T4ThreadCount UINT8 ? ; < Thread count + T4ProcCharacteristics UINT16 ? ; < Characteristics + T4ProcFamily2 UINT16 ? ; < Family 2 + T4ProcVersion CHAR8 (PROC_VERSION_LENGTH) DUP (?) ; < Cpu version + T4ProcManufacturer CHAR8 (PROC_MANU_LENGTH) DUP (?) ; < Manufacturer +TYPE4_DMI_INFO ENDS + + ; DMI Type 7 - Cache information +TYPE7_DMI_INFO STRUCT + T7CacheCfg UINT16 ? ; < Cache cfg + T7MaxCacheSize UINT16 ? ; < Max size + T7InstallSize UINT16 ? ; < Install size + T7SupportedSramType UINT16 ? ; < Supported Sram Type + T7CurrentSramType UINT16 ? ; < Current type + T7CacheSpeed UINT8 ? ; < Speed + T7ErrorCorrectionType UINT8 ? ; < ECC type + T7SystemCacheType UINT8 ? ; < Cache type + T7Associativity UINT8 ? ; < Associativity +TYPE7_DMI_INFO ENDS + + ; DMI Type 16 offset 04h - Location + + OtherLocation EQU 01h ; < Assign 01 to Other + UnknownLocation EQU 2 ; < Assign 02 to Unknown + SystemboardOrMotherboard EQU 3 ; < Assign 03 to systemboard or motherboard + IsaAddonCard EQU 4 ; < Assign 04 to ISA add-on card + EisaAddonCard EQU 5 ; < Assign 05 to EISA add-on card + PciAddonCard EQU 6 ; < Assign 06 to PCI add-on card + McaAddonCard EQU 7 ; < Assign 07 to MCA add-on card + PcmciaAddonCard EQU 8 ; < Assign 08 to PCMCIA add-on card + ProprietaryAddonCard EQU 9 ; < Assign 09 to proprietary add-on card + NuBus EQU 10 ; < Assign 0A to NuBus + Pc98C20AddonCard EQU 11 ; < Assign 0A0 to PC-98/C20 add-on card + Pc98C24AddonCard EQU 12 ; < Assign 0A1 to PC-98/C24 add-on card + Pc98EAddoncard EQU 13 ; < Assign 0A2 to PC-98/E add-on card + Pc98LocalBusAddonCard EQU 14 ; < Assign 0A3 to PC-98/Local bus add-on card +DMI_T16_LOCATION TEXTEQU <DWORD> ;} DMI_T16_LOCATION; + + ; DMI Type 16 offset 05h - Memory Error Correction + + OtherUse EQU 01h ; < Assign 01 to Other + UnknownUse EQU 2 ; < Assign 02 to Unknown + SystemMemory EQU 3 ; < Assign 03 to system memory + VideoMemory EQU 4 ; < Assign 04 to video memory + FlashMemory EQU 5 ; < Assign 05 to flash memory + NonvolatileRam EQU 6 ; < Assign 06 to non-volatile RAM + CacheMemory EQU 7 ; < Assign 07 to cache memory +DMI_T16_USE TEXTEQU <DWORD> ;} DMI_T16_USE; + + ; DMI Type 16 offset 07h - Maximum Capacity + + Dmi16OtherErrCorrection EQU 01h ; < Assign 01 to Other + Dmi16UnknownErrCorrection EQU 2 ; < Assign 02 to Unknown + Dmi16NoneErrCorrection EQU 3 ; < Assign 03 to None + Dmi16Parity EQU 4 ; < Assign 04 to parity + Dmi16SingleBitEcc EQU 5 ; < Assign 05 to Single-bit ECC + Dmi16MultiBitEcc EQU 6 ; < Assign 06 to Multi-bit ECC + Dmi16Crc EQU 7 ; < Assign 07 to CRC +DMI_T16_ERROR_CORRECTION TEXTEQU <DWORD> ;} DMI_T16_ERROR_CORRECTION; + + ; DMI Type 16 - Physical Memory Array +TYPE16_DMI_INFO STRUCT + Location DMI_T16_LOCATION ? ; < The physical location of the Memory Array, + ; < whether on the system board or an add-in board. + Use DMI_T16_USE ? ; < Identifies the function for which the array + ; < is used. + MemoryErrorCorrection DMI_T16_ERROR_CORRECTION ? ; < The primary hardware error correction or + ; < detection method supported by this memory array. + MaximumCapacity UINT32 ? ; < The maximum memory capacity, in kilobytes, + ; < for the array. + NumberOfMemoryDevices UINT16 ? ; < The number of slots or sockets available + ; < for memory devices in this array. + ExtMaxCapacity UINT64 ? ; < The maximum memory capacity, in bytes, + ; < for this array. +TYPE16_DMI_INFO ENDS + + ; DMI Type 17 offset 0Eh - Form Factor + OtherFormFactor EQU 01h ; < Assign 01 to Other + UnknowFormFactor EQU 2 ; < Assign 02 to Unknown + SimmFormFactor EQU 3 ; < Assign 03 to SIMM + SipFormFactor EQU 4 ; < Assign 04 to SIP + ChipFormFactor EQU 5 ; < Assign 05 to Chip + DipFormFactor EQU 6 ; < Assign 06 to DIP + ZipFormFactor EQU 7 ; < Assign 07 to ZIP + ProprietaryCardFormFactor EQU 8 ; < Assign 08 to Proprietary Card + DimmFormFactorFormFactor EQU 9 ; < Assign 09 to DIMM + TsopFormFactor EQU 10 ; < Assign 10 to TSOP + RowOfChipsFormFactor EQU 11 ; < Assign 11 to Row of chips + RimmFormFactor EQU 12 ; < Assign 12 to RIMM + SodimmFormFactor EQU 13 ; < Assign 13 to SODIMM + SrimmFormFactor EQU 14 ; < Assign 14 to SRIMM + FbDimmFormFactor EQU 15 ; < Assign 15 to FB-DIMM +DMI_T17_FORM_FACTOR TEXTEQU <DWORD> + + ; DMI Type 17 offset 12h - Memory Type + OtherMemType EQU 01h ; < Assign 01 to Other + UnknownMemType EQU 2 ; < Assign 02 to Unknown + DramMemType EQU 3 ; < Assign 03 to DRAM + EdramMemType EQU 4 ; < Assign 04 to EDRAM + VramMemType EQU 5 ; < Assign 05 to VRAM + SramMemType EQU 6 ; < Assign 06 to SRAM + RamMemType EQU 7 ; < Assign 07 to RAM + RomMemType EQU 8 ; < Assign 08 to ROM + FlashMemType EQU 9 ; < Assign 09 to Flash + EepromMemType EQU 10 ; < Assign 10 to EEPROM + FepromMemType EQU 11 ; < Assign 11 to FEPROM + EpromMemType EQU 12 ; < Assign 12 to EPROM + CdramMemType EQU 13 ; < Assign 13 to CDRAM + ThreeDramMemType EQU 14 ; < Assign 14 to 3DRAM + SdramMemType EQU 15 ; < Assign 15 to SDRAM + SgramMemType EQU 16 ; < Assign 16 to SGRAM + RdramMemType EQU 17 ; < Assign 17 to RDRAM + DdrMemType EQU 18 ; < Assign 18 to DDR + Ddr2MemType EQU 19 ; < Assign 19 to DDR2 + Ddr2FbdimmMemType EQU 20 ; < Assign 20 to DDR2 FB-DIMM + Ddr3MemType EQU 24 ; < Assign 24 to DDR3 + Fbd2MemType EQU 25 ; < Assign 25 to FBD2 +DMI_T17_MEMORY_TYPE TEXTEQU <DWORD> + + ; DMI Type 17 offset 13h - Type Detail +DMI_T17_TYPE_DETAIL STRUCT + Reserved1 UINT16 ? +; OUT UINT16 Reserved1:1; ; < Reserved +; OUT UINT16 Other:1; ; < Other +; OUT UINT16 Unknown:1; ; < Unknown +; OUT UINT16 FastPaged:1; ; < Fast-Paged +; OUT UINT16 StaticColumn:1; ; < Static column +; OUT UINT16 PseudoStatic:1; ; < Pseudo-static +; OUT UINT16 Rambus:1; ; < RAMBUS +; OUT UINT16 Synchronous:1; ; < Synchronous +; OUT UINT16 Cmos:1; ; < CMOS +; OUT UINT16 Edo:1; ; < EDO +; OUT UINT16 WindowDram:1; ; < Window DRAM +; OUT UINT16 CacheDram:1; ; < Cache Dram +; OUT UINT16 NonVolatile:1; ; < Non-volatile +; OUT UINT16 Registered:1; ; < Registered (Buffered) +; OUT UINT16 Unbuffered:1; ; < Unbuffered (Unregistered) +; OUT UINT16 Reserved2:1; ; < Reserved +DMI_T17_TYPE_DETAIL ENDS + + ; DMI Type 17 - Memory Device +TYPE17_DMI_INFO STRUCT + TotalWidth UINT16 ? ; < Total Width, in bits, of this memory device, including any check or error-correction bits. + DataWidth UINT16 ? ; < Data Width, in bits, of this memory device. + MemorySize UINT16 ? ; < The size of the memory device. + FormFactor DMI_T17_FORM_FACTOR ? ; < The implementation form factor for this memory device. + DeviceSet UINT8 ? ; < Identifies when the Memory Device is one of a set of + ; < Memory Devices that must be populated with all devices of + ; < the same type and size, and the set to which this device belongs. + DeviceLocator CHAR8 (8) DUP (?) ; < The string number of the string that identifies the physically labeled socket or board position where the memory device is located. + BankLocator CHAR8 (10) DUP (?) ; < The string number of the string that identifies the physically labeled bank where the memory device is located. + MemoryType DMI_T17_MEMORY_TYPE ? ; < The type of memory used in this device. + TypeDetail DMI_T17_TYPE_DETAIL {} ; < Additional detail on the memory device type + Speed UINT16 ? ; < Identifies the speed of the device, in megahertz (MHz). + ManufacturerIdCode UINT64 ? ; < Manufacturer ID code. + SerialNumber CHAR8 (9) DUP (?) ; < Serial Number. + PartNumber CHAR8 (19) DUP (?) ; < Part Number. + Attributes UINT8 ? ; < Bits 7-4: Reserved, Bits 3-0: rank. + ExtSize UINT32 ? ; < Extended Size. + ConfigSpeed UINT16 ? ; < Configured memory clock speed +TYPE17_DMI_INFO ENDS + + ; Memory DMI Type 17 and 20 - for memory use +MEM_DMI_INFO STRUCT + TotalWidth UINT16 ? ; < Total Width, in bits, of this memory device, including any check or error-correction bits. + DataWidth UINT16 ? ; < Data Width, in bits, of this memory device. + MemorySize UINT16 ? ; < The size of the memory device. + FormFactor DMI_T17_FORM_FACTOR ? ; < The implementation form factor for this memory device. + DeviceLocator UINT8 ? ; < The string number of the string that identifies the physically labeled socket or board position where the memory device is located. + BankLocator UINT8 ? ; < The string number of the string that identifies the physically labeled bank where the memory device is located. + Speed UINT16 ? ; < Identifies the speed of the device, in megahertz (MHz). + ManufacturerIdCode UINT64 ? ; < Manufacturer ID code. + SerialNumber UINT8 (4) DUP (?) ; < Serial Number. + PartNumber UINT8 (18) DUP (?) ; < Part Number. + Attributes UINT8 ? ; < Bits 7-4: Reserved, Bits 3-0: rank. + ExtSize UINT32 ? ; < Extended Size. + Socket UINT8 ? +; OUT UINT8 Socket:3 ; < Socket ID +; OUT UINT8 Channel:2 ; < Channel ID +; OUT UINT8 Dimm:2 ; < DIMM ID +; OUT UINT8 DimmPresent:1 ; < Dimm Present + StartingAddr UINT32 ? ; < The physical address, in kilobytes, of a range + ; < of memory mapped to the referenced Memory Device. + EndingAddr UINT32 ? ; < The handle, or instance number, associated with + ; < the Memory Device structure to which this address + ; < range is mapped. + ConfigSpeed UINT16 ? ; < Configured memory clock speed + ExtStartingAddr UINT64 ? ; < The physical address, in bytes, of a range of + ; < memory mapped to the referenced Memory Device. + ExtEndingAddr UINT64 ? ; < The physical ending address, in bytes, of the last of + ; < a range of addresses mapped to the referenced Memory Device. +MEM_DMI_INFO ENDS + + ; DMI Type 19 - Memory Array Mapped Address +TYPE19_DMI_INFO STRUCT + StartingAddr UINT32 ? ; < The physical address, in kilobytes, + ; < of a range of memory mapped to the + ; < specified physical memory array. + EndingAddr UINT32 ? ; < The physical ending address of the + ; < last kilobyte of a range of addresses + ; < mapped to the specified physical memory array. + MemoryArrayHandle UINT16 ? ; < The handle, or instance number, associated + ; < with the physical memory array to which this + ; < address range is mapped. + PartitionWidth UINT8 ? ; < Identifies the number of memory devices that + ; < form a single row of memory for the address + ; < partition defined by this structure. + ExtStartingAddr UINT64 ? ; < The physical address, in bytes, of a range of + ; < memory mapped to the specified Physical Memory Array. + ExtEndingAddr UINT64 ? ; < The physical address, in bytes, of a range of + ; < memory mapped to the specified Physical Memory Array. +TYPE19_DMI_INFO ENDS + +; DMI Type 20 - Memory Device Mapped Address +TYPE20_DMI_INFO STRUCT + StartingAddr UINT32 ? ; < The physical address, in kilobytes, of a range + ; < of memory mapped to the referenced Memory Device. + EndingAddr UINT32 ? ; < The handle, or instance number, associated with + ; < the Memory Device structure to which this address + ; < range is mapped. + MemoryDeviceHandle UINT16 ? ; < The handle, or instance number, associated with + ; < the Memory Device structure to which this address + ; < range is mapped. + MemoryArrayMappedAddressHandle UINT16 ? ; < The handle, or instance number, associated + ; < with the Memory Array Mapped Address structure to + ; < which this device address range is mapped. + PartitionRowPosition UINT8 ? ; < Identifies the position of the referenced Memory + ; < Device in a row of the address partition. + InterleavePosition UINT8 ? ; < The position of the referenced Memory Device in + ; < an interleave. + InterleavedDataDepth UINT8 ? ; < The maximum number of consecutive rows from the + ; < referenced Memory Device that are accessed in a + ; < single interleaved transfer. + ExtStartingAddr UINT64 ? ; < The physical address, in bytes, of a range of + ; < memory mapped to the referenced Memory Device. + ExtEndingAddr UINT64 ? ; < The physical ending address, in bytes, of the last of + ; < a range of addresses mapped to the referenced Memory Device. +TYPE20_DMI_INFO ENDS + + ; Collection of pointers to the DMI records +DMI_INFO STRUCT + T4 TYPE4_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 4 struc + T7L1 TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 7 struc 1 + T7L2 TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 7 struc 2 + T7L3 TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 7 struc 3 + T16 TYPE16_DMI_INFO {} ; < Type 16 struc + T17 TYPE17_DMI_INFO (MAX_SOCKETS_SUPPORTED * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL) DUP ({}) ; < Type 17 struc + T19 TYPE19_DMI_INFO {} ; < Type 19 struc + T20 TYPE20_DMI_INFO (MAX_SOCKETS_SUPPORTED * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL) DUP ({}) ; < Type 20 struc +DMI_INFO ENDS + + + +; ********************************************************************* +; * Interface call: AllocateExecutionCache +; ********************************************************************* + MAX_CACHE_REGIONS EQU 3 + + ; AllocateExecutionCache sub param structure for cached memory region +EXECUTION_CACHE_REGION STRUCT + ExeCacheStartAddr UINT32 ? ; < Start address + ExeCacheSize UINT32 ? ; < Size +EXECUTION_CACHE_REGION ENDS + +; ********************************************************************* +; * Interface call: AmdGetAvailableExeCacheSize +; ********************************************************************* + ; Get available Cache remain +AMD_GET_EXE_SIZE_PARAMS STRUCT + StdHeader AMD_CONFIG_PARAMS {} ; < Standard header + AvailableExeCacheSize UINT32 ? ; < Remain size +AMD_GET_EXE_SIZE_PARAMS ENDS + + + + + + + ; Selection type for core leveling + CORE_LEVEL_LOWEST EQU 0 ; < Level to lowest common denominator + CORE_LEVEL_TWO EQU 1 ; < Level to 2 cores + CORE_LEVEL_POWER_OF_TWO EQU 2 ; < Level to 1,2,4 or 8 + CORE_LEVEL_NONE EQU 3 ; < Do no leveling + CORE_LEVEL_COMPUTE_UNIT EQU 4 ; < Level cores to one core per compute unit + CORE_LEVEL_ONE EQU 5 ; < Level to 1 core + CORE_LEVEL_THREE EQU 6 ; < Level to 3 cores + CORE_LEVEL_FOUR EQU 7 ; < Level to 4 cores + CORE_LEVEL_FIVE EQU 8 ; < Level to 5 cores + CORE_LEVEL_SIX EQU 9 ; < Level to 6 cores + CORE_LEVEL_SEVEN EQU 10 ; < Level to 7 cores + CORE_LEVEL_EIGHT EQU 11 ; < Level to 8 cores + CORE_LEVEL_NINE EQU 12 ; < Level to 9 cores + CORE_LEVEL_TEN EQU 13 ; < Level to 10 cores + CORE_LEVEL_ELEVEN EQU 14 ; < Level to 11 cores + CORE_LEVEL_TWELVE EQU 15 ; < Level to 12 cores + CORE_LEVEL_THIRTEEN EQU 16 ; < Level to 13 cores + CORE_LEVEL_FOURTEEN EQU 17 ; < Level to 14 cores + CORE_LEVEL_FIFTEEN EQU 18 ; < Level to 15 cores + CoreLevelModeMax EQU 19 ; < Used for bounds checking +CORE_LEVELING_TYPE TEXTEQU <DWORD> + + +; *********************************************************************** +; * +; * AGESA Basic Level interface structure definition and function prototypes +; * +; ********************************************************************** + +; ********************************************************************* +; * Interface call: AmdCreateStruct +; ********************************************************************* + +; ********************************************************************* +; * Interface call: AmdReleaseStruct +; ********************************************************************* + +; ********************************************************************* +; * Interface call: AmdInitReset +; ********************************************************************* + ; AmdInitReset param structure +AMD_RESET_PARAMS STRUCT + StdHeader AMD_CONFIG_PARAMS {} ; < Standard header + CacheRegion EXECUTION_CACHE_REGION (3) DUP ({}) ; < The cached memory region + HtConfig AMD_HT_RESET_INTERFACE {} ; < The interface for Ht Recovery + FchInterface FCH_RESET_INTERFACE {} ; Interface for FCH configuration +AMD_RESET_PARAMS ENDS + +; ********************************************************************* +; * Interface call: AmdInitEarly +; ********************************************************************* + ; InitEarly param structure + + ; Provide defaults or customizations to each service performed in AmdInitEarly. + +AMD_EARLY_PARAMS STRUCT + StdHeader AMD_CONFIG_PARAMS {} ; < The standard header + CacheRegion EXECUTION_CACHE_REGION (3) DUP ({}) ; < Execution Map Interface + PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics. + HtConfig AMD_HT_INTERFACE {} ; < HyperTransport Interface + GnbConfig GNB_CONFIGURATION {} ; < GNB configuration +AMD_EARLY_PARAMS ENDS + +; ********************************************************************* +; * Interface call: AmdInitPost +; ********************************************************************* + ; AmdInitPost param structure +AMD_POST_PARAMS STRUCT + StdHeader AMD_CONFIG_PARAMS {} ; < Standard header + PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics. + MemConfig MEM_PARAMETER_STRUCT {} ; < Memory post param + GnbPostConfig GNB_POST_CONFIGURATION {} +AMD_POST_PARAMS ENDS + +; ********************************************************************* +; * Interface call: AmdInitEnv +; ********************************************************************* + ; AmdInitEnv param structure +AMD_ENV_PARAMS STRUCT + StdHeader AMD_CONFIG_PARAMS {} ; < Standard header + PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics. + GnbEnvConfiguration GNB_ENV_CONFIGURATION {} ; < GNB configuration + FchInterface FCH_INTERFACE {} ; FCH configuration +AMD_ENV_PARAMS ENDS + +; ********************************************************************* +; * Interface call: AmdInitMid +; ********************************************************************* + ; AmdInitMid param structure +AMD_MID_PARAMS STRUCT + StdHeader AMD_CONFIG_PARAMS {} ; < Standard header + PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics + GnbMidConfiguration GNB_MID_CONFIGURATION {} ; < GNB configuration + FchInterface FCH_INTERFACE {} ; FCH configuration +AMD_MID_PARAMS ENDS + +; ********************************************************************* +; * Interface call: AmdInitLate +; ********************************************************************* + ; AmdInitLate param structure +AMD_LATE_PARAMS STRUCT + StdHeader AMD_CONFIG_PARAMS {} ; < Standard header + PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics. + IvrsExclusionRangeList POINTER ? ; < IVMD exclusion range descriptor + DmiTable POINTER ? ; < DMI Interface + AcpiPState POINTER ? ; < Acpi Pstate SSDT Table + AcpiSrat POINTER ? ; < SRAT Table + AcpiSlit POINTER ? ; < SLIT Table + AcpiWheaMce POINTER ? ; < WHEA MCE Table + AcpiWheaCmc POINTER ? ; < WHEA CMC Table + AcpiAlib POINTER ? ; < ALIB Table + AcpiIvrs POINTER ? ; < IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table + AcpiCrat POINTER ? ; < Component Resource Affinity Table table + AcpiCdit POINTER ? ; < Component Locality Distance Information table +AMD_LATE_PARAMS ENDS + +; ********************************************************************* +; * Interface call: AmdInitRecovery +; ********************************************************************* + ; CPU Recovery Parameters +AMD_CPU_RECOVERY_PARAMS STRUCT + StdHeader AMD_CONFIG_PARAMS {} ; < Standard Header + PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics +AMD_CPU_RECOVERY_PARAMS ENDS + + ; AmdInitRecovery param structure +AMD_RECOVERY_PARAMS STRUCT + StdHeader AMD_CONFIG_PARAMS {} ; < Standard header + MemConfig MEM_PARAMETER_STRUCT {} ; < Memory post param + CacheRegion EXECUTION_CACHE_REGION (3) DUP ({}) ; < The cached memory region. And the max cache region is 3 + CpuRecoveryParams AMD_CPU_RECOVERY_PARAMS {} ; < Params for CPU related recovery init. +AMD_RECOVERY_PARAMS ENDS + + +; ********************************************************************* +; * Interface call: AmdInitResume +; ********************************************************************* + ; AmdInitResume param structure +AMD_RESUME_PARAMS STRUCT + StdHeader AMD_CONFIG_PARAMS {} ; < Standard header + PlatformConfig PLATFORM_CONFIGURATION {} ; < Platform operational characteristics + S3DataBlock AMD_S3_PARAMS {} ; < Save state data +AMD_RESUME_PARAMS ENDS + +; ********************************************************************* +; * Interface call: AmdS3LateRestore +; ********************************************************************* + ; AmdS3LateRestore param structure +AMD_S3LATE_PARAMS STRUCT + StdHeader AMD_CONFIG_PARAMS {} ; < Standard header + PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics. + S3DataBlock AMD_S3_PARAMS {} ; < Save state data +AMD_S3LATE_PARAMS ENDS + +; ********************************************************************* +; * Interface call: AmdS3Save +; ********************************************************************* + ; AmdS3Save param structure +AMD_S3SAVE_PARAMS STRUCT + StdHeader AMD_CONFIG_PARAMS {} ; < Standard header + PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics. + S3DataBlock AMD_S3_PARAMS {} ; < Standard header + FchInterface FCH_INTERFACE {} ; FCH configuration +AMD_S3SAVE_PARAMS ENDS + + ; General Services API + + +; ********************************************************************* +; * Interface service call: AmdGetApicId +; ********************************************************************* + ; Request the APIC ID of a particular core. + +AMD_APIC_PARAMS STRUCT + StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services. + Socket UINT8 ? ; < The Core's Socket. + Core UINT8 ? ; < The Core id. + IsPresent BOOLEAN ? ; < The Core is present, and ApicAddress is valid. + ApicAddress UINT8 ? ; < The Core's APIC ID. +AMD_APIC_PARAMS ENDS + +; ********************************************************************* +; * Interface service call: AmdGetPciAddress +; ********************************************************************* + ; Request the PCI Address of a Processor Module (that is, its Northbridge) + +AMD_GET_PCI_PARAMS STRUCT + StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services. + Socket UINT8 ? ; < The Processor's socket + Module UINT8 ? ; < The Module in that Processor + IsPresent BOOLEAN ? ; < The Core is present, and PciAddress is valid. + PciAddress PCI_ADDR {} ; < The Processor's PCI Config Space address (Function 0, Register 0) +AMD_GET_PCI_PARAMS ENDS + +; ********************************************************************* +; * Interface service call: AmdIdentifyCore +; ********************************************************************* + ; Request the identity (Socket, Module, Core) of the current Processor Core + +AMD_IDENTIFY_PARAMS STRUCT + StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services. + Socket UINT8 ? ; < The current Core's Socket + Module UINT8 ? ; < The current Core's Processor Module + Core UINT8 ? ; < The current Core's core id. +AMD_IDENTIFY_PARAMS ENDS + +; ********************************************************************* +; * Interface service call: AmdReadEventLog +; ********************************************************************* + ; An Event Log Entry. +EVENT_PARAMS STRUCT + StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services. + EventClass UINT32 ? ; < The severity of this event, matches AGESA_STATUS. + EventInfo UINT32 ? ; < The unique event identifier, zero means "no event". + DataParam1 UINT32 ? ; < Data specific to the Event. + DataParam2 UINT32 ? ; < Data specific to the Event. + DataParam3 UINT32 ? ; < Data specific to the Event. + DataParam4 UINT32 ? ; < Data specific to the Event. +EVENT_PARAMS ENDS + +; ********************************************************************* +; * Interface service call: AmdIdentifyDimm +; ********************************************************************* + ; Request the identity of dimm from system address + +AMD_IDENTIFY_DIMM STRUCT + StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services. + MemoryAddress UINT64 ? ; < System Address that needs to be translated to dimm identification. + SocketId UINT8 ? ; < The socket on which the targeted address locates. + MemChannelId UINT8 ? ; < The channel on which the targeted address locates. + DimmId UINT8 ? ; < The dimm on which the targeted address locates. +AMD_IDENTIFY_DIMM ENDS + + ; Data structure for the Mapping Item between Unified ID for IDS Setup Option + ; and the option value. + +IDS_NV_ITEM STRUCT + IdsNvId UINT16 ? ; < Unified ID for IDS Setup Option. + IdsNvValue UINT16 ? ; < The value of IDS Setup Option. +IDS_NV_ITEM ENDS + + ; Data Structure for IDS CallOut Function +IDS_CALLOUT_STRUCT STRUCT + StdHeader AMD_CONFIG_PARAMS {} ; < The Standard Header for AGESA Service + IdsNvPtr POINTER ? ; < Memory Pointer of IDS NV Table + Reserved UINT32 ? ; < reserved +IDS_CALLOUT_STRUCT ENDS + + AGESA_IDS_DFT_VAL EQU 0FFFFh; < Default value of every uninitlized NV item, the action for it will be ignored + AGESA_IDS_NV_END EQU 0FFFFh; < Flag specify end of option structure +; WARNING: Don't change the comment below, it used as signature for script +; AGESA IDS NV ID Definitions + AGESA_IDS_EXT_ID_START EQU 0000h; < specify the start of external NV id + + AGESA_IDS_NV_UCODE EQU 0001h; < Enable or disable microcode patching + + AGESA_IDS_NV_TARGET_PSTATE EQU 0002h; < Set the P-state required to be activated + AGESA_IDS_NV_POSTPSTATE EQU 0003h; < Set the P-state required to be activated through POST + + AGESA_IDS_NV_BANK_INTERLEAVE EQU 0004h; < Enable or disable Bank Interleave + AGESA_IDS_NV_CHANNEL_INTERLEAVE EQU 0005h; < Enable or disable Channel Interleave + AGESA_IDS_NV_NODE_INTERLEAVE EQU 0006h; < Enable or disable Node Interleave + AGESA_IDS_NV_MEMHOLE EQU 0007h; < Enables or disable memory hole + + AGESA_IDS_NV_SCRUB_REDIRECTION EQU 0008h; < Enable or disable a write to dram with corrected data + AGESA_IDS_NV_DRAM_SCRUB EQU 0009h; < Set the rate of background scrubbing for DRAM + AGESA_IDS_NV_DCACHE_SCRUB EQU 000Ah; < Set the rate of background scrubbing for the DCache. + AGESA_IDS_NV_L2_SCRUB EQU 000Bh; < Set the rate of background scrubbing for the L2 cache + AGESA_IDS_NV_L3_SCRUB EQU 000Ch; < Set the rate of background scrubbing for the L3 cache + AGESA_IDS_NV_ICACHE_SCRUB EQU 000Dh; < Set the rate of background scrubbing for the Icache + AGESA_IDS_NV_SYNC_ON_ECC_ERROR EQU 000Eh; < Enable or disable the sync flood on un-correctable ECC error + AGESA_IDS_NV_ECC_SYMBOL_SIZE EQU 000Fh; < Set ECC symbol size + + AGESA_IDS_NV_ALL_MEMCLKS EQU 0010h; < Enable or disable all memory clocks enable + AGESA_IDS_NV_DCT_GANGING_MODE EQU 0011h; < Set the Ganged mode + AGESA_IDS_NV_DRAM_BURST_LENGTH32 EQU 0012h; < Set the DRAM Burst Length 32 + AGESA_IDS_NV_MEMORY_POWER_DOWN EQU 0013h; < Enable or disable Memory power down mode + AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE EQU 0014h; < Set the Memory power down mode + AGESA_IDS_NV_DLL_SHUT_DOWN EQU 0015h; < Enable or disable DLLShutdown + AGESA_IDS_NV_ONLINE_SPARE EQU 0016h; < Enable or disable the Dram controller to designate a DIMM bank as a spare for logical swap + + AGESA_IDS_NV_HT_ASSIST EQU 0017h; < Enable or Disable HT Assist + AGESA_IDS_NV_ATMMODE EQU 0018h; < Enable or Disable ATM mode + + AGESA_IDS_NV_HDTOUT EQU 0019h; < Enable or disable HDTOUT feature + + AGESA_IDS_NV_HTLINKSOCKET EQU 001Ah; < HT Link Socket + AGESA_IDS_NV_HTLINKPORT EQU 001Bh; < HT Link Port + AGESA_IDS_NV_HTLINKFREQ EQU 001Ch; < HT Link Frequency + AGESA_IDS_NV_HTLINKWIDTHIN EQU 001Dh; < HT Link In Width + AGESA_IDS_NV_HTLINKWIDTHOUT EQU 001Eh; < HT Link Out Width + + AGESA_IDS_NV_GNBHDAUDIOEN EQU 001Fh; < Enable or disable GNB HD Audio + + AGESA_IDS_NV_CPB_EN EQU 0020h; < Core Performance Boost + + AGESA_IDS_NV_HTC_EN EQU 0021h; < HTC Enable + AGESA_IDS_NV_HTC_OVERRIDE EQU 0022h; < HTC Override + AGESA_IDS_NV_HTC_PSTATE_LIMIT EQU 0023h; < HTC P-state limit select + AGESA_IDS_NV_HTC_TEMP_HYS EQU 0024h; < HTC Temperature Hysteresis + AGESA_IDS_NV_HTC_ACT_TEMP EQU 0025h; < HTC Activation Temp + + AGESA_IDS_NV_POWER_POLICY EQU 0026h; < Select Platform Power Policy + AGESA_IDS_EXT_ID_END EQU 0027h; < specify the end of external NV ID + + IDS_EX_NV_ID TEXTEQU <DWORD> diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/amd.inc b/src/vendorcode/amd/agesa/f15tn/Legacy/amd.inc new file mode 100644 index 0000000..9f9bac9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Legacy/amd.inc @@ -0,0 +1,488 @@ +; **************************************************************************** +; * +; * @file +; * +; * Agesa structures and definitions +; * +; * Contains AMD AGESA core interface +; * +; * @xrefitem bom "File Content Label" "Release Content" +; * @e project: AGESA +; * @e sub-project: Include +; * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ +; +; **************************************************************************** +; * +; * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; * +; * AMD is granting you permission to use this software (the Materials) +; * pursuant to the terms and conditions of your Software License Agreement +; * with AMD. This header does *NOT* give you permission to use the Materials +; * or any rights under AMD's intellectual property. Your use of any portion +; * of these Materials shall constitute your acceptance of those terms and +; * conditions. If you do not agree to the terms and conditions of the Software +; * License Agreement, please do not use any portion of these Materials. +; * +; * CONFIDENTIALITY: The Materials and all other information, identified as +; * confidential and provided to you by AMD shall be kept confidential in +; * accordance with the terms and conditions of the Software License Agreement. +; * +; * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; * +; * AMD does not assume any responsibility for any errors which may appear in +; * the Materials or any other related information provided to you by AMD, or +; * result from use of the Materials or any related information. +; * +; * You agree that you will not reverse engineer or decompile the Materials. +; * +; * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; * further information, software, technical information, know-how, or show-how +; * available to you. Additionally, AMD retains the right to modify the +; * Materials at any time, without notice, and is not obligated to provide such +; * modified Materials to you. +; * +; * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; * subject to the restrictions as set forth in FAR 52.227-14 and +; * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; * Government constitutes acknowledgement of AMD's proprietary rights in them. +; * +; * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; * direct product thereof will be exported directly or indirectly, into any +; * country prohibited by the United States Export Administration Act and the +; * regulations thereunder, without the required authorization from the U.S. +; * government nor will be used for any purpose prohibited by the same. +; * +; ************************************************************************** + + +UINT64 TEXTEQU <QWORD> +UINT32 TEXTEQU <DWORD> +UINT16 TEXTEQU <WORD> +UINT8 TEXTEQU <BYTE> +CHAR8 TEXTEQU <BYTE> +BOOLEAN TEXTEQU <BYTE> +POINTER TEXTEQU <DWORD> + + ; AGESA Types and Definitions + + AGESA_REVISION EQU "Arch2008" + AGESA_ID EQU "AGESA" + + LAST_ENTRY EQU 0FFFFFFFFh + IMAGE_SIGNATURE EQU 'DMA$' + IOCF8 EQU 0CF8h + IOCFC EQU 0CFCh + + ; The return status for all AGESA public services. + + ; Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK + ; will have log entries with more detail. + + AGESA_SUCCESS EQU 0 ; < The service completed normally. Info may be logged. + AGESA_UNSUPPORTED EQU 1 ; < The dispatcher or create struct had an unimplemented function requested. + ; < Not logged. + AGESA_BOUNDS_CHK EQU 2 ; < A dynamic parameter was out of range and the service was not provided. + ; < Example, memory address not installed, heap buffer handle not found. + ; < Not Logged. + ; AGESA_STATUS of greater severity (the ones below this line), always have a log entry available. + AGESA_ALERT EQU 3 ; < An observed condition, but no loss of function. + ; < See log. Example, HT CRC. + AGESA_WARNING EQU 4 ; < Possible or minor loss of function. See Log. + AGESA_ERROR EQU 5 ; < Significant loss of function, boot may be possible. See Log. + AGESA_CRITICAL EQU 6 ; < Continue boot only to notify user. See Log. + AGESA_FATAL EQU 7 ; < Halt booting. See Log. + AgesaStatusMax EQU 8 ; < Not a status, use for limit checking. +AGESA_STATUS TEXTEQU <DWORD> + +; For checking whether a status is at or above the mandatory log level. +AGESA_STATUS_LOG_LEVEL EQU AGESA_ALERT + + CALLOUT_ENTRY TEXTEQU <POINTER> + IMAGE_ENTRY TEXTEQU <POINTER> + MODULE_ENTRY TEXTEQU <POINTER> + +; This allocation type is used by the AmdCreateStruct entry point + PreMemHeap EQU 0 ; < Create heap in cache. + PostMemDram EQU 1 ; < Create heap in memory. + ByHost EQU 2 ; < Create heap by Host. +ALLOCATION_METHOD TEXTEQU <DWORD> + + ; These width descriptors are used by the library function, and others, to specify the data size + AccessWidth8 EQU 1 ; < Access width is 8 bits. + AccessWidth16 EQU 2 ; < Access width is 16 bits. + AccessWidth32 EQU 3 ; < Access width is 32 bits. + AccessWidth64 EQU 4 ; < Access width is 64 bits. + + AccessS3SaveWidth8 EQU 81h ; < Save 8 bits data. + AccessS3SaveWidth16 EQU 130 ; < Save 16 bits data. + AccessS3SaveWidth32 EQU 131 ; < Save 32 bits data. + AccessS3SaveWidth64 EQU 132 ; < Save 64 bits data. +ACCESS_WIDTH TEXTEQU <DWORD> + + ; AGESA struct name + + ; AGESA BASIC FUNCTIONS + AMD_INIT_RECOVERY EQU 00020000h + AMD_CREATE_STRUCT EQU 00020001h + AMD_INIT_EARLY EQU 00020002h + AMD_INIT_ENV EQU 00020003h + AMD_INIT_LATE EQU 00020004h + AMD_INIT_MID EQU 00020005h + AMD_INIT_POST EQU 00020006h + AMD_INIT_RESET EQU 00020007h + AMD_INIT_RESUME EQU 00020008h + AMD_RELEASE_STRUCT EQU 00020009h + AMD_S3LATE_RESTORE EQU 0002000Ah + AMD_S3_SAVE EQU 0002000Bh + AMD_GET_APIC_ID EQU 0002000Ch + AMD_GET_PCI_ADDRESS EQU 0002000Dh + AMD_IDENTIFY_CORE EQU 0002000Eh + AMD_READ_EVENT_LOG EQU 0002000Fh + AMD_GET_EXECACHE_SIZE EQU 00020010h + AMD_LATE_RUN_AP_TASK EQU 00020011h + AMD_IDENTIFY_DIMMS EQU 00020012h +AGESA_STRUCT_NAME TEXTEQU <DWORD> + + + ; ResetType constant values + WARM_RESET_WHENEVER EQU 1 + COLD_RESET_WHENEVER EQU 2 + WARM_RESET_IMMEDIATELY EQU 3 + COLD_RESET_IMMEDIATELY EQU 4 + + + ; AGESA Structures + + ; The standard header for all AGESA services. +AMD_CONFIG_PARAMS STRUCT + ImageBasePtr UINT32 ? ; < The AGESA Image base address. + Func UINT32 ? ; < The service desired, @sa dispatch.h. + AltImageBasePtr UINT32 ? ; < Alternate Image location + CalloutPtr CALLOUT_ENTRY ? ; < For Callout from AGESA + HeapStatus UINT8 ? ; < For heap status from boot time slide. + HeapBasePtr UINT64 ? ; < Location of the heap + Reserved UINT8 (7) DUP (?) ; < This space is reserved for future use. +AMD_CONFIG_PARAMS ENDS + + + ; Create Struct Interface. +AMD_INTERFACE_PARAMS STRUCT + StdHeader AMD_CONFIG_PARAMS {} ; < Config header + AgesaFunctionName AGESA_STRUCT_NAME ? ; < The service to init, @sa dispatch.h + AllocationMethod ALLOCATION_METHOD ? ; < How to handle buffer allocation + NewStructSize UINT32 ? ; < The size of the allocated data, in for ByHost, else out only. + NewStructPtr POINTER ? ; < The struct for the service. + ; < The struct to init for ByHost allocation, + ; < the initialized struct on return. +AMD_INTERFACE_PARAMS ENDS + + FUNC_0 EQU 0 ; bit-placed for PCI address creation + FUNC_1 EQU 1 + FUNC_2 EQU 2 + FUNC_3 EQU 3 + FUNC_4 EQU 4 + FUNC_5 EQU 5 + FUNC_6 EQU 6 + FUNC_7 EQU 7 + + ; AGESA Binary module header structure +AMD_IMAGE_HEADER STRUCT + Signature UINT32 ? ; < Binary Signature + CreatorID CHAR8 (8) DUP (?) ; < 8 characters ID + Version CHAR8 (12) DUP (?) ; < 12 characters version + ModuleInfoOffset UINT32 ? ; < Offset of module + EntryPointAddress UINT32 ? ; < Entry address + ImageBase UINT32 ? ; < Image base + RelocTableOffset UINT32 ? ; < Relocate Table offset + ImageSize UINT32 ? ; < Size + Checksum UINT16 ? ; < Checksum + ImageType UINT8 ? ; < Type + V_Reserved UINT8 ? ; < Reserved +AMD_IMAGE_HEADER ENDS + ; AGESA Binary module header structure +AMD_MODULE_HEADER STRUCT + ModuleHeaderSignature UINT32 ? ; < Module signature + ModuleIdentifier CHAR8 (8) DUP (?) ; < 8 characters ID + ModuleVersion CHAR8 (12) DUP (?) ; < 12 characters version + ModuleDispatcher POINTER ? ; < A pointer point to dispatcher + NextBlock POINTER ? ; < Next module header link +AMD_MODULE_HEADER ENDS + +; AMD_CODE_HEADER Signatures. +AGESA_CODE_SIGNATURE TEXTEQU <'!', '!', 'A', 'G', 'E', 'S', 'A', ' '> +CIMXNB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'> +CIMXSB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'> + +; AGESA_CODE_SIGNATURE +AMD_CODE_HEADER STRUCT + Signature CHAR8 (8) DUP (?) ; < code header Signature + ComponentName CHAR8 (8) DUP (?) ; < 8 character name of the code module + Version CHAR8 (12) DUP (?) ; < 12 character version string + TerminatorNull CHAR8 ? ; < null terminated string + VerReserved CHAR8 (7) DUP (?) ; < reserved space +AMD_CODE_HEADER ENDS + + ; Extended PCI address format +EXT_PCI_ADDR STRUCT + Register UINT32 ? +; IN OUT UINT32 Register:12; ; < Register offset +; IN OUT UINT32 Function:3; ; < Function number +; IN OUT UINT32 Device:5; ; < Device number +; IN OUT UINT32 Bus:8; ; < Bus number +; IN OUT UINT32 Segment:4; ; < Segment +EXT_PCI_ADDR ENDS + + ; Union type for PCI address +PCI_ADDR UNION + AddressValue UINT32 ? ; < Formal address + Address EXT_PCI_ADDR {} ; < Extended address +PCI_ADDR ENDS + + ; SBDFO - Segment Bus Device Function Offset + ; 31:28 Segment (4-bits) + ; 27:20 Bus (8-bits) + ; 19:15 Device (5-bits) + ; 14:12 Function(3-bits) + ; 11:00 Offset (12-bits) + + + + ILLEGAL_SBDFO EQU 0FFFFFFFFh + + ; CPUID data received registers format +CPUID_DATA STRUCT + EAX_Reg UINT32 ? ; < CPUID instruction result in EAX + EBX_Reg UINT32 ? ; < CPUID instruction result in EBX + ECX_Reg UINT32 ? ; < CPUID instruction result in ECX + EDX_Reg UINT32 ? ; < CPUID instruction result in EDX +CPUID_DATA ENDS + + ; HT frequency for external callbacks +;typedef enum { + HT_FREQUENCY_200M EQU 0 ; < HT speed 200 for external callbacks + HT_FREQUENCY_400M EQU 2 ; < HT speed 400 for external callbacks + HT_FREQUENCY_600M EQU 4 ; < HT speed 600 for external callbacks + HT_FREQUENCY_800M EQU 5 ; < HT speed 800 for external callbacks + HT_FREQUENCY_1000M EQU 6 ; < HT speed 1000 for external callbacks + HT_FREQUENCY_1200M EQU 7 ; < HT speed 1200 for external callbacks + HT_FREQUENCY_1400M EQU 8 ; < HT speed 1400 for external callbacks + HT_FREQUENCY_1600M EQU 9 ; < HT speed 1600 for external callbacks + HT_FREQUENCY_1800M EQU 10 ; < HT speed 1800 for external callbacks + HT_FREQUENCY_2000M EQU 11 ; < HT speed 2000 for external callbacks + HT_FREQUENCY_2200M EQU 12 ; < HT speed 2200 for external callbacks + HT_FREQUENCY_2400M EQU 13 ; < HT speed 2400 for external callbacks + HT_FREQUENCY_2600M EQU 14 ; < HT speed 2600 for external callbacks + HT_FREQUENCY_2800M EQU 17 ; < HT speed 2800 for external callbacks + HT_FREQUENCY_3000M EQU 18 ; < HT speed 3000 for external callbacks + HT_FREQUENCY_3200M EQU 19 ; < HT speed 3200 for external callbacks + HT_FREQUENCY_MAX EQU 20 ; < Limit Check. +HT_FREQUENCIES TEXTEQU <DWORD> ;} HT_FREQUENCIES; + +HT3_FREQUENCY_MIN EQU HT_FREQUENCY_1200M + +IFNDEF BIT0 + BIT0 EQU 0000000000000001h +ENDIF +IFNDEF BIT1 + BIT1 EQU 0000000000000002h +ENDIF +IFNDEF BIT2 + BIT2 EQU 0000000000000004h +ENDIF +IFNDEF BIT3 + BIT3 EQU 0000000000000008h +ENDIF +IFNDEF BIT4 + BIT4 EQU 0000000000000010h +ENDIF +IFNDEF BIT5 + BIT5 EQU 0000000000000020h +ENDIF +IFNDEF BIT6 + BIT6 EQU 0000000000000040h +ENDIF +IFNDEF BIT7 + BIT7 EQU 0000000000000080h +ENDIF +IFNDEF BIT8 + BIT8 EQU 0000000000000100h +ENDIF +IFNDEF BIT9 + BIT9 EQU 0000000000000200h +ENDIF +IFNDEF BIT10 + BIT10 EQU 0000000000000400h +ENDIF +IFNDEF BIT11 + BIT11 EQU 0000000000000800h +ENDIF +IFNDEF BIT12 + BIT12 EQU 0000000000001000h +ENDIF +IFNDEF BIT13 + BIT13 EQU 0000000000002000h +ENDIF +IFNDEF BIT14 + BIT14 EQU 0000000000004000h +ENDIF +IFNDEF BIT15 + BIT15 EQU 0000000000008000h +ENDIF +IFNDEF BIT16 + BIT16 EQU 0000000000010000h +ENDIF +IFNDEF BIT17 + BIT17 EQU 0000000000020000h +ENDIF +IFNDEF BIT18 + BIT18 EQU 0000000000040000h +ENDIF +IFNDEF BIT19 + BIT19 EQU 0000000000080000h +ENDIF +IFNDEF BIT20 + BIT20 EQU 0000000000100000h +ENDIF +IFNDEF BIT21 + BIT21 EQU 0000000000200000h +ENDIF +IFNDEF BIT22 + BIT22 EQU 0000000000400000h +ENDIF +IFNDEF BIT23 + BIT23 EQU 0000000000800000h +ENDIF +IFNDEF BIT24 + BIT24 EQU 0000000001000000h +ENDIF +IFNDEF BIT25 + BIT25 EQU 0000000002000000h +ENDIF +IFNDEF BIT26 + BIT26 EQU 0000000004000000h +ENDIF +IFNDEF BIT27 + BIT27 EQU 0000000008000000h +ENDIF +IFNDEF BIT28 + BIT28 EQU 0000000010000000h +ENDIF +IFNDEF BIT29 + BIT29 EQU 0000000020000000h +ENDIF +IFNDEF BIT30 + BIT30 EQU 0000000040000000h +ENDIF +IFNDEF BIT31 + BIT31 EQU 0000000080000000h +ENDIF +IFNDEF BIT32 + BIT32 EQU 0000000100000000h +ENDIF +IFNDEF BIT33 + BIT33 EQU 0000000200000000h +ENDIF +IFNDEF BIT34 + BIT34 EQU 0000000400000000h +ENDIF +IFNDEF BIT35 + BIT35 EQU 0000000800000000h +ENDIF +IFNDEF BIT36 + BIT36 EQU 0000001000000000h +ENDIF +IFNDEF BIT37 + BIT37 EQU 0000002000000000h +ENDIF +IFNDEF BIT38 + BIT38 EQU 0000004000000000h +ENDIF +IFNDEF BIT39 + BIT39 EQU 0000008000000000h +ENDIF +IFNDEF BIT40 + BIT40 EQU 0000010000000000h +ENDIF +IFNDEF BIT41 + BIT41 EQU 0000020000000000h +ENDIF +IFNDEF BIT42 + BIT42 EQU 0000040000000000h +ENDIF +IFNDEF BIT43 + BIT43 EQU 0000080000000000h +ENDIF +IFNDEF BIT44 + BIT44 EQU 0000100000000000h +ENDIF +IFNDEF BIT45 + BIT45 EQU 0000200000000000h +ENDIF +IFNDEF BIT46 + BIT46 EQU 0000400000000000h +ENDIF +IFNDEF BIT47 + BIT47 EQU 0000800000000000h +ENDIF +IFNDEF BIT48 + BIT48 EQU 0001000000000000h +ENDIF +IFNDEF BIT49 + BIT49 EQU 0002000000000000h +ENDIF +IFNDEF BIT50 + BIT50 EQU 0004000000000000h +ENDIF +IFNDEF BIT51 + BIT51 EQU 0008000000000000h +ENDIF +IFNDEF BIT52 + BIT52 EQU 0010000000000000h +ENDIF +IFNDEF BIT53 + BIT53 EQU 0020000000000000h +ENDIF +IFNDEF BIT54 + BIT54 EQU 0040000000000000h +ENDIF +IFNDEF BIT55 + BIT55 EQU 0080000000000000h +ENDIF +IFNDEF BIT56 + BIT56 EQU 0100000000000000h +ENDIF +IFNDEF BIT57 + BIT57 EQU 0200000000000000h +ENDIF +IFNDEF BIT58 + BIT58 EQU 0400000000000000h +ENDIF +IFNDEF BIT59 + BIT59 EQU 0800000000000000h +ENDIF +IFNDEF BIT60 + BIT60 EQU 1000000000000000h +ENDIF +IFNDEF BIT61 + BIT61 EQU 2000000000000000h +ENDIF +IFNDEF BIT62 + BIT62 EQU 4000000000000000h +ENDIF +IFNDEF BIT63 + BIT63 EQU 8000000000000000h +ENDIF + diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/bridge32.inc b/src/vendorcode/amd/agesa/f15tn/Legacy/bridge32.inc new file mode 100644 index 0000000..81f3335 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Legacy/bridge32.inc @@ -0,0 +1,603 @@ +; **************************************************************************** +; * +; * @file +; * +; * Agesa structures and definitions +; * +; * Contains AMD AGESA core interface +; * +; * @xrefitem bom "File Content Label" "Release Content" +; * @e project: AGESA +; * @e sub-project: Include +; * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ +; +; **************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;***************************************************************************** + +PARAM1 textequ <[bp+8]> +PARAM2 textequ <[bp+12]> +PARAM3 textequ <[bp+16]> +RETAddress textequ <[bp+4]> + +AMD_PRIVATE_PARAMS STRUCT + Gate16_CS DW ? ; Segment of AMD_BRIDGE_32 and AMD_CALLOUT_16 + Gate16_SS DW ? ; RM stack segment + Router_Seg DW ? ; Segment of oem router + Router_Off DW ? ; Offset of oem router +AMD_PRIVATE_PARAMS ENDS + +; OEM may pre-define the GDT and selector offsets. If they do not, use our defaults. +IFNDEF AGESA_SELECTOR_GDT + AGESA_SELECTOR_GDT EQU 00h +ENDIF +IFNDEF AGESA_SELECTOR_CODE16 + AGESA_SELECTOR_CODE16 EQU 08h +ENDIF +IFNDEF AGESA_SELECTOR_DATA16 + AGESA_SELECTOR_DATA16 EQU 10h +ENDIF +IFNDEF AGESA_SELECTOR_CODE32 + AGESA_SELECTOR_CODE32 EQU 18h +ENDIF +IFNDEF AGESA_SELECTOR_DATA32 + AGESA_SELECTOR_DATA32 EQU 20h +ENDIF + + +AMD_BRIDGE_32_GDT MACRO GDT_Name:REQ + + GDT_Name LABEL BYTE + DD 000000000h, 000000000h ; NULL descriptor + DD 00000ffffh, 000009b00h ; 16-bit code, fixed up + DD 00000ffffh, 000009300h ; 16-bit data, fixed up + DD 00000ffffh, 000CF9B00h ; 32-bit protected mode code + DD 00000ffffh, 000CF9300h ; 32-bit protected mode data + GDT_Length EQU ($-GDT_Name) + +ENDM + +;+------------------------------------------------------------------------- +; +; AMD_BRIDGE_32 - Execute Agesa through Pushhigh interface +; +; Processing: +; The following steps are taken: +; 1) Enter 32bit Protected Mode (PM32) +; 2) Run AGESA code +; 3) Restore Real Mode (RM) +; +; Entry: +; [big real mode] : ds, es set to base 0 limit 4G segment +; EDX - if not 0, provides a FAR PTR to oem router (Seg | Offset) +; ESI - configuration block pointer +; +; Exit: +; EAX - return value +; ESI - configuration block pointer +; ds, es, fs, gs - Set to 4GB segment limit for Big Real Mode +; +; Modified: +; None +; + +AMD_BRIDGE_32 MACRO GDT_Name + + local copyGDT + local flushTo16PM + local agesaReturnAddress + local leave32bitPM + local flush2RM + + push gs + push fs + push ebx + push ecx + push edi + mov eax, esp + push eax + movzx esp, sp +; +; Do not use any locals here, BP will be changed frequently during RM->PM32->RM +; + pushf + cli ; Disable interrupts during AGESA + cld ; Need known direction flag during AGESA + +; +; Save the FAR PTR input parameter +; + mov gs, dx ; Offset + shr edx, 16 + mov fs, dx ; Segment +; +; Determine where our binary file is and get entry point +; + mov edx, (AMD_CONFIG_PARAMS PTR [esi]).ImageBasePtr + add edx, (AMD_IMAGE_HEADER PTR [edx]).EntryPointAddress +; +; Figure out the return address we will use after calling AGESA +; and store it in ebx until we have our stack set up properly +; + mov ebx, cs + shl ebx, 4 + add ebx, OFFSET agesaReturnAddress +; +; Save our current RM stack AND entry EBP +; + push ebp +; push esp + push ss + +; +; BEGIN --- STACK MUST BE BALANCED AT THIS POINT --- BEGIN +; +; Copy the GDT onto the stack for modification +; + mov cx, GDT_Length + sub sp, cx + mov bp, sp + lea di, GDT_Name +copyGDT: + mov al, cs:[di] + mov [bp], al + inc di + inc bp + loop copyGDT +; +; Patch 16-bit code and data descriptors on stack. We will +; fix up CS and SS for PM16 during the callout if applicable. +; + mov bp, sp + + mov eax, cs + shl eax, 4 + mov [bp+AGESA_SELECTOR_CODE16+2], ax + shr eax, 16 + mov [bp+AGESA_SELECTOR_CODE16+4], al + + mov eax, ss + shl eax, 4 + mov [bp+AGESA_SELECTOR_DATA16+2], ax + shr eax, 16 + mov [bp+AGESA_SELECTOR_DATA16+4], al +; +; Need to place Length and Address on GDT +; + mov eax, ss + shl eax, 4 + add eax, esp + push eax + push WORD PTR (GDT_Length-1) +; +; Load the GDT +; + mov bp, sp + lgdt FWORD PTR [bp] +; +; TABLE 1 +; +; Place PRIVATE DATA on stack DIRECTLY following GDT +; During this routine, stack data is critical. If +; order is changed or additional added, bad things +; will happen! +; +; HIGHEST PHYSICAL ADDRESS +; +; | ... | +; ------------------------ +; | old RM SP | +; | old RM SS | +; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS + (SIZEOF GDT_LENGTH + 6 {size, address}) +; | GDT_DATA32 | +; | ... | +; | GDT_NULL | +; | GDT Addr, Length | +; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS +; | Priv.Gate16_SS | +; | Priv.Gate16_CS | +; ------------------------ sp +; ------ THEN PUSH ------- +; | Return to 16-bit CS | +; | Return to 16-bit Off | +; | ... | +; +; LOWEST PHYSICAL ADDRESS +; + mov edi, esp + sub edi, SIZEOF AMD_PRIVATE_PARAMS + mov ax, cs + mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS, ax + mov ax, ss + mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS, ax + mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off, gs + mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg, fs + + mov esp, edi +; +; Save an address for returning to 16 bit real mode on stack, +; we'll use it in a far ret after turning off CR0.PE so that +; we can take our address off and force a far jump. Be sure +; no unexpected data is on the stack after this! +; + mov ax, cs + push cs + lea ax, flush2RM + push ax +; +; Convert ss:esp to "flat" +; + + mov ax, sp + push ax + mov eax, ss + shl eax, 4 + add eax, esp + mov esp, eax ; Load the zero based ESP + +; +; Set CR0.PE +; + mov eax, CR0 ; Get CPU control word 0 + or al, 01 ; Enable CPU protected mode + mov CR0, eax ; Write back to CPU control word 0 + jmp flushTo16PM + +flushTo16PM: +; +; 16-bit protected mode +; + mov ax, AGESA_SELECTOR_DATA32 + mov ds, ax + mov es, ax + mov fs, ax + mov gs, ax + mov ss, ax +; +; Push our parameters RIGHT TO LEFT, and then return address +; + push esi ; AGESA configuration block pointer (data) + push ebx ; after AGESA return offset (32PM flat) - consumed by dispatcher ret + pushd AGESA_SELECTOR_CODE32 ; AGESA entry selector (32PM flat) + push edx ; AGESA entry point (32PM flat) + + DB 066h + retf ; <><><> Enter AGESA 32-bit code!!! <><><> + +agesaReturnAddress: +; +; Returns from the Agesa 32-bit code still PM32 +; + DB 0EAh + DD OFFSET leave32bitPM + DW AGESA_SELECTOR_CODE16 + +leave32bitPM: +; +; Now in 16-bit PM +; + add esp, 4 ; +4 to remove our config block pointer +; +; Eax reserve AGESA_STATUS return code, save it +; + mov ebx, eax +; +; Turn off CR0.PE, restore 64K stack limit +; + pop ax + mov sp, ax + mov ax, AGESA_SELECTOR_DATA16 + mov ss, ax + + mov eax, CR0 + and al, NOT 1 ; Disable protected mode + mov CR0, eax ; Write back CR0.PE +; +; Jump far to enter RM, we saved this address on the stack +; already. Hopefully stack is balanced through AGESA +; nor were any params added by pushing them on the stack and +; not removing them between BEGIN-END comments. +; + retf + +flush2RM: +; +; Set segments registers for big real mode before returning +; + xor ax, ax + mov ds, ax + mov es, ax + mov fs, ax + mov gs, ax +; +; Discard GDT, +6 for GDT pointer/size, privates +; + add esp, GDT_Length + 6 + SIZEOF AMD_PRIVATE_PARAMS +; +; Restore real mode stack and entry EBP +; + pop cx +; mov esp, [esp] + mov ss, cx + pop ebp +; +; Restore AGESA_STATUS return code to eax +; + mov eax, ebx +; +; END --- STACK MUST BE BALANCED TO THIS POINT --- END +; + + popf + pop ebx + mov esp, ebx + pop edi + pop ecx + pop ebx + pop fs + pop gs + ; EXIT AMD_BRIDGE_32 +ENDM +;+------------------------------------------------------------------------- +; +; AMD_CALLOUT_16 - Execute Callback from Pushhigh interface +; +; Processing: +; The following steps are taken: +; 1) Enter PM16 +; 2) Setup stack, get private params +; 3) Enter RM +; 4) Get 3 params +; 5) Call oemCallout OR oem router +; 6) Enter PM32 +; 7) Return to Agesa PH +; +; Entry: +; [32-bit protected mode] +; [esp+8] Func +; [esp+12] Data +; [esp+16] Configuration Block +; [esp+4] return address to Agesa +; +; Exit: +; [32-bit protected mode] +; +; Modified: +; None +; +AMD_CALLOUT_16 MACRO LocalOemCalloutRouter +; +; Note that we are still PM32, so MASM may work strangely +; + + push bp ; Save our original SP to access params + mov bp, sp + push bx + push si + push di + push cx + push dx + push di + + DB 066h, 0EAh + DW OFFSET PM16Entry + DW AGESA_SELECTOR_CODE16 + +PM16Entry: +; +; PM16 CS, but still PM32 SS, as we need to access our private params +; before we enter RM. +; +; Note: we are working below the stack temporarily, and and it will +; not affect our ability to get entry params +; + xor ecx, ecx + xor edx, edx +; +; SGDT will give us the original location of the GDT on our CAS stack. +; We need this value because our private parameters are located just +; below the GDT. +; + mov edi, esp + sub edi, GDT_Length + 6 + sgdt FWORD PTR [edi] ; [edi] = word size, dword address + mov edi, DWORD PTR [edi+2] ; Get the PM32 address only + sub edi, SIZEOF AMD_PRIVATE_PARAMS + 6 +; +; cx = code segment of this code in RM +; dx = stack segment of CAS in RM +; fs = code segment of oem router (save for later) +; gs = offset of oem router (save for later) +; fs and gs are loaded after switch to real mode because we can't +; use them as scratch pad registers in protected mode +; + mov cx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS + mov dx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS + + mov eax, edi ; Save edi in eax for after RM switch + mov edi, esp ; Save our current ESP for RM + + movzx ebx, dx + shl ebx, 4 + sub esp, ebx + +; +; We had been accessing the stack in PM32, we will now change to PM16 so we +; will make the stack segment 64KB limit so SP needs to be fixed made PM16 +; compatible. +; + mov bx, AGESA_SELECTOR_DATA16 + mov ss, bx + +; +; Save the RM segment and RM offset of the jump we will need to make in +; order to enter RM so that code in this segment is relocatable. +; +; BEGIN --- Don't unbalance the stack --- BEGIN +; + push cx + pushw OFFSET RMEntry + + mov ebx, CR0 + and bl, NOT 1 + mov CR0, ebx ; CR0.PE cleared +; +; Far jump to clear segment descriptor cache and enter RM +; + retf + +RMEntry: +; +; We are in RM, setup RM stack +; + movzx ebx, dx ; Get RM SS in ebx + shl ebx, 4 ; Get our stack top on entry in EBP to + sub ebp, ebx ; access our entry parameters + sub eax, ebx ; save copy of parameters address + mov ss, dx ; Set stack segment +; +; We are going to figure out the address to use when we return +; and have to go back into PM32 while we have access to it +; + movzx ebx, cx ; Get original CS in ebx + shl ebx, 4 + add ebx, OFFSET PM32Entry +; +; Now we put our data, func, block params into calling convention +; for our hook +; +; ECX = Func +; EDX = Data +; ESI = config pointer +; + mov ecx, PARAM1 ; Func + mov edx, PARAM2 ; Data + mov esi, PARAM3 ; pointer + + push ebx ; Save PM32 mode switch address + push edi ; Save PM32 stack pointer + pushf +; +; Get Router Function Address +; + mov edi, eax + mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg + mov fs, ax + mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off + mov gs, ax + + mov eax, AGESA_UNSUPPORTED ; Default return value +; +; If AMD_BRIDGE_32 EDX == 0 call oemCallout +; otherwise call FAR PTR EDX +; +; Critical: +; sp+2 - EDI aka PM32 stack address +; sp+4 - address of PM32Entry in PM32 +; + mov bx, fs + shl ebx, 16 + mov bx, gs + + .if (ebx == 0) + call LocalOemCalloutRouter + .else +; +; Make far call to Router function +; + push cs + push offset CalloutReturn + push ebx + retf +CalloutReturn: + .endif +; +; Restore PM32 esp from RM stack +; + popf + pop edi ; Our PM32 stack pointer + pop edx ; Our PM32 mode switch address + + mov ebx, CR0 + or bl, 1 ; CR0.PE set + mov CR0, ebx + + mov ebx, AGESA_SELECTOR_DATA32 + pushd AGESA_SELECTOR_CODE32 ; PM32 selector + push edx ; PM32 entry point + + DB 066h + retf ; Far jump to enter PM32 + +PM32Entry: +; +; END --- Don't unbalance the stack --- END +; We are now PM32, so remember MASM is assembling in 16-bit again +; + mov ss, bx + mov ds, bx + mov es, bx + mov fs, bx + mov gs, bx + + mov sp, di + pop di + pop dx + pop cx + pop di + pop si + pop bx + pop bp + ; EXIT AMD_CALLOUT_16 +ENDM diff --git a/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c b/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c new file mode 100644 index 0000000..81ff635 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c @@ -0,0 +1,1387 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Library + * + * Contains interface to the AMD AGESA library + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Lib + * @e $Revision: 48409 $ @e $Date: 2011-03-08 11:19:40 -0600 (Tue, 08 Mar 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2011 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "amdlib.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE LIB_AMDLIB_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +BOOLEAN +STATIC +GetPciMmioAddress ( + OUT UINT64 *MmioAddress, + OUT UINT32 *MmioSize, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +LibAmdGetDataFromPtr ( + IN ACCESS_WIDTH AccessWidth, + IN VOID *Data, + IN VOID *DataMask, + OUT UINT32 *TemData, + OUT UINT32 *TempDataMask + ); +VOID +IdsOutPort ( + IN UINT32 Addr, + IN UINT32 Value, + IN UINT32 Flag + ); + +VOID +CpuidRead ( + IN UINT32 CpuidFcnAddress, + OUT CPUID_DATA *Value + ); + +UINT8 +ReadNumberOfCpuCores( + VOID + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +UINT8 +ReadIo8 ( + IN UINT16 Address + ) +{ + return __inbyte (Address); +} +UINT16 +ReadIo16 ( + IN UINT16 Address + ) +{ + return __inword (Address); +} +UINT32 +ReadIo32 ( + IN UINT16 Address + ) +{ + return __indword (Address); +} +VOID +WriteIo8 ( + IN UINT16 Address, + IN UINT8 Data + ) +{ + __outbyte (Address, Data); +} +VOID +WriteIo16 ( + IN UINT16 Address, + IN UINT16 Data + ) +{ + __outword (Address, Data); +} +VOID +WriteIo32 ( + IN UINT16 Address, + IN UINT32 Data + ) +{ + __outdword (Address, Data); +} +STATIC +UINT64 SetFsBase ( + UINT64 address + ) +{ + UINT64 hwcr; + hwcr = __readmsr (0xC0010015); + __writemsr (0xC0010015, hwcr | 1 << 17); + __writemsr (0xC0000100, address); + return hwcr; +} +STATIC +VOID +RestoreHwcr ( + UINT64 + value + ) +{ + __writemsr (0xC0010015, value); +} +UINT8 +Read64Mem8 ( + IN UINT64 Address + ) +{ + UINT8 dataRead; + UINT64 hwcrSave; + if ((Address >> 32) == 0) { + return *(volatile UINT8 *) (UINTN) Address; + } + hwcrSave = SetFsBase (Address); + dataRead = __readfsbyte (0); + RestoreHwcr (hwcrSave); + return dataRead; +} +UINT16 +Read64Mem16 ( + IN UINT64 Address + ) +{ + UINT16 dataRead; + UINT64 hwcrSave; + if ((Address >> 32) == 0) { + return *(volatile UINT16 *) (UINTN) Address; + } + hwcrSave = SetFsBase (Address); + dataRead = __readfsword (0); + RestoreHwcr (hwcrSave); + return dataRead; +} +UINT32 +Read64Mem32 ( + IN UINT64 Address + ) +{ + UINT32 dataRead; + UINT64 hwcrSave; + if ((Address >> 32) == 0) { + return *(volatile UINT32 *) (UINTN) Address; + } + hwcrSave = SetFsBase (Address); + dataRead = __readfsdword (0); + RestoreHwcr (hwcrSave); + return dataRead; + } +VOID +Write64Mem8 ( + IN UINT64 Address, + IN UINT8 Data + ) +{ + if ((Address >> 32) == 0){ + *(volatile UINT8 *) (UINTN) Address = Data; + } + else { + UINT64 hwcrSave; + hwcrSave = SetFsBase (Address); + __writefsbyte (0, Data); + RestoreHwcr (hwcrSave); + } +} +VOID +Write64Mem16 ( + IN UINT64 Address, + IN UINT16 Data + ) +{ + if ((Address >> 32) == 0){ + *(volatile UINT16 *) (UINTN) Address = Data; + } + else { + UINT64 hwcrSave; + hwcrSave = SetFsBase (Address); + __writefsword (0, Data); + RestoreHwcr (hwcrSave); + } +} +VOID +Write64Mem32 ( + IN UINT64 Address, + IN UINT32 Data + ) +{ + if ((Address >> 32) == 0){ + *(volatile UINT32 *) (UINTN) Address = Data; + } + else { + UINT64 hwcrSave; + hwcrSave = SetFsBase (Address); + __writefsdword (0, Data); + RestoreHwcr (hwcrSave); + } +} +VOID +LibAmdReadCpuReg ( + IN UINT8 RegNum, + OUT UINT32 *Value + ) +{ + *Value = 0; + switch (RegNum){ + case CR4_REG: + *Value = __readcr4 (); + break; + case DR0_REG: + *Value = __readdr (0); + break; + case DR1_REG: + *Value = __readdr (1); + break; + case DR2_REG: + *Value = __readdr (2); + break; + case DR3_REG: + *Value = __readdr (3); + break; + case DR7_REG: + *Value = __readdr (7); + break; + default: + *Value = -1; + } +} +VOID +LibAmdWriteCpuReg ( + IN UINT8 RegNum, + IN UINT32 Value + ) +{ + switch (RegNum){ + case CR4_REG: + __writecr4 (Value); + break; + case DR0_REG: + __writedr (0, Value); + break; + case DR1_REG: + __writedr (1, Value); + break; + case DR2_REG: + __writedr (2, Value); + break; + case DR3_REG: + __writedr (3, Value); + break; + case DR7_REG: + __writedr (7, Value); + break; + default: + ; + } +} +VOID +LibAmdWriteBackInvalidateCache ( + IN VOID + ) +{ + __wbinvd (); +} +VOID +LibAmdHDTBreakPoint ( + VOID + ) +{ + __writemsr (0xC001100A, __readmsr (0xC001100A) | 1); + __debugbreak (); // do you really need icebp? If so, go back to asm code +} +UINT8 +LibAmdBitScanForward ( + IN UINT32 value + ) +{ + UINTN Index; + for (Index = 0; Index < 32; Index++){ + if (value & (1 << Index)) break; + } + return (UINT8) Index; +} +UINT8 +LibAmdBitScanReverse ( + IN UINT32 value +) +{ + UINTN Index; + for (Index = 31; Index >= 0; Index--){ + if (value & (1 << Index)) break; + } + return (UINT8) Index; +} +VOID +LibAmdMsrRead ( + IN UINT32 MsrAddress, + OUT UINT64 *Value, + IN OUT AMD_CONFIG_PARAMS *ConfigPtr + ) +{ + *Value = __readmsr (MsrAddress); +} +VOID +LibAmdMsrWrite ( + IN UINT32 MsrAddress, + IN UINT64 *Value, + IN OUT AMD_CONFIG_PARAMS *ConfigPtr + ) +{ + __writemsr (MsrAddress, *Value); +} +void LibAmdCpuidRead ( + IN UINT32 CpuidFcnAddress, + OUT CPUID_DATA* Value, + IN OUT AMD_CONFIG_PARAMS *ConfigPtr + ) +{ + __cpuid ((int *)Value, CpuidFcnAddress); +} +UINT64 +ReadTSC ( + VOID + ) +{ + return __rdtsc (); +} +VOID +LibAmdSimNowEnterDebugger ( + VOID + ) +{ + STATIC CONST UINT8 opcode [] = {0x60, // pushad + 0xBB, 0x02, 0x00, 0x00, 0x00, // mov ebx, 2 + 0xB8, 0x0B, 0xD0, 0xCC, 0xBA, // mov eax, 0xBACCD00B + 0x0F, 0xA2, // cpuid + 0x61, // popad + 0xC3 // ret + }; + ((VOID (*)(VOID)) (size_t) opcode) (); // call the function +} +#if 0 +VOID F10RevDProbeFilterCritical ( + IN PCI_ADDR PciAddress, + IN UINT32 PciRegister + ) +{ + UINT64 msrsave; + msrsave = __readmsr (0xC001001F); + __writemsr (0xC001001F, msrsave | 1ULL << 46); // EnableCf8ExtCfg + _mm_mfence (); + __outdword (0xCF8, PciAddress.AddressValue); + _mm_mfence (); + __outdword (0xCFC, PciRegister | 2); + _mm_mfence (); + __writemsr (0xC001001F, msrsave); +} +#endif +VOID +IdsOutPort ( + IN UINT32 Addr, + IN UINT32 Value, + IN UINT32 Flag + ) +{ + __outdword ((UINT16) Addr, Value); +} +VOID +StopHere ( + VOID + ) +{ + VOLATILE UINTN x = 1; + while (x); +} +VOID +LibAmdCLFlush ( + IN UINT64 Address, + IN UINT8 Count + ) +{ + UINT64 hwcrSave; + UINT8 *address32; + UINTN Index; + address32 = 0; + hwcrSave = SetFsBase (Address); + for (Index = 0; Index < Count; Index++){ + _mm_mfence (); + _mm_clflush_fs (&address32 [Index * 64]); + } + RestoreHwcr (hwcrSave); +} + +VOID +LibAmdFinit() +{ + /* TODO: finit */ + __asm__ volatile ("finit"); +} +/*---------------------------------------------------------------------------------------*/ +/** + * Read IO port + * + * + * @param[in] AccessWidth Access width + * @param[in] IoAddress IO port address + * @param[in] Value Pointer to save data + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdIoRead ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + OUT VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + switch (AccessWidth) { + case AccessWidth8: + case AccessS3SaveWidth8: + *(UINT8 *) Value = ReadIo8 (IoAddress); + break; + case AccessWidth16: + case AccessS3SaveWidth16: + *(UINT16 *) Value = ReadIo16 (IoAddress); + break; + case AccessWidth32: + case AccessS3SaveWidth32: + *(UINT32 *) Value = ReadIo32 (IoAddress); + break; + default: + ASSERT (FALSE); + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Write IO port + * + * + * @param[in] AccessWidth Access width + * @param[in] IoAddress IO port address + * @param[in] Value Pointer to data + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdIoWrite ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + IN VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + switch (AccessWidth) { + case AccessWidth8: + case AccessS3SaveWidth8: + WriteIo8 (IoAddress, *(UINT8 *) Value); + break; + case AccessWidth16: + case AccessS3SaveWidth16: + WriteIo16 (IoAddress, *(UINT16 *) Value); + break; + case AccessWidth32: + case AccessS3SaveWidth32: + WriteIo32 (IoAddress, *(UINT32 *) Value); + break; + default: + ASSERT (FALSE); + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * IO read modify write + * + * + * @param[in] AccessWidth Access width + * @param[in] IoAddress IO address + * @param[in] Data OR data + * @param[in] DataMask Mask to be used before data write back to register. + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdIoRMW ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + IN VOID *Data, + IN VOID *DataMask, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempData; + UINT32 TempMask; + UINT32 Value; + LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); + LibAmdIoRead (AccessWidth, IoAddress, &Value, StdHeader); + Value = (Value & (~TempMask)) | TempData; + LibAmdIoWrite (AccessWidth, IoAddress, &Value, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Poll IO register + * + * Poll register until (RegisterValue & DataMask) == Data + * + * @param[in] AccessWidth Access width + * @param[in] IoAddress IO address + * @param[in] Data Data to compare + * @param[in] DataMask And mask + * @param[in] Delay Poll for time in 100ns (not supported) + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdIoPoll ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + IN VOID *Data, + IN VOID *DataMask, + IN UINT64 Delay, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempData; + UINT32 TempMask; + UINT32 Value; + LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); + do { + LibAmdIoRead (AccessWidth, IoAddress, &Value, StdHeader); + } while (TempData != (Value & TempMask)); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Read memory/MMIO + * + * + * @param[in] AccessWidth Access width + * @param[in] MemAddress Memory address + * @param[in] Value Pointer to data + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdMemRead ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + OUT VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + switch (AccessWidth) { + case AccessWidth8: + case AccessS3SaveWidth8: + *(UINT8 *) Value = Read64Mem8 (MemAddress); + break; + case AccessWidth16: + case AccessS3SaveWidth16: + *(UINT16 *) Value = Read64Mem16 (MemAddress); + break; + case AccessWidth32: + case AccessS3SaveWidth32: + *(UINT32 *) Value = Read64Mem32 (MemAddress); + break; + default: + ASSERT (FALSE); + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Write memory/MMIO + * + * + * @param[in] AccessWidth Access width + * @param[in] MemAddress Memory address + * @param[in] Value Pointer to data + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdMemWrite ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + IN VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + + switch (AccessWidth) { + case AccessWidth8: + case AccessS3SaveWidth8: + Write64Mem8 (MemAddress, *((UINT8 *) Value)); + break; + case AccessWidth16: + case AccessS3SaveWidth16: + Write64Mem16 (MemAddress, *((UINT16 *) Value)); + break; + case AccessWidth32: + case AccessS3SaveWidth32: + Write64Mem32 (MemAddress, *((UINT32 *) Value)); + break; + default: + ASSERT (FALSE); + } +} +/*---------------------------------------------------------------------------------------*/ +/** + * Memory/MMIO read modify write + * + * + * @param[in] AccessWidth Access width + * @param[in] MemAddress Memory address + * @param[in] Data OR data + * @param[in] DataMask Mask to be used before data write back to register. + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdMemRMW ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + IN VOID *Data, + IN VOID *DataMask, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempData; + UINT32 TempMask; + UINT32 Value; + LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); + LibAmdMemRead (AccessWidth, MemAddress, &Value, StdHeader); + Value = (Value & (~TempMask)) | TempData; + LibAmdMemWrite (AccessWidth, MemAddress, &Value, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Poll Mmio + * + * Poll register until (RegisterValue & DataMask) == Data + * + * @param[in] AccessWidth Access width + * @param[in] MemAddress Memory address + * @param[in] Data Data to compare + * @param[in] DataMask AND mask + * @param[in] Delay Poll for time in 100ns (not supported) + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdMemPoll ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + IN VOID *Data, + IN VOID *DataMask, + IN UINT64 Delay, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempData = 0; + UINT32 TempMask = 0; + UINT32 Value; + LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); + do { + LibAmdMemRead (AccessWidth, MemAddress, &Value, StdHeader); + } while (TempData != (Value & TempMask)); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Read PCI config space + * + * + * @param[in] AccessWidth Access width + * @param[in] PciAddress Pci address + * @param[in] Value Pointer to data + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdPciRead ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + OUT VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 LegacyPciAccess; + UINT32 MMIOSize; + UINT64 RMWrite; + UINT64 RMWritePrevious; + UINT64 MMIOAddress; + + ASSERT (StdHeader != NULL); + ASSERT (PciAddress.AddressValue != ILLEGAL_SBDFO); + if (!GetPciMmioAddress (&MMIOAddress, &MMIOSize, StdHeader)) { + // We need to convert our "portable" PCI address into a "real" PCI access + LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8))); + if (PciAddress.Address.Register <= 0xFF) { + LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader); + LibAmdIoRead (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader); + } else { + LibAmdMsrRead (NB_CFG, &RMWritePrevious, StdHeader); + RMWrite = RMWritePrevious | 0x0000400000000000; + LibAmdMsrWrite (NB_CFG, &RMWrite, StdHeader); + LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader); + LibAmdIoRead (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader); + LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader); + } + //IDS_HDT_CONSOLE (LIB_PCI_RD, "~PCI RD %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value); + } else { + // Setup the MMIO address + ASSERT ((MMIOAddress + MMIOSize) > (MMIOAddress + (PciAddress.AddressValue & 0x0FFFFFFF))); + MMIOAddress += (PciAddress.AddressValue & 0x0FFFFFFF); + LibAmdMemRead (AccessWidth, MMIOAddress, Value, StdHeader); + //IDS_HDT_CONSOLE (LIB_PCI_RD, "~MMIO RD %08x = %08x\n", (UINT32) MMIOAddress, *(UINT32 *)Value); + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Write PCI config space + * + * + * @param[in] AccessWidth Access width + * @param[in] PciAddress Pci address + * @param[in] Value Pointer to data + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdPciWrite ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + IN VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 LegacyPciAccess; + UINT32 MMIOSize; + UINT64 RMWrite; + UINT64 RMWritePrevious; + UINT64 MMIOAddress; + + ASSERT (StdHeader != NULL); + ASSERT (PciAddress.AddressValue != ILLEGAL_SBDFO); + if (!GetPciMmioAddress (&MMIOAddress, &MMIOSize, StdHeader)) { + // We need to convert our "portable" PCI address into a "real" PCI access + LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8))); + if (PciAddress.Address.Register <= 0xFF) { + LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader); + LibAmdIoWrite (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader); + } else { + LibAmdMsrRead (NB_CFG, &RMWritePrevious, StdHeader); + RMWrite = RMWritePrevious | 0x0000400000000000; + LibAmdMsrWrite (NB_CFG, &RMWrite, StdHeader); + LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader); + LibAmdIoWrite (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader); + LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader); + } + //IDS_HDT_CONSOLE (LIB_PCI_WR, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value); + //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);; + //printk(BIOS_DEBUG, "LibAmdPciWrite\n"); + } else { + // Setup the MMIO address + ASSERT ((MMIOAddress + MMIOSize) > (MMIOAddress + (PciAddress.AddressValue & 0x0FFFFFFF))); + MMIOAddress += (PciAddress.AddressValue & 0x0FFFFFFF); + LibAmdMemWrite (AccessWidth, MMIOAddress, Value, StdHeader); + //IDS_HDT_CONSOLE (LIB_PCI_WR, "~MMIO WR %08x = %08x\n", (UINT32) MMIOAddress, *(UINT32 *)Value); + //printk(BIOS_DEBUG, "~MMIO WR %08x = %08x\n", (UINT32) MMIOAddress, *(UINT32 *)Value); + //printk(BIOS_DEBUG, "LibAmdPciWrite mmio\n"); + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * PCI read modify write + * + * + * @param[in] AccessWidth Access width + * @param[in] PciAddress Pci address + * @param[in] Data OR Data + * @param[in] DataMask Mask to be used before data write back to register. + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdPciRMW ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + IN VOID *Data, + IN VOID *DataMask, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempData = 0; + UINT32 TempMask = 0; + UINT32 Value; + LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); + LibAmdPciRead (AccessWidth, PciAddress, &Value, StdHeader); + Value = (Value & (~TempMask)) | TempData; + LibAmdPciWrite (AccessWidth, PciAddress, &Value, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Poll PCI config space register + * + * Poll register until (RegisterValue & DataMask) == Data + * + * @param[in] AccessWidth Access width + * @param[in] PciAddress Pci address + * @param[in] Data Data to compare + * @param[in] DataMask AND mask + * @param[in] Delay Poll for time in 100ns (not supported) + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdPciPoll ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + IN VOID *Data, + IN VOID *DataMask, + IN UINT64 Delay, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempData = 0; + UINT32 TempMask = 0; + UINT32 Value; + LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); + do { + LibAmdPciRead (AccessWidth, PciAddress, &Value, StdHeader); + } while (TempData != (Value & TempMask)); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Get MMIO base address for PCI accesses + * + * @param[out] MmioAddress PCI MMIO base address + * @param[out] MmioSize Size of region in bytes + * @param[in] StdHeader Standard configuration header + * + * @retval TRUE MmioAddress/MmioSize are valid + */ +BOOLEAN +STATIC +GetPciMmioAddress ( + OUT UINT64 *MmioAddress, + OUT UINT32 *MmioSize, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + BOOLEAN MmioIsEnabled; + UINT32 EncodedSize; + UINT64 LocalMsrRegister; + + ASSERT (StdHeader != NULL); + + MmioIsEnabled = FALSE; + LibAmdMsrRead (MSR_MMIO_Cfg_Base, &LocalMsrRegister, StdHeader); + if ((LocalMsrRegister & BIT0) != 0) { + *MmioAddress = LocalMsrRegister & 0xFFFFFFFFFFF00000; + EncodedSize = (UINT32) ((LocalMsrRegister & 0x3C) >> 2); + *MmioSize = ((1 << EncodedSize) * 0x100000); + MmioIsEnabled = TRUE; + } + return MmioIsEnabled; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Read field of PCI config register. + * + * + * + * @param[in] Address Pci address (register must be DWORD aligned) + * @param[in] Highbit High bit position of the field in DWORD + * @param[in] Lowbit Low bit position of the field in DWORD + * @param[out] Value Pointer to data + * @param[in] StdHeader Standard configuration header + */ +VOID +LibAmdPciReadBits ( + IN PCI_ADDR Address, + IN UINT8 Highbit, + IN UINT8 Lowbit, + OUT UINT32 *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + ASSERT (Highbit < 32 && Lowbit < 32 && Highbit >= Lowbit && (Address.AddressValue & 3) == 0); + + LibAmdPciRead (AccessWidth32, Address, Value, StdHeader); + *Value >>= Lowbit; // Shift + + // A 1 << 32 == 1 << 0 due to x86 SHL instruction, so skip if that is the case + + if ((Highbit - Lowbit) != 31) { + *Value &= (((UINT32) 1 << (Highbit - Lowbit + 1)) - 1); + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Write field of PCI config register. + * + * + * + * @param[in] Address Pci address (register must be DWORD aligned) + * @param[in] Highbit High bit position of the field in DWORD + * @param[in] Lowbit Low bit position of the field in DWORD + * @param[in] Value Pointer to data + * @param[in] StdHeader Standard configuration header + */ +VOID +LibAmdPciWriteBits ( + IN PCI_ADDR Address, + IN UINT8 Highbit, + IN UINT8 Lowbit, + IN UINT32 *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Temp; + UINT32 Mask; + + ASSERT (Highbit < 32 && Lowbit < 32 && Highbit >= Lowbit && (Address.AddressValue & 3) == 0); + + // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case + + if ((Highbit - Lowbit) != 31) { + Mask = (((UINT32) 1 << (Highbit - Lowbit + 1)) - 1); + } else { + Mask = (UINT32) 0xFFFFFFFF; + } + + LibAmdPciRead (AccessWidth32, Address, &Temp, StdHeader); + Temp &= ~(Mask << Lowbit); + Temp |= (*Value & Mask) << Lowbit; + LibAmdPciWrite (AccessWidth32, Address, &Temp, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Locate next capability pointer + * + * Given a SBDFO this routine will find the next PCI capabilities list entry. + * if the end of the list is reached, or if a problem is detected, then ILLEGAL_SBDFO is + * returned. + * To start a new search from the head of the list, specify a SBDFO with an offset of zero. + * + * @param[in,out] Address Pci address + * @param[in] StdHeader Standard configuration header + */ + +VOID +LibAmdPciFindNextCap ( + IN OUT PCI_ADDR *Address, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR Base; + UINT32 Offset; + UINT32 Temp; + PCI_ADDR TempAddress; + + ASSERT (Address != NULL); + ASSERT (*(UINT32 *) Address != ILLEGAL_SBDFO); + + Base.AddressValue = Address->AddressValue; + Offset = Base.Address.Register; + Base.Address.Register = 0; + + Address->AddressValue = (UINT32) ILLEGAL_SBDFO; + + // Verify that the SBDFO points to a valid PCI device SANITY CHECK + LibAmdPciRead (AccessWidth32, Base, &Temp, StdHeader); + if (Temp == 0xFFFFFFFF) { + ASSERT (FALSE); + return; // There is no device at this address + } + + // Verify that the device supports a capability list + TempAddress.AddressValue = Base.AddressValue + 0x04; + LibAmdPciReadBits (TempAddress, 20, 20, &Temp, StdHeader); + if (Temp == 0) { + return; // This PCI device does not support capability lists + } + + if (Offset != 0) { + // If we are continuing on an existing list + TempAddress.AddressValue = Base.AddressValue + Offset; + LibAmdPciReadBits (TempAddress, 15, 8, &Temp, StdHeader); + } else { + // We are starting on a new list + TempAddress.AddressValue = Base.AddressValue + 0x34; + LibAmdPciReadBits (TempAddress, 7, 0, &Temp, StdHeader); + } + + if (Temp == 0) { + return; // We have reached the end of the capabilities list + } + + // Error detection and recovery- The statement below protects against + // PCI devices with broken PCI capabilities lists. Detect a pointer + // that is not uint32 aligned, points into the first 64 reserved DWORDs + // or points back to itself. + if (((Temp & 3) != 0) || (Temp == Offset) || (Temp < 0x40)) { + ASSERT (FALSE); + return; + } + + Address->AddressValue = Base.AddressValue + Temp; + return; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Set memory with value + * + * + * @param[in,out] Destination Pointer to memory range + * @param[in] Value Value to set memory with + * @param[in] FillLength Size of the memory range + * @param[in] StdHeader Standard configuration header (Optional) + */ +VOID +LibAmdMemFill ( + IN VOID *Destination, + IN UINT8 Value, + IN UINTN FillLength, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 *Dest; + ASSERT (StdHeader != NULL); + Dest = Destination; + while ((FillLength--) != 0) { + *Dest++ = Value; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Copy memory + * + * + * @param[in,out] Destination Pointer to destination buffer + * @param[in] Source Pointer to source buffer + * @param[in] CopyLength buffer length + * @param[in] StdHeader Standard configuration header (Optional) + */ +VOID +LibAmdMemCopy ( + IN VOID *Destination, + IN VOID *Source, + IN UINTN CopyLength, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 *Dest; + UINT8 *SourcePtr; + ASSERT (StdHeader != NULL); + Dest = Destination; + SourcePtr = Source; + while ((CopyLength--) != 0) { + *Dest++ = *SourcePtr++; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Verify checksum of binary image (B1/B2/B3) + * + * + * @param[in] ImagePtr Pointer to image start + * @retval TRUE Checksum valid + * @retval FALSE Checksum invalid + */ +BOOLEAN +LibAmdVerifyImageChecksum ( + IN VOID *ImagePtr + ) +{ + // Assume ImagePtr points to the binary start ($AMD) + // Checksum is on an even boundary in AMD_IMAGE_HEADER + + UINT16 Sum; + UINT32 i; + + Sum = 0; + + i = ((AMD_IMAGE_HEADER*) ImagePtr)->ImageSize; + + while (i > 1) { + Sum = Sum + *((UINT16 *)ImagePtr); + ImagePtr = (VOID *) ((UINT8 *)ImagePtr + 2); + i = i - 2; + } + if (i > 0) { + Sum = Sum + *((UINT8 *) ImagePtr); + } + + return (Sum == 0)?TRUE:FALSE; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Locate AMD binary image that contain specific module + * + * + * @param[in] StartAddress Pointer to start range + * @param[in] EndAddress Pointer to end range + * @param[in] Alignment Image address alignment + * @param[in] ModuleSignature Module signature. + * @retval NULL if image not found + * @retval pointer to image header + */ +VOID * +LibAmdLocateImage ( + IN VOID *StartAddress, + IN VOID *EndAddress, + IN UINT32 Alignment, + IN CHAR8 ModuleSignature[8] + ) + +{ + UINT8 *CurrentPtr; + AMD_MODULE_HEADER *ModuleHeaderPtr; + UINT64 *SearchStr; + UINT64 *InputStr; + + CurrentPtr = StartAddress; + InputStr = (UINT64 *)ModuleSignature; + + // Search from start to end incrementing by alignment + while ((CurrentPtr >= (UINT8 *) StartAddress) && (CurrentPtr < (UINT8 *) EndAddress)) { + // First find a binary image + if (*((UINT32 *) CurrentPtr) == IMAGE_SIGNATURE) { + if (LibAmdVerifyImageChecksum (CurrentPtr)) { + // If we have a valid image, search module linked list for a match + ModuleHeaderPtr = (AMD_MODULE_HEADER*) ((UINT8 *)CurrentPtr + ((AMD_IMAGE_HEADER *) CurrentPtr)->ModuleInfoOffset); + while (ModuleHeaderPtr != NULL) { + SearchStr = (UINT64 *)&ModuleHeaderPtr->ModuleIdentifier; + if (*InputStr == *SearchStr) { + return CurrentPtr; + } + ModuleHeaderPtr = (AMD_MODULE_HEADER *)ModuleHeaderPtr->NextBlock; + } + } + } + CurrentPtr += Alignment; + } + return NULL; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the package type mask for the processor + * + * + * @param[in] StdHeader Standard configuration header (Optional) + */ + +// Returns the package type mask for the processor +UINT32 +LibAmdGetPackageType ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 ProcessorPackageType; + CPUID_DATA CpuId; + + LibAmdCpuidRead (0x80000001, &CpuId, StdHeader); + ProcessorPackageType = (UINT32) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28 + return (UINT32) (1 << ProcessorPackageType); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the package type mask for the processor + * + * + * @param[in] AccessWidth Access width + * @param[in] Data data + * @param[in] DataMask data + * @param[out] TemData typecast data + * @param[out] TempDataMask typecast data + */ + +VOID +STATIC +LibAmdGetDataFromPtr ( + IN ACCESS_WIDTH AccessWidth, + IN VOID *Data, + IN VOID *DataMask, + OUT UINT32 *TemData, + OUT UINT32 *TempDataMask + ) +{ + switch (AccessWidth) { + case AccessWidth8: + case AccessS3SaveWidth8: + *TemData = (UINT32)*(UINT8 *) Data; + *TempDataMask = (UINT32)*(UINT8 *) DataMask; + break; + case AccessWidth16: + case AccessS3SaveWidth16: + *TemData = (UINT32)*(UINT16 *) Data; + *TempDataMask = (UINT32)*(UINT16 *) DataMask; + break; + case AccessWidth32: + case AccessS3SaveWidth32: + *TemData = *(UINT32 *) Data; + *TempDataMask = *(UINT32 *) DataMask; + break; + default: + IDS_ERROR_TRAP; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the package type mask for the processor + * + * + * @param[in] AccessWidth Access width + * @retval Width in number of bytes + */ + +UINT8 +LibAmdAccessWidth ( + IN ACCESS_WIDTH AccessWidth + ) +{ + UINT8 Width; + + switch (AccessWidth) { + case AccessWidth8: + case AccessS3SaveWidth8: + Width = 1; + break; + case AccessWidth16: + case AccessS3SaveWidth16: + Width = 2; + break; + case AccessWidth32: + case AccessS3SaveWidth32: + Width = 4; + break; + case AccessWidth64: + case AccessS3SaveWidth64: + Width = 8; + break; + default: + Width = 0; + IDS_ERROR_TRAP; + } + return Width; +} + +VOID +CpuidRead ( + IN UINT32 CpuidFcnAddress, + OUT CPUID_DATA *Value + ) +{ + __cpuid ((int *)Value, CpuidFcnAddress); +} + +UINT8 +ReadNumberOfCpuCores( + VOID + ) +{ + CPUID_DATA Value; + CpuidRead (0x80000008, &Value); + return Value.ECX_Reg & 0xff; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.h b/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.h new file mode 100644 index 0000000..d95d22e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.h @@ -0,0 +1,398 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Library + * + * Contains interface to the AMD AGESA library + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Lib + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + **/ + +#ifndef _AMD_LIB_H_ +#define _AMD_LIB_H_ + +#define IOCF8 0xCF8 +#define IOCFC 0xCFC + +// Reg Values for ReadCpuReg and WriteCpuReg +#define CR4_REG 0x04 +#define DR0_REG 0x10 +#define DR1_REG 0x11 +#define DR2_REG 0x12 +#define DR3_REG 0x13 +#define DR7_REG 0x17 + +// PROTOTYPES FOR amdlib32.asm +UINT8 +ReadIo8 ( + IN UINT16 Address + ); + +UINT16 +ReadIo16 ( + IN UINT16 Address + ); + +UINT32 +ReadIo32 ( + IN UINT16 Address + ); + +VOID +WriteIo8 ( + IN UINT16 Address, + IN UINT8 Data + ); + +VOID +WriteIo16 ( + IN UINT16 Address, + IN UINT16 Data + ); + +VOID +WriteIo32 ( + IN UINT16 Address, + IN UINT32 Data + ); + +UINT8 +Read64Mem8 ( + IN UINT64 Address + ); + +UINT16 +Read64Mem16 ( + IN UINT64 Address + ); + +UINT32 +Read64Mem32 ( + IN UINT64 Address + ); + +VOID +Write64Mem8 ( + IN UINT64 Address, + IN UINT8 Data + ); + +VOID +Write64Mem16 ( + IN UINT64 Address, + IN UINT16 Data + ); + +VOID +Write64Mem32 ( + IN UINT64 Address, + IN UINT32 Data + ); + +UINT64 +ReadTSC ( + VOID); + +// MSR +VOID +LibAmdMsrRead ( + IN UINT32 MsrAddress, + OUT UINT64 *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdMsrWrite ( + IN UINT32 MsrAddress, + IN UINT64 *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +// IO +VOID +LibAmdIoRead ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + OUT VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdIoWrite ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + IN VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdIoRMW ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + IN VOID *Data, + IN VOID *DataMask, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdIoPoll ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + IN VOID *Data, + IN VOID *DataMask, + IN UINT64 Delay, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +// Memory or MMIO +VOID +LibAmdMemRead ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + OUT VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdMemWrite ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + IN VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdMemRMW ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + IN VOID *Data, + IN VOID *DataMask, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdMemPoll ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + IN VOID *Data, + IN VOID *DataMask, + IN UINT64 Delay, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +// PCI +VOID +LibAmdPciRead ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + OUT VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdPciWrite ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + IN VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdPciRMW ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + IN VOID *Data, + IN VOID *DataMask, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdPciPoll ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + IN VOID *Data, + IN VOID *DataMask, + IN UINT64 Delay, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdPciReadBits ( + IN PCI_ADDR Address, + IN UINT8 Highbit, + IN UINT8 Lowbit, + OUT UINT32 *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdPciWriteBits ( + IN PCI_ADDR Address, + IN UINT8 Highbit, + IN UINT8 Lowbit, + IN UINT32 *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdPciFindNextCap ( + IN OUT PCI_ADDR *Address, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +// CPUID +VOID +LibAmdCpuidRead ( + IN UINT32 CpuidFcnAddress, + OUT CPUID_DATA *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +// Utility Functions +VOID +LibAmdMemFill ( + IN VOID *Destination, + IN UINT8 Value, + IN UINTN FillLength, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdMemCopy ( + IN VOID *Destination, + IN VOID *Source, + IN UINTN CopyLength, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID * +LibAmdLocateImage ( + IN VOID *StartAddress, + IN VOID *EndAddress, + IN UINT32 Alignment, + IN CHAR8 ModuleSignature[8] + ); + +UINT32 +LibAmdGetPackageType ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +LibAmdVerifyImageChecksum ( + IN VOID *ImagePtr + ); + +UINT8 +LibAmdBitScanReverse ( + IN UINT32 value + ); +UINT8 +LibAmdBitScanForward ( + IN UINT32 value + ); + +VOID +LibAmdReadCpuReg ( + IN UINT8 RegNum, + OUT UINT32 *Value + ); +VOID +LibAmdWriteCpuReg ( + IN UINT8 RegNum, + IN UINT32 Value + ); + +VOID +LibAmdWriteBackInvalidateCache ( + IN VOID + ); + +VOID +LibAmdSimNowEnterDebugger (VOID); + +VOID +LibAmdHDTBreakPoint (VOID); + +UINT8 +LibAmdAccessWidth ( + IN ACCESS_WIDTH AccessWidth + ); + +VOID +LibAmdCLFlush ( + IN UINT64 Address, + IN UINT8 Count + ); + +VOID +LibAmdFinit ( + VOID); + +VOID +StopHere ( + VOID + ); + +#endif // _AMD_LIB_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Lib/helper.c b/src/vendorcode/amd/agesa/f15tn/Lib/helper.c new file mode 100644 index 0000000..2c5de90 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Lib/helper.c @@ -0,0 +1,68 @@ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +// helper.c - these functions are compiled separately because they redefine +// functions invoked directly by the compiler code generator. +// The Microsoft tools do not allow such functions to be compiled +// with the "Enable link-time code generation (/GL)" option. Compile +// this module without /GL to avoid a build failure LNK1237. +// + +#if defined (_MSC_VER) + +#include "Porting.h" + +//--------------------------------------------------------------------------- +void *memcpy (void *dest, const void *src, size_t bytes) + { + // Rep movsb is faster than a byte loop, but still quite slow + // for large operations. However, it is a good choice here because + // this function is intended for use by the compiler only. For + // large copy operations, call LibAmdMemCopy. + __movsb (dest, src, bytes); + return dest; + } + +//--------------------------------------------------------------------------- + +void *memset (void *dest, int value, size_t bytes) + { + // Rep stosb is faster than a byte loop, but still quite slow + // for large operations. However, it is a good choice here because + // this function is intended for use by the compiler only. For + // large fill operations, call LibAmdMemFill. + __stosb (dest, value, bytes); + return dest; + } +//--------------------------------------------------------------------------- + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Lib/x64/amdlib64.asm b/src/vendorcode/amd/agesa/f15tn/Lib/x64/amdlib64.asm new file mode 100644 index 0000000..467f4b7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Lib/x64/amdlib64.asm @@ -0,0 +1,629 @@ +;/** +; * @file +; * +; * Agesa library 64bit +; * +; * Contains AMD AGESA Library +; * +; * @xrefitem bom "File Content Label" "Release Content" +; * @e project: AGESA +; * @e sub-project: Lib +; * @e $Revision: 17071 $ @e $Date: 2009-07-30 10:13:11 -0700 (Thu, 30 Jul 2009) $ +; */ +;***************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;***************************************************************************** + +.code +;/*++ + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * Write IO byte +; * +; * @param[in] CX IO port address +; * @param[in] DL IO port Value +; */ + +PUBLIC WriteIo8 +WriteIo8 PROC + mov al, dl + mov dx, cx + out dx, al + ret +WriteIo8 ENDP + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * Write IO word +; * +; * @param[in] CX IO port address +; * @param[in] DX IO port Value +; */ +PUBLIC WriteIo16 +WriteIo16 PROC + mov ax, dx + mov dx, cx + out dx, ax + ret +WriteIo16 ENDP + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * Write IO dword +; * +; * @param[in] CX IO port address +; * @param[in] EDX IO port Value +; */ + +PUBLIC WriteIo32 +WriteIo32 PROC + mov eax, edx + mov dx, cx + out dx, eax + ret +WriteIo32 ENDP + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * Read IO byte +; * +; * @param[in] CX IO port address +; * @retval AL IO port Value +; */ +PUBLIC ReadIo8 +ReadIo8 PROC + mov dx, cx + in al, dx + ret +ReadIo8 ENDP + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * Read IO word +; * +; * @param[in] CX IO port address +; * @retval AX IO port Value +; */ +PUBLIC ReadIo16 +ReadIo16 PROC + mov dx, cx + in ax, dx + ret +ReadIo16 ENDP + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * Read IO dword +; * +; * @param[in] CX IO port address +; * @retval EAX IO port Value +; */ +PUBLIC ReadIo32 +ReadIo32 PROC + mov dx, cx + in eax, dx + ret +ReadIo32 ENDP + + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * Read MSR +; * +; * @param[in] RCX MSR Address +; * @param[in] RDX Pointer to data +; * @param[in] R8D ConfigPtr (Optional) +; */ +PUBLIC LibAmdMsrRead +LibAmdMsrRead PROC + push rsi + mov rsi, rdx + rdmsr + mov [rsi], eax + mov [rsi+4], edx + pop rsi + ret +LibAmdMsrRead ENDP + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * Write MSR +; * +; * @param[in] RCX MSR Address +; * @param[in] RDX Pointer to data +; * @param[in] R8D ConfigPtr (Optional) +; */ +PUBLIC LibAmdMsrWrite +LibAmdMsrWrite PROC + push rsi + mov rsi, rdx + mov eax, [rsi] + and rax, 0ffffffffh + mov edx, [rsi+4] + and rdx, 0ffffffffh + wrmsr + pop rsi + ret +LibAmdMsrWrite ENDP + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * Read CPUID +; * +; * @param[in] RCX CPUID function +; * @param[in] RDX Pointer to CPUID_DATA to save cpuid data +; * @param[in] R8D ConfigPtr (Optional) +; */ +PUBLIC LibAmdCpuidRead +LibAmdCpuidRead PROC + + push rbx + push rsi + mov rsi, rdx + mov rax, rcx + cpuid + mov [rsi], eax + mov [rsi+4], ebx + mov [rsi+8], ecx + mov [rsi+12],edx + pop rsi + pop rbx + ret + +LibAmdCpuidRead ENDP + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * Read TSC +; * +; * +; * @retval RAX Time stamp counter value +; */ + +PUBLIC ReadTSC +ReadTSC PROC + rdtsc + and rax, 0ffffffffh + shl rdx, 32 + or rax, rdx + ret +ReadTSC ENDP + + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * Read memory/MMIO byte +; * +; * @param[in] RCX - Memory Address +; * @retval Memory byte at given address +; */ +PUBLIC Read64Mem8 +Read64Mem8 PROC + + xor rax, rax + mov al, [rcx] + ret + +Read64Mem8 ENDP + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * Read memory/MMIO word +; * +; * @param[in] RCX - Memory Address +; * @retval Memory word at given address +; */ +PUBLIC Read64Mem16 +Read64Mem16 PROC + + xor rax, rax + mov ax, [rcx] + ret + +Read64Mem16 ENDP + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * Read memory/MMIO dword +; * +; * @param[in] RCX - Memory Address +; * @retval Memory dword at given address +; */ +PUBLIC Read64Mem32 +Read64Mem32 PROC + + xor rax, rax + mov eax, [rcx] + ret + +Read64Mem32 ENDP + + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * Write memory/MMIO byte +; * +; * @param[in] RCX Memory Address +; * @param[in] DL Value to write +; */ + +PUBLIC Write64Mem8 +Write64Mem8 PROC + + xor rax, rax + mov rax, rdx + mov [rcx], al + ret + +Write64Mem8 ENDP + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * Write memory/MMIO word +; * +; * @param[in] RCX Memory Address +; * @param[in] DX Value to write +; */ +PUBLIC Write64Mem16 +Write64Mem16 PROC + + xor rax, rax + mov rax, rdx + mov [rcx], ax + ret + +Write64Mem16 ENDP + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * Write memory/MMIO dword +; * +; * @param[in] RCX Memory Address +; * @param[in] EDX Value to write +; */ +PUBLIC Write64Mem32 +Write64Mem32 PROC + + xor rax, rax + mov rax, rdx + mov [rcx], eax + ret + +Write64Mem32 ENDP + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * Read various CPU registers +; * +; * @param[in] CL Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7) +; * @param[in] RDX Pointer to value +; */ + +PUBLIC LibAmdReadCpuReg +LibAmdReadCpuReg PROC + + push rax + xor rax, rax +Reg00h: + cmp cl, 00h + jne Reg04h + mov rax, cr0 + jmp RegRead +Reg04h: + cmp cl, 04h + jne Reg10h + mov rax, cr4 + jmp RegRead +Reg10h: + cmp cl, 10h + jne Reg11h + mov rax, dr0 + jmp RegRead +Reg11h: + cmp cl, 11h + jne Reg12h + mov rax, dr1 + jmp RegRead +Reg12h: + cmp cl, 12h + jne Reg13h + mov rax, dr2 + jmp RegRead +Reg13h: + cmp cl, 13h + jne Reg17h + mov rax, dr3 + jmp RegRead +Reg17h: + cmp cl, 17h + jne RegRead + mov rax, dr7 +RegRead: + mov [rdx], eax + pop rax + ret +LibAmdReadCpuReg ENDP + + + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * Write various CPU registers +; * +; * @param[in] CL Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7) +; * @param[in] RDX Value to write +; */ + +PUBLIC LibAmdWriteCpuReg +LibAmdWriteCpuReg PROC + + push rax +Reg00h: + cmp cl, 00h + jne Reg04h + mov rax, cr0 + mov eax, edx + mov cr0, rax + jmp Done +Reg04h: + cmp cl, 04h + jne Reg10h + mov rax, cr4 + mov eax, edx + mov cr4, rax + jmp Done +Reg10h: + cmp cl, 10h + jne Reg11h + mov rax, dr0 + mov eax, edx + mov dr0, rax + jmp Done +Reg11h: + cmp cl, 11h + jne Reg12h + mov rax, dr1 + mov eax, edx + mov dr1, rax + jmp Done +Reg12h: + cmp cl, 12h + jne Reg13h + mov rax, dr2 + mov eax, edx + mov dr2, rax + jmp Done +Reg13h: + cmp cl, 13h + jne Reg17h + mov rax, dr3 + mov eax, edx + mov dr3, rax + jmp Done +Reg17h: + cmp cl, 17h + jne Done + mov rax, dr7 + mov eax, edx + mov dr7, rax +Done: + pop rax + ret +LibAmdWriteCpuReg ENDP + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * Write back invalidate caches using wbinvd. +; * +; * +; * +; */ + +PUBLIC LibAmdWriteBackInvalidateCache +LibAmdWriteBackInvalidateCache PROC + wbinvd + ret +LibAmdWriteBackInvalidateCache ENDP + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * Stop CPU +; * +; * +; * +; */ + +PUBLIC StopHere +StopHere PROC +@@: + jmp short @b +StopHere ENDP + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * Enter debugger on SimNow +; * +; * +; * +; */ +PUBLIC LibAmdSimNowEnterDebugger +LibAmdSimNowEnterDebugger PROC + pushfq + mov rax, 0BACCD00Bh ; Backdoor in SimNow + mov rbx, 2 ; Select breakpoint feature + cpuid +@@: + jmp short @b + popfq + ret +LibAmdSimNowEnterDebugger ENDP + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * IDS IO port write +; * +; * @param[in] ECX IO Port Address +; * @param[in] EDX Value to write +; * @param[in] R8D IDS flags +; * +; */ + +PUBLIC IdsOutPort +IdsOutPort PROC + push rbx + push rax + + mov ebx, r8d + mov eax, edx + mov edx, ecx + out dx, eax + + pop rax + pop rbx + ret +IdsOutPort ENDP + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * Force breakpoint on HDT +; * +; * +; */ +PUBLIC LibAmdHDTBreakPoint +LibAmdHDTBreakPoint PROC + + push rbx + + mov rcx, 0C001100Ah ;bit 0 = HDT redirect + mov rdi, 09C5A203Ah ;Password + rdmsr + and rax, 0ffffffffh + or rax, 1 + + wrmsr + + mov rax, 0B2h ;Marker = B2 + db 0F1h ;ICEBP + + pop rbx + ret + +LibAmdHDTBreakPoint ENDP + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * Find the most right hand side non-zero bit with +; * +; * @param[in] ECX Value +; */ +PUBLIC LibAmdBitScanForward +LibAmdBitScanForward PROC + bsf eax, ecx + jnz nonZeroSource + mov al,32 +nonZeroSource: + ret +LibAmdBitScanForward ENDP + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * Find the most left hand side non-zero bit. +; * +; * @param[in] ECX Value +; */ +PUBLIC LibAmdBitScanReverse +LibAmdBitScanReverse PROC + bsr eax, ecx + jnz nonZeroSource + mov al,0FFh +nonZeroSource: + ret +LibAmdBitScanReverse ENDP + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * Flush specified number of cache line +; * +; * @param[in] RCX Physical address to be flushed +; * @param[in] DL number of cachelines to be flushed +; */ +PUBLIC LibAmdCLFlush +LibAmdCLFlush PROC + push rax + mov rax, rcx + movzx rcx, dl + @@: + mfence + clflush [rax] + mfence + add rax,64 + loop @B + pop rax + ret +LibAmdCLFlush ENDP + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * FPU init +; * +; * +; */ +PUBLIC LibAmdFinit +LibAmdFinit PROC + finit + ret +LibAmdFinit ENDP + +END diff --git a/src/vendorcode/amd/agesa/f15tn/MainPage.h b/src/vendorcode/amd/agesa/f15tn/MainPage.h new file mode 100644 index 0000000..1ec2fa0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/MainPage.h @@ -0,0 +1,148 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Create outline and references for mainpage documentation. + * + * Design guides, maintenance guides, and general documentation, are + * collected using this file onto the documentation mainpage. + * This file contains doxygen comment blocks, only. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Documentation + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/** + * @mainpage + * + * The design and maintenance documentation for AGESA Sample Code is organized as + * follows. On this page, you can reference design guides, maintenance guides, and + * general documentation. Detailed Data Structure, Function, and Interface documentation + * may be found using the Data Structures or Files tabs. See Related Pages for a + * Release content summary, and, if this is not a production release, lists of To Do's, + * Deprecated items, etc. + * + * @subpage starthere "Start Here - Initial Porting and Integration." + * + * @subpage optionmain "Build Configuration and Options Guides and Documentation." + * + * @subpage commonmain "Processor Common Component Guides and Documentation." + * + * @subpage cpumain "CPU Component Guides and Documentation." + * + * @subpage htmain "HT Component Guides and Documentation." + * + * @subpage memmain "MEM Component Guides and Documentation." + * + * @subpage gnbmain "GNB Component Documentation." + * + * @subpage fchmain "FCH Component Documentation." + * + * @subpage idsmain "IDS Component Guides and Documentation." + * + * @subpage recoverymain "Recovery Component Guides and Documentation." + * + */ + +/** + * @page starthere Initial Porting and Integration + * + * @par Basic Check List + * + * <ul> + * <li> Copy the <plat>Options.c file from the Addendum directory to the platform tip build directory. + * AMD recommends the use of a sub-directory named AGESA to contain these files and the build output files. + * <li> Copy the OptionsIds.h content in the spec to OptionsIds.h in the platform build tip directory + * and make changes to enable the IDS support desired. It is highly recommended to set the following for + * initial integration and development:@n + * @code + * #define IDSOPT_IDS_ENABLED TRUE + * #define IDSOPT_ERROR_TRAP_ENABLED TRUE + * #define IDSOPT_ASSERT_ENABLED TRUE + * @endcode + * <li> Edit and modify the option selections in those two files to meet the needs of the specific platform. + * <li> Set the environment variable AGESA_ROOT to the root folder of the AGESA code. + * <li> Set the environment variable AGESA_OptsDir the platform build tip AGESA directory. + * <li> Generate the doxygen documentation or locate the file arch2008.chm within your AGESA release package. + * </ul> + * + * @par Debugging Using ASSERT and IDS_ERROR_TRAP + * + * While AGESA code uses ::ASSERT and ::IDS_ERROR_TRAP to check for internal errors, these macros can also + * catch and assist debug of wrapper and platform BIOS issues. + * + * When an ::ASSERT fails or an ::IDS_ERROR_TRAP is executed, the AGESA code will enter a halt loop and display a + * Stop Code. A Stop Code is eight hex digits. The first (most significant) four are the FILECODE. + * FILECODEs can be looked up in Filecode.h to determine which file contains the stop macro. Each file has a + * unique code value. + * The least significant digits are the line number in that file. + * For example, 0210 means the macro is on line two hundred ten. + * (see ::IdsErrorStop for more details on stop code display.) + * + * Enabling ::ASSERT and ::IDS_ERROR_TRAP ensure errors are caught and also provide a useful debug assist. + * Comments near each macro use will describe the nature of the error and typical wrapper errors or other + * root causes. + * + * After your wrapper consistently executes ::ASSERT and ::IDS_ERROR_TRAP stop free, you can disable them in + * OptionsIds.h, except for regression testing. IDS is not expected to be enabled in production BIOS builds. + * + */ diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc new file mode 100644 index 0000000..f90e7b1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc @@ -0,0 +1,95 @@ +#***************************************************************************** +# +# Copyright (c) 2012, Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Advanced Micro Devices, Inc. nor the names of +# its contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +#***************************************************************************** + +# AGESA V5 Files +AGESA_ROOT = src/vendorcode/amd/agesa/f15tn + +AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR) +AGESA_INC += -I$(AGESA_ROOT) +AGESA_INC += -I$(AGESA_ROOT)/Include +AGESA_INC += -I$(AGESA_ROOT)/Lib +AGESA_INC += -I$(AGESA_ROOT)/Legacy +AGESA_INC += -I$(AGESA_ROOT)/Proc/Common +AGESA_INC += -I$(AGESA_ROOT)/Proc/HT +AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU +AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Feature +AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family +AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family/0x15 +AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family/0x15/TN +AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem +AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/NB/TN +AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS +AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Family +AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Family/0x15 +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Common +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Nb +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Nb/Family +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Nb/Family/0x15 +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Nb/Feature +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/PCIe +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/PCIe/Family +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x15 +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/PCIe/Feature +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Gfx +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Gfx/Family +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1 +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1 +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbNbInitLibV1 +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbSbLib +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieTrainingV1 +AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Family/0x15/TN +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib +AGESA_INC += -I$(AGESA_ROOT)/Proc/HT/NbCommon +AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/Main +AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Library +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbNbInitLibV4 +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbIommuIvrs +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbIvrsLib +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbSbIommuLib +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbTable +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4 +AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch +AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common +AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Debug +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieAspm +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Include/Library + +AGESA_INC += -I$(src)/southbridge/amd/agesa/hudson + +AGESA_CFLAGS =-march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing + +export AGESA_ROOT := $(AGESA_ROOT) +export AGESA_INC := $(AGESA_INC) +export AGESA_CFLAGS := $(AGESA_CFLAGS) +CC := $(CC) $(AGESA_INC) $(AGESA_CFLAGS) +####################################################################### diff --git a/src/vendorcode/amd/agesa/f15tn/Porting.h b/src/vendorcode/amd/agesa/f15tn/Porting.h new file mode 100644 index 0000000..4ab5859 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Porting.h @@ -0,0 +1,309 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Describes compiler dependencies - to support several compile time environments + * + * Contains compiler environment porting descriptions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Includes + * @e $Revision: 44324 $ @e $Date: 2010-12-22 03:16:51 -0600 (Wed, 22 Dec 2010) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2011 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _PORTING_H_ +#define _PORTING_H_ + +#if defined (_MSC_VER) + #include <intrin.h> + void _disable (void); + void _enable (void); + #pragma warning(disable: 4103 4001 4733) + #pragma intrinsic (_disable, _enable) + #pragma warning(push) + // ----------------------------------------------------------------------- + // Define a code_seg MACRO + // + #define MAKE_AS_A_STRING(arg) #arg + + #define CODE_GROUP(arg) __pragma (code_seg (MAKE_AS_A_STRING (.t##arg))) + + #define RDATA_GROUP(arg) __pragma (const_seg (MAKE_AS_A_STRING (.d##arg))) + #define FUNC_ATTRIBUTE(arg) __declspec(arg) + //#include <intrin.h> // MS has built-in functions + + #if _MSC_VER < 900 + // ----------------------------------------------------------------------- + // Assume MSVC 1.52C (16-bit) + // + // NOTE: When using MSVC 1.52C use the following command line: + // + // CL.EXE /G3 /AL /O1i /Fa <FILENAME.C> + // + // This will produce 32-bit code in USE16 segment that is optimized for code + // size. + typedef void VOID; + + // Create the universal 32, 16, and 8-bit data types + typedef unsigned long UINTN; + typedef long INT32; + typedef unsigned long UINT32; + typedef int INT16; + typedef unsigned int UINT16; + typedef char INT8; + typedef unsigned char UINT8; + typedef char CHAR8; + typedef unsigned short CHAR16; + + /// struct for 16-bit environment handling of 64-bit value + typedef struct _UINT64 { + IN OUT UINT32 lo; ///< lower 32-bits of 64-bit value + IN OUT UINT32 hi; ///< highest 32-bits of 64-bit value + } UINT64; + + // Create the Boolean type + #define TRUE 1 + #define FALSE 0 + typedef unsigned char BOOLEAN; + + #define CONST const + #define STATIC static + #define VOLATILE volatile + #define CALLCONV __pascal + #define ROMDATA __based( __segname( "_CODE" ) ) + #define _16BYTE_ALIGN __declspec(align(16)) + + // Force tight packing of structures + // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 + #pragma warning( disable : 4103 ) // Disable '#pragma pack' in .h warning + #pragma pack(1) + + // Disable WORD->BYTE automatic conversion warnings. Example: + // BYTE LocalByte; + // void MyFunc(BYTE val); + // + // MyFunc(LocalByte*2+1); // Warning, automatic conversion + // + // The problem is any time math is performed on a BYTE, it is converted to a + // WORD by MSVC 1.52c, and then when it is converted back to a BYTE, a warning + // is generated. Disable warning C4761 + #pragma warning( disable : 4761 ) + + #else + // ----------------------------------------------------------------------- + // Assume a 32-bit MSVC++ + // + // Disable the following warnings: + // 4100 - 'identifier' : unreferenced formal parameter + // 4276 - 'function' : no prototype provided; assumed no parameters + // 4214 - non standard extension used : bit field types other than int + // 4001 - nonstandard extension 'single line comment' was used + // 4142 - benign redefinition of type for following declaration + // - typedef char INT8 + #if defined (_M_IX86) + #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306) + + #ifndef VOID + typedef void VOID; + #endif + // Create the universal 32, 16, and 8-bit data types + #ifndef UINTN + typedef unsigned __w64 UINTN; + #endif + typedef __int64 INT64; + typedef unsigned __int64 UINT64; + typedef int INT32; + typedef unsigned int UINT32; + typedef short INT16; + typedef unsigned short UINT16; + typedef char INT8; + typedef unsigned char UINT8; + typedef char CHAR8; + typedef unsigned short CHAR16; + + // Create the Boolean type + #ifndef TRUE + #define TRUE 1 + #endif + #ifndef FALSE + #define FALSE 0 + #endif + typedef unsigned char BOOLEAN; + + // Force tight packing of structures + // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 + #pragma pack(1) + + #define CONST const + #define STATIC static + #define VOLATILE volatile + #define CALLCONV + #define ROMDATA + #define _16BYTE_ALIGN __declspec(align(64)) + // 64 bit of compiler + #else + #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306 4366) + + #ifndef VOID + typedef void VOID; + #endif + // Create the universal 32, 16, and 8-bit data types + #ifndef UINTN + typedef unsigned __int64 UINTN; + #endif + typedef __int64 INT64; + typedef unsigned __int64 UINT64; + typedef int INT32; + typedef unsigned int UINT32; + typedef short INT16; + typedef unsigned short UINT16; + typedef char INT8; + typedef unsigned char UINT8; + typedef char CHAR8; + typedef unsigned short CHAR16; + + // Create the Boolean type + #ifndef TRUE + #define TRUE 1 + #endif + #ifndef FALSE + #define FALSE 0 + #endif + typedef unsigned char BOOLEAN; + + // Force tight packing of structures + // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 + #pragma pack(1) + + #define CONST const + #define STATIC static + #define VOLATILE volatile + #define CALLCONV + #define ROMDATA + #endif + #endif + // ----------------------------------------------------------------------- + // End of MS compiler versions + +#elif defined __GNUC__ + + #define IN + #define OUT + #define STATIC static + #define VOLATILE volatile + #define TRUE 1 + #define FALSE 0 +// #undef CONST + #define CONST const + #define ROMDATA + #define CALLCONV + #define _16BYTE_ALIGN __attribute__ ((aligned (16))) + + typedef unsigned char BOOLEAN; + typedef signed char INT8; + typedef signed short INT16; + typedef signed long INT32; + typedef char CHAR8; + typedef unsigned char UINT8; + typedef unsigned short UINT16; + typedef unsigned long UINT32; + typedef unsigned long UINTN; + typedef unsigned long long UINT64; + typedef long long INT64; + typedef void VOID; + //typedef unsigned long size_t; + + //#include <intrin.h> // MingW-w64 library header +#pragma pack(1) + +#define CODE_GROUP(arg) +#define RDATA_GROUP(arg) + +#define FUNC_ATTRIBUTE(arg) __attribute__((arg)) +#define MAKE_AS_A_STRING(arg) #arg +#include <stddef.h> +#include "gcc-intrin.h" + +#include <assert.h> +#include <console/console.h> +#include <console/loglevel.h> + +#ifndef NULL + #define NULL (void *)0 +#endif + +#else + // ----------------------------------------------------------------------- + // Unknown or unsupported compiler + // + #error "Unknown compiler in use" +#endif + +// ----------------------------------------------------------------------- +// Common definitions for all compilers +// + +//Support forward reference construct +#define AGESA_FORWARD_DECLARATION(x) typedef struct _##x x + +// The following are use in conformance to the UEFI style guide +#define IN +#define OUT + +#endif // _PORTING_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/F15PstateHpcMode.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/F15PstateHpcMode.c new file mode 100644 index 0000000..738cf39 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/F15PstateHpcMode.c @@ -0,0 +1,234 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 P-state HPC mode Initialization + * + * Enables High performance Computing mode. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15 + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "GeneralServices.h" +#include "cpuServices.h" +#include "cpuRegisters.h" +#include "cpuFamilyTranslation.h" +#include "heapManager.h" +#include "cpuF15PowerMgmt.h" +#include "CommonReturns.h" +#include "cpuPstateHpcMode.h" +#include "cpuPstateTables.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_F15PSTATEHPCMODE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * entry point for enabling High Performance Computing. + * + * This function must be run after P-states initialization and before enabling low power P-states + * + * @param[in] PstateHpcModeServices The current CPU's family services. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config handle for library and services. + * + * @retval AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +STATIC +F15InitializePstateHpcMode ( + IN PSTATE_HPC_MODE_FAMILY_SERVICES *PstateHpcModeServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 OriginalPstate; + UINT8 X; + UINT32 Socket; + UINT32 Module; + UINT32 Core; + UINT32 SocketCount; + UINT32 i; + UINT64 MsrData; + PCI_ADDR PciAddr; + AGESA_STATUS IgnoredSts; + AGESA_STATUS Flag; + F15_CPB_CTRL_REGISTER CpbCtrl; + CLK_PWR_TIMING_CTRL2_REGISTER CPTC2; + HTC_REGISTER Htc; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + LOCATE_HEAP_PTR LocateHeapParams; + PSTATE_LEVELING *PStateLevelingBuffer; + PSTATE_LEVELING *PStateLevelingBufferTemp; + + Flag = AGESA_SUCCESS; + // Locate P-State data buffer + LocateHeapParams.BufferHandle = AMD_PSTATE_DATA_BUFFER_HANDLE; + if (HeapLocateBuffer (&LocateHeapParams, StdHeader) != AGESA_SUCCESS) { + Flag = AGESA_ERROR; + PStateLevelingBuffer = NULL; + SocketCount = 1; + } else { + PStateLevelingBuffer = ((S_CPU_AMD_PSTATE *) (LocateHeapParams.BufferPtr))->PStateLevelingStruc; + SocketCount = ((S_CPU_AMD_PSTATE *) (LocateHeapParams.BufferPtr))->TotalSocketInSystem; + } + + // Step1. Read MSRC001_0063[CurPstate] and store the value in OriginalPstate. + LibAmdMsrRead (MSR_PSTATE_STS, &MsrData, StdHeader); + OriginalPstate = (UINT8) (((PSTATE_STS_MSR *) &MsrData)->CurPstate); + // Step2. Write 0 to MSRC001_0062[PstateCmd]. + // Step3. Wait for MSRC001_0063[CurPstate] == 0. + GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); + FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader); + // Step4. If D18F4x15C[NumBoostStates] != D18F3xDC[PstateMaxVal], execute the following sequence + // 4.A Set X = D18F4x15C[NumBoostStates]. + // 4.B If X+1 == D18F3xDC[PstateMaxVal], go to step 5. + // 4.C Copy MSRC001_00[6B:64] indexed by P-state X to MSRC001_00[6B:64] indexed by P-state X+1. + // 4.D Write 0b to PstateEn from MSRC001_00[6B:64] indexed by P-state X+1. + // 4.E Set X = X+1 and go to step B. + IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); + GetPciAddress (StdHeader, Socket, Module, &PciAddr, &IgnoredSts); + PciAddr.Address.Function = FUNC_4; + PciAddr.Address.Register = CPB_CTRL_REG; + LibAmdPciRead (AccessWidth32, PciAddr, &CpbCtrl, StdHeader); // F4x15C + + PciAddr.Address.Function = FUNC_3; + PciAddr.Address.Register = CPTC2_REG; + LibAmdPciRead (AccessWidth32, PciAddr, &CPTC2, StdHeader); // F3xDC + + // In case that F3xDC[PstateMaxVal] was increased by Low Power Pstate function during the first time of running that function. + // Get the real PstateMaxVal by checking C001_00[6B:64][PsEnable] + while (CPTC2.PstateMaxVal != 0) { + LibAmdMsrRead ((PS_REG_BASE + CPTC2.PstateMaxVal), &MsrData, StdHeader); + if ((MsrData & BIT63) == BIT63) { + break; + } + CPTC2.PstateMaxVal--; + } + + if (CpbCtrl.NumBoostStates != CPTC2.PstateMaxVal) { + X = (UINT8) CpbCtrl.NumBoostStates; + while ((X + 1) < (UINT8) CPTC2.PstateMaxVal) { + LibAmdMsrRead ((PS_REG_BASE + X), &MsrData, StdHeader); + MsrData &= ~BIT63; + LibAmdMsrWrite ((PS_REG_BASE + X + 1), &MsrData, StdHeader); + // Make sure Agesa doesn't declared the P-states modified by these algorithms to the OS + if (PStateLevelingBuffer != NULL) { + PStateLevelingBufferTemp = PStateLevelingBuffer; + for (i = 0; i < SocketCount; i++) { + PStateLevelingBufferTemp->PStateCoreStruct[0].PStateStruct[X + 1].PStateEnable = 0; + //Calculate next node buffer address + PStateLevelingBufferTemp = (PSTATE_LEVELING *) ((UINT8 *) PStateLevelingBufferTemp + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateLevelingBufferTemp->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES))); + } + } + X++; + } + } + // Step5. Write OriginalPstate to MSRC001_0062[PstateCmd]. + // Step6. Wait for MSRC001_0063[CurPstate] == OriginalPstate. + FamilySpecificServices->TransitionPstate (FamilySpecificServices, OriginalPstate, (BOOLEAN) TRUE, StdHeader); + // Step7. Write D18F3x64[HtcPstateLimit] with the value from D18F3xDC[PstateMaxVal] + PciAddr.Address.Register = HTC_REG; + LibAmdPciRead (AccessWidth32, PciAddr, &Htc, StdHeader); // F3x64 + Htc.HtcPstateLimit = CPTC2.PstateMaxVal; + LibAmdPciWrite (AccessWidth32, PciAddr, &Htc, StdHeader); // F3x64 + + return Flag; +} + + + +CONST PSTATE_HPC_MODE_FAMILY_SERVICES ROMDATA F15PstateHpcSupport = +{ + 0, + F15InitializePstateHpcMode +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnC6State.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnC6State.c new file mode 100644 index 0000000..77243c2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnC6State.c @@ -0,0 +1,224 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity C6 C-state feature support functions. + * + * Provides the functions necessary to initialize the C6 feature. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/F15/TN + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuFeatures.h" +#include "cpuC6State.h" +#include "cpuApicUtilities.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "cpuEarlyInit.h" +#include "cpuServices.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNC6STATE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +F15TnReloadMicrocodePatchAfterMemInit ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Is C6 supported on this CPU + * + * @param[in] C6Services Pointer to this CPU's C6 family services. + * @param[in] Socket This core's zero-based socket number. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE C6 state is supported. + * @retval FALSE C6 state is not supported. + * + */ +BOOLEAN +STATIC +F15TnIsC6Supported ( + IN C6_FAMILY_SERVICES *C6Services, + IN UINT32 Socket, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + ASSERT (IsFeatureEnabled (CacheFlushOnHalt, PlatformConfig, StdHeader) == TRUE); + // Assuming CFOH is always enabled. + return (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader)); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Enable C6 on a family 15h CPU. + * + * @param[in] C6Services Pointer to this CPU's C6 family services. + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @return AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +STATIC +F15TnInitializeC6 ( + IN C6_FAMILY_SERVICES *C6Services, + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + CSTATE_CTRL1_REGISTER CstateCtrl1; + POPUP_PSTATE_REGISTER PopDownPstate; + CLK_PWR_TIMING_CTRL2_REGISTER ClkPwrTimingCtrl2; + + if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) { + // Initialize F4x118 + PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader); + // Set C-state Action Field 0 + CstateCtrl1.PwrGateEnCstAct0 = 1; + CstateCtrl1.PwrOffEnCstAct0 = 1; + CstateCtrl1.NbPwrGate0 = 1; + CstateCtrl1.NbClkGate0 = 1; + CstateCtrl1.SelfRefr0 = 1; + CstateCtrl1.CpuPrbEnCstAct0 = 1; + // Set C-state Action Field 1 + CstateCtrl1.PwrGateEnCstAct1 = 1; + CstateCtrl1.PwrOffEnCstAct1 = 1; + CstateCtrl1.NbPwrGate1 = 1; + CstateCtrl1.NbClkGate1 = 1; + CstateCtrl1.SelfRefr1 = 1; + CstateCtrl1.CpuPrbEnCstAct1 = 1; + LibAmdPciWrite (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader); + + // Initialize F3xA8[PopDownPstate] = F3xDC[PstateMaxVal] + PciAddress.AddressValue = CPTC2_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); + PciAddress.AddressValue = POPUP_PSTATE_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &PopDownPstate, StdHeader); + PopDownPstate.PopDownPstate = ClkPwrTimingCtrl2.PstateMaxVal; + LibAmdPciWrite (AccessWidth32, PciAddress, &PopDownPstate, StdHeader); + } + + return AGESA_SUCCESS; +} + +/** + * Reload microcode patch after memory is initialized. + * + * @param[in] StdHeader Config Handle for library, services. + * + */ +VOID +F15TnReloadMicrocodePatchAfterMemInit ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + LoadMicrocodePatch (StdHeader); +} + +CONST C6_FAMILY_SERVICES ROMDATA F15TnC6Support = +{ + 0, + F15TnIsC6Supported, + F15TnInitializeC6, + F15TnReloadMicrocodePatchAfterMemInit +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c new file mode 100644 index 0000000..0089c04 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c @@ -0,0 +1,204 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 CPB Initialization + * + * Enables core performance boost. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/F15/TN + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "cpuFeatures.h" +#include "cpuCpb.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNCPB_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * BSC entry point for checking whether or not CPB is supported. + * + * @param[in] CpbServices The current CPU's family services. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] Socket Zero based socket number to check. + * @param[in] StdHeader Config handle for library and services. + * + * @retval TRUE CPB is supported. + * @retval FALSE CPB is not supported. + * + */ +BOOLEAN +STATIC +F15TnIsCpbSupported ( + IN CPB_FAMILY_SERVICES *CpbServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN UINT32 Socket, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + CPB_CTRL_REGISTER CpbControl; + PCI_ADDR PciAddress; + + PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader); + return (BOOLEAN) (CpbControl.NumBoostStates != 0); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * BSC entry point for for enabling Core Performance Boost. + * + * Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG. + * + * @param[in] CpbServices The current CPU's family services. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] EntryPoint Current CPU feature dispatch point. + * @param[in] Socket Zero based socket number to check. + * @param[in] StdHeader Config handle for library and services. + * + * @retval AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +STATIC +F15TnInitializeCpb ( + IN CPB_FAMILY_SERVICES *CpbServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN UINT64 EntryPoint, + IN UINT32 Socket, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + CPB_CTRL_REGISTER CpbControl; + PCI_ADDR PciAddress; + F15_PSTATE_MSR PstateMsrData; + UINT32 Pbx; + + if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) { + PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader); + if (CpbControl.NumBoostStates == 0) { + CpbControl.ApmMasterEn = 0; + } else { + CpbControl.ApmMasterEn = 1; + } + LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader); + + } else if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) { + PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader); + if ((CpbControl.BoostSrc == 0) && (CpbControl.NumBoostStates != 0)) { + // If any boosted P-state is still enabled, set BoostSrc = 1. + for (Pbx = 0; Pbx < CpbControl.NumBoostStates; Pbx++) { + LibAmdMsrRead (PS_REG_BASE + Pbx, (UINT64 *)&PstateMsrData, StdHeader); + if (PstateMsrData.PsEnable == 1) { + CpbControl.BoostSrc = 1; + LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader); + break; + } + } + } + } + return AGESA_SUCCESS; +} + +CONST CPB_FAMILY_SERVICES ROMDATA F15TnCpbSupport = +{ + 0, + F15TnIsCpbSupported, + F15TnInitializeCpb +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnEquivalenceTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnEquivalenceTable.c new file mode 100644 index 0000000..407455b --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnEquivalenceTable.c @@ -0,0 +1,155 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity Equivalence Table related data + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +#include "amdlib.h" +#include "cpuRegisters.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNEQUIVALENCETABLE_FILECODE + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +GetF15TnMicrocodeEquivalenceTable ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **TnEquivalenceTablePtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +STATIC CONST UINT16 ROMDATA CpuF15TnMicrocodeEquivalenceTable[] = +{ + 0x6101, 0x6101, + 0x6100, 0x6100 +}; + +// Unencrypted equivalent +STATIC CONST UINT16 ROMDATA CpuF15TnUnEncryptedMicrocodeEquivalenceTable[] = +{ + 0x6101, 0x6901, + 0x6100, 0x6900 +}; + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the appropriate microcode patch equivalent ID table. + * + * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[out] TnEquivalenceTablePtr Points to the first entry in the table. + * @param[out] NumberOfElements Number of valid entries in the table. + * @param[in] StdHeader Header for library and services. + * + */ +VOID +GetF15TnMicrocodeEquivalenceTable ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **TnEquivalenceTablePtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 MsrDeCfg; + + LibAmdMsrRead (MSR_DE_CFG, &MsrDeCfg, StdHeader); + if ((MsrDeCfg & 0x80000) == 0) { + *NumberOfElements = ((sizeof (CpuF15TnUnEncryptedMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2); + *TnEquivalenceTablePtr = CpuF15TnUnEncryptedMicrocodeEquivalenceTable; + } else { + *NumberOfElements = ((sizeof (CpuF15TnMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2); + *TnEquivalenceTablePtr = CpuF15TnMicrocodeEquivalenceTable; + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c new file mode 100644 index 0000000..8a41eb8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c @@ -0,0 +1,315 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize the Family 15h Trinity specific way of running early initialization. + * + * Returns the table of initialization steps to perform at + * AmdInitEarly. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x15/TN + * @e $Revision: 64491 $ @e $Date: 2012-01-23 12:37:30 -0600 (Mon, 23 Jan 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +#include "GeneralServices.h" +#include "heapManager.h" +#include "Fch.h" +#include "Gnb.h" +#include "GnbLib.h" +#include "cpuEarlyInit.h" +#include "cpuF15TnPowerMgmt.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) +#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNINITEARLYTABLE_FILECODE + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +F15TnLoadMicrocodePatchAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GetF15TnEarlyInitOnCoreTable ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +ApplyWorkaroundForFchErratum39 ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +F15TnNbPstateForceBeforeApLaunchAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAtEarly; +extern F_PERFORM_EARLY_INIT_ON_CORE F15SetBrandIdRegistersAtEarly; +extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly; + +CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F15TnEarlyInitOnCoreTable[] = +{ + {SetRegistersFromTablesAtEarly, PERFORM_EARLY_ANY_CONDITION}, + {F15SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION}, + {LocalApicInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION}, + {F15TnLoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION}, + {F15TnNbPstateForceBeforeApLaunchAtEarly, PERFORM_EARLY_WARM_RESET}, + {NULL, 0} +}; + +/*------------------------------------------------------------------------------------*/ +/** + * Initializer routine that may be invoked at AmdCpuEarly to return the steps that a + * processor that uses the standard initialization steps should take. + * + * @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}. + * + * @param[in] FamilyServices The current Family Specific Services. + * @param[out] Table Table of appropriate init steps for the executing core. + * @param[in] EarlyParams Service Interface structure to initialize. + * @param[in] StdHeader Opaque handle to standard config header. + * + */ +VOID +GetF15TnEarlyInitOnCoreTable ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *Table = F15TnEarlyInitOnCoreTable; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Update microcode patch in current processor for Family15h TN. + * + * This function acts as a wrapper for calling the LoadMicrocodePatch + * routine at AmdInitEarly. + * + * @param[in] FamilyServices The current Family Specific Services. + * @param[in] EarlyParams Service parameters. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +F15TnLoadMicrocodePatchAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + BOOLEAN IsPatchLoaded; + + AGESA_TESTPOINT (TpProcCpuLoadUcode, StdHeader); + + if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) { + IsPatchLoaded = LoadMicrocodePatch (StdHeader); + } + + // After microcode patch has been loaded, apply the workaround for FCH erratum 39 + ApplyWorkaroundForFchErratum39 (StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Apply the workaround for FCH H2/H3 erratum #39. + * + * This function detects the FCH version and applies the appropriate workaround, if + * required. + * + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +ApplyWorkaroundForFchErratum39 ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 MiscReg51; + UINT8 RevisionId; + UINT16 AcpiPmTmrBlk; + UINT32 VendorIdDeviceId; + UINT64 MsrValue; + PCI_ADDR PciAddress; + AGESA_STATUS IgnoredSts; + CPU_LOGICAL_ID LogicalId; + + // Read Vendor ID / Device ID + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0, 0); + LibAmdPciRead (AccessWidth32, PciAddress, &VendorIdDeviceId, StdHeader); + + // For Hudson based system, perform workaround + if (VendorIdDeviceId == 0x780B1022) { + PciAddress.Address.Register = 0x8; + LibAmdPciRead (AccessWidth8, PciAddress, &RevisionId, StdHeader); + if ((RevisionId == 0x14) && IsBsp (StdHeader, &IgnoredSts)) { + // Enable hardware workaround by setting Misc_reg x51[0] + LibAmdMemRead (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + MISC_BASE + 0x51), &MiscReg51, StdHeader); + MiscReg51 |= BIT0; + LibAmdMemWrite (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + MISC_BASE + 0x51), &MiscReg51, StdHeader); + } else if (RevisionId == 0x13) { + GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); + if ((LogicalId.Revision & AMD_F15_TN_GT_A0) != 0) { + // For revs A1+, set up the C0010055 MSR + GnbLibIndirectIoBlockRead (0xCD6, 0xCD7, AccessWidth8, 0x64, 2, &AcpiPmTmrBlk, StdHeader); + LibAmdMsrRead (0xC0010055, &MsrValue, StdHeader); + MsrValue |= BIT30; + MsrValue |= AcpiPmTmrBlk; + LibAmdMsrWrite (0xC0010055, &MsrValue, StdHeader); + } + } + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Prevent NB P-state transitions prior to AP launch on Family 15h TN. + * + * This function determines the current NB P-state and forces the NB to remain + * in that P-state. + * + * @param[in] FamilyServices The current Family Specific Services. + * @param[in] EarlyParams Service parameters. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +F15TnNbPstateForceBeforeApLaunchAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 MsrValue; + UINT64 PerfCtrlSave; + UINT64 PerfStsSave; + PCI_ADDR PciAddress; + AGESA_STATUS IgnoredSts; + ALLOCATE_HEAP_PARAMS Alloc; + NB_PSTATE_CTRL_REGISTER NbPsCtrl; + + if (IsBsp (StdHeader, &IgnoredSts) && FamilyServices->IsNbPstateEnabled (FamilyServices, &EarlyParams->PlatformConfig, StdHeader)) { + LibAmdMsrRead (MSR_NB_PERF_CTL3, &PerfCtrlSave, StdHeader); + MsrValue = 0x00000006004004E9; + LibAmdMsrRead (MSR_NB_PERF_CTR3, &PerfStsSave, StdHeader); + LibAmdMsrWrite (MSR_NB_PERF_CTL3, &MsrValue, StdHeader); + MsrValue = 0; + LibAmdMsrWrite (MSR_NB_PERF_CTR3, &MsrValue, StdHeader); + PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); + Alloc.RequestedBufferSize = sizeof (NB_PSTATE_CTRL_REGISTER); + Alloc.BufferHandle = AMD_CPU_NB_PSTATE_FIXUP_HANDLE; + Alloc.Persist = 0; + if (HeapAllocateBuffer (&Alloc, StdHeader) == AGESA_SUCCESS) { + *((NB_PSTATE_CTRL_REGISTER *) Alloc.BufferPtr) = NbPsCtrl; + } else { + ASSERT (FALSE); + } + LibAmdMsrRead (MSR_NB_PERF_CTR3, &MsrValue, StdHeader); + if (MsrValue == 0) { + NbPsCtrl.SwNbPstateLoDis = 1; + } else { + NbPsCtrl.SwNbPstateLoDis = 0; + NbPsCtrl.NbPstateDisOnP0 = 0; + NbPsCtrl.NbPstateThreshold = 0; + } + LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); + LibAmdMsrWrite (MSR_NB_PERF_CTL3, &PerfCtrlSave, StdHeader); + LibAmdMsrWrite (MSR_NB_PERF_CTR3, &PerfStsSave, StdHeader); + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnIoCstate.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnIoCstate.c new file mode 100644 index 0000000..acbf23e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnIoCstate.c @@ -0,0 +1,402 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity IO C-state feature support functions. + * + * Provides the functions necessary to initialize the IO C-state feature. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuFeatures.h" +#include "cpuIoCstate.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "cpuLateInit.h" +#include "cpuRegisters.h" +#include "cpuServices.h" +#include "cpuApicUtilities.h" +#include "cpuFamilyTranslation.h" +#include "CommonReturns.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) +#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNIOCSTATE_FILECODE + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +F15TnInitializeIoCstateOnCore ( + IN VOID *CstateBaseMsr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +F15TnIsCsdObjGenerated ( + IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable; + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Enable IO Cstate on a family 15h Trinity CPU. + * Implement BIOS Requirements for Initialization of C-states + * + * @param[in] IoCstateServices Pointer to this CPU's IO Cstate family services. + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @return AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +STATIC +F15TnInitializeIoCstate ( + IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 LocalMsrRegister; + AP_TASK TaskPtr; + PCI_ADDR PciAddress; + CSTATE_POLICY_CTRL1_REGISTER CstatePolicyCtrl1; + + if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) { + // Initialize F4x128 + // bit[1] CoreCstatePolicy = 0 + // bit[4:2] HaltCstateIndex = 0 + // bit[31] CstateMsgDis = 1 + PciAddress.AddressValue = CSTATE_POLICY_CTRL1_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader); + CstatePolicyCtrl1.CoreCstatePolicy = 0; + CstatePolicyCtrl1.HaltCstateIndex = 0; + CstatePolicyCtrl1.CstateMsgDis = 1; + LibAmdPciWrite (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader); + + // Initialize MSRC001_0073[CstateAddr] on each core to a region of + // the IO address map with 8 consecutive available addresses. + LocalMsrRegister = 0; + + IDS_HDT_CONSOLE (CPU_TRACE, " Init IO C-state Base at 0x%x\n", PlatformConfig->CStateIoBaseAddress); + ((CSTATE_ADDRESS_MSR *) &LocalMsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress; + + TaskPtr.FuncAddress.PfApTaskI = F15TnInitializeIoCstateOnCore; + TaskPtr.DataTransfer.DataSizeInDwords = 2; + TaskPtr.DataTransfer.DataPtr = &LocalMsrRegister; + TaskPtr.DataTransfer.DataTransferFlags = 0; + TaskPtr.ExeFlags = WAIT_FOR_CORE; + ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL); + } + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Enable CState on a family 15h Trinity core. + * + * @param[in] CstateBaseMsr MSR value to write to C001_0073 as determined by core 0. + * @param[in] StdHeader Config Handle for library, services. + * + */ +VOID +STATIC +F15TnInitializeIoCstateOnCore ( + IN VOID *CstateBaseMsr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + // Initialize MSRC001_0073[CstateAddr] on each core + LibAmdMsrWrite (MSR_CSTATE_ADDRESS, (UINT64 *) CstateBaseMsr, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the size of CST object + * + * @param[in] IoCstateServices IO Cstate services. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data + * @param[in] StdHeader Config Handle for library, services. + * + * @retval CstObjSize Size of CST Object + * + */ +UINT32 +STATIC +F15TnGetAcpiCstObj ( + IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + BOOLEAN GenerateCsdObj; + UINT32 CStateAcpiObjSize; + IO_CSTATE_FAMILY_SERVICES *FamilyServices; + ACPI_CST_GET_INPUT CstGetInput; + + CstGetInput.IoCstateServices = IoCstateServices; + CstGetInput.PlatformConfig = PlatformConfig; + CstGetInput.CStateAcpiObjSizePtr = &CStateAcpiObjSize; + + IDS_SKIP_HOOK (IDS_CST_SIZE, &CstGetInput, StdHeader) { + CStateAcpiObjSize = CST_HEADER_SIZE + CST_BODY_SIZE; + + // If CSD Object is generated, add the size of CSD Object to the total size of + // CState ACPI Object size + GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); + ASSERT (FamilyServices != NULL); + GenerateCsdObj = FamilyServices->IsCsdObjGenerated (FamilyServices, StdHeader); + + if (GenerateCsdObj) { + CStateAcpiObjSize += CSD_HEADER_SIZE + CSD_BODY_SIZE; + } + } + return CStateAcpiObjSize; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Routine to generate the C-State ACPI objects + * + * @param[in] IoCstateServices IO Cstate services. + * @param[in] LocalApicId Local Apic Id for each core. + * @param[in, out] **PstateAcpiBufferPtr Pointer to the Acpi Buffer Pointer. + * @param[in] StdHeader Config Handle for library, services. + * + */ +VOID +STATIC +F15TnCreateAcpiCstObj ( + IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, + IN UINT8 LocalApicId, + IN OUT VOID **PstateAcpiBufferPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 MsrData; + BOOLEAN GenerateCsdObj; + CST_HEADER_STRUCT *CstHeaderPtr; + CST_BODY_STRUCT *CstBodyPtr; + CSD_HEADER_STRUCT *CsdHeaderPtr; + CSD_BODY_STRUCT *CsdBodyPtr; + IO_CSTATE_FAMILY_SERVICES *FamilyServices; + ACPI_CST_CREATE_INPUT CstInput; + + CstInput.IoCstateServices = IoCstateServices; + CstInput.LocalApicId = LocalApicId; + CstInput.PstateAcpiBufferPtr = PstateAcpiBufferPtr; + + IDS_SKIP_HOOK (IDS_CST_CREATE, &CstInput, StdHeader) { + // Read from MSR C0010073 to obtain CstateAddr + LibAmdMsrRead (MSR_CSTATE_ADDRESS, &MsrData, StdHeader); + + // Typecast the pointer + CstHeaderPtr = (CST_HEADER_STRUCT *) *PstateAcpiBufferPtr; + + // Set CST Header + CstHeaderPtr->NameOpcode = NAME_OPCODE; + CstHeaderPtr->CstName_a__ = CST_NAME__; + CstHeaderPtr->CstName_a_C = CST_NAME_C; + CstHeaderPtr->CstName_a_S = CST_NAME_S; + CstHeaderPtr->CstName_a_T = CST_NAME_T; + + // Typecast the pointer + CstHeaderPtr++; + CstBodyPtr = (CST_BODY_STRUCT *) CstHeaderPtr; + + // Set CST Body + CstBodyPtr->PkgOpcode = PACKAGE_OPCODE; + CstBodyPtr->PkgLength = CST_LENGTH; + CstBodyPtr->PkgElements = CST_NUM_OF_ELEMENTS; + CstBodyPtr->BytePrefix = BYTE_PREFIX_OPCODE; + CstBodyPtr->Count = CST_COUNT; + CstBodyPtr->PkgOpcode2 = PACKAGE_OPCODE; + CstBodyPtr->PkgLength2 = CST_PKG_LENGTH; + CstBodyPtr->PkgElements2 = CST_PKG_ELEMENTS; + CstBodyPtr->BufferOpcode = BUFFER_OPCODE; + CstBodyPtr->BufferLength = CST_SUBPKG_LENGTH; + CstBodyPtr->BufferElements = CST_SUBPKG_ELEMENTS; + CstBodyPtr->BufferOpcode2 = BUFFER_OPCODE; + CstBodyPtr->GdrOpcode = GENERIC_REG_DESCRIPTION; + CstBodyPtr->GdrLength = CST_GDR_LENGTH; + CstBodyPtr->AddrSpaceId = GDR_ASI_SYSTEM_IO; + CstBodyPtr->RegBitWidth = 0x08; + CstBodyPtr->RegBitOffset = 0x00; + CstBodyPtr->AddressSize = GDR_ASZ_BYTE_ACCESS; + CstBodyPtr->RegisterAddr = ((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr + 1; + CstBodyPtr->EndTag = 0x0079; + CstBodyPtr->BytePrefix2 = BYTE_PREFIX_OPCODE; + CstBodyPtr->Type = CST_C2_TYPE; + CstBodyPtr->WordPrefix = WORD_PREFIX_OPCODE; + CstBodyPtr->Latency = 100; + CstBodyPtr->DWordPrefix = DWORD_PREFIX_OPCODE; + CstBodyPtr->Power = 0; + + CstBodyPtr++; + //Update the pointer + *PstateAcpiBufferPtr = CstBodyPtr; + + + // Check whether CSD object should be generated + GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); + ASSERT (FamilyServices != NULL); + GenerateCsdObj = FamilyServices->IsCsdObjGenerated (FamilyServices, StdHeader); + + if (GenerateCsdObj) { + CsdHeaderPtr = (CSD_HEADER_STRUCT *) *PstateAcpiBufferPtr; + + // Set CSD Header + CsdHeaderPtr->NameOpcode = NAME_OPCODE; + CsdHeaderPtr->CsdName_a__ = CST_NAME__; + CsdHeaderPtr->CsdName_a_C = CST_NAME_C; + CsdHeaderPtr->CsdName_a_S = CST_NAME_S; + CsdHeaderPtr->CsdName_a_D = CSD_NAME_D; + + CsdHeaderPtr++; + CsdBodyPtr = (CSD_BODY_STRUCT *) CsdHeaderPtr; + + // Set CSD Body + CsdBodyPtr->PkgOpcode = PACKAGE_OPCODE; + CsdBodyPtr->PkgLength = CSD_BODY_SIZE - 1; + CsdBodyPtr->PkgElements = 1; + CsdBodyPtr->PkgOpcode2 = PACKAGE_OPCODE; + CsdBodyPtr->PkgLength2 = CSD_BODY_SIZE - 4; // CSD_BODY_SIZE - Package() - Package Opcode + CsdBodyPtr->PkgElements2 = 6; + CsdBodyPtr->BytePrefix = BYTE_PREFIX_OPCODE; + CsdBodyPtr->NumEntries = 6; + CsdBodyPtr->BytePrefix2 = BYTE_PREFIX_OPCODE; + CsdBodyPtr->Revision = 0; + CsdBodyPtr->DWordPrefix = DWORD_PREFIX_OPCODE; + CsdBodyPtr->Domain = (LocalApicId & 0xFE) >> 1; + CsdBodyPtr->DWordPrefix2 = DWORD_PREFIX_OPCODE; + CsdBodyPtr->CoordType = CSD_COORD_TYPE_HW_ALL; + CsdBodyPtr->DWordPrefix3 = DWORD_PREFIX_OPCODE; + CsdBodyPtr->NumProcessors = 0x2; + CsdBodyPtr->DWordPrefix4 = DWORD_PREFIX_OPCODE; + CsdBodyPtr->Index = 0x0; + + CsdBodyPtr++; + + // Update the pointer + *PstateAcpiBufferPtr = CsdBodyPtr; + } + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Routine to check whether CSD object should be created. + * + * @param[in] IoCstateServices IO Cstate services. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE CSD Object should be created. + * @retval FALSE CSD Object should not be created. + * + */ +BOOLEAN +F15TnIsCsdObjGenerated ( + IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + // CSD Object should only be created when there are two cores per compute unit + if (GetComputeUnitMapping (StdHeader) == EvenCoresMapping) { + return TRUE; + } + return FALSE; +} + +CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F15TnIoCstateSupport = +{ + 0, + (PF_IO_CSTATE_IS_SUPPORTED) CommonReturnTrue, + F15TnInitializeIoCstate, + F15TnGetAcpiCstObj, + F15TnCreateAcpiCstObj, + F15TnIsCsdObjGenerated +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnLogicalIdTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnLogicalIdTables.c new file mode 100644 index 0000000..931f27f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnLogicalIdTables.c @@ -0,0 +1,134 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity Logical ID Table + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNLOGICALIDTABLES_FILECODE + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +GetF15TnLogicalIdAndRev ( + OUT CONST CPU_LOGICAL_ID_XLAT **TnIdPtr, + OUT UINT8 *NumberOfElements, + OUT UINT64 *LogicalFamily, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF15TnLogicalIdAndRevArray[] = +{ + { + 0x6101, + AMD_F15_TN_A1 + }, + { + 0x6100, + 0x0000000000000100ull + } +}; + +VOID +GetF15TnLogicalIdAndRev ( + OUT CONST CPU_LOGICAL_ID_XLAT **TnIdPtr, + OUT UINT8 *NumberOfElements, + OUT UINT64 *LogicalFamily, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + *NumberOfElements = (sizeof (CpuF15TnLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)); + *TnIdPtr = CpuF15TnLogicalIdAndRevArray; + *LogicalFamily = AMD_FAMILY_15_TN; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c new file mode 100644 index 0000000..dbd9ee2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c @@ -0,0 +1,2701 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD F15Tn Microcode patch. + * + * F15Tn Microcode Patch rev 0600110F for 6101 or equivalent. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e $Revision: 64060 $ @e $Date: 2012-01-15 21:36:26 -0600 (Sun, 15 Jan 2012) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuEarlyInit.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +UCODE_VS_FLAG (0600110F_Enc) + +// Encrypt Patch code 0600110F for 6101 and equivalent + +CONST UINT8 ROMDATA CpuF15TnMicrocodePatch0600110F_Enc [IDS_PAD_4K] = +{ + 0x12, + 0x20, + 0x11, + 0x01, + 0x0f, + 0x11, + 0x00, + 0x06, + 0x02, + 0x80, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x01, + 0x61, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0xd4, + 0x3d, + 0x97, + 0xf0, + 0xd2, + 0x1a, + 0xcf, + 0x44, + 0x1d, + 0x45, + 0x82, + 0x13, + 0xec, + 0xcd, + 0x52, + 0x24, + 0x2d, + 0x26, + 0x73, + 0x9f, + 0x0e, + 0x38, + 0x80, + 0x5b, + 0x02, + 0x6a, + 0xd3, + 0x80, + 0x97, + 0xc0, + 0xe8, + 0x08, + 0xaf, + 0x52, + 0x2e, + 0xe4, + 0x54, + 0xa6, + 0xb3, + 0xb3, + 0x9b, + 0x21, + 0xb9, + 0xe1, + 0xa8, + 0xa4, + 0xed, + 0x9a, + 0x76, + 0xf7, + 0x62, + 0x13, + 0x3b, + 0xf8, + 0x21, + 0xc4, + 0xf3, + 0xff, + 0xb5, + 0x20, + 0xbd, + 0x8c, + 0x3a, + 0x4b, + 0x7e, + 0x44, + 0x88, + 0x9e, + 0x21, + 0xf3, + 0x32, + 0xad, + 0x96, + 0xf9, + 0x1d, + 0xe4, + 0xce, + 0xdd, + 0xb7, + 0x58, + 0x6c, + 0x3c, + 0x78, + 0x00, + 0x9f, + 0x9f, + 0x76, + 0x6e, + 0x92, + 0x80, + 0xb9, + 0x6a, + 0xcf, + 0x66, + 0x2b, + 0x7e, + 0x1d, + 0xbf, + 0x2d, + 0xca, + 0xde, + 0x58, + 0x1b, + 0xc6, + 0xb8, + 0x5e, + 0x82, + 0xc3, + 0xdf, + 0x8b, + 0xd8, + 0xdb, + 0xca, + 0x43, + 0xf2, + 0x75, + 0x40, + 0xb6, + 0xbf, + 0xdb, + 0x5f, + 0xb8, + 0xd2, + 0xdd, + 0x81, + 0xeb, + 0xa6, + 0x7f, + 0x01, + 0xbc, + 0x37, + 0x07, + 0x4e, + 0x73, + 0x13, + 0xcf, + 0x08, + 0xb9, + 0xd6, + 0xda, + 0xe6, + 0x10, + 0xd7, + 0x2c, + 0xfe, + 0x49, + 0x3e, + 0x4b, + 0xa0, + 0xfa, + 0xc1, + 0x81, + 0xe9, + 0xdb, + 0x70, + 0xfd, + 0x46, + 0xc4, + 0x44, + 0x4c, + 0x14, + 0xc2, + 0x1a, + 0x46, + 0xa5, + 0x2c, + 0xb3, + 0x04, + 0x15, + 0xda, + 0x53, + 0x74, + 0x41, + 0x61, + 0xcc, + 0xda, + 0x40, + 0x53, + 0x03, + 0x4a, + 0x51, + 0xc2, + 0x4f, + 0x81, + 0x34, + 0x89, + 0x4f, + 0x7c, + 0x7e, + 0xa0, + 0x50, + 0x7a, + 0xc8, + 0xf3, + 0xd0, + 0xfc, + 0x7f, + 0xda, + 0xa8, + 0x61, + 0x6c, + 0x46, + 0xb3, + 0xc9, + 0x05, + 0x0b, + 0x9f, + 0x5e, + 0xb1, + 0x43, + 0x9d, + 0xc0, + 0x3a, + 0xbe, + 0x6e, + 0x05, + 0x30, + 0x3d, + 0xf1, + 0xee, + 0x0e, + 0xcf, + 0x63, + 0x40, + 0xe9, + 0xd3, + 0x27, + 0x2c, + 0x0a, + 0x48, + 0xe8, + 0xae, + 0xc0, + 0x38, + 0xae, + 0x3b, + 0x41, + 0x21, + 0x5a, + 0xa2, + 0xc0, + 0x20, + 0x77, + 0x18, + 0x9b, + 0x7f, + 0xdd, + 0x95, + 0x4b, + 0x8b, + 0x83, + 0x2c, + 0xfb, + 0x49, + 0xd8, + 0x25, + 0xf2, + 0x21, + 0x6e, + 0x54, + 0xe5, + 0x01, + 0x22, + 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0xb0, + 0xd9, + 0x68, + 0x27, + 0x8c, + 0x93, + 0x47, + 0x3e, + 0x4f, + 0xc0, + 0xa8, + 0x86, + 0x68, + 0x4b, + 0x1a, + 0xf5, + 0x93, + 0xdd, + 0x16, + 0xed, + 0x8e, + 0x27, + 0x66, + 0x4d, + 0x59, + 0xf0, + 0x27, + 0x1b, + 0x37, + 0xa0, + 0x25, + 0x9a, + 0x62, + 0xb4, + 0x6f, + 0xbd, + 0x83, + 0x28, + 0x0b, + 0x26, + 0xa9, + 0x07, + 0xac, + 0xb5, + 0x91, + 0x93, + 0x91, +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c new file mode 100644 index 0000000..c2ea312 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c @@ -0,0 +1,138 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity microcode patches + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "cpuEarlyInit.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNMICROCODEPATCHTABLES_FILECODE + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +extern CONST MICROCODE_PATCHES_4K ROMDATA *CpuF15TnMicroCodePatchArray[]; +extern CONST UINT8 ROMDATA CpuF15TnNumberOfMicrocodePatches; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +GetF15TnMicroCodePatchesStruct ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **TnUcodePtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns a table containing the appropriate microcode patches. + * + * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[out] TnUcodePtr Points to the first entry in the table. + * @param[out] NumberOfElements Number of valid entries in the table. + * @param[in] StdHeader Header for library and services. + * + */ +VOID +GetF15TnMicroCodePatchesStruct ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **TnUcodePtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *NumberOfElements = CpuF15TnNumberOfMicrocodePatches; + *TnUcodePtr = &CpuF15TnMicroCodePatchArray[0]; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c new file mode 100644 index 0000000..1be6154 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c @@ -0,0 +1,324 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity MSR tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e $Revision: 63495 $ @e $Date: 2011-12-23 01:30:59 -0600 (Fri, 23 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuRegisters.h" +#include "cpuF15TnPowerMgmt.h" +#include "F15TnPackageType.h" +#include "Table.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNMSRTABLES_FILECODE + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +SetTopologyExtensions ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +SetForceSmcCheckFlwStDis ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F15TnMsrRegisters[] = +{ +// M S R T a b l e s +// ---------------------- + +// MSR_NB_CFG (0xC001001F) +// bit[23] = 1, erratum #663 + { + MsrRegister, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MSR_NB_CFG, // MSR Address + 0x0000000000800000, // OR Mask + 0x0000000000800000, // NAND Mask + }} + }, + +// MSR_LS_CFG2 (0xC001102D) +// bit[23] DisScbThreshold = 1 + { + MsrRegister, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MSR_LS_CFG2, // MSR Address + 0x0000000000800000, // OR Mask + 0x0000000000800000, // NAND Mask + }} + }, +// MSR_HWCR (0xC0010015) +// bit[27] EffFreqReadOnlyLock = 1 +// bit[12] HltXSpCycEn = 1 + { + MsrRegister, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MSR_HWCR, // MSR Address + 0x0000000008001000, // OR Mask + 0x0000000008001000, // NAND Mask + }} + }, +// MSR_OSVW_ID_Length (0xC0010140) +// bit[15:0] = 4 + { + MsrRegister, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MSR_OSVW_ID_Length, // MSR Address + 0x0000000000000004, // OR Mask + 0x000000000000FFFF, // NAND Mask + }} + }, +// MSR 0xC0011000 +// bit[17] = 1, Disable Erratum #671 +// bit[16] = 1, Erratum #608 for all TN revisions + { + MsrRegister, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + 0xC0011000, // MSR Address + 0x0000000000030000, // OR Mask + 0x0000000000030000, // NAND Mask + }} + }, +// MSR_CPUID_EXT_FEATS (0xC0011005) +// bit[51] NodeId = 1 + { + MsrRegister, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MSR_CPUID_EXT_FEATS, // MSR Address + 0x0008000000000000, // OR Mask + 0x0008000000000000, // NAND Mask + }} + }, +}; + +CONST REGISTER_TABLE ROMDATA F15TnMsrRegisterTable = { + AllCores, + (sizeof (F15TnMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + (TABLE_ENTRY_FIELDS *) &F15TnMsrRegisters, +}; + +// MSR with Special Programming Requirements Table + +STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F15TnMsrWorkarounds[] = +{ +// MSR_C001_1005 + { + FamSpecificWorkaround, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + SetTopologyExtensions, // function call + 0x00000000, // data + }} + }, +// MSR_C001_102D + { + FamSpecificWorkaround, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + SetForceSmcCheckFlwStDis, // function call + 0x00000000, // data + }} + }, +}; + +CONST REGISTER_TABLE ROMDATA F15TnMsrWorkaroundTable = { + AllCores, + (sizeof (F15TnMsrWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)), + (TABLE_ENTRY_FIELDS *) F15TnMsrWorkarounds, +}; + +/*---------------------------------------------------------------------------------------*/ +/** + * MSR special programming requirements for MSR_C001_1005 + * + * AGESA should program MSR_C001_1005[54, TopologyExtensions] as follows: + * IF (CPUID Fn8000_0001_EBX[PkgType]==0010b) THEN 0 ELSE 1 ENDIF. + * + * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +STATIC +SetTopologyExtensions ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 PkgType; + UINT64 CpuMsrData; + + PkgType = LibAmdGetPackageType (StdHeader); + LibAmdMsrRead (MSR_CPUID_EXT_FEATS, &CpuMsrData, StdHeader); + CpuMsrData &= ~(BIT54); + if (PkgType == PACKAGE_TYPE_FM2) { + CpuMsrData |= BIT54; + } + LibAmdMsrWrite (MSR_CPUID_EXT_FEATS, &CpuMsrData, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * MSR special programming requirements for MSR_C001_102D + * + * AGESA should program MSR_C001_102D[14] with the fused value from F3x1FC[23] + * + * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +STATIC +SetForceSmcCheckFlwStDis ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + PRODUCT_INFO_REGISTER ProductInfo; + LS_CFG2_MSR LsCfg2; + + PciAddress.AddressValue = PRCT_INFO_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, (VOID *) &ProductInfo, StdHeader); + + LibAmdMsrRead (MSR_LS_CFG2, (UINT64 *) &LsCfg2, StdHeader); + + LsCfg2.ForceSmcCheckFlwStDis = ProductInfo.ForceSmcCheckFlwStDis; + LibAmdMsrWrite (MSR_LS_CFG2, (UINT64 *) &LsCfg2, StdHeader); + + return; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPackageType.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPackageType.h new file mode 100644 index 0000000..bb8a04a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPackageType.h @@ -0,0 +1,102 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity Package Type Definitions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _F15_TN_PACKAGE_TYPE_H_ +#define _F15_TN_PACKAGE_TYPE_H_ + + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ + +// Below equates are defined to cooperate with LibAmdGetPackageType. +#define PACKAGE_TYPE_FP2 (1 << 0) +#define PACKAGE_TYPE_FS1r2 (1 << 1) +#define PACKAGE_TYPE_FM2 (1 << 2) + + +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ + +#endif // _F15_TN_PACKAGE_TYPE_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPciTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPciTables.c new file mode 100644 index 0000000..c04ce1e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPciTables.c @@ -0,0 +1,849 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity PCI tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e $Revision: 64462 $ @e $Date: 2012-01-21 10:59:15 -0600 (Sat, 21 Jan 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuRegisters.h" +#include "cpuF15TnPowerMgmt.h" +#include "Table.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNPCITABLES_FILECODE + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +STATIC +SetEnCstateBoostBlockCC6Exit ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +Erratum687Workaround ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +// P C I T a b l e s +// ---------------------- + +STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F15TnPciRegisters[] = +{ +// F0x68 - Link Transaction Control +// bits[22:21] DsNpReqLmt = 01b +// bit [19] ApicExtSpur = 1 +// bit [18] ApicExtId = 1 +// bit [17] ApicExtBrdCst = 1 +// bit [15] LimitCldtCfg = 1 +// bit [10] DisFillP = 0 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address + 0x002E8000, // regData + 0x006E8400, // regMask + }} + }, +// F0x6C - Link Initialization Control +// bit[0] RouteTblDis = 0 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x6C), // Address + 0x00000000, // regData + 0x00000001, // regMask + }} + }, +// F0x84 - Link Control +// bit [12] IsocEn = 1 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x84), // Address + 0x00001000, // regData + 0x00001000, // regMask + }} + }, +// F0x90 - Upstream Base Channel Buffer Count +// bits[27:25] FreeData = 0 +// bits[24:20] FreeCmd = 0 +// bits[19:18] RspData = 1 +// bits[17:16] NpReqData = 1 +// bits[15:12] ProbeCmd = 0 +// bits[11:8] RspCmd = 2 +// bits[7:5] PReq = 5 +// bits[4:0] NpReqCmd = 8 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x90), // Address + 0x000502A8, // regData + 0x0FFFFFFF, // regMask + }} + }, +// F0x94 - Link Isochronous Channel Buffer Count +// bits[28:27] IsocRspData = 0 +// bits[26:25] IsocNpReqData = 1 +// bits[24:22] IsocRspCmd = 0 +// bits[21:19] IsocpReq = 0 +// bits[18:16] IsocNpReqCmd = 1 +// bits[15:8] SecBusNum = 0 (F1XE0 [BaseBusNum]) + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x94), // Address + 0x02010000, // regData + 0x1FFFFF00, // regMask + }} + }, +// F1xE0 - Configuration Map +// bits[31:24] BusNumLimit = F8 +// bits[23:16] BaseBusNum = 0 +// bit [1] WE = 1 +// bit [0] RE = 1 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_1, 0xE0),// Address + 0xF8000003, // regData + 0xFFFF0003, // regMask + }} + }, +// F3x44 - MCA NB Configuration +// +// bit[30] SyncFloodOnDramAdrParErr = 1 +// bit[27] NbMcaToMstCpuEn = 1 +// bit[21] SyncFloodOnAnyUcErr = 1 +// bit[20] SyncFloodOnWDT = 1 + + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x44), // Address + 0x48300000, // regData + 0x48300000, // regMask + }} + }, +// F3x70 - SRI_to_XBAR Command Buffer Count +// bits[30:28] IsocRspCBC = 1 +// bits[26:24] IsocPreqCBC = 0 +// bits[22:20] IsocReqCBC = 1 +// bits[18:16] UpRspCBC = 7 +// bits[14:12] DnPreqCBC = 1 +// bits[10:8] UpPreqCBC = 1 +// bits[7:6] DnRspCBC = 1 +// bits[5:4] DnReqCBC = 1 +// bits[2:0] UpReqCBC = 7 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70), // Address + 0x10171157, // regData + 0x777777F7, // regMask + }} + }, +// F3x74 - XBAR_to_SRI Command Buffer Count +// bits[31:28] DRReqCBC = 0 +// bits[26:24] IsocPreqCBC = 1 +// bits[23:20] IsocReqCBC = 1 +// bits[19:16] ProbeCBC = 8 +// bits[14:12] DnPreqCBC = 0 +// bits[10:8] UpPreqCBC = 1 +// bits[6:4] DnReqCBC = 0 +// bits[2:0] UpReqCBC = 1 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address + 0x01180101, // regData + 0xF7FF7777, // regMask + }} + }, +// F3x7C - Free List Buffer Count +// bits[26:23] ExtSrqFreeList = 8 +// bits[22:20] Sri2XbarFreeRspDBC = 0 +// bits[19:16] Sri2XbarFreeXreqDBC = 5 +// bits[15:12] Sri2XbarFreeRspCBC = 0 +// bits[11:8] Sri2XbarFreeXreqCBC = 0xE +// bits[4:0] Xbar2SriFreeListCBC = 18h + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address + 0x04050E18, // regData + 0x07FFFF1F, // regMask + }} + }, +// F3x84 - ACPI Power State Control High +// ACPI State S3 +// bit[1] NbLowPwrEnSmafAct4 = 1 +// bit[7:5] ClkDivisorSmafAct4 = 7 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84), // Address + 0x000000E2, // regData + 0x000000E2, // regMask + }} + }, +// F3xA0 - Power Control Miscellaneous +// bit[14] Svi2HighFreqSel = 1, if PERFORMANCE_VRM_HIGH_SPEED_ENABLE == TRUE + { + ProfileFixup, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + PERFORMANCE_VRM_HIGH_SPEED_ENABLE, // PerformanceFeatures + MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address + 0x00004000, // regData + 0x00004000, // regMask + }} + }, +// F3xD4 - Clock Power Timing Control 0 +// bit [31] NbClkDivApplyAll = 1 +// bits[30:28] NbClkDiv = 4 +// bits[27:24] PowerStepUp = 8 +// bits[23:20] PowerStepDown = 8 +// bit [14] CacheFlushImmOnAllHalt = 0 +// bit [12] ClkRampHystCtl = 0 +// bits[11:8] ClkRampHystSel = 0xF + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4), // Address + 0xC8800F00, // regData + 0xFFF05F00, // regMask + }} + }, +// F3xD8 - Clock Power Timing Control 1 +// bits[6:4] VSRampSlamTime = 100b + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD8), // Address + 0x00000040, // regData + 0x00000070, // regMask + }} + }, +// F3xDC - Clock Power Timing Control 2 +// bits[14:12] NbsynPtrAdj = 5 + { + PciRegister, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address + 0x00005000, // regData + 0x00007000, // regMask + }} + }, +// F3x140 - SRI_to_XCS Token Count +// bits[23:20] FreeTok = 0xA +// bits[17:16] IsocRspTok = 1 +// bits[15:14] IsocPreqTok = 0 +// bits[13:12] IsocReqTok = 1 +// bits[11:10] DnRspTok = 1 +// bits[9:8] UpRspTok = 1 +// bits[7:6] DnPreqTok = 1 +// bits[5:4] UpPreqTok = 1 +// bits[3:2] DnReqTok = 1 +// bits[1:0] UpReqTok = 1 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platform Features + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address + 0x00A11555, // regData + 0x00F3FFFF, // regMask + }} + }, +// F3x144 - MCT_to_XCS Token Count +// bits[7:4] ProbeTok = 7 +// bits[3:0] RspTok = 7 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platform Features + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address + 0x00000077, // regData + 0x000000FF, // regMask + }} + }, +// F3x148 - Link_to_XCS Token Count +// bits[31:30] FreeTok[3:2] = FreeTok[1:0] = 0 +// bit [28] IsocRspTok1 = 0 +// bit [26] IsocPreqTok1 = 0 +// bit [24] IsocReqTok1 = 0 +// bits[23:22] ProbeTok1 = 0 +// bits[21:20] RspTok1 = 0 +// bits[19:18] PReqTok1 = 0 +// bits[17:16] ReqTok1 = 0 +// bits[15:14] FreeTok[1:0] = 0 +// bits[13:12] IsocRspTok0 = 0 +// bits[11:10] IsocPreqTok0 = 1 +// bits[9:8] IsocReqTok0 = 1 +// bits[7:6] ProbeTok0 = 0 +// bits[5:4] RspTok0 = 2 +// bits[3:2] PReqTok0 = 2 +// bits[1:0] ReqTok0 = 2 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platform Features + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address + 0x0000052A, // regData + 0xD5FFFFFF // regMask + }} + }, +// F3x17C - Extended Freelist Buffer Count +// bits[3:0] SPQPrbFreeCBC = 4 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platform Features + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x17C), // Address + 0x00000004, // regData + 0x0000000F // regMask + }} + }, +// F3x180 - NB Extended Configuration +// bit[24] McaLogErrAddrWdtErr = 1 +// bit[22] SyncFloodOnTblWalkErr = 1 +// bit[21] SyncFloodOnCpuLeakErr = 1 +// bit[20] SyncFloodOnL3LeakErr = 1 +// bit[9] SyncFloodOnUCNbAry = 1 +// bit[8] SyncFloodOnHtProt = 1 +// bit[7] SyncFloodOnTgtAbortErr = 1 +// bit[6] SyncFloodOnDatErr = 1 +// bit[5] DisPciCfgCpuMstAbortRsp = 1 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address + 0x017003E0, // regData + 0x017003E0, // regMask + }} + }, +// F3x1A0 - Core to NB Buffer Count +// bit[17:16] CpuToNbFreeBufCnt = 3 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1A0), // Address + 0x00030000, // regData + 0x00030000, // regMask + }} + }, +// F4x110 - Sample and Residency Timer +// bits[11:0] CSampleTimer = 2 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_4, 0x110), // Address + 0x00000002, // regData + 0x00000FFF, // regMask + }} + }, +// F4x124 - C-state Interrupt Control +// bits[26:23] IntMonPC6Limit = 0 +// bit [22] IntMonPC6En = 1 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_4, 0x124), // Address + 0x00400000, // regData + 0x07C00000, // regMask + }} + }, +// F4x16C - Erratum #667 +// bit [1] = 1 +// bit [4] = 1 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_4, 0x16C), // Address + 0x00000012, // regData + 0x00000012, // regMask + }} + }, +// F5xAC - Erratum #667 +// bit [3] = 1 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_5, 0xAC), // Address + 0x00000008, // regData + 0x00000008, // regMask + }} + }, +// F5x88 - Northbridge Configuration 4 +// bit[24] DisHbNpReqBusLock = 1 +// bit[2] IntStpClkHaltExitEn = 1 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_5, 0x88), // Address + 0x01000004, // regData + 0x01000004, // regMask + }} + }, +// F5xE0 - Processor TDP Running Average +// bits[3:0] RunAvgRange = 0x2 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_5, 0xE0), // Address + 0x00000002, // regData + 0x0000000F, // regMask + }} + }, +// F5x128 - Clock Power/Timing Control 3 +// bits[13:12] PwrGateTmr = 1 +// bits[11:10] PllVddOutUpTime = 3 +// bit [9] FastSlamTimeDown = 1 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_5, 0x128), // Address + 0x00001E00, // regData + 0x00003E00, // regMask + }} + }, +// F5x12C - Clock Power/Timing Control 4 +// bit [5] CorePsi1En = 1 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_5, 0x12C), // Address + 0x00000020, // regData + 0x00000020, // regMask + }} + }, +// F5x178 - Northbridge Fusion Configuration +// bit [18] CstateFusionHsDis = 1 +// bit [17] Dis2ndGnbAllowPsWait = 1 +// bit [11] AllowSelfRefrS3Dis = 1 +// bit [10] InbWakeS3Dis = 1 +// bit [2] CstateFusionDis = 1 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_5, 0x178), // Address + 0x00060C04, // regData + 0x00060C04, // regMask + }} + }, +// F0x90 - Upstream Base Channel Buffer Count +// bit [31] LockBc = 1 +// +// NOTE: The entry is intended to be programmed after other bits of D18F0x[90, 94] is programmed and before D18F0x6C[30] is programmed. + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x90), // Address + 0x80000000, // regData + 0x80000000, // regMask + }} + }, +// F0x6C - Link Initialization Control +// bit [30] RlsLnkFullTokCntImm = 1 +// bit [28] RlsIntFullTokCntImm = 1 +// +// NOTE: The entry is intended to be after D18F0x[90, 94] and D18F0x[70, 74, 78, 7C, 140, 144, 148, 17C, 1A0] are programmed. + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x6C), // Address + 0x50000000, // regData + 0x50000000, // regMask + }} + }, +// F0x6C - Link Initialization Control +// bit [27] ApplyIsocModeEnNow = 1 +// +// NOTE: The entry is intended to be after D18F0x6C[30, 28] are programmed. + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x6C), // Address + 0x08000000, // regData + 0x08000000, // regMask + }} + }, +}; + + +// PCI with Special Programming Requirements Table + +STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F15TnPciWorkarounds[] = +{ +// D18F5x88 + { + FamSpecificWorkaround, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + AMD_F15_TN_GT_A0 // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + SetEnCstateBoostBlockCC6Exit, // function call + 0x00000000, // data + }} + }, +// D18F5x88 and D18F2x408 + { + FamSpecificWorkaround, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + Erratum687Workaround, // function call + 0x00000000, // data + }} + }, +}; + + +CONST REGISTER_TABLE ROMDATA F15TnPciRegisterTable = { + PrimaryCores, + (sizeof (F15TnPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + F15TnPciRegisters, +}; + + +CONST REGISTER_TABLE ROMDATA F15TnPciWorkaroundTable = { + PrimaryCores, + (sizeof (F15TnPciWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)), + (TABLE_ENTRY_FIELDS *) F15TnPciWorkarounds, +}; + + +/*---------------------------------------------------------------------------------------*/ +/** + * Workaround for Non-A0 TN processors. + * + * AGESA should program F5x88[18] with the fused value from F3x1FC[20] for non-RevA0 parts. + * + * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +STATIC +SetEnCstateBoostBlockCC6Exit ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + PRODUCT_INFO_REGISTER ProductInfo; + NB_CFG_4_REGISTER NbCfg4; + + PciAddress.AddressValue = PRCT_INFO_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&ProductInfo, StdHeader); + + PciAddress.AddressValue = NB_CFG_REG4_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&NbCfg4, StdHeader); + + NbCfg4.EnCstateBoostBlockCC6Exit = ProductInfo.EnCstateBoostBlockCC6Exit; + LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&NbCfg4, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Workaround for Erratum #687 for TN processors. + * + * AGESA should program F5x88[14] with the fused value from F3x1FC[29] and + * program F2x408[CpuElevPrioDis] with inversed fuse value from F3x1FC[29] for all TN parts. + * + * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +STATIC +Erratum687Workaround ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + PRODUCT_INFO_REGISTER ProductInfo; + NB_CFG_4_REGISTER NbCfg4; + GMC_TO_DCT_CTL_2_REGISTER GmcToDctCtrl2; + UINT32 DctSelCnt; + DCT_CFG_SEL_REGISTER DctCfgSel; + + PciAddress.AddressValue = PRCT_INFO_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&ProductInfo, StdHeader); + + PciAddress.AddressValue = NB_CFG_REG4_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&NbCfg4, StdHeader); + NbCfg4.Bit14 = ProductInfo.EnDcqChgPriToHigh; + LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&NbCfg4, StdHeader); + + for (DctSelCnt = 0; DctSelCnt <= 1; DctSelCnt++) { + PciAddress.AddressValue = GMC_TO_DCT_CTL_2_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&GmcToDctCtrl2, StdHeader); + GmcToDctCtrl2.CpuElevPrioDis = ~ProductInfo.EnDcqChgPriToHigh; + LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&GmcToDctCtrl2, StdHeader); + + PciAddress.AddressValue = DCT_CFG_SEL_REG_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&DctCfgSel, StdHeader); + DctCfgSel.DctCfgSel = ~DctCfgSel.DctCfgSel; + LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&DctCfgSel, StdHeader); + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerMgmtSystemTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerMgmtSystemTables.c new file mode 100644 index 0000000..c9b6b6b --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerMgmtSystemTables.c @@ -0,0 +1,195 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Models 0x10 - 0x1F Power Management related initialization table + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e $Revision: 63692 $ @e $Date: 2012-01-03 22:13:28 -0600 (Tue, 03 Jan 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuApicUtilities.h" +#include "cpuFamilyTranslation.h" +#include "cpuPowerMgmtSystemTables.h" +#include "cpuF15TnCoreAfterReset.h" +#include "cpuF15TnNbAfterReset.h" +#include "F15TnPowerPlane.h" +#include "cpuF15TnPowerCheck.h" +#include "F15TnUtilities.h" +#include "IdsF15TnAllService.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNPOWERMGMTSYSTEMTABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +GetF15TnSysPmTable ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **SysPmTblPtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/* Family 15h Only Table */ +/* ---------------------- */ +CONST SYS_PM_TBL_STEP ROMDATA CpuF15TnSysPmTableArray[] = +{ + IDS_INITIAL_F15_TN_PM_STEP + + // Step 1 - Configure F3x[84:80]. Handled by PCI register table. + // Step 2 - Power Plane Initialization + // Execute both cold & warm + { + 0, // ExeFlags + F15TnPmPwrPlaneInit // Function Pointer + }, + + // Step 3 - Adjust NB VID + // Execute only after cold reset + { + PM_EXEFLAGS_COLD_ONLY, // ExeFlags + F15TnNbPstateVidAdjustAfterReset // Function Pointer + }, + + // Step 4 - Disable NB Pstate, if required + // Execute both cold & warm + { + 0, // ExeFlags + F15TnNbPstateDis // Function Pointer + }, + + // Step 5 - Core Minimum P-state Transition Sequence After Warm Reset + // Execute only after warm reset + { + PM_EXEFLAGS_WARM_ONLY, // ExeFlags + F15TnPmCoreAfterReset // Function Pointer + }, + + // Step 6 - NB P-state COF and VID Synchronization After Warm Reset + // Execute only after warm reset + { + PM_EXEFLAGS_WARM_ONLY, // ExeFlags + F15TnPmNbAfterReset // Function Pointer + }, + + // Step 7 - Power Check + // Execute both cold & warm + { + 0, // ExeFlags + F15TnPmPwrCheck // Function Pointer + }, + + IDS_F15_TN_PM_CUSTOM_STEP + +}; + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the appropriate table of steps to perform to initialize the power management + * subsystem. + * + * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[out] SysPmTblPtr Points to the first entry in the table. + * @param[out] NumberOfElements Number of valid entries in the table. + * @param[in] StdHeader Header for library and services. + * + */ +VOID +GetF15TnSysPmTable ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **SysPmTblPtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *NumberOfElements = (sizeof (CpuF15TnSysPmTableArray) / sizeof (SYS_PM_TBL_STEP)); + *SysPmTblPtr = CpuF15TnSysPmTableArray; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c new file mode 100644 index 0000000..dbf0ab9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c @@ -0,0 +1,207 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Models 0x10 - 0x1F Power Plane Initialization + * + * Performs the "BIOS Requirements for Power Plane Initialization" as described + * in the BKDG. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "cpuApicUtilities.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "Table.h" +#include "F15TnPowerPlane.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNPOWERPLANE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +// Register encodings for D18F3xD8[VSRampSlamTime] +STATIC CONST UINT32 ROMDATA F15TnVSRampSlamWaitTimes[8] = +{ + 500, // 000b: 5.00us + 375, // 001b: 3.75us + 300, // 010b: 3.00us + 240, // 011b: 2.40us + 200, // 100b: 2.00us + 150, // 101b: 1.50us + 120, // 110b: 1.20us + 100 // 111b: 1.00us +}; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Family 15h core 0 entry point for performing power plane initialization. + * + * The steps are as follows: + * 1. Configure D18F3xD8[VSRampSlamTime] based on platform + * requirements. + * 2. Configure F3xD4[PowerStepUp & PowerStepDown] + * 3. Optionally configure F3xA0[PsiVidEn & PsiVid] + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] CpuEarlyParams Service parameters + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +F15TnPmPwrPlaneInit ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + UINT32 SystemSlewRate; + UINT32 WaitTime; + UINT32 VSRampSlamTime; + UINT32 LocalPciRegister; + CLK_PWR_TIMING_CTRL1_REGISTER ClkPwrTimingCtrl1; + BOOLEAN SkipPowerPlan; + + + SkipPowerPlan = FALSE; + IDS_OPTION_CALLOUT (IDS_CALLOUT_POWER_PLAN_INIT, &SkipPowerPlan, StdHeader); + if (!SkipPowerPlan) { + // Step 1 - Configure D18F3xD8[VSRampSlamTime] based on platform requirements. + // Voltage Ramp Time = maximum time to change voltage by 15mV rounded to the next higher encoding. + SystemSlewRate = (CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate <= + CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].SlewRate) ? + CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate : + CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].SlewRate; + + ASSERT (SystemSlewRate != 0); + + // First, calculate the time it takes to change 15mV using the VRM slew rate. + WaitTime = (15000 * 100) / SystemSlewRate; + if (((15000 * 100) % SystemSlewRate) != 0) { + WaitTime++; + } + + // Next, round it to the appropriate encoded value. We will start from encoding 111b which corresponds + // to the fastest slew rate, and work our way down to 000b, which represents the slowest an acceptable + // VRM can be. + for (VSRampSlamTime = ((sizeof (F15TnVSRampSlamWaitTimes) / sizeof (F15TnVSRampSlamWaitTimes[0])) - 1); VSRampSlamTime > 0; VSRampSlamTime--) { + if (WaitTime <= F15TnVSRampSlamWaitTimes[VSRampSlamTime]) { + break; + } + } + + if (WaitTime > F15TnVSRampSlamWaitTimes[0]) { + // The VRMs on this motherboard are too slow for this CPU. + IDS_ERROR_TRAP; + } + + // Lastly, program D18F3xD8[VSRampSlamTime] with the appropriate encoded value. + PciAddress.AddressValue = CPTC1_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl1, StdHeader); + ClkPwrTimingCtrl1.VSRampSlamTime = VSRampSlamTime; + LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl1, StdHeader); + + // Configure PowerStepUp/PowerStepDown + PciAddress.AddressValue = CPTC0_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + ((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->PowerStepUp = 8; + ((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->PowerStepDown = 8; + LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + } +} + + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.h new file mode 100644 index 0000000..df17667 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.h @@ -0,0 +1,103 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Models 0x10 - 0x1F Power Plane related functions and structures + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _F15_TN_POWER_PLANE_H_ +#define _F15_TN_POWER_PLANE_H_ + + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ +VOID +F15TnPmPwrPlaneInit ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif // _F15_TN_POWER_PLANE_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnSharedMsrTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnSharedMsrTable.c new file mode 100644 index 0000000..b603800 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnSharedMsrTable.c @@ -0,0 +1,415 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity Shared MSR table with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e $Revision: 64491 $ @e $Date: 2012-01-23 12:37:30 -0600 (Mon, 23 Jan 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuRegisters.h" +#include "Table.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNSHAREDMSRTABLE_FILECODE + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +F15TnFpCfgInit ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +Update800MHzHtcPstateTo900MHz ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F15TnSharedMsrRegisters[] = +{ +// M S R T a b l e s +// ---------------------- + +// MSR_TOM2 (0xC001001D) +// bits[63:0] TOP_MEM2 = 0 + { + MsrRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MSR_TOM2, // MSR Address - Shared + 0x0000000000000000, // OR Mask + 0xFFFFFFFFFFFFFFFF, // NAND Mask + }} + }, + +// MSR_SYS_CFG (0xC0010010) +// bit[21] MtrrTom2En = 1 + { + MsrRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MSR_SYS_CFG, // MSR Address - Shared + (1 << 21), // OR Mask + (1 << 21), // NAND Mask + }} + }, + +// MSR_IC_CFG (0xC0011021) +// bit[39] DisLoopPredictor = 1 + { + MsrRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MSR_IC_CFG, // MSR Address - Shared + (1ull << 39), // OR Mask + (1ull << 39), // NAND Mask + }} + }, + +// MSR_CU_CFG (0xC0011023) + { + MsrRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MSR_CU_CFG, // MSR Address - Shared + 0, // OR Mask + 0x00000400, // NAND Mask + }} + }, + +// MSR_CU_CFG2 (0xC001102A) +// bit[50] RdMmExtCfgQwEn = 1 +// bit[10] VicResyncChkEn = 1 + + { + MsrRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MSR_CU_CFG2, // MSR Address - Shared + 0x0004000000000400, // OR Mask + 0x0004000000000400, // NAND Mask + }} + }, +// MSR_CU_CFG3 (0xC001102B) +// bit[42] PwcDisableWalkerSharing = 0 +// bit[22] PfcDoubleStride = 1 + { + MsrRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MSR_CU_CFG3, // MSR Address + 0x0000000000400000, // OR Mask + 0x0000040000400000, // NAND Mask + }} + }, +}; + + +// Compute Unit Count Dependent MSR Table + +STATIC CONST MSR_CU_TYPE_ENTRY_INITIALIZER ROMDATA F15TnSharedMsrCuRegisters[] = +{ +// M S R T a b l e s +// ---------------------- + + // MSR_CU_CFG2 (0xC001102A) + // bits[37:36] - ThrottleNbInterface[3:2] = 0 + // bits[7:6] - ThrottleNbInterface[1:0] = 0 + { + CompUnitCountsMsr, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + {(COMPUTE_UNIT_RANGE_0 (1, 1) | COUNT_RANGE_NONE)}, // 1 compute unit + { + MSR_CU_CFG2, // MSR Address - Shared + 0x0000000000000000, // OR Mask + 0x00000030000000C0, // NAND Mask + } + }} + }, + + // MSR_CU_CFG2 (0xC001102A) + // bits[37:36] - ThrottleNbInterface[3:2] = 0 + // bits[7:6] - ThrottleNbInterface[1:0] = 1 + { + CompUnitCountsMsr, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + {(COMPUTE_UNIT_RANGE_0 (2, 2) | COUNT_RANGE_NONE)}, // 2 compute units + { + MSR_CU_CFG2, // MSR Address - Shared + 0x0000000000000040, // OR Mask + 0x00000030000000C0, // NAND Mask + } + }} + } + +}; + + +// Shared MSRs with Special Programming Requirements Table + +STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F15TnSharedMsrWorkarounds[] = +{ + // MSR_FP_CFG (0xC0011028) + // bit[16] - DiDtMode = F3x1FC[0] + // bits[22:18] - DiDtCfg0 = F3x1FC[5:1] + // bits[34:27] - DiDtCfg1 = F3x1FC[13:6] + // bits[26:25] - DiDtCfg2 = F3x1FC[15:14] + // bits[44:42] - DiDtCfg4 = F3x1FC[19:17] + { + FamSpecificWorkaround, + { + AMD_FAMILY_15_TN, + AMD_F15_TN_ALL + }, + {AMD_PF_ALL}, + {{ + F15TnFpCfgInit, + 0x00000000 + }} + }, +}; + + +CONST REGISTER_TABLE ROMDATA F15TnSharedMsrRegisterTable = { + CorePairPrimary, + (sizeof (F15TnSharedMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + (TABLE_ENTRY_FIELDS *) &F15TnSharedMsrRegisters, +}; + + +CONST REGISTER_TABLE ROMDATA F15TnSharedMsrCuRegisterTable = { + CorePairPrimary, + (sizeof (F15TnSharedMsrCuRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + (TABLE_ENTRY_FIELDS *) &F15TnSharedMsrCuRegisters, +}; + +CONST REGISTER_TABLE ROMDATA F15TnSharedMsrWorkaroundTable = { + CorePairPrimary, + (sizeof (F15TnSharedMsrWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)), + (TABLE_ENTRY_FIELDS *) &F15TnSharedMsrWorkarounds, +}; + +/*---------------------------------------------------------------------------------------*/ +/** + * Update the FP_CFG MSR in current processor for Family15h TN. + * + * This function satisfies the programming requirements for the FP_CFG MSR. + * + * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +F15TnFpCfgInit ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 ProductInfo; + UINT64 FpCfg; + PCI_ADDR PciAddress; + + PciAddress.AddressValue = PRCT_INFO_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &ProductInfo, StdHeader); + + LibAmdMsrRead (MSR_FP_CFG, &FpCfg, StdHeader); + ((FP_CFG_MSR *) &FpCfg)->DiDtMode = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtMode; + ((FP_CFG_MSR *) &FpCfg)->DiDtCfg0 = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtCfg0; + ((FP_CFG_MSR *) &FpCfg)->DiDtCfg1 = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtCfg1; + ((FP_CFG_MSR *) &FpCfg)->DiDtCfg2 = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtCfg2; + ((FP_CFG_MSR *) &FpCfg)->DiDtCfg4 = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtCfg4; + ((FP_CFG_MSR *) &FpCfg)->DiDtCfg5 = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtCfg5; + LibAmdMsrWrite (MSR_FP_CFG, &FpCfg, StdHeader); +} + + +// Per-Node MSR with Special Programming Requirements Table +STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F15TnPerNodeMsrWorkarounds[] = +{ +// MSR C001_00[6B:64] + { + FamSpecificWorkaround, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + Update800MHzHtcPstateTo900MHz, // function call + 0x00000000, // data + }} + } +}; + + +CONST REGISTER_TABLE ROMDATA F15TnPerNodeMsrWorkaroundTable = { + PrimaryCores, + (sizeof (F15TnPerNodeMsrWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)), + (TABLE_ENTRY_FIELDS *) F15TnPerNodeMsrWorkarounds, +}; + + +/*---------------------------------------------------------------------------------------*/ +/** + * Workaround for CPUs with a minimum P-state = 800MHz. + * + * AGESA should change the frequency of 800MHz P-states to 900MHz. + * + * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +STATIC +Update800MHzHtcPstateTo900MHz ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + PSTATE_MSR HtcPstate; + PSTATE_MSR HtcPstateMinus1; + HTC_REGISTER HtcRegister; + + PciAddress.AddressValue = HTC_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, (VOID *) &HtcRegister, StdHeader); + + LibAmdMsrRead ((HtcRegister.HtcPstateLimit + MSR_PSTATE_0), (UINT64 *) &HtcPstate, StdHeader); + + if (HtcPstate.CpuFid == 0 && HtcPstate.CpuDid == 1) { + if (HtcRegister.HtcPstateLimit == 0) { + HtcPstateMinus1 = HtcPstate; + } else { + LibAmdMsrRead ((HtcRegister.HtcPstateLimit + MSR_PSTATE_0 - 1), (UINT64 *) &HtcPstateMinus1, StdHeader); + } + HtcPstate.CpuVid = HtcPstateMinus1.CpuVid; + HtcPstate.CpuFid = 2; + LibAmdMsrWrite ((HtcRegister.HtcPstateLimit + MSR_PSTATE_0), (UINT64 *) &HtcPstate, StdHeader); + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnUtilities.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnUtilities.c new file mode 100644 index 0000000..022d1b4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnUtilities.c @@ -0,0 +1,1031 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 models 10h - 1Fh specific utility functions. + * + * Provides numerous utility functions specific to family 15h TN. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e $Revision: 65284 $ @e $Date: 2012-02-12 23:29:39 -0600 (Sun, 12 Feb 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuFamilyTranslation.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "GeneralServices.h" +#include "OptionMultiSocket.h" +#include "F15TnUtilities.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) +#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNUTILITIES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +STATIC +F15TnNbPstateDisCore ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +F15TnGetNbFreqNumeratorInMHz ( + IN UINT32 NbFid, + OUT UINT32 *FreqNumeratorInMHz, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +F15TnGetNbFreqDivisor ( + IN UINT32 NbDid, + OUT UINT32 *FreqDivisor, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +STATIC +F15TnCalculateNbFrequencyInMHz ( + IN UINT32 NbFid, + IN UINT32 NbDid, + OUT UINT32 *FrequencyInMHz, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +F15TnCovertVidInuV ( + IN UINT32 Vid, + OUT UINT32 *VoltageInuV, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +F15TnCmnGetIddDivisor ( + IN UINT32 IddDiv, + OUT UINT32 *IddDivisor, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +F15TnCmnCalculateCurrentInmA ( + IN UINT32 IddValue, + IN UINT32 IddDiv, + OUT UINT32 *CurrentInmA, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +F15TnSetDownCoreRegister ( + IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices, + IN UINT32 *Socket, + IN UINT32 *Module, + IN UINT32 *LeveledCores, + IN CORE_LEVELING_TYPE CoreLevelMode, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; + +/*---------------------------------------------------------------------------------------*/ +/** + * Get CPU pstate current. + * + * @CpuServiceMethod{::F_CPU_GET_IDD_MAX}. + * + * This function returns the ProcIddMax. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] Pstate The P-state to check. + * @param[out] ProcIddMax P-state current in mA. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval TRUE P-state is enabled + * @retval FALSE P-state is disabled + */ +BOOLEAN +F15TnGetProcIddMax ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN UINT8 Pstate, + OUT UINT32 *ProcIddMax, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 MsrAddress; + PSTATE_MSR PstateMsr; + BOOLEAN IsPstateEnabled; + PCI_ADDR PciAddress; + NB_CAPS_2_REGISTER NbCap2; + UINT32 ProcIddMaxPerCore; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnGetProcIddMax - P%d\n", Pstate); + + IsPstateEnabled = FALSE; + + MsrAddress = (UINT32) (Pstate + PS_REG_BASE); + ASSERT (MsrAddress <= PS_MAX_REG); + + LibAmdMsrRead (MsrAddress, (UINT64 *) &PstateMsr, StdHeader); + F15TnCmnCalculateCurrentInmA ((UINT32) PstateMsr.IddValue, (UINT32) PstateMsr.IddDiv, &ProcIddMaxPerCore, StdHeader); + PciAddress.AddressValue = NB_CAPS_REG2_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &NbCap2, StdHeader); + *ProcIddMax = (UINT32) ProcIddMaxPerCore * (NbCap2.CmpCap + 1); + IDS_HDT_CONSOLE (CPU_TRACE, " Pstate %d ProcIddMax %d CmpCap %d\n", Pstate, *ProcIddMax, NbCap2.CmpCap); + if (PstateMsr.PsEnable == 1) { + IsPstateEnabled = TRUE; + } + return IsPstateEnabled; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Set down core register on Trinity + * + * This function set F3x190 Downcore Control Register[5:0] + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] Socket Socket ID. + * @param[in] Module Module ID in socket. + * @param[in] LeveledCores Number of core. + * @param[in] CoreLevelMode Core level mode. + * @param[in] StdHeader Header for library and services. + * + * @retval TRUE Down Core register is updated. + * @retval FALSE Down Core register is not updated. + */ +BOOLEAN +F15TnSetDownCoreRegister ( + IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices, + IN UINT32 *Socket, + IN UINT32 *Module, + IN UINT32 *LeveledCores, + IN CORE_LEVELING_TYPE CoreLevelMode, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 LocalPciRegister; + UINT32 CoreDisableBits; + PCI_ADDR PciAddress; + BOOLEAN IsUpdated; + AGESA_STATUS AgesaStatus; + + IsUpdated = FALSE; + CoreDisableBits = 0; + + if (CoreLevelMode == CORE_LEVEL_COMPUTE_UNIT) { + // CoreLevelMode == CORE_LVEL_COMPUTE_UNIT is not supported. + } else { + switch (*LeveledCores) { + // Only down core to 2 cores will take effect through a warm reset. + case 2: + CoreDisableBits = DOWNCORE_MASK_DUAL; + break; + } + } + + if (CoreDisableBits != 0) { + if (GetPciAddress (StdHeader, (UINT8) *Socket, (UINT8) *Module, &PciAddress, &AgesaStatus)) { + PciAddress.Address.Function = FUNC_5; + PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_2_REG; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + LocalPciRegister = (LocalPciRegister & 0xFF) + 1; + LocalPciRegister = (1 << LocalPciRegister) - 1; + CoreDisableBits &= LocalPciRegister; + + PciAddress.Address.Function = FUNC_3; + PciAddress.Address.Register = DOWNCORE_CTRL; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + if ((LocalPciRegister | CoreDisableBits) != LocalPciRegister) { + LocalPciRegister |= CoreDisableBits; + LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + IsUpdated = TRUE; + } + } + } + + return IsUpdated; +} + + +CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15TnCoreLeveling = +{ + 0, + F15TnSetDownCoreRegister +}; + + +/*---------------------------------------------------------------------------------------*/ +/** + * Determines the NB clock on the desired node. + * + * @CpuServiceMethod{::F_CPU_GET_NB_FREQ}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[out] FrequencyInMHz Northbridge clock frequency in MHz. + * @param[in] StdHeader Header for library and services. + * + * @return AGESA_SUCCESS FrequencyInMHz is valid. + */ +AGESA_STATUS +F15TnGetCurrentNbFrequency ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT UINT32 *FrequencyInMHz, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + NB_PSTATE_STS_REGISTER NbPstateStsReg; + PCI_ADDR PciAddress; + AGESA_STATUS ReturnCode; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnGetCurrentNbFrequency\n"); + + PciAddress.AddressValue = NB_PSTATE_STATUS_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &NbPstateStsReg, StdHeader); + ReturnCode = F15TnCalculateNbFrequencyInMHz ( + NbPstateStsReg.CurNbFid, + NbPstateStsReg.CurNbDid, + FrequencyInMHz, + StdHeader + ); + return ReturnCode; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the node's minimum and maximum northbridge frequency. + * + * @CpuServiceMethod{::F_CPU_GET_MIN_MAX_NB_FREQ}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] PlatformConfig Platform profile/build option config structure. + * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question. + * @param[out] MinFreqInMHz The node's minimum northbridge frequency. + * @param[out] MaxFreqInMHz The node's maximum northbridge frequency. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval AGESA_SUCCESS Northbridge frequency is valid + */ +AGESA_STATUS +F15TnGetMinMaxNbFrequency ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PCI_ADDR *PciAddress, + OUT UINT32 *MinFreqInMHz, + OUT UINT32 *MaxFreqInMHz, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + INT8 NbPsMaxVal; + UINT8 i; + UINT32 LocalPciRegister; + AGESA_STATUS AgesaStatus; + + AgesaStatus = AGESA_ERROR; + + // Obtain the max NB frequency on the node + PciAddress->Address.Function = FUNC_5; + PciAddress->Address.Register = NB_PSTATE_CTRL; + LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader); + NbPsMaxVal = (INT8) ((NB_PSTATE_CTRL_REGISTER *) &LocalPciRegister)->NbPstateMaxVal; + + // Starting from NB Pmax + for (i = 0; i <= NbPsMaxVal; i++) { + PciAddress->Address.Function = FUNC_5; + PciAddress->Address.Register = (NB_PSTATE_0 + (4 * i)); + LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader); + + // Ensure that the NB Pstate is enabled + if (((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbPstateEn == 1) { + AgesaStatus = F15TnCalculateNbFrequencyInMHz (((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbFid, + ((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbDid, + MaxFreqInMHz, + StdHeader); + break; + } + } + // If all of NbPstates are disabled, get MaxFreqInMHz from CurNbPstate + if (i > NbPsMaxVal) { + PciAddress->Address.Register = NB_PSTATE_STATUS; + LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader); + F15TnCalculateNbFrequencyInMHz (((NB_PSTATE_STS_REGISTER *) &LocalPciRegister)->CurNbFid, + ((NB_PSTATE_STS_REGISTER *) &LocalPciRegister)->CurNbDid, + MaxFreqInMHz, + StdHeader); + // No one NbPstate is enabled, so set Min = Max + *MinFreqInMHz = *MaxFreqInMHz; + ASSERT (FALSE); + } else { + // If platform configuration disable NB P-states, return the NB P0 frequency + // as both the min and max frequency on the node. + if (PlatformConfig->PlatformProfile.PlatformPowerPolicy == Performance) { + *MinFreqInMHz = *MaxFreqInMHz; + } else { + PciAddress->Address.Function = FUNC_5; + PciAddress->Address.Register = NB_PSTATE_CTRL; + LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader); + NbPsMaxVal = (INT8) ((NB_PSTATE_CTRL_REGISTER *) &LocalPciRegister)->NbPstateMaxVal; + + // Obtain the min NB frequency on the node, starting from NB Pmin + for (/* NbPsMaxVal */; NbPsMaxVal >= 0; NbPsMaxVal--) { + PciAddress->Address.Function = FUNC_5; + PciAddress->Address.Register = (NB_PSTATE_0 + (4 * NbPsMaxVal)); + LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader); + + // Ensure that the NB Pstate is enabled + if (((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbPstateEn == 1) { + AgesaStatus = F15TnCalculateNbFrequencyInMHz (((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbFid, + ((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbDid, + MinFreqInMHz, + StdHeader); + break; + } + } + } + } + IDS_OPTION_HOOK (IDS_NBPS_MIN_FREQ, MinFreqInMHz, StdHeader); + + return AgesaStatus; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Determines the NB clock on the desired node. + * + * @CpuServiceMethod{::F_CPU_GET_NB_PSTATE_INFO}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] PlatformConfig Platform profile/build option config structure. + * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question. + * @param[in] NbPstate The NB P-state number to check. + * @param[out] FreqNumeratorInMHz The desired node's frequency numerator in megahertz. + * @param[out] FreqDivisor The desired node's frequency divisor. + * @param[out] VoltageInuV The desired node's voltage in microvolts. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval TRUE NbPstate is valid + * @retval FALSE NbPstate is disabled or invalid + */ +BOOLEAN +F15TnGetNbPstateInfo ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PCI_ADDR *PciAddress, + IN UINT32 NbPstate, + OUT UINT32 *FreqNumeratorInMHz, + OUT UINT32 *FreqDivisor, + OUT UINT32 *VoltageInuV, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 NbVid; + BOOLEAN PstateIsValid; + NB_PSTATE_CTRL_REGISTER NbPstateCtrlReg; + NB_PSTATE_REGISTER NbPstateReg; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnGetNbPstateInfo - NB P%d\n", NbPstate); + + ASSERT ((PciAddress->Address.Segment == 0) && (PciAddress->Address.Bus == 0) && (PciAddress->Address.Device == 0x18)); + + PstateIsValid = FALSE; + + // If NB P1, P2, or P3 is requested, make sure that NB Pstate is enabled + if ((NbPstate == 0) || (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, PlatformConfig, StdHeader))) { + PciAddress->AddressValue = NB_PSTATE_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, *PciAddress, &NbPstateCtrlReg, StdHeader); + + ASSERT ((NbPstate < NM_NB_PS_REG) && (NbPstateCtrlReg.NbPstateMaxVal < NM_NB_PS_REG)); + if (NbPstate <= NbPstateCtrlReg.NbPstateMaxVal) { + PciAddress->Address.Register = (NB_PSTATE_0 + (sizeof (NB_PSTATE_REGISTER) * NbPstate)); + LibAmdPciRead (AccessWidth32, *PciAddress, &NbPstateReg, StdHeader); + IDS_HDT_CONSOLE (CPU_TRACE, " En:%d Fid:%x Did:%x Vid:%x\n", NbPstateReg.NbPstateEn, NbPstateReg.NbFid, NbPstateReg.NbDid, GetF15TnNbVid (&NbPstateReg)); + + // Check if at least NB P0 is enabled. + ASSERT ((NbPstate == 0) ? (NbPstateReg.NbPstateEn == 1) : TRUE); + // Ensure that requested NbPstate is enabled + if (NbPstateReg.NbPstateEn == 1) { + // Check for P-state Bandwidth Requirements on + // "All NB P-states must be defined such that D18F5x1[6C:60][NbFid] <= 2Eh" + ASSERT (NbPstateReg.NbFid <= 0x2E); + F15TnGetNbFreqNumeratorInMHz (NbPstateReg.NbFid, FreqNumeratorInMHz, StdHeader); + F15TnGetNbFreqDivisor (NbPstateReg.NbDid, FreqDivisor, StdHeader); + // Check for P-state Bandwidth Requirements on + // "NBCOF >= 700MHz" + ASSERT ((*FreqNumeratorInMHz / *FreqDivisor) >= 700); + + NbVid = GetF15TnNbVid (&NbPstateReg); + F15TnCovertVidInuV (NbVid, VoltageInuV, StdHeader); + PstateIsValid = TRUE; + IDS_HDT_CONSOLE (CPU_TRACE, " NB Pstate %d is Valid. NbVid=%d VoltageInuV=%d\n", NbPstate, NbVid, *VoltageInuV); + } + } + } + return PstateIsValid; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Get NB pstate current. + * + * @CpuServiceMethod{::F_CPU_GET_NB_IDD_MAX}. + * + * This function returns the NbIddMax. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] NbPstate The NB P-state to check. + * @param[out] NbIddMax NB P-state current in mA. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval TRUE NB P-state is enabled, and NbIddMax is valid. + * @retval FALSE NB P-state is disabled + */ +BOOLEAN +F15TnGetNbIddMax ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN UINT8 NbPstate, + OUT UINT32 *NbIddMax, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + BOOLEAN IsNbPsEnabled; + PCI_ADDR PciAddress; + NB_PSTATE_CTRL_REGISTER NbPstateCtrlReg; + NB_PSTATE_REGISTER NbPstateReg; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnGetNbIddMax - NB P%d\n", NbPstate); + + IsNbPsEnabled = FALSE; + + PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &NbPstateCtrlReg, StdHeader); + + ASSERT (NbPstate < NM_NB_PS_REG); + if (NbPstate <= NbPstateCtrlReg.NbPstateMaxVal) { + PciAddress.Address.Register = (NB_PSTATE_0 + (sizeof (NB_PSTATE_REGISTER) * NbPstate)); + LibAmdPciRead (AccessWidth32, PciAddress, &NbPstateReg, StdHeader); + + // Ensure that requested NbPstate is enabled + if (NbPstateReg.NbPstateEn == 1) { + F15TnCmnCalculateCurrentInmA (NbPstateReg.NbIddValue, NbPstateReg.NbIddDiv, NbIddMax, StdHeader); + IsNbPsEnabled = TRUE; + IDS_HDT_CONSOLE (CPU_TRACE, " NB Pstate %d is Valid. NbIddMax %d\n", NbPstate, *NbIddMax); + } + } + return IsNbPsEnabled; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Get the number of physical cores of current processor. + * + * @CpuServiceMethod{::F_CPU_NUMBER_OF_PHYSICAL_CORES}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @return The number of physical cores. + */ +UINT8 +F15TnGetNumberOfPhysicalCores ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + CPUID_DATA CpuId; + + // + //CPUID.80000008h.ECX.NC + 1, 000b = 1, 001b = 2, etc. + // + LibAmdCpuidRead (CPUID_LONG_MODE_ADDR, &CpuId, StdHeader); + return ((UINT8) ((CpuId.ECX_Reg & 0xff) + 1)); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Use the Mailbox Register to get the Ap Mailbox info for the current core. + * + * @CpuServiceMethod{::F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE}. + * + * Access the mailbox register used with this NB family. This is valid until the + * point that some init code initializes the mailbox register for its normal use. + * The Machine Check Misc (Thresholding) register is available as both a PCI config + * register and a MSR, so it can be used as a mailbox from HT to other functions. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[out] ApMailboxInfo The AP Mailbox info + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +VOID +F15TnGetApMailboxFromHardware ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT AP_MAILBOXES *ApMailboxInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + // For Family 15h Trinity, we will return socket 0, node 0, module 0, module type 0, and 0 for + // the system degree + ApMailboxInfo->ApMailInfo.Info = (UINT32) 0x00000000; + ApMailboxInfo->ApMailExtInfo.Info = (UINT32) 0x00000000; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Get this AP's system core number from hardware. + * + * @CpuServiceMethod{::F_CPU_GET_AP_CORE_NUMBER}. + * + * Returns the system core number from the scratch MSR, where + * it was saved at heap initialization. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @return The AP's unique core number + */ +UINT32 +F15TnGetApCoreNumber ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + CPUID_DATA Cpuid; + + LibAmdCpuidRead (0x1, &Cpuid, StdHeader); + return ((Cpuid.EBX_Reg >> 24) & 0xFF); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Is the Northbridge PState feature enabled? + * + * @CpuServiceMethod{::F_IS_NB_PSTATE_ENABLED}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] PlatformConfig Platform profile/build option config structure. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval TRUE The NB PState feature is enabled. + * @retval FALSE The NB PState feature is not enabled. + */ +BOOLEAN +F15TnIsNbPstateEnabled ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + BOOLEAN PowerMode; + BOOLEAN SkipHwCfg; + NB_PSTATE_STS_REGISTER NbPstateSts; + NB_PSTATE_CTRL_REGISTER NbPstateCtrl; + + + PciAddress.AddressValue = NB_PSTATE_STATUS_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, (VOID *) &NbPstateSts, StdHeader); + if (NbPstateSts.NbPstateDis == 1) { + return FALSE; + } + + SkipHwCfg = FALSE; + IDS_OPTION_HOOK (IDS_NBPSDIS_OVERRIDE, &SkipHwCfg, StdHeader); + if (!SkipHwCfg) { + } + + // Defaults to Power Optimized Mode + PowerMode = TRUE; + + // If system is optimized for performance, disable NB P-States + if (PlatformConfig->PlatformProfile.PlatformPowerPolicy == Performance) { + PowerMode = FALSE; + } + + PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, (VOID *) &NbPstateCtrl, StdHeader); + if (((NbPstateCtrl.NbPstateMaxVal != 0) || SkipHwCfg) && (PowerMode)) { + return TRUE; + } + return FALSE; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Disable NB P-state. + * - clear F5x1[6C:64] + * - clear F5x170[NbPstateMaxVal] + * - set F5x170[SwNbPstateLoDis] + * - clear MSRC001_00[6B:64][NbPstate] + * + * @param[in] FamilySpecificServices The current Family Specific Services + * @param[in] CpuEarlyParamsPtr Service Parameters + * @param[in] StdHeader Handle of Header for calling lib functions and services. + */ +VOID +F15TnNbPstateDis ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 i; + UINT32 PciData; + UINT32 NbPsCtrl; + UINT32 NbPsCtrlOrg; + UINT32 AndMask; + BOOLEAN SkipNbPsLoPart; + AP_TASK TaskPtr; + PCI_ADDR PciAddress; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnNbPstateDis\n"); + + // Check whether NB P-state is disabled + if (!FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, &CpuEarlyParamsPtr->PlatformConfig, StdHeader)) { + + IDS_HDT_CONSOLE (CPU_TRACE, " NB Pstates disabled\n"); + + PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); + NbPsCtrlOrg = NbPsCtrl; + + AndMask = 0x00000000; + // If CurNbPstate is not NB P0, get the Pstate pointed to by CurNbPstate and copy it's value to NB P0 to P3 and clear NbPstateHi + PciAddress.Address.Register = NB_PSTATE_STATUS; + LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); + + SkipNbPsLoPart = FALSE; + + if (((NB_PSTATE_STS_REGISTER *) &PciData)->CurNbPstate != 0) { + PciAddress.Address.Register = NB_PSTATE_0 + (((NB_PSTATE_STS_REGISTER *) &PciData)->CurNbPstate * 4); + LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); + + for (i = 1; i < NM_NB_PS_REG; i++) { + PciAddress.Address.Register = NB_PSTATE_0 + (i * 4); + OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, PciData, StdHeader); + } + + if (!SkipNbPsLoPart) { + // Program D18F5x170 to transition the NB P-state: + // 1) NbPstateLo = NbPstateMaxVal. + // 2) SwNbPstateLoDis = NbPstateDisOnP0 = NbPstateThreshold = 0. + + PciAddress.Address.Register = NB_PSTATE_CTRL; + ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateLo = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateMaxVal; + LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); + ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->SwNbPstateLoDis = 0; + ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateDisOnP0 = 0; + ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateThreshold = 0; + LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); + + // Wait for D18F5x174[CurNbPstate] to equal NbPstateLo. + PciAddress.Address.Register = NB_PSTATE_STATUS; + do { + LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); + } while (((NB_PSTATE_STS_REGISTER *) &PciData)->CurNbPstate != ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateLo); + } + } + + // Program D18F5x170 to force the NB P-state: + // 1) NbPstateHi = target NB P-state. + // 2) SwNbPstateLoDis = 1 + // And clear F5x170[NbPstateMaxVal] + PciAddress.Address.Register = NB_PSTATE_CTRL; + ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateHi = 0; + ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateMaxVal = 0; + LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); + ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->SwNbPstateLoDis = 1; + LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); + + // Wait for D18F5x174[CurNbPstate] to equal the target NB P-state. + PciAddress.Address.Register = NB_PSTATE_STATUS; + do { + LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); + } while (((NB_PSTATE_STS_REGISTER *) &PciData)->CurNbPstate != 0); + + // Clear F5x1[6C:64] + AndMask = 0x00000000; + for (i = 1; i < NM_NB_PS_REG; i++) { + PciAddress.Address.Register = NB_PSTATE_0 + (i * 4); + OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, AndMask, StdHeader); + } + + // Clear MSRC001_00[6B:64][NbPstate] on cores + TaskPtr.FuncAddress.PfApTask = F15TnNbPstateDisCore; + TaskPtr.DataTransfer.DataSizeInDwords = 0; + TaskPtr.DataTransfer.DataPtr = NULL; + TaskPtr.ExeFlags = WAIT_FOR_CORE; + ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr); + + + // BIOS performs the following to release the NB P-state force: + // 1. Restore the initial D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateLo] values. + // 2. Restore the initial D18F5x170[NbPstateThreshold, NbPstateHi] values. + PciAddress.Address.Register = NB_PSTATE_CTRL; + LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); + ((NB_PSTATE_CTRL_REGISTER *) &PciData)->NbPstateLo = 0; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader); + ((NB_PSTATE_CTRL_REGISTER *) &PciData)->SwNbPstateLoDis = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOrg)->SwNbPstateLoDis; + ((NB_PSTATE_CTRL_REGISTER *) &PciData)->NbPstateDisOnP0 = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOrg)->NbPstateDisOnP0; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader); + + ((NB_PSTATE_CTRL_REGISTER *) &PciData)->NbPstateHi = 0; + ((NB_PSTATE_CTRL_REGISTER *) &PciData)->NbPstateMaxVal = 0; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader); + ((NB_PSTATE_CTRL_REGISTER *) &PciData)->NbPstateThreshold = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOrg)->NbPstateThreshold; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader); + } +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Disable NB P-state on core. + * - clear MSRC001_00[6B:64][NbPstate]. + * + * @param[in] StdHeader Handle of Header for calling lib functions and services. + */ +VOID +STATIC +F15TnNbPstateDisCore ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 i; + UINT64 MsrData; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnNbPstateDisCore\n"); + + // Only one core per compute unit needs to clear NbPstate in P-state MSRs + if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) { + for (i = MSR_PSTATE_0; i <= MSR_PSTATE_7; i++) { + LibAmdMsrRead (i, &MsrData, StdHeader); + ((PSTATE_MSR *) &MsrData)->NbPstate = 0; + LibAmdMsrWrite (i, &MsrData, StdHeader); + } + } +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Get NB Frequency Numerator in MHz + * + * @param[in] NbFid NB Frequency ID to convert + * @param[out] FreqNumeratorInMHz The desire NB FID's frequency numerator in megahertz. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + */ +VOID +STATIC +F15TnGetNbFreqNumeratorInMHz ( + IN UINT32 NbFid, + OUT UINT32 *FreqNumeratorInMHz, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnGetNbFreqNumeratorInMHz - NbFid=%d\n", NbFid); + *FreqNumeratorInMHz = (NbFid + 4) * 100; + IDS_HDT_CONSOLE (CPU_TRACE, " FreqNumeratorInMHz=%d\n", *FreqNumeratorInMHz); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Get NB Frequency Divisor + * + * @param[in] NbDid NB Divisor ID to convert. + * @param[out] FreqDivisor The desire NB DID's frequency divisor. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + */ +VOID +STATIC +F15TnGetNbFreqDivisor ( + IN UINT32 NbDid, + OUT UINT32 *FreqDivisor, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnGetNbFreqDivisor - NbDid=%d\n", NbDid); + *FreqDivisor = (1 << NbDid); + IDS_HDT_CONSOLE (CPU_TRACE, " FreqDivisor=%d\n", *FreqDivisor); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Calculate NB Frequency in MHz + * + * @param[in] NbFid NB Frequency ID to convert + * @param[in] NbDid NB Divisor ID to convert. + * @param[out] FrequencyInMHz The Northbridge clock frequency in megahertz. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @return AGESA_SUCCESS FrequencyInMHz is valid. + */ +AGESA_STATUS +STATIC +F15TnCalculateNbFrequencyInMHz ( + IN UINT32 NbFid, + IN UINT32 NbDid, + OUT UINT32 *FrequencyInMHz, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 FreqNumeratorInMHz; + UINT32 FreqDivisor; + AGESA_STATUS ReturnStatus; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnCalculateNbFrequencyInMHz - NbFid=%x, NbDid=%x\n", NbFid, NbDid); + + ReturnStatus = AGESA_SUCCESS; + F15TnGetNbFreqNumeratorInMHz (NbFid, &FreqNumeratorInMHz, StdHeader); + F15TnGetNbFreqDivisor (NbDid, &FreqDivisor, StdHeader); + *FrequencyInMHz = FreqNumeratorInMHz / FreqDivisor; + IDS_HDT_CONSOLE (CPU_TRACE, " FrequencyInMHz=%d\n", *FrequencyInMHz); + + return ReturnStatus; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Convert VID to microvolts(uV) + * + * @param[in] Vid The voltage ID of SVI2 encoding to be converted. + * @param[out] VoltageInuV The voltage in microvolts. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + */ +VOID +STATIC +F15TnCovertVidInuV ( + IN UINT32 Vid, + OUT UINT32 *VoltageInuV, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnCovertVidInuV\n"); + // Maximum 1.55V, 6.25mV per stpe + *VoltageInuV = ConvertVidInuV(Vid); + IDS_HDT_CONSOLE (CPU_TRACE, " Vid=%x, VoltageInuV=%d\n", Vid, *VoltageInuV); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Get Core/NB Idd Divisor + * + * @param[in] IddDiv Core/NB current divisor to convert. + * @param[out] IddDivisor The desire Core/NB current divisor. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +VOID +STATIC +F15TnCmnGetIddDivisor ( + IN UINT32 IddDiv, + OUT UINT32 *IddDivisor, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnCmnGetIddDivisor - IddDiv=%d\n", IddDiv); + + switch (IddDiv) { + case 0: + *IddDivisor = 1000; + break; + case 1: + *IddDivisor = 100; + break; + case 2: + *IddDivisor = 10; + break; + default: // IddDiv = 3 is reserved. Use 10 + *IddDivisor = 10; + ASSERT (FALSE); + break; + } + IDS_HDT_CONSOLE (CPU_TRACE, " IddDivisor=%d\n", *IddDivisor); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Calculate Core/NB current in mA + * + * @param[in] IddValue Core/NB current value. + * @param[in] IddDiv Core/NB current divisor. + * @param[out] CurrentInmA The Core/NB current in milliampere. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +VOID +STATIC +F15TnCmnCalculateCurrentInmA ( + IN UINT32 IddValue, + IN UINT32 IddDiv, + OUT UINT32 *CurrentInmA, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 IddDivisor; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnCmnCalculateCurrentInmA - IddValue=%x, IddDiv=%x\n", IddValue, IddDiv); + + F15TnCmnGetIddDivisor (IddDiv, &IddDivisor, StdHeader); + *CurrentInmA = IddValue * IddDivisor; + + IDS_HDT_CONSOLE (CPU_TRACE, " CurrentInmA=%d\n", *CurrentInmA); +} + + + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnUtilities.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnUtilities.h new file mode 100644 index 0000000..1b971fb --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnUtilities.h @@ -0,0 +1,177 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity specific utility functions. + * + * Provides numerous utility functions specific to family 15h. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _F15_TN_UTILITES_H_ +#define _F15_TN_UTILITES_H_ + + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ + +UINT8 +F15TnGetNumberOfPhysicalCores ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +F15TnGetApMailboxFromHardware ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT AP_MAILBOXES *ApMailboxInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +F15TnIsNbPstateEnabled ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +F15TnNbPstateDis ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +F15TnGetProcIddMax ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN UINT8 Pstate, + OUT UINT32 *ProcIddMax, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +F15TnGetNbIddMax ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN UINT8 NbPstate, + OUT UINT32 *NbIddMax, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +F15TnGetCurrentNbFrequency ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT UINT32 *FrequencyInMHz, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +F15TnGetMinMaxNbFrequency ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PCI_ADDR *PciAddress, + OUT UINT32 *MinFreqInMHz, + OUT UINT32 *MaxFreqInMHz, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +F15TnGetNbPstateInfo ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PCI_ADDR *PciAddress, + IN UINT32 NbPstate, + OUT UINT32 *FreqNumeratorInMHz, + OUT UINT32 *FreqDivisor, + OUT UINT32 *VoltageInuV, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +F15TnGetApCoreNumber ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCacheFlushOnHalt.c new file mode 100644 index 0000000..2235eed --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCacheFlushOnHalt.c @@ -0,0 +1,191 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Cache Flush On Halt Function for Family 15h Trinity. + * + * Contains code to initialize Cache Flush On Halt feature for Family 15h Trinity. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + *---------------------------------------------------------------------------- + */ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuRegisters.h" +#include "cpuServices.h" +#include "cpuFamilyTranslation.h" +#include "cpuPostInit.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "cpuFeatures.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNCACHEFLUSHONHALT_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +VOID +SetF15TnCacheFlushOnHaltRegister ( + IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices, + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * P U B L I C F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * Enable Cpu Cache Flush On Halt Function + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + */ +VOID +SetF15TnCacheFlushOnHaltRegister ( + IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices, + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + CLK_PWR_TIMING_CTRL2_REGISTER ClkPwrTimingCtrl2; + CSTATE_POLICY_CTRL1_REGISTER CstatePolicyCtrl1; + CSTATE_CTRL1_REGISTER CstateCtrl1; + + if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) { + // Set D18F3xDC[CacheFlushOnHaltCtl] != 0 + // Set D18F3xDC[CacheFlushOnHaltTmr] + PciAddress.AddressValue = CPTC2_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); + ClkPwrTimingCtrl2.CacheFlushOnHaltCtl = 7; + ClkPwrTimingCtrl2.CacheFlushOnHaltTmr = 0x14; + LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); + + // Set D18F4x128[CacheFlushTmr, CacheFlushSucMonThreshold] + PciAddress.AddressValue = CSTATE_POLICY_CTRL1_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader); + CstatePolicyCtrl1.CacheFlushTmr = 0x14; + CstatePolicyCtrl1.CacheFlushSucMonThreshold = 7; + LibAmdPciWrite (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader); + + // Set cache flush bits in D18F4x118 + PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader); + // Set C-state Action Field 0 + CstateCtrl1.CacheFlushEnCstAct0 = 1; + CstateCtrl1.CacheFlushTmrSelCstAct0 = 2; + CstateCtrl1.ClkDivisorCstAct0 = 0; + // Set C-state Action Field 1 + CstateCtrl1.CacheFlushEnCstAct1 = 1; + CstateCtrl1.CacheFlushTmrSelCstAct1 = 1; + CstateCtrl1.ClkDivisorCstAct1 = 0; + LibAmdPciWrite (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader); + + //Override the default setting + IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, NULL, StdHeader); + } +} + +CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15TnCacheFlushOnHalt = +{ + 0, + SetF15TnCacheFlushOnHaltRegister +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.c new file mode 100644 index 0000000..64e82ef --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.c @@ -0,0 +1,280 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity after warm reset sequence for core P-states + * + * Performs the "Core Minimum P-State Transition Sequence After Warm Reset" + * as described in the BKDG. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "cpuRegisters.h" +#include "GeneralServices.h" +#include "cpuApicUtilities.h" +#include "cpuFamilyTranslation.h" +#include "OptionMultiSocket.h" +#include "cpuF15TnCoreAfterReset.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNCOREAFTERRESET_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +F15TnPmCoreAfterResetPhase1OnCore ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +F15TnPmCoreAfterResetPhase2OnCore ( + IN VOID *HwPsMaxVal, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; +/*---------------------------------------------------------------------------------------*/ +/** + * Family 15h Trinity core 0 entry point for performing the necessary steps for core + * P-states after a warm reset has occurred. + * + * The steps are as follows: + * 1. Write 0 to MSRC001_0062[PstateCmd] on all cores in the processor. + * 2. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from + * MSRC001_00[6B:64] indexed by MSRC001_0071[CurPstateLimit]. + * 3. Write MSRC001_0061[PstateMaxVal] to MSRC001_0062[PstateCmd] on all + * cores in the processor. + * 4. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from + * MSRC001_00[6B:64] indexed by MSRC001_0061[PstateMaxVal]. + * 5. If MSRC001_0071[CurPstateLimit] != MSRC001_0071[CurPstate], wait for + * MSRC001_0071[CurCpuVid] = [CpuVid] from MSRC001_00[6B:64] indexed by + * MSRC001_0061[PstateMaxVal]. + * 6. Wait for MSRC001_0063[CurPstate] = MSRC001_0062[PstateCmd]. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] CpuEarlyParamsPtr Service parameters + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +F15TnPmCoreAfterReset ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Core; + UINT32 HwPsMaxVal; + PCI_ADDR PciAddress; + AP_TASK TaskPtr; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnPmCoreAfterReset\n"); + + GetCurrentCore (&Core, StdHeader); + ASSERT (Core == 0); + + OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); + PciAddress.Address.Function = FUNC_3; + PciAddress.Address.Register = CPTC2_REG; + LibAmdPciRead (AccessWidth32, PciAddress, &HwPsMaxVal, StdHeader); + HwPsMaxVal = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &HwPsMaxVal)->PstateMaxVal; + + // Launch each local core to perform steps 1 through 3. + TaskPtr.FuncAddress.PfApTask = F15TnPmCoreAfterResetPhase1OnCore; + TaskPtr.DataTransfer.DataSizeInDwords = 0; + TaskPtr.ExeFlags = WAIT_FOR_CORE; + ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr); + + // Launch each local core to perform steps 4 through 6. + TaskPtr.FuncAddress.PfApTaskI = F15TnPmCoreAfterResetPhase2OnCore; + TaskPtr.DataTransfer.DataSizeInDwords = 1; + TaskPtr.DataTransfer.DataPtr = &HwPsMaxVal; + TaskPtr.DataTransfer.DataTransferFlags = 0; + TaskPtr.ExeFlags = WAIT_FOR_CORE; + ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr); +} + + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Support routine for F15TnPmCoreAfterReset to perform MSR initialization on all + * cores of a family 15h socket. + * + * This function implements steps 1 - 3 on each core. + * + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +STATIC +F15TnPmCoreAfterResetPhase1OnCore ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 CofvidSts; + UINT64 LocalMsrRegister; + UINT64 PstateCtrl; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnPmCoreAfterResetPhase1OnCore\n"); + + // 1. Write 0 to MSRC001_0062[PstateCmd] on all cores in the processor. + PstateCtrl = 0; + LibAmdMsrWrite (MSR_PSTATE_CTL, &PstateCtrl, StdHeader); + + // 2. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from + // MSRC001_00[6B:64] indexed by MSRC001_0071[CurPstateLimit]. + do { + LibAmdMsrRead (MSR_COFVID_STS, &CofvidSts, StdHeader); + LibAmdMsrRead ((UINT32) (MSR_PSTATE_0 + (UINT32) (((COFVID_STS_MSR *) &CofvidSts)->CurPstateLimit)), &LocalMsrRegister, StdHeader); + } while ((((COFVID_STS_MSR *) &CofvidSts)->CurCpuFid != ((PSTATE_MSR *) &LocalMsrRegister)->CpuFid) || + (((COFVID_STS_MSR *) &CofvidSts)->CurCpuDid != ((PSTATE_MSR *) &LocalMsrRegister)->CpuDid)); + + // 3. Write MSRC001_0061[PstateMaxVal] to MSRC001_0062[PstateCmd] on all + // cores in the processor. + LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader); + ((PSTATE_CTRL_MSR *) &PstateCtrl)->PstateCmd = ((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal; + LibAmdMsrWrite (MSR_PSTATE_CTL, &PstateCtrl, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Support routine for F15TnPmCoreAfterReset to perform MSR initialization on all + * cores of a family 15h socket. + * + * This function implements steps 4 - 6 on each core. + * + * @param[in] HwPsMaxVal Index of the highest enabled HW P-state. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +STATIC +F15TnPmCoreAfterResetPhase2OnCore ( + IN VOID *HwPsMaxVal, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 TargetPsMsr; + UINT64 LocalMsrRegister; + UINT64 PstateCtrl; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnPmCoreAfterResetPhase2OnCore\n"); + + // 4. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from + // MSRC001_00[6B:64] indexed by D18F3xDC[PstateMaxVal]. + LibAmdMsrRead ((*(UINT32 *) HwPsMaxVal) + MSR_PSTATE_0, &TargetPsMsr, StdHeader); + do { + LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader); + } while ((((COFVID_STS_MSR *) &LocalMsrRegister)->CurCpuFid != ((PSTATE_MSR *) &TargetPsMsr)->CpuFid) || + (((COFVID_STS_MSR *) &LocalMsrRegister)->CurCpuDid != ((PSTATE_MSR *) &TargetPsMsr)->CpuDid)); + + // 5. If MSRC001_0071[CurPstateLimit] != MSRC001_0071[CurPstate], wait for + // MSRC001_0071[CurCpuVid] = [CpuVid] from MSRC001_00[6B:64] indexed by + // MSRC001_0061[PstateMaxVal]. + if (((COFVID_STS_MSR *) &LocalMsrRegister)->CurPstateLimit != ((COFVID_STS_MSR *) &LocalMsrRegister)->CurPstate) { + do { + LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader); + } while (GetF15TnCurCpuVid (&LocalMsrRegister) != GetF15TnCpuVid (&TargetPsMsr)); + } + + // 6. Wait for MSRC001_0063[CurPstate] = MSRC001_0062[PstateCmd]. + LibAmdMsrRead (MSR_PSTATE_CTL, &PstateCtrl, StdHeader); + do { + LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader); + } while (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate != ((PSTATE_CTRL_MSR *) &PstateCtrl)->PstateCmd); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.h new file mode 100644 index 0000000..1e5b1ba --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.h @@ -0,0 +1,105 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity after warm reset sequence for core P-states + * + * Contains code that provide power management functionality + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_F15_TN_CORE_AFTER_RESET_H_ +#define _CPU_F15_TN_CORE_AFTER_RESET_H_ + + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ +VOID +F15TnPmCoreAfterReset ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif // _CPU_F15_TN_CORE_AFTER_RESET_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c new file mode 100644 index 0000000..e0240bd --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c @@ -0,0 +1,430 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD DMI Record Creation API, and related functions for Family15h Trinity. + * + * Contains code that produce the DMI related information. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e $Revision: 64351 $ @e $Date: 2012-01-19 03:50:41 -0600 (Thu, 19 Jan 2012) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuRegisters.h" +#include "cpuFamilyTranslation.h" +#include "cpuPstateTables.h" +#include "cpuLateInit.h" +#include "cpuF15Dmi.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "cpuServices.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNDMI_FILECODE + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +CONST CHAR8 ROMDATA str_A10[] = "AMD A10-"; +CONST CHAR8 ROMDATA str_A8[] = "AMD A8-"; +CONST CHAR8 ROMDATA str_A6[] = "AMD A6-"; +CONST CHAR8 ROMDATA str_A4[] = "AMD A4-"; +CONST CHAR8 ROMDATA str_PhenomII[] = "AMD Phenom(TM) II"; +CONST CHAR8 ROMDATA str_AthlonII[] = "AMD Athlon(TM) II"; +CONST CHAR8 ROMDATA str_SempronII[] = "AMD Sempron(TM) II"; +CONST CHAR8 ROMDATA str_Sempron[] = "AMD Sempron(TM)"; +/*--------------------------------------------------------------------------------------- + * Processor Family Table + * + * 048h = "A-Series" + * 0ECh = "AMD Phenom(TM) II Processor Family" + * 0EDh = "AMD Athlon(tm) II" + * 085h = "AMD Sempron(tm)" + * 0E5h = "AMD Sempron(tm) II" + + *-------------------------------------------------------------------------------------*/ + +CONST CPU_T4_PROC_FAMILY ROMDATA F15TnFP2T4ProcFamily[] = +{ + {str_A10, 0x48}, + {str_A8, 0x48}, + {str_A6, 0x48}, + {str_A4, 0x48}, +}; + +CONST CPU_T4_PROC_FAMILY ROMDATA F15TnFS1T4ProcFamily[] = +{ + {str_A10, 0x48}, + {str_A8, 0x48}, + {str_A6, 0x48}, + {str_A4, 0x48}, +}; + +CONST CPU_T4_PROC_FAMILY ROMDATA F15TnFM2T4ProcFamily[] = +{ + {str_A10, 0x48}, + {str_A8, 0x48}, + {str_A6, 0x48}, + {str_A4, 0x48}, + {str_PhenomII, 0xEC}, + {str_AthlonII, 0xED}, + {str_SempronII, 0xE5}, + {str_Sempron, 0x85}, +}; +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +DmiF15TnGetInfo ( + IN OUT CPU_TYPE_INFO *CpuInfoPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +DmiF15TnGetT4ProcFamily ( + IN OUT UINT8 *T4ProcFamily, + IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable, + IN CPU_TYPE_INFO *CpuInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +DmiF15TnGetVoltage ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +DmiF15TnGetMemInfo ( + IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT16 +DmiF15TnGetExtClock ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * DmiF15TnGetInfo + * + * Get CPU type information + * + * @param[in,out] CpuInfoPtr Pointer to CPU_TYPE_INFO struct. + * @param[in] StdHeader Standard Head Pointer + * + */ +VOID +DmiF15TnGetInfo ( + IN OUT CPU_TYPE_INFO *CpuInfoPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 NumOfCoresPerCU; + CPUID_DATA CpuId; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, StdHeader); + CpuInfoPtr->ExtendedFamily = (UINT8) (CpuId.EAX_Reg >> 20) & 0xFF; // bit 27:20 + CpuInfoPtr->ExtendedModel = (UINT8) (CpuId.EAX_Reg >> 16) & 0xF; // bit 19:16 + CpuInfoPtr->BaseFamily = (UINT8) (CpuId.EAX_Reg >> 8) & 0xF; // bit 11:8 + CpuInfoPtr->BaseModel = (UINT8) (CpuId.EAX_Reg >> 4) & 0xF; // bit 7:4 + CpuInfoPtr->Stepping = (UINT8) (CpuId.EAX_Reg & 0xF); // bit 3:0 + + CpuInfoPtr->PackageType = (UINT8) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28 + + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + CpuInfoPtr->TotalCoreNumber = FamilySpecificServices->GetNumberOfPhysicalCores (FamilySpecificServices, StdHeader); + CpuInfoPtr->TotalCoreNumber--; + + LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuId, StdHeader); + CpuInfoPtr->EnabledCoreNumber = (UINT8) (CpuId.ECX_Reg & 0xFF); // bit 7:0 + + switch (CpuInfoPtr->PackageType) { + case TN_SOCKET_FP2: + CpuInfoPtr->ProcUpgrade = P_UPGRADE_NONE; + break; + case TN_SOCKET_FS1: + CpuInfoPtr->ProcUpgrade = P_UPGRADE_FS1; + break; + case TN_SOCKET_FM2: + CpuInfoPtr->ProcUpgrade = P_UPGRADE_FM2; + break; + default: + CpuInfoPtr->ProcUpgrade = P_UPGRADE_UNKNOWN; + break; + } + + switch (GetComputeUnitMapping (StdHeader)) { + case AllCoresMapping: + NumOfCoresPerCU = 1; + break; + case EvenCoresMapping: + NumOfCoresPerCU = 2; + break; + default: + NumOfCoresPerCU = 2; + } + // L1 Size & Associativity + LibAmdCpuidRead (AMD_CPUID_TLB_L1Cache, &CpuId, StdHeader); + CpuInfoPtr->CacheInfo.L1CacheSize = (UINT32) (((UINT8) ((CpuId.ECX_Reg >> 24) * NumOfCoresPerCU) + (UINT8) (CpuId.EDX_Reg >> 24)) * (CpuInfoPtr->EnabledCoreNumber + 1) / NumOfCoresPerCU); + + CpuInfoPtr->CacheInfo.L1CacheAssoc = DMI_ASSOCIATIVE_2_WAY; // Per the BKDG, this is hard-coded to 2-Way. + + // L2 Size & Associativity + LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuId, StdHeader); + CpuInfoPtr->CacheInfo.L2CacheSize = (UINT32) ((UINT16) (CpuId.ECX_Reg >> 16) * (CpuInfoPtr->EnabledCoreNumber + 1) / NumOfCoresPerCU); + + CpuInfoPtr->CacheInfo.L2CacheAssoc = DMI_ASSOCIATIVE_16_WAY; // Per the BKDG, this is hard-coded to 16-Way. + + // L3 Size & Associativity + CpuInfoPtr->CacheInfo.L3CacheSize = 0; + CpuInfoPtr->CacheInfo.L3CacheAssoc = DMI_ASSOCIATIVE_UNKNOWN; + } + +/* -----------------------------------------------------------------------------*/ +/** + * + * DmiF15TnGetT4ProcFamily + * + * Get type 4 processor family information + * + * @param[in,out] T4ProcFamily Pointer to type 4 processor family information. + * @param[in] *CpuDmiProcFamilyTable Pointer to DMI family special service + * @param[in] *CpuInfo Pointer to CPU_TYPE_INFO struct + * @param[in] StdHeader Standard Head Pointer + * + */ +VOID +DmiF15TnGetT4ProcFamily ( + IN OUT UINT8 *T4ProcFamily, + IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable, + IN CPU_TYPE_INFO *CpuInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + CHAR8 NameString[49]; + CONST CHAR8 *DmiString; + CONST VOID *DmiStringTable; + UINT8 NumberOfDmiString; + UINT8 i; + + // Get name string from MSR_C001_00[30:35] + GetNameString (NameString, StdHeader); + // Get DMI String + DmiStringTable = NULL; + switch (CpuInfo->PackageType) { + case TN_SOCKET_FP2: + DmiStringTable = (CONST VOID *) &F15TnFP2T4ProcFamily[0]; + NumberOfDmiString = sizeof (F15TnFP2T4ProcFamily) / sizeof (CPU_T4_PROC_FAMILY); + break; + case TN_SOCKET_FS1: + DmiStringTable = (CONST VOID *) &F15TnFS1T4ProcFamily[0]; + NumberOfDmiString = sizeof (F15TnFS1T4ProcFamily) / sizeof (CPU_T4_PROC_FAMILY); + break; + case TN_SOCKET_FM2: + DmiStringTable = (CONST VOID *) &F15TnFM2T4ProcFamily[0]; + NumberOfDmiString = sizeof (F15TnFM2T4ProcFamily) / sizeof (CPU_T4_PROC_FAMILY); + break; + default: + DmiStringTable = NULL; + NumberOfDmiString = 0; + break; + } + + // Find out which DMI string matches current processor's name string + *T4ProcFamily = P_FAMILY_UNKNOWN; + if ((DmiStringTable != NULL) && (NumberOfDmiString != 0)) { + for (i = 0; i < NumberOfDmiString; i++) { + DmiString = (((CPU_T4_PROC_FAMILY *) DmiStringTable)[i]).Stringstart; + if (IsSourceStrContainTargetStr (NameString, DmiString, StdHeader)) { + *T4ProcFamily = (((CPU_T4_PROC_FAMILY *) DmiStringTable)[i]).T4ProcFamilySetting; + break; + } + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * DmiF15TnGetVoltage + * + * Get the voltage value according to SMBIOS SPEC's requirement. + * + * @param[in] StdHeader Standard Head Pointer + * + * @retval Voltage - CPU Voltage. + * + */ +UINT8 +DmiF15TnGetVoltage ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 MaxVid; + UINT8 Voltage; + UINT8 NumberBoostStates; + UINT64 MsrData; + PCI_ADDR TempAddr; + CPB_CTRL_REGISTER CpbCtrl; + + // Voltage = 0x80 + (voltage at boot time * 10) + TempAddr.AddressValue = CPB_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, TempAddr, &CpbCtrl, StdHeader); // F4x15C + NumberBoostStates = (UINT8) CpbCtrl.NumBoostStates; + + LibAmdMsrRead ((MSR_PSTATE_0 + NumberBoostStates), &MsrData, StdHeader); + MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid); + + if ((MaxVid >= 0xF8) && (MaxVid <= 0xFF)) { + Voltage = 0; + } else { + Voltage = (UINT8) ((155000L - (625 * MaxVid) + 5000) / 10000); + } + + Voltage += 0x80; + return (Voltage); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * DmiF15TnGetMemInfo + * + * Get memory information. + * + * @param[in,out] CpuGetMemInfoPtr Pointer to CPU_GET_MEM_INFO struct. + * @param[in] StdHeader Standard Head Pointer + * + */ +VOID +DmiF15TnGetMemInfo ( + IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + CpuGetMemInfoPtr->EccCapable = FALSE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * DmiF15TnGetExtClock + * + * Get the external clock Speed + * + * @param[in] StdHeader Standard Head Pointer + * + * @retval ExtClock - CPU external clock Speed. + * + */ +UINT16 +DmiF15TnGetExtClock ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return (EXTERNAL_CLOCK_100MHZ); +} + +/* -----------------------------------------------------------------------------*/ +CONST PROC_FAMILY_TABLE ROMDATA ProcFamily15TnDmiTable = +{ +// This table is for Processor family 15h Trinity + AMD_FAMILY_15_TN, // ID for Family 15h Trinity + DmiF15TnGetInfo, // Transfer vectors for family + DmiF15TnGetT4ProcFamily, // Get type 4 processor family information + DmiF15TnGetVoltage, // specific routines (above) + DmiF15GetMaxSpeed, + DmiF15TnGetExtClock, + DmiF15TnGetMemInfo, // Get memory information + 0, + NULL +}; + + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnHtc.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnHtc.c new file mode 100644 index 0000000..b1ac32f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnHtc.c @@ -0,0 +1,204 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 TN HTC Initialization + * + * Enables Hardware Thermal Control (HTC) feature + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e $Revision: 63692 $ @e $Date: 2012-01-03 22:13:28 -0600 (Tue, 03 Jan 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuRegisters.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "cpuFeatures.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "CommonReturns.h" +#include "cpuHtc.h" +#include "OptionMultiSocket.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNHTC_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +F15TnHtcInit ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PCI_ADDR PciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; + +/*---------------------------------------------------------------------------------------*/ +/** + * Entry point for enabling Hardware Thermal Control + * + * This function must be run after all P-State routines have been executed + * + * @param[in] HtcServices The current CPU's family services. + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Platform profile/build option config structure. + * @param[in] StdHeader Config handle for library and services. + * + * @retval AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +STATIC +F15TnInitializeHtc ( + IN HTC_FAMILY_SERVICES *HtcServices, + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) { + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0); + F15TnHtcInit (FamilySpecificServices, PlatformConfig, PciAddress, StdHeader); + } + + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Main entry point for initializing the Thermal Control + * safety net feature. + * + * This must be run by all Family 15h Trinity core 0s in the system. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] PlatformConfig Platform profile/build option config structure + * @param[in] PciAddress Segment, bus, device number of the node to transition. + * @param[in] StdHeader Config handle for library and services. + */ +VOID +F15TnHtcInit ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PCI_ADDR PciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 LocalPciRegister; + + PciAddress.AddressValue = NB_CAPS_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + if (((NB_CAPS_REGISTER *) &LocalPciRegister)->HtcCapable == 1) { + // Enable HTC + PciAddress.Address.Register = HTC_REG; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + if (((HTC_REGISTER *) &LocalPciRegister)->HtcTmpLmt != 0) { + // Enable HTC + ((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 1; + } else { + // Disable HTC + ((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 0; + } + IDS_OPTION_HOOK (IDS_HTC_CTRL, &LocalPciRegister, StdHeader); + LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + } +} + +CONST HTC_FAMILY_SERVICES ROMDATA F15TnHtcSupport = +{ + 0, + (PF_HTC_IS_SUPPORTED) CommonReturnTrue, + F15TnInitializeHtc +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.c new file mode 100644 index 0000000..1f23cc5 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.c @@ -0,0 +1,496 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity after warm reset sequence for NB P-states + * + * Performs the "NB COF and VID Transition Sequence After Warm Reset" + * as described in the BKDG. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e $Revision: 64197 $ @e $Date: 2012-01-17 16:18:33 -0600 (Tue, 17 Jan 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "cpuRegisters.h" +#include "cpuApicUtilities.h" +#include "cpuFamilyTranslation.h" +#include "GeneralServices.h" +#include "cpuServices.h" +#include "heapManager.h" +#include "cpuF15TnNbAfterReset.h" +#include "GnbRegisterAccTN.h" +#include "GnbRegistersTN.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNNBAFTERRESET_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +F15TnPmNbAfterResetOnCore ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +TransitionToNbLow ( + IN PCI_ADDR PciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +TransitionToNbHigh ( + IN PCI_ADDR PciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +WaitForNbTransitionToComplete ( + IN PCI_ADDR PciAddress, + IN UINT32 PstateIndex, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Family 15h Trinity core 0 entry point for performing the necessary steps after + * a warm reset has occurred. + * + * The steps are as follows: + * + * 1. Temp1=D18F5x170[SwNbPstateLoDis]. + * 2. Temp2=D18F5x170[NbPstateDisOnP0]. + * 3. Temp3=D18F5x170[NbPstateThreshold]. + * 4. Temp4=D18F5x170[NbPstateGnbSlowDis]. + * 5. If MSRC001_0070[NbPstate]=0, go to step 6. If MSRC001_0070[NbPstate]=1, go to step 11. + * 6. Write 1 to D18F5x170[NbPstateGnbSlowDis]. + * 7. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold]. + * 8. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, CurNb- + * Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo]. + * 9. Set D18F5x170[SwNbPstateLoDis]=1. + * 10. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, CurNb- + * Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. Go to step 15. + * 11. Write 1 to D18F5x170[SwNbPstateLoDis]. + * 12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, CurNb- + * Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. + * 13. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold]. + * 14. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, CurNb- + * Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo]. + * 15. Set D18F5x170[SwNbPstateLoDis]=Temp1, D18F5x170[NbPstateDisOnP0]=Temp2, D18F5x170[NbP- + * stateThreshold]=Temp3, and D18F5x170[NbPstateGnbSlowDis]=Temp4. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] CpuEarlyParamsPtr Service parameters + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +F15TnPmNbAfterReset ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Socket; + UINT32 Module; + UINT32 Core; + UINT32 TaskedCore; + UINT32 Ignored; + AP_TASK TaskPtr; + PCI_ADDR PciAddress; + AGESA_STATUS IgnoredSts; + LOCATE_HEAP_PTR Locate; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnPmNbAfterReset\n"); + + IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); + + ASSERT (Core == 0); + + if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, &CpuEarlyParamsPtr->PlatformConfig, StdHeader)) { + PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR; + Locate.BufferHandle = AMD_CPU_NB_PSTATE_FIXUP_HANDLE; + if (HeapLocateBuffer (&Locate, StdHeader) == AGESA_SUCCESS) { + LibAmdPciWrite (AccessWidth32, PciAddress, Locate.BufferPtr, StdHeader); + } else { + ASSERT (FALSE); + } + } + + // Launch one core per node. + TaskPtr.FuncAddress.PfApTask = F15TnPmNbAfterResetOnCore; + TaskPtr.DataTransfer.DataSizeInDwords = 0; + TaskPtr.ExeFlags = WAIT_FOR_CORE; + for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { + if (GetGivenModuleCoreRange (Socket, Module, &TaskedCore, &Ignored, StdHeader)) { + if (TaskedCore != 0) { + ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) TaskedCore, &TaskPtr, StdHeader); + } + } + } + ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Family 15h Trinity core 0 entry point for performing the necessary Nb P-state VID adjustment + * after a cold reset has occurred. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] CpuEarlyParamsPtr Service parameters + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +F15TnNbPstateVidAdjustAfterReset ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + BOOLEAN NeitherHiNorLo; + NB_PSTATE_REGISTER NbPsReg; + UINT32 NbPsVid; + UINT32 i; + NB_PSTATE_CTRL_REGISTER NbPsCtrl; + NB_PSTATE_CTRL_REGISTER NbPsCtrlSave; + NB_PSTATE_STS_REGISTER NbPsSts; + CLK_PWR_TIMING_CTRL_5_REGISTER ClkPwrTimgCtrl5; + D0F0xBC_x1F400_STRUCT D0F0xBC_x1F400; + + // Check if D18F5x188[NbOffsetTrim] has been programmed to 01b (-25mV) + PciAddress.AddressValue = CPTC5_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimgCtrl5, StdHeader); + if (ClkPwrTimgCtrl5.NbOffsetTrim == 1) { + return; + } + + // Add 25mV (-4 VID steps) to all VddNb VIDs. + PciAddress.AddressValue = NB_PSTATE_0_PCI_ADDR; + + for (i = 0; i < NM_NB_PS_REG; i++) { + PciAddress.Address.Register = NB_PSTATE_0 + (i * 4); + LibAmdPciRead (AccessWidth32, PciAddress, &NbPsReg, StdHeader); + if (NbPsReg.NbPstateEn == 1) { + NbPsVid = GetF15TnNbVid (&NbPsReg); + NbPsVid -= 4; + SetF15TnNbVid (&NbPsReg, &NbPsVid); + LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsReg, StdHeader); + } + } + + // Check if D18F5x174[CurNbPstate] equals NbPstateHi or NbPstateLo + PciAddress.Address.Register = NB_PSTATE_STATUS; + LibAmdPciRead (AccessWidth32, PciAddress, &NbPsSts, StdHeader); + PciAddress.Address.Register = NB_PSTATE_CTRL; + LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); + // Save NB P-state control setting + NbPsCtrlSave = NbPsCtrl; + + // Force a NB P-state Transition. + NeitherHiNorLo = FALSE; + if (NbPsSts.CurNbPstate == NbPsCtrl.NbPstateHi) { + TransitionToNbLow (PciAddress, StdHeader); + } else if (NbPsSts.CurNbPstate == NbPsCtrl.NbPstateLo) { + TransitionToNbHigh (PciAddress, StdHeader); + } else { + NeitherHiNorLo = TRUE; + } + + // Set OffsetTrim to -25mV: + // D18F5x188[NbOffsetTrim]=01b (-25mV) + // D0F0xBC_x1F400[SviLoadLineOffsetVddNB]=01b (-25mV) + PciAddress.Address.Register = CPTC5_REG; + LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimgCtrl5, StdHeader); + ClkPwrTimgCtrl5.NbOffsetTrim = 1; + LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimgCtrl5, StdHeader); + + GnbRegisterReadTN (D0F0xBC_x1F400_TYPE, D0F0xBC_x1F400_ADDRESS, &D0F0xBC_x1F400, 0, StdHeader); + D0F0xBC_x1F400.Field.SviLoadLineOffsetVddNB = 1; + GnbRegisterWriteTN (D0F0xBC_x1F400_TYPE, D0F0xBC_x1F400_ADDRESS, &D0F0xBC_x1F400, 0, StdHeader); + + // Unforce NB P-state back to CurNbPstate value upon entry. + if (NeitherHiNorLo || (NbPsSts.CurNbPstate == NbPsCtrl.NbPstateHi)) { + TransitionToNbHigh (PciAddress, StdHeader); + } else { + // if (NbPsSts.CurNbPstate == NbPsCtrl.NbPstateLo) + TransitionToNbLow (PciAddress, StdHeader); + } + + // Restore NB P-state control setting + PciAddress.Address.Register = NB_PSTATE_CTRL; + NbPsCtrl = NbPsCtrlSave; + LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); +} + + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Support routine for F15TnPmNbAfterReset to perform MSR initialization on one + * core of each die in a family 15h socket. + * + * This function implements steps 1 - 15 on each core. + * + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +STATIC +F15TnPmNbAfterResetOnCore ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 NbPsCtrlOnEntry; + UINT32 NbPsCtrlOnExit; + UINT64 LocalMsrRegister; + PCI_ADDR PciAddress; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnPmNbAfterResetOnCore\n"); + + // 1. Temp1 = D18F5x170[SwNbPstateLoDis]. + // 2. Temp2 = D18F5x170[NbPstateDisOnP0]. + // 3. Temp3 = D18F5x170[NbPstateThreshold]. + // 4. Temp4 = D18F5x170[NbPstateGnbSlowDis]. + PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnEntry, StdHeader); + + // Check if NB P-states were disabled, and if so, prevent any changes from occurring. + if (((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->SwNbPstateLoDis == 0) { + // 5. If MSRC001_0070[NbPstate] = 1, go to step 11 + LibAmdMsrRead (MSR_COFVID_CTL, &LocalMsrRegister, StdHeader); + if (((COFVID_CTRL_MSR *) &LocalMsrRegister)->NbPstate == 0) { + // 6. Write 1 to D18F5x170[NbPstateGnbSlowDis]. + PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader); + ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateGnbSlowDis = 1; + LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader); + + // 7. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold]. + // 8. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, + // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo]. + TransitionToNbLow (PciAddress, StdHeader); + + // 9. Set D18F5x170[SwNbPstateLoDis] = 1. + // 10. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, + // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. + // Go to step 15. + TransitionToNbHigh (PciAddress, StdHeader); + } else { + // 11. Set D18F5x170[SwNbPstateLoDis] = 1. + // 12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, + // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. + TransitionToNbHigh (PciAddress, StdHeader); + + // 13. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold]. + // 14. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, + // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo]. + TransitionToNbLow (PciAddress, StdHeader); + } + + // 15. Set D18F5x170[SwNbPstateLoDis]=Temp1, D18F5x170[NbPstateDisOnP0]=Temp2, D18F5x170[NbP- + // stateThreshold]=Temp3, and D18F5x170[NbPstateGnbSlowDis]=Temp4. + LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader); + ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->SwNbPstateLoDis = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->SwNbPstateLoDis; + ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateDisOnP0 = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateDisOnP0; + ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateThreshold = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateThreshold; + ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateGnbSlowDis = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateGnbSlowDis; + LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader); + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Support routine for F15TnPmNbAfterResetOnCore to transition to the low NB P-state. + * + * This function implements steps 7, 8, 13, and 14 as needed. + * + * @param[in] PciAddress Segment, bus, device number of the node to transition. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +STATIC +TransitionToNbLow ( + IN PCI_ADDR PciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + NB_PSTATE_CTRL_REGISTER NbPsCtrl; + + IDS_HDT_CONSOLE (CPU_TRACE, " TransitionToNbLow\n"); + + // 7/13. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold]. + PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); + NbPsCtrl.SwNbPstateLoDis = 0; + NbPsCtrl.NbPstateDisOnP0 = 0; + NbPsCtrl.NbPstateThreshold = 0; + LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); + + // 8/14. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, + // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo]. + WaitForNbTransitionToComplete (PciAddress, NbPsCtrl.NbPstateLo, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Support routine for F15TnPmNbAfterResetOnCore to transition to the high NB P-state. + * + * This function implements steps 9, 10, 11, and 12 as needed. + * + * @param[in] PciAddress Segment, bus, device number of the node to transition. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +STATIC +TransitionToNbHigh ( + IN PCI_ADDR PciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + NB_PSTATE_CTRL_REGISTER NbPsCtrl; + + IDS_HDT_CONSOLE (CPU_TRACE, " TransitionToNbHigh\n"); + + // 9/10. Set D18F5x170[SwNbPstateLoDis] = 1. + PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); + NbPsCtrl.SwNbPstateLoDis = 1; + LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); + + // 11/12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, + // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. + WaitForNbTransitionToComplete (PciAddress, NbPsCtrl.NbPstateHi, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Support routine for F15TnPmAfterResetCore to wait for NB FID and DID to + * match a specific P-state. + * + * This function implements steps 8, 10, 12, and 14 as needed. + * + * @param[in] PciAddress Segment, bus, device number of the node to transition. + * @param[in] PstateIndex P-state settings to match. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +STATIC +WaitForNbTransitionToComplete ( + IN PCI_ADDR PciAddress, + IN UINT32 PstateIndex, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + NB_PSTATE_REGISTER TargetNbPs; + NB_PSTATE_STS_REGISTER NbPsSts; + + IDS_HDT_CONSOLE (CPU_TRACE, " WaitForNbTransitionToComplete\n"); + + PciAddress.Address.Function = FUNC_5; + PciAddress.Address.Register = NB_PSTATE_0 + (PstateIndex << 2); + LibAmdPciRead (AccessWidth32, PciAddress, &TargetNbPs, StdHeader); + PciAddress.Address.Register = NB_PSTATE_STATUS; + do { + LibAmdPciRead (AccessWidth32, PciAddress, &NbPsSts, StdHeader); + } while ((NbPsSts.CurNbPstate != PstateIndex || + (NbPsSts.CurNbFid != TargetNbPs.NbFid)) || + (NbPsSts.CurNbDid != TargetNbPs.NbDid)); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.h new file mode 100644 index 0000000..8fe1fdf --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.h @@ -0,0 +1,112 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity after warm reset sequence for NB P-states + * + * Contains code that provide power management functionality + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_F15_TN_NB_AFTER_RESET_H_ +#define _CPU_F15_TN_NB_AFTER_RESET_H_ + + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ +VOID +F15TnPmNbAfterReset ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +F15TnNbPstateVidAdjustAfterReset ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif // _CPU_F15_TN_NB_AFTER_RESET_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.c new file mode 100644 index 0000000..8d050b0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.c @@ -0,0 +1,486 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Tn P-State power check + * + * Performs the "Processor-Systemboard Power Delivery Compatibility Check" as + * described in the BKDG. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "cpuRegisters.h" +#include "cpuApicUtilities.h" +#include "cpuFamilyTranslation.h" +#include "cpuF15PowerCheck.h" +#include "cpuF15TnPowerCheck.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "OptionMultiSocket.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNPOWERCHECK_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +F15TnPmPwrCheckCore ( + IN VOID *ErrorData, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +F15TnPmPwrChkCopyPstate ( + IN UINT8 Dest, + IN UINT8 Src, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; +/*---------------------------------------------------------------------------------------*/ +/** + * Family 15h core 0 entry point for performing the family 15h Processor- + * Systemboard Power Delivery Check. + * + * The steps are as follows: + * 1. Starting with P0, loop through all P-states until a passing state is + * found. A passing state is one in which the current required by the + * CPU is less than the maximum amount of current that the system can + * provide to the CPU. If P0 is under the limit, no further action is + * necessary. + * 2. If at least one P-State is under the limit & at least one P-State is + * over the limit, the BIOS must: + * a. If the processor's current P-State is disabled by the power check, + * then the BIOS must request a transition to an enabled P-state + * using MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate] + * to reflect the new value. + * b. Copy the contents of the enabled P-state MSRs to the highest + * performance P-state locations. + * c. Request a P-state transition to the P-state MSR containing the + * COF/VID values currently applied. + * d. If a subset of boosted P-states are disabled, then copy the contents + * of the highest performance boosted P-state still enabled to the + * boosted P-states that have been disabled. + * e. If all boosted P-states are disabled, then program D18F4x15C[BoostSrc] + * to zero. + * f. Adjust the following P-state parameters affected by the P-state + * MSR copy by subtracting the number of P-states that are disabled + * by the power check. + * 1. F3x64[HtcPstateLimit] + * 2. F3x68[SwPstateLimit] + * 3. F3xDC[PstateMaxVal] + * 3. If all P-States are over the limit, the BIOS must: + * a. If the processor's current P-State is !=F3xDC[PstateMaxVal], then + * write F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] and wait for + * MSRC001_0063[CurPstate] to reflect the new value. + * b. If MSRC001_0061[PstateMaxVal]!=000b, copy the contents of the P-state + * MSR pointed to by F3xDC[PstateMaxVal] to the software P0 MSR. + * Write 000b to MSRC001_0062[PstateCmd] and wait for MSRC001_0063 + * [CurPstate] to reflect the new value. + * c. Adjust the following P-state parameters to zero: + * 1. F3x64[HtcPstateLimit] + * 2. F3x68[SwPstateLimit] + * 3. F3xDC[PstateMaxVal] + * d. Program D18F4x15C[BoostSrc] to zero. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] CpuEarlyParams Service parameters + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +F15TnPmPwrCheck ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 DisPsNum; + UINT8 PsMaxVal; + UINT8 Pstate; + UINT32 ProcIddMax; + UINT32 LocalPciRegister; + UINT32 Socket; + UINT32 Module; + UINT32 Core; + UINT32 AndMask; + UINT32 OrMask; + UINT32 PstateLimit; + PCI_ADDR PciAddress; + UINT64 LocalMsrRegister; + AP_TASK TaskPtr; + AGESA_STATUS IgnoredSts; + PWRCHK_ERROR_DATA ErrorData; + UINT32 NumModules; + UINT32 HighCore; + UINT32 LowCore; + UINT32 ModuleIndex; + NB_CAPS_REGISTER NbCaps; + HTC_REGISTER HtcReg; + CLK_PWR_TIMING_CTRL2_REGISTER ClkPwrTimingCtrl2; + + // update PstateMaxVal if warranted by HtcPstateLimit + PciAddress.AddressValue = NB_CAPS_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader); // D18F3xE8 + if (NbCaps.HtcCapable == 1) { + PciAddress.AddressValue = (MAKE_SBDFO (0, 0, 0x18, FUNC_3, HTC_REG)); + LibAmdPciRead (AccessWidth32, PciAddress, &HtcReg, StdHeader); // D18F3x64 + if (HtcReg.HtcTmpLmt != 0) { + PciAddress.AddressValue = CPTC2_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); // D18F3xDC + if (HtcReg.HtcPstateLimit > ClkPwrTimingCtrl2.PstateMaxVal) { + ClkPwrTimingCtrl2.PstateMaxVal = HtcReg.HtcPstateLimit; + LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); // D18F3xDC + } + } + } + + // get the socket number + IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); + ErrorData.SocketNumber = (UINT8) Socket; + + ASSERT (Core == 0); + + // get the Max P-state value + for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) { + LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &LocalMsrRegister, StdHeader); + if (((F15_PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) { + break; + } + } + + ErrorData.HwPstateNumber = (UINT8) (PsMaxVal + 1); + + // Starting with P0, loop through all P-states until a passing state is + // found. A passing state is one in which the current required by the + // CPU is less than the maximum amount of current that the system can + // provide to the CPU. If P0 is under the limit, no further action is + // necessary. + DisPsNum = 0; + for (Pstate = 0; Pstate < ErrorData.HwPstateNumber; Pstate++) { + if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, Pstate, &ProcIddMax, StdHeader)) { + if (ProcIddMax > CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit) { + // Add to event log the Pstate that exceeded the current limit + PutEventLog (AGESA_WARNING, + CPU_EVENT_PM_PSTATE_OVERCURRENT, + Socket, Pstate, 0, 0, StdHeader); + DisPsNum++; + } else { + break; + } + } + } + + ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisPsNum); + + if (ErrorData.AllowablePstateNumber == 0) { + PutEventLog (AGESA_FATAL, + CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT, + Socket, 0, 0, 0, StdHeader); + } + + if (DisPsNum != 0) { + GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); + PciAddress.Address.Function = FUNC_4; + PciAddress.Address.Register = CPB_CTRL_REG; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F4x15C + ErrorData.NumberOfBoostStates = (UINT8) ((F15_CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates; + + if (DisPsNum >= ErrorData.NumberOfBoostStates) { + // If all boosted P-states are disabled, then program D18F4x15C[BoostSrc] to zero. + AndMask = 0xFFFFFFFF; + ((F15_CPB_CTRL_REGISTER *) &AndMask)->BoostSrc = 0; + OrMask = 0x00000000; + OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F4x15C + + ErrorData.NumberOfSwPstatesDisabled = DisPsNum - ErrorData.NumberOfBoostStates; + } else { + ErrorData.NumberOfSwPstatesDisabled = 0; + } + + NumModules = GetPlatformNumberOfModules (); + + // Only execute this loop if this is an MCM. + if (NumModules > 1) { + + // Since the P-State MSRs are shared across a + // node, we only need to set one core in the node for the modified number of supported p-states + // to be reported across all of the cores in the module. + TaskPtr.FuncAddress.PfApTaskI = F15TnPmPwrCheckCore; + TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PWRCHK_ERROR_DATA); + TaskPtr.DataTransfer.DataPtr = &ErrorData; + TaskPtr.DataTransfer.DataTransferFlags = 0; + TaskPtr.ExeFlags = WAIT_FOR_CORE; + + for (ModuleIndex = 0; ModuleIndex < NumModules; ModuleIndex++) { + // Execute the P-State reduction code on the module's primary core only. + // Skip this code for the BSC's module. + if (ModuleIndex != Module) { + if (GetGivenModuleCoreRange (Socket, ModuleIndex, &LowCore, &HighCore, StdHeader)) { + ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)LowCore, &TaskPtr, StdHeader); + } + } + } + } + + // Path for SCM and the BSC + F15TnPmPwrCheckCore (&ErrorData, StdHeader); + + // Final Step + // F3x64[HtPstatelimit] -= disPsNum + // F3x68[SwPstateLimit] -= disPsNum + // F3xDC[PstateMaxVal] -= disPsNum + + PciAddress.Address.Function = FUNC_3; + PciAddress.Address.Register = HTC_REG; + AndMask = 0xFFFFFFFF; + ((HTC_REGISTER *) &AndMask)->HtcPstateLimit = 0; + OrMask = 0x00000000; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x64 + PstateLimit = ((HTC_REGISTER *) &LocalPciRegister)->HtcPstateLimit; + if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) { + PstateLimit -= ErrorData.NumberOfSwPstatesDisabled; + ((HTC_REGISTER *) &OrMask)->HtcPstateLimit = PstateLimit; + } + OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x64 + + PciAddress.Address.Register = SW_PS_LIMIT_REG; + AndMask = 0xFFFFFFFF; + ((SW_PS_LIMIT_REGISTER *) &AndMask)->SwPstateLimit = 0; + OrMask = 0x00000000; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x68 + PstateLimit = ((SW_PS_LIMIT_REGISTER *) &LocalPciRegister)->SwPstateLimit; + if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) { + PstateLimit -= ErrorData.NumberOfSwPstatesDisabled; + ((SW_PS_LIMIT_REGISTER *) &OrMask)->SwPstateLimit = PstateLimit; + } + OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x68 + + PciAddress.Address.Register = CPTC2_REG; + AndMask = 0xFFFFFFFF; + ((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->PstateMaxVal = 0; + OrMask = 0x00000000; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xDC + PstateLimit = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal; + if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) { + PstateLimit -= ErrorData.NumberOfSwPstatesDisabled; + ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->PstateMaxVal = PstateLimit; + } + OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC + } +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Core-level error handler called if any p-states were determined to be out + * of range for the mother board. + * + * This function implements steps 2a-c and 3a-c on each core. + * + * @param[in] ErrorData Details about the error condition. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +STATIC +F15TnPmPwrCheckCore ( + IN VOID *ErrorData, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + UINT8 HwPsMaxVal; + UINT8 SwPsMaxVal; + UINT8 HwDisPsNum; + UINT8 CurrentSwPs; + UINT8 PsDisableCount; + UINT64 LocalMsrRegister; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) { + // P-state MSRs are shared, so only 1 core per compute unit needs to perform this + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + HwPsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1); + HwDisPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - + ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber); + + LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader); + CurrentSwPs = (UINT8) (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate); + LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader); + SwPsMaxVal = (UINT8) (((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal); + PsDisableCount = 0; + + if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) { + // All P-States are over the limit. + + // Step 1 + // Transition to Pstate Max if not there already + if (CurrentSwPs != SwPsMaxVal) { + FamilySpecificServices->TransitionPstate (FamilySpecificServices, SwPsMaxVal, (BOOLEAN) TRUE, StdHeader); + } + + // Step 2 + // If Pstate Max is not P0, copy Pstate max contents to P0 and switch + // to P0. + if (SwPsMaxVal != 0) { + F15TnPmPwrChkCopyPstate (((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates, HwPsMaxVal, StdHeader); + FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader); + } + + // Disable all SW P-states except P0 + PsDisableCount = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled - 1; + } else { + // At least one P-State is under the limit & at least one P-State is + // over the limit. + if (((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates > HwDisPsNum) { + // A subset of boosted P-states are disabled. Copy the contents of the + // highest performance boosted P-state still enabled to the boosted + // P-states that have been disabled. + for (i = 0; i < HwDisPsNum; i++) { + F15TnPmPwrChkCopyPstate (i, HwDisPsNum, StdHeader); + } + } else if (((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled != 0) { + // Move remaining P-state register(s) up + // Step 1 + // Transition to a valid Pstate if current Pstate has been disabled + if (CurrentSwPs < ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled) { + FamilySpecificServices->TransitionPstate (FamilySpecificServices, ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled, (BOOLEAN) TRUE, StdHeader); + CurrentSwPs = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled; + } + + // Step 2 + // Move enabled Pstates up and disable the remainder + for (i = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates; (i + ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled) <= HwPsMaxVal; i++) { + F15TnPmPwrChkCopyPstate (i, (i + ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled), StdHeader); + } + + // Step 3 + // Transition to current COF/VID at shifted location + CurrentSwPs = (CurrentSwPs - ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled); + FamilySpecificServices->TransitionPstate (FamilySpecificServices, CurrentSwPs, (BOOLEAN) TRUE, StdHeader); + + // Disable the appropriate number of P-states + PsDisableCount = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled; + } + } + // Disable the appropriate P-states if any, starting from HW Pmin + for (i = 0; i < PsDisableCount; i++) { + FamilySpecificServices->DisablePstate (FamilySpecificServices, (HwPsMaxVal - i), StdHeader); + } + } +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Copies the contents of one P-State MSR to another. + * + * @param[in] Dest Destination p-state number + * @param[in] Src Source p-state number + * @param[in] StdHeader Config handle for library and services + * + */ +VOID +STATIC +F15TnPmPwrChkCopyPstate ( + IN UINT8 Dest, + IN UINT8 Src, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 LocalMsrRegister; + + LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &LocalMsrRegister, StdHeader); + LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &LocalMsrRegister, StdHeader); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.h new file mode 100644 index 0000000..a9d940c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.h @@ -0,0 +1,102 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 TN Power related functions and structures + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_F15_TN_POWER_CHECK_H_ +#define _CPU_F15_TN_POWER_CHECK_H_ + + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ +VOID +F15TnPmPwrCheck ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif // _CPU_F15_TN_POWER_CHECK_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerMgmt.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerMgmt.h new file mode 100644 index 0000000..f192c19 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerMgmt.h @@ -0,0 +1,609 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity Power Management related registers defination + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e $Revision: 63661 $ @e $Date: 2012-01-03 01:02:47 -0600 (Tue, 03 Jan 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_F15_TN_POWERMGMT_H_ +#define _CPU_F15_TN_POWERMGMT_H_ + +/* + * Family 15h Trinity CPU Power Management MSR definitions + * + */ + + +/* Interrupt Pending and CMP-Halt MSR Register 0xC0010055 */ +#define MSR_INTPEND 0xC0010055ul + +/// Interrupt Pending and CMP-Halt MSR Register +typedef struct { + UINT64 IoMsgAddr:16; ///< IO message address + UINT64 Intpend1 :8; + UINT64 Intpend2 :1; + UINT64 Intpend3 :1; + UINT64 Intpend4 :1; + UINT64 :37; ///< Reserved +} INTPEND_MSR; + +/* P-state Registers 0xC00100[6B:64] */ + +/// P-state MSR +typedef struct { + UINT64 CpuFid:6; ///< CpuFid + UINT64 CpuDid:3; ///< CpuDid + UINT64 CpuVid:8; ///< CpuVid + UINT64 :5; ///< Reserved + UINT64 NbPstate:1; ///< NbPstate + UINT64 :9; ///< Reserved + UINT64 IddValue:8; ///< IddValue + UINT64 IddDiv:2; ///< IddDiv + UINT64 :21; ///< Reserved + UINT64 PsEnable:1; ///< Pstate Enable +} PSTATE_MSR; + +#define GetF15TnCpuVid(PstateMsr) (((PSTATE_MSR *) PstateMsr)->CpuVid) + + +/* VID operation related macros */ +#define ConvertVidInuV(Vid) (1550000 - (6250 * Vid)) ///< Convert VID in uV. + +/* COFVID Control Register 0xC0010070 */ +#define MSR_COFVID_CTL 0xC0010070ul + +/// COFVID Control MSR Register +typedef struct { + UINT64 CpuFid:6; ///< CpuFid + UINT64 CpuDid:3; ///< CpuDid + UINT64 CpuVid_6_0:7; ///< CpuVid[6:0] + UINT64 PstateId:3; ///< Pstate ID + UINT64 :1; ///< Reserved + UINT64 CpuVid_7:1; ///< CpuVid[7] + UINT64 :1; ///< Reserved + UINT64 NbPstate:1; ///< Northbridge P-state + UINT64 :1; ///< Reserved + UINT64 NbVid:8; ///< NbVid + UINT64 :32; ///< Reserved +} COFVID_CTRL_MSR; + +#define COFVID_CTRL_MSR_CurCpuVid_6_0_OFFSET 9 +#define COFVID_CTRL_MSR_CurCpuVid_6_0_WIDTH 7 +#define COFVID_CTRL_MSR_CurCpuVid_6_0_MASK 0xfe00 +#define COFVID_CTRL_MSR_CurCpuVid_7_OFFSET 20 +#define COFVID_CTRL_MSR_CurCpuVid_7_WIDTH 1 +#define COFVID_CTRL_MSR_CurCpuVid_7_MASK 0x100000ul + +/* SVI VID Encoding */ + +///< Union structure of VID in SVI1/SVI2 modes +typedef union { + UINT32 RawVid; ///< Raw VID value + struct { ///< SVI2 mode VID structure + UINT32 Vid_6_0:7; ///< Vid[6:0] of SVI2 mode + UINT32 Vid_7:1; ///< Vid[7] of SVI2 mode + } SVI2; + struct { ///< SVI1 mode VID structure + UINT32 Vid_LSB_Ignore:1; ///< Ignored LSB of 8bit VID encoding in SVI1 mode + UINT32 Vid_6_0:1; ///< Vid[6:0] of SVI mode + } SVI1; +} SVI_VID; + + +#define SetF15TnCpuVid(CofVidStsMsr, NewCpuVid) ( \ + ((COFVID_CTRL_MSR *) CofVidStsMsr)->CurCpuVid_6_0) = ((SVI_VID *) NewCpuVid)->SVI2.Vid_6_0; \ + ((COFVID_CTRL_MSR *) CofVidStsMsr)->CurCpuVid_7) = ((SVI_VID *) NewCpuVid)->SVI2.Vid_7; \ +) + + +/* COFVID Status Register 0xC0010071 */ +#define MSR_COFVID_STS 0xC0010071ul + +/// COFVID Status MSR Register +typedef struct { + UINT64 CurCpuFid:6; ///< Current CpuFid + UINT64 CurCpuDid:3; ///< Current CpuDid + UINT64 CurCpuVid_6_0:7; ///< Current CpuVid[6:0] + UINT64 CurPstate:3; ///< Current Pstate + UINT64 :1; ///< Reserved + UINT64 CurCpuVid_7:1; ///< Current CpuVid[7] + UINT64 :2; ///< Reserved + UINT64 NbPstateDis:1; ///< NbPstate Disable + UINT64 CurNbVid:8; ///< Current NbVid[7:0] <<<------- check where use it + UINT64 StartupPstate:3; ///< Startup Pstate + UINT64 :14; ///< Reserved + UINT64 MaxCpuCof:6; ///< MaxCpuCof + UINT64 :1; ///< Reserved + UINT64 CurPstateLimit:3; ///< Current Pstate Limit + UINT64 MaxNbCof:5; ///< MaxNbCof +} COFVID_STS_MSR; + +#define COFVID_STS_MSR_CurCpuVid_6_0_OFFSET 9 +#define COFVID_STS_MSR_CurCpuVid_6_0_WIDTH 7 +#define COFVID_STS_MSR_CurCpuVid_6_0_MASK 0xfe00 +#define COFVID_STS_MSR_CurCpuVid_7_OFFSET 20 +#define COFVID_STS_MSR_CurCpuVid_7_WIDTH 1 +#define COFVID_STS_MSR_CurCpuVid_7_MASK 0x100000ul + +#define GetF15TnCurCpuVid(CofVidStsMsr) ( \ + (((COFVID_STS_MSR *) CofVidStsMsr)->CurCpuVid_7 << COFVID_STS_MSR_CurCpuVid_6_0_WIDTH) \ + | ((COFVID_STS_MSR *) CofVidStsMsr)->CurCpuVid_6_0) + + +/* Floating Point Configuration Register 0xC0011028 */ +#define MSR_FP_CFG 0xC0011028ul + +/// Floating Point Configuration MSR Register +typedef struct { + UINT64 :16; ///< Reserved + UINT64 DiDtMode:1; ///< Di/Dt Mode + UINT64 :1; ///< Reserved + UINT64 DiDtCfg0:5; ///< Di/Dt Config 0 + UINT64 :2; ///< Reserved + UINT64 DiDtCfg2:2; ///< Di/Dt Config 2 + UINT64 DiDtCfg1:8; ///< Di/Dt Config 1 + UINT64 :6; ///< Reserved + UINT64 DiDtCfg5:1; ///< Di/Dt Config 5 + UINT64 DiDtCfg4:3; ///< Di/Dt Config 4 + UINT64 :19; ///< Reserved +} FP_CFG_MSR; + +/* Load-Store Configuration 2 0xC001102D */ + +/// Load-Store Configuration 2 MSR Register +typedef struct { + UINT64 :14; ///< Reserved + UINT64 ForceSmcCheckFlwStDis:1; ///< ForceSmcCheckFlwStDis + UINT64 :8; ///< Reserved + UINT64 DisScbThreshold:1; ///< DisScbThreshold + UINT64 :40; ///< Reserved +} LS_CFG2_MSR; + +/* + * Family 15h Trinity CPU Power Management PCI definitions + * + */ + + +/* DRAM Configuration High Register F2x[1,0]94 */ +#define DRAM_CFG_HI_REG0 0x94 +#define DRAM_CFG_HI_REG1 0x194 + +/// DRAM Configuration High PCI Register +typedef struct { + UINT32 MemClkFreq:5; ///< Memory clock frequency + UINT32 :2; ///< Reserved + UINT32 MemClkFreqVal:1; ///< Memory clock frequency valid + UINT32 :2; ///< Reserved + UINT32 ZqcsInterval:2; ///< ZQ calibration short interval + UINT32 :2; ///< Reserved + UINT32 DisDramInterface:1; ///< Disable the DRAM interface + UINT32 PowerDownEn:1; ///< Power down mode enable + UINT32 PowerDownMode:1; ///< Power down mode + UINT32 :2; ///< Reserved + UINT32 DcqArbBypassEn:1; ///< DRAM controller arbiter bypass enable + UINT32 SlowAccessMode:1; ///< Slow access mode + UINT32 FreqChgInProg:1; ///< Frequency change in progress + UINT32 BankSwizzleMode:1; ///< Bank swizzle mode + UINT32 ProcOdtDis:1; ///< Processor on-die termination disable + UINT32 DcqBypassMax:5; ///< DRAM controller queue bypass maximum + UINT32 :3; ///< Reserved +} DRAM_CFG_HI_REGISTER; + +/* DCT Configuration Select D18F1x10C */ +#define DCT_CFG_SEL_REG 0x10C +#define DCT_CFG_SEL_REG_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_1, DCT_CFG_SEL_REG)) + +/// DCT Configuration Select +typedef struct { + UINT32 DctCfgSel:1; ///< DRAM controller configuration select + UINT32 :31; ///< Reserved +} DCT_CFG_SEL_REGISTER; + + +/* GMC to DCT Control 2 D18F2x408_dct[1:0] */ +#define GMC_TO_DCT_CTL_2_REG 0x408 +#define GMC_TO_DCT_CTL_2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_2, GMC_TO_DCT_CTL_2_REG)) + +/// GMC to DCT Control 2 PCI Register +typedef struct { + UINT32 CpuElevPrioDis:1; ///< Cpu elevate priority disable + UINT32 :31; ///< Reserved +} GMC_TO_DCT_CTL_2_REGISTER; + + +/* Power Control Miscellaneous Register F3xA0 */ +#define PW_CTL_MISC_REG 0xA0 +#define PW_CTL_MISC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, PW_CTL_MISC_REG)) + +/// Power Control Miscellaneous PCI Register +typedef struct { + UINT32 PsiVid:7; ///< PSI_L VID threshold VID[6:0] + UINT32 PsiVidEn:1; ///< PSI_L VID enable + UINT32 PsiVid_7:1; ///< PSI_L VID threshold VID[7] + UINT32 :2; ///< Reserved + UINT32 PllLockTime:3; ///< PLL synchronization lock time + UINT32 Svi2HighFreqSel:1; ///< SVI2 high frequency select + UINT32 :1; ///< Reserved + UINT32 ConfigId:12; ///< Configuration ID + UINT32 :3; ///< Reserved + UINT32 CofVidProg:1; ///< COF and VID of Pstate programmed +} POWER_CTRL_MISC_REGISTER; + + +/* Clock Power/Timing Control 0 Register F3xD4 */ +#define CPTC0_REG 0xD4 +#define CPTC0_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC0_REG)) + +/// Clock Power Timing Control PCI Register +typedef struct { + UINT32 MaxSwPstateCpuCof:6; ///< Maximum software P-state core COF + UINT32 :2; ///< Reserved + UINT32 ClkRampHystSel:4; ///< Clock Ramp Hysteresis Select + UINT32 ClkRampHystCtl:1; ///< Clock Ramp Hysteresis Control + UINT32 :1; ///< Reserved + UINT32 CacheFlushImmOnAllHalt:1; ///< Cache Flush Immediate on All Halt + UINT32 :1; ///< Reserved + UINT32 clkpwr0 :2; + UINT32 :2; ///< Reserved + UINT32 PowerStepDown:4; ///< Power Step Down + UINT32 PowerStepUp:4; ///< Power Step Up + UINT32 NbClkDiv:3; ///< NbClkDiv + UINT32 NbClkDivApplyAll:1; ///< NbClkDivApplyAll +} CLK_PWR_TIMING_CTRL_REGISTER; + + +/* Clock Power/Timing Control 1 Register F3xD8 */ +#define CPTC1_REG 0xD8 +#define CPTC1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC1_REG)) + +/// Clock Power Timing Control 1 PCI Register +typedef struct { + UINT32 :4; ///< Reserved + UINT32 VSRampSlamTime:3; ///< Voltage stabilization ramp time + UINT32 :25; ///< Reserved +} CLK_PWR_TIMING_CTRL1_REGISTER; + + +/* Northbridge Capabilities Register F3xE8 */ +#define NB_CAPS_REG 0xE8 +#define NB_CAPS_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, NB_CAPS_REG)) + +/// Northbridge Capabilities PCI Register +typedef struct { + UINT32 :1; ///< Reserved + UINT32 DualNode:1; ///< Dual-node multi-processor capable + UINT32 EightNode:1; ///< Eight-node multi-processor capable + UINT32 Ecc:1; ///< ECC capable + UINT32 Chipkill:1; ///< Chipkill ECC capable + UINT32 :3; ///< Reserved + UINT32 MctCap:1; ///< Memory controller capable + UINT32 SvmCapable:1; ///< SVM capable + UINT32 HtcCapable:1; ///< HTC capable + UINT32 :3; ///< Reserved + UINT32 MultVidPlane:1; ///< Multiple VID plane capable + UINT32 :4; ///< Reserved + UINT32 x2Apic:1; ///< x2Apic capability + UINT32 :4; ///< Reserved + UINT32 MemPstateCap:1; ///< Memory P-state capable + UINT32 L3Capable:1; ///< L3 capable + UINT32 :6; ///< Reserved +} NB_CAPS_REGISTER; + + +/* Product Info Register F3x1FC */ +#define PRCT_INFO_REG 0x1FC +#define PRCT_INFO_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, PRCT_INFO_REG)) + +/// Product Information PCI Register +typedef struct { + UINT32 DiDtMode:1; ///< DiDtMode + UINT32 DiDtCfg0:5; ///< DiDtCfg0 + UINT32 DiDtCfg1:8; ///< DiDtCfg1 + UINT32 DiDtCfg2:2; ///< DiDtCfg2 + UINT32 :1; ///< Reserved + UINT32 DiDtCfg4:3; ///< DiDtCfg4 + UINT32 EnCstateBoostBlockCC6Exit:1;///< EnCstateBoostBlockCC6Exit + UINT32 :1; ///< Reserved + UINT32 DiDtCfg5:1; ///< DiDtCfg5 + UINT32 ForceSmcCheckFlwStDis:1; ///< ForceSmcCheckFlwStDis + UINT32 SWDllCapTableEn:1; ///< SWDllCapTableEn + UINT32 DllProcessFreqCtlIndex2Rate50:4; ///< DllProcessFreqCtlIndex2Rate50 + UINT32 EnDcqChgPriToHigh:1; ///< EnDcqChgPriToHigh + UINT32 :2; ///< Reserved +} PRODUCT_INFO_REGISTER; + + +/* C-state Control 1 Register D18F4x118 */ +#define CSTATE_CTRL1_REG 0x118 +#define CSTATE_CTRL1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_CTRL1_REG)) + +/// C-state Control 1 Register +typedef struct { + UINT32 CpuPrbEnCstAct0:1; ///< Core direct probe enable + UINT32 CacheFlushEnCstAct0:1; ///< Cache flush enable + UINT32 CacheFlushTmrSelCstAct0:2; ///< Cache flush timer select + UINT32 :1; ///< Reserved + UINT32 ClkDivisorCstAct0:3; ///< Clock divisor + UINT32 PwrGateEnCstAct0:1; ///< Power gate enable + UINT32 PwrOffEnCstAct0:1; ///< C-state action field 3 + UINT32 NbPwrGate0:1; ///< NB power-gating 0 + UINT32 NbClkGate0:1; ///< NB clock-gating 0 + UINT32 SelfRefr0:1; ///< Self-refresh 0 + UINT32 SelfRefrEarly0:1; ///< Allow early self-refresh 0 + UINT32 :2; ///< Reserved + UINT32 CpuPrbEnCstAct1:1; ///< Core direct probe enable + UINT32 CacheFlushEnCstAct1:1; ///< Cache flush eable + UINT32 CacheFlushTmrSelCstAct1:2; ///< Cache flush timer select + UINT32 :1; ///< Reserved + UINT32 ClkDivisorCstAct1:3; ///< Clock divisor + UINT32 PwrGateEnCstAct1:1; ///< Power gate enable + UINT32 PwrOffEnCstAct1:1; ///< C-state action field 3 + UINT32 NbPwrGate1:1; ///< NB power-gating 1 + UINT32 NbClkGate1:1; ///< NB clock-gating 1 + UINT32 SelfRefr1:1; ///< Self-refresh 1 + UINT32 SelfRefrEarly1:1; ///< Allow early self-refresh 1 + UINT32 :2; ///< Reserved +} CSTATE_CTRL1_REGISTER; + + +/* C-state Control 2 Register D18F4x11C */ +#define CSTATE_CTRL2_REG 0x11C +#define CSTATE_CTRL2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_CTRL2_REG)) + +/// C-state Control 2 Register +typedef struct { + UINT32 CpuPrbEnCstAct2:1; ///< Core direct probe enable + UINT32 CacheFlushEnCstAct2:1; ///< Cache flush eable + UINT32 CacheFlushTmrSelCstAct2:2; ///< Cache flush timer select + UINT32 cstate0 :1; + UINT32 ClkDivisorCstAct2:3; ///< Clock divisor + UINT32 PwrGateEnCstAct2:1; ///< Power gate enable + UINT32 PwrOffEnCstAct2:1; ///< C-state action field 3 + UINT32 NbPwrGate2:1; ///< NB power-gating 2 + UINT32 NbClkGate2:1; ///< NB clock-gating 2 + UINT32 SelfRefr2:1; ///< Self-refresh 2 + UINT32 SelfRefrEarly2:1; ///< Allow early self-refresh 2 + UINT32 :18; ///< Reserved +} CSTATE_CTRL2_REGISTER; + + +/* Cstate Policy Control 1 Register D18F4x128 */ +#define CSTATE_POLICY_CTRL1_REG 0x128 +#define CSTATE_POLICY_CTRL1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_POLICY_CTRL1_REG)) + +/// Cstate Policy Control 1 Register +typedef struct { + UINT32 cstplyc0 :1; + UINT32 CoreCstatePolicy:1; ///< Specified processor arbitration of voltage and frequency + UINT32 HaltCstateIndex:3; ///< Specifies the IO-based C-state that is invoked by a HLT instruction + UINT32 CacheFlushTmr:7; ///< Cache flush timer + UINT32 :6; ///< Reserved + UINT32 CacheFlushSucMonThreshold:3; ///< Cache flush success monitor threshold + UINT32 :10; ///< Reserved + UINT32 CstateMsgDis:1; ///< C-state messaging disable +} CSTATE_POLICY_CTRL1_REGISTER; + + +/* Core Performance Boost Control Register D18F4x15C */ + +/// Core Performance Boost Control Register +typedef struct { + UINT32 BoostSrc:2; ///< Boost source + UINT32 NumBoostStates:3; ///< Number of boosted states + UINT32 :2; ///< Reserved + UINT32 ApmMasterEn:1; ///< APM master enable + UINT32 :23; ///< Reserved + UINT32 BoostLock:1; ///< +} CPB_CTRL_REGISTER; + + +/* Northbridge Capabilities 2 F5x84*/ +#define NB_CAPS_REG2 0x84 +#define NB_CAPS_REG2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_CAPS_REG2)) + +/// Northbridge Capabilities 2 PCI Register +typedef struct { + UINT32 CmpCap:8; ///< CMP capable + UINT32 :4; ///< Reserved + UINT32 DctEn:2; ///< DCT enabled + UINT32 :2; ///< Reserved + UINT32 DdrMaxRate:5; ///< maximum DDR rate + UINT32 :3; ///< Reserved + UINT32 DdrMaxRateEnf:5; ///< enforced maximum DDR rate: + UINT32 :3; ///< Reserved +} NB_CAPS_2_REGISTER; + +/* Northbridge Configuration 4 F5x88*/ +#define NB_CFG_REG4 0x88 +#define NB_CFG_REG4_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_CFG_REG4)) + +/// Northbridge Configuration 4 PCI Register +typedef struct { + UINT32 :2; ///< Reserved + UINT32 IntStpClkHaltExitEn:1; ///< IntStpClkHaltExitEn + UINT32 :11; ///< Reserved + UINT32 Bit14:1; ///< Reserved + UINT32 :3; ///< Reserved + UINT32 EnCstateBoostBlockCC6Exit:1;///< EnCstateBoostBlockCC6Exit + UINT32 :13; ///< Reserved +} NB_CFG_4_REGISTER; + +/* Northbridge P-state [3:0] F5x1[6C:60] */ + +/// Northbridge P-state Register +typedef struct { + UINT32 NbPstateEn:1; ///< NB P-state enable + UINT32 NbFid:6; ///< NB frequency ID + UINT32 NbDid:1; ///< NB divisor ID + UINT32 :2; ///< Reserved + UINT32 NbVid_6_0:7; ///< NB VID[6:0] + UINT32 :1; ///< Reserved + UINT32 MemPstate:1; ///< Memory P-State + UINT32 :2; ///< Reserved + UINT32 NbVid_7:1; ///< NB VID[7] + UINT32 NbIddDiv:2; ///< northbridge current divisor + UINT32 NbIddValue:8; ///< northbridge current value +} NB_PSTATE_REGISTER; + +#define NB_PSTATE_REGISTER_NbVid_6_0_OFFSET 10 +#define NB_PSTATE_REGISTER_NbVid_6_0_WIDTH 7 +#define NB_PSTATE_REGISTER_NbVid_6_0_MASK 0x0001FC00ul +#define NB_PSTATE_REGISTER_NbVid_7_OFFSET 21 +#define NB_PSTATE_REGISTER_NbVid_7_WIDTH 1 +#define NB_PSTATE_REGISTER_NbVid_7_MASK 0x00200000ul + +#define GetF15TnNbVid(NbPstateRegister) ( \ + (((NB_PSTATE_REGISTER *) NbPstateRegister)->NbVid_7 << NB_PSTATE_REGISTER_NbVid_6_0_WIDTH) \ + | ((NB_PSTATE_REGISTER *) NbPstateRegister)->NbVid_6_0) + +#define SetF15TnNbVid(NbPstateRegister, NewNbVid) { \ + ((NB_PSTATE_REGISTER *) NbPstateRegister)->NbVid_6_0 = ((SVI_VID *) NewNbVid)->SVI2.Vid_6_0; \ + ((NB_PSTATE_REGISTER *) NbPstateRegister)->NbVid_7 = ((SVI_VID *) NewNbVid)->SVI2.Vid_7; \ +} + +/* Northbridge P-state Status */ +#define NB_PSTATE_CTRL 0x170 +#define NB_PSTATE_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_CTRL)) + +/// Northbridge P-state Control Register +typedef struct { + UINT32 NbPstateMaxVal:2; ///< NB P-state maximum value + UINT32 :1; ///< Reserved + UINT32 NbPstateLo:2; ///< NB P-state low + UINT32 :1; ///< Reserved + UINT32 NbPstateHi:2; ///< NB P-state high + UINT32 :1; ///< Reserved + UINT32 NbPstateThreshold:3; ///< NB P-state threshold + UINT32 :1; ///< Reserved + UINT32 NbPstateDisOnP0:1; ///< NB P-state disable on P0 + UINT32 SwNbPstateLoDis:1; ///< Software NB P-state low disable + UINT32 :8; ///< Reserved + UINT32 NbPstateGnbSlowDis:1; ///< Disable NB P-state transition take GnbSlow into account. + UINT32 NbPstateLoRes:3; ///< NB P-state low residency timer + UINT32 NbPstateHiRes:3; ///< NB P-state high residency timer + UINT32 :1; ///< Reserved + UINT32 MemPstateDis:1; ///< Memory P-state disable +} NB_PSTATE_CTRL_REGISTER; + + +/* Northbridge P-state Status */ +#define NB_PSTATE_STATUS 0x174 +#define NB_PSTATE_STATUS_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_STATUS)) + +/// Northbridge P-state Status Register +typedef struct { + UINT32 NbPstateDis:1; ///< Nb pstate disable + UINT32 StartupNbPstate:2; ///< startup northbridge Pstate number + UINT32 CurNbFid:6; ///< Current NB FID + UINT32 CurNbDid:1; ///< Current NB DID + UINT32 :2; ///< Reserved + UINT32 CurNbVid_6_0:7; ///< Current NB VID[6:0] + UINT32 CurNbPstate:2; ///< Current NB Pstate + UINT32 :2; ///< Reserved + UINT32 CurNbVid_7:1; ///< Current NB VID[7] + UINT32 CurMemPstate:1; ///< Current memory P-state + UINT32 :7; ///< Reserved +} NB_PSTATE_STS_REGISTER; + +#define NB_PSTATE_STS_REGISTER_CurNbVid_6_0_OFFSET 12 +#define NB_PSTATE_STS_REGISTER_CurNbVid_6_0_WIDTH 7 +#define NB_PSTATE_STS_REGISTER_CurNbVid_6_0_MASK 0x0007F000ul +#define NB_PSTATE_STS_REGISTER_CurNbVid_7_OFFSET 23 +#define NB_PSTATE_STS_REGISTER_CurNbVid_7_WIDTH 1 +#define NB_PSTATE_STS_REGISTER_CurNbVid_7_MASK 0x00800000ul + +#define GetF15TnCurNbVid(NbPstateStsRegister) ( \ + (((NB_PSTATE_STS_REGISTER *) NbPstateStsRegister)->CurNbVid_7 << NB_PSTATE_STS_REGISTER_CurNbVid_6_0_WIDTH) \ + | ((NB_PSTATE_STS_REGISTER *) NbPstateStsRegister)->CurNbVid_6_0) + +/* Miscellaneous Voltages */ +#define MISC_VOLTAGES 0x17C +#define MISC_VOLTAGES_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, MISC_VOLTAGES)) + +/// Miscellaneous Voltages Register +typedef struct { + UINT32 MaxVid:8; ///< Maximum Voltage + UINT32 :2; ///< Reserved + UINT32 MinVid:8; ///< Minimum Voltage + UINT32 :5; ///< Reserved + UINT32 NbPsi0Vid:8; ///< Northbridge PSI0_L VID threshold + UINT32 NbPsi0VidEn:1; ///< Northbridge PSI0_L VID enable +} MISC_VOLTAGE_REGISTER; + + +/* Clock Power/Timing Control 5 Register F5x188 */ +#define CPTC5_REG 0x188 +#define CPTC5_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, CPTC5_REG)) + +/// Clock Power Timing Control 5 Register +typedef struct { + UINT32 NbOffsetTrim:2; ///< Northbridge offset trim + UINT32 NbLoadLineTrim:3; ///< Northbridge load line trim + UINT32 NbPsi1:1; ///< Northbridge PSI1_L + UINT32 :26; ///< Reserved +} CLK_PWR_TIMING_CTRL_5_REGISTER; + +#endif /* _CPU_F15_TN_POWERMGMT_H_ */ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPsi.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPsi.c new file mode 100644 index 0000000..d808c50 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPsi.c @@ -0,0 +1,308 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 TN PSI Initialization + * + * Enables Power Status Indicator (PSI) feature + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e $Revision: 65284 $ @e $Date: 2012-02-12 23:29:39 -0600 (Sun, 12 Feb 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuRegisters.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "cpuFeatures.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "CommonReturns.h" +#include "cpuPsi.h" +#include "OptionMultiSocket.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNPSI_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +STATIC +F15TnPmVrmLowPowerModeEnable ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PCI_ADDR PciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; + +/*---------------------------------------------------------------------------------------*/ +/** + * Entry point for enabling Power Status Indicator + * + * This function must be run after all P-State routines have been executed + * + * @param[in] PsiServices The current CPU's family services. + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config handle for library and services. + * + * @retval AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +STATIC +F15TnInitializePsi ( + IN PSI_FAMILY_SERVICES *PsiServices, + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) { + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0); + // Configure PsiVid + F15TnPmVrmLowPowerModeEnable (FamilySpecificServices, PlatformConfig, PciAddress, StdHeader); + } + + return AGESA_SUCCESS; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Sets up PSI_L operation. + * + * This function implements the LowPowerThreshold parameter. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] PciAddress Segment, bus, device number of the node to transition. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +STATIC +F15TnPmVrmLowPowerModeEnable ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PCI_ADDR PciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PSTATE_MSR PstateMsr; + CLK_PWR_TIMING_CTRL2_REGISTER ClkPwrTimingCtrl2; + POWER_CTRL_MISC_REGISTER PwrCtrlMisc; + UINT32 CoreVrmLowPowerThreshold; + UINT32 Pstate; + UINT32 HwPstateMaxVal; + UINT32 PstateCurrent; + UINT32 NextPstateCurrent; + UINT32 PreviousVid; + UINT32 CurrentVid; + + NB_PSTATE_REGISTER NbPstateReg; + NB_PSTATE_CTRL_REGISTER NbPsCtrl; + MISC_VOLTAGE_REGISTER MiscVoltageReg; + UINT32 NbVrmLowPowerThreshold; + UINT32 NbPstate; + UINT32 NbPstateMaxVal; + UINT32 NbPstateCurrent; + UINT32 NextNbPstateCurrent; + UINT32 PreviousNbVid; + UINT32 CurrentNbVid; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnPmVrmLowPowerModeEnable\n"); + + if (PlatformConfig->VrmProperties[CoreVrm].LowPowerThreshold != 0) { + // Set up PSI0_L for VDD + CoreVrmLowPowerThreshold = PlatformConfig->VrmProperties[CoreVrm].LowPowerThreshold; + IDS_HDT_CONSOLE (CPU_TRACE, " Core VRM - LowPowerThreshold: %d\n", CoreVrmLowPowerThreshold); + PreviousVid = 0xFF; + CurrentVid = 0xFF; + + PciAddress.AddressValue = CPTC2_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); + HwPstateMaxVal = ClkPwrTimingCtrl2.PstateMaxVal; + ASSERT (HwPstateMaxVal < NM_PS_REG); + + IDS_HDT_CONSOLE (CPU_TRACE, " HwPstateMaxVal %d\n", HwPstateMaxVal); + // Check P-state from P0 to HwPstateMaxVal + for (Pstate = 0; Pstate <= HwPstateMaxVal; Pstate++) { + FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) Pstate, &PstateCurrent, StdHeader); + + LibAmdMsrRead ((UINT32) (Pstate + PS_REG_BASE), (UINT64 *) &PstateMsr, StdHeader); + CurrentVid = (UINT32) PstateMsr.CpuVid; + + if (Pstate == HwPstateMaxVal) { + NextPstateCurrent = 0; + } else { + // Check P-state from P1 to HwPstateMaxVal + FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) (Pstate + 1), &NextPstateCurrent, StdHeader); + } + + if ((PstateCurrent <= CoreVrmLowPowerThreshold) && + (NextPstateCurrent <= CoreVrmLowPowerThreshold) && + (CurrentVid != PreviousVid)) { + // Program PsiVid and PsiVidEn if PSI state is found and stop searching. + PciAddress.AddressValue = PW_CTL_MISC_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &PwrCtrlMisc, StdHeader); + PwrCtrlMisc.PsiVid = CurrentVid; + PwrCtrlMisc.PsiVidEn = 1; + LibAmdPciWrite (AccessWidth32, PciAddress, &PwrCtrlMisc, StdHeader); + IDS_HDT_CONSOLE (CPU_TRACE, " PsiVid is enabled at P-state %d. PsiVid: %d\n", Pstate, CurrentVid); + break; + } else { + PstateCurrent = NextPstateCurrent; + PreviousVid = CurrentVid; + } + } + } + + if (PlatformConfig->VrmProperties[NbVrm].LowPowerThreshold != 0) { + // Set up NBPSI0_L for VDDNB + NbVrmLowPowerThreshold = PlatformConfig->VrmProperties[NbVrm].LowPowerThreshold; + IDS_HDT_CONSOLE (CPU_TRACE, " NB VRM - LowPowerThreshold: %d\n", NbVrmLowPowerThreshold); + PreviousNbVid = 0xFF; + CurrentNbVid = 0xFF; + + PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); + NbPstateMaxVal = NbPsCtrl.NbPstateMaxVal; + ASSERT (NbPstateMaxVal < NM_NB_PS_REG); + + IDS_HDT_CONSOLE (CPU_TRACE, " NbPstateMaxVal %d\n", NbPstateMaxVal); + for (NbPstate = 0; NbPstate <= NbPstateMaxVal; NbPstate++) { + // Check only valid NB P-state + if (FamilySpecificServices->GetNbIddMax (FamilySpecificServices, (UINT8) NbPstate, &NbPstateCurrent, StdHeader) != TRUE) { + continue; + } + + PciAddress.Address.Register = (NB_PSTATE_0 + (sizeof (NB_PSTATE_REGISTER) * NbPstate)); + LibAmdPciRead (AccessWidth32, PciAddress, &NbPstateReg, StdHeader); + CurrentNbVid = (UINT32) GetF15TnNbVid (&NbPstateReg); + + if (NbPstate == NbPstateMaxVal) { + NextNbPstateCurrent = 0; + } else { + // Check only valid NB P-state + if (FamilySpecificServices->GetNbIddMax (FamilySpecificServices, (UINT8) (NbPstate + 1), &NextNbPstateCurrent, StdHeader) != TRUE) { + continue; + } + } + + if ((NbPstateCurrent <= NbVrmLowPowerThreshold) && + (NextNbPstateCurrent <= NbVrmLowPowerThreshold) && + (CurrentNbVid != PreviousNbVid)) { + // Program NbPsi0Vid and NbPsi0VidEn if PSI state is found and stop searching. + PciAddress.AddressValue = MISC_VOLTAGES_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &MiscVoltageReg, StdHeader); + MiscVoltageReg.NbPsi0Vid = CurrentNbVid; + MiscVoltageReg.NbPsi0VidEn = 1; + LibAmdPciWrite (AccessWidth32, PciAddress, &MiscVoltageReg, StdHeader); + IDS_HDT_CONSOLE (CPU_TRACE, " NbPsi0Vid is enabled at NB P-state %d. NbPsi0Vid: %d\n", NbPstate, CurrentNbVid); + break; + } else { + PreviousNbVid = CurrentNbVid; + } + } + } +} + + +CONST PSI_FAMILY_SERVICES ROMDATA F15TnPsiSupport = +{ + 0, + (PF_PSI_IS_SUPPORTED) CommonReturnTrue, + F15TnInitializePsi +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPstate.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPstate.c new file mode 100644 index 0000000..7b6321e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPstate.c @@ -0,0 +1,766 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity Pstate feature support functions. + * + * Provides the functions necessary to initialize the Pstate feature. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "GeneralServices.h" +#include "cpuPstateTables.h" +#include "cpuRegisters.h" +#include "Table.h" +#include "cpuFamilyTranslation.h" +#include "cpuFamRegisters.h" +#include "cpuF15Utilities.h" +#include "F15TnUtilities.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "CommonReturns.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNPSTATE_FILECODE + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +F15TnGetPowerStepValueInTime ( + IN OUT UINT32 *PowerStepPtr + ); + +VOID +STATIC +F15TnGetPllValueInTime ( + IN OUT UINT32 *PllLockTimePtr + ); + +AGESA_STATUS +STATIC +F15TnGetFrequencyXlatRegInfo ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN UINT8 PStateNumber, + IN UINT32 Frequency, + OUT UINT32 *CpuFidPtr, + OUT UINT32 *CpuDidPtr1, + OUT UINT32 *CpuDidPtr2, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +F15TnGetPstateTransLatency ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN PSTATE_LEVELING *PStateLevelingBufferStructPtr, + IN PCI_ADDR *PciAddress, + OUT UINT32 *TransitionLatency, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +F15TnGetPstateFrequency ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN UINT8 StateNumber, + OUT UINT32 *FrequencyInMHz, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +F15TnGetPstatePower ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN UINT8 StateNumber, + OUT UINT32 *PowerInMw, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +F15TnGetPstateMaxState ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + OUT UINT32 *MaxPStateNumber, + OUT UINT8 *NumberOfBoostStates, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +F15TnGetPstateRegisterInfo ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN UINT32 PState, + OUT BOOLEAN *PStateEnabled, + IN OUT UINT32 *IddVal, + IN OUT UINT32 *IddDiv, + OUT UINT32 *SwPstateNumber, + IN AMD_CONFIG_PARAMS *StdHeader + ); + + + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to check if Pstate PSD is dependent. + * + * @param[in] PstateCpuServices Pstate CPU services. + * @param[in,out] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE PSD is dependent. + * @retval FALSE PSD is independent. + * + */ +BOOLEAN +STATIC +F15TnIsPstatePsdDependent ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN OUT PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + BOOLEAN PsdIsDependent; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnIsPstatePsdDependent\n"); + + // Family 15h Trinity defaults to dependent PSD; allow Platform Configuration to + // overwrite the default setting. + PsdIsDependent = TRUE; + if (PlatformConfig->ForcePstateIndependent == TRUE) { + PsdIsDependent = FALSE; + } + + IDS_HDT_CONSOLE (CPU_TRACE, " P-state PSD is dependent: %d\n", PsdIsDependent); + return PsdIsDependent; +} + +/** + * Family specific call to set core TscFreqSel. + * + * @param[in] PstateCpuServices Pstate CPU services. + * @param[in] StdHeader Config Handle for library, services. + * + */ +VOID +STATIC +F15TnSetTscFreqSel ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnSetTscFreqSel\n"); + + //TscFreqSel: TSC frequency select. Read-only. Reset: 1. 1=The TSC increments at the P0 frequency. + //This field uses software P-state numbering. + return; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to get Pstate Transition Latency. + * + * Calculate TransitionLatency by power step value and pll value. + * + * @param[in] PstateCpuServices Pstate CPU services. + * @param[in] PStateLevelingBufferStructPtr Pstate row data buffer pointer + * @param[in] PciAddress Pci address + * @param[out] TransitionLatency The transition latency. + * @param[in] StdHeader Header for library and services + * + * @retval AGESA_SUCCESS Always succeeds. + */ +AGESA_STATUS +F15TnGetPstateTransLatency ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN PSTATE_LEVELING *PStateLevelingBufferStructPtr, + IN PCI_ADDR *PciAddress, + OUT UINT32 *TransitionLatency, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempVar_b; + UINT32 TempVar_c; + UINT32 TempVar_d; + UINT32 TempVar8_a; + UINT32 TempVar8_b; + UINT32 Ignored; + UINT32 k; + UINT32 CpuFidSameFlag; + UINT8 PStateMaxValueOnCurrentCore; + UINT32 TransAndBusMastLatency; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnGetPstateTransLatency\n"); + + CpuFidSameFlag = 1; + + F15TnGetFrequencyXlatRegInfo ( + PstateCpuServices, + 0, + PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[0].CoreFreq, + &TempVar_b, + &TempVar_c, + &Ignored, + StdHeader + ); + + TempVar_d = TempVar_b; + PStateMaxValueOnCurrentCore = PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue; + + // + //Check if MSRC001_00[6B:64][CpuFid] is the same value for all P-states where + //MSRC001_00[6B:64][PstateEn]=1 + // + for (k = 1; k <= PStateMaxValueOnCurrentCore; k++) { + if (PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].PStateEnable != 0) { + F15TnGetFrequencyXlatRegInfo ( + PstateCpuServices, + (UINT8) k, + PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].CoreFreq, + &TempVar_b, + &TempVar_c, + &Ignored, + StdHeader + ); + } + + if (TempVar_d != TempVar_b) { + CpuFidSameFlag = 0; + break; + } + } + + PciAddress->Address.Register = 0xD4; + PciAddress->Address.Function = FUNC_3; + LibAmdPciRead (AccessWidth32, *PciAddress, &TempVar_d, StdHeader); + + // PowerStepDown - Bits 20:23 + TempVar8_a = (TempVar_d & 0x00F00000) >> 20; + + // PowerStepUp - Bits 24:27 + TempVar8_b = (TempVar_d & 0x0F000000) >> 24; + + // Convert the raw numbers in TempVar8_a and TempVar8_b into time + F15TnGetPowerStepValueInTime (&TempVar8_a); + F15TnGetPowerStepValueInTime (&TempVar8_b); + + // + //(12 * (F3xD4[PowerStepDown] + F3xD4[PowerStepUp]) /1000) us + // + TransAndBusMastLatency = + (12 * (TempVar8_a + TempVar8_b) + 999) / 1000; + + if (CpuFidSameFlag == 0) { + // + //+ F3xA0[PllLockTime] + // + PciAddress->Address.Register = 0xA0; + LibAmdPciRead (AccessWidth32, *PciAddress, &TempVar_d, StdHeader); + + TempVar8_a = (0x00003800 & TempVar_d) >> 11; + F15TnGetPllValueInTime (&TempVar8_a); + TransAndBusMastLatency += TempVar8_a; + } + + *TransitionLatency = TransAndBusMastLatency; + + return (AGESA_SUCCESS); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to calculates the frequency in megahertz of the desired P-state. + * + * @param[in] PstateCpuServices Pstate CPU services. + * @param[in] StateNumber The P-State to analyze. + * @param[out] FrequencyInMHz The P-State's frequency in MegaHertz + * @param[in] StdHeader Header for library and services + * + * @retval AGESA_SUCCESS Always Succeeds. + */ +AGESA_STATUS +F15TnGetPstateFrequency ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN UINT8 StateNumber, + OUT UINT32 *FrequencyInMHz, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 TempValue; + UINT32 CpuDid; + UINT32 CpuFid; + UINT64 LocalMsrRegister; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnGetPstateFrequency - P%d\n", StateNumber); + + ASSERT (StateNumber < NM_PS_REG); + LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader); + ASSERT (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1); + CpuDid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuDid); + CpuFid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuFid); + + switch (CpuDid) { + case 0: + TempValue = 1; + break; + case 1: + TempValue = 2; + break; + case 2: + TempValue = 4; + break; + case 3: + TempValue = 8; + break; + case 4: + TempValue = 16; + break; + default: + // CpuDid is set to an undefined value. This is due to either a misfused CPU, or + // an invalid P-state MSR write. + ASSERT (FALSE); + TempValue = 1; + break; + } + *FrequencyInMHz = (100 * (CpuFid + 0x10) / TempValue); + IDS_HDT_CONSOLE (CPU_TRACE, " FrequencyInMHz=%d, CpuFid=%d, CpuDid=%d\n", *FrequencyInMHz, CpuFid, CpuDid); + + return (AGESA_SUCCESS); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to calculates the power in milliWatts of the desired P-state. + * + * @param[in] PstateCpuServices Pstate CPU services. + * @param[in] StateNumber Which P-state to analyze + * @param[out] PowerInMw The Power in milliWatts of that P-State + * @param[in] StdHeader Header for library and services + * + * @retval AGESA_SUCCESS Always succeeds. + */ +AGESA_STATUS +F15TnGetPstatePower ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN UINT8 StateNumber, + OUT UINT32 *PowerInMw, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 CpuVid; + UINT32 IddValue; + UINT32 IddDiv; + UINT32 V_x100000; + UINT32 Power; + UINT64 LocalMsrRegister; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnGetPstatePower - P%d\n", StateNumber); + + ASSERT (StateNumber < NM_PS_REG); + LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader); + ASSERT (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1); + CpuVid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuVid); + IddValue = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->IddValue); + IddDiv = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->IddDiv); + + if (CpuVid >= 0xF8) { + V_x100000 = 0; + } else { + V_x100000 = 155000L - (625L * CpuVid); + } + + Power = V_x100000 * IddValue; + + switch (IddDiv) { + case 0: + *PowerInMw = Power / 100L; + break; + case 1: + *PowerInMw = Power / 1000L; + break; + case 2: + *PowerInMw = Power / 10000L; + break; + default: + // IddDiv is set to an undefined value. This is due to either a misfused CPU, or + // an invalid P-state MSR write. + ASSERT (FALSE); + *PowerInMw = 0; + break; + } + IDS_HDT_CONSOLE (CPU_TRACE, " PowerInMw=%d, CpuVid=%d, IddValue=%d, IddDiv=%d\n", *PowerInMw, CpuVid, IddValue, IddDiv); + + return (AGESA_SUCCESS); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to get CPU pstate max state. + * + * @param[in] PstateCpuServices Pstate CPU services. + * @param[out] MaxPStateNumber The max hw pstate value on the current socket. + * @param[out] NumberOfBoostStates The number of boosted P-states on the current socket. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval AGESA_SUCCESS Always succeeds. + */ +AGESA_STATUS +F15TnGetPstateMaxState ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + OUT UINT32 *MaxPStateNumber, + OUT UINT8 *NumberOfBoostStates, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 NumBoostStates; + UINT64 MsrValue; + UINT32 LocalPciRegister; + PCI_ADDR PciAddress; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnGetPstateMaxState\n"); + + LocalPciRegister = 0; + + // For F15 Trinity CPU, skip boosted p-state. The boosted p-state number = F4x15C[NumBoostStates]. + PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F4x15C + + NumBoostStates = ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates; + *NumberOfBoostStates = (UINT8) NumBoostStates; + + // + // Read PstateMaxVal [6:4] from MSR C001_0061 + // So, we will know the max pstate state in this socket. + // + LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrValue, StdHeader); + *MaxPStateNumber = (UINT32) (((PSTATE_CURLIM_MSR *) &MsrValue)->PstateMaxVal) + NumBoostStates; + IDS_HDT_CONSOLE (CPU_TRACE, " MaxPStateNumber=%d, NumBoostStates=%d\n", *MaxPStateNumber, NumBoostStates); + + return (AGESA_SUCCESS); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to get CPU pstate register information. + * + * @param[in] PstateCpuServices Pstate CPU services. + * @param[in] PState Input Pstate number for query. + * @param[out] PStateEnabled Boolean flag return pstate enable. + * @param[in,out] IddVal Pstate current value. + * @param[in,out] IddDiv Pstate current divisor. + * @param[out] SwPstateNumber Software P-state number. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval AGESA_SUCCESS Always succeeds. + */ +AGESA_STATUS +F15TnGetPstateRegisterInfo ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN UINT32 PState, + OUT BOOLEAN *PStateEnabled, + IN OUT UINT32 *IddVal, + IN OUT UINT32 *IddDiv, + OUT UINT32 *SwPstateNumber, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 LocalPciRegister; + UINT64 LocalMsrRegister; + PCI_ADDR PciAddress; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnGetPstateRegisterInfo - P%d\n", PState); + + ASSERT (PState < NM_PS_REG); + + // For F15 Trinity CPU, skip boosted p-state. The boosted p-state number = F4x15C[NumBoostStates]. + PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F4x15C + + // Read PSTATE MSRs + LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &LocalMsrRegister, StdHeader); + + *SwPstateNumber = PState; + + if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) { + // PState enable = bit 63 + *PStateEnabled = TRUE; + // + // Check input pstate belongs to Boosted-Pstate, if yes, return *PStateEnabled = FALSE. + // + if (PState < ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates) { + *PStateEnabled = FALSE; + } else { + *SwPstateNumber = PState - ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates; + } + IDS_HDT_CONSOLE (CPU_TRACE, " Pstate %d is enabled. SwPstateNumber=%d\n", PState, *SwPstateNumber); + } else { + *PStateEnabled = FALSE; + } + + // Bits 39:32 (high 32 bits [7:0]) + *IddVal = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->IddValue; + // Bits 41:40 (high 32 bits [9:8]) + *IddDiv = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->IddDiv; + + IDS_HDT_CONSOLE (CPU_TRACE, " IddVal=%d, IddDiv=%d\n", *IddVal, *IddDiv); + return (AGESA_SUCCESS); +} + + +CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15TnPstateServices = +{ + 0, + (PF_PSTATE_PSD_IS_NEEDED) CommonReturnTrue, + F15TnIsPstatePsdDependent, + F15TnSetTscFreqSel, + F15TnGetPstateTransLatency, + F15TnGetPstateFrequency, + (PF_CPU_SET_PSTATE_LEVELING_REG) CommonReturnAgesaSuccess, + F15TnGetPstatePower, + F15TnGetPstateMaxState, + F15TnGetPstateRegisterInfo +}; + + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + + +/** + *--------------------------------------------------------------------------------------- + * + * F15TnGetPowerStepValueInTime + * + * Description: + * Convert power step value in time + * + * Parameters: + * @param[out] *PowerStepPtr + * + * @retval VOID + * + *--------------------------------------------------------------------------------------- + **/ +VOID +STATIC +F15TnGetPowerStepValueInTime ( + IN OUT UINT32 *PowerStepPtr + ) +{ + UINT32 TempVar_a; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnGetPowerStepValueInTime\n"); + + TempVar_a = *PowerStepPtr; + + if (TempVar_a < 0x4) { + *PowerStepPtr = 400 - (TempVar_a * 100); + } else if (TempVar_a < 0x9) { + *PowerStepPtr = 130 - (TempVar_a * 10); + } else { + *PowerStepPtr = 90 - (TempVar_a * 5); + } + IDS_HDT_CONSOLE (CPU_TRACE, " PowerStepPtr=%d\n", *PowerStepPtr); +} + +/** + *--------------------------------------------------------------------------------------- + * + * F15TnGetPllValueInTime + * + * Description: + * Convert PLL Value in time + * + * Parameters: + * @param[out] *PllLockTimePtr + * + * @retval VOID + * + *--------------------------------------------------------------------------------------- + **/ +VOID +STATIC +F15TnGetPllValueInTime ( + IN OUT UINT32 *PllLockTimePtr + ) +{ + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnGetPllValueInTime\n"); + + if (*PllLockTimePtr < 4) { + *PllLockTimePtr = *PllLockTimePtr + 1; + } else if (*PllLockTimePtr == 4) { + *PllLockTimePtr = 8; + } else if (*PllLockTimePtr == 5) { + *PllLockTimePtr = 16; + } else + *PllLockTimePtr = 0; + IDS_HDT_CONSOLE (CPU_TRACE, " PllLockTimePtr=%d\n", *PllLockTimePtr); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * This function will return the CpuFid and CpuDid in MHz, using the formula + * described in the BKDG MSRC001_00[68:64] P-State [4:0] Registers:bit 8:0 + * + * @param[in] PstateCpuServices The current Family Specific Services. + * @param[in] PStateNumber P-state number to check. + * @param[in] Frequency Leveled target frequency for PStateNumber. + * @param[out] *CpuFidPtr New leveled FID. + * @param[out] *CpuDidPtr1 New leveled DID info 1. + * @param[out] *CpuDidPtr2 New leveled DID info 2. + * @param[in] *StdHeader Header for library and services. + * + * @retval AGESA_WARNING This P-State does not need to be modified. + * @retval AGESA_SUCCESS This P-State must be modified to be level. + */ +AGESA_STATUS +STATIC +F15TnGetFrequencyXlatRegInfo ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN UINT8 PStateNumber, + IN UINT32 Frequency, + OUT UINT32 *CpuFidPtr, + OUT UINT32 *CpuDidPtr1, + OUT UINT32 *CpuDidPtr2, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 i; + UINT32 j; + AGESA_STATUS Status; + UINT32 FrequencyInMHz; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnGetFrequencyXlatRegInfo - PstateNumber=%d, Frequency=%d\n", PStateNumber, Frequency); + + FrequencyInMHz = 0; + *CpuDidPtr2 = 0xFFFF; + + Status = AGESA_SUCCESS; + + PstateCpuServices->GetPstateFrequency (PstateCpuServices, PStateNumber, &FrequencyInMHz, StdHeader); + if (FrequencyInMHz == Frequency) { + Status |= AGESA_WARNING; + } + + // CPU Frequency = 100 MHz * (CpuFid + 10h) / (2^CpuDid) + // In this for loop i = 2^CpuDid + + + for (i = 1; i < 17; (i += i)) { + for (j = 0; j < 64; j++) { + if (Frequency == ((100 * (j + 0x10)) / i )) { + *CpuFidPtr = j; + if (i == 1) { + *CpuDidPtr1 = 0; + } else if (i == 2) { + *CpuDidPtr1 = 1; + } else if (i == 4) { + *CpuDidPtr1 = 2; + } else if (i == 8) { + *CpuDidPtr1 = 3; + } else if (i == 16) { + *CpuDidPtr1 = 4; + } else { + *CpuFidPtr = 0xFFFF; + *CpuDidPtr1 = 0xFFFF; + } + IDS_HDT_CONSOLE (CPU_TRACE, " CpuFidPtr=%d, CpuDidPtr1=0x%x, CpuDidPtr2=0x%x\n", *CpuFidPtr, *CpuDidPtr1, *CpuDidPtr2); + // Success + return Status; + } + } + } + + // Error Condition + *CpuFidPtr = 0x00FF; + *CpuDidPtr1 = 0x00FF; + *CpuDidPtr2 = 0x00FF; + + IDS_HDT_CONSOLE (CPU_TRACE, " CpuFidPtr=%d, CpuDidPtr1=0x%x, CpuDidPtr2=0x%x\n", *CpuFidPtr, *CpuDidPtr1, *CpuDidPtr2); + return AGESA_ERROR; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c new file mode 100644 index 0000000..6ffed12 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c @@ -0,0 +1,207 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 specific utility functions. + * + * Provides numerous utility functions specific to family 15h. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15 + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "cpuApicUtilities.h" +#include "cpuFamilyTranslation.h" +#include "cpuCommonF15Utilities.h" +#include "cpuF15PowerMgmt.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_CPU_FAMILY_0X15_CPUCOMMONF15UTILITIES_FILECODE + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Set warm reset status and count + * + * @CpuServiceMethod{::F_CPU_SET_WARM_RESET_FLAG}. + * + * This function will use bit9, and bit 10 of register F0x6C as a warm reset status and count. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * @param[in] Request Indicate warm reset status + * + */ +VOID +F15SetAgesaWarmResetFlag ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CONFIG_PARAMS *StdHeader, + IN WARM_RESET_REQUEST *Request + ) +{ + PCI_ADDR PciAddress; + UINT32 PciData; + + PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL); + LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); + + // bit[5] - indicate a warm reset is or is not required + PciData &= ~(HT_INIT_BIOS_RST_DET_0); + PciData = PciData | (Request->RequestBit << 5); + + // bit[10,9] - indicate warm reset status and count + PciData &= ~(HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2); + PciData |= Request->StateBits << 9; + + LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Get warm reset status and count + * + * @CpuServiceMethod{::F_CPU_GET_WARM_RESET_FLAG}. + * + * This function will bit9, and bit 10 of register F0x6C as a warm reset status and count. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] StdHeader Config handle for library and services + * @param[out] Request Indicate warm reset status + * + */ +VOID +F15GetAgesaWarmResetFlag ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CONFIG_PARAMS *StdHeader, + OUT WARM_RESET_REQUEST *Request + ) +{ + PCI_ADDR PciAddress; + UINT32 PciData; + + PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL); + LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); + + // bit[5] - indicate a warm reset is or is not required + Request->RequestBit = (UINT8) ((PciData & HT_INIT_BIOS_RST_DET_0) >> 5); + // bit[10,9] - indicate warm reset status and count + Request->StateBits = (UINT8) ((PciData & (HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2)) >> 9); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Return a number zero or one, based on the Core ID position in the initial APIC Id. + * + * @CpuServiceMethod{::F_CORE_ID_POSITION_IN_INITIAL_APIC_ID}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval CoreIdPositionZero Core Id is not low + * @retval CoreIdPositionOne Core Id is low + */ +CORE_ID_POSITION +F15CpuAmdCoreIdPositionInInitialApicId ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 InitApicIdCpuIdLo; + + // Check bit_54 [InitApicIdCpuIdLo] to find core id position. + LibAmdMsrRead (MSR_NB_CFG, &InitApicIdCpuIdLo, StdHeader); + InitApicIdCpuIdLo = ((InitApicIdCpuIdLo & BIT54) >> 54); + return ((InitApicIdCpuIdLo == 0) ? CoreIdPositionZero : CoreIdPositionOne); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuCommonF15Utilities.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuCommonF15Utilities.h new file mode 100644 index 0000000..c802f8b --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuCommonF15Utilities.h @@ -0,0 +1,118 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 specific utility functions. + * + * Provides numerous utility functions specific to family 15h. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15 + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_COMMON_F15_UTILITES_H_ +#define _CPU_COMMON_F15_UTILITES_H_ + + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ +CORE_ID_POSITION +F15CpuAmdCoreIdPositionInInitialApicId ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +F15SetAgesaWarmResetFlag ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CONFIG_PARAMS *StdHeader, + IN WARM_RESET_REQUEST *Request + ); + +VOID +F15GetAgesaWarmResetFlag ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CONFIG_PARAMS *StdHeader, + OUT WARM_RESET_REQUEST *Request + ); + +#endif // _CPU_COMMON_F15_UTILITES_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Apm.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Apm.c new file mode 100644 index 0000000..439a6ef --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Apm.c @@ -0,0 +1,152 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 APM Initialization + * + * Enables Application Power Management feature + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15 + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "GeneralServices.h" +#include "cpuServices.h" +#include "cpuRegisters.h" +#include "cpuFamilyTranslation.h" +#include "cpuF15PowerMgmt.h" +#include "CommonReturns.h" +#include "cpuApm.h" +#include "OptionMultiSocket.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15APM_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; +/*---------------------------------------------------------------------------------------*/ +/** + * Entry point for enabling Application Power Management + * + * This function must be run after all P-State routines have been executed + * + * @param[in] ApmServices The current CPU's family services. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config handle for library and services. + * + * @retval AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +STATIC +F15InitializeApm ( + IN APM_FAMILY_SERVICES *ApmServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 LocalPciRegister; + PCI_ADDR PciAddress; + + PciAddress.Address.Function = FUNC_4; + PciAddress.Address.Register = CPB_CTRL_REG; + LocalPciRegister = 0; + ((F15_CPB_CTRL_REGISTER *) (&LocalPciRegister))->ApmMasterEn = 1; + OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, 0xFFFFFFFF, LocalPciRegister, StdHeader); + + return AGESA_SUCCESS; +} + + + +CONST APM_FAMILY_SERVICES ROMDATA F15ApmSupport = +{ + 0, + (PF_APM_IS_SUPPORTED) CommonReturnTrue, + F15InitializeApm +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15BrandId.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15BrandId.c new file mode 100644 index 0000000..006111f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15BrandId.c @@ -0,0 +1,249 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU BrandId related functions and structures. + * + * Contains code that provides CPU BrandId information + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15 + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuRegisters.h" +#include "cpuFamilyTranslation.h" +#include "cpuEarlyInit.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "OptionMultiSocket.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15BRANDID_FILECODE + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define NAME_STRING_ADDRESS_PORT 0x194 +#define NAME_STRING_DATA_PORT 0x198 + +extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +/// A structure containing brand string +typedef struct { + CONST CHAR8 *Stringstart; ///< The literal string +} CPU_F15_EXCEPTION_BRAND; + +/// FAM15_BRAND_STRING_MSR +typedef struct _PROCESSOR_NAME_STRING { + UINT32 lo; ///< lower 32-bits of 64-bit value + UINT32 hi; ///< highest 32-bits of 64-bit value +} PROCESSOR_NAME_STRING; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +IsException ( + OUT UINT32 *ExceptionId, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +F15SetBrandIdRegistersAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +// This is an example, need to be updated once Processor Revision Guide define brand string exception +// Brand string is always 48 bytes +CONST CHAR8 ROMDATA str_Exception_0[48] = "AMD Phenom(tm) Octal-Core"; +CONST CHAR8 ROMDATA str_Unprogrammed_Sample[48] = "AMD Unprogrammed Engineering Sample"; +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ +CONST CPU_F15_EXCEPTION_BRAND ROMDATA CpuF15ExceptionBrandIdString[] = +{ + {str_Exception_0} +}; + +/*---------------------------------------------------------------------------------------*/ +/** + * Set the Processor Name String register based on F5x194/198 + * + * This function copies F5x198_x[B:0] to MSR_C001_00[35:30] + * + * @param[in] FamilyServices The current Family Specific Services. + * @param[in] EarlyParams Service parameters. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +F15SetBrandIdRegistersAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 PciData; + UINT32 ExceptionId; + UINT32 MsrIndex; + UINT64 MsrData; + UINT64 *MsrNameStringPtrPtr; + PCI_ADDR PciAddress; + + if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) { + if (IsException (&ExceptionId, StdHeader)) { + ASSERT (ExceptionId < (sizeof (CpuF15ExceptionBrandIdString) / sizeof (CpuF15ExceptionBrandIdString[0]))); + + MsrNameStringPtrPtr = (UINT64 *) CpuF15ExceptionBrandIdString[ExceptionId].Stringstart; + } else { + OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); + PciAddress.Address.Function = FUNC_5; + PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT; + // check if D18F5x198_x0 is 00000000h. + PciData = 0; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader); + PciAddress.Address.Register = NAME_STRING_DATA_PORT; + LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); + if (PciData != 0) { + for (MsrIndex = 0; MsrIndex <= (MSR_CPUID_NAME_STRING5 - MSR_CPUID_NAME_STRING0); MsrIndex++) { + PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT; + PciData = MsrIndex * 2; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader); + PciAddress.Address.Register = NAME_STRING_DATA_PORT; + LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); + ((PROCESSOR_NAME_STRING *) (&MsrData))->lo = PciData; + + PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT; + PciData = (MsrIndex * 2) + 1; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader); + PciAddress.Address.Register = NAME_STRING_DATA_PORT; + LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); + ((PROCESSOR_NAME_STRING *) (&MsrData))->hi = PciData; + + LibAmdMsrWrite ((MsrIndex + MSR_CPUID_NAME_STRING0), &MsrData, StdHeader); + } + return; + } else { + // It is unprogrammed (unfused) parts and use a name string of "AMD Unprogrammed Engineering Sample" + MsrNameStringPtrPtr = (UINT64 *) str_Unprogrammed_Sample; + } + } + // Put values into name MSRs, Always write the full 48 bytes + for (MsrIndex = MSR_CPUID_NAME_STRING0; MsrIndex <= MSR_CPUID_NAME_STRING5; MsrIndex++) { + LibAmdMsrWrite (MsrIndex, MsrNameStringPtrPtr, StdHeader); + MsrNameStringPtrPtr++; + } + } +} + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Check if it's an exception + * + * For family 15h, brand string is obtained from F5x198_x[B:0], but there may be exceptions. + * This function checks if it's an exception. + * + * @param[out] ExceptionId Id of exception + * @param[in] StdHeader Config handle for library and services. + * + * @retval TRUE It's an exception + * @retval FALSE It's NOT an exception + */ +BOOLEAN +STATIC +IsException ( + OUT UINT32 *ExceptionId, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + // This function will be updated, once Processor Revision Guide defines Fam15 brand string exception + *ExceptionId = 0xFFFF; + + return FALSE; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c new file mode 100644 index 0000000..9870ec7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c @@ -0,0 +1,224 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 ROM Execution Cache Defaults + * + * Contains default values for ROM execution cache setup + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15 + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuCacheInit.h" +#include "cpuFamilyTranslation.h" +#include "amdlib.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15CACHEDEFAULTS_FILECODE + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +GetF15CacheInfo ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **CacheInfoPtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +#define MEM_TRAINING_BUFFER_SIZE 16384 +#define VAR_MTRR_MASK 0x0000FFFFFFFFFFFFul +#define VAR_MTRR_MASK_CP 0x0000FFFFFFFEFFFFul + +#define HEAP_BASE_MASK_CP 0x0000FFFFFFFEFF00ul +#define HEAP_BASE_MASK 0x0000FFFFFFFFFFFFul + +#define SHARED_MEM_SIZE 0 + +CONST CACHE_INFO ROMDATA CpuF15CacheInfo = +{ + BSP_STACK_SIZE_64K, + CORE0_STACK_SIZE, + CORE1_STACK_SIZE, + MEM_TRAINING_BUFFER_SIZE, + SHARED_MEM_SIZE, + VAR_MTRR_MASK, + VAR_MTRR_MASK, + HEAP_BASE_MASK, + InfiniteExe +}; + +CONST CACHE_INFO ROMDATA CpuF15CacheInfoCP = +{ + BSP_STACK_SIZE_64K, + CORE0_STACK_SIZE, + CORE1_STACK_SIZE, + MEM_TRAINING_BUFFER_SIZE, + SHARED_MEM_SIZE, + VAR_MTRR_MASK, + VAR_MTRR_MASK_CP, + HEAP_BASE_MASK_CP, + InfiniteExe +}; + + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the family specific properties of the cache, and its usage. + * + * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[out] CacheInfoPtr Points to the cache info properties on exit. + * @param[out] NumberOfElements Will be one to indicate one entry. + * @param[in] StdHeader Header for library and services. + * + */ +VOID +GetF15CacheInfo ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **CacheInfoPtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Enabled; + UINT32 DualCore; + UINT32 Node; + PCI_ADDR PciAddress; + CPU_SPECIFIC_SERVICES *FamilyServices; + AP_MAILBOXES ApMailboxes; + CORE_PAIR_MAP *CorePairMap; + AGESA_STATUS IgnoredStatus; + + if (!IsBsp (StdHeader, &IgnoredStatus)) { + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader); + ASSERT (FamilyServices != NULL); + + FamilyServices->GetApMailboxFromHardware (FamilyServices, &ApMailboxes, StdHeader); + Node = ApMailboxes.ApMailInfo.Fields.Node; + + // Since pre-heap, get compute unit status from hardware, using mailbox info. + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0); + PciAddress.Address.Device = PciAddress.Address.Device + Node; + PciAddress.Address.Function = FUNC_5; + PciAddress.Address.Register = COMPUTE_UNIT_STATUS; + LibAmdPciReadBits (PciAddress, 3, 0, &Enabled, StdHeader); + LibAmdPciReadBits (PciAddress, 19, 16, &DualCore, StdHeader); + + // Find the core to compute unit mapping for this node. + CorePairMap = FamilyServices->CorePairMap; + if ((Enabled != 0) && (CorePairMap != NULL)) { + while (CorePairMap->Enabled != 0xFF) { + if ((Enabled == CorePairMap->Enabled) && (DualCore == CorePairMap->DualCore)) { + break; + } + CorePairMap++; + } + // The assert is for finding a processor configured in a way the core pair map doesn't support. + ASSERT (CorePairMap->Enabled != 0xFF); + switch (CorePairMap->Mapping) { + case AllCoresMapping: + // No cores are sharing a compute unit + *CacheInfoPtr = &CpuF15CacheInfo; + break; + case EvenCoresMapping: + // Cores are paired into compute units + *CacheInfoPtr = &CpuF15CacheInfoCP; + break; + default: + ASSERT (FALSE); + } + } + } else { + // the BSC is always just the first slice, we could return either one. Return the non for safest. + *CacheInfoPtr = &CpuF15CacheInfo; + } + *NumberOfElements = 1; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Crat.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Crat.c new file mode 100644 index 0000000..1f4efa7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Crat.c @@ -0,0 +1,278 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CRAT Record Creation API, and related functions for Family 15h. + * + * Contains code that produce the CRAT related information. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15 + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuRegisters.h" +#include "cpuFamilyTranslation.h" +#include "cpuLateInit.h" +#include "OptionCrat.h" +#include "cpuCrat.h" +#include "cpuServices.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15CRAT_FILECODE + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +extern CONST UINT8 ROMDATA L2L3Associativity[]; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * generate CRAT cache entry for F15 processor + * + * + * @param[in] CratHeaderStructPtr CRAT header pointer + * @param[in, out] TableEnd The end of CRAT + * @param[in, out] StdHeader Standard Head Pointer + * + */ +VOID +STATIC +F15GenerateCratCacheEntry ( + IN CRAT_HEADER *CratHeaderStructPtr, + IN OUT UINT8 **TableEnd, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + UINT8 NodeNum; + UINT8 NodeCount; + UINT8 CoreNumPerCU; + UINT32 Socket; + UINT32 Module; + UINT32 CoreNum; + UINT32 LowCore; + UINT32 HighCore; + UINT32 RegVal; + CPUID_DATA L1CpuId; + CPUID_DATA L2L3CpuId; + CRAT_CACHE *EntryPtr; + AMD_APIC_PARAMS ApicParams; + PCI_ADDR PciAddress; + + // Get Node count + PciAddress.AddressValue = MAKE_SBDFO (0, 0, LOW_NODE_DEVICEID, FUNC_0, 0x60); + LibAmdPciRead (AccessWidth32 , PciAddress, &RegVal, StdHeader); + NodeCount = (UINT8) (((RegVal >> 4) & 0x7) + 1); + + // Get compute unit info + switch (GetComputeUnitMapping (StdHeader)) { + case AllCoresMapping: + CoreNumPerCU = 1; + break; + case EvenCoresMapping: + CoreNumPerCU = 2; + break; + default: + CoreNumPerCU = 1; + } + // Get L1 L2 cache information from CPUID + LibAmdCpuidRead (AMD_CPUID_TLB_L1Cache, &L1CpuId, StdHeader); + LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &L2L3CpuId, StdHeader); + + NodeNum = 0; + ApicParams.StdHeader = *StdHeader; + while (NodeNum < NodeCount) { + GetSocketModuleOfNode ((UINT32) NodeNum, &Socket, &Module, StdHeader); + GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader); + + for (CoreNum = LowCore; CoreNum <= HighCore; CoreNum++) { + ApicParams.Socket = (UINT8) Socket; + ApicParams.Core = (UINT8) CoreNum; + AmdGetApicId (&ApicParams); + if (ApicParams.IsPresent) { + // L1 Data cache + EntryPtr = (CRAT_CACHE *) AddOneCratEntry (CRAT_TYPE_CACHE, CratHeaderStructPtr, TableEnd, StdHeader); + EntryPtr->Flags.Enabled = 1; + EntryPtr->Flags.DataCache = 1; + EntryPtr->Flags.CpuCache = 1; + EntryPtr->ProcessorIdLow = ApicParams.ApicAddress; + i = ApicParams.ApicAddress / 8; + EntryPtr->SiblingMap[i] = 1 << (ApicParams.ApicAddress % 8); + EntryPtr->CacheSize = L1CpuId.ECX_Reg >> 24; // bits[31:24] L1 data cache size + EntryPtr->CacheLevel = 1; + EntryPtr->LinesPerTag = (UINT8) ((L1CpuId.ECX_Reg >> 8) & 0xFF); // bits[15:8] L1 data cache lines per tag; + EntryPtr->CacheLineSize = (UINT16) (L1CpuId.ECX_Reg & 0xFF); // bits[7:0] L1 data cache line size; + EntryPtr->Associativity = (UINT8) ((L1CpuId.ECX_Reg >> 16) & 0xFF); // bits[23:16] L1 data cache associativity; + /// @todo which value should set here? + //EntryPtr->CacheProperties = ; + EntryPtr->CacheLatency = 1; + + if (CoreNum % CoreNumPerCU == 0) { + // L1 Instruction cache, shared by compute unit + EntryPtr = (CRAT_CACHE *) AddOneCratEntry (CRAT_TYPE_CACHE, CratHeaderStructPtr, TableEnd, StdHeader); + EntryPtr->Flags.Enabled = 1; + EntryPtr->Flags.DataCache = 1; + EntryPtr->Flags.CpuCache = 1; + EntryPtr->ProcessorIdLow = ApicParams.ApicAddress; + i = ApicParams.ApicAddress / 8; + EntryPtr->SiblingMap[i] = 3 << (ApicParams.ApicAddress % 8); + EntryPtr->CacheSize = L1CpuId.EDX_Reg >> 24; // bits[31:24] L1 instruction cache size + EntryPtr->CacheLevel = 1; + EntryPtr->LinesPerTag = (UINT8) ((L1CpuId.EDX_Reg >> 8) & 0xFF); // bits[15:8] L1 instruction cache lines per tag + EntryPtr->CacheLineSize = (UINT16) (L1CpuId.EDX_Reg & 0xFF); // bits[7:0] L1 data instruction line size + EntryPtr->Associativity = (UINT8) ((L1CpuId.EDX_Reg >> 16) & 0xFF); // bits[23:16] L1 instruction cache associativity + /// @todo which value should be set here? + //EntryPtr->CacheProperties = ; + EntryPtr->CacheLatency = 1; + + // L2 cache, shared by compute unit + EntryPtr = (CRAT_CACHE *) AddOneCratEntry (CRAT_TYPE_CACHE, CratHeaderStructPtr, TableEnd, StdHeader); + EntryPtr->Flags.Enabled = 1; + EntryPtr->Flags.CpuCache = 1; + EntryPtr->ProcessorIdLow = ApicParams.ApicAddress; + i = ApicParams.ApicAddress / 8; + EntryPtr->SiblingMap[i] = 3 << (ApicParams.ApicAddress % 8); + EntryPtr->CacheSize = L2L3CpuId.ECX_Reg >> 16; // bits[31:16] L2 cache size + EntryPtr->CacheLevel = 2; + EntryPtr->LinesPerTag = (UINT8) ((L2L3CpuId.ECX_Reg >> 8) & 0xF); // bits[11:8] L2 cache lines per tag + EntryPtr->CacheLineSize = (UINT16) (L2L3CpuId.ECX_Reg & 0xFF); // bits[7:0] L2 cache line size + EntryPtr->Associativity = L2L3Associativity[(L2L3CpuId.ECX_Reg >> 12) & 0xF]; // bits[15:12] L2 cache associativity + } + // L3 cache, shared by node + // bits[31:18] L3 cache size + if (((L2L3CpuId.EDX_Reg & 0xFFFC0000) != 0) && (CoreNum == 0)) { + EntryPtr = (CRAT_CACHE *) AddOneCratEntry (CRAT_TYPE_CACHE, CratHeaderStructPtr, TableEnd, StdHeader); + EntryPtr->Flags.Enabled = 1; + EntryPtr->Flags.CpuCache = 1; + EntryPtr->ProcessorIdLow = ApicParams.ApicAddress; + i = ApicParams.ApicAddress / 8; + EntryPtr->SiblingMap[i] = ((1 << (UINT8) (HighCore - LowCore + 1)) - 1) << (ApicParams.ApicAddress % 8); + EntryPtr->CacheSize = (L2L3CpuId.EDX_Reg >> 18) * 512; // bits[31:18] L3 cache size + EntryPtr->CacheLevel = 3; + EntryPtr->LinesPerTag = (UINT8) ((L2L3CpuId.EDX_Reg >> 8) & 0xF); // bits[11:8] L3 cache lines per tag + EntryPtr->CacheLineSize = (UINT16) (L2L3CpuId.EDX_Reg & 0xFF); // bits[7:0] L3 cache line size + EntryPtr->Associativity = L2L3Associativity[(L2L3CpuId.EDX_Reg >> 12) & 0xF]; // bits[15:12] L3 cache associativity + + } + } + } + + NodeNum++; + } + + return; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * generate CRAT TLB entry for F15 processor + * + * + * @param[in] CratHeaderStructPtr CRAT header pointer + * @param[in, out] TableEnd The end of CRAT + * @param[in, out] StdHeader Standard Head Pointer + * + */ +VOID +STATIC +F15GenerateCratTLBEntry ( + IN CRAT_HEADER *CratHeaderStructPtr, + IN OUT UINT8 **TableEnd, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return; +} + +CONST CRAT_FAMILY_SERVICES ROMDATA F15CratSupport = +{ + 0, + F15GenerateCratCacheEntry, + F15GenerateCratTLBEntry +}; + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Dmi.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Dmi.c new file mode 100644 index 0000000..c2f1e33 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Dmi.c @@ -0,0 +1,150 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD DMI Record Creation API, and related functions for Family 15h. + * + * Contains code that produce the DMI related information. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15 + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuRegisters.h" +#include "cpuFamilyTranslation.h" +#include "cpuPstateTables.h" +#include "cpuLateInit.h" +#include "cpuF15PowerMgmt.h" +#include "cpuServices.h" +#include "cpuF15Dmi.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15DMI_FILECODE + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * DmiF15GetMaxSpeed + * + * Get the Max Speed + * + * @param[in] StdHeader Standard Head Pointer + * + * @retval MaxSpeed - CPU Max Speed. + * + */ +UINT16 +DmiF15GetMaxSpeed ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 NumBoostStates; + UINT32 P0Frequency; + UINT32 PciData; + PCI_ADDR PciAddress; + PSTATE_CPU_FAMILY_SERVICES *FamilyServices; + + FamilyServices = NULL; + GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); + ASSERT (FamilyServices != NULL); + + PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_4, 0x15C); + LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); + NumBoostStates = (UINT8) ((PciData >> 2) & 7); + + FamilyServices->GetPstateFrequency (FamilyServices, NumBoostStates, &P0Frequency, StdHeader); + return ((UINT16) P0Frequency); +} + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Dmi.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Dmi.h new file mode 100644 index 0000000..41202ec --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Dmi.h @@ -0,0 +1,103 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD DMI Record Creation API, and related functions for Family 15h. + * + * Contains code that produce the DMI related information. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15 + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_F15_DMI_H_ +#define _CPU_F15_DMI_H_ + + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ + +UINT16 +DmiF15GetMaxSpeed ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif // _CPU_F15_DMI_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c new file mode 100644 index 0000000..9e19d80 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c @@ -0,0 +1,392 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 MMIO map manager + * + * manage MMIO base/limit registers. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/F15 + * @e $Revision: 63522 $ @e $Date: 2011-12-25 20:25:03 -0600 (Sun, 25 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "GeneralServices.h" +#include "cpuServices.h" +#include "cpuFamilyTranslation.h" +#include "mmioMapManager.h" +#include "cpuF15MmioMap.h" +#include "S3SaveState.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15MMIOMAP_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +STATIC CONST UINT16 ROMDATA MmioBaseLowRegOffset[MMIO_REG_PAIR_NUM] = {0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0, 0xB8, 0x1A0, 0x1A8, 0x1B0, 0x1B8}; +STATIC CONST UINT16 ROMDATA MmioLimitLowRegOffset[MMIO_REG_PAIR_NUM] = {0x84, 0x8C, 0x94, 0x9C, 0xA4, 0xAC, 0xB4, 0xBC, 0x1A4, 0x1AC, 0x1B4, 0x1BC}; +STATIC CONST UINT16 ROMDATA MmioBaseLimitHiRegOffset[MMIO_REG_PAIR_NUM] = {0x180, 0x184, 0x188, 0x18C, 0x190, 0x194, 0x198, 0x19C, 0x1C0, 0x1C4, 0x1C8, 0x1CC}; +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------*/ +/** + * BSC entry point for for adding MMIO map + * + * program MMIO base/limit registers + * + * @param[in] MmioMapServices MMIO map manager services. + * @param[in] AmdAddMmioParams Pointer to a data structure containing the parameter information. + * + * @retval AGESA_STATUS AGESA_ERROR - The requested range could not be added because there are not + * enough mapping resources. + * AGESA_BOUNDS_CHK - One or more input parameters are invalid. For example, the + * TargetAddress does not correspond to any device in the system. + * AGESA_SUCCESS - Adding MMIO map succeeds + */ +AGESA_STATUS +STATIC +cpuF15AddingMmioMap ( + IN MMIO_MAP_FAMILY_SERVICES *MmioMapServices, + IN AMD_ADD_MMIO_PARAMS AmdAddMmioParams + ) +{ + UINT8 i; + UINT8 j; + UINT8 Socket; + UINT8 Module; + UINT8 MmioPair; + UINT8 ConfMapRange; + AGESA_STATUS IgnoredSts; + PCI_ADDR PciAddress; + MMIO_BASE_LOW MmioBaseLow; + MMIO_LIMIT_LOW MmioLimitLow; + MMIO_BASE_LIMIT_HI MmioBaseLimitHi; + MMIO_RANGE MmioRange[MMIO_REG_PAIR_NUM]; + MMIO_RANGE MmioRangeTemp; + MMIO_RANGE NewMmioRange; + CONFIGURATION_MAP ConfMapRegister; + + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, FUNC_1, MmioBaseLowRegOffset[0]); + IDS_HDT_CONSOLE (MAIN_FLOW, "MMIO map configuration before merging:\n"); + IDS_HDT_CONSOLE (MAIN_FLOW, " Base Limit NP RE WE Lock DstNode DstLink DstSubLink\n"); + for (MmioPair = 0; MmioPair < MMIO_REG_PAIR_NUM; MmioPair++) { + // MMIO base low + PciAddress.Address.Register = MmioBaseLowRegOffset[MmioPair]; + LibAmdPciRead (AccessWidth32, PciAddress, &MmioBaseLow, &(AmdAddMmioParams.StdHeader)); + // MMIO limit low + PciAddress.Address.Register = MmioLimitLowRegOffset[MmioPair]; + LibAmdPciRead (AccessWidth32, PciAddress, &MmioLimitLow, &(AmdAddMmioParams.StdHeader)); + // MMIO base/limit high + PciAddress.Address.Register = MmioBaseLimitHiRegOffset[MmioPair]; + LibAmdPciRead (AccessWidth32, PciAddress, &MmioBaseLimitHi, &(AmdAddMmioParams.StdHeader)); + // get MMIO info + MmioRange[MmioPair].Base = (MmioBaseLow.MmioBase << 16) | (((UINT64) MmioBaseLimitHi.MmioBase) << 40); + MmioRange[MmioPair].Limit = ((MmioLimitLow.MmioLimit << 16) | (((UINT64) MmioBaseLimitHi.MmioLimit) << 40)) + 0x10000; + MmioRange[MmioPair].Attribute.MmioPostedRange = (UINT8) MmioLimitLow.NP; + MmioRange[MmioPair].Attribute.MmioReadableRange = (UINT8) MmioBaseLow.RE; + MmioRange[MmioPair].Attribute.MmioWritableRange = (UINT8) MmioBaseLow.WE; + MmioRange[MmioPair].Attribute.MmioSecuredRange = (UINT8) MmioBaseLow.Lock; + MmioRange[MmioPair].Destination.DstNode = MmioLimitLow.DstNode; + MmioRange[MmioPair].Destination.DstLink = MmioLimitLow.DstLink; + MmioRange[MmioPair].Destination.DstSubLink = MmioLimitLow.DstSubLink; + MmioRange[MmioPair].RangeNum = MmioPair; + MmioRange[MmioPair].Modified = FALSE; + IDS_HDT_CONSOLE (MAIN_FLOW, " %02d ", MmioPair); + IDS_HDT_CONSOLE (MAIN_FLOW, "%08x%08x %08x%08x", (MmioRange[MmioPair].Base >> 32) & 0xFFFFFFFF, + MmioRange[MmioPair].Base & 0xFFFFFFFF, + (MmioRange[MmioPair].Limit >> 32) & 0xFFFFFFFF, + MmioRange[MmioPair].Limit & 0xFFFFFFFF); + IDS_HDT_CONSOLE (MAIN_FLOW, " %s %s %s %s", MmioRange[MmioPair].Attribute.MmioPostedRange ? "Y" : "N", + MmioRange[MmioPair].Attribute.MmioReadableRange ? "Y" : "N", + MmioRange[MmioPair].Attribute.MmioWritableRange ? "Y" : "N", + MmioRange[MmioPair].Attribute.MmioSecuredRange ? "Y" : "N"); + IDS_HDT_CONSOLE (MAIN_FLOW, " %02d %02d %02d\n", MmioRange[MmioPair].Destination.DstNode, + MmioRange[MmioPair].Destination.DstLink, + MmioRange[MmioPair].Destination.DstSubLink); + } + + // parse requirement + NewMmioRange.Base = AmdAddMmioParams.BaseAddress; + NewMmioRange.Limit = AmdAddMmioParams.BaseAddress + AmdAddMmioParams.Length + 0x10000; + NewMmioRange.Attribute = AmdAddMmioParams.Attributes; + IDS_HDT_CONSOLE (MAIN_FLOW, "req %08x%08x %08x%08x\n", (NewMmioRange.Base >> 32) & 0xFFFFFFFF, + NewMmioRange.Base & 0xFFFFFFFF, + (NewMmioRange.Limit >> 32) & 0xFFFFFFFF, + NewMmioRange.Limit & 0xFFFFFFFF); + for (ConfMapRange = 0; ConfMapRange < CONF_MAP_NUM; ConfMapRange++) { + PciAddress.Address.Register = (CONF_MAP_RANGE_0 + ConfMapRange * 4); + LibAmdPciRead (AccessWidth32, PciAddress, &ConfMapRegister, &(AmdAddMmioParams.StdHeader)); + if ((ConfMapRegister.BusNumBase <= AmdAddMmioParams.TargetAddress.Address.Bus) && + (ConfMapRegister.BusNumLimit >= AmdAddMmioParams.TargetAddress.Address.Bus)) { + NewMmioRange.Destination.DstNode = ConfMapRegister.DstNode; + NewMmioRange.Destination.DstLink = ConfMapRegister.DstLink; + NewMmioRange.Destination.DstSubLink = ConfMapRegister.DstSubLink; + break; + } + } + + if (ConfMapRange == CONF_MAP_NUM) { + // AmdAddMmioParams.TargetAddress doesn't belong to any node + return AGESA_BOUNDS_CHK; + } + + // sort by base address + // range0, range1, range2, non used, non used... + for (i = 0; i < (MMIO_REG_PAIR_NUM - 1); i++) { + for (j = 0; j < (MMIO_REG_PAIR_NUM - i - 1); j++) { + if (((MmioRange[j].Base > MmioRange[j + 1].Base) && ((MmioRange[j + 1].Attribute.MmioReadableRange != 0) || (MmioRange[j + 1].Attribute.MmioWritableRange != 0))) || + (((MmioRange[j].Attribute.MmioReadableRange == 0) && (MmioRange[j].Attribute.MmioWritableRange == 0)) && + ((MmioRange[j + 1].Attribute.MmioReadableRange != 0) || (MmioRange[j + 1].Attribute.MmioWritableRange != 0)))) { + MmioRangeTemp = MmioRange[j]; + MmioRange[j] = MmioRange[j + 1]; + MmioRange[j + 1] = MmioRangeTemp; + } + } + } + + // merge the request to current setting + for (MmioPair = 0; MmioPair < MMIO_REG_PAIR_NUM; MmioPair++) { + if (MmioRange[MmioPair].Attribute.MmioReadableRange != 0 || MmioRange[MmioPair].Attribute.MmioWritableRange != 0) { + if (((NewMmioRange.Base <= MmioRange[MmioPair].Base) && (NewMmioRange.Limit >= MmioRange[MmioPair].Base)) || + ((MmioRange[MmioPair].Base <= NewMmioRange.Base) && (MmioRange[MmioPair].Limit >= NewMmioRange.Base))) { + if ((NewMmioRange.Attribute.MmioPostedRange == MmioRange[MmioPair].Attribute.MmioPostedRange) && + (NewMmioRange.Attribute.MmioReadableRange == MmioRange[MmioPair].Attribute.MmioReadableRange) && + (NewMmioRange.Attribute.MmioWritableRange == MmioRange[MmioPair].Attribute.MmioWritableRange) && + (NewMmioRange.Attribute.MmioSecuredRange == MmioRange[MmioPair].Attribute.MmioSecuredRange) && + (NewMmioRange.Destination.DstNode == MmioRange[MmioPair].Destination.DstNode) && + (NewMmioRange.Destination.DstLink == MmioRange[MmioPair].Destination.DstLink) && + (NewMmioRange.Destination.DstSubLink == MmioRange[MmioPair].Destination.DstSubLink)) { + +// Original sorted MMIO register pair defined ranges: +// ____________ ________ ____________ +// | | | | | | +// base0 limit0 base1 limit1 base2 limit2 +// Requested MMIO range: +// case 1: +// ((NewMmioRange.Base <= MmioRange[MmioPair].Base) && (NewMmioRange.Limit >= MmioRange[MmioPair].Base)) +// __________ +// | | +// new base new limit +// ____________________ +// | | +// new base new limit +// case 2: +// ((MmioRange[MmioPair].Base <= NewMmioRange.Base) && (MmioRange[MmioPair].Limit >= NewMmioRange.Base)) +// ____________ +// | | +// new base new limit + + MmioRange[MmioPair].Base = (MmioRange[MmioPair].Base <= NewMmioRange.Base) ? MmioRange[MmioPair].Base : NewMmioRange.Base; + MmioRange[MmioPair].Modified = TRUE; + for (i = 1; NewMmioRange.Limit >= MmioRange[MmioPair + i].Base; i++) { + if ((NewMmioRange.Attribute.MmioPostedRange == MmioRange[MmioPair + i].Attribute.MmioPostedRange) && + (NewMmioRange.Attribute.MmioReadableRange == MmioRange[MmioPair + i].Attribute.MmioReadableRange) && + (NewMmioRange.Attribute.MmioWritableRange == MmioRange[MmioPair + i].Attribute.MmioWritableRange) && + (NewMmioRange.Attribute.MmioSecuredRange == MmioRange[MmioPair + i].Attribute.MmioSecuredRange) && + (NewMmioRange.Destination.DstNode == MmioRange[MmioPair + i].Destination.DstNode) && + (NewMmioRange.Destination.DstLink == MmioRange[MmioPair + i].Destination.DstLink) && + (NewMmioRange.Destination.DstSubLink == MmioRange[MmioPair + i].Destination.DstSubLink)) { + MmioRange[MmioPair + i].Base = 0; + MmioRange[MmioPair + i].Limit = 0x10000; + MmioRange[MmioPair + i].Attribute.MmioReadableRange = 0; + MmioRange[MmioPair + i].Attribute.MmioWritableRange = 0; + MmioRange[MmioPair + i].Modified = TRUE; + } else if (MmioRange[MmioPair + i].Attribute.MmioReadableRange != 0 || MmioRange[MmioPair + i].Attribute.MmioWritableRange != 0) { + // Overlapped MMIO regions with different attributes are not allowed + return AGESA_ERROR; + } + } + MmioRange[MmioPair].Limit = (MmioRange[MmioPair + i - 1].Limit >= NewMmioRange.Limit) ? MmioRange[MmioPair + i - 1].Limit : NewMmioRange.Limit; + break; + } else { + // Overlapped MMIO regions with different attributes are not allowed + return AGESA_ERROR; + } + } + } else { + +// Original sorted MMIO register pair defined ranges: +// ____________ ________ ____________ +// | | | | | | +// base0 limit0 base1 limit1 base2 limit2 +// Requested MMIO range: +// case 3: +// No overlapping area with the original ranges +// ____________ +// | | +// new base new limit +// ______________ +// | | +// new base new limit + + MmioRange[MmioPair].Base = NewMmioRange.Base; + MmioRange[MmioPair].Limit = NewMmioRange.Limit; + MmioRange[MmioPair].Attribute = NewMmioRange.Attribute; + MmioRange[MmioPair].Destination = NewMmioRange.Destination; + MmioRange[MmioPair].Modified = TRUE; + + break; + } + } + + if (MmioPair == MMIO_REG_PAIR_NUM) { + return AGESA_ERROR; + } + + // write back MMIO base/limit + IDS_HDT_CONSOLE (MAIN_FLOW, "MMIO map configuration after merging:\n"); + IDS_HDT_CONSOLE (MAIN_FLOW, " Base Limit NP RE WE Lock DstNode DstLink DstSubLink\n"); + for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { + if (IsProcessorPresent (Socket, &(AmdAddMmioParams.StdHeader))) { + for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { + if (GetPciAddress (&(AmdAddMmioParams.StdHeader), Socket, Module, &PciAddress, &IgnoredSts)) { + PciAddress.Address.Function = FUNC_1; + for (MmioPair = 0; MmioPair < MMIO_REG_PAIR_NUM; MmioPair++) { + IDS_HDT_CONSOLE (MAIN_FLOW, " %02d ", MmioPair); + IDS_HDT_CONSOLE (MAIN_FLOW, "%08x%08x %08x%08x", (MmioRange[MmioPair].Base >> 32) & 0xFFFFFFFF, + MmioRange[MmioPair].Base & 0xFFFFFFFF, + (MmioRange[MmioPair].Limit >> 32) & 0xFFFFFFFF, + MmioRange[MmioPair].Limit & 0xFFFFFFFF); + IDS_HDT_CONSOLE (MAIN_FLOW, " %s %s %s %s", MmioRange[MmioPair].Attribute.MmioPostedRange ? "Y" : "N", + MmioRange[MmioPair].Attribute.MmioReadableRange ? "Y" : "N", + MmioRange[MmioPair].Attribute.MmioWritableRange ? "Y" : "N", + MmioRange[MmioPair].Attribute.MmioSecuredRange ? "Y" : "N"); + IDS_HDT_CONSOLE (MAIN_FLOW, " %02d %02d %02d\n", MmioRange[MmioPair].Destination.DstNode, + MmioRange[MmioPair].Destination.DstLink, + MmioRange[MmioPair].Destination.DstSubLink); + if (MmioRange[MmioPair].Modified) { + // MMIO base low + PciAddress.Address.Register = MmioBaseLowRegOffset[MmioRange[MmioPair].RangeNum]; + LibAmdPciRead (AccessWidth32, PciAddress, &MmioBaseLow, &(AmdAddMmioParams.StdHeader)); + if (MmioBaseLow.Lock == 1) { + return AGESA_ERROR; + } + // Disable RE/WE before changing the address range + MmioBaseLow.RE = 0; + MmioBaseLow.WE = 0; + S3_SAVE_PCI_WRITE (&(AmdAddMmioParams.StdHeader), PciAddress, AccessWidth32, &MmioBaseLow); + LibAmdPciWrite (AccessWidth32, PciAddress, &MmioBaseLow, &(AmdAddMmioParams.StdHeader)); + + IDS_HDT_CONSOLE (MAIN_FLOW, " Reconfiguring offset %X\n", MmioBaseLowRegOffset[MmioRange[MmioPair].RangeNum]); + MmioBaseLow.MmioBase = (UINT32) (MmioRange[MmioPair].Base >> 16) & 0xFFFFFFul; + MmioBaseLow.RE = MmioRange[MmioPair].Attribute.MmioReadableRange; + MmioBaseLow.WE = MmioRange[MmioPair].Attribute.MmioWritableRange; + S3_SAVE_PCI_WRITE (&(AmdAddMmioParams.StdHeader), PciAddress, AccessWidth32, &MmioBaseLow); + LibAmdPciWrite (AccessWidth32, PciAddress, &MmioBaseLow, &(AmdAddMmioParams.StdHeader)); + + // MMIO limit low + IDS_HDT_CONSOLE (MAIN_FLOW, " Reconfiguring offset %X\n", MmioLimitLowRegOffset[MmioRange[MmioPair].RangeNum]); + PciAddress.Address.Register = MmioLimitLowRegOffset[MmioRange[MmioPair].RangeNum]; + LibAmdPciRead (AccessWidth32, PciAddress, &MmioLimitLow, &(AmdAddMmioParams.StdHeader)); + MmioLimitLow.MmioLimit = (UINT32) ((MmioRange[MmioPair].Limit - 1) >> 16) & 0xFFFFFFul; + MmioLimitLow.NP = MmioRange[MmioPair].Attribute.MmioPostedRange; + MmioLimitLow.DstNode = MmioRange[MmioPair].Destination.DstNode; + MmioLimitLow.DstLink = MmioRange[MmioPair].Destination.DstLink; + MmioLimitLow.DstSubLink = MmioRange[MmioPair].Destination.DstSubLink; + S3_SAVE_PCI_WRITE (&(AmdAddMmioParams.StdHeader), PciAddress, AccessWidth32, &MmioLimitLow); + LibAmdPciWrite (AccessWidth32, PciAddress, &MmioLimitLow, &(AmdAddMmioParams.StdHeader)); + + // MMIO base/limit high + IDS_HDT_CONSOLE (MAIN_FLOW, " Reconfiguring offset %X\n", MmioBaseLimitHiRegOffset[MmioRange[MmioPair].RangeNum]); + PciAddress.Address.Register = MmioBaseLimitHiRegOffset[MmioRange[MmioPair].RangeNum]; + LibAmdPciRead (AccessWidth32, PciAddress, &MmioBaseLimitHi, &(AmdAddMmioParams.StdHeader)); + MmioBaseLimitHi.MmioBase = (UINT32) (MmioRange[MmioPair].Base >> 40) & 0xFFul; + MmioBaseLimitHi.MmioLimit = (UINT32) ((MmioRange[MmioPair].Limit - 1) >> 40) & 0xFFul; + S3_SAVE_PCI_WRITE (&(AmdAddMmioParams.StdHeader), PciAddress, AccessWidth32, &MmioBaseLimitHi); + LibAmdPciWrite (AccessWidth32, PciAddress, &MmioBaseLimitHi, &(AmdAddMmioParams.StdHeader)); + } + } + } + } + } + } + return AGESA_SUCCESS; +} + +CONST MMIO_MAP_FAMILY_SERVICES ROMDATA F15MmioMapSupport = +{ + 0, + cpuF15AddingMmioMap +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.h new file mode 100644 index 0000000..ae74ee8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.h @@ -0,0 +1,145 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 MMIO map manager + * + * manage MMIO base/limit registers. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15 + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_F15_MMIO_MAP_H_ +#define _CPU_F15_MMIO_MAP_H_ + + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ +#define MMIO_REG_PAIR_NUM 12 + +#define CONF_MAP_RANGE_0 0xE0 +#define CONF_MAP_RANGE_1 0xE4 +#define CONF_MAP_RANGE_2 0xE8 +#define CONF_MAP_RANGE_3 0xEC +#define CONF_MAP_NUM 4 +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ +/// MMIO base low +typedef struct { + UINT32 RE:1; ///< Read enable + UINT32 WE:1; ///< Write enable + UINT32 CpuDis:1; ///< CPU Disable + UINT32 Lock:1; ///< Lock + UINT32 :4; ///< Reserved + UINT32 MmioBase:24; ///< MMIO base address register bits[39:16] +} MMIO_BASE_LOW; + +/// MMIO limit low +typedef struct { + UINT32 DstNode:3; ///< Destination node ID bits + UINT32 :1; ///< Reserved + UINT32 DstLink:2; ///< Destination link ID + UINT32 DstSubLink:1; ///< Destination sublink + UINT32 NP:1; ///< Non-posted + UINT32 MmioLimit:24; ///< MMIO limit address register bits[39:16] +} MMIO_LIMIT_LOW; + +/// MMIO base/limit high +typedef struct { + UINT32 MmioBase:8; ///< MMIO base address register bits[47:40] + UINT32 :8; ///< Reserved + UINT32 MmioLimit:8; ///< MMIO limit address register bits[47:40] + UINT32 :8; ///< Reserved +} MMIO_BASE_LIMIT_HI; + +/// MMIO base/limit high +typedef struct { + UINT32 RE:1; ///< Read enable + UINT32 WE:1; ///< Write enable + UINT32 DevCmpEn:1; ///< Device number compare mode enable + UINT32 :1; ///< Reserved + UINT32 DstNode:3; ///< Destination node ID bits + UINT32 :1; ///< Reserved + UINT32 DstLink:2; ///< Destination link ID + UINT32 DstSubLink:1; ///< Destination sublink + UINT32 :5; ///< Reserved + UINT32 BusNumBase:8; ///< Bus number base bits + UINT32 BusNumLimit:8; ///< Bus number limit bits +} CONFIGURATION_MAP; + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ + +#endif // _CPU_F15_MMIO_MAP_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MsrTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MsrTables.c new file mode 100644 index 0000000..8c7474f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MsrTables.c @@ -0,0 +1,161 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 MSR tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15 + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "Table.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15MSRTABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F15MsrRegisters[] = +{ +// M S R T a b l e s +// ---------------------- + +// MSR_HWCR (0xC0010015) +// bit[4] = 1 + { + MsrRegister, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull) // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MSR_HWCR, // MSR Address + 0x0000000000000010, // OR Mask + 0x0000000000000010, // NAND Mask + }} + }, +// MSR_NB_CFG (0xC001001F) +// bit[54] InitApicIdCpuIdLo = 1 + { + MsrRegister, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull) // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MSR_NB_CFG, // MSR Address + 0x0040000000000000, // OR Mask + 0x0040000000000000, // NAND Mask + }} + }, +// This MSR should be set after the code that most errata would be applied in +// MSR_MC0_CTL (0x00000400) +// bits[63:0] = 0xFFFFFFFFFFFFFFFF + { + MsrRegister, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull) // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MSR_MC0_CTL, // MSR Address + 0xFFFFFFFFFFFFFFFF, // OR Mask + 0xFFFFFFFFFFFFFFFF, // NAND Mask + }} + } +}; + +CONST REGISTER_TABLE ROMDATA F15MsrRegisterTable = { + AllCores, + (sizeof (F15MsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + (TABLE_ENTRY_FIELDS *)F15MsrRegisters, +}; + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PciTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PciTables.c new file mode 100644 index 0000000..6ef2ef5 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PciTables.c @@ -0,0 +1,216 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 PCI tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15 + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "Table.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15PCITABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +// P C I T a b l e s +// ---------------------- + +STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F15PciRegisters[] = +{ +// F2x1B0 - Extended Memory Controller Configuration Low +// bits[10:8], CohPrefPrbLmt = 1 + { + PciRegister, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull) // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_2, 0x1B0), // Address + 0x00000100, // regData + 0x00000700, // regMask + }} + }, + +// Function 3 - Misc. Control + +// F3x6C - Data Buffer Count +// bits[30:28] IsocRspDBC = 1 +// bits[18:16] UpRspDBC = 1 +// bits[7:6] DnRspDBC = 1 +// bits[5:4] DnReqDBC = 1 +// bits[2:0] UpReqDBC = 2 + { + PciRegister, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull) // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C), // Address + 0x10010052, // regData + 0x700700F7, // regMask + }} + }, +// F3xA0 - Power Control Miscellaneous +// bits[13:11] PllLockTime = 1 + { + PciRegister, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull) // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address + 0x00000800, // regData + 0x00003800, // regMask + }} + }, +// F3xA4 - Reported Temperature Control +// bits[12:8] PerStepTimeDn = 0x0F +// bits[7] TmpSlewDnEn = 1 +// bits[6:5] TmpMaxDiffUp = 3 +// bits[4:0] PerStepTimeUp = 0x0F + { + PciRegister, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull) // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA4), // Address + 0x00000FEF, // regData + 0x00001FFF, // regMask + }} + }, +// F3x1CC - IBS Control +// bits[8] LvtOffsetVal = 1 +// bits[3:0] LvtOffset = 0 + { + PciRegister, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull) // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1CC), // Address + 0x00000100, // regData + 0x0000010F, // regMask + }} + }, +// F4x15C - Core Performance Boost Control +// bits[1:0] BoostSrc = 0 + { + PciRegister, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull) // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_4, 0x15C), // Address + 0x00000000, // regData + 0x00000003, // regMask + }} + }, +}; + +CONST REGISTER_TABLE ROMDATA F15PciRegisterTable = { + PrimaryCores, + (sizeof (F15PciRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + F15PciRegisters, +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PowerCheck.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PowerCheck.c new file mode 100644 index 0000000..b52931a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PowerCheck.c @@ -0,0 +1,466 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 P-State power check + * + * Performs the "Processor-Systemboard Power Delivery Compatibility Check" as + * described in the BKDG. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15 + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuF15PowerMgmt.h" +#include "cpuRegisters.h" +#include "cpuApicUtilities.h" +#include "cpuFamilyTranslation.h" +#include "cpuF15PowerCheck.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "OptionMultiSocket.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15POWERCHECK_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +F15PmPwrCheckCore ( + IN VOID *ErrorData, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +F15PmPwrChkCopyPstate ( + IN UINT8 Dest, + IN UINT8 Src, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; +/*---------------------------------------------------------------------------------------*/ +/** + * Family 15h core 0 entry point for performing the family 15h Processor- + * Systemboard Power Delivery Check. + * + * The steps are as follows: + * 1. Starting with P0, loop through all P-states until a passing state is + * found. A passing state is one in which the current required by the + * CPU is less than the maximum amount of current that the system can + * provide to the CPU. If P0 is under the limit, no further action is + * necessary. + * 2. If at least one P-State is under the limit & at least one P-State is + * over the limit, the BIOS must: + * a. If the processor's current P-State is disabled by the power check, + * then the BIOS must request a transition to an enabled P-state + * using MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate] + * to reflect the new value. + * b. Copy the contents of the enabled P-state MSRs to the highest + * performance P-state locations. + * c. Request a P-state transition to the P-state MSR containing the + * COF/VID values currently applied. + * d. If a subset of boosted P-states are disabled, then copy the contents + * of the highest performance boosted P-state still enabled to the + * boosted P-states that have been disabled. + * e. If all boosted P-states are disabled, then program D18F4x15C[BoostSrc] + * to zero. + * f. Adjust the following P-state parameters affected by the P-state + * MSR copy by subtracting the number of P-states that are disabled + * by the power check. + * 1. F3x64[HtcPstateLimit] + * 2. F3x68[SwPstateLimit] + * 3. F3xDC[PstateMaxVal] + * 3. If all P-States are over the limit, the BIOS must: + * a. If the processor's current P-State is !=F3xDC[PstateMaxVal], then + * write F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] and wait for + * MSRC001_0063[CurPstate] to reflect the new value. + * b. If MSRC001_0061[PstateMaxVal]!=000b, copy the contents of the P-state + * MSR pointed to by F3xDC[PstateMaxVal] to the software P0 MSR. + * Write 000b to MSRC001_0062[PstateCmd] and wait for MSRC001_0063 + * [CurPstate] to reflect the new value. + * c. Adjust the following P-state parameters to zero: + * 1. F3x64[HtcPstateLimit] + * 2. F3x68[SwPstateLimit] + * 3. F3xDC[PstateMaxVal] + * d. Program D18F4x15C[BoostSrc] to zero. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] CpuEarlyParams Service parameters + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +F15PmPwrCheck ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 DisPsNum; + UINT8 PsMaxVal; + UINT8 Pstate; + UINT32 ProcIddMax; + UINT32 LocalPciRegister; + UINT32 Socket; + UINT32 Module; + UINT32 Core; + UINT32 AndMask; + UINT32 OrMask; + UINT32 PstateLimit; + PCI_ADDR PciAddress; + UINT64 LocalMsrRegister; + AP_TASK TaskPtr; + AGESA_STATUS IgnoredSts; + PWRCHK_ERROR_DATA ErrorData; + UINT32 NumModules; + UINT32 HighCore; + UINT32 LowCore; + UINT32 ModuleIndex; + + + // get the socket number + IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); + ErrorData.SocketNumber = (UINT8) Socket; + + ASSERT (Core == 0); + + // get the Max P-state value + for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) { + LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &LocalMsrRegister, StdHeader); + if (((F15_PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) { + break; + } + } + + ErrorData.HwPstateNumber = (UINT8) (PsMaxVal + 1); + + // Starting with P0, loop through all P-states until a passing state is + // found. A passing state is one in which the current required by the + // CPU is less than the maximum amount of current that the system can + // provide to the CPU. If P0 is under the limit, no further action is + // necessary. + DisPsNum = 0; + for (Pstate = 0; Pstate < ErrorData.HwPstateNumber; Pstate++) { + if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, Pstate, &ProcIddMax, StdHeader)) { + if (ProcIddMax > CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit) { + // Add to event log the Pstate that exceeded the current limit + PutEventLog (AGESA_WARNING, + CPU_EVENT_PM_PSTATE_OVERCURRENT, + Socket, Pstate, 0, 0, StdHeader); + DisPsNum++; + } else { + break; + } + } + } + + ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisPsNum); + + if (ErrorData.AllowablePstateNumber == 0) { + PutEventLog (AGESA_FATAL, + CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT, + Socket, 0, 0, 0, StdHeader); + } + + if (DisPsNum != 0) { + GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); + PciAddress.Address.Function = FUNC_4; + PciAddress.Address.Register = CPB_CTRL_REG; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F4x15C + ErrorData.NumberOfBoostStates = (UINT8) ((F15_CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates; + + if (DisPsNum >= ErrorData.NumberOfBoostStates) { + // If all boosted P-states are disabled, then program D18F4x15C[BoostSrc] to zero. + AndMask = 0xFFFFFFFF; + ((F15_CPB_CTRL_REGISTER *) &AndMask)->BoostSrc = 0; + OrMask = 0x00000000; + OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F4x15C + + ErrorData.NumberOfSwPstatesDisabled = DisPsNum - ErrorData.NumberOfBoostStates; + } else { + ErrorData.NumberOfSwPstatesDisabled = 0; + } + + NumModules = GetPlatformNumberOfModules (); + + // Only execute this loop if this is an MCM. + if (NumModules > 1) { + + // Since the P-State MSRs are shared across a + // node, we only need to set one core in the node for the modified number of supported p-states + // to be reported across all of the cores in the module. + TaskPtr.FuncAddress.PfApTaskI = F15PmPwrCheckCore; + TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PWRCHK_ERROR_DATA); + TaskPtr.DataTransfer.DataPtr = &ErrorData; + TaskPtr.DataTransfer.DataTransferFlags = 0; + TaskPtr.ExeFlags = WAIT_FOR_CORE; + + for (ModuleIndex = 0; ModuleIndex < NumModules; ModuleIndex++) { + // Execute the P-State reduction code on the module's primary core only. + // Skip this code for the BSC's module. + if (ModuleIndex != Module) { + if (GetGivenModuleCoreRange (Socket, ModuleIndex, &LowCore, &HighCore, StdHeader)) { + ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)LowCore, &TaskPtr, StdHeader); + } + } + } + } + + // Path for SCM and the BSC + F15PmPwrCheckCore (&ErrorData, StdHeader); + + // Final Step + // F3x64[HtPstatelimit] -= disPsNum + // F3x68[SwPstateLimit] -= disPsNum + // F3xDC[PstateMaxVal] -= disPsNum + + PciAddress.Address.Function = FUNC_3; + PciAddress.Address.Register = HTC_REG; + AndMask = 0xFFFFFFFF; + ((HTC_REGISTER *) &AndMask)->HtcPstateLimit = 0; + OrMask = 0x00000000; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x64 + PstateLimit = ((HTC_REGISTER *) &LocalPciRegister)->HtcPstateLimit; + if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) { + PstateLimit -= ErrorData.NumberOfSwPstatesDisabled; + ((HTC_REGISTER *) &OrMask)->HtcPstateLimit = PstateLimit; + } + OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x64 + + PciAddress.Address.Register = SW_PS_LIMIT_REG; + AndMask = 0xFFFFFFFF; + ((SW_PS_LIMIT_REGISTER *) &AndMask)->SwPstateLimit = 0; + OrMask = 0x00000000; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x68 + PstateLimit = ((SW_PS_LIMIT_REGISTER *) &LocalPciRegister)->SwPstateLimit; + if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) { + PstateLimit -= ErrorData.NumberOfSwPstatesDisabled; + ((SW_PS_LIMIT_REGISTER *) &OrMask)->SwPstateLimit = PstateLimit; + } + OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x68 + + PciAddress.Address.Register = CPTC2_REG; + AndMask = 0xFFFFFFFF; + ((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->PstateMaxVal = 0; + OrMask = 0x00000000; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xDC + PstateLimit = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal; + if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) { + PstateLimit -= ErrorData.NumberOfSwPstatesDisabled; + ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->PstateMaxVal = PstateLimit; + } + OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC + } +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Core-level error handler called if any p-states were determined to be out + * of range for the mother board. + * + * This function implements steps 2a-c and 3a-c on each core. + * + * @param[in] ErrorData Details about the error condition. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +STATIC +F15PmPwrCheckCore ( + IN VOID *ErrorData, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + UINT8 HwPsMaxVal; + UINT8 SwPsMaxVal; + UINT8 HwDisPsNum; + UINT8 CurrentSwPs; + UINT8 PsDisableCount; + UINT64 LocalMsrRegister; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) { + // P-state MSRs are shared, so only 1 core per compute unit needs to perform this + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + HwPsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1); + HwDisPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - + ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber); + + LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader); + CurrentSwPs = (UINT8) (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate); + LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader); + SwPsMaxVal = (UINT8) (((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal); + PsDisableCount = 0; + + if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) { + // All P-States are over the limit. + + // Step 1 + // Transition to Pstate Max if not there already + if (CurrentSwPs != SwPsMaxVal) { + FamilySpecificServices->TransitionPstate (FamilySpecificServices, SwPsMaxVal, (BOOLEAN) TRUE, StdHeader); + } + + // Step 2 + // If Pstate Max is not P0, copy Pstate max contents to P0 and switch + // to P0. + if (SwPsMaxVal != 0) { + F15PmPwrChkCopyPstate (((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates, HwPsMaxVal, StdHeader); + FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader); + } + + // Disable all SW P-states except P0 + PsDisableCount = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled - 1; + } else { + // At least one P-State is under the limit & at least one P-State is + // over the limit. + if (((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates > HwDisPsNum) { + // A subset of boosted P-states are disabled. Copy the contents of the + // highest performance boosted P-state still enabled to the boosted + // P-states that have been disabled. + for (i = 0; i < HwDisPsNum; i++) { + F15PmPwrChkCopyPstate (i, HwDisPsNum, StdHeader); + } + } else if (((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled != 0) { + // Move remaining P-state register(s) up + // Step 1 + // Transition to a valid Pstate if current Pstate has been disabled + if (CurrentSwPs < ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled) { + FamilySpecificServices->TransitionPstate (FamilySpecificServices, ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled, (BOOLEAN) TRUE, StdHeader); + CurrentSwPs = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled; + } + + // Step 2 + // Move enabled Pstates up and disable the remainder + for (i = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates; (i + ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled) <= HwPsMaxVal; i++) { + F15PmPwrChkCopyPstate (i, (i + ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled), StdHeader); + } + + // Step 3 + // Transition to current COF/VID at shifted location + CurrentSwPs = (CurrentSwPs - ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled); + FamilySpecificServices->TransitionPstate (FamilySpecificServices, CurrentSwPs, (BOOLEAN) TRUE, StdHeader); + + // Disable the appropriate number of P-states + PsDisableCount = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled; + } + } + // Disable the appropriate P-states if any, starting from HW Pmin + for (i = 0; i < PsDisableCount; i++) { + FamilySpecificServices->DisablePstate (FamilySpecificServices, (HwPsMaxVal - i), StdHeader); + } + } +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Copies the contents of one P-State MSR to another. + * + * @param[in] Dest Destination p-state number + * @param[in] Src Source p-state number + * @param[in] StdHeader Config handle for library and services + * + */ +VOID +STATIC +F15PmPwrChkCopyPstate ( + IN UINT8 Dest, + IN UINT8 Src, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 LocalMsrRegister; + + LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &LocalMsrRegister, StdHeader); + LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &LocalMsrRegister, StdHeader); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PowerCheck.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PowerCheck.h new file mode 100644 index 0000000..3993eaf --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PowerCheck.h @@ -0,0 +1,110 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Power related functions and structures + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15 + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_F15_POWER_CHECK_H_ +#define _CPU_F15_POWER_CHECK_H_ + + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ +/// Power Check Error Data +typedef struct { + UINT8 SocketNumber; ///< Socket Number + UINT8 HwPstateNumber; ///< Number of hardware P-states + UINT8 AllowablePstateNumber; ///< Number of allowable P-states + UINT8 NumberOfBoostStates; ///< Number of boosted P-states + UINT8 NumberOfSwPstatesDisabled; ///< Number of software P-states disabled +} PWRCHK_ERROR_DATA; + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ +VOID +F15PmPwrCheck ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif // _CPU_F15_POWER_CHECK_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PowerMgmt.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PowerMgmt.h new file mode 100644 index 0000000..7586898 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15PowerMgmt.h @@ -0,0 +1,320 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Power Management related registers defination + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15 + * @e $Revision: 64491 $ @e $Date: 2012-01-23 12:37:30 -0600 (Mon, 23 Jan 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPUF15POWERMGMT_H_ +#define _CPUF15POWERMGMT_H_ + +/* + * Family 15h CPU Power Management MSR definitions + * + */ + + +/* Last Branch From IP Register 0x000001DB */ +#define MSR_BR_FROM 0x000001DBul + +/* P-state Current Limit Register 0xC0010061 */ +#define MSR_PSTATE_CURRENT_LIMIT 0xC0010061ul // F15 Shared + +/// Pstate Current Limit MSR Register +typedef struct { + UINT64 CurPstateLimit:3; ///< Current Pstate Limit + UINT64 :1; ///< Reserved + UINT64 PstateMaxVal:3; ///< Pstate Max Value + UINT64 :57; ///< Reserved +} PSTATE_CURLIM_MSR; + + +/* P-state Control Register 0xC0010062 */ +#define MSR_PSTATE_CTL 0xC0010062ul // F15 Shared + +/// Pstate Control MSR Register +typedef struct { + UINT64 PstateCmd:3; ///< Pstate change command + UINT64 :61; ///< Reserved +} PSTATE_CTRL_MSR; + + +/* P-state Status Register 0xC0010063 */ +#define MSR_PSTATE_STS 0xC0010063ul + +/// Pstate Status MSR Register +typedef struct { + UINT64 CurPstate:3; ///< Current Pstate + UINT64 :61; ///< Reserved +} PSTATE_STS_MSR; + + +/* P-state Registers 0xC001006[B:4] */ +#define MSR_PSTATE_0 0xC0010064ul +#define MSR_PSTATE_1 0xC0010065ul +#define MSR_PSTATE_2 0xC0010066ul +#define MSR_PSTATE_3 0xC0010067ul +#define MSR_PSTATE_4 0xC0010068ul +#define MSR_PSTATE_5 0xC0010069ul +#define MSR_PSTATE_6 0xC001006Aul +#define MSR_PSTATE_7 0xC001006Bul + +#define PS_REG_BASE MSR_PSTATE_0 /* P-state Register base */ +#define PS_MAX_REG MSR_PSTATE_7 /* Maximum P-State Register */ +#define PS_MIN_REG MSR_PSTATE_0 /* Minimum P-State Register */ +#define NM_PS_REG 8 /* number of P-state MSR registers */ + +/// P-state MSR with common field +typedef struct { + UINT64 :63; ///< CpuFid + UINT64 PsEnable:1; ///< Pstate Enable +} F15_PSTATE_MSR; + + +/* C-state Address Register 0xC0010073 */ +#define MSR_CSTATE_ADDRESS 0xC0010073ul + +/// C-state Address MSR Register +typedef struct { + UINT64 CstateAddr:16; ///< C-state address + UINT64 :48; ///< Reserved +} CSTATE_ADDRESS_MSR; + + +/* + * Family 15h CPU Power Management PCI definitions + * + */ + +/* Extended Memory Controller Configuration Low Register F2x1B0 */ +#define EXT_MEMCTRL_CFG_LOW_REG 0x1B0 + +/// Extended Memory Controller Configuration Low PCI Register +typedef struct { + UINT32 AdapPrefMissRatio:2; ///< Adaptive prefetch miss ratio + UINT32 AdapPrefPositiveStep:2; ///< Adaptive prefetch positive step + UINT32 AdapPrefNegativeStep:2; ///< Adaptive prefetch negative step + UINT32 :2; ///< Reserved + UINT32 CohPrefPrbLmt:3; ///< Coherent prefetch probe limit + UINT32 DisIoCohPref:1; ///< Disable coherent prefetched for IO + UINT32 EnSplitDctLimits:1; ///< Split DCT write limits enable + UINT32 SpecPrefDis:1; ///< Speculative prefetch disable + UINT32 SpecPrefMis:1; ///< Speculative prefetch predict miss + UINT32 SpecPrefThreshold:3; ///< Speculative prefetch threshold + UINT32 :4; ///< Reserved + UINT32 PrefFourConf:3; ///< Prefetch four-ahead confidence + UINT32 PrefFiveConf:3; ///< Prefetch five-ahead confidence + UINT32 DcqBwThrotWm:4; ///< Dcq bandwidth throttle watermark +} EXT_MEMCTRL_CFG_LOW_REGISTER; + + +/* Hardware thermal control register F3x64 */ +#define HTC_REG 0x64 +#define HTC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, HTC_REG)) + +/// Hardware Thermal Control PCI Register +typedef struct { + UINT32 HtcEn:1; ///< HTC Enable + UINT32 :3; ///< Reserved + UINT32 HtcAct:1; ///< HTC Active State + UINT32 HtcActSts:1; ///< HTC Active Status + UINT32 PslApicHiEn:1; ///< P-state limit higher APIC interrupt enable + UINT32 PslApicLoEn:1; ///< P-state limit lower APIC interrupt enable + UINT32 :8; ///< Reserved + UINT32 HtcTmpLmt:7; ///< HTC temperature limit + UINT32 HtcSlewSel:1; ///< HTC slew-controlled temp select + UINT32 HtcHystLmt:4; ///< HTC hysteresis + UINT32 HtcPstateLimit:3; ///< HTC P-state limit select + UINT32 :1; ///< Reserved +} HTC_REGISTER; + + +/* Software P-state limit register F3x68 */ +#define SW_PS_LIMIT_REG 0x68 + +/// Software P-state Limit PCI Register +typedef struct { + UINT32 :5; ///< Reserved + UINT32 SwPstateLimitEn:1; ///< Software P-state limit enable + UINT32 :22; ///< Reserved + UINT32 SwPstateLimit:3; ///< HTC P-state limit select + UINT32 :1; ///< Reserved +} SW_PS_LIMIT_REGISTER; + +/* ACPI Power State Control Registers F3x84:80 */ + +/// System Management Action Field (SMAF) Register +typedef struct { + UINT8 CpuPrbEn:1; ///< CPU direct probe enable + UINT8 NbLowPwrEn:1; ///< Northbridge low-power enable + UINT8 NbGateEn:1; ///< Northbridge gate enable + UINT8 Reserved:2; ///< Reserved + UINT8 ClkDivisor:3; ///< Clock divisor +} SMAF_REGISTER; + +/// union type for ACPI State SMAF setting +typedef union { + UINT8 SMAFValue; ///< SMAF raw value + SMAF_REGISTER SMAF; ///< SMAF structure +} ACPI_STATE_SMAF; + +/// ACPI Power State Control Register F3x80 +typedef struct { + ACPI_STATE_SMAF C2; ///< [7:0] SMAF Code 000b - C2 + ACPI_STATE_SMAF C1eLinkInit; ///< [15:8] SMAF Code 001b - C1e or Link init + ACPI_STATE_SMAF SmafAct2; ///< [23:16] SMAF Code 010b + ACPI_STATE_SMAF S1; ///< [31:24] SMAF Code 011b - S1 +} ACPI_PSC_0_REGISTER; + +/// ACPI Power State Control Register F3x84 +typedef struct { + ACPI_STATE_SMAF S3; ///< [7:0] SMAF Code 100b - S3 + ACPI_STATE_SMAF Throttling; ///< [15:8] SMAF Code 101b - Throttling + ACPI_STATE_SMAF S4S5; ///< [23:16] SMAF Code 110b - S4/S5 + ACPI_STATE_SMAF C1; ///< [31:24] SMAF Code 111b - C1 +} ACPI_PSC_4_REGISTER; + + +/* Popup P-state Register F3xA8 */ +#define POPUP_PSTATE_REG 0xA8 +#define POPUP_PSTATE_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, POPUP_PSTATE_REG)) + +/// Popup P-state Register +typedef struct { + UINT32 :29; ///< Reserved + UINT32 PopDownPstate:3; ///< PopDownPstate +} POPUP_PSTATE_REGISTER; + + +/* Clock Power/Timing Control 2 Register F3xDC */ +#define CPTC2_REG 0xDC +#define CPTC2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC2_REG)) + +/// Clock Power Timing Control 2 PCI Register +typedef struct { + UINT32 :8; ///< Reserved + UINT32 PstateMaxVal:3; ///< P-state maximum value + UINT32 :1; ///< Reserved + UINT32 NbsynPtrAdj:3; ///< NB/Core sync FIFO ptr adjust + UINT32 :1; ///< Reserved + UINT32 CacheFlushOnHaltCtl:3; ///< Cache flush on halt control + UINT32 CacheFlushOnHaltTmr:7; ///< Cache flush on halt timer + UINT32 IgnCpuPrbEn:1; ///< ignore CPU probe enable + UINT32 :5; ///< Reserved +} CLK_PWR_TIMING_CTRL2_REGISTER; + + +/* Core Performance Boost Control Register D18F4x15C */ +#define CPB_CTRL_REG 0x15C +#define CPB_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPB_CTRL_REG)) + +/// Core Performance Boost Control Register of Family 15h common aceess +typedef struct { + UINT32 BoostSrc:2; ///< Boost source + UINT32 NumBoostStates:3; ///< Number of boosted states + UINT32 :2; ///< Reserved + UINT32 ApmMasterEn:1; ///< APM master enable + UINT32 :23; ///< Reserved + UINT32 BoostLock:1; ///< +} F15_CPB_CTRL_REGISTER; + + +#define NM_NB_PS_REG 4 /* Number of NB P-state registers */ + +/* Northbridge P-state */ +#define NB_PSTATE_0 0x160 +#define NB_PSTATE_0_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_0)) + +#define NB_PSTATE_1 0x164 +#define NB_PSTATE_1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_1)) + +#define NB_PSTATE_2 0x168 +#define NB_PSTATE_2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_2)) + +#define NB_PSTATE_3 0x16C +#define NB_PSTATE_3_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_3)) + + +/* Northbridge P-state Status */ +#define F15_NB_PSTATE_CTRL 0x170 +#define F15_NB_PSTATE_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, F15_NB_PSTATE_CTRL)) + +/// Northbridge P-state Control Register +typedef struct { + UINT32 NbPstateMaxVal:2; ///< NB P-state maximum value + UINT32 :1; ///< Reserved + UINT32 NbPstateLo:2; ///< NB P-state low + UINT32 :1; ///< Reserved + UINT32 NbPstateHi:2; ///< NB P-state high + UINT32 :1; ///< Reserved + UINT32 NbPstateThreshold:3; ///< NB P-state threshold + UINT32 :1; ///< Reserved + UINT32 NbPstateDisOnP0:1; ///< NB P-state disable on P0 + UINT32 SwNbPstateLoDis:1; ///< Software NB P-state low disable + UINT32 :17; ///< Reserved +} F15_NB_PSTATE_CTRL_REGISTER; + + +#endif /* _CPUF15POWERMGMT_H */ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Utilities.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Utilities.c new file mode 100644 index 0000000..c319a81 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Utilities.c @@ -0,0 +1,1204 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 specific utility functions. + * + * Provides numerous utility functions specific to family 15h. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15 + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuFamilyTranslation.h" +#include "cpuPstateTables.h" +#include "cpuF15PowerMgmt.h" +#include "cpuApicUtilities.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "cpuF15Utilities.h" +#include "cpuEarlyInit.h" +#include "cpuPostInit.h" +#include "cpuFeatures.h" +#include "OptionMultiSocket.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) +#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15UTILITIES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; +extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; + +// HT Phy registers used in code. +#define HT_PHY_FUSE_PROC_DLL_PROCESS_COMP_RD_SL0 0x4011 +#define HT_PHY_FUSE_PROC_DLL_PROCESS_COMP_RD_SL1 0x4411 +#define HT_PHY_LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL_RD 0x400F +#define HT_PHY_LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL_SL0 0x520F +#define HT_PHY_LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL_SL1 0x530F + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/** + * HT PHY DLL Process Compensation Lookup Table. + * + * If the hardware provides compensation values, the value is provided by accessing the bitfield + * [HiBit:LoBit]. Otherwise, a default value will be used. + * + */ +typedef struct { + UINT32 DefaultComp; ///< The default compensation value if not provided by hardware. + UINT8 CtlIndexLoBit; ///< The low bit position of the compensation value. + UINT8 CtlIndexHiBit; ///< The high bit position of the compensation value. +} HT_PHY_DLL_COMP_LOOKUP_TABLE; + +/** + * Process Compensation Fuses for HT PHY, Link Phy Receiver Process Fuse Control Register. + */ +typedef struct { + UINT32 :11; + UINT32 DllProcessComp10:2; ///< [12:11] DLL Process Comp bits [1:0], this phy's adjustment. + UINT32 DllProcessComp2:1; ///< [13] DLL Process Comp bit 2, Increment or Decrement. + UINT32 : (31 - 13); +} LINK_PHY_RECEIVER_PROCESS_FUSE_CONTROL_FIELDS; + +/// Access register as fields or uint32 value. +typedef union { + UINT32 Value; ///< 32 bit value for register access + LINK_PHY_RECEIVER_PROCESS_FUSE_CONTROL_FIELDS Fields; ///< The register bit fields +} LINK_PHY_RECEIVER_PROCESS_FUSE_CONTROL; + +/** + * Link Phy Receiver Process DLL Control Register. + */ +typedef struct { + UINT32 DllProcessFreqCtlIndex2:4; ///< [3:0] The DLL Compensation override. + UINT32 : (12 - 4); + UINT32 DllProcessFreqCtlOverride:1; ///< [12] Enable DLL Compensation overriding. + UINT32 : (31 - 12); +} LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL_FIELDS; + +/// Access register as fields or uint32 value. +typedef union { + UINT32 Value; ///< 32 bit value for register access + LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL_FIELDS Fields; ///< The register bit fields +} LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL; + +/** + * Provide the HT PHY DLL compensation value for each HT Link frequency. + * + * The HT Frequency enum is not contiguous, there are skipped values. Rather than complicate + * index calculations, add Invalid entries here marked with an invalid compensation value (invalid + * because real compensation values are 0 .. 15). + */ +CONST STATIC HT_PHY_DLL_COMP_LOOKUP_TABLE ROMDATA HtPhyDllCompLookupTable[] = { + {0xAul, 0, 3}, // HT_FREQUENCY_1200M + {0xAul, 0, 3}, // HT_FREQUENCY_1400M + {0x7ul, 4, 7}, // HT_FREQUENCY_1600M + {0x7ul, 4, 7}, // HT_FREQUENCY_1800M + {0x5ul, 8, 11}, // HT_FREQUENCY_2000M + {0x5ul, 8, 11}, // HT_FREQUENCY_2200M + {0x4ul, 12, 15}, // HT_FREQUENCY_2400M + {0x3ul, 16, 19}, // HT_FREQUENCY_2600M + {0xFFFFFFFFul, 0, 0}, // Invalid + {0xFFFFFFFFul, 0, 0}, // Invalid + {0x3ul, 20, 23}, // HT_FREQUENCY_2800M + {0x2ul, 24, 27}, // HT_FREQUENCY_3000M + {0x2ul, 28, 31} // HT_FREQUENCY_3200M +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Disables the desired P-state. + * + * @CpuServiceMethod{::F_CPU_DISABLE_PSTATE}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] StateNumber The P-State to disable. + * @param[in] StdHeader Header for library and services + * + * @retval AGESA_SUCCESS Always succeeds. + */ +AGESA_STATUS +F15DisablePstate ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN UINT8 StateNumber, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 LocalMsrRegister; + + ASSERT (StateNumber < NM_PS_REG); + LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader); + ((F15_PSTATE_MSR *) &LocalMsrRegister)->PsEnable = 0; + LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader); + return (AGESA_SUCCESS); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Transitions the executing core to the desired P-state. + * + * @CpuServiceMethod{::F_CPU_TRANSITION_PSTATE}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] StateNumber The new P-State to make effective. + * @param[in] WaitForTransition True if the caller wants the transition completed upon return. + * @param[in] StdHeader Header for library and services + * + * @retval AGESA_SUCCESS Always Succeeds + */ +AGESA_STATUS +F15TransitionPstate ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN UINT8 StateNumber, + IN BOOLEAN WaitForTransition, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 LocalMsrRegister; + + LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader); + ASSERT (((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal >= StateNumber); + LibAmdMsrRead (MSR_PSTATE_CTL, &LocalMsrRegister, StdHeader); + ((PSTATE_CTRL_MSR *) &LocalMsrRegister)->PstateCmd = (UINT64) StateNumber; + LibAmdMsrWrite (MSR_PSTATE_CTL, &LocalMsrRegister, StdHeader); + if (WaitForTransition) { + do { + LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader); + } while (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate != (UINT64) StateNumber); + } + return (AGESA_SUCCESS); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Determines the rate at which the executing core's time stamp counter is + * incrementing. + * + * @CpuServiceMethod{::F_CPU_GET_TSC_RATE}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[out] FrequencyInMHz TSC actual frequency. + * @param[in] StdHeader Header for library and services. + * + * @return The most severe status of all called services + */ +AGESA_STATUS +F15GetTscRate ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT UINT32 *FrequencyInMHz, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 NumBoostStates; + UINT32 LocalPciRegister; + UINT64 LocalMsrRegister; + PCI_ADDR PciAddress; + PSTATE_CPU_FAMILY_SERVICES *FamilyServices; + + LibAmdMsrRead (0xC0010015, &LocalMsrRegister, StdHeader); + if ((LocalMsrRegister & 0x01000000) != 0) { + FamilyServices = NULL; + GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); + ASSERT (FamilyServices != NULL); + OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); + PciAddress.Address.Function = FUNC_4; + PciAddress.Address.Register = CPB_CTRL_REG; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + NumBoostStates = (UINT8) ((F15_CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates; + return (FamilyServices->GetPstateFrequency (FamilyServices, NumBoostStates, FrequencyInMHz, StdHeader)); + } else { + return (FamilySpecificServices->GetCurrentNbFrequency (FamilySpecificServices, FrequencyInMHz, StdHeader)); + } +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Initially launches the desired core to run from the reset vector. + * + * @CpuServiceMethod{::F_CPU_AP_INITIAL_LAUNCH}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] SocketNum The Processor on which the core is to be launched + * @param[in] ModuleNum The Module in that processor containing that core + * @param[in] CoreNum The Core to launch + * @param[in] PrimaryCoreNum The id of the module's primary core. + * @param[in] StdHeader Header for library and services + * + * @retval TRUE The core was launched + * @retval FALSE The core was previously launched + */ +BOOLEAN +F15LaunchApCore ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN UINT32 SocketNum, + IN UINT32 ModuleNum, + IN UINT32 CoreNum, + IN UINT32 PrimaryCoreNum, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 NodeRelativeCoreNum; + UINT32 LocalPciRegister; + PCI_ADDR PciAddress; + BOOLEAN LaunchFlag; + AGESA_STATUS Ignored; + + // Code Start + LaunchFlag = FALSE; + NodeRelativeCoreNum = CoreNum - PrimaryCoreNum; + GetPciAddress (StdHeader, SocketNum, ModuleNum, &PciAddress, &Ignored); + PciAddress.Address.Function = FUNC_0; + + switch (NodeRelativeCoreNum) { + case 0: + PciAddress.Address.Register = HT_INIT_CTRL; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + if ((LocalPciRegister & HT_INIT_CTRL_REQ_DIS) != 0) { + LocalPciRegister &= ~HT_INIT_CTRL_REQ_DIS; + LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + LaunchFlag = TRUE; + } else { + LaunchFlag = FALSE; + } + break; + + case 1: + PciAddress.Address.Register = CORE_CTRL; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + if ((LocalPciRegister & CORE_CTRL_CORE1_EN) == 0) { + LocalPciRegister |= CORE_CTRL_CORE1_EN; + LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + LaunchFlag = TRUE; + } else { + LaunchFlag = FALSE; + } + break; + + case 2: + PciAddress.Address.Register = CORE_CTRL; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + + if ((LocalPciRegister & CORE_CTRL_CORE2_EN) == 0) { + LocalPciRegister |= CORE_CTRL_CORE2_EN; + LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, + StdHeader); + LaunchFlag = TRUE; + } else { + LaunchFlag = FALSE; + } + break; + + case 3: + PciAddress.Address.Register = CORE_CTRL; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + if ((LocalPciRegister & CORE_CTRL_CORE3_EN) == 0) { + LocalPciRegister |= CORE_CTRL_CORE3_EN; + LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + LaunchFlag = TRUE; + } else { + LaunchFlag = FALSE; + } + break; + + case 4: + PciAddress.Address.Register = CORE_CTRL; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + if ((LocalPciRegister & CORE_CTRL_CORE4_EN) == 0) { + LocalPciRegister |= CORE_CTRL_CORE4_EN; + LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + LaunchFlag = TRUE; + } else { + LaunchFlag = FALSE; + } + break; + + case 5: + PciAddress.Address.Register = CORE_CTRL; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + if ((LocalPciRegister & CORE_CTRL_CORE5_EN) == 0) { + LocalPciRegister |= CORE_CTRL_CORE5_EN; + LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + LaunchFlag = TRUE; + } else { + LaunchFlag = FALSE; + } + break; + + case 6: + PciAddress.Address.Register = CORE_CTRL; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + if ((LocalPciRegister & CORE_CTRL_CORE6_EN) == 0) { + LocalPciRegister |= CORE_CTRL_CORE6_EN; + LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + LaunchFlag = TRUE; + } else { + LaunchFlag = FALSE; + } + break; + + case 7: + PciAddress.Address.Register = CORE_CTRL; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + if ((LocalPciRegister & CORE_CTRL_CORE7_EN) == 0) { + LocalPciRegister |= CORE_CTRL_CORE7_EN; + LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + LaunchFlag = TRUE; + } else { + LaunchFlag = FALSE; + } + break; + + case 8: + PciAddress.Address.Register = CORE_CTRL; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + if ((LocalPciRegister & CORE_CTRL_CORE8_EN) == 0) { + LocalPciRegister |= CORE_CTRL_CORE8_EN; + LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + LaunchFlag = TRUE; + } else { + LaunchFlag = FALSE; + } + break; + + case 9: + PciAddress.Address.Register = CORE_CTRL; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + if ((LocalPciRegister & CORE_CTRL_CORE9_EN) == 0) { + LocalPciRegister |= CORE_CTRL_CORE9_EN; + LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + LaunchFlag = TRUE; + } else { + LaunchFlag = FALSE; + } + break; + + default: + break; + } + + return (LaunchFlag); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Provide the features of the next HT link. + * + * @CpuServiceMethod{::F_GET_NEXT_HT_LINK_FEATURES}. + * + * This method is different than the HT Phy Features method, because for the phy registers + * sublink 1 matches and should be programmed if the link is ganged but for PCI config + * registers sublink 1 is reserved if the link is ganged. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in,out] Link Initially zero, each call returns the link number; + * caller passes it back unmodified each call. + * @param[in,out] LinkBase Initially the PCI bus, device, function=0, offset=0; + * Each call returns the HT Host Capability function and offset; + * Caller may use it to access registers, but must @b not modify it; + * Each new call passes the previous value as input. + * @param[out] HtHostFeats The link's features. + * @param[in] StdHeader Standard Head Pointer + * + * @retval TRUE Valid link and features found. + * @retval FALSE No more links. + */ +BOOLEAN +F15GetNextHtLinkFeatures ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN OUT UINTN *Link, + IN OUT PCI_ADDR *LinkBase, + OUT HT_HOST_FEATS *HtHostFeats, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + UINT32 RegValue; + UINT32 ExtendedFreq; + UINTN LinkOffset; + BOOLEAN Result; + + ASSERT (FamilySpecificServices != NULL); + + // No features present unless link is good and connected. + HtHostFeats->HtHostValue = 0; + + Result = TRUE; + + // Find next link. + if (LinkBase->Address.Register == 0) { + // Beginning iteration now. + LinkBase->Address.Register = HT_CAPABILITIES_POINTER; + LibAmdPciReadBits (*LinkBase, 7, 0, &RegValue, StdHeader); + } else { + // Get next link offset. + LibAmdPciReadBits (*LinkBase, 15, 8, &RegValue, StdHeader); + } + if (RegValue == 0) { + // Are we at the end? Check if we can move to another function. + if (LinkBase->Address.Function == 0) { + LinkBase->Address.Function = 4; + LinkBase->Address.Register = HT_CAPABILITIES_POINTER; + LibAmdPciReadBits (*LinkBase, 7, 0, &RegValue, StdHeader); + } + } + + if (RegValue != 0) { + // Not at end, process the found link. + LinkBase->Address.Register = RegValue; + // Compute link number + *Link = (((LinkBase->Address.Function == 4) ? 4 : 0) + ((LinkBase->Address.Register - 0x80) >> 5)); + + // Handle pending link power off, check End of Chain, Xmit Off. + PciAddress = *LinkBase; + PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_CONTROL_REG_OFFSET; + LibAmdPciReadBits (PciAddress, 7, 6, &RegValue, StdHeader); + if (RegValue == 0) { + // Check coherency (HTHOST_LINK_TYPE_REG = 0x18) + PciAddress = *LinkBase; + PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_TYPE_REG_OFFSET; + LibAmdPciReadBits (PciAddress, 4, 0, &RegValue, StdHeader); + if (RegValue == 3) { + HtHostFeats->HtHostFeatures.Coherent = 1; + } else if (RegValue == 7) { + HtHostFeats->HtHostFeatures.NonCoherent = 1; + } + } + + // If link was not connected, don't check other attributes, make sure + // to return zero, no match. + if ((HtHostFeats->HtHostFeatures.Coherent == 1) || (HtHostFeats->HtHostFeatures.NonCoherent == 1)) { + // Check gen3 + PciAddress = *LinkBase; + PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_EXTENDED_FREQ; + LibAmdPciRead (AccessWidth32, PciAddress, &ExtendedFreq, StdHeader); + PciAddress = *LinkBase; + PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_FREQ_OFFSET; + LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader); + RegValue = (((ExtendedFreq & 0x1) << 4) | ((RegValue & 0x00000F00) >> 8)); + if (RegValue > 6) { + HtHostFeats->HtHostFeatures.Ht3 = 1; + } else { + HtHostFeats->HtHostFeatures.Ht1 = 1; + } + // Check ganged. Must check the bit for sublink 0. + LinkOffset = (*Link > 3) ? ((*Link - 4) * 4) : (*Link * 4); + PciAddress = *LinkBase; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = ((UINT32)LinkOffset + 0x170); + LibAmdPciReadBits (PciAddress, 0, 0, &RegValue, StdHeader); + if (RegValue == 0) { + HtHostFeats->HtHostFeatures.UnGanged = 1; + } else { + if (*Link < 4) { + HtHostFeats->HtHostFeatures.Ganged = 1; + } else { + // If this is a sublink 1 but it will be ganged, clear all features. + HtHostFeats->HtHostValue = 0; + } + } + } + } else { + // end of links. + Result = FALSE; + } + return Result; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Checks to see if the HT phy register table entry should be applied + * + * @CpuServiceMethod{::F_NEXT_LINK_HAS_HTFPY_FEATS}. + * + * Find the next link which matches, if any. + * This method will match for sublink 1 if the link is ganged and sublink 0 matches. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in,out] HtHostCapability Initially the PCI bus, device, function=0, offset=0; + * Each call returns the HT Host Capability function and offset; + * Caller may use it to access registers, but must @b not modify it; + * Each new call passes the previous value as input. + * @param[in,out] Link Initially zero, each call returns the link number; caller passes it back unmodified each call. + * @param[in] HtPhyLinkType Link type field from a register table entry to compare against + * @param[out] MatchedSublink1 TRUE: It is actually just sublink 1 that matches, FALSE: any other condition. + * @param[out] Frequency0 The frequency of sublink0 (200 MHz if not connected). + * @param[out] Frequency1 The frequency of sublink1 (200 MHz if not connected). + * @param[in] StdHeader Standard Head Pointer + * + * @retval TRUE Link matches + * @retval FALSE No more links + * + */ +BOOLEAN +F15NextLinkHasHtPhyFeats ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN OUT PCI_ADDR *HtHostCapability, + IN OUT UINT32 *Link, + IN HT_PHY_LINK_FEATS *HtPhyLinkType, + OUT BOOLEAN *MatchedSublink1, + OUT HT_FREQUENCIES *Frequency0, + OUT HT_FREQUENCIES *Frequency1, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 RegValue; + UINT32 ExtendedFreq; + UINT32 InternalLinks; + UINT32 Width; + PCI_ADDR PciAddress; + PCI_ADDR SubLink1Address; + HT_PHY_LINK_FEATS LinkType; + BOOLEAN IsReallyCheckingBoth; + BOOLEAN IsFound; + BOOLEAN Result; + + ASSERT (*Link < 4); + ASSERT (HtPhyLinkType != NULL); + // error checks: No unknown link type bits set and not a "match none" + ASSERT ((HtPhyLinkType->HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL | HTPHY_LINKTYPE_SL0_AND | HTPHY_LINKTYPE_SL1_AND)) == 0); + ASSERT (HtPhyLinkType->HtPhyLinkValue != 0); + + Result = FALSE; + IsFound = FALSE; + while (!IsFound) { + *Frequency0 = 0; + *Frequency1 = 0; + IsReallyCheckingBoth = FALSE; + *MatchedSublink1 = FALSE; + LinkType.HtPhyLinkValue = 0; + + // Find next link. + PciAddress = *HtHostCapability; + if (PciAddress.Address.Register == 0) { + // Beginning iteration now. + PciAddress.Address.Register = HT_CAPABILITIES_POINTER; + LibAmdPciReadBits (PciAddress, 7, 0, &RegValue, StdHeader); + } else { + // Get next link offset. + LibAmdPciReadBits (PciAddress, 15, 8, &RegValue, StdHeader); + } + if (RegValue != 0) { + HtHostCapability->Address.Register = RegValue; + // Compute link number of this sublink pair (so we don't need to account for function). + *Link = ((HtHostCapability->Address.Register - 0x80) >> 5); + + // Set the link indicators. This assumes each sublink set is contiguous, that is, links 3, 2, 1, 0 and 7, 6, 5, 4. + LinkType.HtPhyLinkValue |= (HTPHY_LINKTYPE_SL0_LINK0 << *Link); + LinkType.HtPhyLinkValue |= (HTPHY_LINKTYPE_SL1_LINK4 << *Link); + + // Read IntLnkRoute from the Link Initialization Status register. + PciAddress = *HtHostCapability; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = 0x1A0; + LibAmdPciReadBits (PciAddress, 23, 16, &InternalLinks, StdHeader); + + // if ganged, don't read sublink 1, but use sublink 0 to check. + SubLink1Address = *HtHostCapability; + + // Check ganged. Since we got called for sublink 0, sublink 1 is implemented also, + // but only access it if it is also unganged. + PciAddress = *HtHostCapability; + PciAddress.Address.Function = 0; + PciAddress.Address.Register = ((*Link * 4) + 0x170); + LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader); + RegValue = (RegValue & 0x01); + if (RegValue == 0) { + // Then really read sublink1, rather than using sublink0 + SubLink1Address.Address.Function = 4; + IsReallyCheckingBoth = TRUE; + } + + // Checks for Sublink 0 + + // Handle pending link power off, check End of Chain, Xmit Off. + PciAddress = *HtHostCapability; + PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_CONTROL_REG_OFFSET; + LibAmdPciReadBits (PciAddress, 7, 6, &RegValue, StdHeader); + if (RegValue == 0) { + // Check coherency (HTHOST_LINK_TYPE_REG = 0x18) + PciAddress = *HtHostCapability; + PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_TYPE_REG_OFFSET; + LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader); + if ((RegValue & 0x1F) == 3) { + LinkType.HtPhyLinkFeatures.HtPhySL0Coh = 1; + } else if ((RegValue & 0x1F) == 7) { + LinkType.HtPhyLinkFeatures.HtPhySL0NonCoh = 1; + } + } + + // If link was not connected, don't check other attributes, make sure + // to return zero, no match. (Phy may be powered off.) + if ((LinkType.HtPhyLinkFeatures.HtPhySL0Coh) || (LinkType.HtPhyLinkFeatures.HtPhySL0NonCoh)) { + // Check gen3 + PciAddress = *HtHostCapability; + PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_EXTENDED_FREQ; + LibAmdPciRead (AccessWidth32, PciAddress, &ExtendedFreq, StdHeader); + PciAddress = *HtHostCapability; + PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_FREQ_OFFSET; + LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader); + RegValue = (((ExtendedFreq & 0x1) << 4) | ((RegValue & 0x00000F00) >> 8)); + *Frequency0 = RegValue; + if (RegValue > 6) { + LinkType.HtPhyLinkFeatures.HtPhySL0Ht3 = 1; + } else { + LinkType.HtPhyLinkFeatures.HtPhySL0Ht1 = 1; + } + // Check internal / external + if ((InternalLinks & (1 << *Link)) == 0) { + // External + LinkType.HtPhyLinkFeatures.HtPhySL0External = 1; + } else { + // Internal + LinkType.HtPhyLinkFeatures.HtPhySL0Internal = 1; + } + } else { + LinkType.HtPhyLinkValue &= ~(HTPHY_LINKTYPE_SL0_ALL); + } + + // Checks for Sublink 1 + // Handle pending link power off, check End of Chain, Xmit Off. + // Also, if the links are ganged but the width is not 16 bits, treat it is an inactive lane. + PciAddress = SubLink1Address; + PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_CONTROL_REG_OFFSET; + LibAmdPciReadBits (PciAddress, 7, 6, &RegValue, StdHeader); + LibAmdPciReadBits (PciAddress, 31, 24, &Width, StdHeader); + if ((RegValue == 0) && (IsReallyCheckingBoth || (Width == 0x11))) { + // Check coherency (HTHOST_LINK_TYPE_REG = 0x18) + PciAddress = SubLink1Address; + PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_TYPE_REG_OFFSET; + LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader); + if ((RegValue & 0x1F) == 3) { + LinkType.HtPhyLinkFeatures.HtPhySL1Coh = 1; + } else if ((RegValue & 0x1F) == 7) { + LinkType.HtPhyLinkFeatures.HtPhySL1NonCoh = 1; + } + } + + if ((LinkType.HtPhyLinkFeatures.HtPhySL1Coh) || (LinkType.HtPhyLinkFeatures.HtPhySL1NonCoh)) { + // Check gen3 + PciAddress = SubLink1Address; + PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_EXTENDED_FREQ; + LibAmdPciRead (AccessWidth32, PciAddress, &ExtendedFreq, StdHeader); + PciAddress = SubLink1Address; + PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_FREQ_OFFSET; + LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader); + RegValue = (((ExtendedFreq & 0x1) << 4) | ((RegValue & 0x00000F00) >> 8)); + *Frequency1 = RegValue; + if (RegValue > 6) { + LinkType.HtPhyLinkFeatures.HtPhySL1Ht3 = 1; + } else { + LinkType.HtPhyLinkFeatures.HtPhySL1Ht1 = 1; + } + // Check internal / external. Note that we do really check sublink 1 regardless of ganging. + if ((InternalLinks & (1 << (*Link + 4))) == 0) { + // External + LinkType.HtPhyLinkFeatures.HtPhySL1External = 1; + } else { + // Internal + LinkType.HtPhyLinkFeatures.HtPhySL1Internal = 1; + } + } else { + LinkType.HtPhyLinkValue &= ~(HTPHY_LINKTYPE_SL1_ALL); + } + + // Determine if the link matches the entry criteria. + // For Deemphasis checking, indicate whether it was actually sublink 1 that matched. + // If the link is ganged or only sublink 0 matched, or the link features didn't match, this is false. + if (((HtPhyLinkType->HtPhyLinkValue & HTPHY_LINKTYPE_SL0_AND) == 0) && + ((HtPhyLinkType->HtPhyLinkValue & HTPHY_LINKTYPE_SL1_AND) == 0)) { + // Match if any feature matches (OR) + Result = (BOOLEAN) ((LinkType.HtPhyLinkValue & HtPhyLinkType->HtPhyLinkValue) != 0); + } else { + // Match if all features match (AND) + Result = (BOOLEAN) ((HtPhyLinkType->HtPhyLinkValue & ~(HTPHY_LINKTYPE_SL0_AND | HTPHY_LINKTYPE_SL1_AND)) == + (LinkType.HtPhyLinkValue & HtPhyLinkType->HtPhyLinkValue)); + } + if (Result) { + if (IsReallyCheckingBoth && + (((LinkType.HtPhyLinkValue & HtPhyLinkType->HtPhyLinkValue) & (HTPHY_LINKTYPE_SL1_ALL)) != 0)) { + *MatchedSublink1 = TRUE; + } + IsFound = TRUE; + } else { + // Go to next link + } + } else { + // No more links + IsFound = TRUE; + } + } + return Result; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Applies an HT Phy read-modify-write based on an HT Phy register table entry. + * + * @CpuServiceMethod{::F_SET_HT_PHY_REGISTER}. + * + * This function performs the necessary sequence of PCI reads, writes, and waits + * necessary to program an HT Phy register. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] HtPhyEntry HT Phy register table entry to apply + * @param[in] CapabilitySet The link's HT Host base address. + * @param[in] Link Zero based, node, link number (not package link). + * @param[in] StdHeader Config handle for library and services + * + */ +VOID +F15SetHtPhyRegister ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN HT_PHY_TYPE_ENTRY_DATA *HtPhyEntry, + IN PCI_ADDR CapabilitySet, + IN UINT32 Link, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Temp; + UINT32 PhyReg; + PCI_ADDR PhyBase; + + // Determine the PCI config address of the HT Phy portal + PhyBase = CapabilitySet; + PhyBase.Address.Function = FUNC_4; + PhyBase.Address.Register = ((Link << 3) + REG_HT4_PHY_OFFSET_BASE_4X180); + + LibAmdPciRead (AccessWidth32, PhyBase, &PhyReg, StdHeader); + + // Handle direct map registers if needed + PhyReg &= ~(HTPHY_DIRECT_OFFSET_MASK); + if ((HtPhyEntry->Address > 0x3FF) || ((HtPhyEntry->Address >= 0xE) && (HtPhyEntry->Address <= 0x11))) { + PhyReg |= HTPHY_DIRECT_MAP; + } + + PhyReg |= (HtPhyEntry->Address); + // Ask the portal to read the HT Phy Register contents + LibAmdPciWrite (AccessWidth32, PhyBase, &PhyReg, StdHeader); + do + { + LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader); + } while (!(Temp & HTPHY_IS_COMPLETE_MASK)); + + // Get the current register contents and do the update requested by the table + PhyBase.AddressValue += 4; + LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader); + Temp &= ~(HtPhyEntry->Mask); + Temp |= (HtPhyEntry->Data); + LibAmdPciWrite (AccessWidth32, PhyBase, &Temp, StdHeader); + + PhyBase.AddressValue -= 4; + // Ask the portal to write our updated value to the HT Phy + PhyReg |= HTPHY_WRITE_CMD; + LibAmdPciWrite (AccessWidth32, PhyBase, &PhyReg, StdHeader); + do + { + LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader); + } while (!(Temp & HTPHY_IS_COMPLETE_MASK)); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Applies an HT Phy write to a specified Phy register. + * + * @CpuServiceMethod{::F_SET_HT_PHY_REGISTER}. + * + * The caller is responsible for performing any read and modify steps. + * This function performs the necessary sequence of PCI reads, writes, and waits + * necessary to program an HT Phy register. + * + * @param[in] CapabilitySet The link's HT Host base address. + * @param[in] Link Zero based, node, link number (not package link). + * @param[in] Address The HT Phy register address + * @param[in] Data The data to write to the register + * @param[in] StdHeader Config handle for library and services + * + */ +VOID +STATIC +F15WriteOnlyHtPhyRegister ( + IN PCI_ADDR CapabilitySet, + IN UINT32 Link, + IN UINT32 Address, + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Temp; + UINT32 PhyReg; + PCI_ADDR PhyBase; + + // Determine the PCI config address of the HT Phy portal + PhyBase = CapabilitySet; + PhyBase.Address.Function = FUNC_4; + PhyBase.Address.Register = ((Link << 3) + REG_HT4_PHY_OFFSET_BASE_4X180); + + LibAmdPciRead (AccessWidth32, PhyBase, &PhyReg, StdHeader); + + // Handle direct map registers if needed + PhyReg &= ~(HTPHY_DIRECT_OFFSET_MASK); + if ((Address > 0x3FF) || ((Address >= 0xE) && (Address <= 0x11))) { + PhyReg |= HTPHY_DIRECT_MAP; + } + + PhyReg |= (Address); + + // Get the current register contents and do the update requested by the table + PhyBase.AddressValue += 4; + LibAmdPciWrite (AccessWidth32, PhyBase, &Data, StdHeader); + + PhyBase.AddressValue -= 4; + // Ask the portal to write our updated value to the HT Phy + PhyReg |= HTPHY_WRITE_CMD; + LibAmdPciWrite (AccessWidth32, PhyBase, &PhyReg, StdHeader); + do + { + LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader); + } while (!(Temp & HTPHY_IS_COMPLETE_MASK)); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Get the value of an HT PHY register. + * + * Reading HT Phy registers is not generally useful, because they return the effective value, + * not the currently written value. So be warned, this function is dangerous if used to read + * a register that will be udpated subsequently elsewhere. + * + * This routine is useful for reading hardware status from the HT Phy that can be used to set + * other phy registers. + * + * @param[in] CapabilitySet The link's HT Host base address. + * @param[in] Link Zero based, node link number (not package link). + * @param[in] Address The HT Phy register address to read + * @param[in] StdHeader Config handle for library and services + * + * @return The register content (in most cases, the effective content not the pending content) + * + */ +UINT32 +STATIC +F15GetHtPhyRegister ( + IN PCI_ADDR CapabilitySet, + IN UINT32 Link, + IN UINT32 Address, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Temp; + UINT32 PhyReg; + PCI_ADDR PhyBase; + + // Determine the PCI config address of the HT Phy portal + PhyBase = CapabilitySet; + PhyBase.Address.Function = FUNC_4; + PhyBase.Address.Register = ((Link << 3) + REG_HT4_PHY_OFFSET_BASE_4X180); + + LibAmdPciRead (AccessWidth32, PhyBase, &PhyReg, StdHeader); + + // Handle direct map registers if needed + PhyReg &= ~(HTPHY_DIRECT_OFFSET_MASK); + if ((Address > 0x3FF) || ((Address >= 0xE) && (Address <= 0x11))) { + PhyReg |= HTPHY_DIRECT_MAP; + } + + PhyReg |= Address; + // Ask the portal to read the HT Phy Register contents + LibAmdPciWrite (AccessWidth32, PhyBase, &PhyReg, StdHeader); + do + { + LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader); + } while (!(Temp & HTPHY_IS_COMPLETE_MASK)); + + // Get the current register contents + PhyBase.AddressValue += 4; + LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader); + + return Temp; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * A Family Specific Workaround method, to override HT DLL Compensation. + * + * @TableTypeFamSpecificInstances. + * + * The Link Product Information register can be fused to contain an HT PHY DLL Compensation Override table. + * Based on link frequency, a compensation override can be selected from the value. + * To accomodate individual link differences in the package, each link can also have a DLL process compensation + * value set. This value can apply an adjustment to the compensation value. + * + * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. + * @param[in] StdHeader Config params for library, services. + */ +VOID +F15HtPhyOverrideDllCompensation ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 ProductLinkInfo; + UINT32 Link; + CPU_LOGICAL_ID CpuFamilyRevision; + PCI_ADDR StartingCapabilitySet; + PCI_ADDR CapabilitySet; + PCI_ADDR PciAddress; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + BOOLEAN MatchedSublink1; + HT_FREQUENCIES Freq0; + HT_FREQUENCIES Freq1; + UINTN Sublink; + HT_PHY_LINK_FEATS DesiredLinkFeats; + BOOLEAN IsEarlyRevProcessor; + BOOLEAN IsHardwareReportingComp; + UINTN LinkFrequency; + UINT32 Compensation; + UINT32 Adjustment; + BOOLEAN IsIncrementAdjust; + LINK_PHY_RECEIVER_PROCESS_FUSE_CONTROL LinkPhyReceiverProcessFuseControl; + LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL LinkPhyReceiverProcessDllControl; + + OptionMultiSocketConfiguration.GetCurrPciAddr (&StartingCapabilitySet, StdHeader); + GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); + GetCpuServicesFromLogicalId (&CpuFamilyRevision, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + + // Check if the hardware reported any compensation values. + IsEarlyRevProcessor = (BOOLEAN) ((Data == 0) ? TRUE : FALSE); + PciAddress = StartingCapabilitySet; + PciAddress.Address.Function = FUNC_5; + PciAddress.Address.Register = 0x190; + LibAmdPciRead (AccessWidth32, PciAddress, &ProductLinkInfo, StdHeader); + IsHardwareReportingComp = (BOOLEAN) (ProductLinkInfo != 0); + + if (!IsEarlyRevProcessor || IsHardwareReportingComp) { + // Process all the sublink 0's and then all the sublink 1's that are at HT3 frequency. + for (Sublink = 0; Sublink < 2; Sublink++) { + CapabilitySet = StartingCapabilitySet; + Link = 0; + DesiredLinkFeats.HtPhyLinkValue = ((Sublink == 0) ? HTPHY_LINKTYPE_SL0_HT3 : HTPHY_LINKTYPE_SL0_HT3); + while (FamilySpecificServices->NextLinkHasHtPhyFeats ( + FamilySpecificServices, + &CapabilitySet, + &Link, + &DesiredLinkFeats, + &MatchedSublink1, + &Freq0, + &Freq1, + StdHeader)) { + + // Look up compensation value. Remember that we matched links which are at HT3 frequency, so Freq[1,0] + // should safely be greater than or equal to 1.2 GHz. + if (Sublink == 0) { + LinkFrequency = Freq0 - HT_FREQUENCY_1200M; + } else { + LinkFrequency = (MatchedSublink1 ? Freq1 : Freq0) - HT_FREQUENCY_1200M; + } + // This assert would catch frequencies higher than we know how to support, or any table overrun bug. + ASSERT (LinkFrequency < (sizeof (HtPhyDllCompLookupTable) / sizeof (HT_PHY_DLL_COMP_LOOKUP_TABLE))); + // Since there are invalid entries in the table, for frequency enum skipped values, ensure we did not + // pick one of those entries. This should be impossible from real hardware. + ASSERT (HtPhyDllCompLookupTable[LinkFrequency].DefaultComp != 0xFFFFFFFFul); + + if (IsHardwareReportingComp) { + LibAmdPciReadBits ( + PciAddress, + HtPhyDllCompLookupTable[LinkFrequency].CtlIndexHiBit, + HtPhyDllCompLookupTable[LinkFrequency].CtlIndexLoBit, + &Compensation, + StdHeader); + } else { + Compensation = HtPhyDllCompLookupTable[LinkFrequency].DefaultComp; + } + + // Apply any per PHY adjustment + LinkPhyReceiverProcessFuseControl.Value = F15GetHtPhyRegister ( + CapabilitySet, + Link, + ((Sublink == 0) ? HT_PHY_FUSE_PROC_DLL_PROCESS_COMP_RD_SL0 : HT_PHY_FUSE_PROC_DLL_PROCESS_COMP_RD_SL1), + StdHeader); + Adjustment = LinkPhyReceiverProcessFuseControl.Fields.DllProcessComp10; + IsIncrementAdjust = (BOOLEAN) ((LinkPhyReceiverProcessFuseControl.Fields.DllProcessComp2 == 0) ? TRUE : FALSE); + if (IsIncrementAdjust) { + Compensation = (((Compensation + Adjustment) > 0x000F) ? 0x000F : (Compensation + Adjustment)); + } else { + // decrement adjustment + Compensation = ((Compensation < Adjustment) ? 0 : (Compensation - Adjustment)); + } + + // Update the DLL Compensation + LinkPhyReceiverProcessDllControl.Value = F15GetHtPhyRegister ( + CapabilitySet, + Link, + HT_PHY_LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL_RD, + StdHeader); + LinkPhyReceiverProcessDllControl.Fields.DllProcessFreqCtlOverride = 1; + LinkPhyReceiverProcessDllControl.Fields.DllProcessFreqCtlIndex2 = Compensation; + F15WriteOnlyHtPhyRegister ( + CapabilitySet, + Link, + ((Sublink == 0) ? HT_PHY_LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL_SL0 : HT_PHY_LINK_PHY_RECEIVER_PROCESS_DLL_CONTROL_SL1), + LinkPhyReceiverProcessDllControl.Value, + StdHeader); + } + } + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns whether or not BIOS is responsible for configuring the NB COFVID. + * + * @CpuServiceMethod{::F_CPU_IS_NBCOF_INIT_NEEDED}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] PciAddress The northbridge to query by pci base address. + * @param[out] NbVidUpdateAll Do all NbVids need to be updated + * @param[in] StdHeader Header for library and services + * + * @retval TRUE Perform northbridge frequency and voltage config. + * @retval FALSE Do not configure them. + */ +BOOLEAN +F15CommonGetNbCofVidUpdate ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PCI_ADDR *PciAddress, + OUT BOOLEAN *NbVidUpdateAll, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *NbVidUpdateAll = FALSE; + return FALSE; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Is the Northbridge PState feature enabled? + * + * @CpuServiceMethod{::F_IS_NB_PSTATE_ENABLED}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] PlatformConfig Platform profile/build option config structure. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval TRUE The NB PState feature is enabled. + * @retval FALSE The NB PState feature is not enabled. + */ +BOOLEAN +F15IsNbPstateEnabled ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 LocalPciRegister; + PCI_ADDR PciAddress; + BOOLEAN PowerMode; + BOOLEAN SkipHwCfg; + + SkipHwCfg = FALSE; + + IDS_OPTION_HOOK (IDS_NBPSDIS_OVERRIDE, &SkipHwCfg, StdHeader); + + // Defaults to Power Optimized Mode + PowerMode = TRUE; + + // If system is optimized for performance, disable NB P-States + if (PlatformConfig->PlatformProfile.PlatformPowerPolicy == Performance) { + PowerMode = FALSE; + } + + PciAddress.AddressValue = F15_NB_PSTATE_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + if ((((((F15_NB_PSTATE_CTRL_REGISTER *) &LocalPciRegister)->NbPstateMaxVal != 0) && + (!IsNonCoherentHt1 (StdHeader))) || SkipHwCfg) && (PowerMode)) { + return TRUE; + } + return FALSE; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Utilities.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Utilities.h new file mode 100644 index 0000000..5414ba9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15Utilities.h @@ -0,0 +1,186 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 specific utility functions. + * + * Provides numerous utility functions specific to family 15h. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15 + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_F15_UTILITES_H_ +#define _CPU_F15_UTILITES_H_ + + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ +/// The structure for Software Initiated NB Voltage Transitions +typedef struct { + UINT32 VidCode; ///< VID code to transition to + BOOLEAN SlamMode; ///< Whether voltage is to be slammed, or stepped +} SW_VOLT_TRANS_NB; + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +F15DisablePstate ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN UINT8 StateNumber, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +F15TransitionPstate ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN UINT8 StateNumber, + IN BOOLEAN WaitForTransition, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +F15GetTscRate ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT UINT32 *FrequencyInMHz, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +F15LaunchApCore ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN UINT32 SocketNum, + IN UINT32 ModuleNum, + IN UINT32 CoreNum, + IN UINT32 PrimaryCoreNum, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +F15HtPhyOverrideDllCompensation ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +F15GetNextHtLinkFeatures ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN OUT UINTN *Link, + IN OUT PCI_ADDR *LinkBase, + OUT HT_HOST_FEATS *HtHostFeats, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +F15NextLinkHasHtPhyFeats ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN OUT PCI_ADDR *HtHostCapability, + IN OUT UINT32 *Link, + IN HT_PHY_LINK_FEATS *HtPhyLinkType, + OUT BOOLEAN *MatchedSublink1, + OUT HT_FREQUENCIES *Frequency0, + OUT HT_FREQUENCIES *Frequency1, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +F15SetHtPhyRegister ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN HT_PHY_TYPE_ENTRY_DATA *HtPhyEntry, + IN PCI_ADDR CapabilitySet, + IN UINT32 Link, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +F15CommonGetNbCofVidUpdate ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PCI_ADDR *PciAddress, + OUT BOOLEAN *NbVidUpdateAll, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +F15IsNbPstateEnabled ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif // _CPU_F15_UTILITES_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c new file mode 100644 index 0000000..ffa56c3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c @@ -0,0 +1,154 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 WHEA initial Data + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15 + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuLateInit.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_CPUF15WHEAINITDATATABLES_FILECODE + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +GetF15WheaInitData ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **F15WheaInitDataPtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AMD_HEST_BANK_INIT_DATA F15HestBankInitData[] = { + {0xFFFFFFFF,0xFFFFFFFF,0x400,0x401,0x402,0x403}, + {0xFFFFFFFF,0xFFFFFFFF,0x404,0x405,0x406,0x407}, + {0xFFFFFFFF,0xFFFFFFFF,0x408,0x409,0x40A,0x40B}, + {0xFFFFFFFF,0xFFFFFFFF,0x410,0x411,0x412,0x413}, + {0xFFFFFFFF,0xFFFFFFFF,0x414,0x415,0x416,0x417}, + {0xFFFFFFFF,0xFFFFFFFF,0x418,0x419,0x41A,0x41B}, +}; + +AMD_WHEA_INIT_DATA F15WheaInitData = { + 0x000000000, // AmdGlobCapInitDataLsd + 0x000000000, // AmdGlobCapInitDataMsd + 0x000000077, // AmdGlobCtrlInitDataLsd + 0x000000000, // AmdGlobCtrlInitDataMsd + 0x00, // AmdMcbClrStatusOnInit + 0x02, // AmdMcbStatusDataFormat + 0x00, // AmdMcbConfWriteEn + (sizeof (F15HestBankInitData) / sizeof (F15HestBankInitData[0])), // HestBankNum + &F15HestBankInitData[0] // Pointer to Initial data of HEST Bank +}; + + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the family specific WHEA table properties. + * + * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[out] F15WheaInitDataPtr Points to the family 15h WHEA properties. + * @param[out] NumberOfElements Will be one to indicate one structure. + * @param[in] StdHeader Header for library and services. + * + */ +VOID +GetF15WheaInitData ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **F15WheaInitDataPtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *NumberOfElements = 1; + *F15WheaInitDataPtr = &F15WheaInitData; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/cpuFamRegisters.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/cpuFamRegisters.h new file mode 100644 index 0000000..1f288fc --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/cpuFamRegisters.h @@ -0,0 +1,275 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Register Table Related Functions + * + * Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_FAM_REGISTERS_H_ +#define _CPU_FAM_REGISTERS_H_ + +/* + *-------------------------------------------------------------- + * + * M O D U L E S U S E D + * + *--------------------------------------------------------------- + */ + +/* + *-------------------------------------------------------------- + * + * D E F I N I T I O N S / M A C R O S + * + *--------------------------------------------------------------- + */ + +// This define should be equal to the total number of families +// in the cpuFamily enum. +#define MAX_CPU_FAMILIES 64 +#define MAX_CPU_REVISIONS 63 // Max Cpu Revisions Per Family + +// CPU_LOGICAL_ID.Family equates +// Family 10h equates +#define AMD_FAMILY_10_RB 0x0000000000000001ull +#define AMD_FAMILY_10_BL 0x0000000000000002ull +#define AMD_FAMILY_10_DA 0x0000000000000004ull +#define AMD_FAMILY_10_HY 0x0000000000000008ull +#define AMD_FAMILY_10_PH 0x0000000000000010ull +#define AMD_FAMILY_10_C32 AMD_FAMILY_10_HY + +#define AMD_FAMILY_10 (AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH) +#define AMD_FAMILY_GH (AMD_FAMILY_10) + +// Family 12h equates +#define AMD_FAMILY_12_LN 0x0000000000000020ull +#define AMD_FAMILY_12 (AMD_FAMILY_12_LN) +#define AMD_FAMILY_LN (AMD_FAMILY_12_LN) + +// Family 14h equates +#define AMD_FAMILY_14_ON 0x0000000000000040ull +#define AMD_FAMILY_ON (AMD_FAMILY_14_ON) +#define AMD_FAMILY_14_KR 0x0000000000000080ull +#define AMD_FAMILY_KR (AMD_FAMILY_14_KR) +#define AMD_FAMILY_14 (AMD_FAMILY_14_ON | AMD_FAMILY_14_KR) + +// Family 15h equates +#define AMD_FAMILY_15_OR 0x0000000000000100ull +#define AMD_FAMILY_OR (AMD_FAMILY_15_OR) +#define AMD_FAMILY_15_TN 0x0000000000000200ull +#define AMD_FAMILY_TN (AMD_FAMILY_15_TN) + + +// Family Unknown +#define AMD_FAMILY_UNKNOWN 0x8000000000000000ull + +// Family Group equates +#define AMD_FAMILY_GE_12 (AMD_FAMILY_12 | AMD_FAMILY_14 | (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) | 0x0000000000010000ull ) + +// Family 10h CPU_LOGICAL_ID.Revision equates +// ------------------------------------- + // Family 10h RB steppings +#define AMD_F10_RB_C0 0x0000000000000001ull +#define AMD_F10_RB_C1 0x0000000000000002ull +#define AMD_F10_RB_C2 0x0000000000000004ull +#define AMD_F10_RB_C3 0x0000000000000008ull + // Family 10h BL steppings +#define AMD_F10_BL_C2 0x0000000000000010ull +#define AMD_F10_BL_C3 0x0000000000000020ull + // Family 10h DA steppings +#define AMD_F10_DA_C2 0x0000000000000040ull +#define AMD_F10_DA_C3 0x0000000000000080ull + // Family 10h HY SCM steppings +#define AMD_F10_HY_SCM_D0 0x0000000000000100ull +#define AMD_F10_HY_SCM_D1 0x0000000000000400ull + // Family 10h HY MCM steppings +#define AMD_F10_HY_MCM_D0 0x0000000000000200ull +#define AMD_F10_HY_MCM_D1 0x0000000000000800ull + // Family 10h PH steppings +#define AMD_F10_PH_E0 0x0000000000001000ull + + // Family 10h Unknown stepping + // * This equate is used to ensure that unknown CPU revisions are * + // * identified as the last known revision of the silicon family: * + // * - Update AMD_F10_UNKNOWN whenever newer F10h steppings are added * +#define AMD_F10_UNKNOWN (AMD_FAMILY_UNKNOWN | AMD_F10_C3 | AMD_F10_D1 | AMD_F10_PH_E0) + + // Family 10h Miscellaneous equates +#define AMD_F10_C0 (AMD_F10_RB_C0) +#define AMD_F10_C1 (AMD_F10_RB_C1) +#define AMD_F10_C2 (AMD_F10_RB_C2 | AMD_F10_DA_C2 | AMD_F10_BL_C2) +#define AMD_F10_C3 (AMD_F10_RB_C3 | AMD_F10_DA_C3 | AMD_F10_BL_C3) +#define AMD_F10_Cx (AMD_F10_C0 | AMD_F10_C1 | AMD_F10_C2 | AMD_F10_C3) + +#define AMD_F10_RB_ALL (AMD_F10_RB_C0 | AMD_F10_RB_C1 | AMD_F10_RB_C2 | AMD_F10_RB_C3) + +#define AMD_F10_BL_ALL (AMD_F10_BL_C2 | AMD_F10_BL_C3) +#define AMD_F10_BL_Cx (AMD_F10_BL_C2 | AMD_F10_BL_C3) + +#define AMD_F10_DA_ALL (AMD_F10_DA_C2 | AMD_F10_DA_C3) +#define AMD_F10_DA_Cx (AMD_F10_DA_C2 | AMD_F10_DA_C3) + +#define AMD_F10_D0 (AMD_F10_HY_SCM_D0 | AMD_F10_HY_MCM_D0) +#define AMD_F10_D1 (AMD_F10_HY_SCM_D1 | AMD_F10_HY_MCM_D1) +#define AMD_F10_Dx (AMD_F10_D0 | AMD_F10_D1) + +#define AMD_F10_PH_ALL (AMD_F10_PH_E0) +#define AMD_F10_Ex (AMD_F10_PH_E0) + +#define AMD_F10_HY_ALL (AMD_F10_Dx) +#define AMD_F10_C32_ALL (AMD_F10_HY_SCM_D0 | AMD_F10_HY_SCM_D1) + +#define AMD_F10_GT_B0 (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex) +#define AMD_F10_GT_Bx (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex) +#define AMD_F10_GT_A2 (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex) +#define AMD_F10_GT_Ax (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex) +#define AMD_F10_GT_C0 ((AMD_F10_Cx & ~AMD_F10_C0) | AMD_F10_Dx | AMD_F10_Ex) +#define AMD_F10_GT_D0 (AMD_F10_Dx & ~AMD_F10_D0 | AMD_F10_Ex) + +#define AMD_F10_ALL (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex) + +// Family 12h CPU_LOGICAL_ID.Revision equates +// ------------------------------------- + + // Family 12h LN steppings +#define AMD_F12_LN_A0 0x0000000000000001ull +#define AMD_F12_LN_A1 0x0000000000000002ull +#define AMD_F12_LN_B0 0x0000000000000004ull + + // Family 12h Unknown stepping + // * This equate is used to ensure that unknown CPU revisions are * + // * identified as the last known revision of the silicon family: * + // * - Update AMD_F12_UNKNOWN whenever newer F12h steppings are added * +#define AMD_F12_UNKNOWN (AMD_FAMILY_UNKNOWN | AMD_F12_LN_B0) + +#define AMD_F12_LN_Ax (AMD_F12_LN_A0 | AMD_F12_LN_A1) +#define AMD_F12_LN_Bx (AMD_F12_LN_B0) + +#define AMD_F12_ALL (AMD_F12_LN_Ax | AMD_F12_LN_Bx) + +// Family 14h CPU_LOGICAL_ID.Revision equates +// ------------------------------------- + + // Family 14h ON steppings +#define AMD_F14_ON_A0 0x0000000000000001ull +#define AMD_F14_ON_A1 0x0000000000000002ull +#define AMD_F14_ON_B0 0x0000000000000004ull +#define AMD_F14_ON_C0 0x0000000000000008ull + // Family 14h KR steppings +#define AMD_F14_KR_A0 0x0000000000000100ull +#define AMD_F14_KR_A1 0x0000000000000200ull +#define AMD_F14_KR_B0 0x0000000000000400ull + + // Family 14h Unknown stepping + // * This equate is used to ensure that unknown CPU revisions are * + // * identified as the last known revision of the silicon family: * + // * - Update AMD_F14_UNKNOWN whenever newer F14h steppings are added * +#define AMD_F14_UNKNOWN (AMD_FAMILY_UNKNOWN | AMD_F14_KR_B0 | AMD_F14_ON_C0) + +#define AMD_F14_ON_Ax (AMD_F14_ON_A0 | AMD_F14_ON_A1) +#define AMD_F14_ON_Bx (AMD_F14_ON_B0) +#define AMD_F14_ON_Cx (AMD_F14_ON_C0) +#define AMD_F14_ON_ALL (AMD_F14_ON_Ax | AMD_F14_ON_Bx | AMD_F14_ON_Cx) + +#define AMD_F14_KR_Ax (AMD_F14_KR_A0 | AMD_F14_KR_A1) +#define AMD_F14_KR_Bx AMD_F14_KR_B0 +#define AMD_F14_KR_ALL (AMD_F14_KR_Ax | AMD_F14_KR_Bx) + +#define AMD_F14_ALL (AMD_F14_ON_ALL | AMD_F14_KR_ALL) + +// Family 15h CPU_LOGICAL_ID.Revision equates +// ------------------------------------- + + // Family 15h OROCHI steppings +#define AMD_F15_OR_A0 0x0000000000000001ull +#define AMD_F15_OR_A1 0x0000000000000002ull +#define AMD_F15_OR_B0 0x0000000000000004ull +#define AMD_F15_OR_B1 0x0000000000000008ull +#define AMD_F15_OR_B2 0x0000000000000010ull + // Family 15h TN steppings +#define AMD_F15_TN_A0 0x0000000000000100ull +#define AMD_F15_TN_A1 0x0000000000000200ull + // Family 15h Unknown stepping + // * This equate is used to ensure that unknown CPU revisions are * + // * identified as the last known revision of the silicon family: * + // * - Update AMD_F15_UNKNOWN whenever newer F15h steppings are added * + +#define AMD_F15_OR_Ax (AMD_F15_OR_A0 | AMD_F15_OR_A1) +#define AMD_F15_OR_Bx (AMD_F15_OR_B0 | AMD_F15_OR_B1 | AMD_F15_OR_B2) +#define AMD_F15_OR_GT_Ax (AMD_F15_OR_Bx) +#define AMD_F15_OR_LT_B1 (AMD_F15_OR_Ax | AMD_F15_OR_B0) +#define AMD_F15_OR_ALL (AMD_F15_OR_Ax | AMD_F15_OR_Bx) + +#define AMD_F15_TN_Ax (AMD_F15_TN_A0 | AMD_F15_TN_A1) +#define AMD_F15_TN_GT_A0 (AMD_F15_TN_ALL & ~AMD_F15_TN_A0) +#define AMD_F15_TN_ALL (AMD_F15_TN_Ax) + + + + +#endif // _CPU_FAM_REGISTERS_H_ + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/PreserveMailbox.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/PreserveMailbox.c new file mode 100644 index 0000000..b728c6d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/PreserveMailbox.c @@ -0,0 +1,245 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA CPU Preserve Registers used for AP Mailbox. + * + * Save and Restore the normal feature content of the registers being used for + * the AP Mailbox. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Feature + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Topology.h" +#include "GeneralServices.h" +#include "OptionMultiSocket.h" +#include "cpuRegisters.h" +#include "cpuApicUtilities.h" +#include "cpuServices.h" +#include "cpuFamilyTranslation.h" +#include "cpuFeatures.h" +#include "PreserveMailbox.h" +#include "heapManager.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FEATURE_PRESERVEMAILBOX_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern CPU_FAMILY_SUPPORT_TABLE PreserveMailboxFamilyServiceTable; + +/*---------------------------------------------------------------------------------------*/ +/** + * The contents of the mailbox registers should always be preserved. + * + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE Always TRUE + * + */ +BOOLEAN +STATIC +IsPreserveAroundMailboxEnabled ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return TRUE; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Save and Restore or Initialize the content of the mailbox registers. + * + * The registers used for AP mailbox should have the content related to their function + * preserved. + * + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @return AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +STATIC +PreserveMailboxes ( + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PRESERVE_MAILBOX_FAMILY_SERVICES *FamilySpecificServices; + UINT32 Socket; + UINT32 Module; + PCI_ADDR BaseAddress; + PCI_ADDR MailboxRegister; + PRESERVE_MAILBOX_FAMILY_REGISTER *NextRegister; + AGESA_STATUS IgnoredStatus; + AGESA_STATUS HeapStatus; + UINT32 Value; + ALLOCATE_HEAP_PARAMS AllocateParams; + LOCATE_HEAP_PTR LocateParams; + UINT32 RegisterEntryIndex; + + BaseAddress.AddressValue = ILLEGAL_SBDFO; + + if (EntryPoint == CPU_FEAT_AFTER_COHERENT_DISCOVERY) { + // The save step. Save either the register content or zero (for cold boot, if family specifies that). + AllocateParams.BufferHandle = PRESERVE_MAIL_BOX_HANDLE; + AllocateParams.RequestedBufferSize = (sizeof (UINT32) * (MAX_PRESERVE_REGISTER_ENTRIES * (MAX_SOCKETS * MAX_DIES))); + AllocateParams.Persist = HEAP_SYSTEM_MEM; + HeapStatus = HeapAllocateBuffer (&AllocateParams, StdHeader); + ASSERT ((HeapStatus == AGESA_SUCCESS) && (AllocateParams.BufferPtr != NULL)); + LibAmdMemFill (AllocateParams.BufferPtr, 0xFF, AllocateParams.RequestedBufferSize, StdHeader); + RegisterEntryIndex = 0; + for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { + for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { + if (GetPciAddress (StdHeader, Socket, Module, &BaseAddress, &IgnoredStatus)) { + GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, (CONST VOID **)&FamilySpecificServices, StdHeader); + ASSERT (FamilySpecificServices != NULL); + NextRegister = FamilySpecificServices->RegisterList; + while (NextRegister->Register.AddressValue != ILLEGAL_SBDFO) { + ASSERT (RegisterEntryIndex < + (MAX_PRESERVE_REGISTER_ENTRIES * GetPlatformNumberOfSockets () * GetPlatformNumberOfModules ())); + if (FamilySpecificServices->IsZeroOnCold && (!IsWarmReset (StdHeader))) { + Value = 0; + } else { + MailboxRegister = BaseAddress; + MailboxRegister.Address.Function = NextRegister->Register.Address.Function; + MailboxRegister.Address.Register = NextRegister->Register.Address.Register; + LibAmdPciRead (AccessWidth32, MailboxRegister, &Value, StdHeader); + Value &= NextRegister->Mask; + } + (* (MAILBOX_REGISTER_SAVE_ENTRY) AllocateParams.BufferPtr) [RegisterEntryIndex] = Value; + RegisterEntryIndex++; + NextRegister++; + } + } + } + } + } else if ((EntryPoint == CPU_FEAT_INIT_LATE_END) || (EntryPoint == CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) { + // The restore step. Just write out the saved content in the buffer. + LocateParams.BufferHandle = PRESERVE_MAIL_BOX_HANDLE; + HeapStatus = HeapLocateBuffer (&LocateParams, StdHeader); + ASSERT ((HeapStatus == AGESA_SUCCESS) && (LocateParams.BufferPtr != NULL)); + RegisterEntryIndex = 0; + for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { + for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { + if (GetPciAddress (StdHeader, Socket, Module, &BaseAddress, &IgnoredStatus)) { + GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, (CONST VOID **)&FamilySpecificServices, StdHeader); + NextRegister = FamilySpecificServices->RegisterList; + while (NextRegister->Register.AddressValue != ILLEGAL_SBDFO) { + ASSERT (RegisterEntryIndex < + (MAX_PRESERVE_REGISTER_ENTRIES * GetPlatformNumberOfSockets () * GetPlatformNumberOfModules ())); + MailboxRegister = BaseAddress; + MailboxRegister.Address.Function = NextRegister->Register.Address.Function; + MailboxRegister.Address.Register = NextRegister->Register.Address.Register; + LibAmdPciRead (AccessWidth32, MailboxRegister, &Value, StdHeader); + Value = ((Value & ~NextRegister->Mask) | (* (MAILBOX_REGISTER_SAVE_ENTRY) LocateParams.BufferPtr) [RegisterEntryIndex]); + LibAmdPciWrite (AccessWidth32, MailboxRegister, &Value, StdHeader); + RegisterEntryIndex++; + NextRegister++; + } + } + } + } + HeapStatus = HeapDeallocateBuffer (PRESERVE_MAIL_BOX_HANDLE, StdHeader); + } + return AGESA_SUCCESS; +} + + +CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePreserveAroundMailbox = +{ + PreserveAroundMailbox, + (CPU_FEAT_AFTER_COHERENT_DISCOVERY | CPU_FEAT_INIT_LATE_END | CPU_FEAT_AFTER_RESUME_MTRR_SYNC), + IsPreserveAroundMailboxEnabled, + PreserveMailboxes +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/PreserveMailbox.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/PreserveMailbox.h new file mode 100644 index 0000000..5debbd5 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/PreserveMailbox.h @@ -0,0 +1,124 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA CPU Preserve Registers used for AP Mailbox. + * + * Save and Restore the normal feature content of the registers being used for + * the AP Mailbox. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Feature + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _PRESERVE_MAILBOX_H_ +#define _PRESERVE_MAILBOX_H_ + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ +#define MAX_PRESERVE_REGISTER_ENTRIES 2 ///< There is room on the heap for up to this per node. + +/// Reference to a save buffer. +typedef UINT32 (*MAILBOX_REGISTER_SAVE_ENTRY) [MAX_PRESERVE_REGISTER_ENTRIES]; + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/** + * Family specific mailbox register descriptor. + * + * Describes a register and bits within the register used as the mailbox. + */ +typedef struct { + PCI_ADDR Register; ///< The PCI address of a mailbox register. + UINT32 Mask; ///< The mask of bits used in Register as the mailbox. +} PRESERVE_MAILBOX_FAMILY_REGISTER; + +/** + * Descriptor for family specific save-restore. + * + * Provide a list of the register offsets to save-restore on each node. Optionally, zero the + * register instead of restoring it. + */ +typedef struct { + UINT16 Revision; ///< Interface version + // Public Data. + BOOLEAN IsZeroOnCold; ///< On a cold boot, zero the register instead of restore. + PRESERVE_MAILBOX_FAMILY_REGISTER *RegisterList; ///< The list of registers, terminated by ILLEGAL_SBDFO. +} PRESERVE_MAILBOX_FAMILY_SERVICES; + + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N S P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ + +#endif // _PRESERVE_MAILBOX_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuApm.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuApm.c new file mode 100644 index 0000000..da34905 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuApm.c @@ -0,0 +1,231 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA CPU Application Power Management (APM) feature support code. + * + * Contains code that declares the AGESA CPU APM related APIs + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Feature + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "cpuApicUtilities.h" +#include "cpuFeatures.h" +#include "cpuApm.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FEATURE_CPUAPM_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +EnableApmOnSocket ( + IN VOID *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern CPU_FAMILY_SUPPORT_TABLE ApmFamilyServiceTable; + +/*---------------------------------------------------------------------------------------*/ +/** + * Should Application Power Management (APM) be enabled + * + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE APM is supported. + * @retval FALSE APM cannot be enabled. + * + */ +BOOLEAN +STATIC +IsApmFeatureEnabled ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Socket; + BOOLEAN IsEnabled; + APM_FAMILY_SERVICES *FamilyServices; + + IsEnabled = FALSE; + + for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { + if (IsProcessorPresent (Socket, StdHeader)) { + GetFeatureServicesOfSocket (&ApmFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader); + if (FamilyServices != NULL) { + if (FamilyServices->IsApmSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) { + IsEnabled = TRUE; + break; + } + } + } + } + return IsEnabled; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Enable Application Power Management (APM) + * + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +STATIC +InitializeApmFeature ( + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 BscSocket; + UINT32 Ignored; + UINT32 Socket; + UINT32 NumberOfSockets; + AP_TASK TaskPtr; + AGESA_STATUS IgnoredSts; + + IDS_HDT_CONSOLE (CPU_TRACE, " APM mode is enabled\n"); + + IdentifyCore (StdHeader, &BscSocket, &Ignored, &Ignored, &IgnoredSts); + NumberOfSockets = GetPlatformNumberOfSockets (); + + TaskPtr.FuncAddress.PfApTaskI = EnableApmOnSocket; + TaskPtr.DataTransfer.DataSizeInDwords = 2; + TaskPtr.DataTransfer.DataPtr = PlatformConfig; + TaskPtr.DataTransfer.DataTransferFlags = 0; + TaskPtr.ExeFlags = WAIT_FOR_CORE; + + for (Socket = 0; Socket < NumberOfSockets; Socket++) { + if (IsProcessorPresent (Socket, StdHeader)) { + if (Socket != BscSocket) { + ApUtilRunCodeOnSocketCore ((UINT8) Socket, 0, &TaskPtr, StdHeader); + } + } + } + + EnableApmOnSocket (PlatformConfig, StdHeader); + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * AP task to enable APM + * + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + */ +VOID +STATIC +EnableApmOnSocket ( + IN VOID *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + APM_FAMILY_SERVICES *FamilyServices; + + GetFeatureServicesOfCurrentCore (&ApmFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); + FamilyServices->EnableApmOnSocket (FamilyServices, + PlatformConfig, + StdHeader); +} + +CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureApm = +{ + CpuApm, + CPU_FEAT_BEFORE_RELINQUISH_AP, + IsApmFeatureEnabled, + InitializeApmFeature +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuApm.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuApm.h new file mode 100644 index 0000000..7fd1814 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuApm.h @@ -0,0 +1,156 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA CPU Application Power Management (APM) Functions declarations. + * + * Contains code that declares the AGESA CPU APM related APIs + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Feature + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_APM_H_ +#define _CPU_APM_H_ + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ +// Forward declaration needed for multi-structure mutual references +AGESA_FORWARD_DECLARATION (APM_FAMILY_SERVICES); + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to check if Application Power Management (APM) is supported. + * + * @param[in] ApmServices APM services. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] Socket Zero-based socket number. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE APM is supported. + * @retval FALSE APM is not supported. + * + */ +typedef BOOLEAN F_APM_IS_SUPPORTED ( + IN APM_FAMILY_SERVICES *CpbServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN UINT32 Socket, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_APM_IS_SUPPORTED *PF_APM_IS_SUPPORTED; + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to enable APM. + * + * @param[in] ApmServices APM services. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @return Family specific error value. + * + */ +typedef AGESA_STATUS F_APM_INIT ( + IN APM_FAMILY_SERVICES *ApmServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_APM_INIT *PF_APM_INIT; + +/** + * Provide the interface to the APM Family Specific Services. + * + * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). + * Each supported Family must provide an implementation for all methods in this interface, even if the + * implementation is a CommonReturn(). + */ +struct _APM_FAMILY_SERVICES { + UINT16 Revision; ///< Interface version + // Public Methods. + PF_APM_IS_SUPPORTED IsApmSupported; ///< Method: Family specific call to check if APM is supported. + PF_APM_INIT EnableApmOnSocket; ///< Method: Family specific call to enable APM. +}; + + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N S P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ + +#endif // _CPU_APM_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuC6State.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuC6State.c new file mode 100644 index 0000000..0e55e48 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuC6State.c @@ -0,0 +1,287 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA CPU C6 feature support code. + * + * Contains code that declares the AGESA CPU C6 related APIs + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Feature + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuEarlyInit.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "OptionMultiSocket.h" +#include "cpuApicUtilities.h" +#include "cpuServices.h" +#include "cpuFeatures.h" +#include "cpuC6State.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FEATURE_CPUC6STATE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +EnableC6OnSocket ( + IN VOID *EntryPoint, + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern CPU_FAMILY_SUPPORT_TABLE C6FamilyServiceTable; +extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; + +/*---------------------------------------------------------------------------------------*/ +/** + * Should C6 be enabled + * + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE C6 is supported. + * @retval FALSE C6 cannot be enabled. + * + */ +BOOLEAN +STATIC +IsC6FeatureEnabled ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Socket; + BOOLEAN IsEnabled; + C6_FAMILY_SERVICES *FamilyServices; + + IsEnabled = FALSE; + if (PlatformConfig->CStateMode == CStateModeC6) { + IsEnabled = TRUE; + for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { + if (IsProcessorPresent (Socket, StdHeader)) { + GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader); + if ((FamilyServices == NULL) || !FamilyServices->IsC6Supported (FamilyServices, Socket, PlatformConfig, StdHeader)) { + IsEnabled = FALSE; + break; + } + } + } + } + return IsEnabled; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Enable the C6 C-state + * + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +STATIC +InitializeC6Feature ( + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 BscSocket; + UINT32 Ignored; + UINT32 BscCoreNum; + UINT32 Core; + UINT32 Socket; + UINT32 NumberOfSockets; + UINT32 NumberOfCores; + AP_TASK TaskPtr; + AMD_CPU_EARLY_PARAMS CpuEarlyParams; + C6_FAMILY_SERVICES *C6FamilyServices; + AGESA_STATUS IgnoredSts; + + CpuEarlyParams.PlatformConfig = *PlatformConfig; + + TaskPtr.FuncAddress.PfApTaskIC = EnableC6OnSocket; + TaskPtr.DataTransfer.DataSizeInDwords = 2; + TaskPtr.DataTransfer.DataPtr = &EntryPoint; + TaskPtr.DataTransfer.DataTransferFlags = 0; + TaskPtr.ExeFlags = PASS_EARLY_PARAMS; + OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams); + + if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) { + // Load any required microcode patches on both normal boot and resume from S3. + IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); + GetFeatureServicesOfSocket (&C6FamilyServiceTable, BscSocket, (CONST VOID **)&C6FamilyServices, StdHeader); + if (C6FamilyServices != NULL) { + C6FamilyServices->ReloadMicrocodePatchAfterMemInit (StdHeader); + } + + // run code on all APs + TaskPtr.DataTransfer.DataSizeInDwords = 0; + TaskPtr.ExeFlags = 0; + + NumberOfSockets = GetPlatformNumberOfSockets (); + + for (Socket = 0; Socket < NumberOfSockets; Socket++) { + if (IsProcessorPresent (Socket, StdHeader)) { + GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, (CONST VOID **)&C6FamilyServices, StdHeader); + if (C6FamilyServices != NULL) { + // run code on all APs + TaskPtr.FuncAddress.PfApTask = C6FamilyServices->ReloadMicrocodePatchAfterMemInit; + if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { + for (Core = 0; Core < NumberOfCores; Core++) { + if ((Socket != BscSocket) || (Core != BscCoreNum)) { + ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); + } + } + } + } + } + } + } + return AGESA_SUCCESS; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * 'Local' core 0 task to enable C6 on it's socket. + * + * @param[in] EntryPoint Timepoint designator. + * @param[in] StdHeader Config Handle for library, services. + * @param[in] CpuEarlyParams Service parameters. + * + */ +VOID +STATIC +EnableC6OnSocket ( + IN VOID *EntryPoint, + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams + ) +{ + + C6_FAMILY_SERVICES *FamilyServices; + + IDS_HDT_CONSOLE (CPU_TRACE, " C6 is enabled\n"); + + GetFeatureServicesOfCurrentCore (&C6FamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); + FamilyServices->InitializeC6 (FamilyServices, + *((UINT64 *) EntryPoint), + &CpuEarlyParams->PlatformConfig, + StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Reload microcode patch after memory is initialized. + * + * @param[in] StdHeader Config Handle for library, services. + * + */ +VOID +ReloadMicrocodePatchAfterMemInit ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + LoadMicrocodePatch (StdHeader); +} + + +CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State = +{ + C6Cstate, + (CPU_FEAT_AFTER_PM_INIT | CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC), + IsC6FeatureEnabled, + InitializeC6Feature +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuC6State.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuC6State.h new file mode 100644 index 0000000..68a61b9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuC6State.h @@ -0,0 +1,183 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA CPU C6 Functions declarations. + * + * Contains code that declares the AGESA CPU C6 related APIs + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Feature + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_C6_STATE_H_ +#define _CPU_C6_STATE_H_ + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ +// Forward declaration needed for multi-structure mutual references +AGESA_FORWARD_DECLARATION (C6_FAMILY_SERVICES); + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to check if C6 is supported. + * + * @param[in] C6Services C6 C-state services. + * @param[in] Socket Zero-based socket number. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE C6 is supported. + * @retval FALSE C6 is not supported. + * + */ +typedef BOOLEAN F_C6_IS_SUPPORTED ( + IN C6_FAMILY_SERVICES *C6Services, + IN UINT32 Socket, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_C6_IS_SUPPORTED *PF_C6_IS_SUPPORTED; + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to enable C6. + * + * @param[in] C6Services C6 services. + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @return Family specific error value. + * + */ +typedef AGESA_STATUS F_C6_INIT ( + IN C6_FAMILY_SERVICES *C6Services, + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_C6_INIT *PF_C6_INIT; + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to reload microcode patch after memory is initialized. + * + * @param[in] StdHeader Config Handle for library, services. + * + */ +typedef VOID F_C6_RELOAD_MICORCODE_PATCH_AFTER_MEM_INIT ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_C6_RELOAD_MICORCODE_PATCH_AFTER_MEM_INIT *PF_C6_RELOAD_MICORCODE_PATCH_AFTER_MEM_INIT; + +/** + * Provide the interface to the C6 Family Specific Services. + * + * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). + * Each supported Family must provide an implementation for all methods in this interface, even if the + * implementation is a CommonReturn(). + */ +struct _C6_FAMILY_SERVICES { + UINT16 Revision; ///< Interface version + // Public Methods. + PF_C6_IS_SUPPORTED IsC6Supported; ///< Method: Family specific call to check if C6 is supported. + PF_C6_INIT InitializeC6; ///< Method: Family specific call to enable C6. + PF_C6_RELOAD_MICORCODE_PATCH_AFTER_MEM_INIT ReloadMicrocodePatchAfterMemInit; ///< Method: Family specific call to reload microcode patch after memory is initialized. +}; + +/*---------------------------------------------------------------------------------------*/ +/** + * Reload microcode patch after memory is initialized. + * + * @param[in] StdHeader Config Handle for library, services. + * + */ +VOID +ReloadMicrocodePatchAfterMemInit ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N S P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ + +#endif // _CPU_C6_STATE_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheFlushOnHalt.c new file mode 100644 index 0000000..3f95f52 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheFlushOnHalt.c @@ -0,0 +1,226 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Cache Flush On Halt Function. + * + * Contains code to initialize Cache Flush On Halt feature. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + *---------------------------------------------------------------------------- + */ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "cpuRegisters.h" +#include "cpuServices.h" +#include "cpuFamilyTranslation.h" +#include "cpuFeatures.h" +#include "cpuApicUtilities.h" +#include "OptionMultiSocket.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) +#define FILECODE PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern CPU_FAMILY_SUPPORT_TABLE CacheFlushOnHaltFamilyServiceTable; +extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +VOID +STATIC +EnableCacheFlushOnHaltOnSocket ( + IN VOID *EntryPoint, + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams + ); + +AGESA_STATUS +InitializeCacheFlushOnHaltFeature ( + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * P U B L I C F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Should cache flush on halt be enabled + * + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE core leveling is supported. + * @retval FALSE core leveling cannot be enabled. + * + */ +BOOLEAN +STATIC +IsCFOHEnabled ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return (TRUE); +} +/* -----------------------------------------------------------------------------*/ +/** + * + * InitializeCacheFlushOnHaltFeature + * + * CPU feature leveling. Enable Cpu Cache Flush On Halt Function + * + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in,out] StdHeader Pointer to AMD_CONFIG_PARAMS struct. + * + * @return The most severe status of any family specific service. + */ +AGESA_STATUS +InitializeCacheFlushOnHaltFeature ( + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + + AP_TASK TaskPtr; + AMD_CPU_EARLY_PARAMS CpuEarlyParams; + + CpuEarlyParams.PlatformConfig = *PlatformConfig; + + IDS_HDT_CONSOLE (CPU_TRACE, " Cache flush on hlt feature is enabled\n"); + TaskPtr.FuncAddress.PfApTaskIC = EnableCacheFlushOnHaltOnSocket; + TaskPtr.DataTransfer.DataSizeInDwords = 2; + TaskPtr.DataTransfer.DataPtr = &EntryPoint; + TaskPtr.DataTransfer.DataTransferFlags = 0; + TaskPtr.ExeFlags = PASS_EARLY_PARAMS; + OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams); + + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * 'Local' core 0 task to enable Cache Flush On Halt on it's socket. + * + * @param[in] EntryPoint Timepoint designator. + * @param[in] StdHeader Config Handle for library, services. + * @param[in] CpuEarlyParams Service parameters. + * + */ +VOID +STATIC +EnableCacheFlushOnHaltOnSocket ( + IN VOID *EntryPoint, + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams + ) +{ + CPU_CFOH_FAMILY_SERVICES *FamilyServices; + + GetFeatureServicesOfCurrentCore (&CacheFlushOnHaltFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); + if (FamilyServices != NULL) { + FamilyServices->SetCacheFlushOnHaltRegister (FamilyServices, *((UINT64 *) EntryPoint), &CpuEarlyParams->PlatformConfig, StdHeader); + } +} + +CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt = +{ + CacheFlushOnHalt, + (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC), + IsCFOHEnabled, + InitializeCacheFlushOnHaltFeature +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c new file mode 100644 index 0000000..3c37dd5 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c @@ -0,0 +1,778 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Execution Cache Allocation functions. + * + * Contains code for doing Execution Cache Allocation for ROM space + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "Topology.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "cpuCacheInit.h" +#include "heapManager.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +// 4G - 1, ~max ROM space +#define SIZE_INFINITE_EXE_CACHE 0xFFFFFFFFul + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * L2 cache Association to Way translation table + *---------------------------------------------------------------------------- + */ +CONST UINT8 ROMDATA L2AssocToL2WayTranslationTable[] = +{ + 0, + 1, + 2, + 0xFF, + 4, + 0xFF, + 8, + 0xFF, + 16, + 0xFF, + 32, + 48, + 64, + 96, + 128, + 0xFF, +}; + + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +UINT8 +STATIC +Ceiling ( + IN UINT32 Divisor, + IN UINT32 Dividend + ); + +UINT32 +STATIC +CalculateOccupiedExeCache ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +CompareRegions ( + IN EXECUTION_CACHE_REGION ARegion, + IN EXECUTION_CACHE_REGION BRegion, + IN OUT MERGED_CACHE_REGION *CRegion, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +STATIC +IsPowerOfTwo ( + IN UINT32 TestNumber + ); + +/*---------------------------------------------------------------------------------------*/ +/** + * This function will setup ROM execution cache. + * + * The execution cache regions are passed in, the max number of execution cache regions + * is three. Several rules are checked for compliance. If a rule test fails then one of + * these error suffixes will be added to the general CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + * in the SubReason field + * -1 available cache size is less than requested, the ROM execution cache + * region has been reduced or eliminated. + * -2 at least one execution cache region crosses the 1MB line, the ROM execution + * cache size has been reduced. + * -3 at least one execution cache region crosses the 4GB line, the ROM execution + * cache size has been reduced. + * -4 the start address of a region is not at the boundary of cache size, + * the starting address has been adjusted downward + * -5 execution cache start address less than D0000, request is ignored + * -6 more than 2 execution cache regions are above 1MB, request is ignored + * If the start address of all three regions are zero, then no execution cache is allocated. + * + * @param[in] StdHeader Handle to config for library and services + * @param[in] AmdExeAddrMapPtr Pointer to the start of EXECUTION_CACHE_REGION array + * + * @retval AGESA_SUCCESS No error + * @retval AGESA_WARNING AGESA_CACHE_SIZE_REDUCED; AGESA_CACHE_REGIONS_ACROSS_1MB; + * AGESA_CACHE_REGIONS_ACROSS_4GB; + * @retval AGESA_ERROR AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY; + * AGESA_CACHE_START_ADDRESS_LESS_D0000; + * AGESA_THREE_CACHE_REGIONS_ABOVE_1MB; + * + */ +AGESA_STATUS +AllocateExecutionCache ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr + ) +{ + AGESA_STATUS AgesaStatus; + AMD_GET_EXE_SIZE_PARAMS AmdGetExeSize; + UINT32 CurrentAllocatedExeCacheSize; + UINT32 RemainingExecutionCacheSize; + UINT64 MsrData; + UINT64 SecondMsrData; + UINT32 RequestStartAddr; + UINT32 RequestSize; + UINT32 StartFixMtrr; + UINT32 CurrentMtrr; + UINT32 EndFixMtrr; + UINT8 i; + UINT8 Ignored; + CACHE_INFO *CacheInfoPtr; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + EXECUTION_CACHE_REGION MtrrV6; + EXECUTION_CACHE_REGION MtrrV7; + MERGED_CACHE_REGION Result; + + // + // If start addresses of all three regions are zero, then return early + // + if (AmdExeAddrMapPtr[0].ExeCacheStartAddr == 0) { + if (AmdExeAddrMapPtr[1].ExeCacheStartAddr == 0) { + if (AmdExeAddrMapPtr[2].ExeCacheStartAddr == 0) { + // No regions defined by the caller + return AGESA_SUCCESS; + } + } + } + + // Get available cache size for ROM execution + AmdGetExeSize.StdHeader = *StdHeader; + AgesaStatus = AmdGetAvailableExeCacheSize (&AmdGetExeSize); + CurrentAllocatedExeCacheSize = CalculateOccupiedExeCache (StdHeader); + ASSERT (CurrentAllocatedExeCacheSize <= AmdGetExeSize.AvailableExeCacheSize); + IDS_HDT_CONSOLE (CPU_TRACE, " Cache size available for execution cache: 0x%x\n", AmdGetExeSize.AvailableExeCacheSize); + RemainingExecutionCacheSize = AmdGetExeSize.AvailableExeCacheSize - CurrentAllocatedExeCacheSize; + + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader); + + // Process each request entry 0 to 2 + for (i = 0; i < 3; i++) { + // Exit if no more cache available + if (RemainingExecutionCacheSize == 0) { + break; + } + + // Skip the region if ExeCacheSize = 0 + if (AmdExeAddrMapPtr[i].ExeCacheSize == 0) { + continue; + } + + // Align starting addresses on 32K boundary + AmdExeAddrMapPtr[i].ExeCacheStartAddr = + AmdExeAddrMapPtr[i].ExeCacheStartAddr & 0xFFFF8000; + + // Adjust size to multiple of 32K (rounding up) + if ((AmdExeAddrMapPtr[i].ExeCacheSize % 0x8000) != 0) { + AmdExeAddrMapPtr[i].ExeCacheSize = ((AmdExeAddrMapPtr[i].ExeCacheSize + 0x8000) & 0xFFFF8000); + } + + // Boundary alignment check and confirm size is an even power of two + if ( !IsPowerOfTwo (AmdExeAddrMapPtr[i].ExeCacheSize) || + ((AmdExeAddrMapPtr[i].ExeCacheStartAddr % AmdExeAddrMapPtr[i].ExeCacheSize) != 0) ) { + AgesaStatus = AGESA_ERROR; + PutEventLog (AgesaStatus, + (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY), + i, AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize, 0, StdHeader); + break; + } + + // Check start address boundary + if (AmdExeAddrMapPtr[i].ExeCacheStartAddr < 0xD0000) { + AgesaStatus = AGESA_ERROR; + PutEventLog (AgesaStatus, + (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_CACHE_START_ADDRESS_LESS_D0000), + i, AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize, 0, StdHeader); + break; + } + + if (CacheInfoPtr->CarExeType == LimitedByL2Size) { + // Verify available execution cache size for region 0 to 2 request + if (RemainingExecutionCacheSize < AmdExeAddrMapPtr[i].ExeCacheSize) { + // Request is larger than available, reduce the allocation & report the change + AmdExeAddrMapPtr[i].ExeCacheSize = RemainingExecutionCacheSize; + RemainingExecutionCacheSize = 0; + AgesaStatus = AGESA_WARNING; + PutEventLog (AgesaStatus, + (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_CACHE_SIZE_REDUCED), + i, AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize, 0, StdHeader); + } else { + RemainingExecutionCacheSize = RemainingExecutionCacheSize - AmdExeAddrMapPtr[i].ExeCacheSize; + } + } + IDS_HDT_CONSOLE (CPU_TRACE, " Exe cache allocated: Base 0x%x, Size 0x%x\n", AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize); + + RequestStartAddr = AmdExeAddrMapPtr[i].ExeCacheStartAddr; + RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize; + + if (RequestStartAddr < 0x100000) { + // Region starts below 1MB - Fixed MTTR region, + // turn on modification bit: MtrrFixDramModEn + LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); + MsrData |= 0x80000; + LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); + + + // Check for 1M boundary crossing + if ((RequestStartAddr + RequestSize) > 0x100000) { + // Request spans the 1M boundary, reduce the size & report the change + RequestSize = 0x100000 - RequestStartAddr; + AmdExeAddrMapPtr[i].ExeCacheSize = RequestSize; + AgesaStatus = AGESA_WARNING; + PutEventLog (AgesaStatus, + (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_CACHE_REGIONS_ACROSS_1MB), + i, RequestStartAddr, RequestSize, 0, StdHeader); + } + + // Find start MTTR and end MTTR for the requested region + StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7); + EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7); + + // + //Check Mtrr before we use it, + // if Mtrr has been used, we need to recover the previously allocated size. + // (only work in blocks of 32K size - no splitting of ways) + for (CurrentMtrr = StartFixMtrr; CurrentMtrr <= EndFixMtrr; CurrentMtrr++) { + LibAmdMsrRead (CurrentMtrr, &MsrData, StdHeader); + if ((CacheInfoPtr->CarExeType == LimitedByL2Size) && (MsrData != 0)) { + // MTRR previously allocated, recover size + RemainingExecutionCacheSize = RemainingExecutionCacheSize + 0x8000; + } else { + // Allocate this MTRR + MsrData = WP_IO; + LibAmdMsrWrite (CurrentMtrr, &MsrData, StdHeader); + } + } + // Turn off modification bit: MtrrFixDramModEn + LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); + MsrData &= 0xFFFFFFFFFFF7FFFFULL; + LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); + + + } else { + // Region above 1MB - Variable MTTR region + // Need to check both VarMTRRs for each requested region for match or overlap + // + + // Check for 4G boundary crossing (using size-1 to keep in 32bit math range) + if ((0xFFFFFFFFUL - RequestStartAddr) < (RequestSize - 1)) { + RequestSize = (0xFFFFFFFFUL - RequestStartAddr) + 1; + AgesaStatus = AGESA_WARNING; + AmdExeAddrMapPtr[i].ExeCacheSize = RequestSize; + PutEventLog (AgesaStatus, + (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_CACHE_REGIONS_ACROSS_4GB), + i, RequestStartAddr, RequestSize, 0, StdHeader); + } + LibAmdMsrRead (AMD_MTRR_VARIABLE_BASE6, &MsrData, StdHeader); + MtrrV6.ExeCacheStartAddr = ((UINT32) MsrData) & 0xFFFFF000UL; + LibAmdMsrRead (AMD_MTRR_VARIABLE_BASE6 + 1, &MsrData, StdHeader); + MtrrV6.ExeCacheSize = (0xFFFFFFFFUL - (((UINT32) MsrData) & 0xFFFFF000UL)) + 1; + + LibAmdMsrRead (AMD_MTRR_VARIABLE_BASE7, &MsrData, StdHeader); + MtrrV7.ExeCacheStartAddr = ((UINT32) MsrData) & 0xFFFFF000UL; + LibAmdMsrRead (AMD_MTRR_VARIABLE_BASE7 + 1, &MsrData, StdHeader); + MtrrV7.ExeCacheSize = (0xFFFFFFFFUL - (((UINT32) MsrData) & 0xFFFFF000UL)) + 1; + + CompareRegions (AmdExeAddrMapPtr[i], MtrrV6, &Result, StdHeader); + if (Result.OverlapType == EmptySet) { + // MTRR6 is empty. Allocate request into MTRR6. + // Note: since all merges are moved down to MTRR6, if MTRR6 is empty so should MTRR7 also be empty + MtrrV6.ExeCacheStartAddr = AmdExeAddrMapPtr[i].ExeCacheStartAddr; + MtrrV6.ExeCacheSize = AmdExeAddrMapPtr[i].ExeCacheSize; + } else if ((Result.OverlapType == Disjoint) || + (Result.OverlapType == NotCombinable)) { + // MTRR6 is in use, and request does not overlap with MTRR6, check MTRR7 + CompareRegions (AmdExeAddrMapPtr[i], MtrrV7, &Result, StdHeader); + if (Result.OverlapType == EmptySet) { + // MTRR7 is empty. Allocate request into MTRR7. + MtrrV7.ExeCacheStartAddr = AmdExeAddrMapPtr[i].ExeCacheStartAddr; + MtrrV7.ExeCacheSize = AmdExeAddrMapPtr[i].ExeCacheSize; + } else if ((Result.OverlapType == Disjoint) || + (Result.OverlapType == NotCombinable)) { + // MTRR7 is also in use and request does not overlap - error: 3rd region above 1M + AgesaStatus = AGESA_ERROR; + PutEventLog (AgesaStatus, + (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_THREE_CACHE_REGIONS_ABOVE_1MB), + i, AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize, 0, StdHeader); + break; + } else { + // Merge request with MTRR7 + MtrrV7.ExeCacheStartAddr = Result.MergedStartAddr; + MtrrV7.ExeCacheSize = Result.MergedSize; + if (CacheInfoPtr->CarExeType == LimitedByL2Size) { + RemainingExecutionCacheSize += Result.OverlapAmount; + } + } + } else { + // Request overlaps with MTRR6, Merge request with MTRR6 + MtrrV6.ExeCacheStartAddr = Result.MergedStartAddr; + MtrrV6.ExeCacheSize = Result.MergedSize; + if (CacheInfoPtr->CarExeType == LimitedByL2Size) { + RemainingExecutionCacheSize += Result.OverlapAmount; + } + CompareRegions (MtrrV6, MtrrV7, &Result, StdHeader); + if ((Result.OverlapType != Disjoint) && + (Result.OverlapType != EmptySet) && + (Result.OverlapType != NotCombinable)) { + // MTRR6 and MTRR7 now overlap, merge them into MTRR6 + MtrrV6.ExeCacheStartAddr = Result.MergedStartAddr; + MtrrV6.ExeCacheSize = Result.MergedSize; + MtrrV7.ExeCacheStartAddr = 0; + MtrrV7.ExeCacheSize = 0; + if (CacheInfoPtr->CarExeType == LimitedByL2Size) { + RemainingExecutionCacheSize += Result.OverlapAmount; + } + } + } + + // Set the VarMTRRs. Base first, then size/mask; this allows for expanding the region safely. + if (MtrrV6.ExeCacheSize != 0) { + MsrData = (UINT64) ( 0xFFFFFFFF00000000ULL | ((0xFFFFFFFFUL - (MtrrV6.ExeCacheSize - 1)) | 0x0800UL)); + MsrData &= CacheInfoPtr->VariableMtrrMask; + SecondMsrData = (UINT64) ( MtrrV6.ExeCacheStartAddr | (WP_IO & 0xFULL)); + } else { + MsrData = 0; + SecondMsrData = 0; + } + LibAmdMsrWrite (AMD_MTRR_VARIABLE_BASE6, &SecondMsrData, StdHeader); + LibAmdMsrWrite ((AMD_MTRR_VARIABLE_BASE6 + 1), &MsrData, StdHeader); + + if (MtrrV7.ExeCacheSize != 0) { + MsrData = (UINT64) ( 0xFFFFFFFF00000000ULL | ((0xFFFFFFFFUL - (MtrrV7.ExeCacheSize - 1)) | 0x0800UL)); + MsrData &= CacheInfoPtr->VariableMtrrMask; + SecondMsrData = (UINT64) ( MtrrV7.ExeCacheStartAddr | (WP_IO & 0xFULL)); + } else { + MsrData = 0; + SecondMsrData = 0; + } + LibAmdMsrWrite (AMD_MTRR_VARIABLE_BASE7, &SecondMsrData, StdHeader); + LibAmdMsrWrite ((AMD_MTRR_VARIABLE_BASE7 + 1), &MsrData, StdHeader); + } // endif of MTRR region check + } // end of requests For loop + + return AgesaStatus; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * This function calculates available L2 cache space for ROM execution. + * + * @param[in] AmdGetExeSizeParams Pointer to the start of AmdGetExeSizeParamsPtr structure + * + * @retval AGESA_SUCCESS No error + * @retval AGESA_ALERT No cache available for execution cache. + * + */ +AGESA_STATUS +AmdGetAvailableExeCacheSize ( + IN OUT AMD_GET_EXE_SIZE_PARAMS *AmdGetExeSizeParams + ) +{ + UINT8 WayUsedForCar; + UINT8 L2Assoc; + UINT32 L2Size; + UINT32 L2WaySize; + UINT32 CurrentCoreNum; + UINT8 L2Ways; + UINT8 Ignored; + UINT32 DieNumber; + UINT32 TotalCores; + CPUID_DATA CpuIdDataStruct; + CACHE_INFO *CacheInfoPtr; + AP_MAIL_INFO ApMailboxInfo; + AGESA_STATUS IgnoredStatus; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdGetExeSizeParams->StdHeader); + FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, &AmdGetExeSizeParams->StdHeader); + // CAR_EXE mode is either "Limited by L2 size" or "Infinite Execution space" + ASSERT (CacheInfoPtr->CarExeType < MaxCarExeMode); + if (CacheInfoPtr->CarExeType == InfiniteExe) { + AmdGetExeSizeParams->AvailableExeCacheSize = SIZE_INFINITE_EXE_CACHE; + return AGESA_SUCCESS; + } + + // EXE cache size is limited by size of the L2, minus previous allocations for stack, heap, etc. + // Check for L2 cache size and way size + LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuIdDataStruct, &AmdGetExeSizeParams->StdHeader); + L2Assoc = (UINT8) ((CpuIdDataStruct.ECX_Reg >> 12) & 0x0F); + + // get L2Ways from L2 Association to Way translation table + L2Ways = L2AssocToL2WayTranslationTable[L2Assoc]; + ASSERT (L2Ways != 0xFF); + + // get L2Size + L2Size = 1024 * ((CpuIdDataStruct.ECX_Reg >> 16) & 0xFFFF); + + // get each L2WaySize + L2WaySize = L2Size / L2Ways; + + // Determine the size for execution cache + if (IsBsp (&AmdGetExeSizeParams->StdHeader, &IgnoredStatus)) { + // BSC (Boot Strap Core) + WayUsedForCar = Ceiling (CacheInfoPtr->BspStackSize, L2WaySize) + + Ceiling (CacheInfoPtr->MemTrainingBufferSize, L2WaySize) + + Ceiling (AMD_HEAP_SIZE_PER_CORE , L2WaySize) + + Ceiling (CacheInfoPtr->SharedMemSize, L2WaySize); + } else { + // AP (Application Processor) + GetCurrentCore (&CurrentCoreNum, &AmdGetExeSizeParams->StdHeader); + + GetApMailbox (&ApMailboxInfo.Info, &AmdGetExeSizeParams->StdHeader); + DieNumber = (1 << ApMailboxInfo.Fields.ModuleType); + GetActiveCoresInCurrentSocket (&TotalCores, &AmdGetExeSizeParams->StdHeader); + ASSERT ((TotalCores % DieNumber) == 0); + if ((CurrentCoreNum % (TotalCores / DieNumber)) == 0) { + WayUsedForCar = Ceiling (CacheInfoPtr->Core0StackSize , L2WaySize) + + Ceiling (CacheInfoPtr->MemTrainingBufferSize, L2WaySize) + + Ceiling (AMD_HEAP_SIZE_PER_CORE , L2WaySize) + + Ceiling (CacheInfoPtr->SharedMemSize, L2WaySize); + } else { + WayUsedForCar = Ceiling (CacheInfoPtr->Core1StackSize , L2WaySize) + + Ceiling (AMD_HEAP_SIZE_PER_CORE , L2WaySize) + + Ceiling (CacheInfoPtr->SharedMemSize, L2WaySize); + } + } + + ASSERT (WayUsedForCar < L2Ways); + + if (WayUsedForCar < L2Ways) { + AmdGetExeSizeParams->AvailableExeCacheSize = L2WaySize * (L2Ways - WayUsedForCar); + return AGESA_SUCCESS; + } else { + AmdGetExeSizeParams->AvailableExeCacheSize = 0; + return AGESA_ALERT; + } +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * This function rounds a quotient up if the remainder is not zero. + * + * @param[in] Divisor The divisor + * @param[in] Dividend The dividend + * + * @retval Value Rounded quotient + * + */ +UINT8 +STATIC +Ceiling ( + IN UINT32 Divisor, + IN UINT32 Dividend + ) +{ + if ((Divisor % Dividend) == 0) { + return (UINT8) (Divisor / Dividend); + } else { + return (UINT8) ((Divisor / Dividend) + 1); + } +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * This function calculates the amount of cache that has already been allocated on the + * executing core. + * + * @param[in] StdHeader Handle to config for library and services + * + * @returns Allocated size in bytes + * + */ +UINT32 +STATIC +CalculateOccupiedExeCache ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 OccupExeCacheSize; + UINT64 MsrData; + UINT8 i; + + MsrData = 0; + OccupExeCacheSize = 0; + + // + //Calculate Variable MTRR base 6~7 + // + for (i = 0; i < 2; i++) { + LibAmdMsrRead ((AMD_MTRR_VARIABLE_BASE6 + (2*i)), &MsrData, StdHeader); + if (MsrData != 0) { + LibAmdMsrRead ((AMD_MTRR_VARIABLE_BASE6 + (2*i + 1)), &MsrData, StdHeader); + OccupExeCacheSize = OccupExeCacheSize + ((~((MsrData & (0xFFFF8000)) - 1))&0xFFFF8000); + } + } + + // + //Calculate Fixed MTRR base D0000~F8000 + // + for (i = 0; i < 6; i++) { + LibAmdMsrRead ((AMD_MTRR_FIX4K_BASE + 2 + i), &MsrData, StdHeader); + if (MsrData!= 0) { + OccupExeCacheSize = OccupExeCacheSize + 0x8000; + } + } + + return (UINT32)OccupExeCacheSize; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * This function compares two memory regions for overlap and returns the combined + * Base,Size to describe the new combined region. + * + * There are 13 cases for how two regions may overlap: key: [] region A, ** region B + * 1- [ ] *** 9- *** [ ] disjoint regions + * 2- [ ]*** 10- ***[ ] adjacent regions + * 3- [ ***] 11- **[**] common ending + * 4- [ *]** 12- *[** ] extending + * 5- [ ** ] 13- *[*]* contained + * 6- [*** ] common start, contained + * 7- [***] identity + * 8- [**]** common start, extending + * 0- one of the regions is empty (has base=0) + * + * @param[in] ARegion pointer to the base,size pair that describes region A + * @param[in] BRegion pointer to the base,size pair that describes region B + * @param[in,out] CRegion pointer to the base,size pair that describes region C This struct also has the + * overlap type and the amount of overlap between the regions. + * @param[in] StdHeader Handle to config for library and services + * + * @returns void, nothing + */ + +VOID +STATIC +CompareRegions ( + IN EXECUTION_CACHE_REGION ARegion, + IN EXECUTION_CACHE_REGION BRegion, + IN OUT MERGED_CACHE_REGION *CRegion, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + // Use Int64 to handle regions ending at or above the 4G boundary. + UINT64 EndOfA; + UINT64 EndOfB; + + + if ((BRegion.ExeCacheStartAddr == 0) || + (ARegion.ExeCacheStartAddr == 0)) { + CRegion->MergedStartAddr = + CRegion->MergedSize = + CRegion->OverlapAmount = 0; + CRegion->OverlapType = EmptySet; + return; + } + if (BRegion.ExeCacheStartAddr < ARegion.ExeCacheStartAddr) { + //swap regions A & B. this collapses types 9-13 onto 1-5 and reduces the number of tests + CRegion->MergedStartAddr = ARegion.ExeCacheStartAddr; + CRegion->MergedSize = ARegion.ExeCacheSize; + ARegion = BRegion; + BRegion.ExeCacheStartAddr = CRegion->MergedStartAddr; + BRegion.ExeCacheSize = CRegion->MergedSize; + } + CRegion->MergedStartAddr = + CRegion->MergedSize = + CRegion->OverlapType = + CRegion->OverlapAmount = 0; + + if (ARegion.ExeCacheStartAddr == BRegion.ExeCacheStartAddr) { + // Common start, cases 6,7, or 8 + if (ARegion.ExeCacheSize == BRegion.ExeCacheSize) { + // case 7, identity. Need to recover the overlap size + CRegion->MergedStartAddr = ARegion.ExeCacheStartAddr; + CRegion->MergedSize = ARegion.ExeCacheSize; + CRegion->OverlapAmount = ARegion.ExeCacheSize; + CRegion->OverlapType = Identity; + } else if (ARegion.ExeCacheSize < BRegion.ExeCacheSize) { + // case 8, common start extending + CRegion->MergedStartAddr = ARegion.ExeCacheStartAddr; + CRegion->MergedSize = BRegion.ExeCacheSize; + CRegion->OverlapType = CommonStartExtending; + CRegion->OverlapAmount = ARegion.ExeCacheSize; + } else { + // case 6, common start contained + CRegion->MergedStartAddr = ARegion.ExeCacheStartAddr; + CRegion->MergedSize = ARegion.ExeCacheSize; + CRegion->OverlapType = CommonStartContained; + CRegion->OverlapAmount = BRegion.ExeCacheSize; + } + } else { + // A_Base is less than B_Base. check for cases 1-5 + EndOfA = ((UINT64) ARegion.ExeCacheStartAddr) + ((UINT64) ARegion.ExeCacheSize); + + if (EndOfA < ((UINT64) BRegion.ExeCacheStartAddr)) { + // case 1, disjoint + CRegion->MergedStartAddr = + CRegion->MergedSize = + CRegion->OverlapAmount = 0; + CRegion->OverlapType = Disjoint; + + } else if (EndOfA == ((UINT64) BRegion.ExeCacheStartAddr)) { + // case 2, adjacent + CRegion->OverlapType = Adjacent; + CRegion->MergedStartAddr = ARegion.ExeCacheStartAddr; + CRegion->MergedSize = ARegion.ExeCacheSize + BRegion.ExeCacheSize; + CRegion->OverlapAmount = 0; + } else { + // EndOfA is > B_Base. check for cases 3,4,5 + EndOfB = ((UINT64) BRegion.ExeCacheStartAddr) + ((UINT64) BRegion.ExeCacheSize); + + if ( EndOfA < EndOfB) { + // case 4, extending + CRegion->OverlapType = Extending; + CRegion->MergedStartAddr = ARegion.ExeCacheStartAddr; + CRegion->MergedSize = (UINT32) (EndOfB - ((UINT64) ARegion.ExeCacheStartAddr)); + CRegion->OverlapAmount = (UINT32) (EndOfA - ((UINT64) BRegion.ExeCacheStartAddr)); + } else { + // case 3, same end; or case 5, contained + CRegion->OverlapType = Contained; + CRegion->MergedStartAddr = ARegion.ExeCacheStartAddr; + CRegion->MergedSize = ARegion.ExeCacheSize; + CRegion->OverlapAmount = BRegion.ExeCacheSize; + } + } + } // endif + // Once we have combined the regions, they must still obey the MTRR size and boundary rules + if ( CRegion->OverlapType != Disjoint ) { + if ((!(IsPowerOfTwo (CRegion->MergedSize))) || + ((CRegion->MergedStartAddr % CRegion->MergedSize) != 0) ) { + CRegion->OverlapType = NotCombinable; + } + } + +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * This local function tests the parameter for being an even power of two + * + * @param[in] TestNumber Number to check + * + * @retval TRUE - TestNumber is a power of two, + * @retval FALSE - TestNumber is not a power of two + * + */ +BOOLEAN +STATIC +IsPowerOfTwo ( + IN UINT32 TestNumber + ) +{ + UINT32 PowerTwo; + + ASSERT (TestNumber >= 0x8000UL); + PowerTwo = 0x8000UL; // Start at 32K + while ( TestNumber > PowerTwo ) { + PowerTwo = PowerTwo * 2; + } + return (((TestNumber % PowerTwo) == 0) ? TRUE: FALSE); +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.h new file mode 100644 index 0000000..6e72bee --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.h @@ -0,0 +1,165 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Execution Cache Allocation functions. + * + * Contains code for doing Execution Cache Allocation for ROM space + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_CACHE_INIT_H_ +#define _CPU_CACHE_INIT_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ +#define BSP_STACK_SIZE_64K 65536 +#define BSP_STACK_SIZE_32K 32768 + +#define CORE0_STACK_SIZE 16384 +#define CORE1_STACK_SIZE 4096 + +#define AMD_MTRR_FIX4K_BASE 0x268 +#define AMD_MTRR_VARIABLE_BASE6 0x20C +#define AMD_MTRR_VARIABLE_BASE7 0x20E + +#define WP_IO 0x0505050505050505ull + +#define AGESA_CACHE_SIZE_REDUCED 1 +#define AGESA_CACHE_REGIONS_ACROSS_1MB 2 +#define AGESA_CACHE_REGIONS_ACROSS_4GB 3 +#define AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 4 +#define AGESA_CACHE_START_ADDRESS_LESS_D0000 5 +#define AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 6 +#define AGESA_DEALLOCATE_CACHE_REGIONS 7 + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ +/// Cache-As-Ram Executable region allocation modes +typedef enum { + LimitedByL2Size, ///< Execution space must be allocated from L2 + InfiniteExe, ///< Family can support unlimited Execution space + MaxCarExeMode ///< Used as limit or bounds check +} CAR_EXE_MODE; + +/// Cache Information +typedef struct { + IN UINT32 BspStackSize; ///< Stack size of BSP + IN UINT32 Core0StackSize; ///< Stack size of primary cores + IN UINT32 Core1StackSize; ///< Stack size of all non primary cores + IN UINT32 MemTrainingBufferSize; ///< Memory training buffer size + IN UINT32 SharedMemSize; ///< Shared memory size + IN UINT64 VariableMtrrMask; ///< Mask to apply before variable MTRR writes + IN UINT64 VariableMtrrHeapMask; ///< Mask to apply before variable MTRR writes for use in heap init. + IN UINT64 HeapBaseMask; ///< Mask used for the heap MTRR settings + IN CAR_EXE_MODE CarExeType; ///< Indicates which algorithm to use when allocating EXE space +} CACHE_INFO; + +/// Merged memory region overlap type +typedef enum { + EmptySet, ///< One of the regions is zero length + Disjoint, ///< The two regions do not touch + Adjacent, ///< one region is next to the other, no gap + CommonEnd, ///< regions overlap with a common end point + Extending, ///< the 2nd region is extending the size of the 1st + Contained, ///< the 2nd region is wholely contained inside the 1st + CommonStartContained, ///< the 2nd region is contained in the 1st with a common start + Identity, ///< the two regions are the same + CommonStartExtending, ///< the 2nd region has same start as 1st, but is larger size + NotCombinable ///< the combined regions do not follow the cache block rules +} OVERLAP_TYPE; + +/// Result of merging two memory regions for cache coverage +typedef struct { + IN OUT UINT32 MergedStartAddr; ///< Start address of the merged regions + IN OUT UINT32 MergedSize; ///< Size of the merged regions + OUT UINT32 OverlapAmount; ///< the size of the overlapping section + OUT OVERLAP_TYPE OverlapType; ///< indicates how the two regions overlap +} MERGED_CACHE_REGION; + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ +AGESA_STATUS +AllocateExecutionCache ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr + ); + +#endif // _CPU_CACHE_INIT_H_ + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCdit.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCdit.c new file mode 100644 index 0000000..62129a7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCdit.c @@ -0,0 +1,369 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CDIT, ACPI table related API functions. + * + * Contains code that generates the CDIT table + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------- + * This file provides functions, that will generate SLIT tables + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "OptionCdit.h" +#include "heapManager.h" +#include "cpuLateInit.h" +#include "cpuRegisters.h" +#include "Ids.h" +#include "cpuFeatures.h" +#include "cpuFamilyTranslation.h" +#include "cpuL3Features.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FEATURE_CPUCDIT_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern OPTION_CDIT_CONFIGURATION OptionCditConfiguration; // global user config record + +STATIC ACPI_TABLE_HEADER ROMDATA CpuCditHdrStruct = +{ + {'C','D','I','T'}, + 0, + 1, + 0, + {'A','M','D',' ',' ',' '}, + {'A','G','E','S','A',' ',' ',' '}, + 1, + {'A','M','D',' '}, + 1 +}; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +AcpiCditHBufferFind ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN UINT8 **SocketTopologyPtr + ); + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GetAcpiCditStub ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + OUT VOID **CditPtr + ); + +AGESA_STATUS +GetAcpiCditMain ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + OUT VOID **CditPtr + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +extern CPU_FAMILY_SUPPORT_TABLE L3FeatureFamilyServiceTable; + +/*---------------------------------------------------------------------------------------*/ +/** + * + * This function generates a complete CDIT table into a memory buffer. + * After completion, this table must be set by the system BIOS into its + * internal ACPI namespace, and linked into the RSDT/XSDT + * + * @param[in, out] StdHeader Standard Head Pointer + * @param[in] PlatformConfig Config handle for platform specific information + * @param[out] CditPtr Point to Cdit Struct including buffer address and length + * + * @retval UINT32 AGESA_STATUS + */ +AGESA_STATUS +CreateAcpiCdit ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + OUT VOID **CditPtr + ) +{ + AGESA_TESTPOINT (Agtp6d , StdHeader); + return ((*(OptionCditConfiguration.CditFeature)) (StdHeader, PlatformConfig, CditPtr)); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * + * This is the default routine for use when the CDIT option is NOT requested. + * + * The option install process will create and fill the transfer vector with + * the address of the proper routine (Main or Stub). The link optimizer will + * strip out of the .DLL the routine that is not used. + * + * @param[in, out] StdHeader Standard Head Pointer + * @param[in] PlatformConfig Config handle for platform specific information + * @param[out] CditPtr Point to Cdit Struct including buffer address and length + * + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GetAcpiCditStub ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + OUT VOID **CditPtr + ) +{ + return AGESA_UNSUPPORTED; +} +/*---------------------------------------------------------------------------------------*/ +/** + * + * This function generates a complete CDIT table into a memory buffer. + * After completion, this table must be set by the system BIOS into its + * internal ACPI namespace, and linked into the RSDT/XSDT + * + * @param[in, out] StdHeader Standard Head Pointer + * @param[in] PlatformConfig Config handle for platform specific information + * @param[out] CditPtr Point to Cdit Struct including buffer address and length + * + * @retval UINT32 AGESA_STATUS + */ +AGESA_STATUS +GetAcpiCditMain ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + OUT VOID **CditPtr + ) +{ + UINT8 MaxHops; + UINT8 DomainNum; + UINT8 i; + UINT8 j; + UINT8 *BufferPtr; + UINT8 *SocketTopologyDataPtr; + UINT8 *SocketTopologyPtr; + UINT32 Socket; + BOOLEAN IsProbeFilterEnabled; + ACPI_TABLE_HEADER *CpuCditHeaderStructPtr; + AGESA_STATUS Flag; + ALLOCATE_HEAP_PARAMS AllocStruct; + L3_FEATURE_FAMILY_SERVICES *FamilyServices; + + MaxHops = 0; + SocketTopologyPtr = NULL; + Flag = AGESA_ERROR; + IsProbeFilterEnabled = FALSE; + + // find out the pointer to the BufferHandle which contains + // Node Topology information + AcpiCditHBufferFind (StdHeader, &SocketTopologyPtr); + if (SocketTopologyPtr == NULL) { + return (Flag); + } + + DomainNum = *SocketTopologyPtr; + + IDS_HDT_CONSOLE (CPU_TRACE, " CDIT is created\n"); + + // create a buffer by calling IBV callout routine + AllocStruct.RequestedBufferSize = (DomainNum * DomainNum) + AMD_ACPI_CDIT_NUM_DOMAINS_LENGTH + sizeof (ACPI_TABLE_HEADER); + AllocStruct.BufferHandle = AMD_ACPI_CDIT_BUFFER_HANDLE; + AllocStruct.Persist = HEAP_SYSTEM_MEM; + if (HeapAllocateBuffer (&AllocStruct, StdHeader) != AGESA_SUCCESS) { + return (Flag); + } + *CditPtr = AllocStruct.BufferPtr; + + //CDIT header + LibAmdMemCopy (*CditPtr, (VOID *) &CpuCditHdrStruct, (UINTN) (sizeof (ACPI_TABLE_HEADER)), StdHeader); + CpuCditHeaderStructPtr = (ACPI_TABLE_HEADER *) *CditPtr; + CpuCditHeaderStructPtr->TableLength = (UINT32) AllocStruct.RequestedBufferSize; + BufferPtr = *CditPtr; + + Flag = AGESA_SUCCESS; + // CDIT body + // Check if Probe Filter is enabled + if (IsFeatureEnabled (L3Features, PlatformConfig, StdHeader)) { + IsProbeFilterEnabled = TRUE; + for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { + if (IsProcessorPresent (Socket, StdHeader)) { + GetFeatureServicesOfSocket (&L3FeatureFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader); + if ((FamilyServices == NULL) || (!FamilyServices->IsHtAssistSupported (FamilyServices, PlatformConfig, StdHeader))) { + IsProbeFilterEnabled = FALSE; + break; + } + } + } + } + + + if (!IsProbeFilterEnabled) { + // probe filter is disabled + // get MaxHops + SocketTopologyDataPtr = SocketTopologyPtr + sizeof (DomainNum); + for (i = 0; i < DomainNum; i++) { + for (j = 0; j < DomainNum; j++) { + if (*SocketTopologyDataPtr > MaxHops) { + MaxHops = *SocketTopologyDataPtr; + } + SocketTopologyDataPtr++; + } + } + + // the Max hop entries have a value of 13 + // and all other entries have 10. + SocketTopologyDataPtr = SocketTopologyPtr + sizeof (DomainNum); + for (i = 0; i < DomainNum; i++) { + for (j = 0; j < DomainNum; j++) { + if (*SocketTopologyDataPtr++ == MaxHops) { + *(BufferPtr + sizeof (ACPI_TABLE_HEADER) + + AMD_ACPI_CDIT_NUM_DOMAINS_LENGTH + (i * DomainNum) + j) = 13; + } else { + *(BufferPtr + sizeof (ACPI_TABLE_HEADER) + + AMD_ACPI_CDIT_NUM_DOMAINS_LENGTH + (i * DomainNum) + j) = 10; + } + } + } + } else { + // probe filter is enabled + // formula : num_hops * 6 + 10 + SocketTopologyDataPtr = SocketTopologyPtr + sizeof (DomainNum); + for (i = 0; i < DomainNum; i++) { + for (j = 0; j < DomainNum; j++) { + *(BufferPtr + sizeof (ACPI_TABLE_HEADER) + + AMD_ACPI_CDIT_NUM_DOMAINS_LENGTH + (i * DomainNum) + j) = + ((*SocketTopologyDataPtr++) * 6) + 10; + } + } + } + + BufferPtr += sizeof (ACPI_TABLE_HEADER); + *((UINT32 *) BufferPtr) = (UINT32) DomainNum; + + //Update CDIT header Checksum + ChecksumAcpiTable ((ACPI_TABLE_HEADER *) *CditPtr, StdHeader); + + return (Flag); +} + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * + * Find out the pointer to the BufferHandle which contains + * Node Topology information + * + * @param[in, out] StdHeader Standard Head Pointer + * @param[in] SocketTopologyPtr Point to the address of Socket Topology + * + */ +VOID +STATIC +AcpiCditHBufferFind ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN UINT8 **SocketTopologyPtr + ) +{ + LOCATE_HEAP_PTR LocateBuffer; + + LocateBuffer.BufferHandle = HOP_COUNT_TABLE_HANDLE; + if (HeapLocateBuffer (&LocateBuffer, StdHeader) == AGESA_SUCCESS) { + *SocketTopologyPtr = (UINT8 *) LocateBuffer.BufferPtr; + } + + return; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCoreLeveling.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCoreLeveling.c new file mode 100644 index 0000000..04d34a8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCoreLeveling.c @@ -0,0 +1,389 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Core Leveling Function. + * + * Contains code to Level the number of core in a multi-socket system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + *---------------------------------------------------------------------------- + */ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "AMD.h" +#include "Topology.h" +#include "cpuRegisters.h" +#include "GeneralServices.h" +#include "cpuServices.h" +#include "cpuFamilyTranslation.h" +#include "cpuFeatures.h" +#include "cpuEarlyInit.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) +#define FILECODE PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern CPU_FAMILY_SUPPORT_TABLE CoreLevelingFamilyServiceTable; + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +AGESA_STATUS +CoreLevelingAtEarly ( + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * P U B L I C F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Should core leveling be enabled + * + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE core leveling is supported. + * @retval FALSE core leveling cannot be enabled. + * + */ +BOOLEAN +STATIC +IsCoreLevelingEnabled ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + CORE_LEVELING_TYPE CoreLevelMode; + + CoreLevelMode = (CORE_LEVELING_TYPE) PlatformConfig->CoreLevelingMode; + if (CoreLevelMode != CORE_LEVEL_NONE) { + return (TRUE); + } else { + return (FALSE); + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Performs core leveling for the system. + * + * This function implements the AMD_CPU_EARLY_PARAMS.CoreLevelingMode parameter. + * The possible modes are: + * -0 CORE_LEVEL_LOWEST Level to lowest common denominator + * -1 CORE_LEVEL_TWO Level to 2 cores + * -2 CORE_LEVEL_POWER_OF_TWO Level to 1,2,4 or 8 + * -3 CORE_LEVEL_NONE Do no leveling + * -4 CORE_LEVEL_COMPUTE_UNIT Level cores to one core per compute unit + * + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the leveling mode parameter + * @param[in] StdHeader Config handle for library and services + * + * @return The most severe status of any family specific service. + * + */ +AGESA_STATUS +CoreLevelingAtEarly ( + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 CoreNumPerComputeUnit; + UINT32 MinNumOfComputeUnit; + UINT32 EnabledComputeUnit; + UINT32 Socket; + UINT32 Module; + UINT32 NumberOfSockets; + UINT32 NumberOfModules; + UINT32 MinCoreCountOnNode; + UINT32 MaxCoreCountOnNode; + UINT32 LowCore; + UINT32 HighCore; + UINT32 LeveledCores; + UINT32 RequestedCores; + UINT32 TotalEnabledCoresOnNode; + BOOLEAN RegUpdated; + AP_MAIL_INFO ApMailboxInfo; + CORE_LEVELING_TYPE CoreLevelMode; + CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices; + WARM_RESET_REQUEST Request; + + IDS_HDT_CONSOLE (CPU_TRACE, "CoreLevelingAtEarly\n CoreLevelMode: %d\n", PlatformConfig->CoreLevelingMode); + + MaxCoreCountOnNode = 0; + MinCoreCountOnNode = 0xFFFFFFFF; + LeveledCores = 0; + CoreNumPerComputeUnit = 1; + MinNumOfComputeUnit = 0xFF; + + ASSERT (PlatformConfig->CoreLevelingMode < CoreLevelModeMax); + + // Get OEM IO core level mode + CoreLevelMode = (CORE_LEVELING_TYPE) PlatformConfig->CoreLevelingMode; + + // Get socket count + NumberOfSockets = GetPlatformNumberOfSockets (); + GetApMailbox (&ApMailboxInfo.Info, StdHeader); + NumberOfModules = ApMailboxInfo.Fields.ModuleType + 1; + + // Collect cpu core info + for (Socket = 0; Socket < NumberOfSockets; Socket++) { + if (IsProcessorPresent (Socket, StdHeader)) { + for (Module = 0; Module < NumberOfModules; Module++) { + if (GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader)) { + // Get the highest and lowest core count in all nodes + TotalEnabledCoresOnNode = HighCore - LowCore + 1; + if (TotalEnabledCoresOnNode < MinCoreCountOnNode) { + MinCoreCountOnNode = TotalEnabledCoresOnNode; + } + if (TotalEnabledCoresOnNode > MaxCoreCountOnNode) { + MaxCoreCountOnNode = TotalEnabledCoresOnNode; + } + EnabledComputeUnit = TotalEnabledCoresOnNode; + switch (GetComputeUnitMapping (StdHeader)) { + case AllCoresMapping: + // All cores are in their own compute unit. + break; + case EvenCoresMapping: + // Cores are paired in compute units. + CoreNumPerComputeUnit = 2; + EnabledComputeUnit = (TotalEnabledCoresOnNode / 2); + break; + default: + ASSERT (FALSE); + } + // Get minimum of compute unit. This will either be the minimum number of cores (AllCoresMapping), + // or less (EvenCoresMapping). + if (EnabledComputeUnit < MinNumOfComputeUnit) { + MinNumOfComputeUnit = EnabledComputeUnit; + } + IDS_HDT_CONSOLE (CPU_TRACE, " Socket %d Module %d MaxCoreCountOnNode %d MinCoreCountOnNode %d TotalEnabledCoresOnNode %d EnabledComputeUnit %d MinNumOfComputeUnit %d\n", \ + Socket, Module, MaxCoreCountOnNode, MinCoreCountOnNode, TotalEnabledCoresOnNode, EnabledComputeUnit, MinNumOfComputeUnit); + } + } + } + } + + // Get LeveledCores + switch (CoreLevelMode) { + case CORE_LEVEL_LOWEST: + if (MinCoreCountOnNode == MaxCoreCountOnNode) { + return (AGESA_SUCCESS); + } + LeveledCores = (MinCoreCountOnNode / CoreNumPerComputeUnit) * CoreNumPerComputeUnit; + break; + case CORE_LEVEL_TWO: + LeveledCores = 2 / NumberOfModules; + if (LeveledCores != 0) { + LeveledCores = (LeveledCores <= MinCoreCountOnNode) ? LeveledCores : MinCoreCountOnNode; + } else { + return (AGESA_WARNING); + } + if ((LeveledCores * NumberOfModules) != 2) { + PutEventLog ( + AGESA_WARNING, + CPU_WARNING_ADJUSTED_LEVELING_MODE, + 2, (LeveledCores * NumberOfModules), 0, 0, StdHeader + ); + } + break; + case CORE_LEVEL_POWER_OF_TWO: + // Level to power of 2 (1, 2, 4, 8...) + LeveledCores = 1; + while (MinCoreCountOnNode >= (LeveledCores * 2)) { + LeveledCores = LeveledCores * 2; + } + break; + case CORE_LEVEL_COMPUTE_UNIT: + // Level cores to one core per compute unit, with additional reduction to level + // all processors to match the processor with the minimum number of cores. + if (CoreNumPerComputeUnit == 1) { + // If there is one core per compute unit, this is the same as CORE_LEVEL_LOWEST. + if (MinCoreCountOnNode == MaxCoreCountOnNode) { + return (AGESA_SUCCESS); + } + LeveledCores = MinCoreCountOnNode; + } else { + // If there are more than one core per compute unit, level to the number of compute units. + LeveledCores = MinNumOfComputeUnit; + } + break; + case CORE_LEVEL_ONE: + LeveledCores = 1; + if (NumberOfModules > 1) { + PutEventLog ( + AGESA_WARNING, + CPU_WARNING_ADJUSTED_LEVELING_MODE, + 1, NumberOfModules, 0, 0, StdHeader + ); + } + break; + case CORE_LEVEL_THREE: + case CORE_LEVEL_FOUR: + case CORE_LEVEL_FIVE: + case CORE_LEVEL_SIX: + case CORE_LEVEL_SEVEN: + case CORE_LEVEL_EIGHT: + case CORE_LEVEL_NINE: + case CORE_LEVEL_TEN: + case CORE_LEVEL_ELEVEN: + case CORE_LEVEL_TWELVE: + case CORE_LEVEL_THIRTEEN: + case CORE_LEVEL_FOURTEEN: + case CORE_LEVEL_FIFTEEN: + // MCM processors can not have an odd number of cores. For an odd CORE_LEVEL_N, MCM processors will be + // leveled as though CORE_LEVEL_N+1 was chosen. + // Processors with compute units disable all cores in an entire compute unit at a time, or on an MCM processor, + // two compute units at a time. For example, on an SCM processor with two cores per compute unit, the effective + // explicit levels are CORE_LEVEL_ONE, CORE_LEVEL_TWO, CORE_LEVEL_FOUR, CORE_LEVEL_SIX, and + // CORE_LEVEL_EIGHT. The same example for an MCM processor with two cores per compute unit has effective + // explicit levels of CORE_LEVEL_TWO, CORE_LEVEL_FOUR, CORE_LEVEL_EIGHT, and CORE_LEVEL_TWELVE. + RequestedCores = CoreLevelMode - CORE_LEVEL_THREE + 3; + LeveledCores = (RequestedCores + NumberOfModules - 1) / NumberOfModules; + LeveledCores = (LeveledCores / CoreNumPerComputeUnit) * CoreNumPerComputeUnit; + LeveledCores = (LeveledCores <= MinCoreCountOnNode) ? LeveledCores : MinCoreCountOnNode; + if (LeveledCores != 1) { + LeveledCores = (LeveledCores / CoreNumPerComputeUnit) * CoreNumPerComputeUnit; + } + if ((LeveledCores * NumberOfModules * CoreNumPerComputeUnit) != RequestedCores) { + PutEventLog ( + AGESA_WARNING, + CPU_WARNING_ADJUSTED_LEVELING_MODE, + RequestedCores, (LeveledCores * NumberOfModules * CoreNumPerComputeUnit), 0, 0, StdHeader + ); + } + break; + default: + ASSERT (FALSE); + } + + // Set down core register + for (Socket = 0; Socket < NumberOfSockets; Socket++) { + if (IsProcessorPresent (Socket, StdHeader)) { + GetFeatureServicesOfSocket (&CoreLevelingFamilyServiceTable, Socket, (CONST VOID **)&FamilySpecificServices, StdHeader); + if (FamilySpecificServices != NULL) { + for (Module = 0; Module < NumberOfModules; Module++) { + IDS_HDT_CONSOLE (CPU_TRACE, " SetDownCoreRegister: Socket %d Module %d LeveledCores %d CoreLevelMode %d\n", Socket, Module, LeveledCores, CoreLevelMode); + RegUpdated = FamilySpecificServices->SetDownCoreRegister (FamilySpecificServices, &Socket, &Module, &LeveledCores, CoreLevelMode, StdHeader); + // If the down core register is updated, trigger a warm reset. + if (RegUpdated) { + GetWarmResetFlag (StdHeader, &Request); + Request.RequestBit = TRUE; + Request.StateBits = Request.PostStage - 1; + IDS_HDT_CONSOLE (CPU_TRACE, " Request a warm reset.\n"); + SetWarmResetFlag (StdHeader, &Request); + } + } + } + } + } + + return (AGESA_SUCCESS); +} + + +CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling = +{ + CoreLeveling, + (CPU_FEAT_AFTER_PM_INIT), + IsCoreLevelingEnabled, + CoreLevelingAtEarly +}; + +/*---------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCpb.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCpb.c new file mode 100644 index 0000000..9fb1c13 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCpb.c @@ -0,0 +1,202 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA CPU Core performance boost feature support code. + * + * Contains code that declares the AGESA CPU CPB related APIs + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Feature + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuFamilyTranslation.h" +#include "cpuFeatures.h" +#include "cpuCpb.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FEATURE_CPUCPB_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern CPU_FAMILY_SUPPORT_TABLE CpbFamilyServiceTable; + +/*---------------------------------------------------------------------------------------*/ +/** + * Should CPB be enabled + * + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE CPB is supported. + * @retval FALSE CPB cannot be enabled. + * + */ +BOOLEAN +STATIC +IsCpbFeatureEnabled ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Socket; + BOOLEAN IsEnabled; + CPB_FAMILY_SERVICES *FamilyServices; + + IsEnabled = FALSE; + + ASSERT (PlatformConfig->CpbMode < MaxCpbMode); + + if (PlatformConfig->CpbMode == CpbModeAuto) { + for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { + if (IsProcessorPresent (Socket, StdHeader)) { + GetFeatureServicesOfSocket (&CpbFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader); + if (FamilyServices != NULL) { + if (FamilyServices->IsCpbSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) { + IsEnabled = TRUE; + break; + } + } + } + } + } + return IsEnabled; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Enable core performance boost + * + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +STATIC +InitializeCpbFeature ( + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Socket; + AGESA_STATUS AgesaStatus; + AGESA_STATUS CalledStatus; + CPB_FAMILY_SERVICES *FamilyServices; + + AgesaStatus = AGESA_SUCCESS; + CalledStatus = AGESA_SUCCESS; + + IDS_HDT_CONSOLE (CPU_TRACE, " Boost is enabled\n"); + + for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { + if (IsProcessorPresent (Socket, StdHeader)) { + GetFeatureServicesOfSocket (&CpbFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader); + if (FamilyServices != NULL) { + if (FamilyServices->IsCpbSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) { + CalledStatus = FamilyServices->EnableCpbOnSocket (FamilyServices, PlatformConfig, EntryPoint, Socket, StdHeader); + if (CalledStatus > AgesaStatus) { + AgesaStatus = CalledStatus; + } + } + } + } + } + + return AgesaStatus; +} + + +CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb = +{ + CoreBoost, + (CPU_FEAT_BEFORE_PM_INIT | CPU_FEAT_AFTER_PM_INIT | CPU_FEAT_INIT_LATE_END | CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_S3_LATE_RESTORE_END | CPU_FEAT_AFTER_RESUME_MTRR_SYNC), + IsCpbFeatureEnabled, + InitializeCpbFeature +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCpb.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCpb.h new file mode 100644 index 0000000..b06bca4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCpb.h @@ -0,0 +1,160 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA CPU Core Performance Boost Functions declarations. + * + * Contains code that declares the AGESA CPU CPB related APIs + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Feature + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_CPB_H_ +#define _CPU_CPB_H_ + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ +// Forward declaration needed for multi-structure mutual references +AGESA_FORWARD_DECLARATION (CPB_FAMILY_SERVICES); + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to check if CPB is supported. + * + * @param[in] CpbServices Core Performance Boost services. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] Socket Zero-based socket number. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE CPB is supported. + * @retval FALSE CPB is not supported. + * + */ +typedef BOOLEAN F_CPB_IS_SUPPORTED ( + IN CPB_FAMILY_SERVICES *CpbServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN UINT32 Socket, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_CPB_IS_SUPPORTED *PF_CPB_IS_SUPPORTED; + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to enable CPB. + * + * @param[in] CpbServices Core Performance Boost services. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] EntryPoint Timepoint designator. + * @param[in] Socket Zero-based socket number. + * @param[in] StdHeader Config Handle for library, services. + * + * @return Family specific error value. + * + */ +typedef AGESA_STATUS F_CPB_INIT ( + IN CPB_FAMILY_SERVICES *CpbServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN UINT64 EntryPoint, + IN UINT32 Socket, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_CPB_INIT *PF_CPB_INIT; + +/** + * Provide the interface to the CPB Family Specific Services. + * + * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). + * Each supported Family must provide an implementation for all methods in this interface, even if the + * implementation is a CommonReturn(). + */ +struct _CPB_FAMILY_SERVICES { + UINT16 Revision; ///< Interface version + // Public Methods. + PF_CPB_IS_SUPPORTED IsCpbSupported; ///< Method: Family specific call to check if CPB is supported. + PF_CPB_INIT EnableCpbOnSocket; ///< Method: Family specific call to enable CPB. +}; + + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N S P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ + +#endif // _CPU_CPB_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCrat.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCrat.c new file mode 100644 index 0000000..5a9de7c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCrat.c @@ -0,0 +1,535 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CRAT, ACPI table related API functions. + * + * Contains code that Create the APCI CRAT Table after early reset. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FEATURE + * @e $Revision: 64574 $ @e $Date: 2012-01-25 01:01:51 -0600 (Wed, 25 Jan 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ***************************************************************************/ + + +/*---------------------------------------------------------------------------- + * This file provides functions, that will generate CRAT tables + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuServices.h" +#include "OptionCrat.h" +#include "cpuCrat.h" +#include "mfCrat.h" +#include "heapManager.h" +#include "cpuRegisters.h" +#include "cpuFamilyTranslation.h" +#include "cpuLateInit.h" +#include "Ids.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FEATURE_CPUCRAT_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern OPTION_CRAT_CONFIGURATION OptionCratConfiguration; // global user config record +extern CPU_FAMILY_SUPPORT_TABLE CratFamilyServiceTable; +extern S_MAKE_CRAT_ENTRY MakeCratEntryTable[]; + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GetAcpiCratStub ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + OUT VOID **CratPtr + ); + +AGESA_STATUS +GetAcpiCratMain ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + OUT VOID **CratPtr + ); + +/*---------------------------------------------------------------------------- + * All of the DATA should be defined in _CODE segment. + * Use ROMDATA to specify that it belongs to _CODE. + *---------------------------------------------------------------------------- + */ +CONST UINT8 ROMDATA L2L3Associativity[] = +{ + 0, + 1, + 2, + 0, + 4, + 0, + 8, + 0, + 16, + 0, + 32, + 48, + 64, + 96, + 128, + 0xFF +}; + +STATIC CRAT_HEADER ROMDATA CratHeaderStruct = +{ + {'C','R','A','T'}, + 0, + 1, + 0, + {'A','M','D',' ',' ',' '}, + {'A','G','E','S','A',' ',' ',' '}, + 1, + {'A','M','D',' '}, + 1, + 0, + 0, + {0, 0, 0, 0, 0, 0} +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------------------*/ +/** + * + * This function will generate a complete Component Resource Affinity Table + * i.e. CRAT into a memory buffer. After completion, this table must be set + * by the system BIOS into its internal ACPI name space. + * + * @param[in, out] StdHeader Standard Head Pointer + * @param[out] CratPtr Point to Crat Struct including buffer address and length + * + * @retval AGESA_STATUS + */ + +AGESA_STATUS +CreateAcpiCrat ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + OUT VOID **CratPtr + ) +{ + AGESA_TESTPOINT (Agtp6c , StdHeader); + return ((*(OptionCratConfiguration.CratFeature)) (StdHeader, CratPtr)); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * + * This is the default routine for use when the CRAT option is NOT requested. + * + * The option install process will create and fill the transfer vector with + * the address of the proper routine (Main or Stub). The link optimizer will + * strip out of the .DLL the routine that is not used. + * + * @param[in, out] StdHeader Standard Head Pointer + * @param[out] CratPtr Point to Crat Struct including buffer address and length + * + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GetAcpiCratStub ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + OUT VOID **CratPtr + ) +{ + return AGESA_UNSUPPORTED; +} +/*---------------------------------------------------------------------------------------*/ +/** + * + * This function will generate a complete Component Resource Affinity Table + * i.e. CRAT into a memory buffer. After completion, this table must be set + * by the system BIOS into its internal ACPI name space. + * + * @param[in, out] StdHeader Standard Head Pointer + * @param[out] CratPtr Point to Crat Struct including buffer address and length + * + * @retval AGESA_STATUS + */ +AGESA_STATUS +GetAcpiCratMain ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + OUT VOID **CratPtr + ) +{ + UINT8 i; + UINT8 *TableEnd; + CRAT_HEADER *CratHeaderStructPtr; + ALLOCATE_HEAP_PARAMS AllocParams; + + // Allocate a buffer + AllocParams.RequestedBufferSize = CRAT_MAX_LENGTH; + AllocParams.BufferHandle = AMD_CRAT_INFO_BUFFER_HANDLE; + AllocParams.Persist = HEAP_SYSTEM_MEM; + + if (HeapAllocateBuffer (&AllocParams, StdHeader) != AGESA_SUCCESS) { + return AGESA_ERROR; + } + *CratPtr = AllocParams.BufferPtr; + + + CratHeaderStructPtr = (CRAT_HEADER *) *CratPtr; + TableEnd = (UINT8 *) *CratPtr; + + // Copy CratHeaderStruct -> data buffer + LibAmdMemCopy ((VOID *) CratHeaderStructPtr, (VOID *) &CratHeaderStruct, (UINTN) (sizeof (CRAT_HEADER)), StdHeader); + + TableEnd += sizeof (CRAT_HEADER); + + // Make all CRAT entries. + for (i = 0; MakeCratEntryTable[i].MakeCratEntry != NULL; i++) { + MakeCratEntryTable[i].MakeCratEntry (CratHeaderStructPtr, &TableEnd, StdHeader); + + } + + // Store size in table (current buffer offset - buffer start offset) + CratHeaderStructPtr->Length = (UINT32) (TableEnd - (UINT8 *) CratHeaderStructPtr); + + //Update SSDT header Checksum + ChecksumAcpiTable ((ACPI_TABLE_HEADER *) CratHeaderStructPtr, StdHeader); + IDS_HDT_CONSOLE (CPU_TRACE, " CRAT is created\n"); + return AGESA_SUCCESS; +} + + +/*---------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------*/ +/** + * This function will add HSA Processing Unit entry. + * + * @param[in] CratHeaderStructPtr CRAT header pointer + * @param[in, out] TableEnd The end of CRAT + * @param[in, out] StdHeader Standard Head Pointer + * + */ +VOID +MakeHSAProcUnitEntry ( + IN CRAT_HEADER *CratHeaderStructPtr, + IN OUT UINT8 **TableEnd, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 NodeNum; + UINT8 NodeCount; + UINT32 Socket; + UINT32 Module; + UINT32 LowCore; + UINT32 HighCore; + UINT32 RegVal; + CRAT_HSA_PROCESSING_UNIT *EntryPtr; + AMD_APIC_PARAMS ApicParams; + PCI_ADDR PciAddress; + + // Get Node count + PciAddress.AddressValue = MAKE_SBDFO (0, 0, LOW_NODE_DEVICEID, FUNC_0, 0x60); + LibAmdPciRead (AccessWidth32 , PciAddress, &RegVal, StdHeader); + NodeCount = (UINT8) (((RegVal >> 4) & 0x7) + 1); + + NodeNum = 0; + ApicParams.StdHeader = *StdHeader; + while (NodeNum < NodeCount) { + GetSocketModuleOfNode ((UINT32) NodeNum, &Socket, &Module, StdHeader); + GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader); + ApicParams.Socket = (UINT8) Socket; + ApicParams.Core = 0; + AmdGetApicId (&ApicParams); + if (ApicParams.IsPresent) { + // Adding one CRAT entry for every node + EntryPtr = (CRAT_HSA_PROCESSING_UNIT *) AddOneCratEntry (CRAT_TYPE_HSA_PROC_UNIT, CratHeaderStructPtr, TableEnd, StdHeader); + + EntryPtr->ProximityDomain = NodeNum; + EntryPtr->ProcessorIdLow = ApicParams.ApicAddress; + EntryPtr->CpuCoreCount = (UINT16) (HighCore - LowCore + 1); + EntryPtr->Flags.Enabled = 1; + EntryPtr->Flags.CpuPresent = 1; + } + /// @todo SimdCount SimdWidth IoCount + CratHeaderStructPtr->NumDomains++; + NodeNum++; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * This function will add memory entry. + * + * @param[in] CratHeaderStructPtr CRAT header pointer + * @param[in, out] TableEnd The end of CRAT + * @param[in, out] StdHeader Standard Head Pointer + * + */ +VOID +MakeMemoryEntry ( + IN CRAT_HEADER *CratHeaderStructPtr, + IN OUT UINT8 **TableEnd, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 EntryNum; + UINT8 NumOfMemAffinityInfoEntries; + UINT32 Width; + AGESA_STATUS AgesaStatus; + CRAT_MEMORY *EntryPtr; + LOCATE_HEAP_PTR LocateHeapParams; + CRAT_MEMORY_AFFINITY_INFO_HEADER *MemAffinityInfoHeaderPtr; + CRAT_MEMORY_AFFINITY_INFO_ENTRY *MemAffinityInfoEntryPtr; + + EntryNum = 0; + + // Get the CRAT memory affinity info from heap + LocateHeapParams.BufferHandle = AMD_MEM_CRAT_INFO_BUFFER_HANDLE; + AgesaStatus = HeapLocateBuffer (&LocateHeapParams, StdHeader); + if (AgesaStatus != AGESA_SUCCESS) { + ASSERT (FALSE); + } else { + MemAffinityInfoHeaderPtr = (CRAT_MEMORY_AFFINITY_INFO_HEADER *) (LocateHeapParams.BufferPtr); + MemAffinityInfoHeaderPtr ++; + MemAffinityInfoEntryPtr = (CRAT_MEMORY_AFFINITY_INFO_ENTRY *) MemAffinityInfoHeaderPtr; + MemAffinityInfoHeaderPtr --; + + // Get the number of CRAT memory affinity entries + NumOfMemAffinityInfoEntries = MemAffinityInfoHeaderPtr->NumOfMemAffinityInfoEntries; + Width = MemAffinityInfoHeaderPtr->MemoryWidth; + + // Create CRAT memory affinity entries + IDS_HDT_CONSOLE (MAIN_FLOW, " CRAT memory affinity entries\n"); + while (EntryNum < NumOfMemAffinityInfoEntries) { + // Add one CRAT memory entry + EntryPtr = (CRAT_MEMORY *) AddOneCratEntry (CRAT_TYPE_MEMORY, CratHeaderStructPtr, TableEnd, StdHeader); + EntryPtr->Flags.Enabled = 1; + EntryPtr->ProximityDomain = MemAffinityInfoEntryPtr->Domain; + EntryPtr->BaseAddressLow = MemAffinityInfoEntryPtr->BaseAddressLow; + EntryPtr->BaseAddressHigh = MemAffinityInfoEntryPtr->BaseAddressHigh; + EntryPtr->LengthLow = MemAffinityInfoEntryPtr->LengthLow; + EntryPtr->LengthHigh = MemAffinityInfoEntryPtr->LengthHigh; + EntryPtr->Width = Width; + IDS_HDT_CONSOLE (MAIN_FLOW, " Entry #%d\n", EntryNum); + IDS_HDT_CONSOLE (MAIN_FLOW, " Type: 0x%08x\n", EntryPtr->Type); + IDS_HDT_CONSOLE (MAIN_FLOW, " Length: 0x%08x\n", EntryPtr->Length); + IDS_HDT_CONSOLE (MAIN_FLOW, " Flags: %s %s %s\n", (EntryPtr->Flags.Enabled == 1) ? "Enabled" : "", + (EntryPtr->Flags.HotPluggable == 1) ? "EnHotPluggableabled" : "", + (EntryPtr->Flags.NonVolatile == 1) ? "NonVolatile" : "" + ); + IDS_HDT_CONSOLE (MAIN_FLOW, " Proximity Domain: 0x%08x\n", EntryPtr->ProximityDomain); + IDS_HDT_CONSOLE (MAIN_FLOW, " Base Address Low: 0x%08x\n", EntryPtr->BaseAddressLow); + IDS_HDT_CONSOLE (MAIN_FLOW, " Base Address High: 0x%08x\n", EntryPtr->BaseAddressHigh); + IDS_HDT_CONSOLE (MAIN_FLOW, " Length Low: 0x%08x\n", EntryPtr->LengthLow); + IDS_HDT_CONSOLE (MAIN_FLOW, " Length High: 0x%08x\n", EntryPtr->LengthHigh); + IDS_HDT_CONSOLE (MAIN_FLOW, " Width: 0x%08x\n", EntryPtr->Width); + MemAffinityInfoEntryPtr ++; + EntryNum ++; + } + HeapDeallocateBuffer ((UINT32) AMD_MEM_CRAT_INFO_BUFFER_HANDLE, StdHeader); + } + + return; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * This function will add cache entry. + * + * @param[in] CratHeaderStructPtr CRAT header pointer + * @param[in, out] TableEnd The end of CRAT + * @param[in, out] StdHeader Standard Head Pointer + * + */ +VOID +MakeCacheEntry ( + IN CRAT_HEADER *CratHeaderStructPtr, + IN OUT UINT8 **TableEnd, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + CRAT_FAMILY_SERVICES *CratFamilyServices; + + GetFeatureServicesOfSocket (&CratFamilyServiceTable, 0, (CONST VOID **)&CratFamilyServices, StdHeader); + CratFamilyServices->generateCratCacheEntry (CratHeaderStructPtr, TableEnd, StdHeader); + return; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * This function will add TLB entry. + * + * @param[in] CratHeaderStructPtr CRAT header pointer + * @param[in, out] TableEnd The end of CRAT + * @param[in, out] StdHeader Standard Head Pointer + * + */ +VOID +MakeTLBEntry ( + IN CRAT_HEADER *CratHeaderStructPtr, + IN OUT UINT8 **TableEnd, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + CRAT_FAMILY_SERVICES *CratFamilyServices; + + GetFeatureServicesOfSocket (&CratFamilyServiceTable, 0, (CONST VOID **)&CratFamilyServices, StdHeader); + CratFamilyServices->generateCratTLBEntry (CratHeaderStructPtr, TableEnd, StdHeader); + return; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * This function will add CRAT entry. + * + * @param[in] CratEntryType CRAT entry type + * @param[in] CratHeaderStructPtr CRAT header pointer + * @param[in, out] TableEnd The end of CRAT + * @param[in, out] StdHeader Standard Head Pointer + * + */ +UINT8 * +AddOneCratEntry ( + IN CRAT_ENTRY_TYPE CratEntryType, + IN CRAT_HEADER *CratHeaderStructPtr, + IN OUT UINT8 **TableEnd, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 *CurrentEntry; + + CurrentEntry = *TableEnd; + CratHeaderStructPtr->TotalEntries++; + switch (CratEntryType) { + case CRAT_TYPE_HSA_PROC_UNIT: + *TableEnd += sizeof (CRAT_HSA_PROCESSING_UNIT); + ASSERT ((*TableEnd - (UINT8 *) CratHeaderStructPtr) <= CRAT_MAX_LENGTH); + CratHeaderStructPtr->Length += sizeof (CRAT_HSA_PROCESSING_UNIT); + ((CRAT_HSA_PROCESSING_UNIT *) CurrentEntry)->Type = (UINT8) CratEntryType; + ((CRAT_HSA_PROCESSING_UNIT *) CurrentEntry)->Length = sizeof (CRAT_HSA_PROCESSING_UNIT); + break; + case CRAT_TYPE_MEMORY: + *TableEnd += sizeof (CRAT_MEMORY); + ASSERT ((*TableEnd - (UINT8 *) CratHeaderStructPtr) <= CRAT_MAX_LENGTH); + CratHeaderStructPtr->Length += sizeof (CRAT_MEMORY); + ((CRAT_MEMORY *) CurrentEntry)->Type = (UINT8) CratEntryType; + ((CRAT_MEMORY *) CurrentEntry)->Length = sizeof (CRAT_MEMORY); + break; + case CRAT_TYPE_CACHE: + *TableEnd += sizeof (CRAT_CACHE); + ASSERT ((*TableEnd - (UINT8 *) CratHeaderStructPtr) <= CRAT_MAX_LENGTH); + CratHeaderStructPtr->Length += sizeof (CRAT_CACHE); + ((CRAT_CACHE *) CurrentEntry)->Type = (UINT8) CratEntryType; + ((CRAT_CACHE *) CurrentEntry)->Length = sizeof (CRAT_CACHE); + break; + case CRAT_TYPE_TLB: + *TableEnd += sizeof (CRAT_TLB); + ASSERT ((*TableEnd - (UINT8 *) CratHeaderStructPtr) <= CRAT_MAX_LENGTH); + CratHeaderStructPtr->Length += sizeof (CRAT_TLB); + ((CRAT_TLB *) CurrentEntry)->Type = (UINT8) CratEntryType; + ((CRAT_TLB *) CurrentEntry)->Length = sizeof (CRAT_TLB); + break; + case CRAT_TYPE_FPU: + *TableEnd += sizeof (CRAT_FPU); + ASSERT ((*TableEnd - (UINT8 *) CratHeaderStructPtr) <= CRAT_MAX_LENGTH); + CratHeaderStructPtr->Length += sizeof (CRAT_FPU); + ((CRAT_FPU *) CurrentEntry)->Type = (UINT8) CratEntryType; + ((CRAT_FPU *) CurrentEntry)->Length = sizeof (CRAT_FPU); + break; + case CRAT_TYPE_IO: + *TableEnd += sizeof (CRAT_IO); + ASSERT ((*TableEnd - (UINT8 *) CratHeaderStructPtr) <= CRAT_MAX_LENGTH); + CratHeaderStructPtr->Length += sizeof (CRAT_IO); + ((CRAT_IO *) CurrentEntry)->Type = (UINT8) CratEntryType; + ((CRAT_IO *) CurrentEntry)->Length = sizeof (CRAT_IO); + break; + default: + ASSERT (FALSE); + break; + } + return CurrentEntry; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCrat.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCrat.h new file mode 100644 index 0000000..a699694 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCrat.h @@ -0,0 +1,112 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA CPU CRAT + * + * Contains code that declares the AGESA CRAT related APIs + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Feature + * @e $Revision: 63552 $ @e $Date: 2011-12-26 19:46:05 -0600 (Mon, 26 Dec 2011) $ + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_CRAT_H_ +#define _CPU_CRAT_H_ + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/** + * Make CRAT entry + * + * @param[in] CratHeaderStructPtr CRAT header pointer + * @param[in, out] TableEnd The end of CRAT + * @param[in, out] StdHeader Standard Head Pointer + * + */ +typedef VOID F_MAKE_CRAT_ENTRY ( + IN CRAT_HEADER *CratHeaderStructPtr, + IN OUT UINT8 **TableEnd, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); +/// Reference to a Method. +typedef F_MAKE_CRAT_ENTRY *PF_MAKE_CRAT_ENTRY; + +/** + * A struct that contains function pointe + */ +typedef struct _S_MAKE_CRAT_ENTRY { + PF_MAKE_CRAT_ENTRY MakeCratEntry; ///< Function Pointer, which points to the function which makes CRAT entry. +} S_MAKE_CRAT_ENTRY; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +#endif // _CPU_CRAT_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c new file mode 100644 index 0000000..23fd79f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c @@ -0,0 +1,867 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD DMI Record Creation API, and related functions. + * + * Contains code that produce the DMI related information. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 64351 $ @e $Date: 2012-01-19 03:50:41 -0600 (Thu, 19 Jan 2012) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "OptionDmi.h" +#include "cpuLateInit.h" +#include "cpuServices.h" +#include "cpuRegisters.h" +#include "GeneralServices.h" +#include "heapManager.h" +#include "Ids.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FEATURE_CPUDMI_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern OPTION_DMI_CONFIGURATION OptionDmiConfiguration; // global user config record + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +CHAR8 ROMDATA str_ProcManufacturer[] = "Advanced Micro Devices, Inc."; +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +UINT16 +STATIC +AdjustGranularity ( + IN UINT32 *CacheSizePtr + ); + +VOID +STATIC +IntToString ( + IN OUT CHAR8 *String, + IN UINT8 *Integer, + IN UINT8 SizeInByte +); + +AGESA_STATUS +GetDmiInfoStub ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT DMI_INFO **DmiTable + ); + +AGESA_STATUS +GetDmiInfoMain ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT DMI_INFO **DmiTable + ); + +AGESA_STATUS +ReleaseDmiBufferStub ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +ReleaseDmiBuffer ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * CreateDmiRecords + * + * Description: + * This function creates DMI/SMBios records pertinent to the processor + * SMBIOS type 4, type 7, and type 40. + * + * Parameters: + * @param[in, out] *StdHeader + * @param[in, out] **DmiTable + * + * @retval AGESA_STATUS + * + */ + +AGESA_STATUS +CreateDmiRecords ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT DMI_INFO **DmiTable + ) +{ + AGESA_TESTPOINT (TpProcCpuEntryDmi, StdHeader); + return ((*(OptionDmiConfiguration.DmiFeature)) (StdHeader, DmiTable)); +} + +/* -----------------------------------------------------------------------------*/ +/** + * GetDmiInfoStub + * + * Description: + * This is the default routine for use when the DMI option is NOT requested. + * The option install process will create and fill the transfer vector with + * the address of the proper routine (Main or Stub). The link optimizer will + * strip out of the .DLL the routine that is not used. + * + * Parameters: + * @param[in, out] *StdHeader + * @param[in, out] **DmiTable + * + * @retval AGESA_STATUS + * + */ +AGESA_STATUS +GetDmiInfoStub ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT DMI_INFO **DmiTable + ) +{ + return AGESA_UNSUPPORTED; +} + +/* -----------------------------------------------------------------------------*/ +/** + * GetDmiInfoMain + * + * Description: + * This is the common routine for getting Dmi type4 and type7 CPU related information. + * + * Parameters: + * @param[in, out] *StdHeader + * @param[in, out] **DmiTable + * + * @retval AGESA_STATUS + * + */ +AGESA_STATUS +GetDmiInfoMain ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT DMI_INFO **DmiTable + ) +{ + UINT8 Socket; + UINT8 Channel; + UINT8 Dimm; + UINT16 Index; + UINT16 DimmIndex; + UINT8 NumberOfDimm; + UINT32 MaxCapacity; + UINT64 MsrData; + UINT64 LocalMsrRegister; + UINT8 TypeDetail; + BOOLEAN FamilyNotFound; + AGESA_STATUS Flag; + AGESA_STATUS CalledStatus; + AP_EXE_PARAMS ApParams; + MEM_DMI_INFO *MemInfo; + DMI_T17_MEMORY_TYPE MemType; + DMI_INFO *DmiBufferPtr; + ALLOCATE_HEAP_PARAMS AllocateHeapParams; + LOCATE_HEAP_PTR LocateHeapParams; + CPU_LOGICAL_ID LogicalId; + PROC_FAMILY_TABLE *ProcData; + CPU_GET_MEM_INFO CpuGetMemInfo; + + MsrData = 0; + Flag = TRUE; + ProcData = NULL; + MemInfo = NULL; + DmiBufferPtr = *DmiTable; + FamilyNotFound = TRUE; + + GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); + for (Index = 0; Index < OptionDmiConfiguration.NumEntries; Index++) { + ProcData = (PROC_FAMILY_TABLE *) ((*OptionDmiConfiguration.FamilyList)[Index]); + if ((ProcData->ProcessorFamily & LogicalId.Family) != 0) { + FamilyNotFound = FALSE; + break; + } + } + + if (FamilyNotFound) { + return AGESA_ERROR; + } + + if (DmiBufferPtr == NULL) { + // + // Allocate a buffer by heap function + // + AllocateHeapParams.BufferHandle = AMD_DMI_INFO_BUFFER_HANDLE; + AllocateHeapParams.RequestedBufferSize = sizeof (DMI_INFO); + AllocateHeapParams.Persist = HEAP_SYSTEM_MEM; + + if (HeapAllocateBuffer (&AllocateHeapParams, StdHeader) != AGESA_SUCCESS) { + return AGESA_ERROR; + } + + DmiBufferPtr = (DMI_INFO *) AllocateHeapParams.BufferPtr; + *DmiTable = DmiBufferPtr; + } + + IDS_HDT_CONSOLE (CPU_TRACE, " DMI is enabled\n"); + + // Fill with 0x00 + LibAmdMemFill (DmiBufferPtr, 0x00, sizeof (DMI_INFO), StdHeader); + + // + // Get CPU information + // + + // Run GetType4Type7Info on all core0s. + ApParams.StdHeader = *StdHeader; + ApParams.FunctionNumber = AP_LATE_TASK_GET_TYPE4_TYPE7; + ApParams.RelatedDataBlock = (VOID *) DmiBufferPtr; + ApParams.RelatedBlockLength = sizeof (DMI_INFO); + CalledStatus = RunLateApTaskOnAllCore0s (&ApParams, StdHeader); + if (CalledStatus > Flag) { + Flag = CalledStatus; + } + CalledStatus = GetType4Type7Info (&ApParams); + if (CalledStatus > Flag) { + Flag = CalledStatus; + } + + //------------------------------ + // T Y P E 16 17 19 20 + //------------------------------ + + LocateHeapParams.BufferHandle = AMD_DMI_MEM_DEV_INFO_HANDLE; + if (HeapLocateBuffer (&LocateHeapParams, StdHeader) != AGESA_SUCCESS) { + if (Flag < AGESA_ERROR) { + Flag = AGESA_ERROR; + } + } else { + NumberOfDimm = *((UINT8 *) (LocateHeapParams.BufferPtr)); + TypeDetail = *((UINT8 *) (LocateHeapParams.BufferPtr) + 1); + MemType = *((DMI_T17_MEMORY_TYPE *) ((UINT8 *) (LocateHeapParams.BufferPtr) + 6)); + MemInfo = (MEM_DMI_INFO *) ((UINT8 *) (LocateHeapParams.BufferPtr) + 6 + sizeof (DMI_T17_MEMORY_TYPE)); + // TYPE 16 + DmiBufferPtr->T16.Location = 0x03; + DmiBufferPtr->T16.Use = 0x03; + + // Gather memory information + ProcData->DmiGetMemInfo (&CpuGetMemInfo, StdHeader); + + if (CpuGetMemInfo.EccCapable) { + DmiBufferPtr->T16.MemoryErrorCorrection = Dmi16MultiBitEcc; + } else { + DmiBufferPtr->T16.MemoryErrorCorrection = Dmi16NoneErrCorrection; + } + + MaxCapacity = *((UINT32 *) ((UINT8 *) (LocateHeapParams.BufferPtr) + 2)); + // For the total size >= 2TB case, we need leave MaximumCapacity (offset 07h) to 80000000h + // and fill the size in bytes into ExtMaxCapacity (offset 0Fh). + if (MaxCapacity < 0x200000) { + DmiBufferPtr->T16.MaximumCapacity = MaxCapacity << 10; + DmiBufferPtr->T16.ExtMaxCapacity = 0; + } else { + DmiBufferPtr->T16.MaximumCapacity = 0x80000000; + DmiBufferPtr->T16.ExtMaxCapacity = (UINT64) MaxCapacity << 20; + } + + DmiBufferPtr->T16.NumberOfMemoryDevices = (UINT16) NumberOfDimm; + + // TYPE 17 + for (DimmIndex = 0; DimmIndex < NumberOfDimm; DimmIndex++) { + Socket = (MemInfo + DimmIndex)->Socket; + Channel = (MemInfo + DimmIndex)->Channel; + Dimm = (MemInfo + DimmIndex)->Dimm; + + DmiBufferPtr->T17[Socket][Channel][Dimm].TotalWidth = (MemInfo + DimmIndex)->TotalWidth; + DmiBufferPtr->T17[Socket][Channel][Dimm].DataWidth = (MemInfo + DimmIndex)->DataWidth; + DmiBufferPtr->T17[Socket][Channel][Dimm].MemorySize = (MemInfo + DimmIndex)->MemorySize; + DmiBufferPtr->T17[Socket][Channel][Dimm].FormFactor = (MemInfo + DimmIndex)->FormFactor; + DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceSet = 0; + + DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[0] = 'D'; + DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[1] = 'I'; + DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[2] = 'M'; + DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[3] = 'M'; + DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[4] = ' '; + DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[5] = Dimm + 0x30; + DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[6] = '\0'; + DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[7] = '\0'; + + DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[0] = 'C'; + DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[1] = 'H'; + DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[2] = 'A'; + DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[3] = 'N'; + DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[4] = 'N'; + DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[5] = 'E'; + DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[6] = 'L'; + DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[7] = ' '; + DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[8] = Channel + 0x41; + DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[9] = '\0'; + + DmiBufferPtr->T17[Socket][Channel][Dimm].MemoryType = MemType; + if ((MemInfo + DimmIndex)->MemorySize != 0) { + DmiBufferPtr->T17[Socket][Channel][Dimm].TypeDetail.Synchronous = 1; + if (TypeDetail == 1) { + DmiBufferPtr->T17[Socket][Channel][Dimm].TypeDetail.Registered = 1; + } else if (TypeDetail == 2) { + DmiBufferPtr->T17[Socket][Channel][Dimm].TypeDetail.Unbuffered = 1; + } else { + DmiBufferPtr->T17[Socket][Channel][Dimm].TypeDetail.Unknown = 1; + } + } + DmiBufferPtr->T17[Socket][Channel][Dimm].Speed = (MemInfo + DimmIndex)->Speed; + + DmiBufferPtr->T17[Socket][Channel][Dimm].ManufacturerIdCode = (MemInfo + DimmIndex)->ManufacturerIdCode; + + IntToString (DmiBufferPtr->T17[Socket][Channel][Dimm].SerialNumber, (MemInfo + DimmIndex)->SerialNumber, (sizeof DmiBufferPtr->T17[Socket][Channel][Dimm].SerialNumber - 1) / 2); + + LibAmdMemCopy (&DmiBufferPtr->T17[Socket][Channel][Dimm].PartNumber, &(MemInfo + DimmIndex)->PartNumber, sizeof (DmiBufferPtr->T17[Socket][Channel][Dimm].PartNumber), StdHeader); + DmiBufferPtr->T17[Socket][Channel][Dimm].PartNumber[18] = 0; + + DmiBufferPtr->T17[Socket][Channel][Dimm].Attributes = (MemInfo + DimmIndex)->Attributes; + DmiBufferPtr->T17[Socket][Channel][Dimm].ExtSize = (MemInfo + DimmIndex)->ExtSize; + DmiBufferPtr->T17[Socket][Channel][Dimm].ConfigSpeed = (MemInfo + DimmIndex)->ConfigSpeed; + + if ((MemInfo + DimmIndex)->MemorySize != 0) { + //TYPE 20 + DmiBufferPtr->T20[Socket][Channel][Dimm].StartingAddr = (MemInfo + DimmIndex)->StartingAddr; + DmiBufferPtr->T20[Socket][Channel][Dimm].EndingAddr = (MemInfo + DimmIndex)->EndingAddr; + DmiBufferPtr->T20[Socket][Channel][Dimm].PartitionRowPosition = 0xFF; + DmiBufferPtr->T20[Socket][Channel][Dimm].InterleavePosition = 0xFF; + DmiBufferPtr->T20[Socket][Channel][Dimm].InterleavedDataDepth = 0xFF; + DmiBufferPtr->T20[Socket][Channel][Dimm].ExtStartingAddr = (MemInfo + DimmIndex)->ExtStartingAddr; + DmiBufferPtr->T20[Socket][Channel][Dimm].ExtEndingAddr = (MemInfo + DimmIndex)->ExtEndingAddr; + } + } + + // TYPE 19 + DmiBufferPtr->T19.StartingAddr = 0; + DmiBufferPtr->T19.ExtStartingAddr = 0; + DmiBufferPtr->T19.ExtEndingAddr = 0; + + // If Ending Address >= 0xFFFFFFFF, update Starting Address (offset 04h) & Ending Address (offset 08h) to 0xFFFFFFFF, + // and use the Extended Starting Address (offset 0Fh) & Extended Ending Address (offset 17h) instead. + LibAmdMsrRead (TOP_MEM2, &LocalMsrRegister, StdHeader); + if (LocalMsrRegister == 0) { + LibAmdMsrRead (TOP_MEM, &LocalMsrRegister, StdHeader); + DmiBufferPtr->T19.EndingAddr = (UINT32) (LocalMsrRegister >> 10); + } else { + if ((LocalMsrRegister >> 10) >= ((UINT64) 0xFFFFFFFF)) { + DmiBufferPtr->T19.StartingAddr = 0xFFFFFFFFUL; + DmiBufferPtr->T19.EndingAddr = 0xFFFFFFFFUL; + DmiBufferPtr->T19.ExtEndingAddr = LocalMsrRegister; + } else { + DmiBufferPtr->T19.EndingAddr = (UINT32) (LocalMsrRegister >> 10); + } + } + + DmiBufferPtr->T19.PartitionWidth = 0xFF; + } + return (Flag); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * GetType4Type7Info + * + * Description: + * This routine should be run on core 0 of every socket. It creates DMI type 4 and type 7 tables. + * + * Parameters: + * @param[in] ApExeParams Handle to config for library and services. + * + * @retval AGESA_STATUS + * + * Processing: + * + */ +AGESA_STATUS +GetType4Type7Info ( + IN AP_EXE_PARAMS *ApExeParams + ) +{ + UINT8 ByteIndexInUint64; + UINT16 Index; + UINT32 SocketNum; + UINT32 IgnoredModule; + UINT32 IgnoredCore; + UINT64 MsrData; + DMI_INFO *DmiBufferPtr; + AGESA_STATUS IgnoredSts; + AGESA_STATUS Flag; + BOOLEAN FamilyNotFound; + CPUID_DATA CpuId; + CPU_TYPE_INFO CpuInfo; + PROC_FAMILY_TABLE *ProcData; + CPU_LOGICAL_ID LogicalID; + + Flag = TRUE; + DmiBufferPtr = (DMI_INFO *) ApExeParams->RelatedDataBlock; + GetLogicalIdOfCurrentCore (&LogicalID, &ApExeParams->StdHeader); + + ProcData = NULL; + FamilyNotFound = TRUE; + for (Index = 0; Index < OptionDmiConfiguration.NumEntries; Index++) { + ProcData = (PROC_FAMILY_TABLE *) ((*OptionDmiConfiguration.FamilyList)[Index]); + if ((ProcData->ProcessorFamily & LogicalID.Family) != 0) { + FamilyNotFound = FALSE; + break; + } + } + + if (FamilyNotFound) { + return AGESA_ERROR; + } + + ProcData->DmiGetCpuInfo (&CpuInfo, &ApExeParams->StdHeader); + + // ------------------------------ + // T Y P E 4 + // ------------------------------ + + IdentifyCore (&ApExeParams->StdHeader, &SocketNum, &IgnoredModule, &IgnoredCore, &IgnoredSts); + + // Type 4 Offset 0x05, Processor Type + DmiBufferPtr->T4[SocketNum].T4ProcType = CENTRAL_PROCESSOR; + + // Type 4 Offset 0x06, Processor Family + ProcData->DmiGetT4ProcFamily (&DmiBufferPtr->T4[SocketNum].T4ProcFamily, ProcData, &CpuInfo, &ApExeParams->StdHeader); + + if (DmiBufferPtr->T4[SocketNum].T4ProcFamily == P_UPGRADE_UNKNOWN) { + Flag = AGESA_ERROR; + } + + // Type4 Offset 0x08, Processor ID + LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuId, &ApExeParams->StdHeader); + DmiBufferPtr->T4[SocketNum].T4ProcId.ProcIdLsd = CpuId.EAX_Reg; + DmiBufferPtr->T4[SocketNum].T4ProcId.ProcIdMsd = CpuId.EDX_Reg; + + // Type4 Offset 0x11, Voltage + DmiBufferPtr->T4[SocketNum].T4Voltage = ProcData->DmiGetVoltage (&ApExeParams->StdHeader); + + // Type4 Offset 0x12, External Clock + DmiBufferPtr->T4[SocketNum].T4ExternalClock = ProcData->DmiGetExtClock (&ApExeParams->StdHeader); + + // Type4 Offset 0x14, Max Speed + DmiBufferPtr->T4[SocketNum].T4MaxSpeed = ProcData->DmiGetMaxSpeed (&ApExeParams->StdHeader); + + // Type4 Offset 0x16, Current Speed + DmiBufferPtr->T4[SocketNum].T4CurrentSpeed = DmiBufferPtr->T4[SocketNum].T4MaxSpeed; + + // Type4 Offset 0x18, Status + DmiBufferPtr->T4[SocketNum].T4Status = SOCKET_POPULATED | CPU_STATUS_ENABLED; + + // Type4 Offset 0x19, Processor Upgrade + DmiBufferPtr->T4[SocketNum].T4ProcUpgrade = CpuInfo.ProcUpgrade; + + // Type4 Offset 0x23, 0x24 and 0x25, Core Count, Core Enabled and Thread Count + DmiBufferPtr->T4[SocketNum].T4CoreCount = CpuInfo.TotalCoreNumber + 1; + DmiBufferPtr->T4[SocketNum].T4CoreEnabled = CpuInfo.EnabledCoreNumber + 1; + DmiBufferPtr->T4[SocketNum].T4ThreadCount = CpuInfo.EnabledCoreNumber + 1; + + // Type4 Offset 0x26, Processor Characteristics + DmiBufferPtr->T4[SocketNum].T4ProcCharacteristics = P_CHARACTERISTICS; + + // Type4 Offset 0x28, Processor Family 2 + DmiBufferPtr->T4[SocketNum].T4ProcFamily2 = DmiBufferPtr->T4[SocketNum].T4ProcFamily; + + // Type4 ProcVersion + for (Index = 0; Index <= 5; Index++) { + LibAmdMsrRead ((MSR_CPUID_NAME_STRING0 + Index), &MsrData, &ApExeParams->StdHeader); + for (ByteIndexInUint64 = 0; ByteIndexInUint64 <= 7; ByteIndexInUint64++) { + DmiBufferPtr->T4[SocketNum].T4ProcVersion[Index * 8 + ByteIndexInUint64] = (UINT8) (MsrData >> (8 * ByteIndexInUint64)); + } + } + + // Type4 Manufacturer + ASSERT (PROC_MANU_LENGTH >= sizeof (str_ProcManufacturer)); + LibAmdMemCopy (DmiBufferPtr->T4[SocketNum].T4ProcManufacturer, str_ProcManufacturer, sizeof (str_ProcManufacturer), &ApExeParams->StdHeader); + + //------------------------------ + // T Y P E 7 + //------------------------------ + + // Type7 Offset 0x05, Cache Configuration + DmiBufferPtr->T7L1[SocketNum].T7CacheCfg = CACHE_CFG_L1; + DmiBufferPtr->T7L2[SocketNum].T7CacheCfg = CACHE_CFG_L2; + DmiBufferPtr->T7L3[SocketNum].T7CacheCfg = CACHE_CFG_L3; + + // Type7 Offset 0x07 and 09, Maximum Cache Size and Installed Size + + // Maximum L1 cache size + DmiBufferPtr->T7L1[SocketNum].T7MaxCacheSize = AdjustGranularity (&CpuInfo.CacheInfo.L1CacheSize); + + // Installed L1 cache size + DmiBufferPtr->T7L1[SocketNum].T7InstallSize = DmiBufferPtr->T7L1[SocketNum].T7MaxCacheSize; + + // Maximum L2 cache size + DmiBufferPtr->T7L2[SocketNum].T7MaxCacheSize = AdjustGranularity (&CpuInfo.CacheInfo.L2CacheSize); + + // Installed L2 cache size + DmiBufferPtr->T7L2[SocketNum].T7InstallSize = DmiBufferPtr->T7L2[SocketNum].T7MaxCacheSize; + + // Maximum L3 cache size + DmiBufferPtr->T7L3[SocketNum].T7MaxCacheSize = AdjustGranularity (&CpuInfo.CacheInfo.L3CacheSize); + + // Installed L3 cache size + DmiBufferPtr->T7L3[SocketNum].T7InstallSize = DmiBufferPtr->T7L3[SocketNum].T7MaxCacheSize; + + // Type7 Offset 0x0B and 0D, Supported SRAM Type and Current SRAM Type + DmiBufferPtr->T7L1[SocketNum].T7SupportedSramType = SRAM_TYPE; + DmiBufferPtr->T7L1[SocketNum].T7CurrentSramType = SRAM_TYPE; + DmiBufferPtr->T7L2[SocketNum].T7SupportedSramType = SRAM_TYPE; + DmiBufferPtr->T7L2[SocketNum].T7CurrentSramType = SRAM_TYPE; + DmiBufferPtr->T7L3[SocketNum].T7SupportedSramType = SRAM_TYPE; + DmiBufferPtr->T7L3[SocketNum].T7CurrentSramType = SRAM_TYPE; + + // Type7 Offset 0x0F, Cache Speed + DmiBufferPtr->T7L1[SocketNum].T7CacheSpeed = 1; + DmiBufferPtr->T7L2[SocketNum].T7CacheSpeed = 1; + DmiBufferPtr->T7L3[SocketNum].T7CacheSpeed = 1; + + // Type7 Offset 0x10, Error Correction Type + DmiBufferPtr->T7L1[SocketNum].T7ErrorCorrectionType = ERR_CORRECT_TYPE; + DmiBufferPtr->T7L2[SocketNum].T7ErrorCorrectionType = ERR_CORRECT_TYPE; + DmiBufferPtr->T7L3[SocketNum].T7ErrorCorrectionType = ERR_CORRECT_TYPE; + + // Type7 Offset 0x11, System Cache Type + DmiBufferPtr->T7L1[SocketNum].T7SystemCacheType = CACHE_TYPE; + DmiBufferPtr->T7L2[SocketNum].T7SystemCacheType = CACHE_TYPE; + DmiBufferPtr->T7L3[SocketNum].T7SystemCacheType = CACHE_TYPE; + + // Type7 Offset 0x12, Associativity + DmiBufferPtr->T7L1[SocketNum].T7Associativity = CpuInfo.CacheInfo.L1CacheAssoc; + DmiBufferPtr->T7L2[SocketNum].T7Associativity = CpuInfo.CacheInfo.L2CacheAssoc; + DmiBufferPtr->T7L3[SocketNum].T7Associativity = CpuInfo.CacheInfo.L3CacheAssoc; + + return (Flag); +} + +/* -----------------------------------------------------------------------------*/ +/** + * DmiGetT4ProcFamilyFromBrandId + * + * Description: + * This is the common routine for getting Type 4 processor family information from brand ID + * + * Parameters: + * @param[in, out] *T4ProcFamily Pointer to type 4 processor family information + * @param[in] *CpuDmiProcFamilyTable Pointer to DMI family special service + * @param[in] *CpuInfo Pointer to CPU_TYPE_INFO struct + * @param[in, out] *StdHeader Standard Head Pointer + * + * @retval AGESA_STATUS + * + */ +VOID +DmiGetT4ProcFamilyFromBrandId ( + IN OUT UINT8 *T4ProcFamily, + IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable, + IN CPU_TYPE_INFO *CpuInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT16 Index; + *T4ProcFamily = P_UPGRADE_UNKNOWN; + if (CpuInfo->BrandId.Model != P_ENGINEERING_SAMPLE) { + for (Index = 0; Index < CpuDmiProcFamilyTable->LenBrandList; Index++) { + if ((CpuDmiProcFamilyTable->DmiBrandList[Index].PackageType == 'x' || CpuDmiProcFamilyTable->DmiBrandList[Index].PackageType == CpuInfo->PackageType) && + (CpuDmiProcFamilyTable->DmiBrandList[Index].PgOfBrandId == 'x' || CpuDmiProcFamilyTable->DmiBrandList[Index].PgOfBrandId == CpuInfo->BrandId.Pg) && + (CpuDmiProcFamilyTable->DmiBrandList[Index].NumberOfCores == 'x' || CpuDmiProcFamilyTable->DmiBrandList[Index].NumberOfCores == CpuInfo->TotalCoreNumber) && + (CpuDmiProcFamilyTable->DmiBrandList[Index].String1ofBrandId == 'x' || CpuDmiProcFamilyTable->DmiBrandList[Index].String1ofBrandId == CpuInfo->BrandId.String1)) { + *T4ProcFamily = CpuDmiProcFamilyTable->DmiBrandList[Index].ValueSetToDmiTable; + break; + } + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * GetNameString + * + * Description: + * Get name string from MSR_C001_00[35:30] + * + * Parameters: + * @param[in, out] *String Pointer to name string + * @param[in, out] *StdHeader + * + */ +VOID +GetNameString ( + IN OUT CHAR8 *String, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + UINT8 StringIndex; + UINT8 MsrIndex; + UINT64 MsrData; + + StringIndex = 0; + for (MsrIndex = 0; MsrIndex <= 5; MsrIndex++) { + LibAmdMsrRead ((MSR_CPUID_NAME_STRING0 + MsrIndex), &MsrData, StdHeader); + for (i = 0; i < 8; i++) { + String[StringIndex] = (CHAR8) (MsrData >> (8 * i)); + StringIndex++; + } + } + String[StringIndex] = '\0'; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * IsSourceStrContainTargetStr + * + * Description: + * check if source string contains target string. + * + * Parameters: + * @param[in, out] *SourceStr Pointer to source CHAR array + * @param[in, out] *TargetStr Pointer to target CHAR array + * @param[in, out] *StdHeader + * + * @retval TRUE Target string is contained in the source string + * @retval FALSE Target string is not contained in the source string + */ +BOOLEAN +IsSourceStrContainTargetStr ( + IN OUT CHAR8 *SourceStr, + IN OUT CONST CHAR8 *TargetStr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + BOOLEAN IsContained; + UINT32 SourceStrIndex; + UINT32 TargetStrIndex; + CHAR8 TargetChar; + + IsContained = FALSE; + if ((TargetStr != NULL) && (SourceStr != NULL)) { + for (SourceStrIndex = 0; SourceStr[SourceStrIndex] != '\0'; SourceStrIndex++) { + // Compare TrgString with SrcString from frist charactor to the '\0' + for (TargetStrIndex = 0; TargetStr[TargetStrIndex] != '\0'; TargetStrIndex++) { + if (TargetStr[TargetStrIndex] != SourceStr[SourceStrIndex + TargetStrIndex]) { + // if it's not match, try to check the upcase/lowcase + TargetChar = 0; + if (TargetStr[TargetStrIndex] >= 'a' && TargetStr[TargetStrIndex] <= 'z') { + TargetChar = TargetStr[TargetStrIndex] - ('a' - 'A'); + } else if (TargetStr[TargetStrIndex] >= 'A' && TargetStr[TargetStrIndex] <= 'Z') { + TargetChar = TargetStr[TargetStrIndex] + ('a' - 'A'); + } + // compare again + if (TargetChar != SourceStr[SourceStrIndex + TargetStrIndex]) { + break; + } + } + } + + if ((TargetStr[TargetStrIndex] == '\0') && (TargetStrIndex != 0)) { + IsContained = TRUE; + break; + } + } + } + return IsContained; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * AdjustGranularity + * + * Description: + * If cache size is greater than or equal to 32M, then set granularity + * to 64K. otherwise, set granularity to 1K + * + * Parameters: + * @param[in] *CacheSizePtr + * + * @retval CacheSize + * + * Processing: + * + */ +UINT16 +STATIC +AdjustGranularity ( + IN UINT32 *CacheSizePtr + ) +{ + UINT16 CacheSize; + + if (*CacheSizePtr >= 0x8000) { + CacheSize = (UINT16) (*CacheSizePtr / 64); + CacheSize |= 0x8000; + } else { + CacheSize = (UINT16) *CacheSizePtr; + } + + return (CacheSize); +} + +/* -----------------------------------------------------------------------------*/ +/** + * ReleaseDmiBufferStub + * + * Description: + * This is the default routine for use when the DMI option is NOT requested. + * + * Parameters: + * @param[in, out] *StdHeader + * + * @retval AGESA_STATUS + * + */ +AGESA_STATUS +ReleaseDmiBufferStub ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + return AGESA_UNSUPPORTED; +} + +/* -----------------------------------------------------------------------------*/ +/** + * ReleaseDmiBuffer + * + * Description: + * Deallocate DMI buffer + * + * Parameters: + * @param[in, out] *StdHeader + * + * @retval AGESA_STATUS + * + */ +AGESA_STATUS +ReleaseDmiBuffer ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + HeapDeallocateBuffer ((UINT32) AMD_DMI_MEM_DEV_INFO_HANDLE, StdHeader); + + return AGESA_SUCCESS; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * IntToString + * + * Description: + * Translate UINT array to CHAR array. + * + * Parameters: + * @param[in, out] *String Pointer to CHAR array + * @param[in] *Integer Pointer to UINT array + * @param[in] SizeInByte The size of UINT array + * + * Processing: + * + */ +VOID +STATIC +IntToString ( + IN OUT CHAR8 *String, + IN UINT8 *Integer, + IN UINT8 SizeInByte + ) +{ + UINT8 Index; + + for (Index = 0; Index < SizeInByte; Index++) { + *(String + Index * 2) = (*(Integer + Index) >> 4) & 0x0F; + *(String + Index * 2 + 1) = *(Integer + Index) & 0x0F; + } + for (Index = 0; Index < (SizeInByte * 2); Index++) { + if (*(String + Index) >= 0x0A) { + *(String + Index) += 0x37; + } else { + *(String + Index) += 0x30; + } + } + *(String + SizeInByte * 2) = 0x0; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c new file mode 100644 index 0000000..ffb33ab --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c @@ -0,0 +1,292 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Feature Leveling Function. + * + * Contains code to Level the Feature in a multi-socket system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + *---------------------------------------------------------------------------- + */ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuRegisters.h" +#include "GeneralServices.h" +#include "cpuServices.h" +#include "cpuPostInit.h" +#include "cpuApicUtilities.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FEATURE_CPUFEATURELEVELING_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +VOID +STATIC +SaveFeatures ( + IN OUT VOID *cpuFeatureListPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +WriteFeatures ( + IN OUT VOID *cpuFeatureListPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +GetGlobalCpuFeatureListAddress ( + OUT UINT64 **Address, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * P U B L I C F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * FeatureLeveling + * + * CPU feature leveling. Set least common features set of all CPUs + * + * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. + * + */ +VOID +FeatureLeveling ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 BscSocket; + UINT32 Ignored; + UINT32 BscCoreNum; + UINT32 Socket; + UINT32 Core; + UINT32 NumberOfSockets; + UINT32 NumberOfCores; + BOOLEAN *FirstTime; + BOOLEAN *NeedLeveling; + AGESA_STATUS IgnoredSts; + CPU_FEATURES_LIST *globalCpuFeatureList; + AP_TASK TaskPtr; + + ASSERT (IsBsp (StdHeader, &IgnoredSts)); + + GetGlobalCpuFeatureListAddress ((UINT64 **) &globalCpuFeatureList, StdHeader); + FirstTime = (BOOLEAN *) ((UINT8 *) globalCpuFeatureList + sizeof (CPU_FEATURES_LIST)); + NeedLeveling = (BOOLEAN *) ((UINT8 *) globalCpuFeatureList + sizeof (CPU_FEATURES_LIST) + sizeof (BOOLEAN)); + + *FirstTime = TRUE; + *NeedLeveling = FALSE; + + LibAmdMemFill (globalCpuFeatureList, 0xFF, sizeof (CPU_FEATURES_LIST), StdHeader); + IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); + NumberOfSockets = GetPlatformNumberOfSockets (); + + TaskPtr.FuncAddress.PfApTaskI = SaveFeatures; + TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (CPU_FEATURES_LIST); + TaskPtr.ExeFlags = WAIT_FOR_CORE; + TaskPtr.DataTransfer.DataPtr = globalCpuFeatureList; + TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY; + + for (Socket = 0; Socket < NumberOfSockets; Socket++) { + if (IsProcessorPresent (Socket, StdHeader)) { + if (Socket != BscSocket) { + ApUtilRunCodeOnSocketCore ((UINT8)Socket, 0, &TaskPtr, StdHeader); + } + } + } + ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, NULL); + + if (*NeedLeveling) { + TaskPtr.FuncAddress.PfApTaskI = WriteFeatures; + for (Socket = 0; Socket < NumberOfSockets; Socket++) { + if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { + for (Core = 0; Core < NumberOfCores; Core++) { + if ((Socket != BscSocket) || (Core != BscCoreNum)) { + ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, &TaskPtr, StdHeader); + } + } + } + } + ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, NULL); + } +} + +/*---------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * SaveFeatures + * + * save least common features set of all CPUs + * + * @param[in,out] cpuFeatureListPtr - Pointer to CPU Feature List. + * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. + * + */ +VOID +STATIC +SaveFeatures ( + IN OUT VOID *cpuFeatureListPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + FamilySpecificServices = NULL; + + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->SaveFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * WriteFeatures + * + * Write out least common features set of all CPUs + * + * @param[in,out] cpuFeatureListPtr - Pointer to CPU Feature List. + * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. + * + */ +VOID +STATIC +WriteFeatures ( + IN OUT VOID *cpuFeatureListPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + FamilySpecificServices = NULL; + + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->WriteFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * + * GetGlobalCpuFeatureListAddress + * + * Determines the address in system DRAM that should be used for CPU feature leveling. + * + * @param[out] Address Address to utilize + * @param[in] StdHeader Config handle for library and services + * + * + */ +VOID +STATIC +GetGlobalCpuFeatureListAddress ( + OUT UINT64 **Address, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 AddressValue; + + AddressValue = GLOBAL_CPU_FEATURE_LIST_TEMP_ADDR; + + *Address = (UINT64 *)(AddressValue); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.c new file mode 100644 index 0000000..1aee1c8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.c @@ -0,0 +1,225 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Implement general feature dispatcher. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "GeneralServices.h" +#include "cpuFeatures.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) +#define FILECODE PROC_CPU_FEATURE_CPUFEATURES_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S - External General Services API + *---------------------------------------------------------------------------------------- + */ +extern CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[]; + +/** + * Determines if a specific feature is or will be enabled. + * + * This code traverses the feature list until a match is + * found, then invokes the 'IsEnabled' function of the + * feature. + * + * @param[in] Feature Indicates the desired feature. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Standard AMD configuration parameters. + * + * @retval TRUE Feature is or will be enabled + * @retval FALSE Feature is not enabled + */ +BOOLEAN +IsFeatureEnabled ( + IN DISPATCHABLE_CPU_FEATURES Feature, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINTN i; + + ASSERT (Feature < MaxCpuFeature); + + for (i = 0; SupportedCpuFeatureList[i] != NULL; i++) { + if (SupportedCpuFeatureList[i]->Feature == Feature) { + return (SupportedCpuFeatureList[i]->IsEnabled (PlatformConfig, StdHeader)); + } + } + return FALSE; +} + +/** + * Dispatches all features needing to perform some initialization at + * this time point. + * + * This routine searches the feature table for features needing to + * run at this time point, and invokes them. + * + * @param[in] EntryPoint Timepoint designator + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Standard AMD configuration parameters. + * + * @return The most severe status of any called service. + */ +AGESA_STATUS +DispatchCpuFeatures ( + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINTN i; + AGESA_STATUS AgesaStatus; + AGESA_STATUS CalledStatus; + AGESA_STATUS IgnoredStatus; + + AgesaStatus = AGESA_SUCCESS; + + if (IsBsp (StdHeader, &IgnoredStatus)) { + for (i = 0; SupportedCpuFeatureList[i] != NULL; i++) { + if ((SupportedCpuFeatureList[i]->EntryPoint & EntryPoint) != 0) { + IDS_SKIP_HOOK (IDS_CPU_FEAT, (CPU_FEATURE_DESCRIPTOR *) SupportedCpuFeatureList[i], StdHeader) { + if (SupportedCpuFeatureList[i]->IsEnabled (PlatformConfig, StdHeader)) { + CalledStatus = SupportedCpuFeatureList[i]->InitializeFeature (EntryPoint, PlatformConfig, StdHeader); + if (CalledStatus > AgesaStatus) { + AgesaStatus = CalledStatus; + } + } + } + } + } + } + return AgesaStatus; +} + +/** + * This routine checks whether any non-coherent links in the system + * runs in HT1 mode; used to determine whether certain features + * should be disabled when this routine returns TRUE. + * + * @param[in] StdHeader Standard AMD configuration parameters. + * + * @retval TRUE One of the non-coherent links in the + * system runs in HT1 mode + * @retval FALSE None of the non-coherent links in the + * system is running in HT1 mode + */ +BOOLEAN +IsNonCoherentHt1 ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINTN Link; + UINT32 Socket; + UINT32 Module; + PCI_ADDR PciAddress; + AGESA_STATUS AgesaStatus; + HT_HOST_FEATS HtHostFeats; + CPU_SPECIFIC_SERVICES *CpuServices; + + for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { + if (IsProcessorPresent (Socket, StdHeader)) { + GetCpuServicesOfSocket (Socket, (CONST CPU_SPECIFIC_SERVICES **)&CpuServices, StdHeader); + for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { + if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) { + HtHostFeats.HtHostValue = 0; + Link = 0; + while (CpuServices->GetNextHtLinkFeatures (CpuServices, &Link, &PciAddress, &HtHostFeats, StdHeader)) { + // Return TRUE and exit routine once we find a non-coherent link in HT1 + if ((HtHostFeats.HtHostFeatures.NonCoherent == 1) && (HtHostFeats.HtHostFeatures.Ht1 == 1)) { + return TRUE; + } + } + } + } + } + } + + return FALSE; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h new file mode 100644 index 0000000..4c18809 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h @@ -0,0 +1,297 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Generic CPU feature dispatcher and related services. + * + * Provides a feature processing engine to handle feature in a + * more generic way. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Common + * @e $Revision: 63692 $ @e $Date: 2012-01-03 22:13:28 -0600 (Tue, 03 Jan 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_FEATURES_H_ +#define _CPU_FEATURES_H_ + +/** + * @page cpufeatimpl CPU Generic Feature Implementation Guide + * + * The CPU generic feature dispatcher provides services which can be used to implement a + * wide range of features in a manner that isolates calling code from knowledge about which + * families or features are supported in the current build. + * + * @par Determine if a New Feature is a Suitable Candidate + * + * A feature must meet the following requirements: + * <ul> + * <li> Any core in the system must be able to determine if the feature should be enabled or not. + * + * <ul> + * <li> MSRs cannot be read in multisocket systems in the 'IsEnabled' function. + * + * <li> Cores cannot be launched in the 'IsEnabled' function. + * </ul> + * </ul> + * + * @par Determine the Time Point at which the Feature Should be Enabled + * + * Factors to consider in making this determination: + * + * <ul> + * <li> Determine if there are any dependencies on other settings that require strict ordering. + * + * <li> Consider the state of the APs that you will need. + * + * <li> Remember that features enabled during AmdInitEarly will automatically be restored on S3 resume. + * </ul> + * + * @par Implementing a new feature + * + * Perform the following steps to implement a new feature: + * + * <ul> + * <li> Create a unique equate for your time point, @b if you cannot use an existing time point. + * + * <li> Create a new value in the DISPATCHABLE_CPU_FEATURES enum for your feature. + * + * <li> Add a new 'C' file to the Features folder for your feature. + * + * <ul> + * <li> The 'C' file must implement 2 functions -- 'IsEnabled' and 'Initialize' + * + * <li> The 'C' file must instantiate a CPU_FEATURE_DESCRIPTOR structure. + * </ul> + * + * <li> Add a new 'H' file to the Features folder for your feature. + * + * <ul> + * <li> The 'H' file declares whatever family specific functions required by the feature. + * + * <li> The 'H' file declares a structure containing all family specific functions. For a reference + * example, your feature API should have a set of conventions similar to cpu specific services, + * @ref cpuimplfss. + * </ul> + * + * <li> Create 'C' files in all applicable family folders. + * + * <ul> + * <li> Implement the required family specific functions. + * + * <li> Instantiate a family specific services structure. + * </ul> + * + * <li> Create <feature name>Install.h in the include folder. + * + * <ul> + * <li> Add logic to determine when your feature should be included in the build. + * + * <li> If the feature should be included, define OPTION_<feature name> to the address of your + * CPU_FEATURE_DESCRIPTOR instantiation. If not, define OPTION_<feature name> to be blank. + * + * <li> Create a family translation table pointing to all applicable instantiations of + * family specific function structures. + * </ul> + * + * <li> Modify OptionCpuFeaturesInstall.h in the include folder. + * + * <ul> + * <li> Include <feature name>Install.h. + * + * <li> Add OPTION_<feature name> to the SupportedCpuFeatureList array. + * </ul> + * + * <li> If a new time point was created, add a call to DispatchCpuFeatures at the desired location, + * passing your new time point equate. + * </ul> + * + */ + + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *---------------------------------------------------------------------------------------- + */ +#define CPU_FEAT_BEFORE_PM_INIT (0x0000000000000001ull) +#define CPU_FEAT_AFTER_PM_INIT (0x0000000000000002ull) +#define CPU_FEAT_AFTER_POST_MTRR_SYNC (0x0000000000000004ull) +#define CPU_FEAT_INIT_MID_END (0x0000000000000008ull) +#define CPU_FEAT_INIT_LATE_END (0x0000000000000010ull) +#define CPU_FEAT_S3_LATE_RESTORE_END (0x0000000000000020ull) +#define CPU_FEAT_AFTER_RESUME_MTRR_SYNC (0x0000000000000040ull) +#define CPU_FEAT_AFTER_COHERENT_DISCOVERY (0x0000000000000080ull) +#define CPU_FEAT_BEFORE_RELINQUISH_AP (0x0000000000000100ull) +/** + * Enumerated list of supported features. + */ +typedef enum { + HardwareC1e, ///< Hardware C1e + L3Features, ///< L3 dependent features + MsgBasedC1e, ///< Message-based C1e + SoftwareC1e, ///< Software C1e + CoreLeveling, ///< Core Leveling + C6Cstate, ///< C6 C-state + IoCstate, ///< IO C-state + CacheFlushOnHalt, ///< Cache Flush On Halt + PreserveAroundMailbox, ///< Save-Restore the registers used for AP mailbox, to preserve their normal function. + CoreBoost, ///< Core Performance Boost (CPB) + LowPwrPstate, ///< 500 MHz Low Power P-state + PstateHpcMode, ///< High performance computing mode + CpuApm, ///< Application Power Management + CpuPsi, ///< Power Status Indicator + CpuHtc, ///< Hardware Thermal Control + MaxCpuFeature ///< Not a valid value, used for verifying input +} DISPATCHABLE_CPU_FEATURES; + +/*---------------------------------------------------------------------------------------*/ +/** + * Feature specific call to check if it is supported by the system. + * + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE Feature is supported. + * @retval FALSE Feature is not supported. + * + */ +typedef BOOLEAN F_CPU_FEATURE_IS_ENABLED ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_CPU_FEATURE_IS_ENABLED *PF_CPU_FEATURE_IS_ENABLED; + +/*---------------------------------------------------------------------------------------*/ +/** + * The feature's main entry point for enablement. + * + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @return Family specific error value. + * + */ +typedef AGESA_STATUS F_CPU_FEATURE_INITIALIZE ( + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_CPU_FEATURE_INITIALIZE *PF_CPU_FEATURE_INITIALIZE; + + +/** + * Generic feature descriptor + */ +typedef struct { + DISPATCHABLE_CPU_FEATURES Feature; ///< Enumerated feature ID + UINT64 EntryPoint; ///< Timepoint designator + PF_CPU_FEATURE_IS_ENABLED IsEnabled; ///< Pointer to the function that checks if the feature is supported + PF_CPU_FEATURE_INITIALIZE InitializeFeature; ///< Pointer to the function that enables the feature +} CPU_FEATURE_DESCRIPTOR; + +/** + * Table descriptor for the installed features. + */ +typedef struct { + UINT8 NumberOfFeats; ///< Number of valid entries in the table. + CPU_FEATURE_DESCRIPTOR *FeatureList; ///< Pointer to the first element in the array. +} CPU_FEATURE_TABLE; + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ + +BOOLEAN +IsFeatureEnabled ( + IN DISPATCHABLE_CPU_FEATURES Feature, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +DispatchCpuFeatures ( + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +IsNonCoherentHt1 ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif // _CPU_FEATURES_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHtc.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHtc.c new file mode 100644 index 0000000..6ad6cbd --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHtc.c @@ -0,0 +1,228 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA CPU Hardware Thermal Control (HTC) feature support code. + * + * Contains code that declares the AGESA CPU HTC related APIs + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Feature + * @e $Revision: 63692 $ @e $Date: 2012-01-03 22:13:28 -0600 (Tue, 03 Jan 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "cpuApicUtilities.h" +#include "cpuFeatures.h" +#include "cpuHtc.h" +#include "OptionMultiSocket.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FEATURE_CPUHTC_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +UINT32 +STATIC +EnableHtcOnSocket ( + IN VOID *EntryPoint, + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern CPU_FAMILY_SUPPORT_TABLE HtcFamilyServiceTable; +extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; + +/*---------------------------------------------------------------------------------------*/ +/** + * Should Hardware Thermal Control (HTC) be enabled + * + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE HTC is supported. + * @retval FALSE HTC cannot be enabled. + * + */ +BOOLEAN +STATIC +IsHtcFeatureEnabled ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Socket; + BOOLEAN IsEnabled; + HTC_FAMILY_SERVICES *HtcFamilyServices; + + IsEnabled = TRUE; + + for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { + if (IsProcessorPresent (Socket, StdHeader)) { + GetFeatureServicesOfSocket (&HtcFamilyServiceTable, Socket, (CONST VOID **)&HtcFamilyServices, StdHeader); + if ((HtcFamilyServices == NULL) || (!HtcFamilyServices->IsHtcSupported (HtcFamilyServices, Socket, PlatformConfig, StdHeader))) { + IsEnabled = FALSE; + break; + } + } + } + return IsEnabled; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Enable Hardware Thermal Control (HTC) + * + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +STATIC +InitializeHtcFeature ( + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AP_TASK TaskPtr; + AGESA_STATUS AgesaStatus; + AMD_CPU_EARLY_PARAMS CpuEarlyParams; + + IDS_HDT_CONSOLE (CPU_TRACE, " HTC is being initialized\n"); + + CpuEarlyParams.PlatformConfig = *PlatformConfig; + + TaskPtr.FuncAddress.PfApTaskIOC = EnableHtcOnSocket; + TaskPtr.DataTransfer.DataSizeInDwords = 2; + TaskPtr.DataTransfer.DataPtr = &EntryPoint; + TaskPtr.DataTransfer.DataTransferFlags = 0; + TaskPtr.ExeFlags = PASS_EARLY_PARAMS | TASK_HAS_OUTPUT; + AgesaStatus = OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams); + + IDS_HDT_CONSOLE (CPU_TRACE, " HTC is enabled\n"); + + return AgesaStatus; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * AP task to enable HTC + * + * @param[in] EntryPoint Timepoint designator. + * @param[in] StdHeader Config Handle for library, services. + * @param[in] CpuEarlyParams Service parameters. + * + */ +UINT32 +STATIC +EnableHtcOnSocket ( + IN VOID *EntryPoint, + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams + ) +{ + AGESA_STATUS CalledStatus; + HTC_FAMILY_SERVICES *HtcFamilyServices; + + CalledStatus = AGESA_UNSUPPORTED; + GetFeatureServicesOfCurrentCore (&HtcFamilyServiceTable, (CONST VOID **)&HtcFamilyServices, StdHeader); + if (HtcFamilyServices != NULL) { + CalledStatus = HtcFamilyServices->EnableHtcOnSocket (HtcFamilyServices, *((UINT64 *) EntryPoint), &CpuEarlyParams->PlatformConfig, StdHeader); + } + return (UINT32) CalledStatus; +} + +CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHtc = +{ + CpuHtc, + (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC), + IsHtcFeatureEnabled, + InitializeHtcFeature +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHtc.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHtc.h new file mode 100644 index 0000000..e021f28 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHtc.h @@ -0,0 +1,157 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA CPU Hardware Thermal Control (HTC) Functions declarations. + * + * Contains code that declares the AGESA CPU HTC related APIs + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Feature + * @e $Revision: 63692 $ @e $Date: 2012-01-03 22:13:28 -0600 (Tue, 03 Jan 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_HTC_H_ +#define _CPU_HTC_H_ + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ +// Forward declaration needed for multi-structure mutual references +AGESA_FORWARD_DECLARATION (HTC_FAMILY_SERVICES); + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to check if Hardware Thermal Control (HTC) is supported. + * + * @param[in] HtcServices HTC services. + * @param[in] Socket Zero-based socket number. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE HTC is supported. + * @retval FALSE HTC is not supported. + * + */ +typedef BOOLEAN F_HTC_IS_SUPPORTED ( + IN HTC_FAMILY_SERVICES *HtcServices, + IN UINT32 Socket, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_HTC_IS_SUPPORTED *PF_HTC_IS_SUPPORTED; + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to enable HTC. + * + * @param[in] HtcServices HTC services. + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @return Family specific error value. + * + */ +typedef AGESA_STATUS F_HTC_INIT ( + IN HTC_FAMILY_SERVICES *HtcServices, + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_HTC_INIT *PF_HTC_INIT; + +/** + * Provide the interface to the HTC Family Specific Services. + * + * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). + * Each supported Family must provide an implementation for all methods in this interface, even if the + * implementation is a CommonReturn(). + */ +/* typedef */struct _HTC_FAMILY_SERVICES { + UINT16 Revision; ///< Interface version + // Public Methods. + PF_HTC_IS_SUPPORTED IsHtcSupported; ///< Method: Family specific call to check if HTC is supported. + PF_HTC_INIT EnableHtcOnSocket; ///< Method: Family specific call to enable HTC. +} /* HTC_FAMILY_SERVICES */; + + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N S P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ + +#endif // _CPU_HTC_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHwC1e.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHwC1e.c new file mode 100644 index 0000000..e06944f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHwC1e.c @@ -0,0 +1,207 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA CPU HW C1e feature support code. + * + * Contains code that declares the AGESA CPU C1e related APIs + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Feature + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuApicUtilities.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "Topology.h" +#include "cpuFeatures.h" +#include "cpuHwC1e.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FEATURE_CPUHWC1E_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern CPU_FAMILY_SUPPORT_TABLE HwC1eFamilyServiceTable; + +/*---------------------------------------------------------------------------------------*/ +/** + * Should hardware C1e be enabled + * + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE HW C1e is supported. + * @retval FALSE HW C1e cannot be enabled. + * + */ +BOOLEAN +STATIC +IsHwC1eFeatureEnabled ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 C1eData; + BOOLEAN IsEnabled; + AP_MAILBOXES ApMailboxes; + HW_C1E_FAMILY_SERVICES *FamilyServices; + + ASSERT (PlatformConfig->C1eMode < MaxC1eMode); + IsEnabled = FALSE; + C1eData = PlatformConfig->C1ePlatformData; + if ((PlatformConfig->C1eMode == C1eModeHardware) || (PlatformConfig->C1eMode == C1eModeHardwareSoftwareDeprecated) || + (PlatformConfig->C1eMode == C1eModeAuto)) { + // If C1eMode is Auto, C1ePlatformData3 specifies the P_LVL3 I/O port of the platform for HW C1e + if (PlatformConfig->C1eMode == C1eModeAuto) { + C1eData = PlatformConfig->C1ePlatformData3; + } + ASSERT (C1eData < 0x10000); + ASSERT (C1eData != 0); + if ((C1eData != 0) && (C1eData < 0xFFFE)) { + if (!IsNonCoherentHt1 (StdHeader)) { + if (GetNumberOfProcessors (StdHeader) == 1) { + GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader); + if (ApMailboxes.ApMailInfo.Fields.ModuleType == 0) { + GetFeatureServicesOfCurrentCore (&HwC1eFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); + if (FamilyServices != NULL) { + IsEnabled = FamilyServices->IsHwC1eSupported (FamilyServices, StdHeader); + } + } + } + } + } + } + return IsEnabled; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Enable Hardware C1e + * + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @return The most severe status of any family specific service. + * + */ +AGESA_STATUS +STATIC +InitializeHwC1eFeature ( + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS CalledStatus; + AGESA_STATUS AgesaStatus; + HW_C1E_FAMILY_SERVICES *FamilyServices; + + AgesaStatus = AGESA_SUCCESS; + + IDS_HDT_CONSOLE (CPU_TRACE, " HW C1e is enabled\n"); + + if (IsWarmReset (StdHeader)) { + GetFeatureServicesOfCurrentCore (&HwC1eFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); + CalledStatus = FamilyServices->InitializeHwC1e (FamilyServices, EntryPoint, PlatformConfig, StdHeader); + if (CalledStatus > AgesaStatus) { + AgesaStatus = CalledStatus; + } + } + return AgesaStatus; +} + +CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHwC1e = +{ + HardwareC1e, + CPU_FEAT_AFTER_PM_INIT, + IsHwC1eFeatureEnabled, + InitializeHwC1eFeature +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHwC1e.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHwC1e.h new file mode 100644 index 0000000..4888e42 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuHwC1e.h @@ -0,0 +1,152 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA CPU HW C1e Functions declarations. + * + * Contains code that declares the AGESA CPU C1e related APIs + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Feature + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_HW_C1E_H_ +#define _CPU_HW_C1E_H_ + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ +// Forward declaration needed for multi-structure mutual references +AGESA_FORWARD_DECLARATION (HW_C1E_FAMILY_SERVICES); + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to check if hardware C1e is supported. + * + * @param[in] HwC1eServices Hardware C1e services. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE HW C1e is supported. + * @retval FALSE HW C1e is not supported. + * + */ +typedef BOOLEAN F_HW_C1E_IS_SUPPORTED ( + IN HW_C1E_FAMILY_SERVICES *HwC1eServices, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_HW_C1E_IS_SUPPORTED *PF_HW_C1E_IS_SUPPORTED; + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to enable hardware C1e. + * + * @param[in] HwC1eServices Hardware C1e services. + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @return Family specific error value. + * + */ +typedef AGESA_STATUS F_HW_C1E_INIT ( + IN HW_C1E_FAMILY_SERVICES *HwC1eServices, + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_HW_C1E_INIT *PF_HW_C1E_INIT; + +/** + * Provide the interface to the hardware C1e Family Specific Services. + * + * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). + * Each supported Family must provide an implementation for all methods in this interface, even if the + * implementation is a CommonReturn(). + */ +struct _HW_C1E_FAMILY_SERVICES { + UINT16 Revision; ///< Interface version + // Public Methods. + PF_HW_C1E_IS_SUPPORTED IsHwC1eSupported; ///< Method: Family specific call to check if hardware C1e is supported. + PF_HW_C1E_INIT InitializeHwC1e; ///< Method: Family specific call to enable hardware C1e. +}; + + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N S P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ + +#endif // _CPU_HW_C1E_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuIoCstate.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuIoCstate.c new file mode 100644 index 0000000..ea54604 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuIoCstate.c @@ -0,0 +1,234 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA CPU IO Cstate function declarations. + * + * Contains code that declares the AGESA CPU IO Cstate related APIs + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Feature + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "cpuFeatures.h" +#include "cpuIoCstate.h" +#include "cpuServices.h" +#include "cpuFamilyTranslation.h" +#include "cpuApicUtilities.h" +#include "OptionMultiSocket.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FEATURE_CPUIOCSTATE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +STATIC +EnableIoCstateOnSocket ( + IN VOID *EntryPoint, + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams + ); +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable; +extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; + +/*---------------------------------------------------------------------------------------*/ +/** + * Should IO Cstate be enabled + * If all processors support IO Cstate, return TRUE. Otherwise, return FALSE + * + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE IO Cstate is supported. + * @retval FALSE IO Cstate cannot be enabled. + * + */ +BOOLEAN +STATIC +IsIoCstateFeatureSupported ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Socket; + BOOLEAN IsSupported; + IO_CSTATE_FAMILY_SERVICES *IoCstateServices; + + IsSupported = FALSE; + if ((PlatformConfig->CStateIoBaseAddress != 0) && (PlatformConfig->CStateIoBaseAddress <= 0xFFF8)) { + for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { + if (IsProcessorPresent (Socket, StdHeader)) { + GetFeatureServicesOfSocket (&IoCstateFamilyServiceTable, Socket, (CONST VOID **)&IoCstateServices, StdHeader); + if (IoCstateServices != NULL) { + if (IoCstateServices->IsIoCstateSupported (IoCstateServices, Socket, StdHeader)) { + IsSupported = TRUE; + } else { + // Stop checking remaining socket(s) once we find one that does not support IO Cstates + IsSupported = FALSE; + break; + } + } else { + // Exit the for loop if we found a socket that does not have the IO Cstates feature installed + IsSupported = FALSE; + break; + } + } + } + } + return IsSupported; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Enable IO Cstate feature + * + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +STATIC +InitializeIoCstateFeature ( + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AP_TASK TaskPtr; + AMD_CPU_EARLY_PARAMS CpuEarlyParams; + + IDS_HDT_CONSOLE (CPU_TRACE, " IO C-state is enabled\n"); + + CpuEarlyParams.PlatformConfig = *PlatformConfig; + + TaskPtr.FuncAddress.PfApTaskIC = EnableIoCstateOnSocket; + TaskPtr.DataTransfer.DataSizeInDwords = 2; + TaskPtr.DataTransfer.DataPtr = &EntryPoint; + TaskPtr.DataTransfer.DataTransferFlags = 0; + TaskPtr.ExeFlags = PASS_EARLY_PARAMS; + OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams); + + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * 'Local' core 0 task to enable IO Cstate on it's socket. + * + * @param[in] EntryPoint Timepoint designator. + * @param[in] StdHeader Config Handle for library, services. + * @param[in] CpuEarlyParams Service parameters. + * + */ +VOID +STATIC +EnableIoCstateOnSocket ( + IN VOID *EntryPoint, + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams + ) +{ + IO_CSTATE_FAMILY_SERVICES *FamilyServices; + + GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); + FamilyServices->InitializeIoCstate (FamilyServices, + *((UINT64 *) EntryPoint), + &CpuEarlyParams->PlatformConfig, + StdHeader); +} + +CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate = +{ + IoCstate, + (CPU_FEAT_AFTER_PM_INIT), + IsIoCstateFeatureSupported, + InitializeIoCstateFeature +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuIoCstate.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuIoCstate.h new file mode 100644 index 0000000..09ad226 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuIoCstate.h @@ -0,0 +1,310 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA CPU IO Cstate feature support code. + * + * Contains code that declares the AGESA CPU IO Cstate related APIs + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Feature + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_IO_CSTATE_H_ +#define _CPU_IO_CSTATE_H_ + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ +// Forward declaration needed for multi-structure mutual references +AGESA_FORWARD_DECLARATION (IO_CSTATE_FAMILY_SERVICES); + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +// Defines for ACPI C-State Objects +#define CST_NAME__ '_' +#define CST_NAME_C 'C' +#define CST_NAME_S 'S' +#define CST_NAME_T 'T' +#define CST_LENGTH (CST_BODY_SIZE - 1) +#define CST_NUM_OF_ELEMENTS 0x02 +#define CST_COUNT 0x01 +#define CST_PKG_LENGTH (CST_BODY_SIZE - 6) // CST_BODY_SIZE - PkgHeader - Count Buffer +#define CST_PKG_ELEMENTS 0x04 +#define CST_SUBPKG_LENGTH 0x14 +#define CST_SUBPKG_ELEMENTS 0x0A +#define CST_GDR_LENGTH 0x000C +#define CST_C1_TYPE 0x01 +#define CST_C2_TYPE 0x02 + +#define CSD_NAME_D 'D' +#define CSD_COORD_TYPE_HW_ALL 0xFE + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +/* AML code definition */ + +/// CST Header +typedef struct _CST_HEADER_STRUCT { + UINT8 NameOpcode; ///< Name Opcode + UINT8 CstName_a__; ///< String "_" + UINT8 CstName_a_C; ///< String "C" + UINT8 CstName_a_S; ///< String "S" + UINT8 CstName_a_T; ///< String "T" +} CST_HEADER_STRUCT; +#define CST_HEADER_SIZE 5 + +/// CST Body +typedef struct _CST_BODY_STRUCT { + UINT8 PkgOpcode; ///< Package Opcode + UINT8 PkgLength; ///< Package Length + UINT8 PkgElements; ///< Number of Elements + UINT8 BytePrefix; ///< Byte Prefix Opcode + UINT8 Count; ///< Number of Cstate info packages + UINT8 PkgOpcode2; ///< Package Opcode + UINT8 PkgLength2; ///< Package Length + UINT8 PkgElements2; ///< Number of Elements + UINT8 BufferOpcode; ///< Buffer Opcode + UINT8 BufferLength; ///< Buffer Length + UINT8 BufferElements; ///< Number of Elements + UINT8 BufferOpcode2; ///< Buffer Opcode + UINT8 GdrOpcode; ///< Generic Register Descriptor Opcode + UINT16 GdrLength; ///< Descriptor Length + UINT8 AddrSpaceId; ///< Address Space ID + UINT8 RegBitWidth; ///< Register Bit Width + UINT8 RegBitOffset; ///< Register Bit Offset + UINT8 AddressSize; ///< Address Size + UINT64 RegisterAddr; ///< Register Address + UINT16 EndTag; ///< End Tag Descriptor + UINT8 BytePrefix2; ///< Byte Prefix Opcode + UINT8 Type; ///< Type + UINT8 WordPrefix; ///< Word Prefix Opcode + UINT16 Latency; ///< Latency + UINT8 DWordPrefix; ///< Dword Prefix Opcode + UINT32 Power; ///< Power +} CST_BODY_STRUCT; +#define CST_BODY_SIZE 39 + +/// CSD Header +typedef struct _CSD_HEADER_STRUCT { + UINT8 NameOpcode; ///< Name Opcode + UINT8 CsdName_a__; ///< String "_" + UINT8 CsdName_a_C; ///< String "C" + UINT8 CsdName_a_S; ///< String "S" + UINT8 CsdName_a_D; ///< String "D" +} CSD_HEADER_STRUCT; +#define CSD_HEADER_SIZE 5 + +/// CSD Body +typedef struct _CSD_BODY_STRUCT { + UINT8 PkgOpcode; ///< Package Opcode + UINT8 PkgLength; ///< Package Length + UINT8 PkgElements; ///< Number of Elements + UINT8 PkgOpcode2; ///< Package Opcode + UINT8 PkgLength2; ///< Package Length + UINT8 PkgElements2; ///< Number of Elements + UINT8 BytePrefix; ///< Byte Prefix Opcode + UINT8 NumEntries; ///< Number of Entries + UINT8 BytePrefix2; ///< Byte Prefix Opcode + UINT8 Revision; ///< Revision + UINT8 DWordPrefix; ///< DWord Prefix Opcode + UINT32 Domain; ///< Dependency Domain Number + UINT8 DWordPrefix2; ///< DWord Prefix Opcode + UINT32 CoordType; ///< Coordination Type + UINT8 DWordPrefix3; ///< Dword Prefix Opcode + UINT32 NumProcessors; ///< Number of Processors in the Domain + UINT8 DWordPrefix4; ///< Dword Prefix Opcode + UINT32 Index; ///< Index of C-State entry for which dependency applies +} CSD_BODY_STRUCT; +#define CSD_BODY_SIZE 30 + +/// input for create _CST +typedef struct _ACPI_CST_CREATE_INPUT { + IO_CSTATE_FAMILY_SERVICES *IoCstateServices; ///< Family service of IoCstate + UINT8 LocalApicId; ///< Local Apic for create _CST + VOID **PstateAcpiBufferPtr; ///< buffer for fill _CST +} ACPI_CST_CREATE_INPUT ; + +/// input for get _CST +typedef struct _ACPI_CST_GET_INPUT { + IO_CSTATE_FAMILY_SERVICES *IoCstateServices; ///< Family service of IoCstate + PLATFORM_CONFIGURATION *PlatformConfig; ///< platform config + UINT32 *CStateAcpiObjSizePtr; ///< Point to size of _CST +} ACPI_CST_GET_INPUT ; + + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to check if IO Cstate is supported. + * + * @param[in] IoCstateServices IO Cstate services. + * @param[in] Socket Zero-based socket number. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE IO Cstate is supported. + * @retval FALSE IO Cstate is not supported. + * + */ +typedef BOOLEAN F_IO_CSTATE_IS_SUPPORTED ( + IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, + IN UINT32 Socket, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to enable IO Cstate. + * + * @param[in] IoCstateServices IO Cstate services. + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @return Family specific error value. + * + */ +typedef AGESA_STATUS F_IO_CSTATE_INIT ( + IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to return the size of ACPI C-State Objects + * + * @param[in] IoCstateServices IO Cstate services. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data + * @param[in] StdHeader Config Handle for library, services. + * + * @retval Size of ACPI C-State Objects + * + */ +typedef UINT32 F_IO_CSTATE_GET_CST_SIZE ( + IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to create ACPI C-State Objects + * + * @param[in] IoCstateServices IO Cstate services. + * @param[in] LocalApicId Local Apic Id + * @param[in, out] PstateAcpiBufferPtr Pointer to Pstate data buffer + * @param[in] StdHeader Config Handle for library, services. + * + */ +typedef VOID F_IO_CSTATE_CREATE_CST ( + IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, + IN UINT8 LocalApicId, + IN OUT VOID **PstateAcpiBufferPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to check whether CSD object should be created. + * + * @param[in] IoCstateServices IO Cstate services. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE CSD Object should be created. + * @retval FALSE CSD Object should not be created. + * + */ +typedef BOOLEAN F_IO_CSTATE_IS_CSD_GENERATED ( + IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method +typedef F_IO_CSTATE_IS_SUPPORTED *PF_IO_CSTATE_IS_SUPPORTED; +typedef F_IO_CSTATE_INIT *PF_IO_CSTATE_INIT; +typedef F_IO_CSTATE_GET_CST_SIZE *PF_IO_CSTATE_GET_CST_SIZE; +typedef F_IO_CSTATE_CREATE_CST *PF_IO_CSTATE_CREATE_CST; +typedef F_IO_CSTATE_IS_CSD_GENERATED *PF_IO_CSTATE_IS_CSD_GENERATED; + +/** + * Provide the interface to the IO Cstate Family Specific Services. + * + * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). + * Each supported Family must provide an implementation for all methods in this interface, even if the + * implementation is a CommonReturn(). + */ +struct _IO_CSTATE_FAMILY_SERVICES { + UINT16 Revision; ///< Interface version + // Public Methods. + PF_IO_CSTATE_IS_SUPPORTED IsIoCstateSupported; ///< Method: Family specific call to check if IO Cstate is supported. + PF_IO_CSTATE_INIT InitializeIoCstate; ///< Method: Family specific call to enable IO Cstate + PF_IO_CSTATE_GET_CST_SIZE GetAcpiCstObj; ///< Method: Family specific call to return the size of ACPI CST objects. + PF_IO_CSTATE_CREATE_CST CreateAcpiCstObj; ///< Method: Family specific call to create ACPI CST object + PF_IO_CSTATE_IS_CSD_GENERATED IsCsdObjGenerated; ///< Method: Family specific call to check whether CSD Object should be created. +}; + +#endif // _CPU_IO_CSTATE_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuL3Features.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuL3Features.c new file mode 100644 index 0000000..7f680ae --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuL3Features.c @@ -0,0 +1,376 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU L3 Features Initialization functions. + * + * Contains code for initializing L3 features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuLateInit.h" +#include "cpuFamilyTranslation.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "cpuFeatures.h" +#include "cpuL3Features.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_CPU_FEATURE_CPUL3FEATURES_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern CPU_FAMILY_SUPPORT_TABLE L3FeatureFamilyServiceTable; + +/*---------------------------------------------------------------------------------------*/ +/** + * Should L3 features be enabled + * + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE L3 Features are supported + * @retval FALSE L3 Features are not supported + * + */ +BOOLEAN +STATIC +IsL3FeatureEnabled ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + BOOLEAN IsEnabled; + UINT32 Socket; + L3_FEATURE_FAMILY_SERVICES *FamilyServices; + + IsEnabled = FALSE; + if (PlatformConfig->PlatformProfile.UseHtAssist || + PlatformConfig->PlatformProfile.UseAtmMode) { + IsEnabled = TRUE; + for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { + if (IsProcessorPresent (Socket, StdHeader)) { + GetFeatureServicesOfSocket (&L3FeatureFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader); + if ((FamilyServices == NULL) || !FamilyServices->IsL3FeatureSupported (FamilyServices, Socket, StdHeader)) { + IsEnabled = FALSE; + break; + } + } + } + } + return IsEnabled; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Enable L3 dependent features. + * + * L3 features initialization requires the following series of steps. + * 1. Disable L3 and DRAM scrubbers on all nodes + * 2. Wait 40us for outstanding scrub results to complete + * 3. Disable all cache activity in the system + * 4. Issue WBINVD on all active cores + * 5. Initialize Probe Filter, if supported + * 6. Initialize ATM Mode, if supported + * 7. Enable all cache activity in the system + * 8. Restore L3 and DRAM scrubber register values + * + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +STATIC +InitializeL3Feature ( + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 CpuCount; + UINT32 Socket; + BOOLEAN HtAssistEnabled; + BOOLEAN AtmModeEnabled; + AGESA_STATUS AgesaStatus; + AP_MAILBOXES ApMailboxes; + AP_EXE_PARAMS ApParams; + UINT32 Scrubbers[MAX_SOCKETS_SUPPORTED][L3_SCRUBBER_CONTEXT_ARRAY_SIZE]; + L3_FEATURE_FAMILY_SERVICES *FamilyServices[MAX_SOCKETS_SUPPORTED]; + + AgesaStatus = AGESA_SUCCESS; + HtAssistEnabled = TRUE; + AtmModeEnabled = TRUE; + + IDS_HDT_CONSOLE (CPU_TRACE, " Enabling L3 dependent features\n"); + + // There are many family service call outs. Initialize the family service array while + // cache is still enabled. + for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) { + if (IsProcessorPresent (Socket, StdHeader)) { + GetFeatureServicesOfSocket (&L3FeatureFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices[Socket], StdHeader); + } else { + FamilyServices[Socket] = NULL; + } + } + + if (EntryPoint == CPU_FEAT_AFTER_POST_MTRR_SYNC) { + // Check for optimal settings + GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader); + CpuCount = GetNumberOfProcessors (StdHeader); + if (((CpuCount == 1) && (ApMailboxes.ApMailInfo.Fields.ModuleType == 1)) || + ((CpuCount == 2) && (ApMailboxes.ApMailInfo.Fields.ModuleType == 0))) { + for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { + // Only check for non-optimal HT Assist setting is if's supported. + if ((FamilyServices[Socket] != NULL) && + (FamilyServices[Socket]->IsHtAssistSupported (FamilyServices[Socket], PlatformConfig, StdHeader))) { + if (FamilyServices[Socket]->IsNonOptimalConfig (FamilyServices[Socket], Socket, StdHeader)) { + // Non-optimal settings. Log an event. + AgesaStatus = AGESA_WARNING; + PutEventLog (AgesaStatus, CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG, 0, 0, 0, 0, StdHeader); + break; + } + } + } + } + } else { + // Disable the scrubbers. + for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { + if (FamilyServices[Socket] != NULL) { + FamilyServices[Socket]->GetL3ScrubCtrl (FamilyServices[Socket], Socket, &Scrubbers[Socket][0], StdHeader); + + // If any node in the system does not support Probe Filter, disable it on the system + if (!FamilyServices[Socket]->IsHtAssistSupported (FamilyServices[Socket], PlatformConfig, StdHeader)) { + HtAssistEnabled = FALSE; + } + // If any node in the system does not support ATM mode, disable it on the system + if (!FamilyServices[Socket]->IsAtmModeSupported (FamilyServices[Socket], PlatformConfig, StdHeader)) { + AtmModeEnabled = FALSE; + } + } + } + + // Wait for 40us + WaitMicroseconds ((UINT32) 40, StdHeader); + + // Run DisableAllCaches on AP cores. + ApParams.StdHeader = *StdHeader; + ApParams.FunctionNumber = AP_LATE_TASK_DISABLE_CACHE; + ApParams.RelatedDataBlock = (VOID *) &HtAssistEnabled; + ApParams.RelatedBlockLength = sizeof (BOOLEAN); + RunLateApTaskOnAllAPs (&ApParams, StdHeader); + + // Run DisableAllCaches on core 0. + DisableAllCaches (&ApParams); + + // Family hook before initialization. + for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { + if (FamilyServices[Socket] != NULL) { + FamilyServices[Socket]->HookBeforeInit (FamilyServices[Socket], Socket, StdHeader); + } + } + + // Activate Probe Filter & ATM mode. + for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { + if (FamilyServices[Socket] != NULL) { + if (HtAssistEnabled) { + FamilyServices[Socket]->HtAssistInit (FamilyServices[Socket], Socket, StdHeader); + } + if (AtmModeEnabled) { + FamilyServices[Socket]->AtmModeInit (FamilyServices[Socket], Socket, StdHeader); + } + } + } + + // Family hook after initialization. + for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { + if (FamilyServices[Socket] != NULL) { + FamilyServices[Socket]->HookAfterInit (FamilyServices[Socket], Socket, StdHeader); + } + } + + // Run EnableAllCaches on core 0. + EnableAllCaches (&ApParams); + + // Run EnableAllCaches on every core. + ApParams.FunctionNumber = AP_LATE_TASK_ENABLE_CACHE; + RunLateApTaskOnAllAPs (&ApParams, StdHeader); + + // Restore the scrubbers. + for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { + if (FamilyServices[Socket] != NULL) { + FamilyServices[Socket]->SetL3ScrubCtrl (FamilyServices[Socket], Socket, &Scrubbers[Socket][0], StdHeader); + } + } + } + + return AgesaStatus; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * + * Disable all the caches on current core. + * + * @param[in] ApExeParams Handle to config for library and services. + * + * @retval AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +DisableAllCaches ( + IN AP_EXE_PARAMS *ApExeParams + ) +{ + UINT32 CR0Data; + L3_FEATURE_FAMILY_SERVICES *FamilyServices; + + // Disable cache through CR0. + LibAmdReadCpuReg (0, &CR0Data); + CR0Data |= (0x60000000); + LibAmdWriteCpuReg (0, CR0Data); + + // Execute wbinvd + LibAmdWriteBackInvalidateCache (); + + GetFeatureServicesOfCurrentCore (&L3FeatureFamilyServiceTable, (CONST VOID **)&FamilyServices, &ApExeParams->StdHeader); + + FamilyServices->HookDisableCache (FamilyServices, *(BOOLEAN *) ApExeParams->RelatedDataBlock, &ApExeParams->StdHeader); + + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * + * Enable all the caches on current core. + * + * @param[in] ApExeParams Handle to config for library and services. + * + * @retval AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +EnableAllCaches ( + IN AP_EXE_PARAMS *ApExeParams + ) +{ + UINT32 CR0Data; + L3_FEATURE_FAMILY_SERVICES *FamilyServices; + + // Enable cache through CR0. + LibAmdReadCpuReg (0, &CR0Data); + CR0Data &= ~(0x60000000); + LibAmdWriteCpuReg (0, CR0Data); + + GetFeatureServicesOfCurrentCore (&L3FeatureFamilyServiceTable, (CONST VOID **)&FamilyServices, &ApExeParams->StdHeader); + + FamilyServices->HookEnableCache (FamilyServices, &ApExeParams->StdHeader); + + return AGESA_SUCCESS; +} + +CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuL3Features = +{ + L3Features, + (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_INIT_MID_END | CPU_FEAT_S3_LATE_RESTORE_END), + IsL3FeatureEnabled, + InitializeL3Feature +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuL3Features.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuL3Features.h new file mode 100644 index 0000000..e0290a2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuL3Features.h @@ -0,0 +1,385 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU L3 Features Initialization functions. + * + * Contains code that declares the AGESA CPU L3 dependent feature related APIs + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Feature + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_L3_FEATURES_H_ +#define _CPU_L3_FEATIRES_H_ + +#include "Filecode.h" +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ +// Forward declaration needed for multi-structure mutual references +AGESA_FORWARD_DECLARATION (L3_FEATURE_FAMILY_SERVICES); + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define AP_LATE_TASK_DISABLE_CACHE (0x00000000ul | PROC_CPU_FEATURE_CPUL3FEATURES_FILECODE) +#define AP_LATE_TASK_ENABLE_CACHE (0x00010000ul | PROC_CPU_FEATURE_CPUL3FEATURES_FILECODE) + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +#define L3_SCRUBBER_CONTEXT_ARRAY_SIZE 4 + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to check if L3 Features are supported. + * + * @param[in] L3FeatureServices L3 Feature family services. + * @param[in] Socket Processor socket to check. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE L3 dependent features are supported + * @retval FALSE L3 dependent features are not supported + * + */ +typedef BOOLEAN F_L3_FEATURE_IS_SUPPORTED ( + IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, + IN UINT32 Socket, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_L3_FEATURE_IS_SUPPORTED *PF_L3_FEATURE_IS_SUPPORTED; + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific hook before L3 features are initialized. + * + * @param[in] L3FeatureServices L3 Feature family services. + * @param[in] Socket Processor socket to check. + * @param[in] StdHeader Config Handle for library, services. + * + */ +typedef VOID F_L3_FEATURE_BEFORE_INIT ( + IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, + IN UINT32 Socket, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_L3_FEATURE_BEFORE_INIT *PF_L3_FEATURE_BEFORE_INIT; + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to disable cache. + * + * @param[in] L3FeatureServices L3 Feature family services. + * @param[in] HtAssistEnabled Indicates whether Ht Assist is enabled. + * @param[in] StdHeader Config Handle for library, services. + * + */ +typedef VOID F_L3_FEATURE_DISABLE_CACHE ( + IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, + IN BOOLEAN HtAssistEnabled, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_L3_FEATURE_DISABLE_CACHE *PF_L3_FEATURE_DISABLE_CACHE; + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to disable cache. + * + * @param[in] L3FeatureServices L3 Feature family services. + * @param[in] StdHeader Config Handle for library, services. + * + * @return Family specific error value. + * + */ +typedef VOID F_L3_FEATURE_ENABLE_CACHE ( + IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_L3_FEATURE_ENABLE_CACHE *PF_L3_FEATURE_ENABLE_CACHE; + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to Initialize L3 Features + * + * @param[in] L3FeatureServices L3 Feature family services. + * @param[in] Socket Processor socket to enable. + * @param[in] StdHeader Config Handle for library, services. + * + */ +typedef VOID F_L3_FEATURE_INIT ( + IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, + IN UINT32 Socket, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_L3_FEATURE_INIT *PF_L3_FEATURE_INIT; + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific hook after L3 Features are initialized. + * + * @param[in] L3FeatureServices L3 Features family services. + * @param[in] Socket Processor socket to check. + * @param[in] StdHeader Config Handle for library, services. + * + */ +typedef VOID F_L3_FEATURE_AFTER_INIT ( + IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, + IN UINT32 Socket, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_L3_FEATURE_AFTER_INIT *PF_L3_FEATURE_AFTER_INIT; + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to save the L3 scrubber. + * + * @param[in] L3FeatureServices L3 Feature family services. + * @param[in] Socket Processor socket to check. + * @param[in] ScrubSettings Location to store current L3 scrubber settings. + * @param[in] StdHeader Config Handle for library, services. + * + */ +typedef VOID F_L3_FEATURE_GET_L3_SCRUB_CTRL ( + IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, + IN UINT32 Socket, + IN UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE], + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_L3_FEATURE_GET_L3_SCRUB_CTRL *PF_L3_FEATURE_GET_L3_SCRUB_CTRL; + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to restore the L3 scrubber. + * + * @param[in] L3FeatureServices L3 Feature family services. + * @param[in] Socket Processor socket to check. + * @param[in] ScrubSettings Contains L3 scrubber settings to restore. + * @param[in] StdHeader Config Handle for library, services. + * + */ +typedef VOID F_L3_FEATURE_SET_L3_SCRUB_CTRL ( + IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, + IN UINT32 Socket, + IN UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE], + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_L3_FEATURE_SET_L3_SCRUB_CTRL *PF_L3_FEATURE_SET_L3_SCRUB_CTRL; + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to check if HT Assist is supported. + * + * @param[in] L3FeatureServices L3 Feature family services. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE HT Assist is supported. + * @retval FALSE HT Assist is not supported. + * + */ +typedef BOOLEAN F_HT_ASSIST_IS_SUPPORTED ( + IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_HT_ASSIST_IS_SUPPORTED *PF_HT_ASSIST_IS_SUPPORTED; + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to Initialize HT Assist + * + * @param[in] L3FeatureServices L3 Features family services. + * @param[in] Socket Processor socket to enable. + * @param[in] StdHeader Config Handle for library, services. + * + */ +typedef VOID F_HT_ASSIST_INIT ( + IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, + IN UINT32 Socket, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_HT_ASSIST_INIT *PF_HT_ASSIST_INIT; + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to provide non_optimal HT Assist support + * + * @param[in] L3FeatureServices L3 Feature family services. + * @param[in] Socket Processor socket to check. + * @param[in] StdHeader Config Handle for library, services. + * + * @return TRUE The system may be running with non-optimal settings. + * @return FALSE The system may is running optimally. + * + */ +typedef BOOLEAN F_HT_ASSIST_IS_NONOPTIMAL ( + IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, + IN UINT32 Socket, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_HT_ASSIST_IS_NONOPTIMAL *PF_HT_ASSIST_IS_NONOPTIMAL; + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to check if ATM Mode is supported. + * + * @param[in] L3FeatureServices L3 Features family services. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE ATM Mode is supported. + * @retval FALSE ATM Mode is not supported. + * + */ +typedef BOOLEAN F_ATM_MODE_IS_SUPPORTED ( + IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_ATM_MODE_IS_SUPPORTED *PF_ATM_MODE_IS_SUPPORTED; + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to Initialize ATM mode + * + * @param[in] L3FeatureServices L3 Features family services. + * @param[in] Socket Processor socket to enable. + * @param[in] StdHeader Config Handle for library, services. + * + */ +typedef VOID F_ATM_MODE_INIT ( + IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices, + IN UINT32 Socket, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_ATM_MODE_INIT *PF_ATM_MODE_INIT; + +/** + * Provide the interface to the L3 dependent features Family Specific Services. + * + * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). + * Each supported Family must provide an implementation for all methods in this interface, even if the + * implementation is a CommonReturn(). + */ +struct _L3_FEATURE_FAMILY_SERVICES { + UINT16 Revision; ///< Interface version + // Public Methods. + PF_L3_FEATURE_IS_SUPPORTED IsL3FeatureSupported; ///< Method: Check if L3 dependent features are supported. + PF_L3_FEATURE_GET_L3_SCRUB_CTRL GetL3ScrubCtrl; ///< Method: Save/disable the L3 scrubber. + PF_L3_FEATURE_SET_L3_SCRUB_CTRL SetL3ScrubCtrl; ///< Method: Restore the L3 scrubber. + PF_L3_FEATURE_BEFORE_INIT HookBeforeInit; ///< Method: Hook before enabling L3 dependent features. + PF_L3_FEATURE_AFTER_INIT HookAfterInit; ///< Method: Hook after enabling L3 dependent features. + PF_L3_FEATURE_DISABLE_CACHE HookDisableCache; ///< Method: Core hook just before disabling cache. + PF_L3_FEATURE_ENABLE_CACHE HookEnableCache; ///< Method: Core hook just after enabling cache. + PF_HT_ASSIST_IS_SUPPORTED IsHtAssistSupported; ///< Method: Check if HT Assist is supported. + PF_HT_ASSIST_INIT HtAssistInit; ///< Method: Enable HT Assist. + PF_HT_ASSIST_IS_NONOPTIMAL IsNonOptimalConfig; ///< Method: Check if HT Assist is running optimally. + PF_ATM_MODE_IS_SUPPORTED IsAtmModeSupported; ///< Method: Check if ATM Mode is supported. + PF_ATM_MODE_INIT AtmModeInit; ///< Method: Enable ATM Mode. +}; + + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N S P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +DisableAllCaches ( + IN AP_EXE_PARAMS *ApExeParams + ); + +AGESA_STATUS +EnableAllCaches ( + IN AP_EXE_PARAMS *ApExeParams + ); + +#endif // _CPU_L3_FEATURES_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuLowPwrPstate.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuLowPwrPstate.c new file mode 100644 index 0000000..c70a448 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuLowPwrPstate.c @@ -0,0 +1,309 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA CPU create low power P-state for PROCHOT_L throttling support code. + * + * Contains code that declares the AGESA CPU low power P-state related APIs + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Feature + * @e $Revision: 63523 $ @e $Date: 2011-12-25 20:31:15 -0600 (Sun, 25 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "cpuApicUtilities.h" +#include "OptionMultiSocket.h" +#include "cpuRegisters.h" +#include "cpuApicUtilities.h" +#include "cpuFeatures.h" +#include "cpuLowPwrPstate.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FEATURE_CPULOWPWRPSTATE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +EnableLowPwrPstateOnSocket ( + IN VOID *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +ProgramHtcPstateLimit ( + IN VOID *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern CPU_FAMILY_SUPPORT_TABLE LowPwrPstateFamilyServiceTable; + +/*---------------------------------------------------------------------------------------*/ +/** + * Should Low Power P-state be enabled + * If all processors support Low Power P-state, reture TRUE, otherwise reture FALSE + * + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE Low Power P-state is supported. + * @retval FALSE Low Power P-state cannot be enabled. + * + */ +BOOLEAN +STATIC +IsLowPwrPstateFeatureSupported ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Socket; + BOOLEAN IsSupported; + LOW_PWR_PSTATE_FAMILY_SERVICES *FamilyServices; + + IsSupported = FALSE; + if (PlatformConfig->LowPowerPstateForProcHot == LOW_POWER_PSTATE_FOR_PROCHOT_AUTO) { + for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { + if (IsProcessorPresent (Socket, StdHeader)) { + GetFeatureServicesOfSocket (&LowPwrPstateFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader); + if (FamilyServices != NULL) { + if (FamilyServices->IsLowPwrPstateSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) { + IsSupported = TRUE; + } else { + IsSupported = FALSE; + break; + } + } else { + IsSupported = FALSE; + break; + } + } + } + } + IDS_OPTION_HOOK (IDS_LOW_POWER_PSTATE, &IsSupported, StdHeader); + return IsSupported; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Enable low power P-state + * + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +STATIC +InitializeLowPwrPstateFeature ( + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 BscSocket; + UINT32 Ignored; + UINT32 BscCoreNum; + UINT32 Core; + UINT32 Socket; + UINT32 NumberOfSockets; + UINT32 NumberOfCores; + AP_TASK TaskPtr; + AGESA_STATUS IgnoredSts; + + IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); + NumberOfSockets = GetPlatformNumberOfSockets (); + + if (!IsWarmReset (StdHeader)) { + IDS_HDT_CONSOLE (CPU_TRACE, " Low pwr P-state is enabled\n"); + + TaskPtr.FuncAddress.PfApTaskI = EnableLowPwrPstateOnSocket; + TaskPtr.DataTransfer.DataSizeInDwords = 2; + TaskPtr.DataTransfer.DataPtr = PlatformConfig; + TaskPtr.DataTransfer.DataTransferFlags = 0; + TaskPtr.ExeFlags = WAIT_FOR_CORE; + + for (Socket = 0; Socket < NumberOfSockets; Socket++) { + if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { + for (Core = 0; Core < NumberOfCores; Core++) { + if ((Socket != BscSocket) || (Core != BscCoreNum)) { + ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); + } + } + } + } + + EnableLowPwrPstateOnSocket (PlatformConfig, StdHeader); + } else { + TaskPtr.FuncAddress.PfApTaskI = ProgramHtcPstateLimit; + TaskPtr.DataTransfer.DataSizeInDwords = 2; + TaskPtr.DataTransfer.DataPtr = PlatformConfig; + TaskPtr.DataTransfer.DataTransferFlags = 0; + TaskPtr.ExeFlags = WAIT_FOR_CORE; + + for (Socket = 0; Socket < NumberOfSockets; Socket++) { + if (IsProcessorPresent (Socket, StdHeader)) { + if (Socket != BscSocket) { + ApUtilRunCodeOnSocketCore ((UINT8) Socket, 0, &TaskPtr, StdHeader); + } + } + } + + ProgramHtcPstateLimit (PlatformConfig, StdHeader); + } + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * All APs task to enable low power P-state + * + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + */ +VOID +STATIC +EnableLowPwrPstateOnSocket ( + IN VOID *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + LOW_PWR_PSTATE_FAMILY_SERVICES *FamilyServices; + + GetFeatureServicesOfCurrentCore (&LowPwrPstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); + FamilyServices->EnableLowPwrPstate (FamilyServices, + PlatformConfig, + StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * 'Local' core 0 task to enable low power P-state + * + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + */ +VOID +STATIC +ProgramHtcPstateLimit ( + IN VOID *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 OrMask; + UINT32 HtcCtrl; + UINT32 CPTC2; + PCI_ADDR PciAddress; + + OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); + PciAddress.Address.Function = FUNC_3; + + PciAddress.Address.Register = CLOCK_POWER_TIMING_CTRL2_REG; + LibAmdPciRead (AccessWidth32, PciAddress, &CPTC2, StdHeader); // F3xDC[10:8] HwPstateMaxVal + OrMask = CPTC2 & 0x700; + OrMask = OrMask << 20; + + PciAddress.Address.Register = HARDWARE_THERMAL_CTRL_REG; + LibAmdPciRead (AccessWidth32, PciAddress, &HtcCtrl, StdHeader); // F3x64[30:28] HtcPstateLimit + // F3x64[30:28] HtcPstateLimit = F3xDC[10:8] HwPstateMaxVal + HtcCtrl = (HtcCtrl & 0x8FFFFFFF) | OrMask; + LibAmdPciWrite (AccessWidth32, PciAddress, &HtcCtrl, StdHeader); +} + +CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureLowPwrPstate = +{ + LowPwrPstate, + (CPU_FEAT_BEFORE_RELINQUISH_AP | CPU_FEAT_AFTER_RESUME_MTRR_SYNC), + IsLowPwrPstateFeatureSupported, + InitializeLowPwrPstateFeature +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuLowPwrPstate.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuLowPwrPstate.h new file mode 100644 index 0000000..77a3dd4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuLowPwrPstate.h @@ -0,0 +1,156 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA CPU create low power P-state for PROCHOT_L throttling Functions declarations. + * + * Contains code that declares the AGESA CPU low power P-state related APIs + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Feature + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_LOW_PWR_PSTATE_H_ +#define _CPU_LOW_PWR_PSTATE_H_ + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ +// Forward declaration needed for multi-structure mutual references +AGESA_FORWARD_DECLARATION (LOW_PWR_PSTATE_FAMILY_SERVICES); + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to check if Low Power P-state is supported. + * + * @param[in] LowPwrPstateService Low Power P-state services. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] Socket Zero-based socket number. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE Low Power P-state is supported. + * @retval FALSE Low Power P-state is not supported. + * + */ +typedef BOOLEAN F_LOW_PWR_PSTATE_IS_SUPPORTED ( + IN LOW_PWR_PSTATE_FAMILY_SERVICES *LowPwrPstateService, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN UINT32 Socket, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_LOW_PWR_PSTATE_IS_SUPPORTED *PF_LOW_PWR_PSTATE_IS_SUPPORTED; + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to enable Low Power P-state + * + * @param[in] LowPwrPstateService Low Power P-state services. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @return Family specific error value. + * + */ +typedef AGESA_STATUS F_LOW_PWR_PSTATE_INIT ( + IN LOW_PWR_PSTATE_FAMILY_SERVICES *LowPwrPstateService, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_LOW_PWR_PSTATE_INIT *PF_LOW_PWR_PSTATE_INIT; + +/** + * Provide the interface to the Low Power P-state Family Specific Services. + * + * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). + * Each supported Family must provide an implementation for all methods in this interface, even if the + * implementation is a CommonReturn(). + */ +struct _LOW_PWR_PSTATE_FAMILY_SERVICES { + UINT16 Revision; ///< Interface version + // Public Methods. + PF_LOW_PWR_PSTATE_IS_SUPPORTED IsLowPwrPstateSupported; ///< Method: Family specific call to check if Low Power P-state is supported. + PF_LOW_PWR_PSTATE_INIT EnableLowPwrPstate; ///< Method: Family specific call to enable Low Power P-state. +}; + + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N S P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ + +#endif // _CPU_LOW_PWR_PSTATE_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuMsgBasedC1e.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuMsgBasedC1e.c new file mode 100644 index 0000000..0b7c272 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuMsgBasedC1e.c @@ -0,0 +1,238 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA CPU Message-based C1e feature support code. + * + * Contains code that declares the AGESA CPU C1e related APIs + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Feature + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMultiSocket.h" +#include "cpuRegisters.h" +#include "cpuApicUtilities.h" +#include "cpuServices.h" +#include "cpuFamilyTranslation.h" +#include "cpuFeatures.h" +#include "cpuMsgBasedC1e.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FEATURE_CPUMSGBASEDC1E_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +EnableMsgC1eOnSocket ( + IN VOID *EntryPoint, + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern CPU_FAMILY_SUPPORT_TABLE MsgBasedC1eFamilyServiceTable; +extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; + +/*---------------------------------------------------------------------------------------*/ +/** + * Should message-based C1e be enabled + * + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE Message-based C1e is supported. + * @retval FALSE Message-based C1e cannot be enabled. + * + */ +BOOLEAN +STATIC +IsMsgBasedC1eFeatureEnabled ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + BOOLEAN IsEnabled; + UINT32 Socket; + MSG_BASED_C1E_FAMILY_SERVICES *FamilyServices; + + ASSERT (PlatformConfig->C1eMode < MaxC1eMode); + + IsEnabled = FALSE; + if ((PlatformConfig->C1eMode == C1eModeMsgBased) || (PlatformConfig->C1eMode == C1eModeAuto)) { + ASSERT (PlatformConfig->C1ePlatformData < 0x10000); + ASSERT (PlatformConfig->C1ePlatformData != 0); + if ((PlatformConfig->C1ePlatformData != 0) && (PlatformConfig->C1ePlatformData < 0xFFFE)) { + IsEnabled = TRUE; + if (IsNonCoherentHt1 (StdHeader)) { + IsEnabled = FALSE; + } else { + for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { + if (IsProcessorPresent (Socket, StdHeader)) { + GetFeatureServicesOfSocket (&MsgBasedC1eFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader); + if ((FamilyServices == NULL) || !FamilyServices->IsMsgBasedC1eSupported (FamilyServices, Socket, StdHeader)) { + IsEnabled = FALSE; + break; + } + } + } + } + } + } + return IsEnabled; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Enable Message-based C1e + * + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @return AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +STATIC +InitializeMsgBasedC1eFeature ( + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AP_TASK TaskPtr; + AMD_CPU_EARLY_PARAMS CpuEarlyParams; + + IDS_HDT_CONSOLE (CPU_TRACE, " MT C1e is enabled\n"); + + if ((EntryPoint != CPU_FEAT_AFTER_PM_INIT) || (IsWarmReset (StdHeader))) { + CpuEarlyParams.PlatformConfig = *PlatformConfig; + + TaskPtr.FuncAddress.PfApTaskIC = EnableMsgC1eOnSocket; + TaskPtr.DataTransfer.DataSizeInDwords = 2; + TaskPtr.DataTransfer.DataPtr = &EntryPoint; + TaskPtr.DataTransfer.DataTransferFlags = 0; + TaskPtr.ExeFlags = PASS_EARLY_PARAMS; + OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams); + } + return AGESA_SUCCESS; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * 'Local' core 0 task to enable message-based C1e on it's socket. + * + * @param[in] EntryPoint Timepoint designator. + * @param[in] StdHeader Config Handle for library, services. + * @param[in] CpuEarlyParams Service parameters. + * + */ +VOID +STATIC +EnableMsgC1eOnSocket ( + IN VOID *EntryPoint, + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams + ) +{ + MSG_BASED_C1E_FAMILY_SERVICES *FamilyServices; + + GetFeatureServicesOfCurrentCore (&MsgBasedC1eFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); + FamilyServices->InitializeMsgBasedC1e (FamilyServices, + *((UINT64 *) EntryPoint), + &CpuEarlyParams->PlatformConfig, + StdHeader); +} + +CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e = +{ + MsgBasedC1e, + (CPU_FEAT_AFTER_PM_INIT | CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC), + IsMsgBasedC1eFeatureEnabled, + InitializeMsgBasedC1eFeature +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuMsgBasedC1e.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuMsgBasedC1e.h new file mode 100644 index 0000000..40128fa --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuMsgBasedC1e.h @@ -0,0 +1,154 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA CPU Message-based C1e Functions declarations. + * + * Contains code that declares the AGESA CPU C1e related APIs + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Feature + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_MSG_BASED_C1E_H_ +#define _CPU_MSG_BASED_C1E_H_ + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ +// Forward declaration needed for multi-structure mutual references +AGESA_FORWARD_DECLARATION (MSG_BASED_C1E_FAMILY_SERVICES); + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to check if message-based C1e is supported. + * + * @param[in] MsgBasedC1eServices Contains the runtime modifiable feature input data. + * @param[in] Socket Processor socket to check. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE Message-based C1e is supported. + * @retval FALSE Message-based C1e is not supported. + * + */ +typedef BOOLEAN F_MSG_BASED_C1E_IS_SUPPORTED ( + IN MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices, + IN UINT32 Socket, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_MSG_BASED_C1E_IS_SUPPORTED *PF_MSG_BASED_C1E_IS_SUPPORTED; + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to enable hardware C1e. + * + * @param[in] MsgBasedC1eServices Hardware C1e services. + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @return Family specific error value. + * + */ +typedef AGESA_STATUS F_MSG_BASED_C1E_INIT ( + IN MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices, + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_MSG_BASED_C1E_INIT *PF_MSG_BASED_C1E_INIT; + +/** + * Provide the interface to the hardware C1e Family Specific Services. + * + * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). + * Each supported Family must provide an implementation for all methods in this interface, even if the + * implementation is a CommonReturn(). + */ +struct _MSG_BASED_C1E_FAMILY_SERVICES { + UINT16 Revision; ///< Interface version + // Public Methods. + PF_MSG_BASED_C1E_IS_SUPPORTED IsMsgBasedC1eSupported; ///< Method: Family specific call to check if hardware C1e is supported. + PF_MSG_BASED_C1E_INIT InitializeMsgBasedC1e; ///< Method: Family specific call to enable hardware C1e. +}; + + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N S P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ + +#endif // _CPU_MSG_BASED_C1E_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPsi.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPsi.c new file mode 100644 index 0000000..24c907e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPsi.c @@ -0,0 +1,240 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA CPU Power Status Indicator (PSI) feature support code. + * + * Contains code that declares the AGESA CPU PSI related APIs + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Feature + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "cpuApicUtilities.h" +#include "cpuFeatures.h" +#include "cpuPsi.h" +#include "OptionMultiSocket.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FEATURE_CPUPSI_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +UINT32 +STATIC +EnablePsiOnSocket ( + IN VOID *EntryPoint, + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern CPU_FAMILY_SUPPORT_TABLE PsiFamilyServiceTable; +extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; + +/*---------------------------------------------------------------------------------------*/ +/** + * Should Power Status Indicator (PSI) be enabled + * + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE PSI is supported. + * @retval FALSE PSI cannot be enabled. + * + */ +BOOLEAN +STATIC +IsPsiFeatureEnabled ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Socket; + BOOLEAN IsEnabled; + PSI_FAMILY_SERVICES *PsiFamilyServices; + UINT32 VrmType; + + IsEnabled = FALSE; + + for (VrmType = 0; VrmType < MaxVrmType; VrmType++) { + if (PlatformConfig->VrmProperties[VrmType].LowPowerThreshold != 0) { + IsEnabled = TRUE; + break; + } + } + + if (!IsEnabled) { + return FALSE; + } + + for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { + if (IsProcessorPresent (Socket, StdHeader)) { + GetFeatureServicesOfSocket (&PsiFamilyServiceTable, Socket, (CONST VOID **)&PsiFamilyServices, StdHeader); + if ((PsiFamilyServices == NULL) || (!PsiFamilyServices->IsPsiSupported (PsiFamilyServices, Socket, PlatformConfig, StdHeader))) { + IsEnabled = FALSE; + break; + } + } + } + return IsEnabled; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Enable Power Status Indicator (PSI) + * + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +STATIC +InitializePsiFeature ( + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AP_TASK TaskPtr; + AGESA_STATUS AgesaStatus; + AMD_CPU_EARLY_PARAMS CpuEarlyParams; + + IDS_HDT_CONSOLE (CPU_TRACE, " PSI mode is being initialized\n"); + + CpuEarlyParams.PlatformConfig = *PlatformConfig; + + TaskPtr.FuncAddress.PfApTaskIOC = EnablePsiOnSocket; + TaskPtr.DataTransfer.DataSizeInDwords = 2; + TaskPtr.DataTransfer.DataPtr = &EntryPoint; + TaskPtr.DataTransfer.DataTransferFlags = 0; + TaskPtr.ExeFlags = PASS_EARLY_PARAMS | TASK_HAS_OUTPUT; + AgesaStatus = OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams); + + IDS_HDT_CONSOLE (CPU_TRACE, " PSI mode is enabled\n"); + + return AgesaStatus; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * AP task to enable PSI + * + * @param[in] EntryPoint Timepoint designator. + * @param[in] StdHeader Config Handle for library, services. + * @param[in] CpuEarlyParams Service parameters. + * + */ +UINT32 +STATIC +EnablePsiOnSocket ( + IN VOID *EntryPoint, + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams + ) +{ + AGESA_STATUS CalledStatus; + PSI_FAMILY_SERVICES *PsiFamilyServices; + + CalledStatus = AGESA_UNSUPPORTED; + GetFeatureServicesOfCurrentCore (&PsiFamilyServiceTable, (CONST VOID **)&PsiFamilyServices, StdHeader); + if (PsiFamilyServices != NULL) { + CalledStatus = PsiFamilyServices->EnablePsiOnSocket (PsiFamilyServices, *((UINT64 *) EntryPoint), &CpuEarlyParams->PlatformConfig, StdHeader); + } + return (UINT32) CalledStatus; +} + +CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePsi = +{ + CpuPsi, + (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC), + IsPsiFeatureEnabled, + InitializePsiFeature +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPsi.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPsi.h new file mode 100644 index 0000000..ca94466 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPsi.h @@ -0,0 +1,157 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA CPU Power Status Indicator (PSI) Functions declarations. + * + * Contains code that declares the AGESA CPU PSI related APIs + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Feature + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_PSI_H_ +#define _CPU_PSI_H_ + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ +// Forward declaration needed for multi-structure mutual references +AGESA_FORWARD_DECLARATION (PSI_FAMILY_SERVICES); + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to check if Power Status Indicator (PSI) is supported. + * + * @param[in] PsiServices PSI services. + * @param[in] Socket Zero-based socket number. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE PSI is supported. + * @retval FALSE PSI is not supported. + * + */ +typedef BOOLEAN F_PSI_IS_SUPPORTED ( + IN PSI_FAMILY_SERVICES *PsiServices, + IN UINT32 Socket, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_PSI_IS_SUPPORTED *PF_PSI_IS_SUPPORTED; + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to enable PSI. + * + * @param[in] PsiServices PSI services. + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @return Family specific error value. + * + */ +typedef AGESA_STATUS F_PSI_INIT ( + IN PSI_FAMILY_SERVICES *PsiServices, + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_PSI_INIT *PF_PSI_INIT; + +/** + * Provide the interface to the PSI Family Specific Services. + * + * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). + * Each supported Family must provide an implementation for all methods in this interface, even if the + * implementation is a CommonReturn(). + */ +/* typedef */struct _PSI_FAMILY_SERVICES { + UINT16 Revision; ///< Interface version + // Public Methods. + PF_PSI_IS_SUPPORTED IsPsiSupported; ///< Method: Family specific call to check if PSI is supported. + PF_PSI_INIT EnablePsiOnSocket; ///< Method: Family specific call to enable PSI. +} /* PSI_FAMILY_SERVICES */; + + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N S P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ + +#endif // _CPU_PSI_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateGather.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateGather.c new file mode 100644 index 0000000..f28c853 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateGather.c @@ -0,0 +1,437 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Pstate Data Gather Function. + * + * Contains code to collect all the Pstate related information from MSRs, and PCI registers. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "OptionPstate.h" +#include "cpuRegisters.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "cpuPostInit.h" +#include "Ids.h" +#include "cpuFamilyTranslation.h" +#include "cpuPstateTables.h" +#include "cpuApicUtilities.h" +#include "cpuFeatures.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FEATURE_CPUPSTATEGATHER_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +extern OPTION_PSTATE_POST_CONFIGURATION OptionPstatePostConfiguration; // global user config record +extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +AGESA_STATUS +PStateGatherStub ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr + ); + +AGESA_STATUS +PStateGatherMain ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr + ); + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +VOID +PStateGather ( + IN OUT VOID *PStateBuffer, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + *--------------------------------------------------------------------------------------- + * + * PStateGatherData + * + * Description: + * This function will gather PState information from the MSRs and fill up the + * pStateBuf. This buffer will be used by the PState Leveling, and PState Table + * generation code later. + * + * Parameters: + * @param[in] *PlatformConfig + * @param[in, out] *PStateStrucPtr + * @param[in] *StdHeader + * + * @retval AGESA_STATUS + * + *--------------------------------------------------------------------------------------- + **/ +AGESA_STATUS +PStateGatherData ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + + AGESA_STATUS AgesaStatus; + + AGESA_TESTPOINT (TpProcCpuEntryPstateGather, StdHeader); + AgesaStatus = AGESA_SUCCESS; + + // Gather data for ACPI Tables if ACPI P-States/C-States object generation is enabled. + if ((PlatformConfig->UserOptionPState) || (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader))) { + AgesaStatus = (*(OptionPstatePostConfiguration.PstateGather)) (StdHeader, PStateStrucPtr); + // Note: Split config struct into PEI/DXE halves. This one is PEI. + } + + return AgesaStatus; +} + +/**-------------------------------------------------------------------------------------- + * + * PStateGatherStub + * + * Description: + * This is the default routine for use when the PState option is NOT requested. + * The option install process will create and fill the transfer vector with + * the address of the proper routine (Main or Stub). The link optimizer will + * strip out of the .DLL the routine that is not used. + * + * Parameters: + * @param[in] *StdHeader + * @param[in, out] *PStateStrucPtr + * + * @retval AGESA_STATUS + * + *--------------------------------------------------------------------------------------- + **/ +AGESA_STATUS +PStateGatherStub ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr + ) +{ + return AGESA_UNSUPPORTED; +} + +/**-------------------------------------------------------------------------------------- + * + * PStateGatherMain + * + * Description: + * This is the common routine for BSP gathering the Pstate data. + * + * Parameters: + * @param[in] *StdHeader + * @param[in, out] *PStateStrucPtr + * + * @retval AGESA_STATUS + * + *--------------------------------------------------------------------------------------- + **/ +AGESA_STATUS +PStateGatherMain ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr + ) +{ + AP_TASK TaskPtr; + UINT32 BscSocket; + UINT32 Ignored; + UINT32 PopulatedSockets; + UINT32 NumberOfSockets; + UINT32 Socket; + AGESA_STATUS IgnoredSts; + PSTATE_LEVELING *PStateBufferPtr; + PSTATE_CPU_FAMILY_SERVICES *FamilyServices; + UINT32 MaxState; + UINT8 IgnoredByte; + + ASSERT (IsBsp (StdHeader, &IgnoredSts)); + + FamilyServices = NULL; + GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); + ASSERT (FamilyServices != NULL); + + PopulatedSockets = 1; + PStateBufferPtr = PStateStrucPtr->PStateLevelingStruc; + + NumberOfSockets = GetPlatformNumberOfSockets (); + IdentifyCore (StdHeader, &BscSocket, &Ignored, &Ignored, &IgnoredSts); + + PStateStrucPtr->SizeOfBytes = sizeof (S_CPU_AMD_PSTATE); + + MaxState = 0; + FamilyServices->GetPstateMaxState (FamilyServices, &MaxState, &IgnoredByte, StdHeader); + + TaskPtr.FuncAddress.PfApTaskI = PStateGather; + // + // Calculate max buffer size in dwords that need to pass to ap task. + // + TaskPtr.DataTransfer.DataSizeInDwords = (UINT16) ((MaxState + 1) * (SIZE_IN_DWORDS (S_PSTATE_VALUES))); + TaskPtr.ExeFlags = WAIT_FOR_CORE; + TaskPtr.DataTransfer.DataPtr = PStateBufferPtr; + TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY; + + // + //Get P-States and fill the PStateBufferPtr for BSP + // + ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, NULL); + + // + //Calculate next node buffer address + // + PStateBufferPtr->SocketNumber = (UINT8) BscSocket; + PStateBufferPtr->PStateLevelingSizeOfBytes = (UINT16) (sizeof (PSTATE_LEVELING) + (UINT32) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES))); + PStateStrucPtr->SizeOfBytes += (UINT32) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)); + PStateBufferPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES))); + CpuGetPStateLevelStructure (&PStateBufferPtr, PStateStrucPtr, 1, StdHeader); + // + //Get CPU P-States and fill the PStateBufferPtr for each node(BSC) + // + for (Socket = 0; Socket < NumberOfSockets; Socket++) { + if (Socket != BscSocket) { + if (IsProcessorPresent (Socket, StdHeader)) { + PopulatedSockets++; + LibAmdMemFill (PStateBufferPtr, 0, sizeof (PSTATE_LEVELING), StdHeader); + TaskPtr.DataTransfer.DataPtr = PStateBufferPtr; + ApUtilRunCodeOnSocketCore ((UINT8)Socket, 0, &TaskPtr, StdHeader); + PStateBufferPtr->SocketNumber = (UINT8) Socket; + // + //Calculate next node buffer address + // + PStateBufferPtr->PStateLevelingSizeOfBytes = (UINT16) (sizeof (PSTATE_LEVELING) + (UINT32) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES))); + PStateStrucPtr->SizeOfBytes += PStateBufferPtr->PStateLevelingSizeOfBytes; + PStateBufferPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES))); + } + } + } + PStateStrucPtr->TotalSocketInSystem = PopulatedSockets; + + return AGESA_SUCCESS; +} +/**-------------------------------------------------------------------------------------- + * + * PStateGather + * + * Description: + * This is the common routine run on each BSC for gathering Pstate data. + * + * Parameters: + * @param[in,out] *PStateBuffer + * @param[in] *StdHeader + * + * @retval VOID + * + *--------------------------------------------------------------------------------------- + **/ +VOID +PStateGather ( + IN OUT VOID *PStateBuffer, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 k; + UINT32 IddVal; + UINT32 IddDiv; + UINT32 NodeNum; + UINT32 CoreNum; + UINT32 TempVar_c; + UINT32 TotalEnabledPStates; + UINT32 SwPstate; + UINT8 BoostStates; + PCI_ADDR PciAddress; + PSTATE_LEVELING *PStateBufferPtr; + BOOLEAN PStateEnabled; + PSTATE_CPU_FAMILY_SERVICES *FamilyServices; + UINT32 Socket; + AGESA_STATUS IgnoredSts; + CPUID_DATA CpuId; + + PStateBufferPtr = (PSTATE_LEVELING *) PStateBuffer; + TotalEnabledPStates = 0; + FamilyServices = NULL; + PStateEnabled = FALSE; + + GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); + ASSERT (FamilyServices != NULL); + + // + /// Sockets number: code looking at PStateBufferPtr->TotalCoresInNode + /// needs to know it is Processor (or socket) core count and NOT a Node Core count. + GetActiveCoresInCurrentSocket (&CoreNum, StdHeader); + PStateBufferPtr->TotalCoresInNode = (UINT8) CoreNum; + + // + // Assume current CoreNum always zero.(BSC) + // + GetCurrentNodeAndCore (&NodeNum, &CoreNum, StdHeader); + + PStateBufferPtr->CreateAcpiTables = 1; + + // + // We need to know the max pstate state in this socket. + // + FamilyServices->GetPstateMaxState (FamilyServices, &TempVar_c, &BoostStates, StdHeader); + PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue = (UINT8) TempVar_c; + PStateBufferPtr->PStateCoreStruct[0].NumberOfBoostedStates = BoostStates; + + for (k = 0; k <= TempVar_c; k++) { + // Check if PState is enabled + FamilyServices->GetPstateRegisterInfo ( FamilyServices, + k, + &PStateEnabled, + &IddVal, + &IddDiv, + &SwPstate, + StdHeader); + + LibAmdMemFill (&(PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k]), 0, sizeof (S_PSTATE_VALUES), StdHeader); + + if (PStateEnabled) { + FamilyServices->GetPstateFrequency ( + FamilyServices, + (UINT8) k, + &(PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].CoreFreq), + StdHeader); + + FamilyServices->GetPstatePower ( + FamilyServices, + (UINT8) k, + &(PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].Power), + StdHeader); + + PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].IddValue = IddVal; + PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].IddDiv = IddDiv; + PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber = SwPstate; + + PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 1; + TotalEnabledPStates++; + } + } // for (k = 0; k < MPPSTATE_MAXIMUM_STATES; k++) + + // Don't create ACPI Tables if there is one or less than one PState is enabled + if (TotalEnabledPStates <= 1) { + PStateBufferPtr[0].CreateAcpiTables = 0; + } + + //--------------------Check Again-------------------------------- + + IdentifyCore (StdHeader, &Socket, &NodeNum, &CoreNum, &IgnoredSts); + // Get the PCI address of internal die 0 as it is the only die programmed. + GetPciAddress (StdHeader, Socket, 0, &PciAddress, &IgnoredSts); + PciAddress.Address.Function = FUNC_3; + PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_REG; + TempVar_c = 0; + LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_c, StdHeader); + PStateBufferPtr->PStateCoreStruct[0].HtcCapable = + (UINT8) ((TempVar_c & 0x00000400) >> 10); // Bit 10 + + TempVar_c = 0; + PciAddress.Address.Register = HARDWARE_THERMAL_CTRL_REG; + LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_c, StdHeader); + PStateBufferPtr->PStateCoreStruct[0].HtcPstateLimit = + (UINT8) ((TempVar_c & 0x70000000) >> 28); // Bits 30:28 + + // Get LocalApicId from CPUID Fn0000_0001_EBX + LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuId, StdHeader); + PStateBufferPtr->PStateCoreStruct[0].LocalApicId = (UINT8) ((CpuId.EBX_Reg & 0xFF000000) >> 24); +} + + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateHpcMode.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateHpcMode.c new file mode 100644 index 0000000..90956ce --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateHpcMode.c @@ -0,0 +1,247 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA CPU create Pstate HPC mode support code. + * + * Contains code that declares the AGESA CPU Pstate HPC mode related APIs + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Feature + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "cpuApicUtilities.h" +#include "OptionMultiSocket.h" +#include "cpuRegisters.h" +#include "cpuApicUtilities.h" +#include "cpuFeatures.h" +#include "cpuPstateHpcMode.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FEATURE_CPUPSTATEHPCMODE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +EnablePstateHpcModeOnAps ( + IN VOID *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern CPU_FAMILY_SUPPORT_TABLE PstateHpcModeFamilyServiceTable; + +/*---------------------------------------------------------------------------------------*/ +/** + * Should P-state HPC mode be enabled + * If PlatformConfig->PStatesInHpcMode is TRUE, return TRUE, otherwise reture FALSE + * + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE P-state HPC mode is supported. + * @retval FALSE P-state HPC mode cannot be enabled. + * + */ +BOOLEAN +STATIC +IsPstateHpcModeFeatureSupported ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + BOOLEAN IsEnabled; + UINT32 Socket; + PSTATE_HPC_MODE_FAMILY_SERVICES *FamilyServices; + + IsEnabled = TRUE; + + if (PlatformConfig->PStatesInHpcMode) { + for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { + if (IsProcessorPresent (Socket, StdHeader)) { + GetFeatureServicesOfSocket (&PstateHpcModeFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader); + if (FamilyServices == NULL) { + IsEnabled = FALSE; + break; + } + } + } + } else { + IsEnabled = FALSE; + } + return IsEnabled; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Enable high performance computing (HPC mode) + * + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +STATIC +InitializePstateHpcModeFeature ( + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 BscSocket; + UINT32 Ignored; + UINT32 BscCoreNum; + UINT32 Core; + UINT32 Socket; + UINT32 NumberOfSockets; + UINT32 NumberOfCores; + AP_TASK TaskPtr; + AGESA_STATUS IgnoredSts; + + if (!IsWarmReset (StdHeader)) { + IDS_HDT_CONSOLE (CPU_TRACE, " P-state HPC mode is enabled\n"); + + IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); + NumberOfSockets = GetPlatformNumberOfSockets (); + + TaskPtr.FuncAddress.PfApTaskI = EnablePstateHpcModeOnAps; + TaskPtr.DataTransfer.DataSizeInDwords = 2; + TaskPtr.DataTransfer.DataPtr = PlatformConfig; + TaskPtr.DataTransfer.DataTransferFlags = 0; + TaskPtr.ExeFlags = WAIT_FOR_CORE; + + for (Socket = 0; Socket < NumberOfSockets; Socket++) { + if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { + for (Core = 0; Core < NumberOfCores; Core++) { + if ((Socket != BscSocket) || (Core != BscCoreNum)) { + ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); + } + } + } + } + + EnablePstateHpcModeOnAps (PlatformConfig, StdHeader); + } + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * AP task to enable Pstate HPC mode + * + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + */ +VOID +STATIC +EnablePstateHpcModeOnAps ( + IN VOID *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PSTATE_HPC_MODE_FAMILY_SERVICES *FamilyServices; + + GetFeatureServicesOfCurrentCore (&PstateHpcModeFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); + FamilyServices->EnablePstateHpcMode (FamilyServices, + PlatformConfig, + StdHeader); + +} + + +CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePstateHpcMode = +{ + PstateHpcMode, + (CPU_FEAT_BEFORE_RELINQUISH_AP | CPU_FEAT_AFTER_RESUME_MTRR_SYNC), + IsPstateHpcModeFeatureSupported, + InitializePstateHpcModeFeature +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateHpcMode.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateHpcMode.h new file mode 100644 index 0000000..8995398 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateHpcMode.h @@ -0,0 +1,127 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA CPU Pstate HPC mode Functions declarations. + * + * Contains code that declares the AGESA CPU Pstate HPC mode related APIs + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Feature + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_PSTATE_HPC_MODE_H_ +#define _CPU_PSTATE_HPC_MODE_H_ + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ +AGESA_FORWARD_DECLARATION (PSTATE_HPC_MODE_FAMILY_SERVICES); + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to enable P-state HPC mode + * + * @param[in] PstateHpcModeService P-state HPC mode services. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @return Family specific error value. + * + */ +typedef AGESA_STATUS F_PSTATE_HPC_MODE_INIT ( + IN PSTATE_HPC_MODE_FAMILY_SERVICES *PstateHpcModeService, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_PSTATE_HPC_MODE_INIT *PF_PSTATE_HPC_MODE_INIT; + +/** + * Provide the interface to the P-state HPC mode Family Specific Services. + * + * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). + * Each supported Family must provide an implementation for all methods in this interface, even if the + * implementation is a CommonReturn(). + */ +struct _PSTATE_HPC_MODE_FAMILY_SERVICES { + UINT16 Revision; ///< Interface version + // Public Methods. + PF_PSTATE_HPC_MODE_INIT EnablePstateHpcMode; ///< Method: Family specific call to enable P-state HPC mode. +}; +/*---------------------------------------------------------------------------------------- + * F U N C T I O N S P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ + +#endif // _CPU_PSTATE_HPC_MODE_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateLeveling.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateLeveling.c new file mode 100644 index 0000000..76565a6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateLeveling.c @@ -0,0 +1,1123 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Pstate Leveling Function. + * + * Contains code to level the Pstates in a multi-socket system + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + *---------------------------------------------------------------------------- + */ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "OptionPstate.h" +#include "cpuLateInit.h" +#include "cpuRegisters.h" +#include "cpuPostInit.h" +#include "Ids.h" +#include "cpuFamilyTranslation.h" +#include "cpuPstateTables.h" +#include "cpuApicUtilities.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FEATURE_CPUPSTATELEVELING_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +extern OPTION_PSTATE_POST_CONFIGURATION OptionPstatePostConfiguration; // global user config record +extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +AGESA_STATUS +PutAllCoreInPState0 ( + IN OUT PSTATE_LEVELING *PStateBufferPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +StartPstateMsrModify ( + IN S_CPU_AMD_PSTATE *CpuAmdPState, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +PutCoreInPState0 ( + IN VOID *PStateBuffer, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PStateLevelingStub ( + IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PStateLevelingMain ( + IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +CorePstateRegModify ( + IN VOID *CpuAmdPState, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + *--------------------------------------------------------------------------------------- + * + * PStateLeveling + * + * Description: + * This function will populate the PStateBuffer, after doing the PState Leveling + * Note: This function should be called for every core in the system. + * + * Parameters: + * @param[in,out] *PStateStrucPtr + * @param[in] *StdHeader + * + * @retval AGESA_STATUS + * + *--------------------------------------------------------------------------------------- + **/ +AGESA_STATUS +PStateLeveling ( + IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_TESTPOINT (TpProcCpuEntryPstateLeveling, StdHeader); + return ((*(OptionPstatePostConfiguration.PstateLeveling)) (PStateStrucPtr, StdHeader)); + // Note: Split config struct into PEI/DXE halves. This one is PEI. +} + +/**-------------------------------------------------------------------------------------- + * + * PStateLevelingStub + * + * Description: + * This is the default routine for use when the PState option is NOT requested. + * The option install process will create and fill the transfer vector with + * the address of the proper routine (Main or Stub). The link optimizer will + * strip out of the .DLL the routine that is not used. + * + * Parameters: + * @param[in,out] *PStateStrucPtr + * @param[in] *StdHeader + * + * @retval AGESA_STATUS + * + *--------------------------------------------------------------------------------------- + **/ +AGESA_STATUS +PStateLevelingStub ( + IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return AGESA_UNSUPPORTED; +} + +/**-------------------------------------------------------------------------------------- + * + * PStateLevelingMain + * + * Description: + * This is the common routine for creating the ACPI information tables. + * + * Parameters: + * @param[in,out] *PStateStrucPtr + * @param[in] *StdHeader + * + * @retval AGESA_STATUS + * + *--------------------------------------------------------------------------------------- + **/ +AGESA_STATUS +PStateLevelingMain ( + IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 i; + UINT32 k; + UINT32 m; + UINT32 TotalIterations; + UINT32 LogicalSocketCount; + UINT32 TempVar_a; + UINT32 TempVar_b; + UINT32 TempVar_c; + UINT32 TempVar_d; + UINT32 TempVar_e; + UINT32 TempVar_f; + PCI_ADDR PciAddress; + + UINT32 TempFreqArray[20]; + UINT32 TempPowerArray[20]; + UINT32 TempIddValueArray[20]; + UINT32 TempIddDivArray[20]; + UINT32 TempSocketPiArray[20]; + UINT32 TempSwP0Array[MAX_SOCKETS_SUPPORTED]; + + BOOLEAN TempFlag1; + BOOLEAN TempFlag2; + BOOLEAN TempFlag3; + BOOLEAN TempFlag4; + BOOLEAN AllCoresHaveHtcCapEquToZeroFlag; + BOOLEAN AllCoreHaveMaxOnePStateFlag; + BOOLEAN PstateMaxValEquToPstateHtcLimitFlag; + BOOLEAN AtLeastOneCoreHasPstateHtcLimitEquToOneFlag; + BOOLEAN PstateMaxValMinusHtcPstateLimitLessThan2Flag; + PSTATE_LEVELING *PStateBufferPtr; + PSTATE_LEVELING *PStateBufferPtrTmp = NULL; + UINT32 MaxPstateInNode; + AGESA_STATUS Status; + + TempFlag1 = FALSE; + TempFlag2 = FALSE; + TempFlag3 = FALSE; + TempFlag4 = FALSE; + AllCoresHaveHtcCapEquToZeroFlag = FALSE; + AllCoreHaveMaxOnePStateFlag = FALSE; + PstateMaxValEquToPstateHtcLimitFlag = FALSE; + AtLeastOneCoreHasPstateHtcLimitEquToOneFlag = FALSE; + PstateMaxValMinusHtcPstateLimitLessThan2Flag = FALSE; + PStateBufferPtr = PStateStrucPtr->PStateLevelingStruc; + Status = AGESA_SUCCESS; + + if (PStateBufferPtr[0].SetPState0 == PSTATE_FLAG_1) { + PStateBufferPtr[0].AllCpusHaveIdenticalPStates = TRUE; + PStateBufferPtr[0].InitStruct = 1; + return AGESA_UNSUPPORTED; + } + + LogicalSocketCount = PStateStrucPtr->TotalSocketInSystem; + ASSERT (LogicalSocketCount <= MAX_SOCKETS_SUPPORTED); + + // This section of code will execute only for "core 0" i.e. BSP + // Read P-States of all the cores. + if (PStateBufferPtr[0].InitStruct == 0) { + // Determine 'software' P0 indices for each socket + for (i = 0; i < LogicalSocketCount; i++) { + CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); + TempSwP0Array[i] = (UINT32) (PStateBufferPtrTmp->PStateCoreStruct[0].NumberOfBoostedStates); + } + + // Check if core frequency and power are same across all sockets. + TempFlag1 = FALSE; + for (i = 1; i < LogicalSocketCount; i++) { + CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); + if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue != PStateBufferPtr[0].PStateCoreStruct[0].PStateMaxValue)) { + TempFlag1 = TRUE; + break; + } + MaxPstateInNode = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue; + for (k = TempSwP0Array[i]; k <= MaxPstateInNode; k++) { + if ((PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[k].CoreFreq != + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].CoreFreq) || + (PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[k].Power != + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].Power)) { + TempFlag1 = TRUE; + break; // Come out of the inner FOR loop + } + } + if (TempFlag1) { + break; // Come out of the outer FOR loop + } + } + + if (!TempFlag1) { + // No need to do pStateLeveling, or writing to pState MSR registers + // if all CPUs have Identical PStates + PStateBufferPtr[0].AllCpusHaveIdenticalPStates = TRUE; + PStateBufferPtr[0].InitStruct = 1; + PutAllCoreInPState0 (PStateBufferPtr, StdHeader); + return AGESA_UNSUPPORTED; + } else { + PStateBufferPtr[0].AllCpusHaveIdenticalPStates = FALSE; + } + + // 1_b) & 1_c) + TempFlag1 = FALSE; + TempFlag2 = FALSE; + for (i = 0; i < LogicalSocketCount; i++) { + CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); + if (PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue == TempSwP0Array[i]) { + TempFlag1 = TRUE; + } else { + TempFlag2 = TRUE; + } + if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcCapable == 0) { + TempFlag3 = TRUE; + } else { + TempFlag4 = TRUE; + } + + if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue - + PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) < 2) { + PstateMaxValMinusHtcPstateLimitLessThan2Flag = TRUE; + } + + if (PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue == + PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) { + PstateMaxValEquToPstateHtcLimitFlag = TRUE; + } + + if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit == 1) { + AtLeastOneCoreHasPstateHtcLimitEquToOneFlag = TRUE; + } + } + + // Do general setup of flags, that we may use later + // Implementation of (1_b) + if (TempFlag1 && TempFlag2) { + // + //Processors with only one enabled P-state (F3xDC[PstateMaxVal]=000b) cannot be mixed in a system with + //processors with more than one enabled P-state (F3xDC[PstateMaxVal]!=000b). + // + PStateBufferPtr[0].InitStruct = 1; + PStateBufferPtr[0].CreateAcpiTables = 0; + PutAllCoreInPState0 (PStateBufferPtr, StdHeader); + return AGESA_UNSUPPORTED; + } else if (TempFlag1 && !TempFlag2) { + // + //all processors have only 1 enabled P-state + // + AllCoreHaveMaxOnePStateFlag = TRUE; + PStateBufferPtr[0].OnlyOneEnabledPState = TRUE; + } + + // Processors with F3xE8[HTC_CAPABLE] = 1 can not be + // mixed in system with processors with F3xE8[HTC_CAPABLE] = 0. + if (TempFlag3 && TempFlag4) { + PStateBufferPtr[0].InitStruct = 1; + PStateBufferPtr[0].CreateAcpiTables = 0; + PutAllCoreInPState0 (PStateBufferPtr, StdHeader); + return AGESA_UNSUPPORTED; + } + + if (TempFlag3) { + // + //If code run to here means that all processors do not have HTC_CAPABLE. + // + AllCoresHaveHtcCapEquToZeroFlag = TRUE; + } + + //-------------------------------------------------------------------------------- + // S T E P - 2 + //-------------------------------------------------------------------------------- + // Now run the PState Leveling Algorithm which will create mixed CPU P-State + // Tables. + // Follow the algorithm in the latest BKDG + // ------------------------------------------------------------------------------- + // Match P0 CPU COF for all CPU cores to the lowest P0 CPU COF value in the + // coherent fabric, and match P0 power for all CPU cores to the highest P0 power + // value in the coherent fabric. + // 2_a) If all processors have only 1 enabled P-State BIOS must write the + // appropriate CpuFid value resulting from the matched CPU COF to all + // copies of MSRC001_0070[CpuFid], and exit the sequence (No further + // steps are executed) + //-------------------------------------------------------------------------------- + // Identify the lowest P0 Frequency and maximum P0 Power + TempVar_d = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSwP0Array[0]].CoreFreq; + TempVar_e = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSwP0Array[0]].Power; + TempVar_a = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSwP0Array[0]].IddValue; + TempVar_b = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSwP0Array[0]].IddDiv; + + for (i = 0; i < LogicalSocketCount; i++) { + CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); + if (TempVar_d > PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].CoreFreq) { + TempVar_d = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].CoreFreq; + } + + if (TempVar_e < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].Power) { + TempVar_e = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].Power; + TempVar_a = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].IddValue; + TempVar_b = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].IddDiv; + } + } + + // Set P0 Frequency and Power for all CPUs + for (i = 0; i < LogicalSocketCount; i++) { + CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].CoreFreq = TempVar_d; + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].Power = TempVar_e; + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].IddValue = TempVar_a; + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSwP0Array[i]].IddDiv = TempVar_b; + } + + // 2_a) + if (!AllCoreHaveMaxOnePStateFlag) { + //-------------------------------------------------------------------------- + // STEP - 3 + //-------------------------------------------------------------------------- + // Match the CPU COF and power for P-states used by HTC. Skip to step 4 + // is any processor reports F3xE8[HTC_Capable] = 0; + // 3_a) Set F3x64[HtcPstateLimit] = 001b and F3x68[StcPstateLimit] = 001b for + // processors with F3x64[HtcPstateLimit] = 000b. + // 3_b) Identify the lowest CPU COF for all processors in the P-state + // pointed to by [The Hardware Thermal Control (HTC) Register] + // F3x64[HtcPstateLimit] + // 3_c) Modify the CPU COF pointed to by [The Hardware Thermal Control + // (HTC) Register] F3x64[HtcPstateLimit] for all processors to the + // previously identified lowest CPU COF value. + // 3_d) Identify the highest power for all processors in the P-state + // pointed to by [The Hardware Thermal Control (HTC) Register] + // F3x64[HtcPstateLimit]. + // 3_e) Modify the power pointed to by [The Hardware Thermal Control (HTC) + // Register] F3x64[HtcPstateLimit] to the previously identified + // highest power value. + if (!AllCoresHaveHtcCapEquToZeroFlag) { + // 3_a) + for (i = 0; i < LogicalSocketCount; i++) { + CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); + if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit == 0) { + // To Be Done (Set Htc and Stc PstateLimit values) + // for this CPU (using PCI address space) + for (k = 0; k < (UINT8)GetPlatformNumberOfModules (); k++) { + if (GetPciAddress (StdHeader, PStateBufferPtrTmp->SocketNumber, k, &PciAddress, &Status)) { + // Set F3x64[HtcPstateLimit] = 001b + PciAddress.Address.Function = FUNC_3; + PciAddress.Address.Register = HARDWARE_THERMAL_CTRL_REG; + LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_d, StdHeader); + // Bits 30:28 + TempVar_d = (TempVar_d & 0x8FFFFFFF) | 0x10000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar_d, StdHeader); + + // Set F3x68[StcPstateLimit] = 001b + PciAddress.Address.Register = SOFTWARE_THERMAL_CTRL_REG; + LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_d, StdHeader); + // Bits 28:30 + TempVar_d = (TempVar_d & 0x8FFFFFFF) | 0x10000000; + LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar_d, StdHeader); + } + } + // Set LocalBuffer + PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit = 1; + if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue - 1) < 2) { + PstateMaxValMinusHtcPstateLimitLessThan2Flag = TRUE; + } + + if (PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue == 1) { + PstateMaxValEquToPstateHtcLimitFlag = TRUE; + } + } + + if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit == 1) { + AtLeastOneCoreHasPstateHtcLimitEquToOneFlag = TRUE; + } + } + + // 3_b) and 3_d) + TempVar_a = PStateBufferPtr[0].PStateCoreStruct[0].HtcPstateLimit; + TempVar_d = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].CoreFreq; + TempVar_e = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].Power; + TempVar_f = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].IddValue; + TempVar_c = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].IddDiv; + for (i = 0; i < LogicalSocketCount; i++) { + CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); + for (k = 0; k < 1; k++) { + TempVar_b = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit; + if (TempVar_d > PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].CoreFreq) { + TempVar_d = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].CoreFreq; + } + + if (TempVar_e < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].Power) { + TempVar_e = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].Power; + TempVar_f = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].IddValue; + TempVar_c = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].IddDiv; + } + } + } + + // 3_c) and 3_e) + for (i = 0; i < LogicalSocketCount; i++) { + CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); + TempVar_a = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit; + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].CoreFreq = TempVar_d; + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].Power = TempVar_e; + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].IddValue = TempVar_f; + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].IddDiv = TempVar_c; + } + } // if(AllCoresHaveHtcCapEquToZeroFlag) + + + //-------------------------------------------------------------------------- + // STEP - 4 + //-------------------------------------------------------------------------- + // Match the CPU COF and power for the lowest performance P-state: + // 4_a) If F3xDC[PstateMaxVal] = F3x64[HtcPstateLimit] for any processor, + // set PstateEn = 0 for all the P-states greater than + // F3x64[HtcPstateLimit] for all processors. + // 4_b) Identify the lowest CPU COF for all processors in the P-state + // pointed to by F3xDC[PstateMaxVal]. + // 4_c) Modify the CPU COF for all processors in the P-state pointed to by + // F3xDC[PstateMaxVal] to the previously identified lowest CPU COF + // value. + // 4_d) Identify the highest power for all processors in the P-state + // pointed to by F3xDC[PstateMaxVal]. + // 4_e) Modify the power for all processors in the P-state pointed to by + // F3xDC[PstateMaxVal] to the previously identified highest power + // value. + + // 4_a) + if (PstateMaxValEquToPstateHtcLimitFlag) { + for (i = 0; i < LogicalSocketCount; i++) { + CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); + TempVar_b = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit + 1; + for (k = TempVar_b; k <= PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue; k++) { + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0; + } + //-------------------------------------------------------------------------- + // STEP - 5 + //-------------------------------------------------------------------------- + // 5_a) Modify F3xDC[PstateMaxVal] to indicate the lowest performance + // P-state with PstateEn set for each processor (Step 4 can disable + // P-states pointed to by F3xDC[PstateMaxVal]) + + // Use this value of HtcPstateLimit to program the + // F3xDC[pStateMaxValue] + TempVar_e = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit; + TempVar_e <<= 8; + // Bits 10:8 + + for (m = 0; m < (UINT8)GetPlatformNumberOfModules (); m++) { + if (GetPciAddress (StdHeader, PStateBufferPtrTmp->SocketNumber, m, &PciAddress, &Status)) { + PciAddress.Address.Function = FUNC_3; + PciAddress.Address.Register = CLOCK_POWER_TIMING_CTRL2_REG; + LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_d, StdHeader); + TempVar_d = (TempVar_d & 0xFFFFF8FF) | TempVar_e; + LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar_d, StdHeader); + } + }//End of step 5 + } + }// End of 4_a) + + // 4_b) and 4_d) + TempVar_a = PStateBufferPtr[0].PStateCoreStruct[0].PStateMaxValue; + TempVar_d = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].CoreFreq; + TempVar_e = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].Power; + TempVar_f = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].IddValue; + TempVar_c = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].IddDiv; + + for (i = 0; i < LogicalSocketCount; i++) { + CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); + TempVar_b = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue; + if (TempVar_d > + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].CoreFreq) { + TempVar_d = + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].CoreFreq; + } + + if (TempVar_e < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].Power) { + TempVar_e = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].Power; + TempVar_f = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].IddValue; + TempVar_c = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].IddDiv; + } + } + + // 4_c) and 4_e) + for (i = 0; i < LogicalSocketCount; i++) { + CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); + TempVar_a = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue; + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].CoreFreq = TempVar_d; + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].Power = TempVar_e; + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].IddValue = TempVar_f; + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].IddDiv = TempVar_c; + } + + + //-------------------------------------------------------------------------- + // STEP - 6 + //-------------------------------------------------------------------------- + // Match the CPU COF and power for upper intermediate performance + // P-state(s): + // Upper intermediate PStates = PStates between (Not including) P0 and + // F3x64[HtcPstateLimit] + // 6_a) If F3x64[HtcPstateLimit] = 001b for any processor, set PstateEn = 0 + // for enabled upper intermediate P-states for all processors with + // F3x64[HtcPstateLimit] > 001b and skip the remaining actions for + // this numbered step. + // 6_b) Define each of the available upper intermediate P-states; for each + // processor concurrently evaluate the following loop; when any + // processor falls out of the loop (runs out of available upper + // intermediate Pstates) all other processors have their remaining + // upper intermediate P-states invalidated (PstateEn = 0); + // for (i = F3x64[HtcPstateLimit] - 1; i > 0; i--) + // - Identify the lowest CPU COF for P(i). + // - Identify the highest power for P(i). + // - Modify P(i) CPU COF for all processors to the previously + // identified lowest CPU COF value. + // - Modify P(i) power for all processors to the previously + // identified highest power value. + + // 6_a) + if (AtLeastOneCoreHasPstateHtcLimitEquToOneFlag) { + for (i = 0; i < LogicalSocketCount; i++) { + CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); + for (k = TempSwP0Array[i] + 1; k < (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit); k++) { + if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit > 1) { + // Make a function call to clear the + // structure values + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0; + } + } + } + } + // 6_b) + else { + // Identify Lowest Frequency and Highest Power + TotalIterations = 0; + TempFlag1 = TRUE; + + for (i = 0; i < LogicalSocketCount; i++) { + CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); + TempSocketPiArray[i] = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit - 1; + } + + do { + //For first socket, try to find a candidate + if (TempSocketPiArray[0] != TempSwP0Array[0]) { + while (PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].PStateEnable == 0) { + TempSocketPiArray[0] = TempSocketPiArray[0] - 1; + if (TempSocketPiArray[0] == TempSwP0Array[0]) { + TempFlag1 = FALSE; + break; + } + } + } else { + TempFlag1 = FALSE; + } + if (TempFlag1) { + TempFreqArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].CoreFreq; + TempPowerArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].Power; + TempIddValueArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].IddValue; + TempIddDivArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].IddDiv; + + //Try to find next candidate + for (i = 1; i < LogicalSocketCount; i++) { + CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); + if (TempSocketPiArray[i] != TempSwP0Array[i]) { + while (PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].PStateEnable == 0) { + TempSocketPiArray[i]--; + if (TempSocketPiArray[i] == TempSwP0Array[i]) { + TempFlag1 = FALSE; + break; + } + }//end while + } else { + TempFlag1 = FALSE; + } + + } //end for LogicalSocketCount + } + + if (TempFlag1) { + for (i = 0; i < LogicalSocketCount; i++) { + // + //Compare + // + CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); + if (TempFreqArray[TotalIterations] > PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq) { + TempFreqArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq; + } + + if (TempPowerArray[TotalIterations] < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power) { + TempPowerArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power; + TempIddValueArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddValue; + TempIddDivArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddDiv; + } + } + // Modify (Pi) CPU COF and Power for all the CPUs + for (i = 0; i < LogicalSocketCount; i++) { + CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq = TempFreqArray[TotalIterations]; + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power = TempPowerArray[TotalIterations]; + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddValue = TempIddValueArray[TotalIterations]; + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddDiv = TempIddDivArray[TotalIterations]; + TempSocketPiArray[i] = TempSocketPiArray[i] - 1; + } + } else { + for (i = 0; i < LogicalSocketCount; i++) { + CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); + for (m = TempSocketPiArray[i]; m > TempSwP0Array[i]; m--) { + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[m].PStateEnable = 0; + } + } + } + + TotalIterations++; + } while (TempFlag1); + + } // else + + //-------------------------------------------------------------------------- + // STEP - 7 + //-------------------------------------------------------------------------- + // Match the CPU COF and power for lower intermediate performance P - state(s) + // Lower Intermediate Pstates = Pstates between (not including) + // F3x64[HtcPstateLimit] and F3xDC[PstateMaxVal] + // 7_a) If F3xDC[PstateMaxVal] - F3x64[HtcPstateLimit] < 2 for any + // processor, set PstateEn = 0 for enabled lower intermediate P - states + // for all processors with (F3xDC[PstateMaxVal] - + // F3x64[HtcPstateLimit] > 1) and skip the remaining actions for this + // numbered step. + // 7_b) Define each of the available lower intermediate P-states; for each + // processor concurrently evaluate the following loop; when any + // processor falls out of the loop (runs out of available lower + // intermediate Pstates) all other processors have their remaining + // lower intermediate P-states invalidated (PstateEn = 0); + // for (i = F3xDC[PstateMaxVal]-1; i > F3x64[HtcPstateLimit]; i--) + // - Identify the lowest CPU COF for P-states between + // (not including) F3x64[HtcPstateLimit] and P(i). + // - Identify the highest power for P-states between + // (not including) F3x64[HtcPstateLimit] and P(i). + // - Modify P(i) CPU COF for all processors to the previously + // identified lowest CPU COF value. + // - Modify P(i) power for all processors to the previously + // identified highest power value. + + + // 7_a) + if (PstateMaxValMinusHtcPstateLimitLessThan2Flag) { + for (i = 0; i < LogicalSocketCount; i++) { + CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); + + for (k = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue - 1; + k > PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit; + k--) { + if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue - + PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) > 1) { + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0; + } + } + } + } + + // 7_b) + else { + // Identify Lowest Frequency and Highest Power + + TotalIterations = 0; + TempFlag1 = TRUE; + + for (i = 0; i < LogicalSocketCount; i++) { + CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); + TempSocketPiArray[i] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue - 1; + } + + do { + //For first socket, try to find a candidate + if (TempSocketPiArray[0] != PStateBufferPtr[0].PStateCoreStruct[0].HtcPstateLimit) { + while (PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].PStateEnable == 0) { + TempSocketPiArray[0] = TempSocketPiArray[0] - 1; + if (TempSocketPiArray[0] == PStateBufferPtr[0].PStateCoreStruct[0].HtcPstateLimit) { + TempFlag1 = FALSE; + break; + } + } + } else { + TempFlag1 = FALSE; + } + if (TempFlag1) { + TempFreqArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].CoreFreq; + TempPowerArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].Power; + TempIddValueArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].IddValue; + TempIddDivArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].IddDiv; + + //Try to find next candidate + for (i = 1; i < LogicalSocketCount; i++) { + CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); + if (TempSocketPiArray[i] != PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) { + while (PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].PStateEnable == 0) { + TempSocketPiArray[i]--; + if (TempSocketPiArray[i] == PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) { + TempFlag1 = FALSE; + break; + } + }//end while + } else { + TempFlag1 = FALSE; + } + } //end for LogicalSocketCount + } + + if (TempFlag1) { + for (i = 0; i < LogicalSocketCount; i++) { + // + //Compare + // + CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); + if (TempFreqArray[TotalIterations] > PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq) { + TempFreqArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq; + } + if (TempPowerArray[TotalIterations] < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power) { + TempPowerArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power; + TempIddValueArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddValue; + TempIddDivArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddDiv; + } + } + // Modify (Pi) CPU COF and Power for all the CPUs + for (i = 0; i < LogicalSocketCount; i++) { + CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq = TempFreqArray[TotalIterations]; + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power = TempPowerArray[TotalIterations]; + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddValue = TempIddValueArray[TotalIterations]; + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddDiv = TempIddDivArray[TotalIterations]; + TempSocketPiArray[i] = TempSocketPiArray[i] - 1; + } + } else { + for (i = 0; i < LogicalSocketCount; i++) { + CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader); + for (m = TempSocketPiArray[i]; m > PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit; m--) { + PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[m].PStateEnable = 0; + } + } + } + TotalIterations++; + } while (TempFlag1); + } // else + } // if(!AllCoreHaveMaxOnePStateFlag) + + PStateBufferPtr[0].InitStruct = 1; + } // CurrentCore + + + // Update the pState MSRs + // This can be done only by individual core + StartPstateMsrModify (PStateStrucPtr, StdHeader); + + //---------------------------------------------------------------------------------- + // STEP - 8 + //---------------------------------------------------------------------------------- + // Place all cores into a valid COF and VID configuration corresponding to an + // enabled P-state: + // 8_a) Select an enabled P-state != to the P-state pointed to by + // MSRC001_0063[CurPstate] for each core. + // 8_b) Transition all cores to the selected P-states by writing the Control value + // from the_PSS object corresponding to the selected P-state to + // MSRC001_0062[PstateCmd]. + // 8_c) Wait for all cores to report the Status value from the _PSS object + // corresponding to the selected P-state in MSRC001_0063[CurPstate]. + // + PutAllCoreInPState0 (PStateBufferPtr, StdHeader); + + return AGESA_SUCCESS; +} + + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/** + *--------------------------------------------------------------------------------------- + * + * PutAllCoreInPState0 + * + * Description: + * This function will put core pstate to p0. + * + * Parameters: + * @param[in,out] *PStateBufferPtr + * @param[in] *StdHeader + * + * @retval AGESA_STATUS + * + *--------------------------------------------------------------------------------------- + **/ +AGESA_STATUS +PutAllCoreInPState0 ( + IN OUT PSTATE_LEVELING *PStateBufferPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AP_TASK TaskPtr; + UINT32 BscSocket; + UINT32 Ignored; + UINT32 BscCoreNum; + UINT32 Core; + UINT32 Socket; + UINT32 NumberOfSockets; + UINT32 NumberOfCores; + AGESA_STATUS IgnoredSts; + + TaskPtr.FuncAddress.PfApTaskI = PutCoreInPState0; + TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PSTATE_LEVELING); + TaskPtr.ExeFlags = WAIT_FOR_CORE; + TaskPtr.DataTransfer.DataPtr = PStateBufferPtr; + TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY; + + IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); + NumberOfSockets = GetPlatformNumberOfSockets (); + + PutCoreInPState0 (PStateBufferPtr, StdHeader); + + for (Socket = 0; Socket < NumberOfSockets; Socket++) { + if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { + for (Core = 0; Core < NumberOfCores; Core++) { + if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCoreNum)) { + ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); + } + } + } + } + + return AGESA_SUCCESS; +} + +/** + *--------------------------------------------------------------------------------------- + * + * CorePstateRegModify + * + * Description: + * This function will setting the Pstate MSR to each APs base on Pstate Buffer. + * Note: This function should be called for every core in the system. + * + * Parameters: + * @param[in,out] *CpuAmdPState + * @param[in] *StdHeader + * + * @retval VOID + * + *--------------------------------------------------------------------------------------- + **/ +VOID +CorePstateRegModify ( + IN VOID *CpuAmdPState, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PSTATE_CPU_FAMILY_SERVICES *FamilySpecificServices; + FamilySpecificServices = NULL; + + GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (CONST VOID **)&FamilySpecificServices, StdHeader); + ASSERT (FamilySpecificServices != NULL) + FamilySpecificServices->SetPStateLevelReg (FamilySpecificServices, (S_CPU_AMD_PSTATE *) CpuAmdPState, StdHeader); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * This function will set msr on all cores of all nodes. + * + * @param[in] CpuAmdPState Pointer to S_CPU_AMD_PSTATE. + * @param[in] StdHeader Header for library and services. + * + * @retval AGESA_SUCCESS Always succeeds + * + */ +AGESA_STATUS +StartPstateMsrModify ( + IN S_CPU_AMD_PSTATE *CpuAmdPState, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AP_TASK TaskPtr; + UINT32 BscSocket; + UINT32 Ignored; + UINT32 BscCoreNum; + UINT32 Core; + UINT32 Socket; + UINT32 NumberOfSockets; + UINT32 NumberOfCores; + AGESA_STATUS IgnoredSts; + + TaskPtr.FuncAddress.PfApTaskI = CorePstateRegModify; + TaskPtr.DataTransfer.DataSizeInDwords = (UINT16) (CpuAmdPState->SizeOfBytes / 4 + 1); + TaskPtr.ExeFlags = WAIT_FOR_CORE; + TaskPtr.DataTransfer.DataPtr = CpuAmdPState; + TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY; + + IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); + NumberOfSockets = GetPlatformNumberOfSockets (); + + CorePstateRegModify (CpuAmdPState, StdHeader); + + for (Socket = 0; Socket < NumberOfSockets; Socket++) { + if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { + for (Core = 0; Core < NumberOfCores; Core++) { + if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCoreNum)) { + ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); + } + } + } + } + + return AGESA_SUCCESS; +} + + +/** + *--------------------------------------------------------------------------------------- + * + * CpuGetPStateLevelStructure + * + * Description: + * Based on the LogicalSocketNumber, this function will return a pointer + * point to the accurate offset of the PSTATE_LEVELING structure. + * + * Parameters: + * @param[in,out] *PStateBufferPtr + * @param[in] *CpuAmdPState + * @param[in] LogicalSocketNumber + * @param[in] *StdHeader + * + * @retval VOID + * + *--------------------------------------------------------------------------------------- + **/ +AGESA_STATUS +CpuGetPStateLevelStructure ( + OUT PSTATE_LEVELING **PStateBufferPtr, + IN S_CPU_AMD_PSTATE *CpuAmdPState, + IN UINT32 LogicalSocketNumber, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PSTATE_LEVELING *PStateBufferPtrTmp; + UINT32 i; + + if (LogicalSocketNumber > CpuAmdPState->TotalSocketInSystem) { + return AGESA_UNSUPPORTED; + } + + PStateBufferPtrTmp = CpuAmdPState->PStateLevelingStruc; + + for (i = 1; i <= LogicalSocketNumber; i++) { + PStateBufferPtrTmp = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtrTmp + ((UINTN) PStateBufferPtrTmp->PStateLevelingSizeOfBytes)); + } + + *PStateBufferPtr = PStateBufferPtrTmp; + + return AGESA_SUCCESS; +} + + +/** + *--------------------------------------------------------------------------------------- + * + * PutCoreInPState0 + * + * Description: + * This function will take the CPU core into P0 + * + * Parameters: + * @param[in] *PStateBuffer + * @param[in] *StdHeader + * + * @retval VOID + * + *--------------------------------------------------------------------------------------- + **/ +VOID +STATIC +PutCoreInPState0 ( + IN VOID *PStateBuffer, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + PSTATE_LEVELING *PStateBufferPtr; + + PStateBufferPtr = (PSTATE_LEVELING *) PStateBuffer; + + if ((PStateBufferPtr[0].SetPState0 == PSTATE_FLAG_1 ) || + (PStateBufferPtr[0].SetPState0 == PSTATE_FLAG_2)) { + return; + } + + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + + FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) FALSE, StdHeader); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateTables.c new file mode 100644 index 0000000..4776b13 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateTables.c @@ -0,0 +1,917 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD PSTATE, ACPI table related API functions. + * + * Contains code that generates the _PSS, _PCT, and other ACPI tables. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "OptionPstate.h" +#include "cpuLateInit.h" +#include "cpuRegisters.h" +#include "cpuFamilyTranslation.h" +#include "GeneralServices.h" +#include "cpuServices.h" +#include "heapManager.h" +#include "Ids.h" +#include "Filecode.h" +#include "GeneralServices.h" +#include "cpuPstateTables.h" +#include "cpuFeatures.h" +#include "cpuIoCstate.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +extern OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration; // global user config record +extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; +extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable; + +STATIC ACPI_TABLE_HEADER ROMDATA CpuSsdtHdrStruct = +{ + {'S','S','D','T'}, + 0, + 1, + 0, + {'A','M','D',' ',' ',' '}, + {'P','O','W','E','R','N','O','W'}, + 1, + {'A','M','D',' '}, + 1 +}; + + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +UINT32 +STATIC +CalAcpiTablesSize ( + IN S_CPU_AMD_PSTATE *AmdPstatePtr, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GenerateSsdtStub ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT VOID **SsdtPtr + ); + +UINT32 +CreateAcpiTablesStub ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PSTATE_LEVELING *PStateLevelingBuffer, + IN OUT VOID **SsdtPtr, + IN UINT8 LocalApicId, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +CreatePStateAcpiTables ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PSTATE_LEVELING *PStateLevelingBuffer, + IN OUT VOID **SsdtPtr, + IN UINT8 LocalApicId, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +CreateCStateAcpiTables ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PSTATE_LEVELING *PStateLevelingBuffer, + IN OUT VOID **SsdtPtr, + IN UINT8 LocalApicId, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GenerateSsdt ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT VOID **SsdtPtr + ); + +/** + *--------------------------------------------------------------------------------------- + * + * CalAcpiTablesSize + * + * Description: + * This function will calculate the size of ACPI PState tables + * + * Parameters: + * @param[in] *AmdPstatePtr + * @param[in] *PlatformConfig + * @param[in] *StdHeader + * + * @retval UINT32 + * + *--------------------------------------------------------------------------------------- + */ +UINT32 +STATIC +CalAcpiTablesSize ( + IN S_CPU_AMD_PSTATE *AmdPstatePtr, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 ScopeSize; + UINT32 CoreCount; + UINT32 SocketCount; + UINT32 MaxCoreNumberInCurrentSocket; + UINT32 MaxSocketNumberInSystem; + UINT32 MaxPstateNumberInCurrentCore; + UINT32 CstateAcpiObjSize; + PSTATE_LEVELING *PStateLevelingBufferStructPtr; + IO_CSTATE_FAMILY_SERVICES *IoCstateFamilyServices; + + ScopeSize = sizeof (ACPI_TABLE_HEADER); + CstateAcpiObjSize = 0; + IoCstateFamilyServices = NULL; + + PStateLevelingBufferStructPtr = AmdPstatePtr->PStateLevelingStruc; + MaxSocketNumberInSystem = AmdPstatePtr->TotalSocketInSystem; + + if (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader)) { + GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (CONST VOID **)&IoCstateFamilyServices, StdHeader); + // If we're supporting multiple families, only proceed when IO Cstate family services are available + if (IoCstateFamilyServices != NULL) { + CstateAcpiObjSize = IoCstateFamilyServices->GetAcpiCstObj (IoCstateFamilyServices, PlatformConfig, StdHeader); + } + } + + for (SocketCount = 0; SocketCount < MaxSocketNumberInSystem; SocketCount++) { + MaxCoreNumberInCurrentSocket = PStateLevelingBufferStructPtr->TotalCoresInNode; + for (CoreCount = 0; CoreCount < MaxCoreNumberInCurrentSocket; CoreCount++) { + MaxPstateNumberInCurrentCore = PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue + 1; + + ScopeSize += (SCOPE_STRUCT_SIZE - 1); // Scope size per core + ScopeSize += CstateAcpiObjSize; // C-State ACPI objects size per core + + // Add P-State ACPI Objects size per core + if ((PStateLevelingBufferStructPtr[0].CreateAcpiTables != 0) && (PlatformConfig->UserOptionPState)) { + ScopeSize += (PCT_STRUCT_SIZE + + PSS_HEADER_STRUCT_SIZE + + (MaxPstateNumberInCurrentCore * PSS_BODY_STRUCT_SIZE) + + XPSS_HEADER_STRUCT_SIZE + + (MaxPstateNumberInCurrentCore * XPSS_BODY_STRUCT_SIZE) + + PSD_HEADER_STRUCT_SIZE + + PSD_BODY_STRUCT_SIZE + + PPC_HEADER_BODY_STRUCT_SIZE); + } + } + ScopeSize += MaxCoreNumberInCurrentSocket; + PStateLevelingBufferStructPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateLevelingBufferStructPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES))); + } + AmdPstatePtr->SizeOfBytes = ScopeSize; + + return ScopeSize; +} + +/**-------------------------------------------------------------------------------------- + * + * GenerateSsdtStub + * + * Description: + * This is the default routine for use when both PState and CState option is NOT + * requested. The option install process will create and fill the transfer vector + * with the address of the proper routine (Main or Stub). The link optimizer will + * strip out of the .DLL the routine that is not used. + * + * Parameters: + * @param[in] StdHeader Handle to config for library and services + * @param[in] PlatformConfig Contains the power cap parameter + * @param[in,out] SsdtPtr ACPI SSDT table pointer + * + * @retval AGESA_STATUS + * + *--------------------------------------------------------------------------------------- + **/ +AGESA_STATUS +GenerateSsdtStub ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT VOID **SsdtPtr + ) +{ + return AGESA_UNSUPPORTED; +} + +/** + *--------------------------------------------------------------------------------------- + * + * GenerateSsdt + * + * Description: + * This function will populate the SSDT with ACPI P-States and C-States Objects, whenever + * necessary + * This function should be called only from BSP + * + * Parameters: + * @param[in] StdHeader Handle to config for library and services + * @param[in] PlatformConfig Contains the power cap parameter + * @param[in,out] SsdtPtr ACPI SSDT pointer + * + * @retval AGESA_STATUS + * + *--------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GenerateSsdt ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT VOID **SsdtPtr + ) +{ + UINT32 i; + UINT32 j; + UINT32 TempVar8_a; + UINT32 CurrSize; + UINT32 TempVar_a; + UINT32 TempVar_b; + UINT32 ScopeSize; + UINT32 CoreCount; + UINT32 SocketCount; + UINT32 MaxCorePerNode; + UINT8 LocalApicId; + UINT8 *IntermediatePtr; + AGESA_STATUS AgesaStatus; + LOCATE_HEAP_PTR LocateHeapParams; + ALLOCATE_HEAP_PARAMS AllocateHeapParams; + S_CPU_AMD_PSTATE *AmdPstatePtr; + PSTATE_LEVELING *PStateLevelingBufferStructPtr; + SCOPE *ScopeAcpiTablesStructPtr; + SCOPE *ScopeAcpiTablesStructPtrTemp; + + AGESA_TESTPOINT (TpProcCpuEntryPstate, StdHeader); + + ASSERT (IsBsp (StdHeader, &AgesaStatus)); + + // If P-State and C-State ACPI tables do not need to be generated, exit this routine + if ((!PlatformConfig->UserOptionPState) && (!IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader))) { + AgesaStatus = AGESA_UNSUPPORTED; + return AgesaStatus; + } + + // Initialize data variables + ScopeSize = 0; + CoreCount = 0; + LocalApicId = 0; + CurrSize = 0; + + // Locate P-State data buffer + LocateHeapParams.BufferHandle = AMD_PSTATE_DATA_BUFFER_HANDLE; + AGESA_TESTPOINT (TpProcCpuBeforeLocateSsdtBuffer, StdHeader); + if (HeapLocateBuffer (&LocateHeapParams, StdHeader) != AGESA_SUCCESS) { + return AGESA_ERROR; + } + AGESA_TESTPOINT (TpProcCpuAfterLocateSsdtBuffer, StdHeader); + + AmdPstatePtr = (S_CPU_AMD_PSTATE *) LocateHeapParams.BufferPtr; + PStateLevelingBufferStructPtr = AmdPstatePtr->PStateLevelingStruc; + + // Allocate rough buffer for AcpiTable, if SsdtPtr is NULL + if (*SsdtPtr == NULL) { + //Do not know the actual size.. pre-calculate it. + AllocateHeapParams.RequestedBufferSize = CalAcpiTablesSize (AmdPstatePtr, PlatformConfig, StdHeader); + AllocateHeapParams.BufferHandle = AMD_PSTATE_ACPI_BUFFER_HANDLE; + AllocateHeapParams.Persist = HEAP_SYSTEM_MEM; + + AGESA_TESTPOINT (TpProcCpuBeforeAllocateSsdtBuffer, StdHeader); + if (HeapAllocateBuffer (&AllocateHeapParams, StdHeader) != AGESA_SUCCESS) { + return AGESA_ERROR; + } + AGESA_TESTPOINT (TpProcCpuAfterAllocateSsdtBuffer, StdHeader); + *SsdtPtr = AllocateHeapParams.BufferPtr; + } + + IDS_HDT_CONSOLE (CPU_TRACE, " SSDT is created\n"); + + // Copy SSDT header into allocated buffer + LibAmdMemCopy (*SsdtPtr, (VOID *) &CpuSsdtHdrStruct, (UINTN) (sizeof (ACPI_TABLE_HEADER)), StdHeader); + IntermediatePtr = (UINT8 *) *SsdtPtr; + ScopeAcpiTablesStructPtr = (SCOPE *) &IntermediatePtr[sizeof (ACPI_TABLE_HEADER)]; + + SocketCount = AmdPstatePtr->TotalSocketInSystem; + + // Generate name scope and ACPI objects for every core in the system + for (i = 0; i < SocketCount; i++) { + MaxCorePerNode = PStateLevelingBufferStructPtr->TotalCoresInNode; + for (j = 0; j < MaxCorePerNode; j++) { + CoreCount++; + // Set Name Scope for CPU0, 1, 2, ..... n + // CPU0 to CPUn will name as C000 to Cnnn + // ----------------------------------------- + ScopeAcpiTablesStructPtr->ScopeOpcode = SCOPE_OPCODE; + // This value will be filled at the end of this function + // Since at this time, we don't know how many Pstates we + // would have + ScopeAcpiTablesStructPtr->ScopeLength = 0; + ScopeAcpiTablesStructPtr->ScopeValue1 = SCOPE_VALUE1; + ScopeAcpiTablesStructPtr->ScopeValue2 = SCOPE_VALUE2; + ScopeAcpiTablesStructPtr->ScopeNamePt1a__ = SCOPE_NAME__; + if (PlatformConfig->ProcessorScopeInSb) { + ScopeAcpiTablesStructPtr->ScopeNamePt1a_P = SCOPE_NAME_S; + ScopeAcpiTablesStructPtr->ScopeNamePt1a_R = SCOPE_NAME_B; + } else { + ScopeAcpiTablesStructPtr->ScopeNamePt1a_P = SCOPE_NAME_P; + ScopeAcpiTablesStructPtr->ScopeNamePt1a_R = SCOPE_NAME_R; + } + ScopeAcpiTablesStructPtr->ScopeNamePt1b__ = SCOPE_NAME__; + ASSERT ((PlatformConfig->ProcessorScopeName0 >= 'A') && (PlatformConfig->ProcessorScopeName0 <= 'Z')) + ASSERT (((PlatformConfig->ProcessorScopeName1 >= 'A') && (PlatformConfig->ProcessorScopeName1 <= 'Z')) || \ + ((PlatformConfig->ProcessorScopeName1 >= '0') && (PlatformConfig->ProcessorScopeName1 <= '9')) || \ + (PlatformConfig->ProcessorScopeName1 == '_')) + + ScopeAcpiTablesStructPtr->ScopeNamePt2a_C = PlatformConfig->ProcessorScopeName0; + ScopeAcpiTablesStructPtr->ScopeNamePt2a_P = PlatformConfig->ProcessorScopeName1; + + TempVar8_a = ((CoreCount - 1) >> 4) & 0x0F; + ScopeAcpiTablesStructPtr->ScopeNamePt2a_U = (UINT8) (SCOPE_NAME_0 + TempVar8_a); + + TempVar8_a = (CoreCount - 1) & 0x0F; + if (TempVar8_a < 0xA) { + ScopeAcpiTablesStructPtr->ScopeNamePt2a_0 = (UINT8) (SCOPE_NAME_0 + TempVar8_a); + } else { + ScopeAcpiTablesStructPtr->ScopeNamePt2a_0 = (UINT8) (SCOPE_NAME_A + TempVar8_a - 0xA); + } + // Increment and typecast the pointer + ScopeAcpiTablesStructPtrTemp = ScopeAcpiTablesStructPtr; + ScopeAcpiTablesStructPtrTemp++; + + // Get the Local Apic Id for each core + LocalApicId = PStateLevelingBufferStructPtr->PStateCoreStruct[0].LocalApicId + (UINT8) j; + + // Create P-State ACPI Objects + CurrSize += ((*(OptionPstateLateConfiguration.PstateFeature)) (PlatformConfig, PStateLevelingBufferStructPtr, (VOID *) &ScopeAcpiTablesStructPtrTemp, LocalApicId, StdHeader)); + + // Create C-State ACPI Objects + CurrSize += ((*(OptionPstateLateConfiguration.CstateFeature)) (PlatformConfig, PStateLevelingBufferStructPtr, (VOID *) &ScopeAcpiTablesStructPtrTemp, LocalApicId, StdHeader)); + + // Now update the SCOPE Length field + { + CurrSize += (SCOPE_STRUCT_SIZE - 1); + ScopeSize += CurrSize; + + TempVar_b = ((CurrSize << 4) & 0x0000FF00); + TempVar_b |= ((CurrSize & 0x0000000F) | 0x00000040); + TempVar_a = TempVar_b; + ScopeAcpiTablesStructPtr->ScopeLength = (UINT16) TempVar_a; + CurrSize = 0; + } + + ScopeAcpiTablesStructPtr = ScopeAcpiTablesStructPtrTemp; + } + //Calculate next node buffer address + PStateLevelingBufferStructPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateLevelingBufferStructPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES))); + } + //Update SSDT header Checksum + ((ACPI_TABLE_HEADER *) *SsdtPtr)->TableLength = (ScopeSize + CoreCount + sizeof (ACPI_TABLE_HEADER)); + ChecksumAcpiTable ((ACPI_TABLE_HEADER *) *SsdtPtr, StdHeader); + + return AGESA_SUCCESS; +} + +/**-------------------------------------------------------------------------------------- + * + * CreateAcpiTablesStub + * + * Description: + * This is the default routine for use when the P-State or C-State option is NOT + * requested. The option install process will create and fill the transfer vector + * with the address of the proper routine (Main or Stub). The link optimizer will + * strip out of the .DLL the routine that is not used. + * + * Parameters: + * @param[in] PlatformConfig Platform operational characteristics; power cap + * @param[in] PStateLevelingBuffer Buffer that contains P-State Leveling information + * @param[in,out] SsdtPtr ACPI SSDT table pointer + * @param[in] LocalApicId Local Apic Id + * @param[in] StdHeader Handle to config for library and services + * + * @retval Size of generated ACPI objects + * + *--------------------------------------------------------------------------------------- + **/ +UINT32 +CreateAcpiTablesStub ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PSTATE_LEVELING *PStateLevelingBuffer, + IN OUT VOID **SsdtPtr, + IN UINT8 LocalApicId, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return 0; +} + + +/**-------------------------------------------------------------------------------------- + * + * CreatePStateAcpiTables + * + * Description: + * This is the common routine for creating ACPI P-State objects + * + * Parameters: + * @param[in] PlatformConfig Platform operational characteristics; power cap + * @param[in] PStateLevelingBuffer Buffer that contains P-State Leveling information + * @param[in,out] SsdtPtr ACPI SSDT table pointer + * @param[in] LocalApicId Local Apic Id + * @param[in] StdHeader Handle to config for library and services + * + * @retval Size of generated ACPI P-States objects + * + *--------------------------------------------------------------------------------------- + **/ +UINT32 +CreatePStateAcpiTables ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PSTATE_LEVELING *PStateLevelingBuffer, + IN OUT VOID **SsdtPtr, + IN UINT8 LocalApicId, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 PstateCapLevelSupport; + UINT8 PStateMaxValueOnCurrentCore; + BOOLEAN PstateCapEnable; + BOOLEAN PstateCapLevelSupportDetermined; + BOOLEAN IsPsdDependent; + UINT32 k; + UINT32 TempVar_a; + UINT32 TempVar_b; + UINT32 TempVar_c; + UINT32 PstateCapInputMilliWatts; + UINT32 CurrSize; + UINT32 PstateCount; + UINT32 CoreCount1; + UINT32 TransAndBusMastLatency; + AGESA_STATUS IgnoredStatus; + PCI_ADDR PciAddress; + PCT_HEADER_BODY *pPctAcpiTables; + PSS_HEADER *pPssHeaderAcpiTables; + PSS_BODY *pPssBodyAcpiTables; + XPSS_HEADER *pXpssHeaderAcpiTables; + XPSS_BODY *pXpssBodyAcpiTables; + PSD_HEADER *pPsdHeaderAcpiTables; + PSD_BODY *pPsdBodyAcpiTables; + PPC_HEADER_BODY *pPpcAcpiTables; + PSTATE_CPU_FAMILY_SERVICES *FamilyServices; + + CurrSize = 0; + PstateCount = 0; + PstateCapEnable = FALSE; + PstateCapLevelSupport = DEFAULT_PERF_PRESENT_CAP; + PstateCapLevelSupportDetermined = TRUE; + PstateCapInputMilliWatts = PlatformConfig->PowerCeiling; + IsPsdDependent = !(PlatformConfig->ForcePstateIndependent); + TransAndBusMastLatency = 0; + + if ((PStateLevelingBuffer[0].CreateAcpiTables != 0) && (PlatformConfig->UserOptionPState)) { + pPctAcpiTables = (PCT_HEADER_BODY *) *SsdtPtr; + + //Check Pstate Capability + if (PstateCapInputMilliWatts != 0) { + PstateCapEnable = TRUE; + PstateCapLevelSupportDetermined = FALSE; + } + + PStateMaxValueOnCurrentCore = PStateLevelingBuffer->PStateCoreStruct[0].PStateMaxValue; + if (OptionPstateLateConfiguration.CfgPstatePct) { + // Set _PCT Table + // -------------- + pPctAcpiTables->NameOpcode = NAME_OPCODE; + pPctAcpiTables->PctName_a__ = PCT_NAME__; + pPctAcpiTables->PctName_a_P = PCT_NAME_P; + pPctAcpiTables->PctName_a_C = PCT_NAME_C; + pPctAcpiTables->PctName_a_T = PCT_NAME_T; + pPctAcpiTables->Value1 = PCT_VALUE1; + pPctAcpiTables->Value2 = PCT_VALUE2; + pPctAcpiTables->Value3 = PCT_VALUE3; + pPctAcpiTables->GenericRegDescription1 = GENERIC_REG_DESCRIPTION; + pPctAcpiTables->Length1 = PCT_LENGTH; + pPctAcpiTables->AddressSpaceId1 = PCT_ADDRESS_SPACE_ID; + pPctAcpiTables->RegisterBitWidth1 = PCT_REGISTER_BIT_WIDTH; + pPctAcpiTables->RegisterBitOffset1 = PCT_REGISTER_BIT_OFFSET; + pPctAcpiTables->Reserved1 = PCT_RESERVED; + pPctAcpiTables->ControlRegAddressLo = PCT_CONTROL_REG_LO; + pPctAcpiTables->ControlRegAddressHi = PCT_CONTROL_REG_HI; + pPctAcpiTables->Value4 = PCT_VALUE4; + pPctAcpiTables->Value5 = PCT_VALUE5; + pPctAcpiTables->GenericRegDescription2 = GENERIC_REG_DESCRIPTION; + pPctAcpiTables->Length2 = PCT_LENGTH; + pPctAcpiTables->AddressSpaceId2 = PCT_ADDRESS_SPACE_ID; + pPctAcpiTables->RegisterBitWidth2 = PCT_REGISTER_BIT_WIDTH; + pPctAcpiTables->RegisterBitOffset2 = PCT_REGISTER_BIT_OFFSET; + pPctAcpiTables->Reserved2 = PCT_RESERVED; + pPctAcpiTables->StatusRegAddressLo = PCT_STATUS_REG_LO; + pPctAcpiTables->StatusRegAddressHi = PCT_STATUS_REG_HI; + pPctAcpiTables->Value6 = PCT_VALUE6; + + // Increment and then typecast the pointer + pPctAcpiTables++; + CurrSize += PCT_STRUCT_SIZE; + + *SsdtPtr = pPctAcpiTables; + } // end of OptionPstateLateConfiguration.CfgPstatePct + + pPssHeaderAcpiTables = (PSS_HEADER *) pPctAcpiTables; + pPssBodyAcpiTables = (PSS_BODY *) pPctAcpiTables; + if (OptionPstateLateConfiguration.CfgPstatePss) { + // Set _PSS Header + // Note: Set pssLength and numOfItemsInPss later + //--------------------------------------------------- + pPssHeaderAcpiTables->NameOpcode = NAME_OPCODE; + pPssHeaderAcpiTables->PssName_a__ = PSS_NAME__; + pPssHeaderAcpiTables->PssName_a_P = PSS_NAME_P; + pPssHeaderAcpiTables->PssName_a_S = PSS_NAME_S; + pPssHeaderAcpiTables->PssName_b_S = PSS_NAME_S; + pPssHeaderAcpiTables->PkgOpcode = PACKAGE_OPCODE; + + pPssHeaderAcpiTables++; + pPssBodyAcpiTables = (PSS_BODY *) pPssHeaderAcpiTables; + // Restore the pPssHeaderAcpiTables + pPssHeaderAcpiTables--; + + // Set _PSS Body + //--------------- + PstateCount = 0; + + // Calculate PCI address for socket only + GetPciAddress (StdHeader, (UINT32) PStateLevelingBuffer->SocketNumber, 0, &PciAddress, &IgnoredStatus); + TransAndBusMastLatency = 0; + GetFeatureServicesOfSocket (&PstateFamilyServiceTable, (UINT32) PStateLevelingBuffer->SocketNumber, (CONST VOID **)&FamilyServices, StdHeader); + ASSERT (FamilyServices != NULL) + FamilyServices->GetPstateLatency ( FamilyServices, + PStateLevelingBuffer, + &PciAddress, + &TransAndBusMastLatency, + StdHeader); + + for (k = 0; k <= PStateMaxValueOnCurrentCore; k++) { + if (PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].PStateEnable != 0) { + pPssBodyAcpiTables->PkgOpcode = PACKAGE_OPCODE; + pPssBodyAcpiTables->PkgLength = PSS_PKG_LENGTH; + pPssBodyAcpiTables->NumOfElements = PSS_NUM_OF_ELEMENTS; + pPssBodyAcpiTables->DwordPrefixOpcode1 = DWORD_PREFIX_OPCODE; + pPssBodyAcpiTables->Frequency = + PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].CoreFreq; + pPssBodyAcpiTables->DwordPrefixOpcode2 = DWORD_PREFIX_OPCODE; + pPssBodyAcpiTables->Power = + PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].Power; + + if (PstateCapEnable && (!PstateCapLevelSupportDetermined) && (PstateCapInputMilliWatts >= pPssBodyAcpiTables->Power)) { + PstateCapLevelSupport = (UINT8) PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber; + PstateCapLevelSupportDetermined = TRUE; + } + + pPssBodyAcpiTables->DwordPrefixOpcode3 = DWORD_PREFIX_OPCODE; + pPssBodyAcpiTables->TransitionLatency = TransAndBusMastLatency; + pPssBodyAcpiTables->DwordPrefixOpcode4 = DWORD_PREFIX_OPCODE; + pPssBodyAcpiTables->BusMasterLatency = TransAndBusMastLatency; + pPssBodyAcpiTables->DwordPrefixOpcode5 = DWORD_PREFIX_OPCODE; + pPssBodyAcpiTables->Control = + PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber; + pPssBodyAcpiTables->DwordPrefixOpcode6 = DWORD_PREFIX_OPCODE; + pPssBodyAcpiTables->Status = + PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber; + + pPssBodyAcpiTables++; + PstateCount++; + } + } // for (k = 0; k < MPPSTATE_MAXIMUM_STATES; k++) + + if (PstateCapEnable && (!PstateCapLevelSupportDetermined)) { + PstateCapLevelSupport = PStateMaxValueOnCurrentCore; + } + + // Set _PSS Header again + // Now Set pssLength and numOfItemsInPss + //--------------------------------------- + TempVar_a = (PstateCount * PSS_BODY_STRUCT_SIZE) + 3; + TempVar_b = TempVar_a; + TempVar_c = ((TempVar_b << 4) & 0x0000FF00); + TempVar_c = TempVar_c | ((TempVar_b & 0x0000000F) | 0x00000040); + TempVar_a = (UINT16) TempVar_c; + + pPssHeaderAcpiTables->PssLength = (UINT16) TempVar_a; + pPssHeaderAcpiTables->NumOfItemsInPss = (UINT8) PstateCount; + CurrSize += (PSS_HEADER_STRUCT_SIZE + (PstateCount * PSS_BODY_STRUCT_SIZE)); + + *SsdtPtr = pPssBodyAcpiTables; + } // end of PSS Body if OptionPstateLateConfiguration.CfgPstatePss + + // Set XPSS Table + //--------------- + // Typecast the pointer + pXpssHeaderAcpiTables = (XPSS_HEADER *) pPssBodyAcpiTables; + pXpssBodyAcpiTables = (XPSS_BODY *) pPssBodyAcpiTables; + if (OptionPstateLateConfiguration.CfgPstateXpss) { + // Set XPSS Header + // Note: Set the pssLength and numOfItemsInPss later + //--------------------------------------------------- + pXpssHeaderAcpiTables->NameOpcode = NAME_OPCODE; + pXpssHeaderAcpiTables->XpssName_a_X = PSS_NAME_X; + pXpssHeaderAcpiTables->XpssName_a_P = PSS_NAME_P; + pXpssHeaderAcpiTables->XpssName_a_S = PSS_NAME_S; + pXpssHeaderAcpiTables->XpssName_b_S = PSS_NAME_S; + pXpssHeaderAcpiTables->PkgOpcode = PACKAGE_OPCODE; + + // Increment and then typecast the pointer + pXpssHeaderAcpiTables++; + pXpssBodyAcpiTables = (XPSS_BODY *) pXpssHeaderAcpiTables; + // Restore the pXpssHeaderAcpiTables + pXpssHeaderAcpiTables--; + + // Set XPSS Body + //--------------- + for (k = 0; k <= PStateMaxValueOnCurrentCore; k++) { + if (PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].PStateEnable != 0) { + pXpssBodyAcpiTables->PkgOpcode = PACKAGE_OPCODE; + pXpssBodyAcpiTables->PkgLength = XPSS_PKG_LENGTH; + pXpssBodyAcpiTables->NumOfElements = XPSS_NUM_OF_ELEMENTS; + pXpssBodyAcpiTables->XpssValueTbd = 04; + pXpssBodyAcpiTables->DwordPrefixOpcode1 = DWORD_PREFIX_OPCODE; + pXpssBodyAcpiTables->Frequency = + PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].CoreFreq; + pXpssBodyAcpiTables->DwordPrefixOpcode2 = DWORD_PREFIX_OPCODE; + pXpssBodyAcpiTables->Power = + PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].Power; + pXpssBodyAcpiTables->DwordPrefixOpcode3 = DWORD_PREFIX_OPCODE; + pXpssBodyAcpiTables->TransitionLatency = TransAndBusMastLatency; + pXpssBodyAcpiTables->DwordPrefixOpcode4 = DWORD_PREFIX_OPCODE; + pXpssBodyAcpiTables->BusMasterLatency = TransAndBusMastLatency; + pXpssBodyAcpiTables->ControlBuffer = XPSS_ACPI_BUFFER; + pXpssBodyAcpiTables->ControlLo = + PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber; + pXpssBodyAcpiTables->ControlHi = 0; + pXpssBodyAcpiTables->StatusBuffer = XPSS_ACPI_BUFFER; + pXpssBodyAcpiTables->StatusLo = + PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber; + pXpssBodyAcpiTables->StatusHi = 0; + pXpssBodyAcpiTables->ControlMaskBuffer = XPSS_ACPI_BUFFER; + pXpssBodyAcpiTables->ControlMaskLo = 0; + pXpssBodyAcpiTables->ControlMaskHi = 0; + pXpssBodyAcpiTables->StatusMaskBuffer = XPSS_ACPI_BUFFER; + pXpssBodyAcpiTables->StatusMaskLo = 0; + pXpssBodyAcpiTables->StatusMaskHi = 0; + + pXpssBodyAcpiTables++; + } + } // for (k = 0; k < MPPSTATE_MAXIMUM_STATES; k++) + + // Set XPSS Header again + // Now set pssLength and numOfItemsInPss + //--------------------------------------- + TempVar_a = (PstateCount * XPSS_BODY_STRUCT_SIZE) + 3; + TempVar_b = TempVar_a; + TempVar_c = ((TempVar_b << 4) & 0x0000FF00); + TempVar_c = TempVar_c | ((TempVar_b & 0x0000000F) | 0x00000040); + TempVar_a = (UINT16) TempVar_c; + + pXpssHeaderAcpiTables->XpssLength = (UINT16) TempVar_a; + pXpssHeaderAcpiTables->NumOfItemsInXpss = (UINT8) PstateCount; + CurrSize += (XPSS_HEADER_STRUCT_SIZE + (PstateCount * XPSS_BODY_STRUCT_SIZE)); + + *SsdtPtr = pXpssBodyAcpiTables; + } //end of XPSS Body OptionPstateLateConfiguration.CfgPstateXpss + + // Set _PSD Table + //--------------- + // Typecast the pointer + pPsdHeaderAcpiTables = (PSD_HEADER *) pXpssBodyAcpiTables; + pPsdBodyAcpiTables = (PSD_BODY *) pXpssBodyAcpiTables; + // Get Total Cores Per Node + if (GetActiveCoresInGivenSocket ((UINT32) PStateLevelingBuffer->SocketNumber, &CoreCount1, StdHeader)) { + GetFeatureServicesOfSocket (&PstateFamilyServiceTable, (UINT32) PStateLevelingBuffer->SocketNumber, (CONST VOID **)&FamilyServices, StdHeader); + ASSERT (FamilyServices != NULL) + if ((CoreCount1 != 1) && (OptionPstateLateConfiguration.CfgPstatePsd) && + FamilyServices->IsPstatePsdNeeded (FamilyServices, PlatformConfig, StdHeader)) { + // Set _PSD Header + //---------------- + pPsdHeaderAcpiTables->NameOpcode = NAME_OPCODE; + pPsdHeaderAcpiTables->PkgOpcode = PACKAGE_OPCODE; + pPsdHeaderAcpiTables->PsdLength = PSD_HEADER_LENGTH; + pPsdHeaderAcpiTables->Value1 = PSD_VALUE1; + pPsdHeaderAcpiTables->PsdName_a__ = PSD_NAME__; + pPsdHeaderAcpiTables->PsdName_a_P = PSD_NAME_P; + pPsdHeaderAcpiTables->PsdName_a_S = PSD_NAME_S; + pPsdHeaderAcpiTables->PsdName_a_D = PSD_NAME_D; + + // Typecast the pointer + pPsdHeaderAcpiTables++; + CurrSize += PSD_HEADER_STRUCT_SIZE; + pPsdBodyAcpiTables = (PSD_BODY *) pPsdHeaderAcpiTables; + + pPsdHeaderAcpiTables--; + // Set _PSD Body + //-------------- + pPsdBodyAcpiTables->PkgOpcode = PACKAGE_OPCODE; + pPsdBodyAcpiTables->PkgLength = PSD_PKG_LENGTH; + pPsdBodyAcpiTables->NumOfEntries = NUM_OF_ENTRIES; + pPsdBodyAcpiTables->BytePrefixOpcode1 = BYTE_PREFIX_OPCODE; + pPsdBodyAcpiTables->PsdNumOfEntries = PSD_NUM_OF_ENTRIES; + pPsdBodyAcpiTables->BytePrefixOpcode2 = BYTE_PREFIX_OPCODE; + pPsdBodyAcpiTables->PsdRevision = PSD_REVISION; + pPsdBodyAcpiTables->DwordPrefixOpcode1 = DWORD_PREFIX_OPCODE; + + IsPsdDependent = FamilyServices->IsPstatePsdDependent (FamilyServices, PlatformConfig, StdHeader); + + if (IsPsdDependent) { + pPsdBodyAcpiTables->DependencyDomain = PSD_DEPENDENCY_DOMAIN; + pPsdBodyAcpiTables->CoordinationType = PSD_COORDINATION_TYPE_SW_ALL; + pPsdBodyAcpiTables->NumOfProcessors = CoreCount1; + } else { + switch (GetComputeUnitMapping (StdHeader)) { + case AllCoresMapping: + // All cores are in their own compute unit. + pPsdBodyAcpiTables->DependencyDomain = LocalApicId; + pPsdBodyAcpiTables->CoordinationType = PSD_COORDINATION_TYPE_SW_ANY; + pPsdBodyAcpiTables->NumOfProcessors = PSD_NUM_OF_PROCESSORS; + break; + case EvenCoresMapping: + // Cores are paired in compute units. + pPsdBodyAcpiTables->DependencyDomain = (LocalApicId >> 1) & PSD_DOMAIN_COMPUTE_UNIT_MASK; + pPsdBodyAcpiTables->CoordinationType = PSD_COORDINATION_TYPE_HW_ALL; + pPsdBodyAcpiTables->NumOfProcessors = PSD_CORE_NUM_PER_COMPUTE_UNIT; + break; + default: + ASSERT (FALSE); + } + } + pPsdBodyAcpiTables->DwordPrefixOpcode2 = DWORD_PREFIX_OPCODE; + pPsdBodyAcpiTables->DwordPrefixOpcode3 = DWORD_PREFIX_OPCODE; + + pPsdBodyAcpiTables++; + *SsdtPtr = pPsdBodyAcpiTables; + CurrSize += PSD_BODY_STRUCT_SIZE; + } + }// end of PSD Body if (CoreCount1 != 1) || (OptionPstateLateConfiguration.CfgPstatePsd) + // Typecast the pointer + + pPpcAcpiTables = (PPC_HEADER_BODY *) pPsdBodyAcpiTables; + + // Set _PPC Table + //--------------- + if (OptionPstateLateConfiguration.CfgPstatePpc) { + // Name (PPCV, value) + pPpcAcpiTables->NameOpcode = NAME_OPCODE; + pPpcAcpiTables->PpcName_a_P = PPC_NAME_P; + pPpcAcpiTables->PpcName_b_P = PPC_NAME_P; + pPpcAcpiTables->PpcName_a_C = PPC_NAME_C; + pPpcAcpiTables->PpcName_a_V = PPC_NAME_V; + pPpcAcpiTables->Value1 = PPC_VALUE1; + pPpcAcpiTables->DefaultPerfPresentCap = PstateCapLevelSupport; + // Method (_PPC) { return (PPCV) } + pPpcAcpiTables->MethodOpcode = METHOD_OPCODE; + pPpcAcpiTables->PpcLength = PPC_METHOD_LENGTH; + pPpcAcpiTables->PpcName_a__ = PPC_NAME__; + pPpcAcpiTables->PpcName_c_P = PPC_NAME_P; + pPpcAcpiTables->PpcName_d_P = PPC_NAME_P; + pPpcAcpiTables->PpcName_b_C = PPC_NAME_C; + pPpcAcpiTables->MethodFlags = PPC_METHOD_FLAGS; + pPpcAcpiTables->ReturnOpcode = RETURN_OPCODE; + pPpcAcpiTables->PpcName_e_P = PPC_NAME_P; + pPpcAcpiTables->PpcName_f_P = PPC_NAME_P; + pPpcAcpiTables->PpcName_c_C = PPC_NAME_C; + pPpcAcpiTables->PpcName_b_V = PPC_NAME_V; + + CurrSize += PPC_HEADER_BODY_STRUCT_SIZE; + // Increment and typecast the pointer + pPpcAcpiTables++; + *SsdtPtr = pPpcAcpiTables; + }// end of OptionPstateLateConfiguration.CfgPstatePpc + } + return CurrSize; +} + +/**-------------------------------------------------------------------------------------- + * + * CreateCStateAcpiTables + * + * Description: + * This is the common routine for creating ACPI C-State objects + * + * Parameters: + * @param[in] PlatformConfig Platform operational characteristics; power cap + * @param[in] PStateLevelingBuffer Buffer that contains P-State Leveling information + * @param[in,out] SsdtPtr ACPI SSDT table pointer + * @param[in] LocalApicId Local Apic Id + * @param[in] StdHeader Handle to config for library and services + * + * @retval Size of ACPI C-States objects generated + * + *--------------------------------------------------------------------------------------- + **/ +UINT32 +CreateCStateAcpiTables ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PSTATE_LEVELING *PStateLevelingBuffer, + IN OUT VOID **SsdtPtr, + IN UINT8 LocalApicId, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 ObjSize; + IO_CSTATE_FAMILY_SERVICES *IoCstateFamilyServices; + + ObjSize = 0; + + if (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader)) { + GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (CONST VOID **)&IoCstateFamilyServices, StdHeader); + // If we're supporting multiple families, only proceed when IO Cstate family services are available + if (IoCstateFamilyServices != NULL) { + IoCstateFamilyServices->CreateAcpiCstObj (IoCstateFamilyServices, LocalApicId, SsdtPtr, StdHeader); + ObjSize = IoCstateFamilyServices->GetAcpiCstObj (IoCstateFamilyServices, PlatformConfig, StdHeader); + } + } + return ObjSize; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateTables.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateTables.h new file mode 100644 index 0000000..09120fa --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuPstateTables.h @@ -0,0 +1,357 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA CPU Pstate Table Functions declarations. + * + * Contains code that declares the AGESA CPU _PSS related APIs + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Feature + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_PSTATE_TABLES_H_ +#define _CPU_PSTATE_TABLES_H_ + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ +// Forward declaration needed for multi-structure mutual references +AGESA_FORWARD_DECLARATION (PSTATE_CPU_FAMILY_SERVICES); + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +/// P-state structure for each state +typedef struct { + IN OUT UINT32 PStateEnable; ///< Pstate enable + IN OUT UINT32 CoreFreq; ///< MHz + IN OUT UINT32 Power; ///< milliWatts + IN OUT UINT32 IddValue; ///< Current value field + IN OUT UINT32 IddDiv; ///< Current divisor field + IN OUT UINT32 SwPstateNumber; ///< Software P-state number +} S_PSTATE_VALUES; + +/// P-state structure for each core +typedef struct { + IN OUT UINT8 PStateMaxValue; ///< Max p-state number in this core + IN OUT UINT8 HtcPstateLimit; ///< Htc limit + IN OUT UINT8 HtcCapable; ///< Htc capable + IN OUT UINT8 LocalApicId; ///< Local Apic Id + IN OUT UINT8 NumberOfBoostedStates; ///< Number of boost P-states + IN OUT S_PSTATE_VALUES PStateStruct[1]; ///< P state struc +} S_PSTATE; + +/// P-state structure for each node +typedef struct { + IN UINT8 SetPState0; ///< If value = 0x55 (Don't set PState0) + IN UINT8 TotalCoresInNode; ///< core number per node + IN UINT16 PStateLevelingSizeOfBytes; ///< Size + IN BOOLEAN OnlyOneEnabledPState; ///< Only P0 + IN UINT8 InitStruct; ///< Init struc + IN BOOLEAN AllCpusHaveIdenticalPStates; ///< Have Identical p state + IN UINT8 CreateAcpiTables; ///< Create table flag + IN UINT8 SocketNumber; ///< Physical socket number of this socket + IN UINT8 Reserved[2]; ///< Reserved. + IN OUT S_PSTATE PStateCoreStruct[1]; ///< P state core struc +} PSTATE_LEVELING; + +/// P-state structure for whole system +typedef struct { + IN OUT UINT32 TotalSocketInSystem; ///< Total node number in system + IN OUT UINT32 SizeOfBytes; ///< Structure size + IN OUT PSTATE_LEVELING PStateLevelingStruc[1]; ///< P state level structure +} S_CPU_AMD_PSTATE; + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to check if PSD need to be generated. + * + * @param[in] PstateCpuFamilyServices Pstate CPU services. + * @param[in,out] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE PSD need to be generated + * @retval FALSE PSD does NOT need to be generated + * + */ +typedef BOOLEAN F_PSTATE_PSD_IS_NEEDED ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN OUT PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_PSTATE_PSD_IS_NEEDED *PF_PSTATE_PSD_IS_NEEDED; + + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to check if Pstate PSD is dependent. + * + * @param[in] PstateCpuFamilyServices Pstate CPU services. + * @param[in,out] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE PSD is dependent. + * @retval FALSE PSD is independent. + * + */ +typedef BOOLEAN F_PSTATE_PSD_IS_DEPENDENT ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN OUT PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_PSTATE_PSD_IS_DEPENDENT *PF_PSTATE_PSD_IS_DEPENDENT; + +/** + * Family specific call to set core TscFreqSel. + * + * @param[in] PstateCpuFamilyServices Pstate CPU services. + * @param[in] StdHeader Config Handle for library, services. + * + */ +typedef VOID F_PSTATE_SET_TSC_FREQ_SEL ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_PSTATE_SET_TSC_FREQ_SEL *PF_PSTATE_SET_TSC_FREQ_SEL; + +/** + * Family specific call to get CPU pstate transition latency for current socket. + * + * @param[in] PstateCpuFamilyServices Pstate CPU services. + * @param[in] PStateLevelingBufferStructPtr Pstate row data buffer pointer. + * @param[in] PciAddress Pci address struct. + * @param[out] TransitionLatency Pstate Transition latency result. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +typedef AGESA_STATUS F_CPU_PSTATE_TRANSITION_LATENCY ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN PSTATE_LEVELING *PStateLevelingBufferStructPtr, + IN PCI_ADDR *PciAddress, + OUT UINT32 *TransitionLatency, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_CPU_PSTATE_TRANSITION_LATENCY *PF_CPU_PSTATE_TRANSITION_LATENCY; + +/** + * Family specific call to get the desired P-state's frequency in megahertz. + * + * @param[in] PstateCpuFamilyServices Pstate CPU services. + * @param[in] StateNumber P-state number. + * @param[out] PowerInMw P-state frequency in megahertz. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +typedef AGESA_STATUS F_CPU_GET_PSTATE_FREQ ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN UINT8 StateNumber, + OUT UINT32 *FreqInMHz, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_CPU_GET_PSTATE_FREQ *PF_CPU_GET_PSTATE_FREQ; + +/** + * Family specific call to set the system wide P-state settings on the current core. + * + * @param[in] PstateCpuFamilyServices Pstate CPU services. + * @param[in] CpuAmdPState The current core's P-state data. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +typedef AGESA_STATUS F_CPU_SET_PSTATE_LEVELING_REG ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN S_CPU_AMD_PSTATE *CpuAmdPState, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_CPU_SET_PSTATE_LEVELING_REG *PF_CPU_SET_PSTATE_LEVELING_REG; + +/** + * Family specific call to get the desired P-state's rated power in milliwatts. + * + * @param[in] PstateCpuFamilyServices Pstate CPU services. + * @param[in] StateNumber P-state number. + * @param[out] PowerInMw P-state power in milliwatts. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +typedef AGESA_STATUS F_CPU_GET_PSTATE_POWER ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN UINT8 StateNumber, + OUT UINT32 *PowerInMw, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_CPU_GET_PSTATE_POWER *PF_CPU_GET_PSTATE_POWER; + +/** + * Family specific call to get CPU Pstate Max State. + * + * @param[in] PstateCpuFamilyServices Pstate CPU services. + * @param[out] MaxPStateNumber The max hw pstate value on the current socket. + * @param[out] NumberOfBoostStates The number of boosted P-states on the current socket. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +typedef AGESA_STATUS F_CPU_GET_PSTATE_MAX_STATE ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + OUT UINT32 *MaxPStateNumber, + OUT UINT8 *NumberOfBoostStates, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_CPU_GET_PSTATE_MAX_STATE *PF_CPU_GET_PSTATE_MAX_STATE; + +/** + * Family specific call to get CPU pstate register information. + * + * @param[in] PstateCpuFamilyServices Pstate CPU services. + * @param[in] PState Input hardware Pstate number for query. + * @param[out] PStateEnabled Boolean flag return pstate enable. + * @param[in,out] IddVal Pstate current value. + * @param[in,out] IddDiv Pstate current divisor. + * @param[out] SwPstateNumber Software P-state number. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +typedef AGESA_STATUS F_CPU_GET_PSTATE_REGISTER_INFO ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN UINT32 PState, + OUT BOOLEAN *PStateEnabled, + IN OUT UINT32 *IddVal, + IN OUT UINT32 *IddDiv, + OUT UINT32 *SwPstateNumber, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_CPU_GET_PSTATE_REGISTER_INFO *PF_CPU_GET_PSTATE_REGISTER_INFO; + +/** + * Provide the interface to the Pstate dependent Family Specific Services. + * + * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). + * Each supported Family must provide an implementation for all methods in this interface, even if the + * implementation is a CommonReturn(). + */ +struct _PSTATE_CPU_FAMILY_SERVICES { + UINT16 Revision; ///< Interface version + // Public Methods. + PF_PSTATE_PSD_IS_NEEDED IsPstatePsdNeeded; ///< Method: Family specific call to check if PSD need to be generated. + PF_PSTATE_PSD_IS_DEPENDENT IsPstatePsdDependent; ///< Method: Family specific call to check if PSD is dependent. + PF_PSTATE_SET_TSC_FREQ_SEL CpuSetTscFreqSel; ///< Method: Family specific call to set core TscFreqSel. + PF_CPU_PSTATE_TRANSITION_LATENCY GetPstateLatency; ///< Method: Family specific call to get pstate transition latency. + PF_CPU_GET_PSTATE_FREQ GetPstateFrequency; ///< Method: Family specific call to get the desired P-state's frequency in megahertz. + PF_CPU_SET_PSTATE_LEVELING_REG SetPStateLevelReg; ///< Method: Family specific call to set the system wide P-state settings on the current core. + PF_CPU_GET_PSTATE_POWER GetPstatePower; ///< Method: Family specific call to get the desired P-state's rated power in milliwatts. + PF_CPU_GET_PSTATE_MAX_STATE GetPstateMaxState; ///< Method: Family specific call to get pstate max state number. + PF_CPU_GET_PSTATE_REGISTER_INFO GetPstateRegisterInfo; ///< Method: Family specific call to get pstate register information. +}; + + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N S P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +PStateGatherData ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PStateLeveling ( + IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +CpuGetPStateLevelStructure ( + OUT PSTATE_LEVELING **PStateBufferPtr, + IN S_CPU_AMD_PSTATE *CpuAmdPState, + IN UINT32 LogicalSocketNumber, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif // _CPU_PSTATE_TABLES_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSlit.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSlit.c new file mode 100644 index 0000000..e26487d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSlit.c @@ -0,0 +1,423 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD SLIT, ACPI table related API functions. + * + * Contains code that generates the SLIT table + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------- + * This file provides functions, that will generate SLIT tables + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "OptionSlit.h" +#include "heapManager.h" +#include "cpuLateInit.h" +#include "cpuRegisters.h" +#include "Ids.h" +#include "cpuFeatures.h" +#include "cpuFamilyTranslation.h" +#include "cpuL3Features.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FEATURE_CPUSLIT_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern OPTION_SLIT_CONFIGURATION OptionSlitConfiguration; // global user config record + +STATIC ACPI_TABLE_HEADER ROMDATA CpuSlitHdrStruct = +{ + {'S','L','I','T'}, + 0, + 1, + 0, + {'A','M','D',' ',' ',' '}, + {'A','G','E','S','A',' ',' ',' '}, + 1, + {'A','M','D',' '}, + 1 +}; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +AcpiSlitHBufferFind ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN UINT8 **SocketTopologyPtr + ); + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GetAcpiSlitStub ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT VOID **SlitPtr + ); + +AGESA_STATUS +GetAcpiSlitMain ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT VOID **SlitPtr + ); + +AGESA_STATUS +ReleaseSlitBufferStub ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +ReleaseSlitBuffer ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +extern CPU_FAMILY_SUPPORT_TABLE L3FeatureFamilyServiceTable; + +/*---------------------------------------------------------------------------------------*/ +/** + * + * This function generates a complete SLIT table into a memory buffer. + * After completion, this table must be set by the system BIOS into its + * internal ACPI namespace, and linked into the RSDT/XSDT + * + * @param[in, out] StdHeader Standard Head Pointer + * @param[in] PlatformConfig Config handle for platform specific information + * @param[in, out] SlitPtr Point to Slit Struct including buffer address and length + * + * @retval UINT32 AGESA_STATUS + */ +AGESA_STATUS +CreateAcpiSlit ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT VOID **SlitPtr + ) +{ + AGESA_TESTPOINT (TpProcCpuEntrySlit, StdHeader); + return ((*(OptionSlitConfiguration.SlitFeature)) (StdHeader, PlatformConfig, SlitPtr)); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * + * This is the default routine for use when the SLIT option is NOT requested. + * + * The option install process will create and fill the transfer vector with + * the address of the proper routine (Main or Stub). The link optimizer will + * strip out of the .DLL the routine that is not used. + * + * @param[in, out] StdHeader Standard Head Pointer + * @param[in] PlatformConfig Config handle for platform specific information + * @param[in, out] SlitPtr Point to Slit Struct including buffer address and length + * + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GetAcpiSlitStub ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT VOID **SlitPtr + ) +{ + return AGESA_UNSUPPORTED; +} +/*---------------------------------------------------------------------------------------*/ +/** + * + * This function generates a complete SLIT table into a memory buffer. + * After completion, this table must be set by the system BIOS into its + * internal ACPI namespace, and linked into the RSDT/XSDT + * + * @param[in, out] StdHeader Standard Head Pointer + * @param[in] PlatformConfig Config handle for platform specific information + * @param[in, out] SlitPtr Point to Slit Struct including buffer address and length + * + * @retval UINT32 AGESA_STATUS + */ +AGESA_STATUS +GetAcpiSlitMain ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT VOID **SlitPtr + ) +{ + UINT8 MaxHops; + UINT8 SocketNum; + UINT8 i; + UINT8 j; + UINT8 *BufferPtr; + UINT8 *SocketTopologyDataPtr; + UINT8 *SocketTopologyPtr; + UINT32 Socket; + BOOLEAN IsProbeFilterEnabled; + ACPI_TABLE_HEADER *CpuSlitHeaderStructPtr; + AGESA_STATUS Flag; + ALLOCATE_HEAP_PARAMS AllocStruct; + L3_FEATURE_FAMILY_SERVICES *FamilyServices; + + MaxHops = 0; + SocketTopologyPtr = NULL; + Flag = AGESA_ERROR; + IsProbeFilterEnabled = FALSE; + + // find out the pointer to the BufferHandle which contains + // Node Topology information + AcpiSlitHBufferFind (StdHeader, &SocketTopologyPtr); + if (SocketTopologyPtr == NULL) { + return (Flag); + } + + SocketNum = *SocketTopologyPtr; + + IDS_HDT_CONSOLE (CPU_TRACE, " SLIT is created\n"); + + // create a buffer by calling IBV callout routine + AllocStruct.RequestedBufferSize = (SocketNum * SocketNum) + AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + sizeof (ACPI_TABLE_HEADER); + AllocStruct.BufferHandle = AMD_ACPI_SLIT_BUFFER_HANDLE; + AllocStruct.Persist = HEAP_SYSTEM_MEM; + if (HeapAllocateBuffer (&AllocStruct, StdHeader) != AGESA_SUCCESS) { + return (Flag); + } + *SlitPtr = AllocStruct.BufferPtr; + + //SLIT header + LibAmdMemCopy (*SlitPtr, (VOID *) &CpuSlitHdrStruct, (UINTN) (sizeof (ACPI_TABLE_HEADER)), StdHeader); + CpuSlitHeaderStructPtr = (ACPI_TABLE_HEADER *) *SlitPtr; + CpuSlitHeaderStructPtr->TableLength = (UINT32) AllocStruct.RequestedBufferSize; + BufferPtr = *SlitPtr; + + Flag = AGESA_SUCCESS; + // SLIT body + // Check if Probe Filter is enabled + if (IsFeatureEnabled (L3Features, PlatformConfig, StdHeader)) { + IsProbeFilterEnabled = TRUE; + for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { + if (IsProcessorPresent (Socket, StdHeader)) { + GetFeatureServicesOfSocket (&L3FeatureFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader); + if ((FamilyServices == NULL) || (!FamilyServices->IsHtAssistSupported (FamilyServices, PlatformConfig, StdHeader))) { + IsProbeFilterEnabled = FALSE; + break; + } + } + } + } + + + if (!IsProbeFilterEnabled) { + // probe filter is disabled + // get MaxHops + SocketTopologyDataPtr = SocketTopologyPtr + sizeof (SocketNum); + for (i = 0; i < SocketNum; i++) { + for (j = 0; j < SocketNum; j++) { + if (*SocketTopologyDataPtr > MaxHops) { + MaxHops = *SocketTopologyDataPtr; + } + SocketTopologyDataPtr++; + } + } + + // the Max hop entries have a value of 13 + // and all other entries have 10. + SocketTopologyDataPtr = SocketTopologyPtr + sizeof (SocketNum); + for (i = 0; i < SocketNum; i++) { + for (j = 0; j < SocketNum; j++) { + if (*SocketTopologyDataPtr++ == MaxHops) { + *(BufferPtr + sizeof (ACPI_TABLE_HEADER) + + AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + (i * SocketNum) + j) = 13; + } else { + *(BufferPtr + sizeof (ACPI_TABLE_HEADER) + + AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + (i * SocketNum) + j) = 10; + } + } + } + } else { + // probe filter is enabled + // formula : num_hops * 6 + 10 + SocketTopologyDataPtr = SocketTopologyPtr + sizeof (SocketNum); + for (i = 0; i < SocketNum; i++) { + for (j = 0; j < SocketNum; j++) { + *(BufferPtr + sizeof (ACPI_TABLE_HEADER) + + AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + (i * SocketNum) + j) = + ((*SocketTopologyDataPtr++) * 6) + 10; + } + } + } + + BufferPtr += sizeof (ACPI_TABLE_HEADER); + *((UINT64 *) BufferPtr) = (UINT64) SocketNum; + + //Update SLIT header Checksum + ChecksumAcpiTable ((ACPI_TABLE_HEADER *) *SlitPtr, StdHeader); + + return (Flag); +} + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * + * Find out the pointer to the BufferHandle which contains + * Node Topology information + * + * @param[in, out] StdHeader Standard Head Pointer + * @param[in] SocketTopologyPtr Point to the address of Socket Topology + * + */ +VOID +STATIC +AcpiSlitHBufferFind ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN UINT8 **SocketTopologyPtr + ) +{ + LOCATE_HEAP_PTR LocateBuffer; + + LocateBuffer.BufferHandle = HOP_COUNT_TABLE_HANDLE; + if (HeapLocateBuffer (&LocateBuffer, StdHeader) == AGESA_SUCCESS) { + *SocketTopologyPtr = (UINT8 *) LocateBuffer.BufferPtr; + } + + return; +} + + +/* -----------------------------------------------------------------------------*/ +/** + * ReleaseSlitBufferStub + * + * Description: + * This is the default routine for use when the SLIT option is NOT requested. + * + * Parameters: + * @param[in, out] *StdHeader + * + * @retval AGESA_STATUS + * + */ +AGESA_STATUS +ReleaseSlitBufferStub ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + return AGESA_UNSUPPORTED; +} + +/* -----------------------------------------------------------------------------*/ +/** + * ReleaseSlitBuffer + * + * Description: + * Deallocate SLIT buffer + * + * Parameters: + * @param[in, out] *StdHeader + * + * @retval AGESA_STATUS + * + */ +AGESA_STATUS +ReleaseSlitBuffer ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + HeapDeallocateBuffer ((UINT32) HOP_COUNT_TABLE_HANDLE, StdHeader); + + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSrat.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSrat.c new file mode 100644 index 0000000..6d87fbe --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSrat.c @@ -0,0 +1,643 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD SRAT, ACPI table related API functions. + * + * Contains code that Create the APCI SRAT Table after early reset. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ***************************************************************************/ + + +/*---------------------------------------------------------------------------- + * This file provides functions, that will generate SRAT tables + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuServices.h" +#include "OptionSrat.h" +#include "heapManager.h" +#include "cpuRegisters.h" +#include "cpuLateInit.h" +#include "Ids.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FEATURE_CPUSRAT_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern OPTION_SRAT_CONFIGURATION OptionSratConfiguration; // global user config record + +#define NodeID 0x60 +#define FOURGB 0x010000ul + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GetAcpiSratStub ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT VOID **SratPtr + ); + +AGESA_STATUS +GetAcpiSratMain ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT VOID **SratPtr + ); + +/*---------------------------------------------------------------------------- + * All of the DATA should be defined in _CODE segment. + * Use ROMDATA to specify that it belongs to _CODE. + *---------------------------------------------------------------------------- + */ +STATIC CPU_SRAT_HEADER ROMDATA CpuSratHdrStruct = +{ + {'S','R','A','T'}, + 0, + 2, + 0, + {'A','M','D',' ',' ',' '}, + {'A','G','E','S','A',' ',' ',' '}, + 1, + {'A','M','D',' '}, + 1, + 1, + {0, 0, 0, 0, 0, 0, 0, 0} +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +UINT8 +STATIC +*MakeApicEntry ( + IN UINT8 ApicId, + IN UINT8 Domain, + IN UINT8 *BufferLocPtr + ); + +UINT8 +STATIC +*FillMemoryForCurrentNode ( + IN UINT8 *PDomain, + IN OUT UINT8 *PDomainForBase640K, + IN UINT8 Node, + IN OUT UINT8 *BufferLocPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +STATIC +*MakeMemEntry ( + IN UINT8 PDomain, + IN UINT8 Node, + IN UINT32 Base, + IN UINT32 Size, + IN UINT8 *BufferLocPtr + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------------------*/ +/** + * + * This function will generate a complete Static Resource Affinity Table + * i.e. SRAT into a memory buffer. After completion, this table must be set + * by the system BIOS into its internal ACPI name space. + * + * @param[in, out] StdHeader Standard Head Pointer + * @param[in, out] SratPtr Point to Srat Struct including buffer address and length + * + * @retval AGESA_STATUS + */ + +AGESA_STATUS +CreateAcpiSrat ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT VOID **SratPtr + ) +{ + AGESA_TESTPOINT (TpProcCpuEntrySrat, StdHeader); + return ((*(OptionSratConfiguration.SratFeature)) (StdHeader, SratPtr)); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * + * This is the default routine for use when the SRAT option is NOT requested. + * + * The option install process will create and fill the transfer vector with + * the address of the proper routine (Main or Stub). The link optimizer will + * strip out of the .DLL the routine that is not used. + * + * @param[in, out] StdHeader Standard Head Pointer + * @param[in, out] SratPtr Point to Srat Struct including buffer address and length + * + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GetAcpiSratStub ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT VOID **SratPtr + ) +{ + return AGESA_UNSUPPORTED; +} +/*---------------------------------------------------------------------------------------*/ +/** + * + * This function will generate a complete Static Resource Affinity Table + * i.e. SRAT into a memory buffer. After completion, this table must be set + * by the system BIOS into its internal ACPI name space. + * + * @param[in, out] StdHeader Standard Head Pointer + * @param[in, out] SratPtr Point to Srat Struct including buffer address and length + * + * @retval AGESA_STATUS + */ +AGESA_STATUS +GetAcpiSratMain ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT VOID **SratPtr + ) +{ + UINT8 *BufferPtr; + UINT8 NodeNum; + UINT8 NodeCount; + UINT8 PDomain; + UINT8 PDomainForBase640K; + UINT32 Socket; + UINT32 Module; + UINT32 LowCore; + UINT32 HighCore; + UINT32 CoreNum; + UINT32 RegVal; + UINT32 tempVar_32; + AMD_APIC_PARAMS ApicParams; + PCI_ADDR PciAddress; + CPU_SRAT_HEADER *CpuSratHeaderStructPtr; + ALLOCATE_HEAP_PARAMS AllocParams; + + // Get Node count + PciAddress.AddressValue = MAKE_SBDFO (0, 0, LOW_NODE_DEVICEID, FUNC_0, NodeID); + LibAmdPciRead (AccessWidth32 , PciAddress, &RegVal, StdHeader); + NodeCount = (UINT8) (((RegVal >> 4) & 0x7) + 1); + + // The worst-case buffer size to request is for the SRAT table header, one + // entree for special region (base 640k block), two memory + // regions per node, and APIC entries for each core in the system. + tempVar_32 = (sizeof (CPU_SRAT_HEADER)) + (sizeof (CPU_SRAT_MEMORY_ENTRY)) + + ((UINT32) NodeCount * (2 * (sizeof (CPU_SRAT_MEMORY_ENTRY)) + + ((UINT32) GetActiveCoresInCurrentModule (StdHeader) * sizeof (CPU_SRAT_APIC_ENTRY)))); + + if (*SratPtr == NULL) { + // + // Allocate a buffer + // + AllocParams.RequestedBufferSize = tempVar_32; + AllocParams.BufferHandle = AMD_SRAT_INFO_BUFFER_HANDLE; + AllocParams.Persist = HEAP_SYSTEM_MEM; + + AGESA_TESTPOINT (TpProcCpuBeforeAllocateSratBuffer, StdHeader); + if (HeapAllocateBuffer (&AllocParams, StdHeader) != AGESA_SUCCESS) { + return AGESA_ERROR; + } + AGESA_TESTPOINT (TpProcCpuAfterAllocateSratBuffer, StdHeader); + + *SratPtr = AllocParams.BufferPtr; + } + + IDS_HDT_CONSOLE (CPU_TRACE, " SRAT is created\n"); + + CpuSratHeaderStructPtr = (CPU_SRAT_HEADER *) *SratPtr; + BufferPtr = (UINT8 *) *SratPtr; + + // Copy acpiSRATHeader -> data buffer + LibAmdMemCopy (*SratPtr, (VOID *) &CpuSratHdrStruct, (UINTN) (sizeof (CPU_SRAT_HEADER)), StdHeader); + + BufferPtr += sizeof (CPU_SRAT_HEADER); + + // Place all memory and IO affinity entries + NodeNum = 0; + PDomain = 0; + PDomainForBase640K = 0xFF; + ApicParams.StdHeader = *StdHeader; + while (NodeNum < NodeCount) { + GetSocketModuleOfNode ((UINT32) NodeNum, &Socket, &Module, StdHeader); + GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader); + BufferPtr = FillMemoryForCurrentNode (&PDomain, &PDomainForBase640K, NodeNum, BufferPtr, StdHeader); + for (CoreNum = LowCore; CoreNum <= HighCore; CoreNum++) { + ApicParams.Socket = (UINT8) Socket; + ApicParams.Core = (UINT8) CoreNum; + AmdGetApicId (&ApicParams); + if (ApicParams.IsPresent) { + BufferPtr = MakeApicEntry (ApicParams.ApicAddress, PDomain, BufferPtr); + } + } + + NodeNum++; + PDomain = NodeNum; + } + + // Store size in table (current buffer offset - buffer start offset) + CpuSratHeaderStructPtr->TableLength = (UINT32) (BufferPtr - (UINT8 *) CpuSratHeaderStructPtr); + + //Update SSDT header Checksum + ChecksumAcpiTable ((ACPI_TABLE_HEADER *) CpuSratHeaderStructPtr, StdHeader); + + return AGESA_SUCCESS; +} + + +/*---------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * + * This function will build Memory entry for current node. + * Note that we only create a memory affinity entry if we find one + * that matches the current node. This makes an easier to read table + * though it is not necessary. + * + * @param[in] PDomain Proximity Domain + * @param[in, out] PDomainForBase640K The PDomain for Base 640K + * @param[in] Node The number of Node + * @param[in, out] BufferLocPtr Point to the address of buffer + * @param[in, out] StdHeader Standard Head Pointer + * + * @retval UINT8 *(New buffer location ptr) + */ +UINT8 +STATIC +*FillMemoryForCurrentNode ( + IN UINT8 *PDomain, + IN OUT UINT8 *PDomainForBase640K, + IN UINT8 Node, + IN OUT UINT8 *BufferLocPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 ValueLimit; + UINT32 ValueTOM; + BOOLEAN isModified; + UINT8 Domain; + UINT32 RegVal; + UINT32 DramLeng; + UINT32 DramBase; + UINT32 DramLimit; + UINT32 OffsetRegs; + PCI_ADDR PciAddress; + UINT64 MsrValue; + UINT32 TopOfMemoryAbove4Gb; + + Domain = *PDomain; + + PciAddress.Address.Segment = 0; + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = LOW_NODE_DEVICEID; + PciAddress.Address.Function = FUNC_1; + + for (OffsetRegs = DRAMBase0; OffsetRegs < MMIOBase0; OffsetRegs += 8) { + isModified = FALSE; // FALSE means normal update procedure + // Get DRAM Base Address + PciAddress.Address.Register = OffsetRegs; + LibAmdPciRead (AccessWidth32, PciAddress, &DramBase, StdHeader); + if ((DramBase & 3) != 3) { + // 0:1 set if memory range enabled + // Not set, so we don't have an enabled range + continue; // Proceed to next Base register + } + + // Get DRAM Limit + PciAddress.Address.Register = OffsetRegs + 4; + LibAmdPciRead (AccessWidth32, PciAddress, &DramLimit, StdHeader); + if (DramLimit == 0xFFFFFFFF) { + // Node not installed(all FF's)? + continue; // Proceed to next Base register + } + + if ((DramLimit & 0xFF) != Node) { + // Check if Destination Node ID is current node + continue; // Proceed to next Base register + } + + // We only add an entry now if detected range belongs to current node/PDomain + PciAddress.Address.Register = OffsetRegs + 0x104; + LibAmdPciRead (AccessWidth32, PciAddress, &RegVal, StdHeader); + + DramLimit = (((RegVal & 0xFF) << 16) | (DramLimit >> 16)); // Get DRAM Limit addr [47:24] + DramLimit++; // Add 1 for potential length + DramLimit <<= 8; + + // Get DRAM Base Address + PciAddress.Address.Register = OffsetRegs + 0x100; + LibAmdPciRead (AccessWidth32, PciAddress, &RegVal, StdHeader); + DramBase = ((((RegVal & 0xFF) << 24) | (DramBase >> 8)) & 0xFFFFFF00); // Get DRAM Base Base value [47:24] + DramLeng = DramLimit - DramBase; // Subtract base from limit to get length + + // Leave hole for conventional memory (Less than 640K). It must be on CPU 0. + if (DramBase == 0) { + if (*PDomainForBase640K == 0xFF) { + // It is the first time that the range start at 0. + // If Yes, then Place 1MB memory gap and save Domain to PDomainForBase640K + BufferLocPtr = MakeMemEntry ( + Domain, + Node, + 0, // Base = 0 + 0xA0000 >> 16, // Put it into format used in DRAM regs.. + BufferLocPtr + ); + DramBase += 0x10; // Add 1MB, so range = 1MB to Top of Region + DramLeng -= 0x10; // Also subtract 1MB from the length + *PDomainForBase640K = Domain; // Save Domain number for memory Less than 640K + } else { + // If No, there are more than one memory range less than 640K, it should that + // node interleaving is enabled. All nodes have the same memory ranges + // and all cores in these nodes belong to the same domain. + *PDomain = *PDomainForBase640K; + return (BufferLocPtr); + } + } + LibAmdMsrRead (TOP_MEM, &MsrValue, StdHeader); + ValueTOM = (UINT32) MsrValue >> 16; // Save it in 39:24 format + ValueLimit = DramBase + DramLeng; // We need to know how large region is + + LibAmdMsrRead (SYS_CFG, &MsrValue, StdHeader); + if ((MsrValue & BIT21) != 0) { + LibAmdMsrRead (TOP_MEM2, &MsrValue, StdHeader); + TopOfMemoryAbove4Gb = (UINT32) (MsrValue >> 16); // Save it in 47:16 format + } else { + TopOfMemoryAbove4Gb = 0xFFFFFFFF; + } + + // SPECIAL CASES: + // + // Several conditions require that we process the values of the memory range differently. + // Here are descriptions of the corner cases. + // + // 1. TRUNCATE LOW - Memory range starts below TOM, ends in TOM (memory hole). For this case, + // the range must be truncated to end at TOM. + // ******************************* ******************************* + // * * * -> * * + // ******************************* ******************************* + // 2 TOM 4 2 TOM + // + // 2. TRUNCATE HIGH - Memory range starts below 4GB, ends above 4GB. This is handled by changing the + // start base to 4GB. + // **************** ********** + // * * * -> * * + // **************** ********** + // TOM 3.8 4 6 TOM 3.8 4 6 + // + // 3. Memory range starts below TOM, ends above 4GB. For this case, the range must be truncated + // to end at TOM. Note that this scenario creates two ranges, as the second comparison below + // will find that it ends above 4GB since base and limit have been restored after first truncation, + // and a second range will be written based at 4GB ending at original end address. + // ******************************* **************** ********** + // * * * * -> * * * * + // ******************************* **************** ********** + // 2 TOM 4 6 2 TOM 4 6 + // + // 4. Memory range starts above TOM, ends below or equal to 4GB. This invalid range should simply + // be ignored. + // ******* + // * * -> < NULL > + // ******* + // TOM 3.8 4 + // + // 5. Memory range starts below TOM2, and ends beyond TOM2. This range must be truncated to TOM2. + // ************************ ******************************* + // * * * -> * * + // ************************ ******************************* + // 768 TOM2 1024 768 TOM2 + // + // 6. Memory range starts above TOM2. This invalid range should simply be ignored. + // ******************** + // * * -> < NULL > + // ******************** + // TOM2 1024 1280 + + if (((DramBase < ValueTOM) && (ValueLimit <= FOURGB) && (ValueLimit > ValueTOM)) + || ((DramBase < ValueTOM) && (ValueLimit > FOURGB))) { + // TRUNCATE LOW!!! Shrink entry below TOM... + // Base = DramBase, Size = TOM - DramBase + BufferLocPtr = MakeMemEntry (Domain, Node, DramBase, (ValueTOM - DramBase), BufferLocPtr); + isModified = TRUE; + } + + if ((ValueLimit > FOURGB) && (DramBase < FOURGB)) { + // TRUNCATE HIGH!!! Shrink entry above 4GB... + // Size = Base + Size - 4GB, Base = 4GB + BufferLocPtr = MakeMemEntry (Domain, Node, FOURGB, (DramLeng + DramBase - FOURGB), BufferLocPtr); + isModified = TRUE; + } + + if ((DramBase >= ValueTOM) && (ValueLimit <= FOURGB)) { + // IGNORE!!! Entry located entirely within memory hole + isModified = TRUE; + } + + if ((DramBase < TopOfMemoryAbove4Gb) && (ValueLimit > TopOfMemoryAbove4Gb)) { + // Truncate to TOM2 + // Base = DramBase, Size = TOM2 - DramBase + BufferLocPtr = MakeMemEntry (Domain, Node, DramBase, (TopOfMemoryAbove4Gb - DramBase), BufferLocPtr); + isModified = TRUE; + } + + if (DramBase >= TopOfMemoryAbove4Gb) { + // IGNORE!!! Entry located entirely above TOM2 + isModified = TRUE; + } + + // If special range(isModified), we are done. + // If not, finally write the memory entry. + if (isModified == FALSE) { + // Finally write the memory entry. + BufferLocPtr = MakeMemEntry (Domain, Node, DramBase, DramLeng, BufferLocPtr); + } + + } // for ( OffsetRegs = DRAMBase0; ... ) + + return (BufferLocPtr); +} // FillMemoryForCurrentNode() + + +/*---------------------------------------------------------------------------------------*/ +/** + * This function will add APIC entry. + * + * @param[in] ApicId APIC ID number + * @param[in] Domain Domain number + * @param[in] BufferLocPtr Point to the address of buffer + * + * @retval UINT8 *(New buffer location ptr) + */ +UINT8 +STATIC +*MakeApicEntry ( + IN UINT8 ApicId, + IN UINT8 Domain, + IN UINT8 *BufferLocPtr + ) +{ + CPU_SRAT_APIC_ENTRY *psSratApicEntry; + UINT8 ReservedBytes; + + psSratApicEntry = (CPU_SRAT_APIC_ENTRY *)BufferLocPtr; + + psSratApicEntry->Type = AE_APIC; + psSratApicEntry->Length = (UINT8)sizeof (CPU_SRAT_APIC_ENTRY); + psSratApicEntry->Domain = Domain; + psSratApicEntry->ApicId = ApicId; + psSratApicEntry->Flags = ENABLED; + psSratApicEntry->LSApicEid = 0; + for (ReservedBytes = 0; ReservedBytes < (UINT8)sizeof (psSratApicEntry->Reserved); ReservedBytes++) { + psSratApicEntry->Reserved[ReservedBytes] = 0; + } + return (BufferLocPtr + (UINT8)sizeof (CPU_SRAT_APIC_ENTRY)); +} // MakeApicEntry + + +/*---------------------------------------------------------------------------------------*/ +/** + * + * This function will add Memory entry. + * + * Parameters: + * @param[in] PDomain Proximity Domain + * @param[in] Node The number of Node + * @param[in] Base Memory Base + * @param[in] Size Memory Size + * @param[in] BufferLocPtr Point to the address of buffer + * + * @retval UINT8 * (new buffer location ptr) + */ +UINT8 +STATIC +*MakeMemEntry ( + IN UINT8 PDomain, + IN UINT8 Node, + IN UINT32 Base, + IN UINT32 Size, + IN UINT8 *BufferLocPtr + ) +{ + CPU_SRAT_MEMORY_ENTRY *psSratMemEntry; + UINT8 ReservedBytes; + + psSratMemEntry = (CPU_SRAT_MEMORY_ENTRY *)BufferLocPtr; + + psSratMemEntry->Type = AE_MEMORY; // [0] = Memory Entry + psSratMemEntry->Length = (UINT8)sizeof (CPU_SRAT_MEMORY_ENTRY); // [1] = 40 + psSratMemEntry->Domain = PDomain; // [2] = Proximity Domain + + // [6-7] = Reserved + for (ReservedBytes = 0; ReservedBytes < (UINT8)sizeof (psSratMemEntry->Reserved1); ReservedBytes++) { + psSratMemEntry->Reserved1[ReservedBytes] = 0; + } + + // [8-11] = Keep 31:0 of address only -> Base Addr Low + psSratMemEntry->BaseAddrLow = Base << 16; + + // [12-15] = Keep 39:32 of address only -> Base Addr High + psSratMemEntry->BaseAddrHigh = Base >> 16; + + // [16-19] = Keep 31:0 of address only -> Length Low + psSratMemEntry->LengthAddrLow = Size << 16; + + // [20-23] = Keep 39:32 of address only -> Length High + psSratMemEntry->LengthAddrHigh = Size >> 16; + + // [24-27] = Reserved + for (ReservedBytes = 0; ReservedBytes < (UINT8)sizeof (psSratMemEntry->Reserved2); ReservedBytes++) { + psSratMemEntry->Reserved2[ReservedBytes] = 0; + } + + // [28-31] = Flags + psSratMemEntry->Flags = ENABLED; + + // [32-40] = Reserved + for (ReservedBytes = 0; ReservedBytes < (UINT8)sizeof (psSratMemEntry->Reserved3); ReservedBytes++) { + psSratMemEntry->Reserved3[ReservedBytes] = 0; + } + return (BufferLocPtr + (UINT8)sizeof (CPU_SRAT_MEMORY_ENTRY)); +} // MakeMemEntry() + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSwC1e.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSwC1e.c new file mode 100644 index 0000000..87cd3b1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSwC1e.c @@ -0,0 +1,204 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA CPU SW C1e feature support code. + * + * Contains code that declares the AGESA CPU C1e related APIs + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Feature + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuApicUtilities.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "Topology.h" +#include "cpuFeatures.h" +#include "cpuSwC1e.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FEATURE_CPUSWC1E_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern CPU_FAMILY_SUPPORT_TABLE SwC1eFamilyServiceTable; + +/*---------------------------------------------------------------------------------------*/ +/** + * Should software C1e be enabled + * + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE SW C1e is supported. + * @retval FALSE SW C1e not supported. + * + */ +BOOLEAN +STATIC +IsSwC1eFeatureEnabled ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + BOOLEAN IsEnabled; + BOOLEAN IsOtherC1eEnabled; + AP_MAILBOXES ApMailboxes; + SW_C1E_FAMILY_SERVICES *SwFamilyServices; + + ASSERT (PlatformConfig->C1eMode < MaxC1eMode); + IsEnabled = FALSE; + + // Check whether software C1e is enabled only if other C1e methods is/are not supported + // or if the platform specifically uses C1eModeSoftwareDeprecated. + IsOtherC1eEnabled = (IsFeatureEnabled (HardwareC1e, PlatformConfig, StdHeader) || + IsFeatureEnabled (MsgBasedC1e, PlatformConfig, StdHeader)); + if ((PlatformConfig->C1eMode == C1eModeSoftwareDeprecated) || + ((!IsOtherC1eEnabled) && ((PlatformConfig->C1eMode == C1eModeHardwareSoftwareDeprecated) || (PlatformConfig->C1eMode == C1eModeAuto)))) { + ASSERT ((PlatformConfig->C1ePlatformData1 < 0x10000) && (PlatformConfig->C1ePlatformData1 != 0)); + ASSERT (PlatformConfig->C1ePlatformData2 < 0x100); + if ((PlatformConfig->C1ePlatformData1 != 0) && (PlatformConfig->C1ePlatformData1 < 0xFFFE) && (PlatformConfig->C1ePlatformData2 < 0xFF)) { + if (!IsNonCoherentHt1 (StdHeader)) { + if (GetNumberOfProcessors (StdHeader) == 1) { + GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader); + if (ApMailboxes.ApMailInfo.Fields.ModuleType == 0) { + GetFeatureServicesOfCurrentCore (&SwC1eFamilyServiceTable, (CONST VOID **)&SwFamilyServices, StdHeader); + if (SwFamilyServices != NULL) { + IsEnabled = SwFamilyServices->IsSwC1eSupported (SwFamilyServices, StdHeader); + } + } + } + } + } + } + return IsEnabled; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Enable Software C1e + * + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @return The most severe status of any family specific service. + * + */ +AGESA_STATUS +STATIC +InitializeSwC1eFeature ( + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + SW_C1E_FAMILY_SERVICES *FamilyServices; + + AgesaStatus = AGESA_SUCCESS; + + IDS_HDT_CONSOLE (CPU_TRACE, " SW C1e is enabled\n"); + + if (IsWarmReset (StdHeader)) { + GetFeatureServicesOfCurrentCore (&SwC1eFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); + AgesaStatus = FamilyServices->InitializeSwC1e (FamilyServices, EntryPoint, PlatformConfig, StdHeader); + } + + return AgesaStatus; +} + +CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureSwC1e = +{ + SoftwareC1e, + CPU_FEAT_AFTER_PM_INIT, + IsSwC1eFeatureEnabled, + InitializeSwC1eFeature +}; \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSwC1e.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSwC1e.h new file mode 100644 index 0000000..1316f7d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuSwC1e.h @@ -0,0 +1,146 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA CPU SW C1e Functions declarations. + * + * Contains code that declares the AGESA CPU C1e related APIs + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Feature + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_SW_C1E_H_ +#define _CPU_SW_C1E_H_ + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ +// Forward declaration needed for multi-structure mutual references +AGESA_FORWARD_DECLARATION (SW_C1E_FAMILY_SERVICES); + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to check if software C1e is supported. + * + * @param[in] SwC1eServices Software C1e services. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE SW C1e is supported. + * @retval FALSE SW C1e is not supported. + * + */ +typedef BOOLEAN F_SW_C1E_IS_SUPPORTED ( + IN SW_C1E_FAMILY_SERVICES *SwC1eServices, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method +typedef F_SW_C1E_IS_SUPPORTED *PF_SW_C1E_IS_SUPPORTED; + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to enable software C1e. + * + * @param[in] SwC1eServices Software C1e services. + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @return Family specific error value. + * + */ +typedef AGESA_STATUS F_SW_C1E_INIT ( + IN SW_C1E_FAMILY_SERVICES *SwC1eServices, + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method +typedef F_SW_C1E_INIT *PF_SW_C1E_INIT; + +/** + * Provide the interface to the software C1e Family Specific Services. + * + * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). + * Each supported Family must provide an implementation for all methods in this interface, even if the + * implementation is a CommonReturn(). + */ +struct _SW_C1E_FAMILY_SERVICES { + UINT16 Revision; ///< Interface version + // Public Methods. + PF_SW_C1E_IS_SUPPORTED IsSwC1eSupported; ///< Method: Family specific call to check if software C1e is supported. + PF_SW_C1E_INIT InitializeSwC1e; ///< Method: Family specific call to enable software C1e. +}; + +#endif // _CPU_SW_C1E_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuWhea.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuWhea.c new file mode 100644 index 0000000..c2bb6aa --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuWhea.c @@ -0,0 +1,310 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD WHEA Table Creation API, and related functions. + * + * Contains code that produce the ACPI WHEA related information. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "OptionWhea.h" +#include "cpuLateInit.h" +#include "heapManager.h" +#include "cpuRegisters.h" +#include "cpuFamilyTranslation.h" +#include "Ids.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FEATURE_CPUWHEA_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ + +extern OPTION_WHEA_CONFIGURATION OptionWheaConfiguration; // global user config record + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +CreateHestBank ( + IN AMD_HEST_BANK *HestBankPtr, + IN UINT8 BankNum, + IN AMD_WHEA_INIT_DATA *WheaInitDataPtr + ); + +AGESA_STATUS +GetAcpiWheaStub ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT VOID **WheaMcePtr, + IN OUT VOID **WheaCmcPtr + ); + +AGESA_STATUS +GetAcpiWheaMain ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT VOID **WheaMcePtr, + IN OUT VOID **WheaCmcPtr + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------------------*/ +/** + * + * It will create the ACPI table of WHEA and return the pointer to the table. + * + * @param[in, out] StdHeader Standard Head Pointer + * @param[in, out] WheaMcePtr Point to Whea Hest Mce table + * @param[in, out] WheaCmcPtr Point to Whea Hest Cmc table + * + * @retval AGESA_STATUS + */ +AGESA_STATUS +CreateAcpiWhea ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT VOID **WheaMcePtr, + IN OUT VOID **WheaCmcPtr + ) +{ + AGESA_TESTPOINT (TpProcCpuEntryWhea, StdHeader); + return ((*(OptionWheaConfiguration.WheaFeature)) (StdHeader, WheaMcePtr, WheaCmcPtr)); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * + * This is the default routine for use when the WHEA option is NOT requested. + * + * The option install process will create and fill the transfer vector with + * the address of the proper routine (Main or Stub). The link optimizer will + * strip out of the .DLL the routine that is not used. + * + * @param[in, out] StdHeader Standard Head Pointer + * @param[in, out] WheaMcePtr Point to Whea Hest Mce table + * @param[in, out] WheaCmcPtr Point to Whea Hest Cmc table + * + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GetAcpiWheaStub ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT VOID **WheaMcePtr, + IN OUT VOID **WheaCmcPtr + ) +{ + return AGESA_UNSUPPORTED; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * + * It will create the ACPI tale of WHEA and return the pointer to the table. + * + * @param[in, out] StdHeader Standard Head Pointer + * @param[in, out] WheaMcePtr Point to Whea Hest Mce table + * @param[in, out] WheaCmcPtr Point to Whea Hest Cmc table + * + * @retval UINT32 AGESA_STATUS + */ +AGESA_STATUS +GetAcpiWheaMain ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT VOID **WheaMcePtr, + IN OUT VOID **WheaCmcPtr + ) +{ + UINT8 BankNum; + UINT8 Entries; + UINT16 HestMceTableSize; + UINT16 HestCmcTableSize; + UINT64 MsrData; + AMD_HEST_MCE_TABLE *HestMceTablePtr; + AMD_HEST_CMC_TABLE *HestCmcTablePtr; + AMD_HEST_BANK *HestBankPtr; + AMD_WHEA_INIT_DATA *WheaInitDataPtr; + ALLOCATE_HEAP_PARAMS AllocParams; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + FamilySpecificServices = NULL; + + IDS_HDT_CONSOLE (CPU_TRACE, " WHEA is created\n"); + + // step 1: calculate Hest table size + LibAmdMsrRead (MSR_MCG_CAP, &MsrData, StdHeader); + BankNum = (UINT8) (((MSR_MCG_CAP_STRUCT *) (&MsrData))->Count); + if (BankNum == 0) { + return AGESA_ERROR; + } + + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->GetWheaInitData (FamilySpecificServices, (CONST VOID **) &WheaInitDataPtr, &Entries, StdHeader); + + ASSERT (WheaInitDataPtr->HestBankNum <= BankNum); + + HestMceTableSize = sizeof (AMD_HEST_MCE_TABLE) + WheaInitDataPtr->HestBankNum * sizeof (AMD_HEST_BANK); + HestCmcTableSize = sizeof (AMD_HEST_CMC_TABLE) + WheaInitDataPtr->HestBankNum * sizeof (AMD_HEST_BANK); + + HestMceTablePtr = (AMD_HEST_MCE_TABLE *) *WheaMcePtr; + HestCmcTablePtr = (AMD_HEST_CMC_TABLE *) *WheaCmcPtr; + + // step 2: allocate a buffer by callback function + if ((HestMceTablePtr == NULL) || (HestCmcTablePtr == NULL)) { + AllocParams.RequestedBufferSize = (UINT32) (HestMceTableSize + HestCmcTableSize); + AllocParams.BufferHandle = AMD_WHEA_BUFFER_HANDLE; + AllocParams.Persist = HEAP_SYSTEM_MEM; + + AGESA_TESTPOINT (TpProcCpuBeforeAllocateWheaBuffer, StdHeader); + if (HeapAllocateBuffer (&AllocParams, StdHeader) != AGESA_SUCCESS) { + return AGESA_ERROR; + } + AGESA_TESTPOINT (TpProcCpuAfterAllocateWheaBuffer, StdHeader); + + HestMceTablePtr = (AMD_HEST_MCE_TABLE *) AllocParams.BufferPtr; + HestCmcTablePtr = (AMD_HEST_CMC_TABLE *) ((UINT8 *) (HestMceTablePtr + 1) + (WheaInitDataPtr->HestBankNum * sizeof (AMD_HEST_BANK))); + } + + // step 3: fill in Hest MCE table + HestMceTablePtr->TblLength = HestMceTableSize; + HestMceTablePtr->GlobCapInitDataLSD = WheaInitDataPtr->GlobCapInitDataLSD; + HestMceTablePtr->GlobCapInitDataMSD = WheaInitDataPtr->GlobCapInitDataMSD; + HestMceTablePtr->GlobCtrlInitDataLSD = WheaInitDataPtr->GlobCtrlInitDataLSD; + HestMceTablePtr->GlobCtrlInitDataMSD = WheaInitDataPtr->GlobCtrlInitDataMSD; + HestMceTablePtr->NumHWBanks = WheaInitDataPtr->HestBankNum; + + HestBankPtr = (AMD_HEST_BANK *) (HestMceTablePtr + 1); + CreateHestBank (HestBankPtr, WheaInitDataPtr->HestBankNum, WheaInitDataPtr); + + // step 4: fill in Hest CMC table + HestCmcTablePtr->NumHWBanks = WheaInitDataPtr->HestBankNum; + HestCmcTablePtr->TblLength = HestCmcTableSize; + + HestBankPtr = (AMD_HEST_BANK *) (HestCmcTablePtr + 1); + CreateHestBank (HestBankPtr, WheaInitDataPtr->HestBankNum, WheaInitDataPtr); + + // step 5: fill in the incoming structure + *WheaMcePtr = HestMceTablePtr; + *WheaCmcPtr = HestCmcTablePtr; + + return (AGESA_SUCCESS); +} + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * + * It will create Bank structure for Hest table + * + * @param[in] HestBankPtr Pointer to the Hest Back structure + * @param[in] BankNum The number of Bank + * @param[in] WheaInitDataPtr Pointer to the AMD_WHEA_INIT_DATA structure + * + */ +VOID +STATIC +CreateHestBank ( + IN AMD_HEST_BANK *HestBankPtr, + IN UINT8 BankNum, + IN AMD_WHEA_INIT_DATA *WheaInitDataPtr + ) +{ + UINT8 BankIndex; + for (BankIndex = 0; BankIndex < BankNum; BankIndex++) { + HestBankPtr->BankNum = BankIndex; + HestBankPtr->ClrStatusOnInit = WheaInitDataPtr->ClrStatusOnInit; + HestBankPtr->StatusDataFormat = WheaInitDataPtr->StatusDataFormat; + HestBankPtr->ConfWriteEn = WheaInitDataPtr->ConfWriteEn; + HestBankPtr->CtrlRegMSRAddr = WheaInitDataPtr->HestBankInitData[BankIndex].CtrlRegMSRAddr; + HestBankPtr->CtrlInitDataLSD = WheaInitDataPtr->HestBankInitData[BankIndex].CtrlInitDataLSD; + HestBankPtr->CtrlInitDataMSD = WheaInitDataPtr->HestBankInitData[BankIndex].CtrlInitDataMSD; + HestBankPtr->StatRegMSRAddr = WheaInitDataPtr->HestBankInitData[BankIndex].StatRegMSRAddr; + HestBankPtr->AddrRegMSRAddr = WheaInitDataPtr->HestBankInitData[BankIndex].AddrRegMSRAddr; + HestBankPtr->MiscRegMSRAddr = WheaInitDataPtr->HestBankInitData[BankIndex].MiscRegMSRAddr; + HestBankPtr++; + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c new file mode 100644 index 0000000..af00f26 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c @@ -0,0 +1,1259 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * ACPI S3 Support routines + * + * Contains routines needed for supporting resume from the ACPI S3 sleep state. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Interface + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "S3.h" +#include "mfs3.h" +#include "GeneralServices.h" +#include "cpuServices.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_S3_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +SaveDeviceContext ( + IN DEVICE_BLOCK_HEADER *DeviceList, + IN CALL_POINTS CallPoint, + OUT UINT32 *ActualBufferSize, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +SavePciDevice ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN PCI_DEVICE_DESCRIPTOR *Device, + IN CALL_POINTS CallPoint, + IN OUT VOID **OrMask + ); + +VOID +SaveConditionalPciDevice ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device, + IN CALL_POINTS CallPoint, + IN OUT VOID **OrMask + ); + +VOID +SaveMsrDevice ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN MSR_DEVICE_DESCRIPTOR *Device, + IN CALL_POINTS CallPoint, + IN OUT UINT64 **OrMask + ); + +VOID +SaveConditionalMsrDevice ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device, + IN CALL_POINTS CallPoint, + IN OUT UINT64 **OrMask + ); + +VOID +RestorePciDevice ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN PCI_DEVICE_DESCRIPTOR *Device, + IN CALL_POINTS CallPoint, + IN OUT VOID **OrMask + ); + +VOID +RestoreConditionalPciDevice ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device, + IN CALL_POINTS CallPoint, + IN OUT VOID **OrMask + ); + +VOID +RestoreMsrDevice ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN MSR_DEVICE_DESCRIPTOR *Device, + IN CALL_POINTS CallPoint, + IN OUT UINT64 **OrMask + ); + +VOID +RestoreConditionalMsrDevice ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device, + IN CALL_POINTS CallPoint, + IN OUT UINT64 **OrMask + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Saves all devices in the given device list. + * + * This traverses the entire device list twice. In the first pass, we save + * all devices identified as Pre ESR. In the second pass, we save devices + * marked as post ESR. + * + * @param[in] DeviceList Beginning of the device list to save. + * @param[in] Storage Beginning of the context buffer. + * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or + * AMD_S3LATE_RESTORE. + * @param[out] ActualBufferSize Actual size used in saving the device list. + * @param[in] StdHeader AMD standard header config param. + * + */ +VOID +SaveDeviceListContext ( + IN DEVICE_BLOCK_HEADER *DeviceList, + IN VOID *Storage, + IN CALL_POINTS CallPoint, + OUT UINT32 *ActualBufferSize, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + // Copy device list over + LibAmdMemCopy (Storage, + DeviceList, + (UINTN) DeviceList->RelativeOrMaskOffset, + StdHeader); + SaveDeviceContext (Storage, CallPoint, ActualBufferSize, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Saves all devices in the given device list. + * + * This traverses the entire device list twice. In the first pass, we save + * all devices identified as Pre ESR. In the second pass, we save devices + * marked as post ESR. + * + * @param[in,out] DeviceList Beginning of the device list to save. + * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or + * AMD_S3LATE_RESTORE. + * @param[out] ActualBufferSize Actual size used in saving the device list. + * @param[in] StdHeader AMD standard header config param. + * + */ +VOID +SaveDeviceContext ( + IN DEVICE_BLOCK_HEADER *DeviceList, + IN CALL_POINTS CallPoint, + OUT UINT32 *ActualBufferSize, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + DEVICE_DESCRIPTORS Device; + UINT16 i; + UINT64 StartAddress; + UINT64 EndAddress; + VOID *OrMask; + + StartAddress = (UINT64)DeviceList; + Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; + OrMask = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset; + + // Process Pre ESR List + for (i = 0; i < DeviceList->NumDevices; i++) { + switch (Device.CommonDeviceHeader->Type) { + case DEV_TYPE_PCI_PRE_ESR: + SavePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMask); + // Fall through to advance the pointer after saving context + case DEV_TYPE_PCI: + Device.PciDevice++; + break; + case DEV_TYPE_CPCI_PRE_ESR: + SaveConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMask); + // Fall through to advance the pointer after saving context + case DEV_TYPE_CPCI: + Device.CPciDevice++; + break; + case DEV_TYPE_MSR_PRE_ESR: + SaveMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMask); + // Fall through to advance the pointer after saving context + case DEV_TYPE_MSR: + Device.MsrDevice++; + break; + case DEV_TYPE_CMSR_PRE_ESR: + SaveConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMask); + // Fall through to advance the pointer after saving context + case DEV_TYPE_CMSR: + Device.CMsrDevice++; + break; + } + } + + Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; + // Process Post ESR List + for (i = 0; i < DeviceList->NumDevices; i++) { + switch (Device.CommonDeviceHeader->Type) { + case DEV_TYPE_PCI: + SavePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMask); + // Fall through to advance the pointer after saving context + case DEV_TYPE_PCI_PRE_ESR: + Device.PciDevice++; + break; + case DEV_TYPE_CPCI: + SaveConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMask); + // Fall through to advance the pointer after saving context + case DEV_TYPE_CPCI_PRE_ESR: + Device.CPciDevice++; + break; + case DEV_TYPE_MSR: + SaveMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMask); + // Fall through to advance the pointer after saving context + case DEV_TYPE_MSR_PRE_ESR: + Device.MsrDevice++; + break; + case DEV_TYPE_CMSR: + SaveConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMask); + // Fall through to advance the pointer after saving context + case DEV_TYPE_CMSR_PRE_ESR: + Device.CMsrDevice++; + break; + } + } + EndAddress = (UINT64) OrMask; + *ActualBufferSize = (UINT32) (EndAddress - StartAddress); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Saves the context of a PCI device. + * + * This traverses the provided register list saving PCI registers. + * + * @param[in] StdHeader AMD standard header config param. + * @param[in] Device PCI device to restore. + * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or + * AMD_S3LATE_RESTORE. + * @param[in,out] OrMask Current buffer pointer of raw register values. + * + */ +VOID +SavePciDevice ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN PCI_DEVICE_DESCRIPTOR *Device, + IN CALL_POINTS CallPoint, + IN OUT VOID **OrMask + ) +{ + UINT8 RegSizeInBytes; + UINT8 SpecialCaseIndex; + UINT8 *IntermediatePtr; + UINT16 i; + UINT32 Socket; + UINT32 Module; + UINT32 AndMask; + ACCESS_WIDTH AccessWidth; + AGESA_STATUS IgnoredSts; + PCI_ADDR PciAddress; + PCI_REGISTER_BLOCK_HEADER *RegisterHdr; + + GetSocketModuleOfNode ((UINT32) Device->Node, + &Socket, + &Module, + StdHeader); + GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); + + if (CallPoint == INIT_RESUME) { + MemFS3GetPciDeviceRegisterList (Device, &RegisterHdr, StdHeader); + } else { + S3GetPciDeviceRegisterList (Device, &RegisterHdr, StdHeader); + } + + for (i = 0; i < RegisterHdr->NumRegisters; i++) { + PciAddress.Address.Function = RegisterHdr->RegisterList[i].Function; + PciAddress.Address.Register = RegisterHdr->RegisterList[i].Offset; + RegSizeInBytes = RegisterHdr->RegisterList[i].Type.RegisterSize; + switch (RegSizeInBytes) { + case 1: + AndMask = 0xFFFFFFFF & ((UINT8) RegisterHdr->RegisterList[i].AndMask); + AccessWidth = AccessS3SaveWidth8; + break; + case 2: + AndMask = 0xFFFFFFFF & ((UINT16) RegisterHdr->RegisterList[i].AndMask); + AccessWidth = AccessS3SaveWidth16; + break; + case 3: + // In this case, we don't need to save a register. We just need to call a special + // function to do certain things in the save and resume sequence. + // This should not be used in a non-special case. + AndMask = 0; + RegSizeInBytes = 0; + AccessWidth = 0; + break; + default: + AndMask = RegisterHdr->RegisterList[i].AndMask; + RegSizeInBytes = 4; + AccessWidth = AccessS3SaveWidth32; + break; + } + if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) { + ASSERT ((AndMask != 0) && (RegSizeInBytes != 0) && (AccessWidth != 0)); + LibAmdPciRead (AccessWidth, PciAddress, *OrMask, StdHeader); + } else { + SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex; + RegisterHdr->SpecialCases[SpecialCaseIndex].Save (AccessWidth, PciAddress, *OrMask, StdHeader); + } + if (AndMask != 0) { + // If AndMask is 0, then it is a not-care. Don't need to apply it to the OrMask + **((UINT32 **) OrMask) &= AndMask; + } + if ((RegSizeInBytes == 0) && (**((UINT32 **) OrMask) == RESTART_FROM_BEGINNING_LIST)) { + // Restart from the beginning of the register list + i = 0xFFFF; + } + IntermediatePtr = (UINT8 *) *OrMask; + *OrMask = &IntermediatePtr[RegSizeInBytes]; // += RegSizeInBytes; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Saves the context of a 'conditional' PCI device. + * + * This traverses the provided register list saving PCI registers when appropriate. + * + * @param[in] StdHeader AMD standard header config param. + * @param[in] Device 'conditional' PCI device to restore. + * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or + * AMD_S3LATE_RESTORE. + * @param[in,out] OrMask Current buffer pointer of raw register values. + * + */ +VOID +SaveConditionalPciDevice ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device, + IN CALL_POINTS CallPoint, + IN OUT VOID **OrMask + ) +{ + UINT8 RegSizeInBytes; + UINT8 SpecialCaseIndex; + UINT8 *IntermediatePtr; + UINT16 i; + UINT32 Socket; + UINT32 Module; + UINT32 AndMask; + ACCESS_WIDTH AccessWidth; + AGESA_STATUS IgnoredSts; + PCI_ADDR PciAddress; + CPCI_REGISTER_BLOCK_HEADER *RegisterHdr; + + GetSocketModuleOfNode ((UINT32) Device->Node, + &Socket, + &Module, + StdHeader); + GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); + + if (CallPoint == INIT_RESUME) { + MemFS3GetCPciDeviceRegisterList (Device, &RegisterHdr, StdHeader); + } else { + S3GetCPciDeviceRegisterList (Device, &RegisterHdr, StdHeader); + } + + for (i = 0; i < RegisterHdr->NumRegisters; i++) { + if (((Device->Mask1 & RegisterHdr->RegisterList[i].Mask1) != 0) && + ((Device->Mask2 & RegisterHdr->RegisterList[i].Mask2) != 0)) { + PciAddress.Address.Function = RegisterHdr->RegisterList[i].Function; + PciAddress.Address.Register = RegisterHdr->RegisterList[i].Offset; + RegSizeInBytes = RegisterHdr->RegisterList[i].Type.RegisterSize; + switch (RegSizeInBytes) { + case 1: + AndMask = 0xFFFFFFFF & ((UINT8) RegisterHdr->RegisterList[i].AndMask); + AccessWidth = AccessS3SaveWidth8; + break; + case 2: + AndMask = 0xFFFFFFFF & ((UINT16) RegisterHdr->RegisterList[i].AndMask); + AccessWidth = AccessS3SaveWidth16; + break; + case 3: + // In this case, we don't need to save a register. We just need to call a special + // function to do certain things in the save and resume sequence. + // This should not be used in a non-special case. + AndMask = 0; + RegSizeInBytes = 0; + AccessWidth = 0; + break; + default: + AndMask = RegisterHdr->RegisterList[i].AndMask; + RegSizeInBytes = 4; + AccessWidth = AccessS3SaveWidth32; + break; + } + if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) { + ASSERT ((AndMask != 0) && (RegSizeInBytes != 0) && (AccessWidth != 0)); + LibAmdPciRead (AccessWidth, PciAddress, *OrMask, StdHeader); + } else { + SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex; + RegisterHdr->SpecialCases[SpecialCaseIndex].Save (AccessWidth, PciAddress, *OrMask, StdHeader); + } + if (AndMask != 0) { + // If AndMask is 0, then it is a not-care. Don't need to apply it to the OrMask + **((UINT32 **) OrMask) &= AndMask; + } + if ((RegSizeInBytes == 0) && (**((UINT32 **) OrMask) == RESTART_FROM_BEGINNING_LIST)) { + // Restart from the beginning of the register list + i = 0xFFFF; + } + IntermediatePtr = (UINT8 *) *OrMask; + *OrMask = &IntermediatePtr[RegSizeInBytes]; // += RegSizeInBytes; + } + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Saves the context of an MSR device. + * + * This traverses the provided register list saving MSRs. + * + * @param[in] StdHeader AMD standard header config param. + * @param[in] Device MSR device to restore. + * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or + * AMD_S3LATE_RESTORE. + * @param[in,out] OrMask Current buffer pointer of raw register values. + * + */ +VOID +SaveMsrDevice ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN MSR_DEVICE_DESCRIPTOR *Device, + IN CALL_POINTS CallPoint, + IN OUT UINT64 **OrMask + ) +{ + UINT8 SpecialCaseIndex; + UINT16 i; + MSR_REGISTER_BLOCK_HEADER *RegisterHdr; + + if (CallPoint == INIT_RESUME) { + MemFS3GetMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader); + } else { + S3GetMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader); + } + + for (i = 0; i < RegisterHdr->NumRegisters; i++) { + if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) { + LibAmdMsrRead (RegisterHdr->RegisterList[i].Address, *OrMask, StdHeader); + } else { + SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex; + RegisterHdr->SpecialCases[SpecialCaseIndex].Save (RegisterHdr->RegisterList[i].Address, *OrMask, StdHeader); + } + **OrMask &= RegisterHdr->RegisterList[i].AndMask; + (*OrMask)++; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Saves the context of a 'conditional' MSR device. + * + * This traverses the provided register list saving MSRs when appropriate. + * + * @param[in] StdHeader AMD standard header config param. + * @param[in] Device 'conditional' MSR device to restore. + * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or + * AMD_S3LATE_RESTORE. + * @param[in,out] OrMask Current buffer pointer of raw register values. + * + */ +VOID +SaveConditionalMsrDevice ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device, + IN CALL_POINTS CallPoint, + IN OUT UINT64 **OrMask + ) +{ + UINT8 SpecialCaseIndex; + UINT16 i; + CMSR_REGISTER_BLOCK_HEADER *RegisterHdr; + + if (CallPoint == INIT_RESUME) { + MemFS3GetCMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader); + } else { + S3GetCMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader); + } + + for (i = 0; i < RegisterHdr->NumRegisters; i++) { + if (((Device->Mask1 & RegisterHdr->RegisterList[i].Mask1) != 0) && + ((Device->Mask2 & RegisterHdr->RegisterList[i].Mask2) != 0)) { + if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) { + LibAmdMsrRead (RegisterHdr->RegisterList[i].Address, (UINT64 *) *OrMask, StdHeader); + } else { + SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex; + RegisterHdr->SpecialCases[SpecialCaseIndex].Save (RegisterHdr->RegisterList[i].Address, (UINT64 *) *OrMask, StdHeader); + } + **OrMask &= RegisterHdr->RegisterList[i].AndMask; + (*OrMask)++; + } + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Determines the maximum amount of space required to store all raw register + * values for the given device list. + * + * This traverses the entire device list, and calculates the worst case size + * of each device in the device list. + * + * @param[in] DeviceList Beginning of the device list. + * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or + * AMD_S3LATE_RESTORE. + * @param[in] StdHeader AMD standard header config param. + * + * @retval Size in bytes required for storing all registers. + */ +UINT32 +GetWorstCaseContextSize ( + IN DEVICE_BLOCK_HEADER *DeviceList, + IN CALL_POINTS CallPoint, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 WorstCaseSize; + DEVICE_DESCRIPTORS Device; + UINT16 i; + REGISTER_BLOCK_HEADERS RegisterHdr; + + WorstCaseSize = DeviceList->RelativeOrMaskOffset; + Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; + + // Process Device List + for (i = 0; i < DeviceList->NumDevices; i++) { + switch (Device.CommonDeviceHeader->Type) { + case DEV_TYPE_PCI_PRE_ESR: + // PRE_ESR and post ESR take the same amount of space + case DEV_TYPE_PCI: + if (CallPoint == INIT_RESUME) { + MemFS3GetPciDeviceRegisterList (Device.PciDevice, &RegisterHdr.PciRegisters, StdHeader); + } else { + S3GetPciDeviceRegisterList (Device.PciDevice, &RegisterHdr.PciRegisters, StdHeader); + } + WorstCaseSize += (RegisterHdr.PciRegisters->NumRegisters * 4); + Device.PciDevice++; + break; + case DEV_TYPE_CPCI_PRE_ESR: + // PRE_ESR and post ESR take the same amount of space + case DEV_TYPE_CPCI: + if (CallPoint == INIT_RESUME) { + MemFS3GetCPciDeviceRegisterList (Device.CPciDevice, &RegisterHdr.CPciRegisters, StdHeader); + } else { + S3GetCPciDeviceRegisterList (Device.CPciDevice, &RegisterHdr.CPciRegisters, StdHeader); + } + WorstCaseSize += (RegisterHdr.CPciRegisters->NumRegisters * 4); + Device.CPciDevice++; + break; + case DEV_TYPE_MSR_PRE_ESR: + // PRE_ESR and post ESR take the same amount of space + case DEV_TYPE_MSR: + if (CallPoint == INIT_RESUME) { + MemFS3GetMsrDeviceRegisterList (Device.MsrDevice, &RegisterHdr.MsrRegisters, StdHeader); + } else { + S3GetMsrDeviceRegisterList (Device.MsrDevice, &RegisterHdr.MsrRegisters, StdHeader); + } + WorstCaseSize += (RegisterHdr.MsrRegisters->NumRegisters * 8); + Device.MsrDevice++; + break; + case DEV_TYPE_CMSR_PRE_ESR: + // PRE_ESR and post ESR take the same amount of space + case DEV_TYPE_CMSR: + if (CallPoint == INIT_RESUME) { + MemFS3GetCMsrDeviceRegisterList (Device.CMsrDevice, &RegisterHdr.CMsrRegisters, StdHeader); + } else { + S3GetCMsrDeviceRegisterList (Device.CMsrDevice, &RegisterHdr.CMsrRegisters, StdHeader); + } + WorstCaseSize += (RegisterHdr.CMsrRegisters->NumRegisters * 8); + Device.CMsrDevice++; + break; + default: + ASSERT (FALSE); + } + } + return (WorstCaseSize); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Restores all devices marked as 'before exiting self-refresh.' + * + * This traverses the entire device list, restoring all devices identified + * as Pre ESR. + * + * @param[in,out] OrMaskPtr Current buffer pointer of raw register values. + * @param[in] Storage Beginning of the device list. + * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or + * AMD_S3LATE_RESTORE. + * @param[in] StdHeader AMD standard header config param. + * + */ +VOID +RestorePreESRContext ( + OUT VOID **OrMaskPtr, + IN VOID *Storage, + IN CALL_POINTS CallPoint, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + DEVICE_DESCRIPTORS Device; + UINT16 i; + DEVICE_BLOCK_HEADER *DeviceList; + + DeviceList = (DEVICE_BLOCK_HEADER *) Storage; + Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; + *OrMaskPtr = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset; + + // Process Pre ESR List + for (i = 0; i < DeviceList->NumDevices; i++) { + switch (Device.CommonDeviceHeader->Type) { + case DEV_TYPE_PCI_PRE_ESR: + RestorePciDevice (StdHeader, Device.PciDevice, CallPoint, OrMaskPtr); + // Fall through to advance the pointer after restoring context + case DEV_TYPE_PCI: + Device.PciDevice++; + break; + case DEV_TYPE_CPCI_PRE_ESR: + RestoreConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, OrMaskPtr); + // Fall through to advance the pointer after restoring context + case DEV_TYPE_CPCI: + Device.CPciDevice++; + break; + case DEV_TYPE_MSR_PRE_ESR: + RestoreMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) OrMaskPtr); + // Fall through to advance the pointer after restoring context + case DEV_TYPE_MSR: + Device.MsrDevice++; + break; + case DEV_TYPE_CMSR_PRE_ESR: + RestoreConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) OrMaskPtr); + // Fall through to advance the pointer after restoring context + case DEV_TYPE_CMSR: + Device.CMsrDevice++; + break; + } + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Restores all devices marked as 'after exiting self-refresh.' + * + * This traverses the entire device list, restoring all devices identified + * as Post ESR. + * + * @param[in] OrMaskPtr Current buffer pointer of raw register values. + * @param[in] Storage Beginning of the device list. + * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or + * AMD_S3LATE_RESTORE. + * @param[in] StdHeader AMD standard header config param. + * + */ +VOID +RestorePostESRContext ( + IN VOID *OrMaskPtr, + IN VOID *Storage, + IN CALL_POINTS CallPoint, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + DEVICE_DESCRIPTORS Device; + UINT16 i; + DEVICE_BLOCK_HEADER *DeviceList; + + DeviceList = (DEVICE_BLOCK_HEADER *) Storage; + Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; + + // Process Pre ESR List + for (i = 0; i < DeviceList->NumDevices; i++) { + switch (Device.CommonDeviceHeader->Type) { + case DEV_TYPE_PCI: + RestorePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMaskPtr); + // Fall through to advance the pointer after restoring context + case DEV_TYPE_PCI_PRE_ESR: + Device.PciDevice++; + break; + case DEV_TYPE_CPCI: + RestoreConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMaskPtr); + // Fall through to advance the pointer after restoring context + case DEV_TYPE_CPCI_PRE_ESR: + Device.CPciDevice++; + break; + case DEV_TYPE_MSR: + RestoreMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMaskPtr); + // Fall through to advance the pointer after restoring context + case DEV_TYPE_MSR_PRE_ESR: + Device.MsrDevice++; + break; + case DEV_TYPE_CMSR: + RestoreConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMaskPtr); + // Fall through to advance the pointer after restoring context + case DEV_TYPE_CMSR_PRE_ESR: + Device.CMsrDevice++; + break; + } + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Restores the context of a PCI device. + * + * This traverses the provided register list restoring PCI registers. + * + * @param[in] StdHeader AMD standard header config param. + * @param[in] Device 'conditional' PCI device to restore. + * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or + * AMD_S3LATE_RESTORE. + * @param[in,out] OrMask Current buffer pointer of raw register values. + * + */ +VOID +RestorePciDevice ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN PCI_DEVICE_DESCRIPTOR *Device, + IN CALL_POINTS CallPoint, + IN OUT VOID **OrMask + ) +{ + UINT8 RegSizeInBytes; + UINT8 SpecialCaseIndex; + UINT8 *IntermediatePtr; + UINT16 i; + UINT32 Socket; + UINT32 Module; + UINT32 AndMask; + UINT32 RegValueRead; + UINT32 RegValueWrite; + ACCESS_WIDTH AccessWidth; + AGESA_STATUS IgnoredSts; + PCI_ADDR PciAddress; + PCI_REGISTER_BLOCK_HEADER *RegisterHdr; + + GetSocketModuleOfNode ((UINT32) Device->Node, + &Socket, + &Module, + StdHeader); + GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); + + if (CallPoint == INIT_RESUME) { + MemFS3GetPciDeviceRegisterList (Device, &RegisterHdr, StdHeader); + } else { + S3GetPciDeviceRegisterList (Device, &RegisterHdr, StdHeader); + } + + for (i = 0; i < RegisterHdr->NumRegisters; i++) { + PciAddress.Address.Function = RegisterHdr->RegisterList[i].Function; + PciAddress.Address.Register = RegisterHdr->RegisterList[i].Offset; + RegSizeInBytes = RegisterHdr->RegisterList[i].Type.RegisterSize; + switch (RegSizeInBytes) { + case 1: + AndMask = 0xFFFFFFFF & ((UINT8) RegisterHdr->RegisterList[i].AndMask); + RegValueWrite = **(UINT8 **)OrMask; + AccessWidth = AccessS3SaveWidth8; + break; + case 2: + AndMask = 0xFFFFFFFF & ((UINT16) RegisterHdr->RegisterList[i].AndMask); + RegValueWrite = **(UINT16 **)OrMask; + AccessWidth = AccessS3SaveWidth16; + break; + case 3: + // In this case, we don't need to restore a register. We just need to call a special + // function to do certain things in the save and resume sequence. + // This should not be used in a non-special case. + AndMask = 0; + RegValueWrite = 0; + RegSizeInBytes = 0; + AccessWidth = 0; + break; + default: + AndMask = RegisterHdr->RegisterList[i].AndMask; + RegSizeInBytes = 4; + RegValueWrite = **(UINT32 **)OrMask; + AccessWidth = AccessS3SaveWidth32; + break; + } + if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) { + ASSERT ((AndMask != 0) && (RegSizeInBytes != 0) && (AccessWidth != 0)); + LibAmdPciRead (AccessWidth, PciAddress, &RegValueRead, StdHeader); + RegValueWrite |= RegValueRead & (~AndMask); + LibAmdPciWrite (AccessWidth, PciAddress, &RegValueWrite, StdHeader); + } else { + SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex; + if (AndMask != 0) { + RegisterHdr->SpecialCases[SpecialCaseIndex].Save (AccessWidth, + PciAddress, + &RegValueRead, + StdHeader); + RegValueWrite |= RegValueRead & (~AndMask); + } + RegisterHdr->SpecialCases[SpecialCaseIndex].Restore (AccessWidth, + PciAddress, + &RegValueWrite, + StdHeader); + } + IntermediatePtr = (UINT8 *) *OrMask; + *OrMask = &IntermediatePtr[RegSizeInBytes]; // += RegSizeInBytes; + if ((RegSizeInBytes == 0) && (RegValueWrite == RESTART_FROM_BEGINNING_LIST)) { + // Restart from the beginning of the register list + i = 0xFFFF; + } + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Restores the context of a 'conditional' PCI device. + * + * This traverses the provided register list restoring PCI registers when appropriate. + * + * @param[in] StdHeader AMD standard header config param. + * @param[in] Device 'conditional' PCI device to restore. + * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or + * AMD_S3LATE_RESTORE. + * @param[in,out] OrMask Current buffer pointer of raw register values. + * + */ +VOID +RestoreConditionalPciDevice ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device, + IN CALL_POINTS CallPoint, + IN OUT VOID **OrMask + ) +{ + UINT8 RegSizeInBytes; + UINT8 SpecialCaseIndex; + UINT8 *IntermediatePtr; + UINT16 i; + UINT32 Socket; + UINT32 Module; + UINT32 RegValueRead; + UINT32 RegValueWrite; + UINT32 AndMask; + ACCESS_WIDTH AccessWidth; + AGESA_STATUS IgnoredSts; + PCI_ADDR PciAddress; + CPCI_REGISTER_BLOCK_HEADER *RegisterHdr; + + GetSocketModuleOfNode ((UINT32) Device->Node, + &Socket, + &Module, + StdHeader); + GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); + + if (CallPoint == INIT_RESUME) { + MemFS3GetCPciDeviceRegisterList (Device, &RegisterHdr, StdHeader); + } else { + S3GetCPciDeviceRegisterList (Device, &RegisterHdr, StdHeader); + } + + for (i = 0; i < RegisterHdr->NumRegisters; i++) { + if (((Device->Mask1 & RegisterHdr->RegisterList[i].Mask1) != 0) && + ((Device->Mask2 & RegisterHdr->RegisterList[i].Mask2) != 0)) { + PciAddress.Address.Function = RegisterHdr->RegisterList[i].Function; + PciAddress.Address.Register = RegisterHdr->RegisterList[i].Offset; + RegSizeInBytes = RegisterHdr->RegisterList[i].Type.RegisterSize; + switch (RegSizeInBytes) { + case 1: + AndMask = 0xFFFFFFFF & ((UINT8) RegisterHdr->RegisterList[i].AndMask); + RegValueWrite = **(UINT8 **)OrMask; + AccessWidth = AccessS3SaveWidth8; + break; + case 2: + AndMask = 0xFFFFFFFF & ((UINT16) RegisterHdr->RegisterList[i].AndMask); + RegValueWrite = **(UINT16 **)OrMask; + AccessWidth = AccessS3SaveWidth16; + break; + case 3: + // In this case, we don't need to restore a register. We just need to call a special + // function to do certain things in the save and resume sequence. + // This should not be used in a non-special case. + AndMask = 0; + RegValueWrite = 0; + RegSizeInBytes = 0; + AccessWidth = 0; + break; + default: + AndMask = RegisterHdr->RegisterList[i].AndMask; + RegSizeInBytes = 4; + RegValueWrite = **(UINT32 **)OrMask; + AccessWidth = AccessS3SaveWidth32; + break; + } + if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) { + LibAmdPciRead (AccessWidth, PciAddress, &RegValueRead, StdHeader); + RegValueWrite |= RegValueRead & (~AndMask); + LibAmdPciWrite (AccessWidth, PciAddress, &RegValueWrite, StdHeader); + } else { + SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex; + if (AndMask != 0) { + RegisterHdr->SpecialCases[SpecialCaseIndex].Save (AccessWidth, + PciAddress, + &RegValueRead, + StdHeader); + RegValueWrite |= RegValueRead & (~AndMask); + } + RegisterHdr->SpecialCases[SpecialCaseIndex].Restore (AccessWidth, + PciAddress, + &RegValueWrite, + StdHeader); + } + IntermediatePtr = (UINT8 *) *OrMask; + *OrMask = &IntermediatePtr[RegSizeInBytes]; + if ((RegSizeInBytes == 0) && (RegValueWrite == RESTART_FROM_BEGINNING_LIST)) { + // Restart from the beginning of the register list + i = 0xFFFF; + } + } + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Restores the context of an MSR device. + * + * This traverses the provided register list restoring MSRs. + * + * @param[in] StdHeader AMD standard header config param. + * @param[in] Device MSR device to restore. + * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or + * AMD_S3LATE_RESTORE. + * @param[in,out] OrMask Current buffer pointer of raw register values. + * + */ +VOID +RestoreMsrDevice ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN MSR_DEVICE_DESCRIPTOR *Device, + IN CALL_POINTS CallPoint, + IN OUT UINT64 **OrMask + ) +{ + UINT8 SpecialCaseIndex; + UINT16 i; + UINT64 RegValueRead; + UINT64 RegValueWrite; + MSR_REGISTER_BLOCK_HEADER *RegisterHdr; + + if (CallPoint == INIT_RESUME) { + MemFS3GetMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader); + } else { + S3GetMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader); + } + + for (i = 0; i < RegisterHdr->NumRegisters; i++) { + RegValueWrite = **OrMask; + if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) { + LibAmdMsrRead (RegisterHdr->RegisterList[i].Address, &RegValueRead, StdHeader); + RegValueWrite |= RegValueRead & (~RegisterHdr->RegisterList[i].AndMask); + LibAmdMsrWrite (RegisterHdr->RegisterList[i].Address, &RegValueWrite, StdHeader); + } else { + SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex; + RegisterHdr->SpecialCases[SpecialCaseIndex].Save (RegisterHdr->RegisterList[i].Address, + &RegValueRead, + StdHeader); + RegValueWrite |= RegValueRead & (~RegisterHdr->RegisterList[i].AndMask); + RegisterHdr->SpecialCases[SpecialCaseIndex].Restore (RegisterHdr->RegisterList[i].Address, + &RegValueWrite, + StdHeader); + } + (*OrMask)++; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Restores the context of a 'conditional' MSR device. + * + * This traverses the provided register list restoring MSRs when appropriate. + * + * @param[in] StdHeader AMD standard header config param. + * @param[in] Device 'conditional' MSR device to restore. + * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or + * AMD_S3LATE_RESTORE. + * @param[in,out] OrMask Current buffer pointer of raw register values. + * + */ +VOID +RestoreConditionalMsrDevice ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device, + IN CALL_POINTS CallPoint, + IN OUT UINT64 **OrMask + ) +{ + UINT8 SpecialCaseIndex; + UINT16 i; + UINT64 RegValueRead; + UINT64 RegValueWrite; + CMSR_REGISTER_BLOCK_HEADER *RegisterHdr; + + if (CallPoint == INIT_RESUME) { + MemFS3GetCMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader); + } else { + S3GetCMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader); + } + + for (i = 0; i < RegisterHdr->NumRegisters; i++) { + if (((Device->Mask1 & RegisterHdr->RegisterList[i].Mask1) != 0) && + ((Device->Mask2 & RegisterHdr->RegisterList[i].Mask2) != 0)) { + RegValueWrite = **OrMask; + if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) { + LibAmdMsrRead (RegisterHdr->RegisterList[i].Address, &RegValueRead, StdHeader); + RegValueWrite |= RegValueRead & (~RegisterHdr->RegisterList[i].AndMask); + LibAmdMsrWrite (RegisterHdr->RegisterList[i].Address, &RegValueWrite, StdHeader); + } else { + SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex; + RegisterHdr->SpecialCases[SpecialCaseIndex].Save (RegisterHdr->RegisterList[i].Address, + &RegValueRead, + StdHeader); + RegValueWrite |= RegValueRead & (~RegisterHdr->RegisterList[i].AndMask); + RegisterHdr->SpecialCases[SpecialCaseIndex].Restore (RegisterHdr->RegisterList[i].Address, + &RegValueWrite, + StdHeader); + } + (*OrMask)++; + } + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Unique device ID to PCI register list translator. + * + * This translates the given device header in storage to the appropriate list + * of registers in the AGESA image. + * + * @param[out] NonMemoryRelatedDeviceList List of devices to save and restore + * during S3LateRestore. + * @param[in] StdHeader AMD standard header config param. + * + */ +VOID +GetNonMemoryRelatedDeviceList ( + OUT DEVICE_BLOCK_HEADER **NonMemoryRelatedDeviceList, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *NonMemoryRelatedDeviceList = NULL; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Unique device ID to PCI register list translator. + * + * This translates the given device header in storage to the appropriate list + * of registers in the AGESA image. + * + * @param[in] Device Device header containing the unique ID. + * @param[out] RegisterHdr Output PCI register list pointer. + * @param[in] StdHeader AMD standard header config param. + * + * @retval AGESA_SUCCESS Always succeeds. + */ +AGESA_STATUS +S3GetPciDeviceRegisterList ( + IN PCI_DEVICE_DESCRIPTOR *Device, + OUT PCI_REGISTER_BLOCK_HEADER **RegisterHdr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *RegisterHdr = NULL; + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Unique device ID to 'conditional' PCI register list translator. + * + * This translates the given device header in storage to the appropriate list + * of registers in the AGESA image. + * + * @param[in] Device Device header containing the unique ID. + * @param[out] RegisterHdr Output 'conditional' PCI register list pointer. + * @param[in] StdHeader AMD standard header config param. + * + * @retval AGESA_SUCCESS Always succeeds. + */ +AGESA_STATUS +S3GetCPciDeviceRegisterList ( + IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device, + OUT CPCI_REGISTER_BLOCK_HEADER **RegisterHdr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *RegisterHdr = NULL; + return AGESA_SUCCESS; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Unique device ID to MSR register list translator. + * + * This translates the given device header in storage to the appropriate list + * of registers in the AGESA image. + * + * @param[in] Device Device header containing the unique ID. + * @param[out] RegisterHdr Output MSR register list pointer. + * @param[in] StdHeader AMD standard header config param. + * + * @retval AGESA_SUCCESS Always succeeds. + */ +AGESA_STATUS +S3GetMsrDeviceRegisterList ( + IN MSR_DEVICE_DESCRIPTOR *Device, + OUT MSR_REGISTER_BLOCK_HEADER **RegisterHdr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *RegisterHdr = NULL; + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Unique device ID to 'conditional' MSR register list translator. + * + * This translates the given device header in storage to the appropriate list + * of registers in the AGESA image. + * + * @param[in] Device Device header containing the unique ID. + * @param[out] RegisterHdr Output 'conditional' MSR register list pointer. + * @param[in] StdHeader AMD standard header config param. + * + * @retval AGESA_SUCCESS Always succeeds. + */ +AGESA_STATUS +S3GetCMsrDeviceRegisterList ( + IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device, + OUT CMSR_REGISTER_BLOCK_HEADER **RegisterHdr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *RegisterHdr = NULL; + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Constructor for the AMD_S3_PARAMS structure. + * + * This routine initializes failsafe values for the AMD_S3_PARAMS structure + * to be used by the AMD_INIT_RESUME, AMD_S3_SAVE, and AMD_S3LATE_RESTORE + * entry points. + * + * @param[in,out] S3Params Required input parameter for the AMD_S3_SAVE, + * AMD_INIT_RESUME, and AMD_S3_SAVE entry points. + * + */ +VOID +AmdS3ParamsInitializer ( + OUT AMD_S3_PARAMS *S3Params + ) +{ + S3Params->Signature = 0x52545341; + S3Params->Version = 0x0000; + S3Params->VolatileStorage = NULL; + S3Params->VolatileStorageSize = 0x00000000; + S3Params->Flags = 0x00000000; + S3Params->NvStorage = NULL; + S3Params->NvStorageSize = 0x00000000; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.h new file mode 100644 index 0000000..09f5f46 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.h @@ -0,0 +1,421 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * ACPI S3 support definitions. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _S3_H_ +#define _S3_H_ + + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ +#define RESTART_FROM_BEGINNING_LIST 0xFFFFFFFFul + +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ + +/* Device related definitions */ + +/// Header at the beginning of a context save buffer. +typedef struct { + UINT16 Version; ///< Version of header + UINT16 NumDevices; ///< Number of devices in the list + UINT16 RelativeOrMaskOffset; ///< Size of device list + header +} DEVICE_BLOCK_HEADER; + +/// S3 device types +typedef enum { + DEV_TYPE_PCI_PRE_ESR, ///< PCI device before exiting self-refresh + DEV_TYPE_PCI, ///< PCI device after exiting self-refresh + DEV_TYPE_CPCI_PRE_ESR, ///< 'conditional' PCI device before exiting self-refresh + DEV_TYPE_CPCI, ///< 'conditional' PCI device after exiting self-refresh + DEV_TYPE_MSR_PRE_ESR, ///< MSR device before exiting self-refresh + DEV_TYPE_MSR, ///< MSR device after exiting self-refresh + DEV_TYPE_CMSR_PRE_ESR, ///< 'conditional' MSR device before exiting self-refresh + DEV_TYPE_CMSR ///< 'conditional' MSR device after exiting self-refresh +} S3_DEVICE_TYPES; + +/// S3 restoration call points +typedef enum { + INIT_RESUME, ///< AMD_INIT_RESUME + S3_LATE_RESTORE ///< AMD_S3LATE_RESTORE +} CALL_POINTS; + +/// S3 device common header +typedef struct { + UINT32 RegisterListID; ///< Unique ID of this device + UINT8 Type; ///< Appropriate S3_DEVICE_TYPES type +} DEVICE_DESCRIPTOR; + +/// S3 PCI device header +typedef struct { + UINT32 RegisterListID; ///< Unique ID of this device + UINT8 Type; ///< DEV_TYPE_PCI / DEV_TYPE_PCI_PRE_ESR + UINT8 Node; ///< Zero-based node number +} PCI_DEVICE_DESCRIPTOR; + +/// S3 'conditional' PCI device header +typedef struct { + UINT32 RegisterListID; ///< Unique ID of this device + UINT8 Type; ///< DEV_TYPE_CPCI / DEV_TYPE_CPCI_PRE_ESR + UINT8 Node; ///< Zero-based node number + UINT8 Mask1; ///< Conditional mask 1 + UINT8 Mask2; ///< Conditional mask 2 +} CONDITIONAL_PCI_DEVICE_DESCRIPTOR; + +/// S3 MSR device header +typedef struct { + UINT32 RegisterListID; ///< Unique ID of this device + UINT8 Type; ///< DEV_TYPE_MSR / DEV_TYPE_MSR_PRE_ESR +} MSR_DEVICE_DESCRIPTOR; + +/// S3 'conditional' MSR device header +typedef struct { + UINT32 RegisterListID; ///< Unique ID of this device + UINT8 Type; ///< DEV_TYPE_CMSR / DEV_TYPE_CMSR_PRE_ESR + UINT8 Mask1; ///< Conditional mask 1 + UINT8 Mask2; ///< Conditional mask 2 +} CONDITIONAL_MSR_DEVICE_DESCRIPTOR; + +/* Special case related definitions */ + +/** + * PCI special case save handler + * + * @param[in] AccessWidth 8, 16, or 32 bit wide access + * @param[in] Address full PCI address of the register to save + * @param[out] Value Value read from the register + * @param[in] ConfigPtr AMD standard header config parameter + * + */ +typedef VOID (*PF_S3_SPECIAL_PCI_SAVE) ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + OUT VOID *Value, + IN VOID *ConfigPtr + ); + +/** + * PCI special case restore handler + * + * @param[in] AccessWidth 8, 16, or 32 bit wide access + * @param[in] Address full PCI address of the register to save + * @param[in] Value Value to write to the register + * @param[in] ConfigPtr AMD standard header config parameter + * + */ +typedef VOID (*PF_S3_SPECIAL_PCI_RESTORE) ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + IN VOID *Value, + IN VOID *StdHeader + ); + +/** + * MSR special case save handler + * + * @param[in] MsrAddress Address of model specific register to save + * @param[out] Value Value read from the register + * @param[in] ConfigPtr AMD standard header config parameter + * + */ +typedef VOID (*PF_S3_SPECIAL_MSR_SAVE) ( + IN UINT32 MsrAddress, + OUT UINT64 *Value, + IN VOID *StdHeader + ); + +/** + * MSR special case restore handler + * + * @param[in] MsrAddress Address of model specific register to restore + * @param[in] Value Value to write to the register + * @param[in] ConfigPtr AMD standard header config parameter + * + */ +typedef VOID (*PF_S3_SPECIAL_MSR_RESTORE) ( + IN UINT32 MsrAddress, + IN UINT64 *Value, + IN VOID *StdHeader + ); + +/// PCI special case save/restore structure. +typedef struct { + PF_S3_SPECIAL_PCI_SAVE Save; ///< Save routine + PF_S3_SPECIAL_PCI_RESTORE Restore; ///< Restore routine +} PCI_SPECIAL_CASE; + +/// MSR special case save/restore structure. +typedef struct { + PF_S3_SPECIAL_MSR_SAVE Save; ///< Save routine + PF_S3_SPECIAL_MSR_RESTORE Restore; ///< Restore routine +} MSR_SPECIAL_CASE; + +/* Register related definitions */ +/// S3 register type bit fields +typedef struct { + UINT8 SpecialCaseIndex:4; ///< Special Case array index + UINT8 RegisterSize:3; ///< For PCI, 1 = byte, 2 = word, else = dword. + ///< For MSR, don't care + UINT8 SpecialCaseFlag:1; ///< Indicates special case +} S3_REGISTER_TYPE; + +/// S3 PCI register descriptor. +typedef struct { + S3_REGISTER_TYPE Type; ///< Type[7] = special case flag, + ///< Type[6:3] = register size in bytes, + ///< Type[2:0] = special case index + UINT8 Function; ///< PCI function of the register + UINT16 Offset; ///< PCI offset of the register + UINT32 AndMask; ///< AND mask to be applied to the value before saving +} PCI_REG_DESCRIPTOR; + +/// S3 'conditional' PCI register descriptor. +typedef struct { + S3_REGISTER_TYPE Type; ///< Type[7] = special case flag, + ///< Type[6:3] = register size in bytes, + ///< Type[2:0] = special case index + UINT8 Function; ///< PCI function of the register + UINT16 Offset; ///< PCI offset of the register + UINT32 AndMask; ///< AND mask to be applied to the value before saving + UINT8 Mask1; ///< conditional mask 1 + UINT8 Mask2; ///< conditional mask 2 +} CONDITIONAL_PCI_REG_DESCRIPTOR; + +/// S3 MSR register descriptor. +typedef struct { + S3_REGISTER_TYPE Type; ///< Type[7] = special case flag, + ///< Type[6:3] = reserved, + ///< Type[2:0] = special case index + UINT32 Address; ///< MSR address + UINT64 AndMask; ///< AND mask to be applied to the value before saving +} MSR_REG_DESCRIPTOR; + +/// S3 'conditional' MSR register descriptor. +typedef struct { + S3_REGISTER_TYPE Type; ///< Type[7] = special case flag, + ///< Type[6:3] = reserved, + ///< Type[2:0] = special case index + UINT32 Address; ///< MSR address + UINT64 AndMask; ///< AND mask to be applied to the value before saving + UINT8 Mask1; ///< conditional mask 1 + UINT8 Mask2; ///< conditional mask 2 +} CONDITIONAL_MSR_REG_DESCRIPTOR; + +/// Common header at the beginning of an S3 register list. +typedef struct { + UINT16 Version; ///< Version of header + UINT16 NumRegisters; ///< Number of registers in the list +} REGISTER_BLOCK_HEADER; + +/// S3 PCI register list header. +typedef struct { + UINT16 Version; ///< Version of header + UINT16 NumRegisters; ///< Number of registers in the list + PCI_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor + PCI_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers +} PCI_REGISTER_BLOCK_HEADER; + +/// S3 'conditional' PCI register list header. +typedef struct { + UINT16 Version; ///< Version of header + UINT16 NumRegisters; ///< Number of registers in the list + CONDITIONAL_PCI_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor + PCI_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers +} CPCI_REGISTER_BLOCK_HEADER; + +/// S3 MSR register list header. +typedef struct { + UINT16 Version; ///< Version of header + UINT16 NumRegisters; ///< Number of registers in the list + MSR_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor + MSR_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers +} MSR_REGISTER_BLOCK_HEADER; + +/// S3 'conditional' MSR register list header. +typedef struct { + UINT16 Version; ///< Version of header + UINT16 NumRegisters; ///< Number of registers in the list + CONDITIONAL_MSR_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor + MSR_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers +} CMSR_REGISTER_BLOCK_HEADER; + +/// S3 device descriptor pointers for ease of proper pointer advancement. +typedef union { + DEVICE_DESCRIPTOR *CommonDeviceHeader; ///< Common header + PCI_DEVICE_DESCRIPTOR *PciDevice; ///< PCI header + CONDITIONAL_PCI_DEVICE_DESCRIPTOR *CPciDevice; ///< 'conditional' PCI header + MSR_DEVICE_DESCRIPTOR *MsrDevice; ///< MSR header + CONDITIONAL_MSR_DEVICE_DESCRIPTOR *CMsrDevice; ///< 'conditional' MSR header +} DEVICE_DESCRIPTORS; + +/// S3 register list header pointers for ease of proper pointer advancement. +typedef union { + DEVICE_DESCRIPTOR *CommonDeviceHeader; ///< Common header + PCI_REGISTER_BLOCK_HEADER *PciRegisters; ///< PCI header + CPCI_REGISTER_BLOCK_HEADER *CPciRegisters; ///< 'conditional' PCI header + MSR_REGISTER_BLOCK_HEADER *MsrRegisters; ///< MSR header + CMSR_REGISTER_BLOCK_HEADER *CMsrRegisters; ///< 'conditional' MSR header +} REGISTER_BLOCK_HEADERS; + +/// S3 Volatile Storage Header +typedef struct { + UINT32 HeapOffset; ///< Offset to beginning of heap data + UINT32 HeapSize; ///< Size of the heap data + UINT32 RegisterDataOffset; ///< Offset to beginning of raw save data + UINT32 RegisterDataSize; ///< Size of raw save data +} S3_VOLATILE_STORAGE_HEADER; + + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ +UINT32 +GetWorstCaseContextSize ( + IN DEVICE_BLOCK_HEADER *DeviceList, + IN CALL_POINTS CallPoint, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +SaveDeviceListContext ( + IN DEVICE_BLOCK_HEADER *DeviceList, + IN VOID *Storage, + IN CALL_POINTS CallPoint, + OUT UINT32 *ActualBufferSize, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +RestorePreESRContext ( + OUT VOID **OrMaskPtr, + IN VOID *Storage, + IN CALL_POINTS CallPoint, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +RestorePostESRContext ( + IN VOID *OrMaskPtr, + IN VOID *Storage, + IN CALL_POINTS CallPoint, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +AmdS3ParamsInitializer ( + OUT AMD_S3_PARAMS *S3Params + ); + +VOID +GetNonMemoryRelatedDeviceList ( + OUT DEVICE_BLOCK_HEADER **NonMemoryRelatedDeviceList, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +S3GetPciDeviceRegisterList ( + IN PCI_DEVICE_DESCRIPTOR *Device, + OUT PCI_REGISTER_BLOCK_HEADER **RegisterHdr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +S3GetCPciDeviceRegisterList ( + IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device, + OUT CPCI_REGISTER_BLOCK_HEADER **RegisterHdr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +S3GetMsrDeviceRegisterList ( + IN MSR_DEVICE_DESCRIPTOR *Device, + OUT MSR_REGISTER_BLOCK_HEADER **RegisterHdr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +S3GetCMsrDeviceRegisterList ( + IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device, + OUT CMSR_REGISTER_BLOCK_HEADER **RegisterHdr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + + +#endif // _S3_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.c new file mode 100644 index 0000000..1293159 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.c @@ -0,0 +1,919 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Register Table Related Functions + * + * Set registers according to a set of register tables + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Topology.h" +#include "OptionMultiSocket.h" +#include "cpuRegisters.h" +#include "cpuFamilyTranslation.h" +#include "Table.h" +#include "GeneralServices.h" +#include "cpuServices.h" +#include "cpuFeatures.h" +#include "CommonReturns.h" +#include "cpuL3Features.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_TABLE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +SetRegistersFromTablesAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern BUILD_OPT_CFG UserOptions; +extern CPU_FAMILY_SUPPORT_TABLE L3FeatureFamilyServiceTable; + +/*---------------------------------------------------------------------------------------*/ +/** + * An iterator for all the Family and Model Register Tables. + * + * RegisterTableHandle should be set to NULL to begin iteration, the first time the method is + * invoked. Register tables can be processed, until this method returns NULL. RegisterTableHandle + * should simply be passed back to the method without modification or use by the caller. + * The table selector allows the relevant tables for different cores to be iterated, if the family separates + * tables. For example, MSRs can be in a table processed by all cores and PCI registers in a table processed by + * primary cores. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] Selector Select whether to iterate over tables for either all cores, primary cores, bsp, .... + * @param[in,out] RegisterTableHandle IN: The handle of the current register table, or NULL if Begin. + * OUT: The handle of the next register table, if not End. + * @param[out] NumberOfEntries The number of entries in the table returned, if not End. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @return The pointer to the next Register Table, or NULL if End. + */ +TABLE_ENTRY_FIELDS +STATIC +*GetNextRegisterTable ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN TABLE_CORE_SELECTOR Selector, + IN OUT REGISTER_TABLE ***RegisterTableHandle, + OUT UINTN *NumberOfEntries, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + REGISTER_TABLE **NextTable; + TABLE_ENTRY_FIELDS *Entries; + + ASSERT ((FamilySpecificServices != NULL) && (StdHeader != NULL)); + ASSERT (Selector < TableCoreSelectorMax); + + NextTable = *RegisterTableHandle; + if (NextTable == NULL) { + // Begin + NextTable = FamilySpecificServices->RegisterTableList; + IDS_OPTION_HOOK (IDS_TRAP_TABLE, &NextTable, StdHeader); + } else { + NextTable++; + } + // skip if not selected + while ((*NextTable != NULL) && (*NextTable)->Selector != Selector) { + NextTable++; + } + if (*NextTable == NULL) { + // End + *RegisterTableHandle = NULL; + Entries = NULL; + } else { + // Iterate next table + *RegisterTableHandle = NextTable; + *NumberOfEntries = (*NextTable)->NumberOfEntries; + Entries = (TABLE_ENTRY_FIELDS *) (*NextTable)->Table; + } + return Entries; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Compare counts to a pair of ranges. + * + * @param[in] FirstCount The actual count to be compared to the first range. + * @param[in] SecondCount The actual count to be compared to the second range. + * @param[in] Ranges The ranges which the counts are compared to. + * + * @retval TRUE Either one, or both, of the counts is in the range given. + * @retval FALSE Neither count is in the range given. + */ +BOOLEAN +IsEitherCountInRange ( + IN UINTN FirstCount, + IN UINTN SecondCount, + IN COUNT_RANGE_FEATURE Ranges + ) +{ + // Errors: Entire Range value is zero, Min and Max reversed or not <=, ranges overlap (OK if first range is all), + // the real counts are too big. + ASSERT ((Ranges.Range0Min <= Ranges.Range0Max) && + (Ranges.Range1Min <= Ranges.Range1Max) && + (Ranges.Range0Max != 0) && + (Ranges.Range1Max != 0) && + ((Ranges.Range0Max == COUNT_RANGE_HIGH) || (Ranges.Range0Max < Ranges.Range1Min)) && + ((FirstCount < COUNT_RANGE_HIGH) && (SecondCount < COUNT_RANGE_HIGH))); + + return (BOOLEAN) (((FirstCount <= Ranges.Range0Max) && (FirstCount >= Ranges.Range0Min)) || + ((SecondCount <= Ranges.Range1Max) && (SecondCount >= Ranges.Range1Min))); +} + +/*-------------------------------------------------------------------------------------*/ +/** + * Returns the performance profile features list of the currently running processor core. + * + * @param[out] Features The performance profile features supported by this platform + * @param[in] PlatformConfig Config handle for platform specific information + * @param[in] StdHeader Header for library and services + * + */ +VOID +GetPerformanceFeatures ( + OUT PERFORMANCE_PROFILE_FEATS *Features, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + CPUID_DATA CpuidDataStruct; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + L3_FEATURE_FAMILY_SERVICES *FeatureFamilyServices; + + Features->PerformanceProfileValue = 0; + // Reflect Probe Filter Configuration. + Features->PerformanceProfileFeatures.ProbeFilter = 0; + if (IsFeatureEnabled (L3Features, PlatformConfig, StdHeader)) { + GetFeatureServicesOfCurrentCore (&L3FeatureFamilyServiceTable, (CONST VOID **)&FeatureFamilyServices, StdHeader); + if ((FeatureFamilyServices != NULL) && + (FeatureFamilyServices->IsHtAssistSupported (FeatureFamilyServices, PlatformConfig, StdHeader))) { + Features->PerformanceProfileFeatures.ProbeFilter = 1; + } + } + + // Reflect Display Refresh Requests use 32 bytes Configuration. + Features->PerformanceProfileFeatures.RefreshRequest32Byte = 0; + if (PlatformConfig->PlatformProfile.Use32ByteRefresh) { + Features->PerformanceProfileFeatures.RefreshRequest32Byte = 1; + } + // Reflect Mct Isoc Read Priority set to variable Configuration. + Features->PerformanceProfileFeatures.MctIsocVariable = 0; + if (PlatformConfig->PlatformProfile.UseVariableMctIsocPriority) { + Features->PerformanceProfileFeatures.MctIsocVariable = 1; + } + // Indicate if this boot is a warm reset. + Features->PerformanceProfileFeatures.IsWarmReset = 0; + if (IsWarmReset (StdHeader)) { + Features->PerformanceProfileFeatures.IsWarmReset = 1; + } + + // Get L3 Cache present as indicated by CPUID + Features->PerformanceProfileFeatures.L3Cache = 0; + Features->PerformanceProfileFeatures.NoL3Cache = 1; + LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuidDataStruct, StdHeader); + if (((CpuidDataStruct.EDX_Reg & 0xFFFC0000) >> 18) != 0) { + Features->PerformanceProfileFeatures.L3Cache = 1; + Features->PerformanceProfileFeatures.NoL3Cache = 0; + } + + // Get VRM select high speed from build option. + Features->PerformanceProfileFeatures.VrmHighSpeed = 0; + if (PlatformConfig->VrmProperties[CoreVrm].HiSpeedEnable) { + Features->PerformanceProfileFeatures.VrmHighSpeed = 1; + } + + // Get some family, model specific performance type info. + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + ASSERT (FamilySpecificServices != NULL); + + // Is the Northbridge P-State feature enabled + Features->PerformanceProfileFeatures.NbPstates = 0; + if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, PlatformConfig, StdHeader)) { + Features->PerformanceProfileFeatures.NbPstates = 1; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Perform the MSR Register Entry. + * + * @TableEntryTypeMethod{::MsrRegister}. + * + * Read - Modify - Write the MSR, clearing masked bits, and setting the data bits. + * + * @param[in] Entry The MSR register entry to perform + * @param[in] PlatformConfig Config handle for platform specific information + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +SetRegisterForMsrEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 MsrData; + + // Even for only single bit fields, use those in the mask. "Mask nothing" is a bug, even if just by policy. + ASSERT (Entry->MsrEntry.Mask != 0); + + LibAmdMsrRead (Entry->MsrEntry.Address, &MsrData, StdHeader); + MsrData = MsrData & (~(Entry->MsrEntry.Mask)); + MsrData = MsrData | Entry->MsrEntry.Data; + LibAmdMsrWrite (Entry->MsrEntry.Address, &MsrData, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Perform the PCI Register Entry. + * + * @TableEntryTypeMethod{::PciRegister}. + * + * Make the current core's PCI address with the function and register for the entry. + * Read - Modify - Write the PCI register, clearing masked bits, and setting the data bits. + * + * @param[in] Entry The PCI register entry to perform + * @param[in] PlatformConfig Config handle for platform specific information + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +SetRegisterForPciEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempVar32_a; + UINT32 MySocket; + UINT32 MyModule; + UINT32 Ignored; + PCI_ADDR MyPciAddress; + AGESA_STATUS IgnoredSts; + TABLE_ENTRY_DATA PciEntry; + + // Errors: Possible values in unused entry space, extra type features, value range checks. + // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. + // Even for only single bit fields, use those in the mask. "Mask nothing" is a bug, even if just by policy. + ASSERT ((Entry->InitialValues[4] == 0) && + (Entry->InitialValues[3] == 0) && + (Entry->PciEntry.Mask != 0)); + + LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); + PciEntry.PciEntry = Entry->PciEntry; + + IDS_OPTION_HOOK (IDS_SET_PCI_REGISTER_ENTRY, &PciEntry, StdHeader); + + IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredSts); + GetPciAddress (StdHeader, MySocket, MyModule, &MyPciAddress, &IgnoredSts); + MyPciAddress.Address.Function = PciEntry.PciEntry.Address.Address.Function; + MyPciAddress.Address.Register = PciEntry.PciEntry.Address.Address.Register; + LibAmdPciRead (AccessWidth32, MyPciAddress, &TempVar32_a, StdHeader); + TempVar32_a = TempVar32_a & (~(PciEntry.PciEntry.Mask)); + TempVar32_a = TempVar32_a | PciEntry.PciEntry.Data; + LibAmdPciWrite (AccessWidth32, MyPciAddress, &TempVar32_a, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Perform the Family Specific Workaround Register Entry. + * + * @TableEntryTypeMethod{::FamSpecificWorkaround}. + * + * Call the function, passing the data. + * + * See if you can use the other entries or make an entry that covers the fix. + * After all, the purpose of having a table entry is to @b NOT have code which + * isn't generic feature code, but is family/model code specific to one case. + * + * @param[in] Entry The Family Specific Workaround register entry to perform + * @param[in] PlatformConfig Config handle for platform specific information + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +SetRegisterForFamSpecificWorkaroundEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + ASSERT (Entry->FamSpecificEntry.DoAction != NULL); + + Entry->FamSpecificEntry.DoAction (Entry->FamSpecificEntry.Data, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Perform the Performance Profile PCI Register Entry. + * + * @TableEntryTypeMethod{::ProfileFixup}. + * + * Check the entry's performance profile features to the platform's and do the + * PCI register entry if they match. + * + * @param[in] Entry The Performance Profile register entry to perform + * @param[in] PlatformConfig Config handle for platform specific information + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +SetRegisterForPerformanceProfileEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PERFORMANCE_PROFILE_FEATS PlatformProfile; + TABLE_ENTRY_DATA PciEntry; + + // Errors: Possible values in unused entry space, extra type features, value range checks. + // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. + ASSERT (((Entry->TokenPciEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0) && + (Entry->InitialValues[4] == 0)); + + GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader); + if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, + Entry->FixupEntry.TypeFeats.PerformanceProfileValue)) { + LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); + PciEntry.PciEntry = Entry->FixupEntry.PciEntry; + SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader); + } +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Perform the Core Counts Performance PCI Register Entry. + * + * @TableEntryTypeMethod{::CoreCountsPciRegister}. + * + * Check the performance profile. + * Check the actual core count to the range pair given, and apply if matched. + * + * @param[in] Entry The PCI register entry to perform + * @param[in] PlatformConfig Config handle for platform specific information + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +SetRegisterForCoreCountsPerformanceEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PERFORMANCE_PROFILE_FEATS PlatformProfile; + UINTN ActualCoreCount; + TABLE_ENTRY_DATA PciEntry; + + // Errors: Possible values in unused entry space, extra type features, value range checks. + // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. + ASSERT (((Entry->CoreCountEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0)); + + GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader); + if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, Entry->CoreCountEntry.TypeFeats.PerformanceProfileValue)) { + ActualCoreCount = GetActiveCoresInCurrentModule (StdHeader); + // Check if the actual core count is in either range. + if (IsEitherCountInRange (ActualCoreCount, ActualCoreCount, Entry->CoreCountEntry.CoreCounts.CoreRanges)) { + LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); + PciEntry.PciEntry = Entry->CoreCountEntry.PciEntry; + SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader); + } + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Perform the Processor Counts PCI Register Entry. + * + * @TableEntryTypeMethod{::ProcCountsPciRegister}. + * + * Check the performance profile. + * Check the actual processor count (not node count!) to the range pair given, and apply if matched. + * + * @param[in] Entry The PCI register entry to perform + * @param[in] PlatformConfig Config handle for platform specific information + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +SetRegisterForProcessorCountsEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PERFORMANCE_PROFILE_FEATS PlatformProfile; + UINTN ProcessorCount; + TABLE_ENTRY_DATA PciEntry; + + // Errors: Possible values in unused entry space, extra type features, value range checks. + // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. + ASSERT (((Entry->ProcCountEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0)); + + GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader); + if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, Entry->ProcCountEntry.TypeFeats.PerformanceProfileValue)) { + ProcessorCount = GetNumberOfProcessors (StdHeader); + // Check if the actual processor count is in either range. + if (IsEitherCountInRange (ProcessorCount, ProcessorCount, Entry->ProcCountEntry.ProcessorCounts.ProcessorCountRanges)) { + LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); + PciEntry.PciEntry = Entry->ProcCountEntry.PciEntry; + SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader); + } + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Perform the Compute Unit Counts PCI Register Entry. + * + * @TableEntryTypeMethod{::CompUnitCountsPciRegister}. + * + * Check the entry's performance profile features and the compute unit count + * to the platform's and do the PCI register entry if they match. + * + * @param[in] Entry The PCI register entry to perform + * @param[in] PlatformConfig Config handle for platform specific information + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +SetRegisterForComputeUnitCountsEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PERFORMANCE_PROFILE_FEATS PlatformProfile; + UINTN ComputeUnitCount; + TABLE_ENTRY_DATA PciEntry; + + // Errors: Possible values in unused entry space, extra type features, value range checks. + // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. + ASSERT (((Entry->CompUnitCountEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0)); + + GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader); + if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, Entry->CompUnitCountEntry.TypeFeats.PerformanceProfileValue)) { + ComputeUnitCount = GetNumberOfCompUnitsInCurrentModule (StdHeader); + // Check if the actual compute unit count is in either range. + if (IsEitherCountInRange (ComputeUnitCount, ComputeUnitCount, Entry->CompUnitCountEntry.ComputeUnitCounts.ComputeUnitRanges)) { + LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); + PciEntry.PciEntry = Entry->CompUnitCountEntry.PciEntry; + SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader); + } + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Perform the Compute Unit Counts MSR Register Entry. + * + * @TableEntryTypeMethod{::CompUnitCountsMsr}. + * + * Check the entry's compute unit count to the platform's and do the + * MSR entry if they match. + * + * @param[in] Entry The PCI register entry to perform + * @param[in] PlatformConfig Config handle for platform specific information + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +SetMsrForComputeUnitCountsEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINTN ComputeUnitCount; + TABLE_ENTRY_DATA MsrEntry; + + ComputeUnitCount = GetNumberOfCompUnitsInCurrentModule (StdHeader); + // Check if the actual compute unit count is in either range. + if (IsEitherCountInRange (ComputeUnitCount, ComputeUnitCount, Entry->CompUnitCountMsrEntry.ComputeUnitCounts.ComputeUnitRanges)) { + LibAmdMemFill (&MsrEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); + MsrEntry.MsrEntry = Entry->CompUnitCountMsrEntry.MsrEntry; + SetRegisterForMsrEntry (&MsrEntry, PlatformConfig, StdHeader); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * Returns the platform features list of the currently running processor core. + * + * @param[out] Features The Features supported by this platform + * @param[in] PlatformConfig Config handle for platform specific information + * @param[in] StdHeader Header for library and services + * + */ +VOID +GetPlatformFeatures ( + OUT PLATFORM_FEATS *Features, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + UINT32 CapabilityReg; + UINT32 Link; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + UINT32 CoreCount; + + // Start with none. + Features->PlatformValue = 0; + + switch (PlatformConfig->PlatformProfile.PlatformControlFlowMode) { + case Nfcm: + Features->PlatformFeatures.PlatformNfcm = 1; + break; + case UmaDr: + Features->PlatformFeatures.PlatformUma = 1; + break; + case UmaIfcm: + Features->PlatformFeatures.PlatformUmaIfcm = 1; + break; + case Ifcm: + Features->PlatformFeatures.PlatformIfcm = 1; + break; + case Iommu: + Features->PlatformFeatures.PlatformIommu = 1; + break; + default: + ASSERT (FALSE); + } + // Check - Single Link? + // This is based on the implemented links on the package regardless of their + // connection status. All processors must match the BSP, so we only check it and + // not the current node. We don't care exactly how many links there are, as soon + // as we find more than one we are done. + Link = 0; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, PCI_DEV_BASE, FUNC_0, 0); + // Until either all capabilities are done or until the desired link is found, + // keep looking for HT Host Capabilities. + while (Link < 2) { + LibAmdPciFindNextCap (&PciAddress, StdHeader); + if (PciAddress.AddressValue != ILLEGAL_SBDFO) { + LibAmdPciRead (AccessWidth32, PciAddress, &CapabilityReg, StdHeader); + if ((CapabilityReg & 0xE00000FF) == 0x20000008) { + Link++; + } + // A capability other than an HT capability, keep looking. + } else { + // end of capabilities + break; + } + } + if (Link < 2) { + Features->PlatformFeatures.PlatformSingleLink = 1; + } else { + Features->PlatformFeatures.PlatformMultiLink = 1; + } + + // Set the legacy core count bits. + GetActiveCoresInCurrentSocket (&CoreCount, StdHeader); + switch (CoreCount) { + case 1: + Features->PlatformFeatures.PlatformSingleCore = 1; + break; + case 2: + Features->PlatformFeatures.PlatformDualCore = 1; + break; + default: + Features->PlatformFeatures.PlatformMultiCore = 1; + } + + // + // Get some specific platform type info, VC...etc. + // + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + ASSERT (FamilySpecificServices != NULL); + FamilySpecificServices->GetPlatformTypeSpecificInfo (FamilySpecificServices, Features, StdHeader); + +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Checks if a register table entry applies to the executing core. + * + * This function uses a combination of logical ID and platform features to + * determine whether or not a register table entry applies to the executing core. + * + * @param[in] CoreCpuRevision The current core's logical ID + * @param[in] EntryCpuRevision The entry's desired logical IDs + * @param[in] PlatformFeatures The platform features + * @param[in] EntryFeatures The entry's desired platform features + * + * @retval TRUE This entry should be applied + * @retval FALSE This entry does not apply + * + */ +BOOLEAN +STATIC +DoesEntryMatchPlatform ( + IN CPU_LOGICAL_ID CoreCpuRevision, + IN CPU_LOGICAL_ID EntryCpuRevision, + IN PLATFORM_FEATS PlatformFeatures, + IN PLATFORM_FEATS EntryFeatures + ) +{ + BOOLEAN Result; + + Result = FALSE; + + if (((CoreCpuRevision.Family & EntryCpuRevision.Family) != 0) && + ((CoreCpuRevision.Revision & EntryCpuRevision.Revision) != 0)) { + if (EntryFeatures.PlatformFeatures.AndPlatformFeats == 0) { + // Match if ANY entry feats match a platform feat (an OR test) + if ((EntryFeatures.PlatformValue & PlatformFeatures.PlatformValue) != 0) { + Result = TRUE; + } + } else { + // Match if ALL entry feats match a platform feat (an AND test) + if ((EntryFeatures.PlatformValue & ~(AMD_PF_AND)) == + (EntryFeatures.PlatformValue & PlatformFeatures.PlatformValue)) { + Result = TRUE; + } + } + } + + return Result; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Checks register table entry type specific criteria to the platform. + * + * Entry Data Type implementer methods can use this generically to check their own + * specific criteria. The method collects the actual platform characteristics and + * provides them along with the table entry's criteria to this service. + * + * There are a couple considerations for any implementer method using this service. + * The criteria value has to be representable as a UINT32. The MSB, Bit 31, has to + * be used as a AND test request if set in the entry. (The platform value should never + * have that bit set.) + * + * @param[in] PlatformTypeSpecificFeatures The platform features + * @param[in] EntryTypeFeatures The entry's desired platform features + * + * @retval TRUE This entry should be applied + * @retval FALSE This entry does not apply + * + */ +BOOLEAN +DoesEntryTypeSpecificInfoMatch ( + IN UINT32 PlatformTypeSpecificFeatures, + IN UINT32 EntryTypeFeatures + ) +{ + BOOLEAN Result; + + Result = FALSE; + + if ((EntryTypeFeatures & BIT31) == 0) { + // Match if ANY entry feats match a platform feat (an OR test) + if ((EntryTypeFeatures & PlatformTypeSpecificFeatures) != 0) { + Result = TRUE; + } + } else { + // Match if ALL entry feats match a platform feat (an AND test) + if ((EntryTypeFeatures & ~(BIT31)) == (EntryTypeFeatures & PlatformTypeSpecificFeatures)) { + Result = TRUE; + } + } + return Result; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Determine this core's Selector matches. + * + * @param[in] Selector Is the current core this selector type? + * @param[in] StdHeader Config handle for library and services. + * + * @retval TRUE Yes, it is. + * @retval FALSE No, it is not. + */ +BOOLEAN +STATIC +IsCoreSelector ( + IN TABLE_CORE_SELECTOR Selector, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + BOOLEAN Result; + AGESA_STATUS CalledStatus; + + Result = TRUE; + ASSERT (Selector < TableCoreSelectorMax); + + if ((Selector == PrimaryCores) && !IsCurrentCorePrimary (StdHeader)) { + Result = FALSE; + } + if ((Selector == CorePairPrimary) && !IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) { + Result = FALSE; + } + if ((Selector == BscCore) && (!IsBsp (StdHeader, &CalledStatus))) { + Result = FALSE; + } + return Result; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Set the registers for this core based on entries in a list of Register Tables. + * + * Determine the platform features and this core's logical id. Get the specific table + * entry type implementations for the logical model, which may be either generic (the ones + * in this file) or specific. + * + * Scan the tables starting the with ones for all cores and progressively narrowing the selection + * based on this core's role (ex. primary core). For a selected table, check for each entry + * matching the current core and platform, and call the implementer method to perform the + * register set operation if it matches. + * + * @param[in] PlatformConfig Config handle for platform specific information + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +SetRegistersFromTables ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + CPU_LOGICAL_ID CpuLogicalId; + PLATFORM_FEATS PlatformFeatures; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + TABLE_ENTRY_FIELDS *Entries; + TABLE_CORE_SELECTOR Selector; + TABLE_ENTRY_TYPE EntryType; + REGISTER_TABLE **TableHandle; + UINTN NumberOfEntries; + UINTN CurrentEntryCount; + TABLE_ENTRY_TYPE_DESCRIPTOR *TypeImplementer; + PF_DO_TABLE_ENTRY DoTableEntry[TableEntryTypeMax]; + + // Did you really mean to increase the size of ALL table entries??!! + // While it is not necessarily a bug to increase the size of table entries: + // - Is this warning a surprise? Please fix it. + // - If expected, is this really a feature which is worth the increase? Then let other entries also use the space. + ASSERT (sizeof (TABLE_ENTRY_DATA) == (MAX_ENTRY_TYPE_ITEMS32 * sizeof (UINT32))); + + PlatformFeatures.PlatformValue = 0; + GetLogicalIdOfCurrentCore (&CpuLogicalId, StdHeader); + GetPlatformFeatures (&PlatformFeatures, PlatformConfig, StdHeader); + GetCpuServicesFromLogicalId (&CpuLogicalId, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + + // Build a non-sparse table of implementer methods, so we don't have to keep searching. + // It is a bug to not include a descriptor for a type that is in the table (but the + // descriptor can point to a non-assert stub). + // Also, it is not a bug to have no register table implementations, but it is a bug to have none and call this routine. + for (EntryType = MsrRegister; EntryType < TableEntryTypeMax; EntryType++) { + DoTableEntry[EntryType] = (PF_DO_TABLE_ENTRY)CommonAssert; + } + TypeImplementer = FamilySpecificServices->TableEntryTypeDescriptors; + ASSERT (TypeImplementer != NULL); + while (TypeImplementer->EntryType < TableEntryTypeMax) { + DoTableEntry[TypeImplementer->EntryType] = TypeImplementer->DoTableEntry; + TypeImplementer++; + } + + for (Selector = AllCores; Selector < TableCoreSelectorMax; Selector++) { + if (IsCoreSelector (Selector, StdHeader)) { + // If the current core is the selected type of core, work the table list for tables for that type of core. + TableHandle = NULL; + Entries = GetNextRegisterTable (FamilySpecificServices, Selector, &TableHandle, &NumberOfEntries, StdHeader); + while (Entries != NULL) { + for (CurrentEntryCount = 0; CurrentEntryCount < NumberOfEntries; CurrentEntryCount++, Entries++) { + if (DoesEntryMatchPlatform (CpuLogicalId, Entries->CpuRevision, PlatformFeatures, Entries->Features)) { + // The entry matches this config, Do It! + // Find the implementer for this entry type and pass the entry data to it. + ASSERT (Entries->EntryType < TableEntryTypeMax); + DoTableEntry[Entries->EntryType] (&Entries->Entry, PlatformConfig, StdHeader); + } + } + Entries = GetNextRegisterTable (FamilySpecificServices, Selector, &TableHandle, &NumberOfEntries, StdHeader); + } + } else { + // Once a selector does not match the current core, quit looking. + break; + } + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Set the registers for this core based on entries in a list of Register Tables. + * + * This function acts as a wrapper for calling the SetRegistersFromTables + * routine at AmdInitEarly. + * + * @param[in] FamilyServices The current Family Specific Services. + * @param[in] EarlyParams Service parameters. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +SetRegistersFromTablesAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_TESTPOINT (TpProcCpuProcessRegisterTables, StdHeader); + SetRegistersFromTables (&EarlyParams->PlatformConfig, StdHeader); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h new file mode 100644 index 0000000..42a4ae6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.h @@ -0,0 +1,1321 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Register Table Related Functions + * + * Contains code to initialize the CPU MSRs and PCI registers with BKDG recommended values + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_TABLE_H_ +#define _CPU_TABLE_H_ + +#define MAX_ENTRY_TYPE_ITEMS32 6 // The maximum number of initializer items for UINT32 entry data types. + +/** + * @page regtableimpl Register Table Implementation Guide + * + * This register table implementation is modular and extensible, so that support code as + * well as table data can be family specific or built out if not needed, and new types + * of table entries can be added with low overhead. Because many aspects are now generic, + * there can be common implementations for CPU revision and platform feature matching and for + * finding and iterating tables. + * + * @par Adding a new table entry type. + * + * To add a new table entry type follow these steps. + * <ul> + * <li> Add a member to the enum TABLE_ENTRY_TYPE which is a descriptive name of the entry's purpose + * or distinct characteristics. + * + * <li> Create an entry data struct with the customized data needed. For example, custom register designations, + * data and mask sizes, or feature comparisons. Name your struct by adding "_" and upper-casing the enum name + * and adding "_TYPE_ENTRY_DATA" at the end. + * + * <li> Add the entry data type as a member of the TABLE_ENTRY_DATA union. Be aware of the size of your + * entry data struct; all table entries in all tables will share any size increase you introduce! + * + * <li> If your data entry contains any member types except for UINT32, you can't use the generic first union member + * for the initializers that make up the actual tables (it's just UINT32's). The generic MSR entry is + * an example. Follow the steps below: + * + * <ul> + * <li> Make a union which has your entry data type as the first member. Use TABLE_ENTRY_DATA as the + * second member. Name this with your register followed by "_DATA_INITIALIZER". + * + * <li> Make a copy of TABLE_ENTRY_FIELDS, and rename it your register "_TYPE_ENTRY_INITIALIZER". Rename + * the TABLE_ENTRY_DATA member of that struct to have the type you created in the previous step. + * This type can be used to declare an array of entries and make a register table in some family specific + * file. + * </ul> + * + * <li> Add the descriptor that will link table entries of your data type to an implementation for it. + * <ul> + * <li> Find the options file which instantiates the CPU_SPECIFIC_SERVICES for each logical model that will + * support the new entry type. + * + * <li> From there find the instantiation of its TABLE_ENTRY_TYPE_DESCRIPTOR. Add a descriptor to the + * to the list for your new type. Provide the name of a function which will implement the + * entry data. The function name should reflect that it implements the action for the entry type. + * The function must be an instance of F_DO_TABLE_ENTRY. + * </ul> + * + * <li> Implement the function for your entry type data. (If parts of it are family specific add methods to + * CPU_SPECIFIC_SERVICES for that and implement them for each family or model required.) @n + * The definition of the function must conform to F_DO_TABLE_ENTRY. + * In the function preamble, include a cross reference to the entry enum: + * @code + * * + * * @TableEntryTypeMethod{::MyRegister} + * * + * @endcode + * + * </ul> + * + * @par Adding a new Register Table + * + * To add a new register table for a logical CPU model follow the steps below. + * + * <ul> + * <li> Find the options file which instantiates the CPU_SPECIFIC_SERVICES for the logical model that + * should include the table. + * + * <li> From there find the instantiation of its REGISTER_TABLE list. Add the name of the new register table. + * </ul> + * + */ + +/*------------------------------------------------------------------------------------------*/ +/* + * Define the supported table entries. + */ +/*------------------------------------------------------------------------------------------*/ + +/** + * These are the available types of table entries. + * + * Each type corresponds to: + * - a semantics for the type specific data, for example semantics for a Register value, + * Data value, and Mask value. + * - optionally, including a method for type specific matching criteria + * - a method for writing the desired update to the hardware. + * + * All types share in common a method to match CPU Family and Model and a method to match + * platform feature set. + * + */ +typedef enum { + MsrRegister, ///< Processor MSR registers. + PciRegister, ///< Processor Config Space registers. + FamSpecificWorkaround, ///< Processor Family Specific Workarounds which are @b not practical using the other types. + HtPhyRegister, ///< Processor HT Phy registers. + HtPhyRangeRegister, ///< Processor HT Phy range of contiguous registers (ex. 40h:48h). + DeemphasisRegister, ///< Processor Deemphasis register (HT Phy special case). + HtPhyFreqRegister, ///< Processor Frequency dependent HT Phy settings. + ProfileFixup, ///< Processor Performance Profile fixups to PCI Config Registers. + HtHostPciRegister, ///< Processor Ht Host capability registers (PCI Config). + HtHostPerfPciRegister, ///< Processor Ht Host capability registers which depend on performance features. + HtTokenPciRegister, ///< Processor Ht Link Token count registers. + CoreCountsPciRegister, ///< Processor PCI Config Registers which depend on core counts. + ProcCountsPciRegister, ///< Processor PCI Config Registers which depend on processor counts. + CompUnitCountsPciRegister, ///< Processor PCI Config Registers which depend on compute unit counts. + TokenPciRegister, ///< Processor northbridge Token Count register which may be dependent on connectivity. + HtFeatPciRegister, ///< Processor HT Link feature dependant PCI Config Registers. + HtPhyProfileRegister, ///< Processor HT Phy registers which depend on performance features. + HtLinkPciRegister, ///< Processor HT Link registers (one per link) not part of HT Host capability. + CompUnitCountsMsr, ///< Processor MSRs which depend on compute unit counts. + TableEntryTypeMax ///< Not a valid entry type, use for limit checking. +} TABLE_ENTRY_TYPE; + +/*------------------------------------------------------------------------------------------*/ +/* + * Useful types and defines: Selectors, Platform Features, and type specific features. + */ +/*------------------------------------------------------------------------------------------*/ + +/** + * Select tables for the current core. + * + * This allows more efficient register table processing, by allowing cores to skip + * redundantly setting PCI registers, for example. This feature is not intended to + * be relied on for function: it is valid to have a single register table with all settings + * processed by every core; it's just slower. + * + */ +typedef enum { + AllCores, ///< Select only tables which apply to all cores. + CorePairPrimary, ///< Select tables which apply to the primary core of a compute unit (SharedC, SharedNc). + PrimaryCores, ///< Select tables which apply to primary cores. + BscCore, ///< Select tables which apply to the boot core. + TableCoreSelectorMax ///< Not a valid selector, use for limit checking. +} TABLE_CORE_SELECTOR; + +// Initializer bit pattern values for platform features. +// Keep in synch with the PLATFORM_FEATURES struct! + +// The 5 control flow modes. +#define AMD_PF_NFCM BIT0 +#define AMD_PF_UMA BIT1 // UMA_DR +#define AMD_PF_UMA_IFCM BIT2 +#define AMD_PF_IFCM BIT3 +#define AMD_PF_IOMMU BIT4 +// Degree of HT connectivity possible. +#define AMD_PF_SINGLE_LINK BIT5 +#define AMD_PF_MULTI_LINK BIT6 +// For some legacy MSRs, define a couple core count bits. Do not continue adding +// core counts to the platform feats, if you need more than this design a table entry type. +// Here, provide exactly 1, exactly 2, or anything else. +#define AMD_PF_SINGLE_CORE BIT7 +#define AMD_PF_DUAL_CORE BIT8 +#define AMD_PF_MULTI_CORE BIT9 + +// Not a platform type, but treat all others as AND +#define AMD_PF_AND BIT31 + +#define AMD_PF_ALL (AMD_PF_NFCM | \ + AMD_PF_UMA | \ + AMD_PF_UMA_IFCM | \ + AMD_PF_IFCM | \ + AMD_PF_IOMMU | \ + AMD_PF_SINGLE_LINK | \ + AMD_PF_MULTI_LINK | \ + AMD_PF_SINGLE_CORE | \ + AMD_PF_DUAL_CORE | \ + AMD_PF_MULTI_CORE) +// Do not include AMD_PF_AND in AMD_PF_ALL ! + +/** + * The current platform features. + * + * Keep this in sync with defines above that are used in the initializers! + * + * The comments with the bit number are useful for the computing the reserved member size, but + * do not write code that assumes you know what bit number one of these members is. + * + * These platform features are standard for all logical families and models. + */ +typedef struct { + UINT32 PlatformNfcm:1; ///< BIT_0 Normal Flow Control Mode. + UINT32 PlatformUma:1; ///< BIT_1 UMA (Display Refresh) Flow Control. + UINT32 PlatformUmaIfcm:1; ///< BIT_2 UMA using Isochronous Flow Control. + UINT32 PlatformIfcm:1; ///< BIT_3 Isochronous Flow Control Mode (not UMA). + UINT32 PlatformIommu:1; ///< BIT_4 IOMMU (a special case Isochronous mode). + UINT32 PlatformSingleLink:1; ///< BIT_5 The processor is in a package which implements only a single HT Link. + UINT32 PlatformMultiLink:1; ///< BIT_6 The processor is in a package which implements more than one HT Link. + UINT32 PlatformSingleCore:1; ///< BIT_7 Single Core processor, for legacy entries. + UINT32 PlatformDualCore:1; ///< BIT_8 Dual Core processor, for legacy entries. + UINT32 PlatformMultiCore:1; ///< BIT_9 More than dual Core processor, for legacy entries. + UINT32 :(30 - 9); ///< The possibilities are (not quite) endless. + UINT32 AndPlatformFeats:1; ///< BIT_31 +} PLATFORM_FEATURES; + +/** + * Platform Features + */ +typedef union { + UINT32 PlatformValue; ///< Describe Platform Features in UINT32. + ///< This one goes first, because then initializers use it automatically for the union. + PLATFORM_FEATURES PlatformFeatures; ///< Describe Platform Features in structure +} PLATFORM_FEATS; + +// Sublink Types are defined so they can match each attribute against either +// sublink zero or one. The table entry must contain the correct matching +// values based on the register. This is available in the BKDG, for each register +// which sublink it controls. If the register is independent of sublink, OR values +// together or use HT_LINKTYPE_ALL to match if either sublink matches (ex. E0 - E5). +// Sublink 0 types, bits 0 thru 14 +#define HTPHY_LINKTYPE_SL0_HT3 BIT0 +#define HTPHY_LINKTYPE_SL0_HT1 BIT1 +#define HTPHY_LINKTYPE_SL0_COHERENT BIT2 +#define HTPHY_LINKTYPE_SL0_NONCOHERENT BIT3 +#define HTPHY_LINKTYPE_SL0_LINK0 BIT4 +#define HTPHY_LINKTYPE_SL0_LINK1 BIT5 +#define HTPHY_LINKTYPE_SL0_LINK2 BIT6 +#define HTPHY_LINKTYPE_SL0_LINK3 BIT7 +#define HTPHY_LINKTYPE_SL0_INTERNAL BIT8 +#define HTPHY_LINKTYPE_SL0_EXTERNAL BIT9 +#define HTPHY_LINKTYPE_SL0_AND BIT15 + +// SubLink 1 types, bits 16 thru 30 +#define HTPHY_LINKTYPE_SL1_HT3 BIT16 +#define HTPHY_LINKTYPE_SL1_HT1 BIT17 +#define HTPHY_LINKTYPE_SL1_COHERENT BIT18 +#define HTPHY_LINKTYPE_SL1_NONCOHERENT BIT19 +#define HTPHY_LINKTYPE_SL1_LINK4 BIT20 +#define HTPHY_LINKTYPE_SL1_LINK5 BIT21 +#define HTPHY_LINKTYPE_SL1_LINK6 BIT22 +#define HTPHY_LINKTYPE_SL1_LINK7 BIT23 +#define HTPHY_LINKTYPE_SL1_INTERNAL BIT24 +#define HTPHY_LINKTYPE_SL1_EXTERNAL BIT25 +#define HTPHY_LINKTYPE_SL1_AND BIT31 + +#define HTPHY_LINKTYPE_SL0_ALL (HTPHY_LINKTYPE_SL0_HT3 | \ + HTPHY_LINKTYPE_SL0_HT1 | \ + HTPHY_LINKTYPE_SL0_COHERENT | \ + HTPHY_LINKTYPE_SL0_NONCOHERENT | \ + HTPHY_LINKTYPE_SL0_LINK0 | \ + HTPHY_LINKTYPE_SL0_LINK1 | \ + HTPHY_LINKTYPE_SL0_LINK2 | \ + HTPHY_LINKTYPE_SL0_LINK3 | \ + HTPHY_LINKTYPE_SL0_INTERNAL | \ + HTPHY_LINKTYPE_SL0_EXTERNAL) +#define HTPHY_LINKTYPE_SL1_ALL (HTPHY_LINKTYPE_SL1_HT3 | \ + HTPHY_LINKTYPE_SL1_HT1 | \ + HTPHY_LINKTYPE_SL1_COHERENT | \ + HTPHY_LINKTYPE_SL1_NONCOHERENT | \ + HTPHY_LINKTYPE_SL1_LINK4 | \ + HTPHY_LINKTYPE_SL1_LINK5 | \ + HTPHY_LINKTYPE_SL1_LINK6 | \ + HTPHY_LINKTYPE_SL1_LINK7 | \ + HTPHY_LINKTYPE_SL1_INTERNAL | \ + HTPHY_LINKTYPE_SL1_EXTERNAL) +#define HTPHY_LINKTYPE_ALL (HTPHY_LINKTYPE_SL0_ALL | HTPHY_LINKTYPE_SL1_ALL) + +#define HTPHY_REGISTER_MAX 0x0000FFFFul +/** + * HT PHY Link Features + */ +typedef struct { + UINT32 HtPhySL0Ht3:1; ///< Ht Phy Sub-link 0 Ht3 + UINT32 HtPhySL0Ht1:1; ///< Ht Phy Sub-link 0 Ht1 + UINT32 HtPhySL0Coh:1; ///< Ht Phy Sub-link 0 Coherent + UINT32 HtPhySL0NonCoh:1; ///< Ht Phy Sub-link 0 NonCoherent + UINT32 HtPhySL0Link0:1; ///< Ht Phy Sub-link 0 specifically for node link 0. + UINT32 HtPhySL0Link1:1; ///< Ht Phy Sub-link 0 specifically for node link 1. + UINT32 HtPhySL0Link2:1; ///< Ht Phy Sub-link 0 specifically for node link 2. + UINT32 HtPhySL0Link3:1; ///< Ht Phy Sub-link 0 specifically for node link 3. + UINT32 HtPhySL0Internal:1; ///< Ht Phy Sub-link 0 is internal link. Intended for IDS support. + UINT32 HtPhySL0External:1; ///< Ht Phy Sub-link 0 is external link. Intended for IDS support. + UINT32 :(14 - 9); ///< Ht Phy Sub-link 0 Pad + UINT32 HtPhySL0And:1; ///< Ht Phy feature match should match all selected features, for sub-link 0. + UINT32 HtPhySL1Ht3:1; ///< Ht Phy Sub-link 1 Ht3 + UINT32 HtPhySL1Ht1:1; ///< Ht Phy Sub-link 1 Ht1 + UINT32 HtPhySL1Coh:1; ///< Ht Phy Sub-link 1 Coherent + UINT32 HtPhySL1NonCoh:1; ///< Ht Phy Sub-link 1 NonCoherent + UINT32 HtPhySL1Link4:1; ///< Ht Phy Sub-link 1 specifically for node link 4. + UINT32 HtPhySL1Link5:1; ///< Ht Phy Sub-link 1 specifically for node link 5. + UINT32 HtPhySL1Link6:1; ///< Ht Phy Sub-link 1 specifically for node link 6. + UINT32 HtPhySL1Link7:1; ///< Ht Phy Sub-link 1 specifically for node link 7. + UINT32 HtPhySL1Internal:1; ///< Ht Phy Sub-link 1 is internal link. Intended for IDS support. + UINT32 HtPhySL1External:1; ///< Ht Phy Sub-link 1 is external link. Intended for IDS support. + UINT32 :(30 - 25); ///< Ht Phy Sub-link 1 Pad + UINT32 HtPhySL1And:1; ///< Ht Phy feature match should match all selected features, for sub-link 1. +} HT_PHY_LINK_FEATURES; + +/** + * Ht Phy Link Features + */ +typedef union { + UINT32 HtPhyLinkValue; ///< Describe HY Phy Features in UINT32. + ///< This one goes first, because then initializers use it automatically for the union. + HT_PHY_LINK_FEATURES HtPhyLinkFeatures; ///< Describe HT Phy Features in structure. +} HT_PHY_LINK_FEATS; + +// DB Level for initializing Deemphasis +// This must be in sync with DEEMPHASIS_FEATURES and PLATFORM_DEEMPHASIS_LEVEL (agesa.h) +#define DEEMPHASIS_LEVEL_NONE BIT0 +#define DEEMPHASIS_LEVEL__3 BIT1 +#define DEEMPHASIS_LEVEL__6 BIT2 +#define DEEMPHASIS_LEVEL__8 BIT3 +#define DEEMPHASIS_LEVEL__11 BIT4 +#define DEEMPHASIS_LEVEL__11_8 BIT5 +#define DCV_LEVEL_NONE BIT16 +#define DCV_LEVEL__2 BIT17 +#define DCV_LEVEL__3 BIT18 +#define DCV_LEVEL__5 BIT19 +#define DCV_LEVEL__6 BIT20 +#define DCV_LEVEL__7 BIT21 +#define DCV_LEVEL__8 BIT22 +#define DCV_LEVEL__9 BIT23 +#define DCV_LEVEL__11 BIT24 +// Note that an "AND" feature doesn't make any sense, levels are mutually exclusive. + +// An error check value. +#define DEEMPHASIS_LEVELS_ALL (DEEMPHASIS_LEVEL_NONE | \ + DEEMPHASIS_LEVEL__3 | \ + DEEMPHASIS_LEVEL__6 | \ + DEEMPHASIS_LEVEL__8 | \ + DEEMPHASIS_LEVEL__11 | \ + DEEMPHASIS_LEVEL__11_8) + +#define DCV_LEVELS_ALL (DCV_LEVEL_NONE | \ + DCV_LEVEL__2 | \ + DCV_LEVEL__3 | \ + DCV_LEVEL__5 | \ + DCV_LEVEL__6 | \ + DCV_LEVEL__7 | \ + DCV_LEVEL__8 | \ + DCV_LEVEL__9 | \ + DCV_LEVEL__11) + +#define VALID_DEEMPHASIS_LEVELS (DEEMPHASIS_LEVELS_ALL | DCV_LEVELS_ALL) + +/** + * Deemphasis Ht Phy Link Deemphasis. + * + * This must be in sync with defines above and ::PLATFORM_DEEMPHASIS_LEVEL (agesa.h) + */ +typedef struct { + UINT32 DeemphasisLevelNone:1; ///< The deemphasis level None. + UINT32 DeemphasisLevelMinus3:1; ///< The deemphasis level minus 3 db. + UINT32 DeemphasisLevelMinus6:1; ///< The deemphasis level minus 6 db. + UINT32 DeemphasisLevelMinus8:1; ///< The deemphasis level minus 8 db. + UINT32 DeemphasisLevelMinus11:1; ///< The deemphasis level minus 11 db. + UINT32 DeemphasisLevelMinus11w8:1; ///< The deemphasis level minus 11 db, minus 8 precursor. + UINT32 :(15 - 5); ///< reserved. + UINT32 DcvLevelNone:1; ///< The level for DCV None. + UINT32 DcvLevelMinus2:1; ///< The level for DCV minus 2 db. + UINT32 DcvLevelMinus3:1; ///< The level for DCV minus 3 db. + UINT32 DcvLevelMinus5:1; ///< The level for DCV minus 5 db. + UINT32 DcvLevelMinus6:1; ///< The level for DCV minus 6 db. + UINT32 DcvLevelMinus7:1; ///< The level for DCV minus 7 db. + UINT32 DcvLevelMinus8:1; ///< The level for DCV minus 8 db. + UINT32 DcvLevelMinus9:1; ///< The level for DCV minus 9 db. + UINT32 DcvLevelMinus11:1; ///< The level for DCV minus 11 db. + UINT32 :(15 - 8); ///< reserved. +} DEEMPHASIS_FEATURES; + +/** + * Deemphasis Ht Phy Link Features. + */ +typedef union { + UINT32 DeemphasisValues; ///< Initialize HT Deemphasis in UINT32. + DEEMPHASIS_FEATURES DeemphasisLevels; ///< HT Deemphasis levels. +} DEEMPHASIS_FEATS; + +// Initializer bit patterns for PERFORMANCE_PROFILE_FEATS. +#define PERFORMANCE_REFRESH_REQUEST_32B BIT0 +#define PERFORMANCE_PROBEFILTER BIT1 +#define PERFORMANCE_L3_CACHE BIT2 +#define PERFORMANCE_NO_L3_CACHE BIT3 +#define PERFORMANCE_MCT_ISOC_VARIABLE BIT4 +#define PERFORMANCE_IS_WARM_RESET BIT5 +#define PERFORMANCE_VRM_HIGH_SPEED_ENABLE BIT6 +#define PERFORMANCE_NB_PSTATES_ENABLE BIT7 +#define PERFORMANCE_AND BIT31 + +#define PERFORMANCE_PROFILE_ALL (PERFORMANCE_REFRESH_REQUEST_32B | \ + PERFORMANCE_PROBEFILTER | \ + PERFORMANCE_L3_CACHE | \ + PERFORMANCE_NO_L3_CACHE | \ + PERFORMANCE_MCT_ISOC_VARIABLE | \ + PERFORMANCE_IS_WARM_RESET | \ + PERFORMANCE_VRM_HIGH_SPEED_ENABLE | \ + PERFORMANCE_NB_PSTATES_ENABLE) + +/** + * Performance Profile specific Type Features. + * + * Register settings for the different control flow modes can have additional dependencies + */ +typedef struct { + UINT32 RefreshRequest32Byte:1; ///< BIT_0. Display Refresh Requests use 32 bytes (32BE). + UINT32 ProbeFilter:1; ///< BIT_1 Probe Filter will be enabled. + UINT32 L3Cache:1; ///< BIT_2 L3 Cache is present. + UINT32 NoL3Cache:1; ///< BIT_3 L3 Cache is NOT present. + UINT32 MctIsocVariable:1; ///< BIT_4 Mct Isoc Read Priority set to variable. + UINT32 IsWarmReset:1; ///< BIT_5 This boot is on a warm reset, cold reset pass is already completed. + UINT32 VrmHighSpeed:1; ///< BIT_6 Select high speed VRM. + UINT32 NbPstates:1; ///< BIT_7 Northbridge PStates are enabled + UINT32 :(30 - 7); ///< available for future expansion. + UINT32 AndPerformanceFeats:1; ///< BIT_31. AND other selected features. +} PERFORMANCE_PROFILE_FEATURES; + +/** + * Performance Profile features. + */ +typedef union { + UINT32 PerformanceProfileValue; ///< Initializer value. + PERFORMANCE_PROFILE_FEATURES PerformanceProfileFeatures; ///< The performance profile features. +} PERFORMANCE_PROFILE_FEATS; + +/** + * Package Type Features + * + */ +typedef struct { + UINT32 PkgType0:1; ///< Package Type 0 + UINT32 PkgType1:1; ///< Package Type 1 + UINT32 PkgType2:1; ///< Package Type 2 + UINT32 PkgType3:1; ///< Package Type 3 + UINT32 PkgType4:1; ///< Package Type 4 + UINT32 PkgType5:1; ///< Package Type 5 + UINT32 PkgType6:1; ///< Package Type 6 + UINT32 PkgType7:1; ///< Package Type 7 + UINT32 PkgType8:1; ///< Package Type 8 + UINT32 PkgType9:1; ///< Package Type 9 + UINT32 PkgType10:1; ///< Package Type 10 + UINT32 PkgType11:1; ///< Package Type 11 + UINT32 PkgType12:1; ///< Package Type 12 + UINT32 PkgType13:1; ///< Package Type 13 + UINT32 PkgType14:1; ///< Package Type 14 + UINT32 PkgType15:1; ///< Package Type 15 + UINT32 Reserved:15; ///< Package Type Reserved + UINT32 ReservedAndFeats:1; ///< BIT_31. AND other selected features. Always zero here. +} PACKAGE_TYPE_FEATURES; + +// Initializer Values for Package Type +#define PACKAGE_TYPE_ALL 0XFFFF ///< Package Type apply all packages + +// Initializer Values for Ht Host Pci Config Registers +#define HT_HOST_FEAT_COHERENT BIT0 +#define HT_HOST_FEAT_NONCOHERENT BIT1 +#define HT_HOST_FEAT_GANGED BIT2 +#define HT_HOST_FEAT_UNGANGED BIT3 +#define HT_HOST_FEAT_HT3 BIT4 +#define HT_HOST_FEAT_HT1 BIT5 +#define HT_HOST_AND BIT31 + +#define HT_HOST_FEATURES_ALL (HT_HOST_FEAT_COHERENT | \ + HT_HOST_FEAT_NONCOHERENT | \ + HT_HOST_FEAT_GANGED | \ + HT_HOST_FEAT_UNGANGED | \ + HT_HOST_FEAT_HT3 | \ + HT_HOST_FEAT_HT1) + +/** + * HT Host PCI register features. + * + * Links which are not connected do not match any of these features. + */ +typedef struct { + UINT32 Coherent:1; ///< BIT_0 Apply to links with a coherent connection. + UINT32 NonCoherent:1; ///< BIT_1 Apply to links with a non-coherent connection. + UINT32 Ganged:1; ///< BIT_2 Apply to links with a ganged connection. + UINT32 UnGanged:1; ///< BIT_3 Apply to links with a unganged connection. + UINT32 Ht3:1; ///< BIT_4 Apply to links with HT3 frequency (> 1000 MHz) + UINT32 Ht1:1; ///< BIT_5 Apply to links with HT1 frequency (< 1200 MHz) + UINT32 :(30 - 5); ///< Future expansion. + UINT32 AndHtHostFeats:1; ///< BIT_31. AND other selected features. +} HT_HOST_FEATURES; + +/** + * HT Host features for table data. + */ +typedef union { + UINT32 HtHostValue; ///< Initializer value. + HT_HOST_FEATURES HtHostFeatures; ///< The HT Host Features. +} HT_HOST_FEATS; + +// Core Range Initializer values. +#define COUNT_RANGE_LOW 0ul +#define COUNT_RANGE_HIGH 0xFFul + +// A count range matching none is often useful as the second range, matching will then be +// based on the first range. A count range all is provided as a first range for default settings. +#define COUNT_RANGE_NONE ((((COUNT_RANGE_HIGH) << 8) | (COUNT_RANGE_HIGH)) << 16) +#define COUNT_RANGE_ALL (((COUNT_RANGE_HIGH) << 8) | (COUNT_RANGE_LOW)) +#define IGNORE_FREQ_0 (((COUNT_RANGE_HIGH) << 8) | (COUNT_RANGE_HIGH)) +#define IGNORE_PROCESSOR_0 (((COUNT_RANGE_HIGH) << 8) | (COUNT_RANGE_HIGH)) + +#define CORE_RANGE_0(min, max) ((((UINT32)(max)) << 8) | (UINT32)(min)) +#define CORE_RANGE_1(min, max) (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16) +#define PROCESSOR_RANGE_0(min, max) ((((UINT32)(max)) << 8) | (UINT32)(min)) +#define PROCESSOR_RANGE_1(min, max) (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16) +#define DEGREE_RANGE_0(min, max) ((((UINT32)(max)) << 8) | (UINT32)(min)) +#define DEGREE_RANGE_1(min, max) (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16) +#define FREQ_RANGE_0(min, max) ((((UINT32)(max)) << 8) | (UINT32)(min)) +#define FREQ_RANGE_1(min, max) (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16) +#define COMPUTE_UNIT_RANGE_0(min, max) ((((UINT32)(max)) << 8) | (UINT32)(min)) +#define COMPUTE_UNIT_RANGE_1(min, max) (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16) + +/** + * Count Range Feature, two count ranges for core counts, processor counts, or node counts. + */ +typedef struct { + UINT32 Range0Min:8; ///< The minimum of the first count range. + UINT32 Range0Max:8; ///< The maximum of the first count range. + UINT32 Range1Min:8; ///< The minimum of the second count range. + UINT32 Range1Max:8; ///< The maximum of the second count range. +} COUNT_RANGE_FEATURE; + +/** + * Core Count Ranges for table data. + * + * Provide a pair of core count ranges. If the actual core count is included in either range (OR), + * the feature should be considered a match. + */ +typedef union { + UINT32 CoreRangeValue; ///< Initializer value. + COUNT_RANGE_FEATURE CoreRanges; ///< The Core Counts. +} CORE_COUNT_RANGES; + +/** + * Processor count ranges for table data. + * + * Provide a pair of processor count ranges. If the actual counts are included in either range (OR), + * the feature should be considered a match. + */ +typedef union { + UINT32 ProcessorCountRangeValue; ///< Initializer value. + COUNT_RANGE_FEATURE ProcessorCountRanges; ///< The Processor and Node Counts. +} PROCESSOR_COUNTS; + +/** + * Compute unit count ranges for table data. + * + * Provide a pair of compute unit count ranges. If the actual counts are included in either ranges (OR), + * the feature should be considered a match. + */ +typedef union { + UINT32 ComputeUnitRangeValue; ///< Initializer value. + COUNT_RANGE_FEATURE ComputeUnitRanges; ///< The Processor and Node Counts. +} COMPUTE_UNIT_COUNTS; + +/** + * Connectivity count ranges for table data. + * + * Provide a processor count range and a system degree range. The degree of a system is + * the maximum degree of any node. The degree of a node is the number of nodes to which + * it is directly connected (not considering width or redundant links). If both the actual + * counts are included in each range (AND), the feature should be considered a match. + */ +typedef union { + UINT32 ConnectivityCountRangeValue; ///< Initializer value. + COUNT_RANGE_FEATURE ConnectivityCountRanges; ///< The Processor and Degree Counts. +} CONNECTIVITY_COUNT; + +/** + * HT Frequency Count Range. + * + * Provide a pair of Frequency count ranges, with the frequency encoded as an HT Frequency value + * (such as would be programmed into the HT Host Link Frequency register). By converting a NB freq, + * the same count can be applied for it. If the actual value is included in either range + */ +typedef union { + UINT32 HtFreqCountRangeValue; ///< Initializer value. + COUNT_RANGE_FEATURE HtFreqCountRanges; ///< The HT Freq counts. +} HT_FREQ_COUNTS; + +/*------------------------------------------------------------------------------------------*/ +/* + * The specific data for each table entry. + */ +/*------------------------------------------------------------------------------------------*/ + +/** + * Make an extra type so we can use compilers that don't support designated initializers. + * + * All the entry type unions are no more than 5 UINT32's in size. For entry types which are a struct of UINT32's, + * this type can be used so that initializers can be declared TABLE_ENTRY_FIELDS, instead of a special non-union type. + * A non-union type then has to be cast back to TABLE_ENTRY_FIELDS in order to process the table, and you can't mix + * entry types with non-union initializers in the same table with any other type. + * + * If the entry type contains anything but UINT32's, then it must have a non-union initializer type for creating the + * actual tables. For example, MSR entry has UINT64 and workaround entry has a function pointer. + */ +typedef UINT32 GENERIC_TYPE_ENTRY_INITIALIZER[MAX_ENTRY_TYPE_ITEMS32]; + +/** + * Table Entry Data for MSR Registers. + * + * Apply data to register after mask, for MSRs. + */ +typedef struct { + UINT32 Address; ///< MSR address + UINT64 Data; ///< Data to set in the MSR + UINT64 Mask; ///< Mask to be applied to the MSR. Set every bit of all updated fields. +} MSR_TYPE_ENTRY_DATA; + +/** + * Table Entry Data for PCI Registers. + * + * Apply data to register after mask, for PCI Config registers. + */ +typedef struct { + PCI_ADDR Address; ///< Address should contain Function, Offset only. It will apply to all CPUs + UINT32 Data; ///< Data to be written into PCI device + UINT32 Mask; ///< Mask to be used before data write. Set every bit of all updated fields. +} PCI_TYPE_ENTRY_DATA; + +/** + * Table Entry Data for HT Phy Registers. + * + * Apply data to register after mask, for HT Phy registers, repeated for all active links. + */ +typedef struct { + HT_PHY_LINK_FEATS TypeFeats; ///< HT Phy Link Features + UINT32 Address; ///< Address of Ht Phy Register + UINT32 Data; ///< Data to be written into PCI device + UINT32 Mask; ///< Mask to be used before data write. Set every bit of all updated fields. +} HT_PHY_TYPE_ENTRY_DATA; + +/** + * Table Entry Data for HT Phy Register Ranges. + * + * Apply data to register after mask, for a range of HT Phy registers, repeated for all active links. + */ +typedef struct { + HT_PHY_LINK_FEATS TypeFeats; ///< HT Phy Link Features + UINT32 LowAddress; ///< Low address of Ht Phy Register range. + UINT32 HighAddress; ///< High address of register range. + UINT32 Data; ///< Data to be written into PCI device. + UINT32 Mask; ///< Mask to be used before data write. Set every bit of all updated fields. +} HT_PHY_RANGE_TYPE_ENTRY_DATA; + +/** + * Table Entry Data for HT Phy Deemphasis Registers. + * + * Apply data to register after mask, for HT Phy registers, repeated for all active links. + */ +typedef struct { + DEEMPHASIS_FEATS Levels; ///< The DCV and Deemphasis levels to match + HT_PHY_TYPE_ENTRY_DATA HtPhyEntry; ///< The HT Phy Entry to set the deemphasis values +} DEEMPHASIS_HT_PHY_TYPE_ENTRY_DATA; + +/** + * Table Entry Date for HT Phy Frequency Count Register updates. + * + * Compare the NB freq to a range, the HT freq to a range, the link features. + * Apply data to register after mask, if all three matched. + */ +typedef struct { + HT_FREQ_COUNTS HtFreqCounts; ///< Specify the HT Frequency range. + HT_FREQ_COUNTS NbFreqCounts; ///< Specify the NB Frequency range. + HT_PHY_TYPE_ENTRY_DATA HtPhyEntry; ///< The HT Phy register update to perform. +} HT_PHY_FREQ_TYPE_ENTRY_DATA; + +/** + * Table Entry Data for Profile Fixup Registers. + * + * If TypeFeats matches current config, apply data to register after mask for PCI Config registers. + */ +typedef struct { + PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features. + PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data. +} PROFILE_FIXUP_TYPE_ENTRY_DATA; + +/** + * A variation of PCI register for the HT Host registers. + * + * A setting to the HT Host buffer counts needs to be made to all the registers for + * all the links. There are also link specific criteria to check. + */ +typedef struct { + HT_HOST_FEATS TypeFeats; ///< Link Features. + PCI_ADDR Address; ///< Address of PCI Register to Fixed Up. + UINT32 Data; ///< Data to be written into PCI device + UINT32 Mask; ///< Mask to be used before data write. Set every bit of all updated fields. +} HT_HOST_PCI_TYPE_ENTRY_DATA; + +/** + * A variation of PCI register for the HT Host performance registers. + * + * A setting to the HT Host buffer counts needs to be made to all the registers for + * all the links. There are also link specific criteria to check. + */ +typedef struct { + PERFORMANCE_PROFILE_FEATS PerformanceFeats; ///< Performance Profile features. + HT_HOST_PCI_TYPE_ENTRY_DATA HtHostEntry; ///< Link Features. +} HT_HOST_PERFORMANCE_PCI_TYPE_ENTRY_DATA; + +/** + * A variation of HT Host PCI register for the Link Token registers. + * + * Use Link Features, Performance Fixup features, and processor counts to match entries. + * Link Features are iterated through the connected links. All the matching Link Token count + * registers are updated. + */ +typedef struct { + CONNECTIVITY_COUNT ConnectivityCount; ///< Specify Processor count and Degree count range. + PERFORMANCE_PROFILE_FEATS PerformanceFeats; ///< Performance Profile features. + HT_HOST_FEATS LinkFeats; ///< Link Features. + PCI_ADDR Address; ///< Address of PCI Register to Fixed Up. + UINT32 Data; ///< Data to be written into PCI device + UINT32 Mask; ///< Mask to be used before data write. Set every bit of all updated fields. +} HT_TOKEN_PCI_REGISTER; + +/** + * Core Count dependent PCI registers. + * + */ +typedef struct { + PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features. + CORE_COUNT_RANGES CoreCounts; ///< Specify up to two core count ranges to match. + PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data. +} CORE_COUNTS_PCI_TYPE_ENTRY_DATA; + +/** + * Processor Count dependent PCI registers. + * + */ +typedef struct { + PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features. + PROCESSOR_COUNTS ProcessorCounts; ///< Specify a processor count range. + PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data. +} PROCESSOR_COUNTS_PCI_TYPE_ENTRY_DATA; + +/** + * Compute Unit Count dependent PCI registers. + * + */ +typedef struct { + PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features. + COMPUTE_UNIT_COUNTS ComputeUnitCounts; ///< Specify a compute unit count range. + PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data. +} COMPUTE_UNIT_COUNTS_PCI_TYPE_ENTRY_DATA; + +/** + * Compute Unit Count dependent MSR registers. + * + */ +typedef struct { + COMPUTE_UNIT_COUNTS ComputeUnitCounts; ///< Specify a compute unit count range. + MSR_TYPE_ENTRY_DATA MsrEntry; ///< The MSR Register entry data. +} COMPUTE_UNIT_COUNTS_MSR_TYPE_ENTRY_DATA; + +/** + * System connectivity dependent PCI registers. + * + * The topology specific recommended settings are based on the different connectivity of nodes + * in each configuration: the more connections, the fewer resources each connection gets. + * The connectivity criteria translate as: + * - 2 Socket, half populated == Degree 1 + * - 4 Socket, half populated == Degree 2 + * - 2 Socket, fully populated == Degree 3 + * - 4 Socket, fully populated == Degree > 3. (4 or 5 if 3P, 6 if 4P) + * + */ +typedef struct { + PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features. + CONNECTIVITY_COUNT ConnectivityCount; ///< Specify a system degree range. + PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data. +} CONNECTIVITY_COUNTS_PCI_TYPE_ENTRY_DATA; + +/** + * A Family Specific Workaround method. + * + * @TableTypeFamSpecificInstances. + * + * When called, the entry's CPU Logical ID and Platform Features matched the current config. + * The method must implement any specific criteria checking for the workaround. + * + * See if you can use the other entries or make an entry specifically for the fix. + * After all, the purpose of having a table entry is to @b NOT have code which + * isn't generic feature code, but is family/model specific. + * + * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. + * @param[in] StdHeader Config params for library, services. + */ +typedef VOID F_FAM_SPECIFIC_WORKAROUND ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ); +/// Reference to a method. +typedef F_FAM_SPECIFIC_WORKAROUND *PF_FAM_SPECIFIC_WORKAROUND; + +/** + * Table Entry Data for Family Specific Workarounds. + * + * See if you can use the other entries or make an entry specifically for the fix. + * After all, the purpose of having a table entry is to @b NOT have code which + * isn't generic feature code, but is family/model specific. + * + * Call DoAction passing Data. + */ +typedef struct { + PF_FAM_SPECIFIC_WORKAROUND DoAction; ///< A function implementing the workaround. + UINT32 Data; ///< This data is passed to DoAction(). +} FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_DATA; + +/** + * Package Type Features + * + * FamilyPackageType are various among CPU families. + * + */ +typedef union { + UINT32 PackageTypeValue; ///< Package Type + PACKAGE_TYPE_FEATURES FamilyPackageType; ///< Package Type of CPU family +} PACKAGE_TYPE_FEATS; + +/** + * HT Features dependent Global PCI registers. + * + */ +typedef struct { + HT_HOST_FEATS LinkFeats; ///< Link Features. + PACKAGE_TYPE_FEATS PackageType; ///< Package Type + PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data. +} HT_FEATURES_PCI_TYPE_ENTRY_DATA; + +/** + * Table Entry Data for HT Phy Registers which depend on performance profile features. + * + * Match performance profile features and link features. + * Apply data to register after mask, for HT Phy registers, repeated for all active links. + */ +typedef struct { + PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features. + HT_PHY_TYPE_ENTRY_DATA HtPhyEntry; ///< The HT Phy Entry to set the deemphasis values +} PROFILE_HT_PHY_TYPE_ENTRY_DATA; + +/** + * HT Link PCI registers that are not in the HT Host capability. + * + * Some HT Link registers have an instance per link, but are just sequential. Specify the base register + * in the table register address (link 0 sublink 0). + */ +typedef struct { + HT_HOST_FEATS LinkFeats; ///< Link Features. + PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data. +} HT_LINK_PCI_TYPE_ENTRY_DATA; + +/*------------------------------------------------------------------------------------------*/ +/* + * A complete register table and table entries. + */ +/*------------------------------------------------------------------------------------------*/ + +/** + * All the available entry data types. + */ +typedef union { + GENERIC_TYPE_ENTRY_INITIALIZER InitialValues; ///< Not a valid entry type; as the first union item, + ///< it can be used with initializers. + MSR_TYPE_ENTRY_DATA MsrEntry; ///< Msr entry. + PCI_TYPE_ENTRY_DATA PciEntry; ///< PCI entry. + FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_DATA FamSpecificEntry; ///< Family Specific Workaround entry. + HT_PHY_TYPE_ENTRY_DATA HtPhyEntry; ///< HT Phy entry. + HT_PHY_RANGE_TYPE_ENTRY_DATA HtPhyRangeEntry; ///< A range of Ht Phy Registers + DEEMPHASIS_HT_PHY_TYPE_ENTRY_DATA DeemphasisEntry; ///< A HT Deemphasis level's settings. + HT_PHY_FREQ_TYPE_ENTRY_DATA HtPhyFreqEntry; ///< A frequency dependent Ht Phy Register setting. + PROFILE_FIXUP_TYPE_ENTRY_DATA FixupEntry; ///< Profile Fixup entry. + HT_HOST_PCI_TYPE_ENTRY_DATA HtHostEntry; ///< HT Host PCI entry. + HT_HOST_PERFORMANCE_PCI_TYPE_ENTRY_DATA HtHostPerfEntry; ///< HT Host Performance PCI entry + HT_TOKEN_PCI_REGISTER HtTokenEntry; ///< HT Link Token Count entry. + CORE_COUNTS_PCI_TYPE_ENTRY_DATA CoreCountEntry; ///< Core count dependent settings. + PROCESSOR_COUNTS_PCI_TYPE_ENTRY_DATA ProcCountEntry; ///< Processor count entry. + COMPUTE_UNIT_COUNTS_PCI_TYPE_ENTRY_DATA CompUnitCountEntry; ///< Compute unit count dependent entry. + CONNECTIVITY_COUNTS_PCI_TYPE_ENTRY_DATA TokenPciEntry; ///< System connectivity dependent Token register. + HT_FEATURES_PCI_TYPE_ENTRY_DATA HtFeatPciEntry; ///< HT Features PCI entry. + PROFILE_HT_PHY_TYPE_ENTRY_DATA HtPhyProfileEntry; ///< Performance dependent HT Phy register. + HT_LINK_PCI_TYPE_ENTRY_DATA HtLinkPciEntry; ///< Per Link, non HT Host, PCI registers. + COMPUTE_UNIT_COUNTS_MSR_TYPE_ENTRY_DATA CompUnitCountMsrEntry; ///< Compute unit count dependent MSR entry. +} TABLE_ENTRY_DATA; + +/** + * Register Table Entry common fields. + * + * All the various types of register table entries are subclasses of this object. + */ +typedef struct { + TABLE_ENTRY_TYPE EntryType; ///< The type of table entry this is. + CPU_LOGICAL_ID CpuRevision; ///< Common CPU Logical ID match criteria. + PLATFORM_FEATS Features; ///< Common Platform Features match criteria. + TABLE_ENTRY_DATA Entry; ///< The type dependent entry data (ex. register, data, mask). +} TABLE_ENTRY_FIELDS; + +/** + * An entire register table. + */ +typedef struct { + TABLE_CORE_SELECTOR Selector; ///< For efficiency, these cores should process this table + UINTN NumberOfEntries; ///< The number of entries in the table. + CONST TABLE_ENTRY_FIELDS *Table; ///< The table entries. +} REGISTER_TABLE; + +/*------------------------------------------------------------------------------------------*/ +/* + * Describe implementers for table entries. + */ +/*------------------------------------------------------------------------------------------*/ + +/** + * Implement the semantics of a Table Entry Type. + * + * @TableEntryTypeInstances. + * + * @param[in] CurrentEntry The type specific entry data to be implemented (that is written). + * @param[in] PlatformConfig Config handle for platform specific information + * @param[in] StdHeader Config params for library, services. + */ +typedef VOID F_DO_TABLE_ENTRY ( + IN TABLE_ENTRY_DATA *CurrentEntry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); +/// Reference to a method +typedef F_DO_TABLE_ENTRY *PF_DO_TABLE_ENTRY; + +/** + * Describe the attributes of a Table Entry Type. + */ +typedef struct { + TABLE_ENTRY_TYPE EntryType; ///< The type of table entry this describes. + PF_DO_TABLE_ENTRY DoTableEntry; ///< Provide all semantics associated with TABLE_ENTRY_DATA +} TABLE_ENTRY_TYPE_DESCRIPTOR; + +/*------------------------------------------------------------------------------------------*/ +/* + * Non-union initializers for entry data which is not just UINT32. + */ +/*------------------------------------------------------------------------------------------*/ + +/** + * A union of data types, that can be initialized with MSR data. + * + * This ensures the entry data is the same size as TABLE_ENTRY_DATA. + */ +typedef union { + MSR_TYPE_ENTRY_DATA MsrInitializer; ///< The data in the table initializer is assigned to this member. + TABLE_ENTRY_DATA Reserved; ///< Make sure the size is the same as the real union. +} MSR_DATA_INITIALIZER; + +/** + * A type suitable for an initializer for MSR Table entries. + */ +typedef struct { + TABLE_ENTRY_TYPE Type; ///< The type of table entry this is. + CPU_LOGICAL_ID CpuRevision; ///< Common CPU Logical ID match criteria. + PLATFORM_FEATS Features; ///< Common Platform Features match criteria. + MSR_DATA_INITIALIZER EntryData; ///< The special union which accepts msr data initializer. +} MSR_TYPE_ENTRY_INITIALIZER; + +/** + * A union of data types, that can be initialized with MSR CU data. + * + * This ensures the entry data is the same size as TABLE_ENTRY_DATA. + */ +typedef union { + COMPUTE_UNIT_COUNTS_MSR_TYPE_ENTRY_DATA MsrInitializer; ///< The data in the table initializer is assigned to this member. + TABLE_ENTRY_DATA Reserved; ///< Make sure the size is the same as the real union. +} MSR_CU_DATA_INITIALIZER; + +/** + * A type suitable for an initializer for MSR CU count Table entries. + */ +typedef struct { + TABLE_ENTRY_TYPE Type; ///< The type of table entry this is. + CPU_LOGICAL_ID CpuRevision; ///< Common CPU Logical ID match criteria. + PLATFORM_FEATS Features; ///< Common Platform Features match criteria. + MSR_CU_DATA_INITIALIZER EntryData; ///< The special union which accepts msr data initializer. +} MSR_CU_TYPE_ENTRY_INITIALIZER; + +/** + * A union of data types, that can be initialized with Family Specific Workaround data. + * + * This ensures the entry data is the same size as TABLE_ENTRY_DATA. + */ +typedef union { + FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_DATA FamSpecificInitializer; ///< The data in the table initializer is assigned to this member. + TABLE_ENTRY_DATA Reserved; ///< Make sure the size is the same as the real union. +} FAM_SPECIFIC_WORKAROUND_DATA_INITIALIZER; + +/** + * A type suitable for an initializer for Family Specific Workaround Table entries. + */ +typedef struct { + TABLE_ENTRY_TYPE Type; ///< The type of table entry this is. + CPU_LOGICAL_ID CpuRevision; ///< Common CPU Logical ID match criteria. + PLATFORM_FEATS Features; ///< Common Platform Features match criteria. + FAM_SPECIFIC_WORKAROUND_DATA_INITIALIZER EntryData; ///< Special union accepts family specific workaround data initializer. +} FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER; + +/*------------------------------------------------------------------------------------------*/ +/* + * Table related function prototypes (many are instance of F_DO_TABLE_ENTRY method). + */ +/*------------------------------------------------------------------------------------------*/ + +/** + * Set the registers for this core based on entries in a list of Register Tables. + */ +VOID SetRegistersFromTables ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Find the features of the running platform. + */ +VOID +GetPlatformFeatures ( + OUT PLATFORM_FEATS *Features, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Checks register table entry type specific criteria to the platform. + */ +BOOLEAN +DoesEntryTypeSpecificInfoMatch ( + IN UINT32 PlatformTypeSpecificFeatures, + IN UINT32 EntryTypeFeatures + ); + +/** + * Perform the MSR Register Entry. + */ +VOID +SetRegisterForMsrEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Perform the PCI Register Entry. + */ +VOID +SetRegisterForPciEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Perform the Performance Profile PCI Register Entry. + */ +VOID +SetRegisterForPerformanceProfileEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Perform the HT Host PCI Register Entry. + */ +VOID +SetRegisterForHtHostEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Perform the HT Host Performance PCI Register Entry. + */ +VOID +SetRegisterForHtHostPerfEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Set the HT Link Token Count registers. + */ +VOID +SetRegisterForHtLinkTokenEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Perform the Core Counts Performance PCI Register Entry. + */ +VOID +SetRegisterForCoreCountsPerformanceEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Perform the Processor Counts PCI Register Entry. + */ +VOID +SetRegisterForProcessorCountsEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Perform the Compute Unit Counts PCI Register Entry. + */ +VOID +SetRegisterForComputeUnitCountsEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Perform the Compute Unit Counts MSR Register Entry. + */ +VOID +SetMsrForComputeUnitCountsEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Perform the Family Specific Workaround Register Entry. + */ +VOID +SetRegisterForFamSpecificWorkaroundEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Program HT Phy PCI registers. + */ +VOID +SetRegisterForHtPhyEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Program a range of HT Phy PCI registers. + */ +VOID +SetRegisterForHtPhyRangeEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Program Deemphasis registers, for the platform specified levels. + */ +VOID +SetRegisterForDeemphasisEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Program HT Phy PCI registers which have complex frequency dependencies. + */ +VOID +SetRegisterForHtPhyFreqEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Perform the Processor Token Counts PCI Register Entry. + */ +VOID +SetRegisterForTokenPciEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Perform the HT Link Feature PCI Register Entry. + */ +VOID +SetRegisterForHtFeaturePciEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Perform the HT Phy Performance Profile Register Entry. + */ +VOID +SetRegisterForHtPhyProfileEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Perform the HT Link PCI Register Entry. + */ +VOID +SetRegisterForHtLinkPciEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Compare counts to a pair of ranges. + */ +BOOLEAN +IsEitherCountInRange ( + IN UINTN FirstCount, + IN UINTN SecondCount, + IN COUNT_RANGE_FEATURE Ranges + ); + +/** + * Returns the performance profile features list of the currently running processor core. + */ +VOID +GetPerformanceFeatures ( + OUT PERFORMANCE_PROFILE_FEATS *Features, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif // _CPU_TABLE_H_ + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/TableHt.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/TableHt.c new file mode 100644 index 0000000..f2dc00b --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/TableHt.c @@ -0,0 +1,954 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Register Table Related Functions + * + * Set registers according to a set of register tables + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Topology.h" +#include "OptionMultiSocket.h" +#include "cpuRegisters.h" +#include "cpuFamilyTranslation.h" +#include "Table.h" +#include "GeneralServices.h" +#include "cpuServices.h" +#include "cpuFeatures.h" +#include "CommonReturns.h" +#include "cpuL3Features.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_TABLEHT_FILECODE + +extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern BUILD_OPT_CFG UserOptions; + + +/*---------------------------------------------------------------------------------------*/ +/** + * Program HT Phy PCI registers using BKDG values. + * + * @TableEntryTypeMethod{::HtPhyRegister}. + * + * + * @param[in] Entry The type specific entry data to be implemented (that is written). + * @param[in] PlatformConfig Config handle for platform specific information + * @param[in] StdHeader Config params for library, services. + * + */ +VOID +SetRegisterForHtPhyEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Link; + UINT32 MySocket; + UINT32 MyModule; + AGESA_STATUS IgnoredStatus; + UINT32 Ignored; + CPU_LOGICAL_ID CpuFamilyRevision; + PCI_ADDR CapabilitySet; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + BOOLEAN MatchedSublink1; + HT_FREQUENCIES Freq0; + HT_FREQUENCIES Freq1; + + // Errors: Possible values in unused entry space, extra type features, value range checks. + // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. + ASSERT ((Entry->InitialValues[4] == 0) && + ((Entry->HtPhyEntry.TypeFeats.HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL | HTPHY_LINKTYPE_SL0_AND | HTPHY_LINKTYPE_SL1_AND)) == 0) && + (Entry->HtPhyEntry.Address < HTPHY_REGISTER_MAX)); + + IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); + GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); + GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); + GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader); + Link = 0; + while (FamilySpecificServices->NextLinkHasHtPhyFeats ( + FamilySpecificServices, + &CapabilitySet, + &Link, + &Entry->HtPhyEntry.TypeFeats, + &MatchedSublink1, + &Freq0, + &Freq1, + StdHeader)) { + FamilySpecificServices->SetHtPhyRegister (FamilySpecificServices, &Entry->HtPhyEntry, CapabilitySet, Link, StdHeader); + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Program a range of HT Phy PCI registers using BKDG values. + * + * @TableEntryTypeMethod{::HtPhyRangeRegister}. + * + * + * @param[in] Entry The type specific entry data to be implemented (that is written). + * @param[in] PlatformConfig Config handle for platform specific information + * @param[in] StdHeader Config params for library, services. + * + */ +VOID +SetRegisterForHtPhyRangeEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Link; + UINT32 MySocket; + UINT32 MyModule; + AGESA_STATUS IgnoredStatus; + UINT32 Ignored; + CPU_LOGICAL_ID CpuFamilyRevision; + PCI_ADDR CapabilitySet; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + HT_PHY_TYPE_ENTRY_DATA CurrentHtPhyRegister; + BOOLEAN MatchedSublink1; + HT_FREQUENCIES Freq0; + HT_FREQUENCIES Freq1; + + // Errors: Possible values in unused entry space, extra type features, value range checks. + // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. + ASSERT (((Entry->HtPhyRangeEntry.TypeFeats.HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL)) == 0) && + (Entry->HtPhyRangeEntry.LowAddress <= Entry->HtPhyRangeEntry.HighAddress) && + (Entry->HtPhyRangeEntry.HighAddress < HTPHY_REGISTER_MAX) && + (Entry->HtPhyRangeEntry.HighAddress != 0)); + + CurrentHtPhyRegister.Mask = Entry->HtPhyRangeEntry.Mask; + CurrentHtPhyRegister.Data = Entry->HtPhyRangeEntry.Data; + CurrentHtPhyRegister.TypeFeats = Entry->HtPhyRangeEntry.TypeFeats; + + IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); + GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); + GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); + GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader); + Link = 0; + while (FamilySpecificServices->NextLinkHasHtPhyFeats ( + FamilySpecificServices, + &CapabilitySet, + &Link, + &Entry->HtPhyRangeEntry.TypeFeats, + &MatchedSublink1, + &Freq0, + &Freq1, + StdHeader)) { + for (CurrentHtPhyRegister.Address = Entry->HtPhyRangeEntry.LowAddress; + CurrentHtPhyRegister.Address <= Entry->HtPhyRangeEntry.HighAddress; + CurrentHtPhyRegister.Address++) { + FamilySpecificServices->SetHtPhyRegister (FamilySpecificServices, &CurrentHtPhyRegister, CapabilitySet, Link, StdHeader); + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Is PackageLink an Internal Link? + * + * This is a test for the logical link match codes in the user interface, not a test for + * the actual northbridge links. + * + * @param[in] PackageLink The link + * + * @retval TRUE This is an internal link + * @retval FALSE This is not an internal link + */ +BOOLEAN +STATIC +IsDeemphasisLinkInternal ( + IN UINT32 PackageLink + ) +{ + return (BOOLEAN) ((PackageLink <= HT_LIST_MATCH_INTERNAL_LINK_2) && (PackageLink >= HT_LIST_MATCH_INTERNAL_LINK_0)); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get the Package Link number, for the current node and real link number. + * + * Based on the link to package link mapping from BKDG, look up package link for + * the input link on the internal node number corresponding to the current core's node. + * For single module processors, the northbridge link and package link are the same. + * + * @param[in] Link the link on the current node. + * @param[in] FamilySpecificServices CPU specific support interface. + * @param[in] StdHeader Config params for library, services. + * + * @return the Package Link, HT_LIST_TERMINAL Not connected in package, HT_LIST_MATCH_INTERNAL_LINK package internal link. + * + */ +UINT32 +STATIC +LookupPackageLink ( + IN UINT32 Link, + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 PackageLinkMapItem; + UINT32 PackageLink; + AP_MAIL_INFO ApMailbox; + + PackageLink = HT_LIST_TERMINAL; + + GetApMailbox (&ApMailbox.Info, StdHeader); + + if (ApMailbox.Fields.ModuleType != 0) { + ASSERT (FamilySpecificServices->PackageLinkMap != NULL); + // Use table to find this module's package link + PackageLinkMapItem = 0; + while ((*FamilySpecificServices->PackageLinkMap)[PackageLinkMapItem].Link != HT_LIST_TERMINAL) { + if (((*FamilySpecificServices->PackageLinkMap)[PackageLinkMapItem].Module == ApMailbox.Fields.Module) && + ((*FamilySpecificServices->PackageLinkMap)[PackageLinkMapItem].Link == Link)) { + PackageLink = (*FamilySpecificServices->PackageLinkMap)[PackageLinkMapItem].PackageLink; + break; + } + PackageLinkMapItem++; + } + } else { + PackageLink = Link; + } + return PackageLink; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Get the platform's specified deemphasis levels for the current link. + * + * Search the platform's list for a match to the current link and also matching frequency. + * If a match is found, use the specified deemphasis levels. + * + * @param[in] Socket The current Socket. + * @param[in] Link The link on that socket. + * @param[in] Frequency The frequency the link is set to. + * @param[in] PlatformConfig Config handle for platform specific information + * @param[in] FamilySpecificServices CPU specific support interface. + * @param[in] StdHeader Config params for library, services. + * + * @return The Deemphasis values for the link. + */ +UINT32 +STATIC +GetLinkDeemphasis ( + IN UINT32 Socket, + IN UINT32 Link, + IN HT_FREQUENCIES Frequency, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Result; + CPU_HT_DEEMPHASIS_LEVEL *Match; + UINT32 PackageLink; + + PackageLink = LookupPackageLink (Link, FamilySpecificServices, StdHeader); + // All External and Internal links have deemphasis level none as the default. + // However, it is expected that the platform BIOS will provide deemphasis levels for the external links. + Result = ((DCV_LEVEL_NONE) | (DEEMPHASIS_LEVEL_NONE)); + + if (PlatformConfig->PlatformDeemphasisList != NULL) { + Match = PlatformConfig->PlatformDeemphasisList; + while (Match->Socket != HT_LIST_TERMINAL) { + if (((Match->Socket == Socket) || (Match->Socket == HT_LIST_MATCH_ANY)) && + ((Match->Link == PackageLink) || + ((Match->Link == HT_LIST_MATCH_ANY) && (!IsDeemphasisLinkInternal (PackageLink))) || + ((Match->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsDeemphasisLinkInternal (PackageLink)))) && + ((Match->LoFreq <= Frequency) && (Match->HighFreq >= Frequency))) { + // Found a match, get the deemphasis value. + ASSERT ((MaxPlatformDeemphasisLevel > Match->DcvDeemphasis) | (MaxPlatformDeemphasisLevel > Match->ReceiverDeemphasis)); + Result = ((1 << Match->DcvDeemphasis) | (1 << Match->ReceiverDeemphasis)); + break; + } else { + Match++; + } + } + } + return Result; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Program Deemphasis registers using BKDG values, for the platform specified levels. + * + * @TableEntryTypeMethod{::DeemphasisRegister}. + * + * + * @param[in] Entry The type specific entry data to be implemented (that is written). + * @param[in] PlatformConfig Config handle for platform specific information + * @param[in] StdHeader Config params for library, services. + * + */ +VOID +SetRegisterForDeemphasisEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Link; + UINT32 MySocket; + UINT32 MyModule; + AGESA_STATUS IgnoredStatus; + UINT32 Ignored; + CPU_LOGICAL_ID CpuFamilyRevision; + PCI_ADDR CapabilitySet; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + BOOLEAN MatchedSublink1; + HT_FREQUENCIES Freq0; + HT_FREQUENCIES Freq1; + + // Errors: Possible values in unused entry space, extra type features, value range checks. + // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. + ASSERT (((Entry->DeemphasisEntry.Levels.DeemphasisValues & ~(VALID_DEEMPHASIS_LEVELS)) == 0) && + ((Entry->DeemphasisEntry.HtPhyEntry.TypeFeats.HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL)) == 0) && + (Entry->DeemphasisEntry.HtPhyEntry.Address < HTPHY_REGISTER_MAX)); + + IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); + GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); + GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); + GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader); + Link = 0; + while (FamilySpecificServices->NextLinkHasHtPhyFeats ( + FamilySpecificServices, + &CapabilitySet, + &Link, + &Entry->DeemphasisEntry.HtPhyEntry.TypeFeats, + &MatchedSublink1, + &Freq0, + &Freq1, + StdHeader)) { + if (DoesEntryTypeSpecificInfoMatch ( + GetLinkDeemphasis ( + MySocket, + (MatchedSublink1 ? (Link + 4) : Link), + (MatchedSublink1 ? Freq1 : Freq0), + PlatformConfig, + FamilySpecificServices, + StdHeader), + Entry->DeemphasisEntry.Levels.DeemphasisValues)) { + FamilySpecificServices->SetHtPhyRegister ( + FamilySpecificServices, + &Entry->DeemphasisEntry.HtPhyEntry, + CapabilitySet, + Link, + StdHeader + ); + IDS_HDT_CONSOLE (HT_TRACE, "Socket %d Module %d Sub-link %1d :\n ----> running on HT3, %s Level is %s\n", + MySocket, MyModule, + ((Entry->DeemphasisEntry.HtPhyEntry.TypeFeats.HtPhyLinkValue & HTPHY_LINKTYPE_SL0_ALL) != 0) ? Link : (Link + 4), + ((Entry->DeemphasisEntry.Levels.DeemphasisValues & DCV_LEVELS_ALL) != 0) ? "DCV" : "Deemphasis", + (Entry->DeemphasisEntry.Levels.DeemphasisValues == DEEMPHASIS_LEVEL_NONE) ? " 0 dB" : + (Entry->DeemphasisEntry.Levels.DeemphasisValues == DEEMPHASIS_LEVEL__3) ? " - 3 dB" : + (Entry->DeemphasisEntry.Levels.DeemphasisValues == DEEMPHASIS_LEVEL__6) ? " - 6 dB" : + (Entry->DeemphasisEntry.Levels.DeemphasisValues == DEEMPHASIS_LEVEL__6) ? " - 6 dB" : + (Entry->DeemphasisEntry.Levels.DeemphasisValues == DEEMPHASIS_LEVEL__8) ? " - 8 dB" : + (Entry->DeemphasisEntry.Levels.DeemphasisValues == DEEMPHASIS_LEVEL__11) ? " - 11 dB" : + (Entry->DeemphasisEntry.Levels.DeemphasisValues == DEEMPHASIS_LEVEL__11_8) ? " - 11 dB postcursor with - 8 dB precursor" : + (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL_NONE) ? " 0 dB" : + (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__2) ? " - 2 dB" : + (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__3) ? " - 3 dB" : + (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__5) ? " - 5 dB" : + (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__6) ? " - 6 dB" : + (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__7) ? " - 7 dB" : + (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__8) ? " - 8 dB" : + (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__9) ? " - 9 dB" : + (Entry->DeemphasisEntry.Levels.DeemphasisValues == DCV_LEVEL__11) ? " - 11 dB" : "Undefined"); + } + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Program HT Phy PCI registers which have complex frequency dependencies. + * + * @TableEntryTypeMethod{::HtPhyFreqRegister}. + * + * After matching a link for HT Features, check if the HT frequency matches the given range. + * If it does, get the northbridge frequency limits for implemented NB P-states and check if + * each matches the given range - range 0 and range 1 for each NB frequency, respectively. + * If all matches, apply the entry. + * + * @param[in] Entry The type specific entry data to be implemented (that is written). + * @param[in] PlatformConfig Config handle for platform specific information + * @param[in] StdHeader Config params for library, services. + * + */ +VOID +SetRegisterForHtPhyFreqEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Link; + UINT32 MySocket; + UINT32 MyModule; + AGESA_STATUS IgnoredStatus; + UINT32 Ignored; + CPU_LOGICAL_ID CpuFamilyRevision; + PCI_ADDR CapabilitySet; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + BOOLEAN MatchedSublink1; + HT_FREQUENCIES Freq0; + HT_FREQUENCIES Freq1; + BOOLEAN Temp1; + BOOLEAN Temp2; + UINT32 NbFreq0; + UINT32 NbFreq1; + UINT32 NbDivisor0; + UINT32 NbDivisor1; + + // Errors: extra type features, value range checks. + // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. + ASSERT (((Entry->HtPhyFreqEntry.HtPhyEntry.TypeFeats.HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL)) == 0) && + (Entry->HtPhyFreqEntry.HtPhyEntry.Address < HTPHY_REGISTER_MAX)); + + IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); + GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); + GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); + GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader); + Link = 0; + while (FamilySpecificServices->NextLinkHasHtPhyFeats ( + FamilySpecificServices, + &CapabilitySet, + &Link, + &Entry->HtPhyFreqEntry.HtPhyEntry.TypeFeats, + &MatchedSublink1, + &Freq0, + &Freq1, + StdHeader)) { + // Check the HT Frequency for match to the range. + if (IsEitherCountInRange ( + (MatchedSublink1 ? Freq1 : Freq0), + (MatchedSublink1 ? Freq1 : Freq0), + Entry->HtPhyFreqEntry.HtFreqCounts.HtFreqCountRanges)) { + // Get the NB Frequency, convert to 100's of MHz, then convert to equivalent HT encoding. This supports + // NB frequencies from 800 MHz to 2600 MHz, which is currently greater than any processor supports. + OptionMultiSocketConfiguration.GetSystemNbPstateSettings ( + (UINT32) 0, + PlatformConfig, + &NbFreq0, + &NbDivisor0, + &Temp1, + &Temp2, + StdHeader); + + if (OptionMultiSocketConfiguration.GetSystemNbPstateSettings ( + (UINT32) 1, + PlatformConfig, + &NbFreq1, + &NbDivisor1, + &Temp1, + &Temp2, + StdHeader)) { + ASSERT (NbDivisor1 != 0); + NbFreq1 = (NbFreq1 / NbDivisor1); + NbFreq1 = (NbFreq1 / 100); + NbFreq1 = (NbFreq1 / 2) + 1; + } else { + NbFreq1 = 0; + } + + ASSERT (NbDivisor0 != 0); + NbFreq0 = (NbFreq0 / NbDivisor0); + NbFreq0 = (NbFreq0 / 100); + NbFreq0 = (NbFreq0 / 2) + 1; + if (IsEitherCountInRange (NbFreq0, NbFreq1, Entry->HtPhyFreqEntry.NbFreqCounts.HtFreqCountRanges)) { + FamilySpecificServices->SetHtPhyRegister ( + FamilySpecificServices, + &Entry->HtPhyFreqEntry.HtPhyEntry, + CapabilitySet, + Link, + StdHeader); + } + } + } +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Perform the HT Phy Performance Profile Register Entry. + * + * @TableEntryTypeMethod{::HtPhyProfileRegister}. + * + * @param[in] Entry The HT Phy register entry to perform + * @param[in] PlatformConfig Config handle for platform specific information + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +SetRegisterForHtPhyProfileEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PERFORMANCE_PROFILE_FEATS PlatformProfile; + TABLE_ENTRY_DATA HtPhyEntry; + + // Errors: Possible values in unused entry space, extra type features, value range checks. + // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. + ASSERT (((Entry->HtPhyProfileEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0) && + (Entry->InitialValues[5] == 0)); + + GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader); + if (DoesEntryTypeSpecificInfoMatch ( + PlatformProfile.PerformanceProfileValue, + Entry->HtPhyProfileEntry.TypeFeats.PerformanceProfileValue)) { + LibAmdMemFill (&HtPhyEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); + HtPhyEntry.HtPhyEntry = Entry->HtPhyProfileEntry.HtPhyEntry; + SetRegisterForHtPhyEntry (&HtPhyEntry, PlatformConfig, StdHeader); + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Perform the HT Host PCI Register Entry. + * + * @TableEntryTypeMethod{::HtHostPciRegister}. + * + * Make the current core's PCI address with the function and register for the entry. + * For all HT links, check the link's feature set for a match to the entry. + * Read - Modify - Write the PCI register, clearing masked bits, and setting the data bits. + * + * @param[in] Entry The PCI register entry to perform + * @param[in] PlatformConfig Config handle for platform specific information + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +SetRegisterForHtHostEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINTN Link; + UINT32 MySocket; + UINT32 MyModule; + AGESA_STATUS IgnoredStatus; + UINT32 Ignored; + CPU_LOGICAL_ID CpuFamilyRevision; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + PCI_ADDR CapabilitySet; + PCI_ADDR PciAddress; + HT_HOST_FEATS HtHostFeats; + UINT32 RegisterData; + + // Errors: Possible values in unused entry space, extra type features, value range checks. + // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. + ASSERT ((Entry->InitialValues[4] == 0) && + ((Entry->HtHostEntry.TypeFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0) && + (Entry->HtHostEntry.Address.Address.Register < HT_LINK_HOST_CAP_MAX)); + + HtHostFeats.HtHostValue = 0; + IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); + GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); + GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); + GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader); + Link = 0; + while (FamilySpecificServices->GetNextHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader)) { + if (DoesEntryTypeSpecificInfoMatch (HtHostFeats.HtHostValue, Entry->HtHostEntry.TypeFeats.HtHostValue)) { + // Do the HT Host PCI register update. + PciAddress = CapabilitySet; + PciAddress.Address.Register += Entry->HtHostEntry.Address.Address.Register; + LibAmdPciRead (AccessWidth32, PciAddress, &RegisterData, StdHeader); + RegisterData = RegisterData & (~(Entry->HtHostEntry.Mask)); + RegisterData = RegisterData | Entry->HtHostEntry.Data; + LibAmdPciWrite (AccessWidth32, PciAddress, &RegisterData, StdHeader); + } + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Perform the HT Host Performance PCI Register Entry. + * + * @TableEntryTypeMethod{::HtHostPerfPciRegister}. + * + * Make the current core's PCI address with the function and register for the entry. + * For all HT links, check the link's feature set for a match to the entry. + * Read - Modify - Write the PCI register, clearing masked bits, and setting the data bits. + * + * @param[in] Entry The PCI register entry to perform + * @param[in] PlatformConfig Config handle for platform specific information + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +SetRegisterForHtHostPerfEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PERFORMANCE_PROFILE_FEATS PlatformProfile; + TABLE_ENTRY_DATA HtHostPciTypeEntryData; + + // Errors: Possible values in unused entry space, extra type features, value range checks. + // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. + ASSERT ((Entry->InitialValues[5] == 0) && + ((Entry->HtHostEntry.TypeFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0) && + (Entry->HtHostEntry.Address.Address.Register < HT_LINK_HOST_CAP_MAX)); + + // Check for any performance profile features. + GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader); + if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, + Entry->HtHostPerfEntry.PerformanceFeats.PerformanceProfileValue)) { + // Perform HT Host entry process. + LibAmdMemFill (&HtHostPciTypeEntryData, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); + HtHostPciTypeEntryData.HtHostEntry = Entry->HtHostPerfEntry.HtHostEntry; + SetRegisterForHtHostEntry (&HtHostPciTypeEntryData, PlatformConfig, StdHeader); + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Set the HT Link Token Count registers. + * + * @TableEntryTypeMethod{::HtTokenPciRegister}. + * + * Make the current core's PCI address with the function and register for the entry. + * Check the performance profile features. + * For all HT links, check the link's feature set for a match to the entry. + * Read - Modify - Write the PCI register, clearing masked bits, and setting the data bits. + * + * @param[in] Entry The Link Token register entry to perform + * @param[in] PlatformConfig Config handle for platform specific information + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +SetRegisterForHtLinkTokenEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINTN Link; + UINT32 MySocket; + UINT32 MyModule; + AGESA_STATUS IgnoredStatus; + UINT32 Ignored; + CPU_LOGICAL_ID CpuFamilyRevision; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + PCI_ADDR CapabilitySet; + HT_HOST_FEATS HtHostFeats; + PERFORMANCE_PROFILE_FEATS PlatformProfile; + UINTN ProcessorCount; + UINTN SystemDegree; + UINT32 RegisterData; + PCI_ADDR PciAddress; + + // Errors: Possible values in unused entry space, extra type features, value range checks. + // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. + ASSERT (((Entry->HtTokenEntry.LinkFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0) && + ((Entry->HtTokenEntry.PerformanceFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0) && + (Entry->HtTokenEntry.Mask != 0)); + + HtHostFeats.HtHostValue = 0; + IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); + GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); + GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); + GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader); + + // Check if the actual processor count and SystemDegree are in either range. + ProcessorCount = GetNumberOfProcessors (StdHeader); + SystemDegree = GetSystemDegree (StdHeader); + if (IsEitherCountInRange (ProcessorCount, SystemDegree, Entry->HtTokenEntry.ConnectivityCount.ConnectivityCountRanges)) { + // Check for any performance profile features. + GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader); + if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, + Entry->HtTokenEntry.PerformanceFeats.PerformanceProfileValue)) { + // Check the link features. + Link = 0; + while (FamilySpecificServices->GetNextHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader)) { + if (DoesEntryTypeSpecificInfoMatch (HtHostFeats.HtHostValue, Entry->HtTokenEntry.LinkFeats.HtHostValue)) { + // Do the HT Host PCI register update. Token register are four registers, sublink 0 and 1 share fields. + // If sublink 0 is unconnected, we should let sublink 1 match. If the links are ganged, of course only sublink 0 matches. + // If the links are unganged and both connected, the BKDG settings are for both coherent. + PciAddress = CapabilitySet; + PciAddress.Address.Register = Entry->HtTokenEntry.Address.Address.Register + + ((Link > 3) ? (((UINT32)Link - 4) * 4) : ((UINT32)Link * 4)); + PciAddress.Address.Function = Entry->HtTokenEntry.Address.Address.Function; + LibAmdPciRead (AccessWidth32, PciAddress, &RegisterData, StdHeader); + RegisterData = RegisterData & (~(Entry->HtTokenEntry.Mask)); + RegisterData = RegisterData | Entry->HtTokenEntry.Data; + LibAmdPciWrite (AccessWidth32, PciAddress, &RegisterData, StdHeader); + } + } + } + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Perform the Processor Token Counts PCI Register Entry. + * + * @TableEntryTypeMethod{::TokenPciRegister}. + * + * The table criteria then translate as: + * - 2 Socket, half populated == Degree 1 + * - 4 Socket, half populated == Degree 2 + * - 2 Socket, fully populated == Degree 3 + * - 4 Socket, fully populated == Degree > 3. (4 or 5 if 3P, 6 if 4P) + * + * @param[in] Entry The PCI register entry to perform + * @param[in] PlatformConfig Config handle for platform specific information + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +SetRegisterForTokenPciEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PERFORMANCE_PROFILE_FEATS PlatformProfile; + UINTN SystemDegree; + TABLE_ENTRY_DATA PciEntry; + + // Errors: Possible values in unused entry space, extra type features, value range checks. + // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. + ASSERT (((Entry->TokenPciEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0)); + + GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader); + if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, Entry->TokenPciEntry.TypeFeats.PerformanceProfileValue)) { + SystemDegree = GetSystemDegree (StdHeader); + // Check if the system degree is in the range. + if (IsEitherCountInRange (SystemDegree, SystemDegree, Entry->TokenPciEntry.ConnectivityCount.ConnectivityCountRanges)) { + LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); + PciEntry.PciEntry = Entry->TokenPciEntry.PciEntry; + SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader); + } + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Perform the HT Link Feature PCI Register Entry. + * + * @TableEntryTypeMethod{::HtFeatPciRegister}. + * + * Set a single field (that is, the register field is not in HT Host capability or a + * set of per link registers) in PCI config, based on HT link features and package type. + * This code is used for two cases: single link processors and multilink processors. + * For single link cases, the link will be tested for a match to the HT Features for the link. + * For multilink processors, the entry will match if @b any link is found which matches. + * For example, a setting can be applied based on coherent HT3 by matching coherent AND HT3. + * + * Make the core's PCI address. Check the package type (currently more important to the single link case), + * and if matching, iterate through all links checking for an HT feature match until found or exhausted. + * If a match was found, pass the PCI entry data to the implementer for writing for the current core. + * + * @param[in] Entry The PCI register entry to perform + * @param[in] PlatformConfig Config handle for platform specific information + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +SetRegisterForHtFeaturePciEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINTN Link; + UINT32 MySocket; + UINT32 MyModule; + AGESA_STATUS IgnoredStatus; + UINT32 Ignored; + CPU_LOGICAL_ID CpuFamilyRevision; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + PCI_ADDR CapabilitySet; + HT_HOST_FEATS HtHostFeats; + UINT32 ProcessorPackageType; + BOOLEAN IsMatch; + TABLE_ENTRY_DATA PciEntry; + + // Errors: Possible values in unused entry space, extra type features, value range checks. + // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. + ASSERT ((Entry->HtFeatPciEntry.PciEntry.Mask != 0) && + ((Entry->HtFeatPciEntry.LinkFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0)); + + HtHostFeats.HtHostValue = 0; + LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); + PciEntry.PciEntry = Entry->HtFeatPciEntry.PciEntry; + IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); + GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); + GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); + GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader); + + ASSERT ((Entry->HtFeatPciEntry.PackageType.PackageTypeValue & ~(PACKAGE_TYPE_ALL)) == 0); + + ProcessorPackageType = LibAmdGetPackageType (StdHeader); + if (DoesEntryTypeSpecificInfoMatch (ProcessorPackageType, Entry->HtFeatPciEntry.PackageType.PackageTypeValue)) { + IsMatch = FALSE; + while (FamilySpecificServices->GetNextHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader)) { + if (DoesEntryTypeSpecificInfoMatch (HtHostFeats.HtHostValue, Entry->HtFeatPciEntry.LinkFeats.HtHostValue)) { + IsMatch = TRUE; + break; + } + } + if (IsMatch) { + // Do the PCI register update. + SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader); + } + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Perform the HT Link PCI Register Entry. + * + * @TableEntryTypeMethod{::HtLinkPciRegister}. + * + * Make the current core's PCI address with the function and register for the entry. + * Registers are processed for match per link, assuming sequential PCI address per link. + * Read - Modify - Write each matching link's PCI register, clearing masked bits, and setting the data bits. + * + * @param[in] Entry The PCI register entry to perform + * @param[in] PlatformConfig Config handle for platform specific information + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +SetRegisterForHtLinkPciEntry ( + IN TABLE_ENTRY_DATA *Entry, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINTN Link; + UINT32 MySocket; + UINT32 MyModule; + AGESA_STATUS IgnoredStatus; + UINT32 Ignored; + CPU_LOGICAL_ID CpuFamilyRevision; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + PCI_ADDR CapabilitySet; + HT_HOST_FEATS HtHostFeats; + TABLE_ENTRY_DATA PciEntry; + + // Errors: Possible values in unused entry space, extra type features, value range checks. + // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry. + ASSERT ((Entry->HtLinkPciEntry.PciEntry.Mask != 0) && + ((Entry->HtLinkPciEntry.LinkFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0)); + + HtHostFeats.HtHostValue = 0; + LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader); + PciEntry.PciEntry = Entry->HtLinkPciEntry.PciEntry; + IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); + GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); + GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); + GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader); + + Link = 0; + while (FamilySpecificServices->GetNextHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader)) { + if (DoesEntryTypeSpecificInfoMatch (HtHostFeats.HtHostValue, Entry->HtLinkPciEntry.LinkFeats.HtHostValue)) { + // Do the update to the link's non-Host PCI register, based on the entry address. + PciEntry.PciEntry.Address = Entry->HtLinkPciEntry.PciEntry.Address; + PciEntry.PciEntry.Address.Address.Register = PciEntry.PciEntry.Address.Address.Register + ((UINT32)Link * 4); + SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader); + } + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahalt.asm b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahalt.asm new file mode 100644 index 0000000..a41683f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahalt.asm @@ -0,0 +1,388 @@ +;/** +; * @file +; * +; * Agesa pre-memory miscellaneous support, including ap halt loop. +; * +; * @xrefitem bom "File Content Label" "Release Content" +; * @e project: AGESA +; * @e sub-project: CPU +; * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ +; */ +;***************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;***************************************************************************** + + .XLIST + INCLUDE agesa.inc + INCLUDE cpcarmac.inc + .LIST + + .586P + +;=============================================== +;=============================================== +;== +;== M E M O R Y A B S E N T S E G M E N T +;== +;=============================================== +;=============================================== + .MODEL flat + .CODE +;====================================================================== +; ExecuteFinalHltInstruction: Disables the stack and performs +; a hlt instruction on an AP. +; +; In: +; None +; +; Out: +; None +; +; Destroyed: +; eax, ebx, ecx, edx, esp +; +;====================================================================== +PUBLIC ExecuteFinalHltInstruction +ExecuteFinalHltInstruction PROC NEAR C USES ESI EDI HaltFlags:DWORD, ApMtrrSettingList:PTR, StandardHeader:PTR + + mov esi, StandardHeader ; The code must reference all parameters to avoid a build warning + mov esi, HaltFlags + mov edi, ApMtrrSettingList + ; Do these special steps in case if the core is part of a compute unit + ; Note: The following bits are family specific flags, that gets set during build time, + ; and indicates things like "family cache control methodology", etc. + ; esi bit0 = 0 -> not a Primary core + ; esi bit0 = 1 -> Primary core + ; esi bit1 = 0 -> Cache disable + ; esi bit1 = 1 -> Cache enable + .if (esi & 2h) + ; Set CombineCr0Cd bit + mov ecx, CU_CFG3 + _RDMSR + bts edx, (COMBINE_CR0_CD - 32) + _WRMSR + ; Clear the CR0.CD bit + mov eax, CR0 ; Make sure cache is enabled for all APs + btr eax, CR0_CD + btr eax, CR0_NW + mov CR0, eax ; Write back to CR0 + .else + mov eax, CR0 ; Make sure cache is disabled for all APs + bts eax, CR0_CD ; Disable cache + bts eax, CR0_NW + mov CR0, eax ; Write back to CR0 + .endif + + .if (esi & 1h) + ; This core is a primary core and needs to do all the MTRRs, including shared MTRRs. + mov esi, edi ; Get ApMtrrSettingList + + ; Configure the MTRRs on the AP so + ; when it runs remote code it will execute + ; out of RAM instead of ROM. + + ; Disable MTRRs and turn on modification enable bit + mov ecx, MTRR_SYS_CFG + _RDMSR + btr eax, MTRR_VAR_DRAM_EN ; Disable + bts eax, MTRR_FIX_DRAM_MOD_EN ; Enable + btr eax, MTRR_FIX_DRAM_EN ; Disable + bts eax, SYS_UC_LOCK_EN + _WRMSR + + ; Setup default values for Fixed-Sized MTRRs + ; Set 7FFFh-00000h as WB + mov ecx, AMD_AP_MTRR_FIX64k_00000 + mov eax, 1E1E1E1Eh + mov edx, eax + _WRMSR + + ; Set 9FFFFh-80000h also as WB + mov ecx, AMD_AP_MTRR_FIX16k_80000 + _WRMSR + + ; Set BFFFFh-A0000h as Uncacheable Memory-mapped IO + mov ecx, AMD_AP_MTRR_FIX16k_A0000 + xor eax, eax + xor edx, edx + _WRMSR + + ; Set DFFFFh-C0000h as Uncacheable Memory-mapped IO + xor eax, eax + xor edx, edx + mov ecx, AMD_AP_MTRR_FIX4k_C0000 + +CDLoop: + _WRMSR + inc ecx + cmp ecx, AMD_AP_MTRR_FIX4k_D8000 + jbe CDLoop + + ; Set FFFFFh-E0000h as Uncacheable Memory + mov eax, 18181818h + mov edx, eax + + mov ecx, AMD_AP_MTRR_FIX4k_E0000 + +EFLoop: + _WRMSR + inc ecx + cmp ecx, AMD_AP_MTRR_FIX4k_F8000 + jbe EFLoop + + ; If IBV provided settings for Fixed-Sized MTRRs, + ; overwrite the default settings. + .if ((esi != 0) && (esi != 0FFFFFFFFh)) + mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr + ; While we are not at the end of the list + .while (ecx != CPU_LIST_TERMINAL) + ; Ensure that the MSR address is valid for Fixed-Sized MTRRs + .if ( ((ecx >= AMD_AP_MTRR_FIX4k_C0000) && (ecx <= AMD_AP_MTRR_FIX4k_F8000)) || \ + (ecx == AMD_AP_MTRR_FIX64k_00000) || (ecx == AMD_AP_MTRR_FIX16k_80000 ) || (ecx == AMD_AP_MTRR_FIX16k_A0000)) + mov eax, dword ptr (AP_MTRR_SETTINGS ptr [esi]).MsrData + mov edx, dword ptr (AP_MTRR_SETTINGS ptr [esi+4]).MsrData + _WRMSR + .endif + add esi, sizeof (AP_MTRR_SETTINGS) + mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr + .endw + .endif + + ; Enable fixed-range and variable-range MTRRs + mov ecx, AMD_MTRR_DEFTYPE + _RDMSR + bts eax, MTRR_DEF_TYPE_EN ; MtrrDefTypeEn + bts eax, MTRR_DEF_TYPE_FIX_EN ; MtrrDefTypeFixEn + _WRMSR + + ; Enable Top-of-Memory setting + ; Enable use of RdMem/WrMem bits attributes + mov ecx, MTRR_SYS_CFG + _RDMSR + bts eax, MTRR_VAR_DRAM_EN ; Enable + btr eax, MTRR_FIX_DRAM_MOD_EN ; Disable + bts eax, MTRR_FIX_DRAM_EN ; Enable + _WRMSR + + mov esi, (1 SHL FLAG_IS_PRIMARY) + .else ; end if primary core + xor esi, esi + .endif + ; Make sure not to touch any Shared MSR from this point on + + AMD_DISABLE_STACK_FAMILY_HOOK + + bt esi, FLAG_IS_PRIMARY + .if (carry?) + ; restore variable MTRR6 and MTRR7 to default states + mov ecx, AMD_MTRR_VARIABLE_MASK7 ; clear MTRRPhysBase6 MTRRPhysMask6 + xor eax, eax ; and MTRRPhysBase7 MTRRPhysMask7 + xor edx, edx + .while (cx >= AMD_MTRR_VARIABLE_BASE6) + _WRMSR + dec cx + .endw + .endif + +@@: + cli + hlt + jmp @B ;ExecuteHltInstruction + ret +ExecuteFinalHltInstruction ENDP + +;====================================================================== +; ExecuteHltInstruction: Performs a hlt instruction. +; +; In: +; None +; +; Out: +; None +; +; Destroyed: +; eax, ebx, ecx, edx, esp +; +;====================================================================== +PUBLIC ExecuteHltInstruction +ExecuteHltInstruction PROC NEAR C + cli + hlt + ret +ExecuteHltInstruction ENDP + +;====================================================================== +; NmiHandler: Simply performs an IRET. +; +; In: +; None +; +; Out: +; None +; +; Destroyed: +; None +; +;====================================================================== +PUBLIC NmiHandler +NmiHandler PROC NEAR C + iretd +NmiHandler ENDP + +;====================================================================== +; GetCsSelector: Returns the current protected mode CS selector. +; +; In: +; None +; +; Out: +; None +; +; Destroyed: +; None +; +;====================================================================== +PUBLIC GetCsSelector +GetCsSelector PROC NEAR C, CsSelector:PTR + push ax + push ebx + + call FarCallGetCs + mov ebx, CsSelector + mov [ebx], ax + pop ebx + pop ax + ret +GetCsSelector ENDP + +;====================================================================== +; FarCallGetCs: +; +; In: +; None +; +; Out: +; None +; +; Destroyed: +; none +; +;====================================================================== +FarCallGetCs PROC FAR PRIVATE + + mov ax, ss:[esp + 4] + retf + +FarCallGetCs ENDP + +;====================================================================== +; SetIdtr: +; +; In: +; @param[in] IdtPtr Points to IDT table +; +; Out: +; None +; +; Destroyed: +; none +; +;====================================================================== +PUBLIC SetIdtr +SetIdtr PROC NEAR C USES EBX, IdtPtr:PTR + mov ebx, IdtPtr + lidt fword ptr ss:[ebx] + ret +SetIdtr ENDP + +;====================================================================== +; GetIdtr: +; +; In: +; @param[in] IdtPtr Points to IDT table +; +; Out: +; None +; +; Destroyed: +; none +; +;====================================================================== +PUBLIC GetIdtr +GetIdtr PROC NEAR C USES EBX, IdtPtr:PTR + mov ebx, IdtPtr + sidt fword ptr ss:[ebx] + ret +GetIdtr ENDP + +;====================================================================== +; ExecuteWbinvdInstruction: Performs a wbinvd instruction. +; +; In: +; None +; +; Out: +; None +; +; Destroyed: +; None +; +;====================================================================== +PUBLIC ExecuteWbinvdInstruction +ExecuteWbinvdInstruction PROC NEAR C + wbinvd ; Write back the cache tag RAMs + ret +ExecuteWbinvdInstruction ENDP + +END diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahalt.c new file mode 100644 index 0000000..bc80453 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahalt.c @@ -0,0 +1,160 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * HyperTransport features and sequence implementation. + * + * Implements the external AmdHtInitialize entry point. + * Contains routines for directing the sequence of available features. + * Mostly, but not exclusively, AGESA_TESTPOINT invocations should be + * contained in this file, and not in the feature code. + * + * From a build option perspective, it may be that a few lines could be removed + * from compilation in this file for certain options. It is considered that + * the code savings from this are too small to be of concern and this file + * should not have any explicit build option implementation. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: HyperTransport + * @e $Revision: 35978 $ @e $Date: 2010-08-07 02:18:50 +0800 (Sat, 07 Aug 2010) $ + * + */ +/* +***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +#include "AGESA.h" +#include "cpuRegisters.h" +#include "cpuApicUtilities.h" +#include "Filecode.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +// typedef unsigned int uintptr_t; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +ExecuteFinalHltInstruction ( + IN UINT32 SharedCore, + IN AP_MTRR_SETTINGS *ApMtrrSettingsList, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +NmiHandler ( + IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr + ); + +VOID +ExecuteHltInstruction ( + IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr + ); + +VOID +ExecuteWbinvdInstruction ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/// Structure needed to load the IDTR using the lidt instruction + +VOID +SetIdtr ( + IN IDT_BASE_LIMIT *IdtInfo, + IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr + ) +{ + __lidt (IdtInfo); +} + +//---------------------------------------------------------------------------- + +VOID +GetCsSelector ( + IN UINT16 *Selector, + IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr + ) +{ + static const UINT8 opcode [] = {0x8C, 0xC8, 0xC3}; // mov eax, cs; ret + *Selector = ((UINT16 (*)(void)) (size_t) opcode) (); +} + +//---------------------------------------------------------------------------- + +VOID +NmiHandler ( + IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr + ) +{ + static const UINT8 opcode [] = {0xCF}; // iret + ((void (*)(void)) (size_t) opcode) (); +} + +//---------------------------------------------------------------------------- + +VOID +ExecuteHltInstruction ( + IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr + ) +{ + _disable (); + __halt (); +} + +//--------------------------------------------------------------------------- + +VOID +ExecuteWbinvdInstruction ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + __wbinvd (); +} + +//---------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahalt64.asm b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahalt64.asm new file mode 100644 index 0000000..7270b8f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahalt64.asm @@ -0,0 +1,200 @@ +;/** +; * @file +; * +; * Agesa pre-memory miscellaneous support, including ap halt loop. +; * +; * @xrefitem bom "File Content Label" "Release Content" +; * @e project: AGESA +; * @e sub-project: CPU +; * @e $Revision: 10071 $ @e $Date: 2008-12-16 18:03:04 -0600 (Tue, 16 Dec 2008) $ +; */ +;***************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;***************************************************************************** + + text SEGMENT + + +;====================================================================== +; ExecuteFinalHltInstruction: Performs a hlt instruction. +; +; In: +; None +; +; Out: +; None +; +; Destroyed: +; eax, ebx, ecx, edx, esp +; +;====================================================================== +ExecuteFinalHltInstruction PROC PUBLIC +@@: + cli + hlt + jmp @B ;ExecuteHltInstruction +ExecuteFinalHltInstruction ENDP + +;====================================================================== +; ExecuteHltInstruction: Performs a hlt instruction. +; +; In: +; None +; +; Out: +; None +; +; Destroyed: +; eax, ebx, ecx, edx, esp +; +;====================================================================== +ExecuteHltInstruction PROC PUBLIC + cli + hlt + ret +ExecuteHltInstruction ENDP + +;====================================================================== +; NmiHandler: Simply performs an IRET. +; +; In: +; None +; +; Out: +; None +; +; Destroyed: +; None +; +;====================================================================== +NmiHandler PROC PUBLIC + iretq +NmiHandler ENDP + +;====================================================================== +; GetCsSelector: Returns the current protected mode CS selector. +; +; In: +; None +; +; Out: +; None +; +; Destroyed: +; None +; +;====================================================================== +GetCsSelector PROC PUBLIC + ; This stub function is here to avoid compilation errors. + ; At this time, there is no need to provide a 64 bit function. + ret +GetCsSelector ENDP + +;====================================================================== +; SetIdtr: +; +; In: +; @param[in] IdtPtr Points to IDT table +; +; Out: +; None +; +; Destroyed: +; none +; +;====================================================================== +SetIdtr PROC PUBLIC + ; This stub function is here to avoid compilation errors. + ; At this time, there is no need to provide a 64 bit function. + ret +SetIdtr ENDP + +;====================================================================== +; GetIdtr: +; +; In: +; @param[in] IdtPtr Points to IDT table +; +; Out: +; None +; +; Destroyed: +; none +; +;====================================================================== +GetIdtr PROC PUBLIC + ; This stub function is here to avoid compilation errors. + ; At this time, there is no need to provide a 64 bit function. + ret +GetIdtr ENDP + +;====================================================================== +; ExecuteWbinvdInstruction: Performs a wbinvd instruction. +; +; In: +; None +; +; Out: +; None +; +; Destroyed: +; None +; +;====================================================================== +ExecuteWbinvdInstruction PROC PUBLIC + wbinvd ; Write back the cache tag RAMs + ret +ExecuteWbinvdInstruction ENDP + +END diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S new file mode 100644 index 0000000..4ab535a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +.include "src/vendorcode/amd/agesa/f15tn/gcccar.inc" + +.code32 +.align 4 +.globl ExecuteFinalHltInstruction + .type ExecuteFinalHltInstruction, @function +/* ExecuteFinalHltInstruction ( + IN UINT32 HaltFlags, + IN AP_MTRR_SETTINGS *ApMtrrSettingsList, + IN AMD_CONFIG_PARAMS *StdHeader + ) +*/ + +/* This function disables CAR. We don't care about the stack on this CPU */ +ExecuteFinalHltInstruction: + movl 4(%esp), %esi /* HaltFlags*/ + movl 8(%esp), %edi /* ApMtrrSettingList */ +//1: jmp 1b //good +/* Do these special steps in case if the core is part of a compute unit + * Note: The following bits are family specific flags, that gets set during build time, + * and indicates things like "family cache control methodology", etc. + * esi bit0 = 0 -> not a Primary core + * esi bit0 = 1 -> Primary core + * esi bit1 = 0 -> Cache disable + * esi bit1 = 1 -> Cache enable + */ + + bt $1, %esi /* .if (esi & 2h) */ + jz 0f + /* Set CombineCr0Cd bit */ + movl $CU_CFG3, %ecx + rdmsr + bts $(COMBINE_CR0_CD - 32), %edx + wrmsr + /* Clear the CR0.CD bit */ + movl %cr0, %eax /* Make sure cache is enabled for all APs */ + btr $CR0_CD, %eax + btr $CR0_NW, %eax + mov %eax, %cr0 /* Write back to CR0 */ + jmp 1f /* .else */ +0: + movl %cr0, %eax /* Make sure cache is disabled for all APs */ + bts $CR0_CD, %eax /* Disable cache */ + bts $CR0_NW, %eax + movl %eax, %cr0 /* Write back to CR0 */ +1: /* .endif */ + +// jmp 1b + bt $0, %esi /* .if (esi & 1h) */ + jz 2f + /* This core is a primary core and needs to do all the MTRRs, including shared MTRRs. */ + movl %edi, %esi /* Get ApMtrrSettingList */ + + /* Configure the MTRRs on the AP so + * when it runs remote code it will execute + * out of RAM instead of ROM. + */ + + /* Disable MTRRs and turn on modification enable bit */ + movl $MTRR_SYS_CFG, %ecx + rdmsr + /* TODO: why comment this? */ + //btr $MTRR_VAR_DRAM_EN, %eax /* Disable */ + bts $MTRR_FIX_DRAM_MOD_EN, %eax /* Enable */ + btr $MTRR_FIX_DRAM_EN, %eax /* Disable */ + //bts $SYS_UC_LOCK_EN, %eax + wrmsr + + /* Setup default values for Fixed-Sized MTRRs */ + /* Set 7FFFh-00000h as WB */ + movl $AMD_AP_MTRR_FIX64k_00000, %ecx + movl $0x1E1E1E1E, %eax + movl %eax, %edx + wrmsr + + /* Set 9FFFFh-80000h also as WB */ + movl $AMD_AP_MTRR_FIX16k_80000, %ecx + wrmsr + + /* Set BFFFFh-A0000h as Uncacheable Memory-mapped IO */ + movl $AMD_AP_MTRR_FIX16k_A0000, %ecx + xorl %eax, %eax + xorl %edx, %edx + wrmsr + + /* Set DFFFFh-C0000h as Uncacheable Memory-mapped IO */ + xorl %eax, %eax + xorl %edx, %edx + movl $AMD_AP_MTRR_FIX4k_C0000, %ecx + +CDLoop: + wrmsr + inc %ecx + cmp $AMD_AP_MTRR_FIX4k_D8000, %ecx + jbe CDLoop + + /* Set FFFFFh-E0000h as Uncacheable Memory */ + movl $0x18181818, %eax + movl %eax, %edx + + mov $AMD_AP_MTRR_FIX4k_E0000, %ecx + +EFLoop: + wrmsr + inc %ecx + cmp $AMD_AP_MTRR_FIX4k_F8000, %ecx + jbe EFLoop + + /* If IBV provided settings for Fixed-Sized MTRRs, + * overwrite the default settings. */ + cmp $0, %esi /*.if ((esi != 0) && (esi != 0FFFFFFFFh)) */ + jz 4f + cmp $0xFFFFFFFF, %esi + jz 4f + 5: + mov (%esi), %ecx /* (AP_MTRR_SETTINGS ptr [esi]).MsrAddr */ + /* While we are not at the end of the list */ + cmp $CPU_LIST_TERMINAL, %ecx /* .while (ecx != CPU_LIST_TERMINAL)*/ + je 4f + /* TODO - coreboot isn't checking for valid data. + * Ensure that the MSR address is valid for Fixed-Sized MTRRs */ + /*.if ( ((ecx >= AMD_AP_MTRR_FIX4k_C0000) && (ecx <= AMD_AP_MTRR_FIX4k_F8000)) || \ + (ecx == AMD_AP_MTRR_FIX64k_00000) || (ecx == AMD_AP_MTRR_FIX16k_80000 ) || \ + (ecx == AMD_AP_MTRR_FIX16k_A0000)) + */ + mov 4(%esi), %eax /* MsrData */ + mov 8(%esi), %edx /* MsrData */ + wrmsr + /* .endif */ + add $12, %esi /* sizeof (AP_MTRR_SETTINGS) */ + jmp 5b /* .endw */ + 4: /* .endif */ + + /* Enable fixed-range and variable-range MTRRs */ + mov $AMD_MTRR_DEFTYPE, %ecx + rdmsr + bts $MTRR_DEF_TYPE_EN, %eax /* MtrrDefTypeEn */ + bts $MTRR_DEF_TYPE_FIX_EN, %eax /* MtrrDefTypeFixEn */ + wrmsr + + /* Enable Top-of-Memory setting */ + /* Enable use of RdMem/WrMem bits attributes */ + mov $MTRR_SYS_CFG, %ecx + rdmsr + /* TODO: */ + //bts $MTRR_VAR_DRAM_EN, %eax /* Enable */ + btr $MTRR_FIX_DRAM_MOD_EN, %eax /* Disable */ + bts $MTRR_FIX_DRAM_EN, %eax /* Enable */ + wrmsr + + bts $FLAG_IS_PRIMARY, %esi + jmp 3f /* .else ; end if primary core */ + 2: + xor %esi, %esi + 3: /* .endif*/ + +//8: jmp 8b //bad + /* Make sure not to touch any Shared MSR from this point on */ + + AMD_DISABLE_STACK_FAMILY_HOOK + + /* restore variable MTTR6 and MTTR7 to default states */ + bt $FLAG_IS_PRIMARY, %esi /* .if (esi & 1h) */ + jz 6f + movl $AMD_MTRR_VARIABLE_MASK7, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */ + xor %eax, %eax /* and MTRRPhysBase7 MTRRPhysMask7 */ + xor %edx, %edx + cmp $AMD_MTRR_VARIABLE_BASE6, %ecx /* .while (cl < 010h) */ + jl 6f + wrmsr + dec %ecx + 6: /* .endw */ + + xor %eax, %eax + +7: + cli + hlt + jmp 7b /* ExecuteHltInstruction */ + + .size ExecuteFinalHltInstruction, .-ExecuteFinalHltInstruction diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuApicUtilities.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuApicUtilities.c new file mode 100644 index 0000000..a24dd11 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuApicUtilities.c @@ -0,0 +1,1469 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU APIC related utility functions. + * + * Contains code that provides mechanism to invoke and control APIC communication. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuCacheInit.h" +#include "cpuRegisters.h" +#include "cpuApicUtilities.h" +#include "cpuFamilyTranslation.h" +#include "GeneralServices.h" +#include "cpuServices.h" +#include "heapManager.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_CPUAPICUTILITIES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +/* ApFlags bits */ +#define AP_TASK_HAS_INPUT 0x00000001ul +#define AP_TASK_HAS_OUTPUT 0x00000002ul +#define AP_RETURN_PARAMS 0x00000004ul +#define AP_END_AT_HLT 0x00000008ul +#define AP_PASS_EARLY_PARAMS 0x00000010ul + +#define XFER_ELEMENT_SIZE sizeof (UINT32) + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +typedef VOID F_CPU_AMD_NMI_HANDLER ( + IN AMD_CONFIG_PARAMS *StdHeader + ); +typedef F_CPU_AMD_NMI_HANDLER *PF_CPU_AMD_NMI_HANDLER; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +ApUtilSetupIdtForHlt ( + IN IDT_DESCRIPTOR *NmiIdtDescPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +STATIC +ApUtilRemoteRead ( + IN UINT32 TargetApicId, + IN UINT8 RegAddr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +ApUtilLocalWrite ( + IN UINT32 RegAddr, + IN UINT32 Value, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +STATIC +ApUtilLocalRead ( + IN UINT32 RegAddr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +ApUtilGetLocalApicBase ( + OUT UINT64 *ApicBase, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +STATIC +ApUtilCalculateUniqueId ( + IN UINT8 Socket, + IN UINT8 Core, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +ApUtilFireDirectedNmi ( + IN UINT32 TargetApicId, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +ApUtilReceivePointer ( + IN UINT32 TargetApicId, + OUT VOID **ReturnPointer, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +ApUtilTransmitPointer ( + IN UINT32 TargetApicId, + IN VOID **Pointer, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +PerformFinalHalt ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LocalApicInitialization ( + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LocalApicInitializationAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern +VOID +ExecuteHltInstruction ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +extern +VOID +NmiHandler ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +extern +VOID +ExecuteFinalHltInstruction ( + IN UINT32 SharedCore, + IN AP_MTRR_SETTINGS *ApMtrrSettingsList, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +extern BUILD_OPT_CFG UserOptions; + +/*---------------------------------------------------------------------------------------*/ +/** + * Initialize the Local APIC. + * + * This function determines and programs the appropriate APIC ID value + * for the executing core. This code must be run after HT initialization + * is complete. + * + * @param[in] CpuEarlyParamsPtr Service parameters. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +LocalApicInitialization ( + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 CurrentCore; + UINT32 CurrentNodeNum; + UINT32 CoreIdBits; + UINT32 Mnc; + UINT32 ProcessorCount; + UINT32 ProcessorApicIndex; + UINT32 IoApicNum; + UINT32 StartLocalApicId; + UINT64 LocalApicBase; + UINT32 TempVar_a; + UINT64 MsrData; + UINT64 Address; + CPUID_DATA CpuidData; + + // Local variables default values + IoApicNum = CpuEarlyParamsPtr->PlatformConfig.NumberOfIoApics; + + GetCurrentCore (&CurrentCore, StdHeader); + GetCurrentNodeNum (&CurrentNodeNum, StdHeader); + + // Get Mnc + LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuidData, StdHeader); + CoreIdBits = (CpuidData.ECX_Reg & 0x0000F000) >> 12; + Mnc = 1 << (CoreIdBits & 0x000F); + + // Get ProcessorCount in the system + ProcessorCount = GetNumberOfProcessors (StdHeader); + + // Get the APIC Index of this processor. + ProcessorApicIndex = GetProcessorApicIndex (CurrentNodeNum, StdHeader); + + TempVar_a = (Mnc * ProcessorCount) + IoApicNum; + ASSERT (TempVar_a < 255); + + // Apply apic enumeration rules + // For systems with >= 16 APICs, put the IO-APICs at 0..n and + // put the local-APICs at m..z + // For systems with < 16 APICs, put the Local-APICs at 0..n and + // put the IO-APICs at (n + 1)..z + // This is needed because many IO-APIC devices only have 4 bits + // for their APIC id and therefore must reside at 0..15 + StartLocalApicId = 0; + if (TempVar_a >= 16) { + if (IoApicNum >= 1) { + StartLocalApicId = (IoApicNum - 1) / Mnc; + StartLocalApicId = (StartLocalApicId + 1) * Mnc; + } + } + + // Set local apic id + TempVar_a = (ProcessorApicIndex * Mnc) + CurrentCore + StartLocalApicId; + IDS_HDT_CONSOLE (CPU_TRACE, " Node %d core %d APIC ID = 0x%x\n", CurrentNodeNum, CurrentCore, TempVar_a); + TempVar_a = TempVar_a << APIC20_ApicId; + + // Enable local apic id + LibAmdMsrRead (MSR_APIC_BAR, &MsrData, StdHeader); + MsrData |= APIC_ENABLE_BIT; + LibAmdMsrWrite (MSR_APIC_BAR, &MsrData, StdHeader); + + // Get local apic base Address + ApUtilGetLocalApicBase (&LocalApicBase, StdHeader); + + Address = LocalApicBase + APIC_ID_REG; + LibAmdMemWrite (AccessWidth32, Address, &TempVar_a, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Initialize the Local APIC at the AmdInitEarly entry point. + * + * This function acts as a wrapper for calling the LocalApicInitialization + * routine at AmdInitEarly. + * + * @param[in] FamilyServices The current Family Specific Services. + * @param[in] EarlyParams Service parameters. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +LocalApicInitializationAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_TESTPOINT (TpProcCpuLocalApicInit, StdHeader); + LocalApicInitialization (EarlyParams, StdHeader); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Main entry point for all APs in the system. + * + * This routine puts the AP cores in an infinite loop in which the cores + * will poll their masters, waiting to be told to perform a task. At early, + * all socket-relative core zeros will receive their tasks from the BSC. + * All others will receive their tasks from the core zero of their local + * processor. At the end of AmdInitEarly, all cores will switch to receiving + * their tasks from the BSC. + * + * @param[in] StdHeader Handle to config for library and services. + * @param[in] CpuEarlyParams AMD_CPU_EARLY_PARAMS pointer. + * + */ +VOID +ApEntry ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams + ) +{ + UINT8 RemoteCmd; + UINT8 SourceSocket; + UINT8 CommandStart; + UINT32 ApFlags; + UINT32 FuncType; + UINT32 ReturnCode; + UINT32 CurrentSocket; + UINT32 CurrentCore; + UINT32 *InputDataPtr; + UINT32 BscSocket; + UINT32 Ignored; + UINT32 TargetApicId; + AP_FUNCTION_PTR FuncAddress; + IDT_DESCRIPTOR IdtDesc[32]; + AP_DATA_TRANSFER DataTransferInfo; + AGESA_STATUS IgnoredSts; + + ASSERT (!IsBsp (StdHeader, &IgnoredSts)); + + // Initialize local variables + ReturnCode = 0; + DataTransferInfo.DataTransferFlags = 0; + InputDataPtr = NULL; + + // Determine the executing core's socket and core numbers + IdentifyCore (StdHeader, &CurrentSocket, &Ignored, &CurrentCore, &IgnoredSts); + + IDS_HDT_CONSOLE (CPU_TRACE, " Socket %d core %d begin AP tasking engine\n", CurrentSocket, CurrentCore); + + // Determine the BSC's socket number + GetSocketModuleOfNode ((UINT32) 0x00000000, &BscSocket, &Ignored, StdHeader); + + // Setup Interrupt Descriptor Table for sleep mode + ApUtilSetupIdtForHlt (&IdtDesc[2], StdHeader); + + // Indicate to the BSC that we have reached the tasking engine + ApUtilWriteControlByte (CORE_IDLE, StdHeader); + + if (CurrentCore == 0) { + // Core 0s receive their tasks from the BSC + SourceSocket = (UINT8) BscSocket; + } else { + // All non-zero cores receive their tasks from the core 0 of their socket + SourceSocket = (UINT8) CurrentSocket; + } + + GetLocalApicIdForCore (SourceSocket, 0, &TargetApicId, StdHeader); + + // Determine the unique value that the master will write when it has a task + // for this core to perform. + CommandStart = ApUtilCalculateUniqueId ( + (UINT8)CurrentSocket, + (UINT8)CurrentCore, + StdHeader + ); + for (;;) { + RemoteCmd = ApUtilReadRemoteControlByte (TargetApicId, StdHeader); + if (RemoteCmd == CommandStart) { + ApFlags = ApUtilReadRemoteDataDword (TargetApicId, StdHeader); + + ApUtilReceivePointer (TargetApicId, (VOID **) &FuncAddress, StdHeader); + + FuncType = ApFlags & (UINT32) (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS); + if ((ApFlags & AP_TASK_HAS_INPUT) != 0) { + DataTransferInfo.DataSizeInDwords = 0; + DataTransferInfo.DataPtr = NULL; + DataTransferInfo.DataTransferFlags = 0; + if (ApUtilReceiveBuffer (SourceSocket, 0, &DataTransferInfo, StdHeader) == AGESA_ERROR) { + // There is not enough space to put the input data on the heap. Undefined behavior is about + // to result. + IDS_ERROR_TRAP; + } + InputDataPtr = (UINT32 *) DataTransferInfo.DataPtr; + } + ApUtilWriteControlByte (CORE_ACTIVE, StdHeader); + switch (FuncType) { + case 0: + FuncAddress.PfApTask (StdHeader); + break; + case AP_TASK_HAS_INPUT: + FuncAddress.PfApTaskI (InputDataPtr, StdHeader); + break; + case AP_PASS_EARLY_PARAMS: + FuncAddress.PfApTaskC (StdHeader, CpuEarlyParams); + break; + case (AP_TASK_HAS_INPUT | AP_PASS_EARLY_PARAMS): + FuncAddress.PfApTaskIC (InputDataPtr, StdHeader, CpuEarlyParams); + break; + case AP_TASK_HAS_OUTPUT: + ReturnCode = FuncAddress.PfApTaskO (StdHeader); + break; + case (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT): + ReturnCode = FuncAddress.PfApTaskIO (InputDataPtr, StdHeader); + break; + case (AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS): + ReturnCode = FuncAddress.PfApTaskOC (StdHeader, CpuEarlyParams); + break; + case (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS): + ReturnCode = FuncAddress.PfApTaskIOC (InputDataPtr, StdHeader, CpuEarlyParams); + break; + default: + ReturnCode = 0; + break; + } + if (((ApFlags & AP_RETURN_PARAMS) != 0)) { + ApUtilTransmitBuffer (SourceSocket, 0, &DataTransferInfo, StdHeader); + } + if ((ApFlags & AP_TASK_HAS_OUTPUT) != 0) { + ApUtilWriteDataDword (ReturnCode, StdHeader); + } + if ((ApFlags & AP_END_AT_HLT) != 0) { + RemoteCmd = CORE_IDLE_HLT; + } else { + ApUtilWriteControlByte (CORE_IDLE, StdHeader); + } + } + if (RemoteCmd == CORE_IDLE_HLT) { + SourceSocket = (UINT8) BscSocket; + GetLocalApicIdForCore (SourceSocket, 0, &TargetApicId, StdHeader); + ApUtilWriteControlByte (CORE_IDLE_HLT, StdHeader); + ExecuteHltInstruction (StdHeader); + ApUtilWriteControlByte (CORE_IDLE, StdHeader); + } + } +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Reads the 'control byte' on the designated remote core. + * + * This function will read the current contents of the control byte + * on the designated core using the APIC remote read inter- + * processor interrupt sequence. + * + * @param[in] TargetApicId Local APIC ID of the desired core + * @param[in] StdHeader Configuration parameters pointer + * + * @return The current value of the remote cores control byte + * + */ +UINT8 +ApUtilReadRemoteControlByte ( + IN UINT32 TargetApicId, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 ControlByte; + UINT32 ApicRegister; + + ApicRegister = ApUtilRemoteRead (TargetApicId, APIC_CTRL_DWORD, StdHeader); + ControlByte = (UINT8) ((ApicRegister & APIC_CTRL_MASK) >> APIC_CTRL_SHIFT); + return (ControlByte); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Writes the 'control byte' on the executing core. + * + * This function writes data to a local APIC offset used in inter- + * processor communication. + * + * @param[in] Value + * @param[in] StdHeader + * + */ +VOID +ApUtilWriteControlByte ( + IN UINT8 Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 ApicRegister; + + ApicRegister = ApUtilLocalRead (APIC_CTRL_REG, StdHeader); + ApicRegister = ((ApicRegister & ~APIC_CTRL_MASK) | (UINT32) (Value << APIC_CTRL_SHIFT)); + ApUtilLocalWrite (APIC_CTRL_REG, ApicRegister, StdHeader); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Reads the 'data dword' on the designated remote core. + * + * This function will read the current contents of the data dword + * on the designated core using the APIC remote read inter- + * processor interrupt sequence. + * + * @param[in] TargetApicId Local APIC ID of the desired core + * @param[in] StdHeader Configuration parameters pointer + * + * @return The current value of the remote core's data dword + * + */ +UINT32 +ApUtilReadRemoteDataDword ( + IN UINT32 TargetApicId, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return (ApUtilRemoteRead (TargetApicId, APIC_DATA_DWORD, StdHeader)); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Writes the 'data dword' on the executing core. + * + * This function writes data to a local APIC offset used in inter- + * processor communication. + * + * @param[in] Value Value to write + * @param[in] StdHeader Configuration parameters pointer + * + */ +VOID +ApUtilWriteDataDword ( + IN UINT32 Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + ApUtilLocalWrite (APIC_DATA_REG, Value, StdHeader); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Runs the given task on the specified local core. + * + * This function is used to invoke an AP to run a specified AGESA + * procedure. It can only be called by cores that have subordinate + * APs -- the BSC at POST, or any socket-relative core 0s at Early. + * + * @param[in] Socket Socket number of the target core + * @param[in] Core Core number of the target core + * @param[in] TaskPtr Function descriptor + * @param[in] StdHeader Configuration parameters pointer + * + * @return Return value of the task that the AP core ran, + * or zero if the task was VOID. + * + */ +UINT32 +ApUtilRunCodeOnSocketCore ( + IN UINT8 Socket, + IN UINT8 Core, + IN AP_TASK *TaskPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 CoreId; + UINT8 CurrentStatus; + UINT8 WaitStatus[3]; + UINT32 ApFlags; + UINT32 ReturnCode; + UINT32 TargetApicId; + AP_WAIT_FOR_STATUS WaitForStatus; + + ApFlags = 0; + ReturnCode = 0; + + CoreId = ApUtilCalculateUniqueId (Socket, Core, StdHeader); + + GetLocalApicIdForCore (Socket, Core, &TargetApicId, StdHeader); + + if (TaskPtr->DataTransfer.DataSizeInDwords != 0) { + ApFlags |= AP_TASK_HAS_INPUT; + if (((TaskPtr->ExeFlags & RETURN_PARAMS) != 0) && + ((TaskPtr->DataTransfer.DataTransferFlags & DATA_IN_MEMORY) == 0)) { + ApFlags |= AP_RETURN_PARAMS; + } + } + + if ((TaskPtr->ExeFlags & TASK_HAS_OUTPUT) != 0) { + ApFlags |= AP_TASK_HAS_OUTPUT; + } + + if ((TaskPtr->ExeFlags & END_AT_HLT) != 0) { + ApFlags |= AP_END_AT_HLT; + } + + if ((TaskPtr->ExeFlags & PASS_EARLY_PARAMS) != 0) { + ApFlags |= AP_PASS_EARLY_PARAMS; + } + + WaitStatus[0] = CORE_IDLE; + WaitStatus[1] = CORE_IDLE_HLT; + WaitStatus[2] = CORE_UNAVAILABLE; + WaitForStatus.Status = WaitStatus; + WaitForStatus.NumberOfElements = 3; + WaitForStatus.RetryCount = WAIT_INFINITELY; + WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY; + CurrentStatus = ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); + + if (CurrentStatus != CORE_UNAVAILABLE) { + ApUtilWriteDataDword (ApFlags, StdHeader); + ApUtilWriteControlByte (CoreId, StdHeader); + + if (CurrentStatus == CORE_IDLE_HLT) { + ApUtilFireDirectedNmi (TargetApicId, StdHeader); + } + + ApUtilTransmitPointer (TargetApicId, (VOID **) &TaskPtr->FuncAddress, StdHeader); + + if ((ApFlags & AP_TASK_HAS_INPUT) != 0) { + ApUtilTransmitBuffer (Socket, Core, &TaskPtr->DataTransfer, StdHeader); + } + + if ((TaskPtr->ExeFlags & WAIT_FOR_CORE) != 0) { + if (((ApFlags & AP_TASK_HAS_INPUT) != 0) && + ((ApFlags & AP_RETURN_PARAMS) != 0) && + ((TaskPtr->DataTransfer.DataTransferFlags & DATA_IN_MEMORY) == 0)) { + if (ApUtilReceiveBuffer (Socket, Core, &TaskPtr->DataTransfer, StdHeader) == AGESA_ERROR) { + // There is not enough space to put the return data. This should never occur. If it + // does, this would point to strange heap corruption. + IDS_ERROR_TRAP; + } + } + + ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); + if ((ApFlags & AP_TASK_HAS_OUTPUT) != 0) { + ReturnCode = ApUtilReadRemoteDataDword (TargetApicId, StdHeader); + } + } + } else { + ReturnCode = 0; + } + return (ReturnCode); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Waits for a remote core's control byte value to either be equal or + * not equal to any number of specified values. + * + * This function will loop doing remote read IPIs until the remote core's + * control byte becomes one of the values in the input array if the input + * flags are set for equality. Otherwise, the loop will continue until + * the control byte value is not equal to one of the elements in the + * array. The caller can also specify an iteration count for timeout + * purposes. + * + * @param[in] TargetApicId Local APIC ID of the desired core + * @param[in] WaitParamsPtr Wait parameter structure + * @param[in] StdHeader Configuration parameteres pointer + * + * @return The current value of the remote core's control byte + * + */ +UINT8 +ApUtilWaitForCoreStatus ( + IN UINT32 TargetApicId, + IN AP_WAIT_FOR_STATUS *WaitParamsPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + BOOLEAN IsEqual; + UINT8 CoreStatus; + UINT8 i; + UINT8 j; + + CoreStatus = 0; + for (i = 0; (WaitParamsPtr->RetryCount == WAIT_INFINITELY) || + (i < WaitParamsPtr->RetryCount); ++i) { + CoreStatus = ApUtilReadRemoteControlByte (TargetApicId, StdHeader); + // Determine whether or not the current remote status is equal + // to an element in the array. + IsEqual = FALSE; + for (j = 0; !IsEqual && j < WaitParamsPtr->NumberOfElements; ++j) { + if (CoreStatus == WaitParamsPtr->Status[j]) { + IsEqual = TRUE; + } + } + if ((((WaitParamsPtr->WaitForStatusFlags & WAIT_STATUS_EQUALITY) != 0) && IsEqual) || + (((WaitParamsPtr->WaitForStatusFlags & WAIT_STATUS_EQUALITY) == 0) && !IsEqual)) { + break; + } + } + return (CoreStatus); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Runs the AP task on the executing core. + * + * @param[in] TaskPtr Function descriptor + * @param[in] StdHeader Configuration parameters pointer + * @param[in] ConfigParams Entry point CPU parameters pointer + * + * @return Return value of the task, or zero if the task + * was VOID. + * + */ +UINT32 +ApUtilTaskOnExecutingCore ( + IN AP_TASK *TaskPtr, + IN AMD_CONFIG_PARAMS *StdHeader, + IN VOID *ConfigParams + ) +{ + UINT32 InvocationOptions; + UINT32 ReturnCode; + + ReturnCode = 0; + InvocationOptions = 0; + + if (TaskPtr->DataTransfer.DataSizeInDwords != 0) { + InvocationOptions |= AP_TASK_HAS_INPUT; + } + if ((TaskPtr->ExeFlags & TASK_HAS_OUTPUT) != 0) { + InvocationOptions |= AP_TASK_HAS_OUTPUT; + } + if ((TaskPtr->ExeFlags & PASS_EARLY_PARAMS) != 0) { + InvocationOptions |= AP_PASS_EARLY_PARAMS; + } + + switch (InvocationOptions) { + case 0: + TaskPtr->FuncAddress.PfApTask (StdHeader); + break; + case AP_TASK_HAS_INPUT: + TaskPtr->FuncAddress.PfApTaskI (TaskPtr->DataTransfer.DataPtr, StdHeader); + break; + case AP_PASS_EARLY_PARAMS: + TaskPtr->FuncAddress.PfApTaskC (StdHeader, ConfigParams); + break; + case (AP_TASK_HAS_INPUT | AP_PASS_EARLY_PARAMS): + TaskPtr->FuncAddress.PfApTaskIC (TaskPtr->DataTransfer.DataPtr, StdHeader, ConfigParams); + break; + case AP_TASK_HAS_OUTPUT: + ReturnCode = TaskPtr->FuncAddress.PfApTaskO (StdHeader); + break; + case (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT): + ReturnCode = TaskPtr->FuncAddress.PfApTaskIO (TaskPtr->DataTransfer.DataPtr, StdHeader); + break; + case (AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS): + ReturnCode = TaskPtr->FuncAddress.PfApTaskOC (StdHeader, ConfigParams); + break; + case (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS): + ReturnCode = TaskPtr->FuncAddress.PfApTaskIOC (TaskPtr->DataTransfer.DataPtr, StdHeader, ConfigParams); + break; + default: + ReturnCode = 0; + break; + } + return (ReturnCode); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Sets up the AP's IDT with NMI (INT2) being the only valid descriptor + * + * This function prepares the executing AP core for recovering from a hlt + * instruction by initializing its IDTR. + * + * @param[in] NmiIdtDescPtr Pointer to a writable IDT entry to + * be used for NMIs + * @param[in] StdHeader Configuration parameters pointer + * + */ +VOID +STATIC +ApUtilSetupIdtForHlt ( + IN IDT_DESCRIPTOR *NmiIdtDescPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 DescSize; + UINT64 HandlerOffset; + UINT64 EferRegister; + IDT_BASE_LIMIT IdtInfo; + + LibAmdMsrRead (MSR_EXTENDED_FEATURE_EN, &EferRegister, StdHeader); + if ((EferRegister & 0x100) != 0) { + DescSize = 16; + } else { + DescSize = 8; + } + + HandlerOffset = (UINT64) (UINTN) NmiHandler; + NmiIdtDescPtr->OffsetLo = (UINT16) HandlerOffset & 0xFFFF; + NmiIdtDescPtr->OffsetHi = (UINT16) (HandlerOffset >> 16); + GetCsSelector (&NmiIdtDescPtr->Selector, StdHeader); + NmiIdtDescPtr->Flags = IDT_DESC_PRESENT | IDT_DESC_TYPE_INT32; + NmiIdtDescPtr->Rsvd = 0; + NmiIdtDescPtr->Offset64 = (UINT32) (HandlerOffset >> 32); + NmiIdtDescPtr->Rsvd64 = 0; + IdtInfo.Limit = (UINT16) ((DescSize * 3) - 1); + IdtInfo.Base = (UINT64) (UINTN) NmiIdtDescPtr - (DescSize * 2); + IDS_EXCEPTION_TRAP (IDS_IDT_UPDATE_EXCEPTION_VECTOR_FOR_AP, &IdtInfo, StdHeader); + SetIdtr (&IdtInfo , StdHeader); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Calculate the APIC ID for a given core. + * + * Get the current node's apic id and deconstruct it to the base id of local apic id space. + * Then construct the target's apic id using that base. + * @b Assumes: The target Socket and Core exist! + * Other Notes: + * - Must run after HT initialization is complete. + * - Code sync: This calculation MUST match the assignment + * calculation done above in LocalApicInitializationAtEarly function. + * - Assumes family homogeneous population of all sockets. + * + * @param[in] TargetSocket The socket in which the Core's Processor is installed. + * @param[in] TargetCore The Core on that Processor + * @param[out] LocalApicId Its APIC Id + * @param[in] StdHeader Handle to header for library and services. + * + */ +VOID +GetLocalApicIdForCore ( + IN UINT32 TargetSocket, + IN UINT32 TargetCore, + OUT UINT32 *LocalApicId, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 CoreIdBits; + UINT32 CurrentNode; + UINT32 CurrentCore; + UINT32 TargetNode; + UINT32 MaxCoresInProcessor; + UINT32 TotalCores; + UINT32 CurrentLocalApicId; + UINT64 LocalApicBase; + UINT32 TempVar_a; + UINT64 Address; + UINT32 ProcessorApicIndex; + BOOLEAN ReturnResult; + CPUID_DATA CpuidData; + + TargetNode = 0; + + // Get local apic base Address + ApUtilGetLocalApicBase (&LocalApicBase, StdHeader); + Address = LocalApicBase + APIC_ID_REG; + + LibAmdMemRead (AccessWidth32, Address, &TempVar_a, StdHeader); + + // ApicId [7:0] + CurrentLocalApicId = (TempVar_a >> APIC20_ApicId) & 0x000000FF; + + GetCurrentNodeAndCore (&CurrentNode, &CurrentCore, StdHeader); + LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuidData, StdHeader); + CoreIdBits = (CpuidData.ECX_Reg & 0x0000F000) >> 12; + MaxCoresInProcessor = (1 << CoreIdBits); + + // Get the APIC Index of this processor. + ProcessorApicIndex = GetProcessorApicIndex (CurrentNode, StdHeader); + + TotalCores = (MaxCoresInProcessor * ProcessorApicIndex) + CurrentCore; + CurrentLocalApicId -= TotalCores; + + // Use the Node Id of TargetSocket, Module 0. No socket transitions are missed or added, + // even if the TargetCore is not on Module 0 in that processor and that's all that matters now. + ReturnResult = GetNodeId (TargetSocket, 0, (UINT8 *)&TargetNode, StdHeader); + ASSERT (ReturnResult); + + // Get the APIC Index of this processor. + ProcessorApicIndex = GetProcessorApicIndex (TargetNode, StdHeader); + + CurrentLocalApicId += ((MaxCoresInProcessor * ProcessorApicIndex) + TargetCore); + *LocalApicId = CurrentLocalApicId; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Securely passes a buffer to the designated remote core. + * + * This function uses a sequence of remote reads to transmit a data + * buffer, one UINT32 at a time. + * + * @param[in] Socket Socket number of the remote core + * @param[in] Core Core number of the remote core + * @param[in] BufferInfo Information about the buffer to pass, and + * how to pass it + * @param[in] StdHeader Configuration parameters pointer + * + */ +VOID +ApUtilTransmitBuffer ( + IN UINT8 Socket, + IN UINT8 Core, + IN AP_DATA_TRANSFER *BufferInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 TargetCore; + UINT8 MyUniqueId; + UINT8 CurrentStatus; + UINT32 *CurrentPtr; + UINT32 i; + UINT32 MyCore; + UINT32 MySocket; + UINT32 Ignored; + UINT32 TargetApicId; + AP_WAIT_FOR_STATUS WaitForStatus; + AGESA_STATUS IgnoredSts; + + GetLocalApicIdForCore ((UINT32) Socket, (UINT32) Core, &TargetApicId, StdHeader); + + if ((BufferInfo->DataTransferFlags & DATA_IN_MEMORY) != 0) { + ApUtilWriteDataDword ((UINT32) 0x00000000, StdHeader); + } else { + ApUtilWriteDataDword ((UINT32) BufferInfo->DataSizeInDwords, StdHeader); + } + TargetCore = ApUtilCalculateUniqueId (Socket, Core, StdHeader); + + ApUtilWriteControlByte (TargetCore, StdHeader); + + IdentifyCore (StdHeader, &MySocket, &Ignored, &MyCore, &IgnoredSts); + + MyUniqueId = ApUtilCalculateUniqueId ((UINT8)MySocket, (UINT8)MyCore, StdHeader); + + WaitForStatus.Status = &MyUniqueId; + WaitForStatus.NumberOfElements = 1; + WaitForStatus.RetryCount = WAIT_INFINITELY; + WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY; + + ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); + ApUtilWriteDataDword (BufferInfo->DataTransferFlags, StdHeader); + + ApUtilWriteControlByte (CORE_DATA_FLAGS_READY, StdHeader); + WaitForStatus.WaitForStatusFlags = 0; + ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); + if ((BufferInfo->DataTransferFlags & DATA_IN_MEMORY) != 0) { + ApUtilTransmitPointer (TargetApicId, (VOID **) &BufferInfo->DataPtr, StdHeader); + } else { + ApUtilWriteControlByte (CORE_STS_DATA_READY_1, StdHeader); + CurrentStatus = CORE_STS_DATA_READY_0; + WaitForStatus.Status = &CurrentStatus; + WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY; + ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); + WaitForStatus.WaitForStatusFlags = 0; + CurrentPtr = (UINT32 *) BufferInfo->DataPtr; + for (i = 0; i < BufferInfo->DataSizeInDwords; ++i) { + ApUtilWriteDataDword (*CurrentPtr++, StdHeader); + ApUtilWriteControlByte (CurrentStatus, StdHeader); + ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); + CurrentStatus ^= 0x01; + } + } + ApUtilWriteControlByte (CORE_ACTIVE, StdHeader); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Securely receives a buffer from the designated remote core. + * + * This function uses a sequence of remote reads to receive a data + * buffer, one UINT32 at a time. + * + * @param[in] Socket Socket number of the remote core + * @param[in] Core Core number of the remote core + * @param[in] BufferInfo Information about where to place the buffer + * @param[in] StdHeader Configuration parameters pointer + * + * @retval AGESA_SUCCESS Transaction was successful + * @retval AGESA_ALERT The non-NULL desired location to place + * the buffer was not used as the buffer + * resides in a shared memory space. The + * input data pointer has changed. + * @retval AGESA_ERROR There is not enough room to receive the + * buffer. + * + */ +AGESA_STATUS +ApUtilReceiveBuffer ( + IN UINT8 Socket, + IN UINT8 Core, + IN OUT AP_DATA_TRANSFER *BufferInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 MyUniqueId; + UINT8 SourceUniqueId; + UINT8 CurrentStatus; + UINT32 i; + UINT32 MySocket; + UINT32 MyCore; + UINT32 Ignored; + UINT32 *CurrentPtr; + UINT32 TransactionSize; + UINT32 TargetApicId; + AGESA_STATUS ReturnStatus; + ALLOCATE_HEAP_PARAMS HeapMalloc; + AP_WAIT_FOR_STATUS WaitForStatus; + + ReturnStatus = AGESA_SUCCESS; + IdentifyCore (StdHeader, &MySocket, &Ignored, &MyCore, &ReturnStatus); + + MyUniqueId = ApUtilCalculateUniqueId ((UINT8)MySocket, (UINT8)MyCore, StdHeader); + + GetLocalApicIdForCore ((UINT32) Socket, (UINT32) Core, &TargetApicId, StdHeader); + + WaitForStatus.Status = &MyUniqueId; + WaitForStatus.NumberOfElements = 1; + WaitForStatus.RetryCount = WAIT_INFINITELY; + WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY; + + ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); + TransactionSize = ApUtilReadRemoteDataDword (TargetApicId, StdHeader); + + if (BufferInfo->DataPtr == NULL && TransactionSize != 0) { + HeapMalloc.BufferHandle = AMD_CPU_AP_TASKING_HANDLE; + HeapMalloc.Persist = HEAP_LOCAL_CACHE; + // Deallocate the general purpose heap structure, if it exists. Ignore + // the status in case it does not exist. + HeapDeallocateBuffer (HeapMalloc.BufferHandle, StdHeader); + HeapMalloc.RequestedBufferSize = (TransactionSize * XFER_ELEMENT_SIZE); + if (HeapAllocateBuffer (&HeapMalloc, StdHeader) == AGESA_SUCCESS) { + BufferInfo->DataPtr = (UINT32 *) HeapMalloc.BufferPtr; + BufferInfo->DataSizeInDwords = (UINT16) (HeapMalloc.RequestedBufferSize / XFER_ELEMENT_SIZE); + } else { + BufferInfo->DataSizeInDwords = 0; + } + } + + if (TransactionSize <= BufferInfo->DataSizeInDwords) { + SourceUniqueId = ApUtilCalculateUniqueId (Socket, Core, StdHeader); + ApUtilWriteControlByte (SourceUniqueId, StdHeader); + CurrentStatus = CORE_DATA_FLAGS_READY; + WaitForStatus.Status = &CurrentStatus; + ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); + BufferInfo->DataTransferFlags = ApUtilReadRemoteDataDword (TargetApicId, StdHeader); + ApUtilWriteControlByte (CORE_DATA_FLAGS_ACKNOWLEDGE, StdHeader); + if ((BufferInfo->DataTransferFlags & DATA_IN_MEMORY) != 0) { + if (BufferInfo->DataPtr != NULL) { + ReturnStatus = AGESA_ALERT; + } + ApUtilReceivePointer (TargetApicId, (VOID **) &BufferInfo->DataPtr, StdHeader); + } else { + CurrentStatus = CORE_STS_DATA_READY_1; + ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); + CurrentStatus = CORE_STS_DATA_READY_0; + ApUtilWriteControlByte (CurrentStatus, StdHeader); + CurrentPtr = BufferInfo->DataPtr; + for (i = 0; i < TransactionSize; ++i) { + ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); + *CurrentPtr++ = ApUtilReadRemoteDataDword (TargetApicId, StdHeader); + CurrentStatus ^= 0x01; + ApUtilWriteControlByte (CurrentStatus, StdHeader); + } + } + ApUtilWriteControlByte (CORE_ACTIVE, StdHeader); + } else { + BufferInfo->DataSizeInDwords = (UINT16) TransactionSize; + ReturnStatus = AGESA_ERROR; + } + return (ReturnStatus); +} + + +VOID +RelinquishControlOfAllAPs ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 BscSocket; + UINT32 Ignored; + UINT32 BscCoreNum; + UINT32 Core; + UINT32 Socket; + UINT32 NumberOfSockets; + AP_TASK TaskPtr; + AGESA_STATUS IgnoredSts; + + ASSERT (IsBsp (StdHeader, &IgnoredSts)); + + TaskPtr.FuncAddress.PfApTask = PerformFinalHalt; + TaskPtr.DataTransfer.DataSizeInDwords = 0; + TaskPtr.ExeFlags = WAIT_FOR_CORE; + + IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); + NumberOfSockets = GetPlatformNumberOfSockets (); + + for (Socket = 0; Socket < NumberOfSockets; Socket++) { + if (GetActiveCoresInGivenSocket (Socket, &Core, StdHeader)) { + while (Core-- > 0) { + if ((Socket != BscSocket) || (Core != BscCoreNum)) { + ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); + } + } + } + } +} + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * The last AGESA code that an AP performs + * + * This function, run only by APs, breaks down their cache subsystem, sets up + * for memory to be present upon wake (from IBV Init/Startup IPIs), and halts. + * + * @param[in] StdHeader Config handle for library and services + * + */ +VOID +STATIC +PerformFinalHalt ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 PrimaryCore; + UINT32 HaltFlags; + UINT32 CacheEnDis; + CPU_SPECIFIC_SERVICES *FamilyServices; + + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader); + ASSERT (FamilyServices != NULL); + // CacheEnDis is a family specific flag, that lets the code to decide whether to + // keep the cache control bits set or cleared. + CacheEnDis = FamilyServices->InitCacheDisabled; + + // Determine if the current core has the primary core role. The first core to execute + // in each compute unit has the primary role. + PrimaryCore = (UINT32) IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader); + + // Aggregate the flags for the halt service. + HaltFlags = PrimaryCore | (CacheEnDis << 1); + + ApUtilWriteControlByte (CORE_UNAVAILABLE, StdHeader); + ExecuteFinalHltInstruction (HaltFlags, UserOptions.CfgApMtrrSettingsList, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Reads the APIC register on the designated remote core. + * + * This function uses the remote read inter-processor interrupt protocol + * to read an APIC register from the remote core + * + * @param[in] TargetApicId Local APIC ID of the desired core + * @param[in] RegAddr APIC register to read + * @param[in] StdHeader Configuration parameters pointer + * + * @return The current value of the remote core's desired APIC register + * + */ +UINT32 +STATIC +ApUtilRemoteRead ( + IN UINT32 TargetApicId, + IN UINT8 RegAddr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 ApicRegister; + UINT64 ApicBase; + UINT64 ApicAddr; + + ApUtilGetLocalApicBase (&ApicBase, StdHeader); + TargetApicId <<= LOCAL_APIC_ID; + + do { + ApicAddr = ApicBase + APIC_CMD_HI_REG; + LibAmdMemWrite (AccessWidth32, ApicAddr, &TargetApicId, StdHeader); + ApicAddr = ApicBase + APIC_CMD_LO_REG; + ApicRegister = CMD_REG_TO_READ | (UINT32) RegAddr; + LibAmdMemWrite (AccessWidth32, ApicAddr, &ApicRegister, StdHeader); + do { + LibAmdMemRead (AccessWidth32, ApicAddr, &ApicRegister, StdHeader); + } while ((ApicRegister & CMD_REG_DELIVERY_STATUS) != 0); + while ((ApicRegister & CMD_REG_REMOTE_RD_STS_MSK) == CMD_REG_REMOTE_DELIVERY_PENDING) { + LibAmdMemRead (AccessWidth32, ApicAddr, &ApicRegister, StdHeader); + } + } while ((ApicRegister & CMD_REG_REMOTE_RD_STS_MSK) != CMD_REG_REMOTE_DELIVERY_DONE); + ApicAddr = ApicBase + APIC_REMOTE_READ_REG; + LibAmdMemRead (AccessWidth32, ApicAddr, &ApicRegister, StdHeader); + return (ApicRegister); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Writes an APIC register on the executing core. + * + * This function gets the base address of the executing core's local APIC, + * and writes a UINT32 value to a specified offset. + * + * @param[in] RegAddr APIC register to write to + * @param[in] Value Data to be written to the desired APIC register + * @param[in] StdHeader Configuration parameters pointer + * + */ +VOID +STATIC +ApUtilLocalWrite ( + IN UINT32 RegAddr, + IN UINT32 Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 ApicAddr; + + ApUtilGetLocalApicBase (&ApicAddr, StdHeader); + ApicAddr += RegAddr; + + LibAmdMemWrite (AccessWidth32, ApicAddr, &Value, StdHeader); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Reads an APIC register on the executing core. + * + * This function gets the base address of the executing core's local APIC, + * and reads a UINT32 value from a specified offset. + * + * @param[in] RegAddr APIC register to read from + * @param[in] StdHeader Configuration parameters pointer + * + * @return The current value of the local APIC register + * + */ +UINT32 +STATIC +ApUtilLocalRead ( + IN UINT32 RegAddr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 ApicRegister; + UINT64 ApicAddr; + + ApUtilGetLocalApicBase (&ApicAddr, StdHeader); + ApicAddr += RegAddr; + LibAmdMemRead (AccessWidth32, ApicAddr, &ApicRegister, StdHeader); + + return (ApicRegister); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the 64-bit base address of the executing core's local APIC. + * + * This function reads the APICBASE MSR and isolates the programmed address. + * + * @param[out] ApicBase Base address + * @param[in] StdHeader Configuration parameters pointer + * + */ +VOID +STATIC +ApUtilGetLocalApicBase ( + OUT UINT64 *ApicBase, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + LibAmdMsrRead (MSR_APIC_BAR, ApicBase, StdHeader); + *ApicBase &= LAPIC_BASE_ADDR_MASK; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Determines the unique ID of the input Socket/Core. + * + * This routine converts a socket-core combination to to a number + * that will be used to directly address a particular core. This + * unique value must be less than 128 because we only have a byte + * to use for status. APIC IDs are not guaranteed to be below + * 128. + * + * @param[in] Socket Socket number of the remote core + * @param[in] Core Core number of the remote core + * @param[in] StdHeader Configuration parameters pointer + * + * @return The unique ID of the desired core + * + */ +UINT8 +STATIC +ApUtilCalculateUniqueId ( + IN UINT8 Socket, + IN UINT8 Core, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 UniqueId; + + UniqueId = ((Core << 3) | Socket); + ASSERT ((UniqueId & 0x80) == 0); + return (UniqueId); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Wakes up a core from the halted state. + * + * This function sends a directed NMI inter-processor interrupt to + * the input Socket/Core. + * + * @param[in] TargetApicId Local APIC ID of the desired core + * @param[in] StdHeader Configuration parameters pointer + * + */ +VOID +STATIC +ApUtilFireDirectedNmi ( + IN UINT32 TargetApicId, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + TargetApicId <<= LOCAL_APIC_ID; + + ApUtilLocalWrite ((UINT32) APIC_CMD_HI_REG, TargetApicId, StdHeader); + ApUtilLocalWrite ((UINT32) APIC_CMD_LO_REG, (UINT32) CMD_REG_TO_NMI, StdHeader); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Securely receives a pointer from the designated remote core. + * + * This function uses a sequence of remote reads to receive a pointer, + * one UINT32 at a time. + * + * @param[in] TargetApicId Local APIC ID of the desired core + * @param[out] ReturnPointer Pointer passed from remote core + * @param[in] StdHeader Configuration parameters pointer + * + */ +VOID +STATIC +ApUtilReceivePointer ( + IN UINT32 TargetApicId, + OUT VOID **ReturnPointer, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + UINT8 WaitStatus; + UINT32 *AddressScratchPtr; + AP_WAIT_FOR_STATUS WaitForStatus; + + WaitStatus = CORE_STS_DATA_READY_0; + WaitForStatus.Status = &WaitStatus; + WaitForStatus.NumberOfElements = 1; + WaitForStatus.RetryCount = WAIT_INFINITELY; + AddressScratchPtr = (UINT32 *) ReturnPointer; + for (i = 0; i < SIZE_IN_DWORDS (AddressScratchPtr); ++i) { + ApUtilWriteControlByte (CORE_NEEDS_PTR, StdHeader); + WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY; + ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); + *AddressScratchPtr++ = ApUtilReadRemoteDataDword (TargetApicId, StdHeader); + ApUtilWriteControlByte (CORE_ACTIVE, StdHeader); + WaitForStatus.WaitForStatusFlags = 0; + ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); + } +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Securely transmits a pointer to the designated remote core. + * + * This function uses a sequence of remote reads to transmit a pointer, + * one UINT32 at a time. + * + * @param[in] TargetApicId Local APIC ID of the desired core + * @param[out] Pointer Pointer passed from remote core + * @param[in] StdHeader Configuration parameters pointer + * + */ +VOID +STATIC +ApUtilTransmitPointer ( + IN UINT32 TargetApicId, + IN VOID **Pointer, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + UINT8 WaitStatus; + UINT32 *AddressScratchPtr; + AP_WAIT_FOR_STATUS WaitForStatus; + + WaitStatus = CORE_NEEDS_PTR; + WaitForStatus.Status = &WaitStatus; + WaitForStatus.NumberOfElements = 1; + WaitForStatus.RetryCount = WAIT_INFINITELY; + + AddressScratchPtr = (UINT32 *) Pointer; + + for (i = 0; i < SIZE_IN_DWORDS (AddressScratchPtr); i++) { + WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY; + ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); + ApUtilWriteDataDword (*AddressScratchPtr++, StdHeader); + ApUtilWriteControlByte (CORE_STS_DATA_READY_0, StdHeader); + WaitForStatus.WaitForStatusFlags = 0; + ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); + ApUtilWriteControlByte (CORE_ACTIVE, StdHeader); + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuApicUtilities.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuApicUtilities.h new file mode 100644 index 0000000..3c8e4de --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuApicUtilities.h @@ -0,0 +1,330 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU APIC related utility functions and structures + * + * Contains code that provides mechanism to invoke and control APIC communication. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_APIC_UTILITIES_H_ +#define _CPU_APIC_UTILITIES_H_ + + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ +#define APIC_CTRL_DWORD 0xF +#define APIC_CTRL_REG (APIC_CTRL_DWORD << 4) +#define APIC_CTRL_MASK 0xFF +#define APIC_CTRL_SHIFT 0 + +#define APIC_DATA_DWORD 0x38 +#define APIC_DATA_REG (APIC_DATA_DWORD << 4) + +#define APIC_REMOTE_READ_REG 0xC0 +#define APIC_CMD_LO_REG 0x300 +#define APIC_CMD_HI_REG 0x310 + +// APIC_CMD_LO_REG bits +#define CMD_REG_DELIVERY_STATUS 0x1000 +#define CMD_REG_TO_READ 0x300 +#define CMD_REG_REMOTE_RD_STS_MSK 0x30000ul +#define CMD_REG_REMOTE_DELIVERY_PENDING 0x10000ul +#define CMD_REG_REMOTE_DELIVERY_DONE 0x20000ul +#define CMD_REG_TO_NMI 0x400 + +// ExeFlags bits +#define WAIT_FOR_CORE 0x00000001ul +#define TASK_HAS_OUTPUT 0x00000002ul +#define RETURN_PARAMS 0x00000004ul +#define END_AT_HLT 0x00000008ul +#define PASS_EARLY_PARAMS 0x00000010ul + +// Control Byte Values +// bit 7 indicates the type of message +// 1 - control message +// 0 - launch + APIC ID = message to go +// +#define CORE_UNAVAILABLE 0xFF +#define CORE_IDLE 0xFE +#define CORE_IDLE_HLT 0xFD +#define CORE_ACTIVE 0xFC +#define CORE_NEEDS_PTR 0xFB +#define CORE_NEEDS_DATA_SIZE 0xFA +#define CORE_STS_DATA_READY_1 0xF9 +#define CORE_STS_DATA_READY_0 0xF8 +#define CORE_DATA_FLAGS_READY 0xF7 +#define CORE_DATA_FLAGS_ACKNOWLEDGE 0xF6 +#define CORE_DATA_PTR_READY 0xF5 + +// Macro used to determine the number of dwords to transmit to the AP as input +#define SIZE_IN_DWORDS(sInput) ((UINT32) (((sizeof (sInput)) + 3) >> 2)) + +// IDT table +#define IDT_DESC_PRESENT 0x80 + +#define IDT_DESC_TYPE_LDT 0x02 +#define IDT_DESC_TYPE_CALL16 0x04 +#define IDT_DESC_TYPE_TASK 0x05 +#define IDT_DESC_TYPE_INT16 0x06 +#define IDT_DESC_TYPE_TRAP16 0x07 +#define IDT_DESC_TYPE_CALL32 0x0C +#define IDT_DESC_TYPE_INT32 0x0E +#define IDT_DESC_TYPE_TRAP32 0x0F +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ +typedef VOID (*PF_AP_TASK) (AMD_CONFIG_PARAMS *StdHeader); +typedef VOID (*PF_AP_TASK_I) (VOID *, AMD_CONFIG_PARAMS *StdHeader); +typedef VOID (*PF_AP_TASK_C) (AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *); +typedef VOID (*PF_AP_TASK_IC) (VOID *, AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *); +typedef UINT32 (*PF_AP_TASK_O) (AMD_CONFIG_PARAMS *StdHeader); +typedef UINT32 (*PF_AP_TASK_IO) (VOID *, AMD_CONFIG_PARAMS *StdHeader); +typedef UINT32 (*PF_AP_TASK_OC) (AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *); +typedef UINT32 (*PF_AP_TASK_IOC) (VOID *, AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *); + +/// Function pointer union representing the eight different +/// types of functions that an AP can be asked to perform. +typedef union { + PF_AP_TASK PfApTask; ///< AMD_CONFIG_PARAMS * input with no output + PF_AP_TASK_I PfApTaskI; ///< VOID * + AMD_CONFIG_PARAMS * input with no output + PF_AP_TASK_C PfApTaskC; ///< AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with no output + PF_AP_TASK_IC PfApTaskIC; ///< VOID * + AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with no output + PF_AP_TASK_O PfApTaskO; ///< AMD_CONFIG_PARAMS * input with UINT32 output + PF_AP_TASK_IO PfApTaskIO; ///< VOID * + AMD_CONFIG_PARAMS * input with UINT32 output + PF_AP_TASK_OC PfApTaskOC; ///< AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with UINT32 output + PF_AP_TASK_IOC PfApTaskIOC; ///< VOID * + AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with UINT32 output +} AP_FUNCTION_PTR; + +/// Input structure for ApUtilTransmitBuffer and ApUtilReceiveBuffer +/// containing information about the data transfer from one core +/// to another. +typedef struct { + IN OUT UINT16 DataSizeInDwords; ///< Size of the data to be transferred rounded up to the nearest dword + IN OUT VOID *DataPtr; ///< Pointer to the data + IN UINT32 DataTransferFlags; ///< Flags dictating certain aspects of the data transfer +} AP_DATA_TRANSFER; + +/// Input structure for ApUtilRunCodeOnSocketCore. +typedef struct _AP_TASK { + AP_FUNCTION_PTR FuncAddress; ///< Pointer to the function that the AP will run + AP_DATA_TRANSFER DataTransfer; ///< Data transfer struct for optionally passing data that the AP should use as input to the function + UINT32 ExeFlags; ///< Flags dictating certain aspects of the AP tasking sequence +} AP_TASK; + +/// Input structure for ApUtilWaitForCoreStatus. +typedef struct { + IN UINT8 *Status; ///< Pointer to the 1st element of an array of values to wait for + IN UINT8 NumberOfElements; ///< Number of elements in the array + IN UINT32 RetryCount; ///< Number of remote read cycles to complete before quitting + IN UINT32 WaitForStatusFlags; ///< Flags dictating certain aspects of ApUtilWaitForCoreStatus +} AP_WAIT_FOR_STATUS; + +/// Interrupt Descriptor Table entry +typedef struct { + UINT16 OffsetLo; ///< Lower 16 bits of the interrupt handler routine's offset + UINT16 Selector; ///< Interrupt handler routine's selector + UINT8 Rsvd; ///< Reserved + UINT8 Flags; ///< Interrupt flags + UINT16 OffsetHi; ///< Upper 16 bits of the interrupt handler routine's offset + UINT32 Offset64; ///< High order 32 bits of the handler's offset needed when in 64 bit mode + UINT32 Rsvd64; ///< Reserved +} IDT_DESCRIPTOR; + +/// Structure needed to load the IDTR using the lidt instruction +typedef struct { + UINT16 Limit; ///< Interrupt Descriptor Table size + UINT64 Base; ///< Interrupt Descriptor Table base address +} IDT_BASE_LIMIT; + +#define WAIT_STATUS_EQUALITY 0x00000001ul +#define WAIT_INFINITELY 0 + +// Data Transfer Flags +#define DATA_IN_MEMORY 0x00000001ul + + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ +// These are P U B L I C functions, used by AGESA +UINT8 +ApUtilReadRemoteControlByte ( + IN UINT32 TargetApicId, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +ApUtilWriteControlByte ( + IN UINT8 Value, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +ApUtilReadRemoteDataDword ( + IN UINT32 TargetApicId, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +ApUtilWriteDataDword ( + IN UINT32 Value, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +ApUtilRunCodeOnSocketCore ( + IN UINT8 Socket, + IN UINT8 Core, + IN AP_TASK *TaskPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +ApUtilWaitForCoreStatus ( + IN UINT32 TargetApicId, + IN AP_WAIT_FOR_STATUS *WaitParamsPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +ApEntry ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams + ); + +UINT32 +ApUtilTaskOnExecutingCore ( + IN AP_TASK *TaskPtr, + IN AMD_CONFIG_PARAMS *StdHeader, + IN VOID *ConfigParams + ); + +VOID +ApUtilTransmitBuffer ( + IN UINT8 Socket, + IN UINT8 Core, + IN AP_DATA_TRANSFER *BufferInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +ApUtilReceiveBuffer ( + IN UINT8 Socket, + IN UINT8 Core, + IN OUT AP_DATA_TRANSFER *BufferInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GetLocalApicIdForCore ( + IN UINT32 TargetSocket, + IN UINT32 TargetCore, + OUT UINT32 *LocalApicId, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +ApUtilRunCodeOnAllLocalCoresAtEarly ( + IN AP_TASK *TaskPtr, + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr + ); + +VOID +RelinquishControlOfAllAPs ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GetCsSelector ( + IN UINT16 *Selector, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +SetIdtr ( + IN IDT_BASE_LIMIT *IdtInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GetIdtr ( + IN IDT_BASE_LIMIT *IdtInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif /* _CPU_APIC_UTILITIES_H_ */ + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuBist.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuBist.c new file mode 100644 index 0000000..5249f9c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuBist.c @@ -0,0 +1,198 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU BIST Status Check Implementation. + * + * Implement CPU BIST Status checking + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "GeneralServices.h" +#include "cpuServices.h" +#include "cpuApicUtilities.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) +#define FILECODE PROC_CPU_CPUBIST_FILECODE + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +UINT32 +STATIC +GetBistResults ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + + /*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + /*---------------------------------------------------------------------------------------*/ + /** + * + * This function checks the status of BIST and places the error status in the event log + * if there are any errors + * + * @param[in] StdHeader Header for library and services + * + * @retval AGESA_SUCCESS No BIST errors have been logged. + * @retval AGESA_ALERT BIST errors have been detected and added to the + * event log. + */ +AGESA_STATUS +CheckBistStatus ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Socket; + UINT32 Core; + UINT32 BscSocket; + UINT32 BscCoreNum; + UINT32 NumberOfSockets; + UINT32 NumberOfCores; + UINT32 Ignored; + UINT32 ReturnCode; + AGESA_STATUS IgnoredSts; + AGESA_STATUS AgesaStatus; + AP_TASK TaskPtr; + + // Make sure that Standard Header is valid + ASSERT (StdHeader != NULL); + ASSERT (IsBsp (StdHeader, &IgnoredSts)); + + AgesaStatus = AGESA_SUCCESS; + + // Get the BscSocket, BscCoreNum and NumberOfSockets in the system + IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); + NumberOfSockets = GetPlatformNumberOfSockets (); + + // Setup TaskPtr struct to execute routine on APs + TaskPtr.FuncAddress.PfApTaskO = GetBistResults; + TaskPtr.DataTransfer.DataSizeInDwords = 0; + TaskPtr.ExeFlags = TASK_HAS_OUTPUT | WAIT_FOR_CORE; + + for (Socket = 0; Socket < NumberOfSockets; Socket++) { + if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { + for (Core = 0; Core < NumberOfCores; Core++) { + if ((Socket != BscSocket) || (Core != BscCoreNum)) { + ReturnCode = ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, &TaskPtr, StdHeader); + } else { + ReturnCode = TaskPtr.FuncAddress.PfApTaskO (StdHeader); + } + + // If BIST value is non-zero, add to BSP's event log + if (ReturnCode != 0) { + IDS_HDT_CONSOLE (CPU_TRACE, " BIST failure: socket %d core %d, status = 0x%x\n", Socket, Core, ReturnCode); + AgesaStatus = AGESA_ALERT; + PutEventLog (AGESA_ALERT, + CPU_EVENT_BIST_ERROR, + ReturnCode, Socket, Core, 0, StdHeader); + } + } + } + } + + return AgesaStatus; +} + +/*---------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- +*/ + +/*---------------------------------------------------------------------------------------*/ +/** + * + * Reads the lower 32 bits of the BIST register + * + * @param[in] StdHeader Header for library and services + * + * @retval Value of the BIST register +*/ +UINT32 +STATIC +GetBistResults ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 BistResults; + + // Read MSRC001_0060 BIST Results Register + LibAmdMsrRead (MSR_BIST, &BistResults, StdHeader); + + return (UINT32) (BistResults & 0xFFFFFFFF); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuBrandId.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuBrandId.c new file mode 100644 index 0000000..e296e3c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuBrandId.c @@ -0,0 +1,339 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU BrandId related functions. + * + * Contains code that provides CPU BrandId information + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "OptionPstate.h" +#include "cpuRegisters.h" +#include "cpuFamilyTranslation.h" +#include "cpuEarlyInit.h" +#include "cpuRegisters.h" +#include "heapManager.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) +#define FILECODE PROC_CPU_CPUBRANDID_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +CONST CHAR8 ROMDATA strEngSample[] = "AMD Engineering Sample"; +CONST CHAR8 ROMDATA strTtkSample[] = "AMD Thermal Test Kit"; +CONST CHAR8 ROMDATA strUnknown[] = "AMD Processor Model Unknown"; + +CONST AMD_CPU_BRAND ROMDATA EngSample_Str = {0, 0, 0, SOCKET_IGNORE, strEngSample, sizeof (strEngSample)}; +CONST AMD_CPU_BRAND ROMDATA TtkSample_Str = {0, 1, 0, SOCKET_IGNORE, strTtkSample, sizeof (strTtkSample)}; +CONST AMD_CPU_BRAND ROMDATA Dflt_Str1 = {0, 0, 0, SOCKET_IGNORE, strUnknown, sizeof (strUnknown)}; +CONST AMD_CPU_BRAND ROMDATA Dflt_Str2 = {0, 0, 0, SOCKET_IGNORE, DR_NO_STRING, DR_NO_STRING}; + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +SetBrandIdRegistersAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Program BrandID registers (CPUIDNameStringPtr[0-5]) + * + * This function determines the appropriate brand string for the executing + * core, and programs the namestring MSRs. + * + * @param[in,out] StdHeader Config handle for library and services. + * + */ +VOID +SetBrandIdRegisters ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 SocketIndex; + UINT8 SuffixStatus; + UINT8 TableElements; + UINT8 TableEntryCount; + UINT8 TableEntryIndex; + CHAR8 TempChar; + CHAR8 *NameStringPtr; + CHAR8 *SuffixStringPtr; + CHAR8 *BrandStringPtr; + CHAR8 *TempNameCharPtr; + UINT32 MsrIndex; + UINT32 Quotient; + UINT32 Remainder; + UINT64 *MsrNameStringPtrPtr; + CPUID_DATA CpuId; + CPU_LOGICAL_ID CpuLogicalId; + CPU_BRAND_TABLE *SocketTableEntry; + CPU_BRAND_TABLE **SocketTableEntry1; + AMD_CPU_BRAND *SocketTablePtr; + AMD_CPU_BRAND_DATA Data; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + SuffixStatus = 0; + FamilySpecificServices = NULL; + SocketTablePtr = NULL; + SocketTableEntry = NULL; + + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + // Step1: Allocate 48 bytes from Heap space + AllocHeapParams.RequestedBufferSize = CPU_BRAND_ID_LENGTH; + AllocHeapParams.BufferHandle = AMD_BRAND_ID_BUFFER_HANDLE; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { + // Clear NameBuffer + BrandStringPtr = (CHAR8 *) AllocHeapParams.BufferPtr; + LibAmdMemFill (BrandStringPtr, 0, CPU_BRAND_ID_LENGTH, StdHeader); + } else { + PutEventLog ( + AGESA_ERROR, + CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE, + 0, 0, 0, 0, StdHeader + ); + return; + } + + // Step2: Get brandid from model number and model string + LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, StdHeader); + + // Step3: Figure out Socket/Page/Model/String1/String2/Core Number + Data.String2 = (UINT8) (CpuId.EBX_Reg & 0x0f); + Data.Model = (UINT8) ((CpuId.EBX_Reg >> 4) & 0x7f); + Data.String1 = (UINT8) ((CpuId.EBX_Reg >> 11) & 0x0f); + Data.Page = (UINT8) ((CpuId.EBX_Reg >> 15) & 0x01); + Data.Socket = (UINT8) ((CpuId.EBX_Reg >> 28) & 0x0f); + Data.Cores = FamilySpecificServices->GetNumberOfPhysicalCores (FamilySpecificServices, StdHeader); + + // Step4: If NN = 0, we have an engineering sample, no suffix; then jump to Step6 + if (Data.Model == 0) { + if (Data.Page == 0) { + SocketTablePtr = (AMD_CPU_BRAND *)&EngSample_Str; + } else { + SocketTablePtr = (AMD_CPU_BRAND *)&TtkSample_Str; + } + } else { + + // Model is not equal to zero, so decrement it + // For family 10 if PkgType[3:0] is greater than or equal to 2h and families >= 12h + GetLogicalIdOfCurrentCore (&CpuLogicalId, StdHeader); + if ((((CpuLogicalId.Family & AMD_FAMILY_10) != 0) && (Data.Socket >= DR_SOCKET_S1G3)) || + ((CpuLogicalId.Family & AMD_FAMILY_GE_12) != 0)) { + Data.Model--; + } + + // Step5: Search for String1 (there can be only 1) + FamilySpecificServices->GetBrandString1 (FamilySpecificServices, (CONST VOID **) &SocketTableEntry, &TableEntryCount, StdHeader); + SocketTableEntry1 = (CPU_BRAND_TABLE **) SocketTableEntry; + for (TableEntryIndex = 0; ((TableEntryIndex < TableEntryCount) + && (SuffixStatus == 0)); TableEntryIndex++, SocketTableEntry1++) { + if (*SocketTableEntry1 == NULL) { + break; + } + SocketTablePtr = (AMD_CPU_BRAND *) (*SocketTableEntry1)->Table; + TableElements = (*SocketTableEntry1)->NumberOfEntries; + for (SocketIndex = 0; (SocketIndex < TableElements) + && SuffixStatus == 0; SocketIndex++) { + if ((SocketTablePtr->Page == Data.Page) && + (SocketTablePtr->Index == Data.String1) && + (SocketTablePtr->Socket == Data.Socket) && + (SocketTablePtr->Cores == Data.Cores)) { + SuffixStatus = 1; + } else { + SocketTablePtr++; + } + } + } + if (SuffixStatus == 0) { + SocketTablePtr = (AMD_CPU_BRAND *)&Dflt_Str1; // We did not find one, make 'Unknown' + } + } + + // Step6: Copy String into NameBuffer + // We now have data structure pointing to correct type in (*SocketTablePtr) + LibAmdMemCopy (BrandStringPtr, + (CHAR8 *)SocketTablePtr->Stringstart, + SocketTablePtr->Stringlength, + StdHeader); + + // Step7: Get suffix, determine addition to BRANDSPEED + if (SuffixStatus != 0) { + // Turn our value into a decimal string + // We have a value like 37d which we need to turn into '3' '7' + // Divide by 10, store remainder as an ASCII char on stack, repeat until Quotient is 0 + NameStringPtr = BrandStringPtr + SocketTablePtr->Stringlength - 1; + TempNameCharPtr = NameStringPtr; + Quotient = Data.Model; + do { + Remainder = Quotient % 10; + Quotient = Quotient / 10; + *TempNameCharPtr++ = (CHAR8) (Remainder + '0'); // Put suffix into our NameBuffer + } while (Quotient != 0); + if (Data.Model < 10) { + *TempNameCharPtr++ = '0'; + } + + // Step8: Reverse the string sequence and copy into NameBuffer + SuffixStringPtr = TempNameCharPtr--; + while (NameStringPtr < TempNameCharPtr) { + TempChar = *NameStringPtr; + *NameStringPtr = *TempNameCharPtr; + *TempNameCharPtr = TempChar; + NameStringPtr++; + TempNameCharPtr--; + } + + // Step9: Search for String2 + SuffixStatus = 0; + FamilySpecificServices->GetBrandString2 (FamilySpecificServices, (CONST VOID **) &SocketTableEntry, &TableEntryCount, StdHeader); + SocketTableEntry1 = (CPU_BRAND_TABLE **) SocketTableEntry; + for (TableEntryIndex = 0; ((TableEntryIndex < TableEntryCount) + && (SuffixStatus == 0)); TableEntryIndex++, SocketTableEntry1++) { + if (*SocketTableEntry1 == NULL) { + break; + } + SocketTablePtr = (AMD_CPU_BRAND *) (*SocketTableEntry1)->Table; + TableElements = (*SocketTableEntry1)->NumberOfEntries; + for (SocketIndex = 0; (SocketIndex < TableElements) + && SuffixStatus == 0; SocketIndex++) { + if ((SocketTablePtr->Page == Data.Page) && + (SocketTablePtr->Index == Data.String2) && + (SocketTablePtr->Socket == Data.Socket) && + (SocketTablePtr->Cores == Data.Cores)) { + SuffixStatus = 1; + } else { + SocketTablePtr++; + } + } + } + if (SuffixStatus == 0) { + SocketTablePtr = (AMD_CPU_BRAND *)&Dflt_Str2; + } + + // Step10: Copy String2 into our NameBuffer + if (SocketTablePtr->Stringlength != 0) { + LibAmdMemCopy (SuffixStringPtr, + (CHAR8 *)SocketTablePtr->Stringstart, + SocketTablePtr->Stringlength, + StdHeader); + } + } + + // Step11: Put values into name MSRs, Always write the full 48 bytes + MsrNameStringPtrPtr = (UINT64 *) BrandStringPtr; + for (MsrIndex = MSR_CPUID_NAME_STRING0; MsrIndex <= MSR_CPUID_NAME_STRING5; MsrIndex++) { + LibAmdMsrWrite (MsrIndex, MsrNameStringPtrPtr, StdHeader); + MsrNameStringPtrPtr++; + } + HeapDeallocateBuffer (AMD_BRAND_ID_BUFFER_HANDLE, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Program BrandID registers (CPUIDNameStringPtr[0-5]) + * + * This function acts as a wrapper for calling the SetBrandIdRegisters + * routine at AmdInitEarly. + * + * @param[in] FamilyServices The current Family Specific Services. + * @param[in] EarlyParams Service parameters. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +SetBrandIdRegistersAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_TESTPOINT (TpProcCpuSetBrandID, StdHeader); + SetBrandIdRegisters (StdHeader); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.c new file mode 100644 index 0000000..6078ca0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.c @@ -0,0 +1,436 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Reset API, and related functions. + * + * Contains code that initialized the CPU after early reset. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "Table.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "Topology.h" +#include "cpuFamilyTranslation.h" +#include "cpuFeatures.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_CPUEARLYINIT_FILECODE + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern BUILD_OPT_CFG UserOptions; +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +GetPerformEarlyFlag ( + IN OUT UINT32 *PerformEarlyFlag, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +McaInitializationAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +/*------------------------------------------------------------------------------------*/ +/** + * Initializer routine that will be invoked by AmdCpuEarly to initialize the input + * structure for the Cpu Init @ Early routine. + * + * @param[in] StdHeader Opaque handle to standard config header + * @param[in] PlatformConfig Config handle for platform specific information + * @param[in,out] CpuEarlyParamsPtr Service Interface structure to initialize. + * + * @retval AGESA_SUCCESS Always Succeeds + */ +VOID +AmdCpuEarlyInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr + ) +{ + ASSERT (CpuEarlyParamsPtr != NULL); + + CpuEarlyParamsPtr->MemInitPState = (UINT8) UserOptions.CfgMemInitPstate; + CpuEarlyParamsPtr->PlatformConfig = *PlatformConfig; +} +/*---------------------------------------------------------------------------------------*/ +/** + * Performs CPU related initialization at the early entry point + * + * This function performs a large list of initialization items. These items + * include: + * + * -1 local APIC initialization + * -2 MSR table initialization + * -3 PCI table initialization + * -4 HT Phy PCI table initialization + * -5 microcode patch loading + * -6 namestring determination/programming + * -7 AP initialization + * -8 power management initialization + * -9 core leveling + * + * This routine must be run by all cores in the system. Please note that + * all APs that enter will never exit. + * + * @param[in] StdHeader Config handle for library and services + * @param[in] PlatformConfig Config handle for platform specific information + * + * @retval AGESA_SUCCESS + * + */ +AGESA_STATUS +AmdCpuEarly ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig + ) +{ + UINT8 WaitStatus; + UINT8 i; + UINT8 StartCore; + UINT8 EndCore; + UINT32 NodeNum; + UINT32 PrimaryCore; + UINT32 SocketNum; + UINT32 ModuleNum; + UINT32 HighCore; + UINT32 ApHeapIndex; + UINT32 CurrentPerformEarlyFlag; + UINT32 TargetApicId; + AP_WAIT_FOR_STATUS WaitForStatus; + AGESA_STATUS Status; + AGESA_STATUS CalledStatus; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + AMD_CPU_EARLY_PARAMS CpuEarlyParams; + S_PERFORM_EARLY_INIT_ON_CORE *EarlyTableOnCore; + + Status = AGESA_SUCCESS; + CalledStatus = AGESA_SUCCESS; + + AmdCpuEarlyInitializer (StdHeader, PlatformConfig, &CpuEarlyParams); + + IDS_OPTION_HOOK (IDS_CPU_Early_Override, &CpuEarlyParams, StdHeader); + + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + EarlyTableOnCore = NULL; + FamilySpecificServices->GetEarlyInitOnCoreTable (FamilySpecificServices, (CONST S_PERFORM_EARLY_INIT_ON_CORE **)&EarlyTableOnCore, &CpuEarlyParams, StdHeader); + if (EarlyTableOnCore != NULL) { + GetPerformEarlyFlag (&CurrentPerformEarlyFlag, StdHeader); + for (i = 0; EarlyTableOnCore[i].PerformEarlyInitOnCore != NULL; i++) { + if ((EarlyTableOnCore[i].PerformEarlyInitFlag & CurrentPerformEarlyFlag) != 0) { + IDS_HDT_CONSOLE (CPU_TRACE, " Perform core init step %d\n", i); + EarlyTableOnCore[i].PerformEarlyInitOnCore (FamilySpecificServices, &CpuEarlyParams, StdHeader); + } + } + } + + // B S P C O D E T O I N I T I A L I Z E A Ps + // ------------------------------------------------------- + // ------------------------------------------------------- + // IMPORTANT: Here we determine if we are BSP or AP + if (IsBsp (StdHeader, &CalledStatus)) { + + // Even though the bsc does not need to send itself a heap index, this sequence performs other important initialization. + // Use '0' as a dummy heap index value. + GetSocketModuleOfNode (0, &SocketNum, &ModuleNum, StdHeader); + GetCpuServicesOfSocket (SocketNum, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->SetApCoreNumber (FamilySpecificServices, SocketNum, ModuleNum, 0, StdHeader); + FamilySpecificServices->TransferApCoreNumber (FamilySpecificServices, StdHeader); + + // Clear BSP's Status Byte + ApUtilWriteControlByte (CORE_ACTIVE, StdHeader); + + NodeNum = 0; + ApHeapIndex = 1; + while (NodeNum < MAX_NODES && + GetSocketModuleOfNode (NodeNum, &SocketNum, &ModuleNum, StdHeader)) { + GetCpuServicesOfSocket (SocketNum, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + GetGivenModuleCoreRange (SocketNum, ModuleNum, &PrimaryCore, &HighCore, StdHeader); + if (NodeNum == 0) { + StartCore = (UINT8) PrimaryCore + 1; + } else { + StartCore = (UINT8) PrimaryCore; + } + + EndCore = (UINT8) HighCore; + for (i = StartCore; i <= EndCore; i++) { + FamilySpecificServices->SetApCoreNumber (FamilySpecificServices, SocketNum, ModuleNum, ApHeapIndex, StdHeader); + IDS_HDT_CONSOLE (CPU_TRACE, " Launch socket %d core %d\n", SocketNum, i); + if (FamilySpecificServices->LaunchApCore (FamilySpecificServices, SocketNum, ModuleNum, i, PrimaryCore, StdHeader)) { + IDS_HDT_CONSOLE (CPU_TRACE, " Waiting for socket %d core %d\n", SocketNum, i); + GetLocalApicIdForCore (SocketNum, i, &TargetApicId, StdHeader); + WaitStatus = CORE_IDLE; + WaitForStatus.Status = &WaitStatus; + WaitForStatus.NumberOfElements = 1; + WaitForStatus.RetryCount = WAIT_INFINITELY; + WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY; + ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); + ApHeapIndex++; + } + } + NodeNum++; + } + + // B S P P h a s e - 1 E N D + + IDS_OPTION_HOOK (IDS_BEFORE_PM_INIT, &CpuEarlyParams, StdHeader); + + AGESA_TESTPOINT (TpProcCpuBeforePMFeatureInit, StdHeader); + IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features before early power mgmt init\n"); + CalledStatus = DispatchCpuFeatures (CPU_FEAT_BEFORE_PM_INIT, PlatformConfig, StdHeader); + if (CalledStatus > Status) { + Status = CalledStatus; + } + + AGESA_TESTPOINT (TpProcCpuPowerMgmtInit, StdHeader); + CalledStatus = PmInitializationAtEarly (&CpuEarlyParams, StdHeader); + if (CalledStatus > Status) { + Status = CalledStatus; + } + + AGESA_TESTPOINT (TpProcCpuEarlyFeatureInit, StdHeader); + IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features after early power mgmt init\n"); + CalledStatus = DispatchCpuFeatures (CPU_FEAT_AFTER_PM_INIT, PlatformConfig, StdHeader); + + IDS_OPTION_HOOK (IDS_BEFORE_AP_EARLY_HALT, &CpuEarlyParams, StdHeader); + + // Sleep all APs + IDS_HDT_CONSOLE (CPU_TRACE, " Halting all APs\n"); + ApUtilWriteControlByte (CORE_IDLE_HLT, StdHeader); + } else { + ApEntry (StdHeader, &CpuEarlyParams); + } + + if (CalledStatus > Status) { + Status = CalledStatus; + } + + return (Status); +} + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Initialize Machine Check Architecture registers + * + * This function initializes the MCA MSRs. On cold reset, these registers + * have an invalid data that must be cleared on all cores. + * + * @param[in] StdHeader Config handle for library and services + * + *--------------------------------------------------------------------------------------- + */ +VOID +McaInitialization ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT16 TempVar16_a; + UINT32 MsrAddress; + UINT64 MsrData; + CPUID_DATA CpuIdDataStruct; + + if (!(IsWarmReset (StdHeader))) { + // Run CPUID to verify that the processor supports MCE and MCA + // i.e. edx[7], and edx[14] + // CPUID_MODEL = 1 + LibAmdCpuidRead (1, &CpuIdDataStruct, StdHeader); + if ((CpuIdDataStruct.EDX_Reg & 0x4080) != 0) { + // Check to see if the MCG_CTL_P bit is set + // MCG = Global Machine Check Exception Reporting Control Register + LibAmdMsrRead (MSR_MCG_CAP, &MsrData, StdHeader); + if ((MsrData & MCG_CTL_P) != 0) { + TempVar16_a = (UINT16) ((MsrData & 0x000000FF) << 2); + TempVar16_a += MSR_MC0_CTL; + + // Initialize the data + MsrData = 0; + for (MsrAddress = MSR_MC0_CTL; MsrAddress < TempVar16_a; MsrAddress++) { + LibAmdMsrWrite (MsrAddress, &MsrData, StdHeader); + } + } + } + } +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Initialize Machine Check Architecture registers + * + * This function acts as a wrapper for calling the McaInitialization + * routine at AmdInitEarly. + * + * @param[in] FamilyServices The current Family Specific Services. + * @param[in] EarlyParams Service parameters. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +McaInitializationAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + McaInitialization (StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Runs the given task on all cores (including self) on the socket of the executing + * core 0. + * + * This function is used to invoke all APs on the socket of the executing core 0 to + * run a specified AGESA procedure. + * + * @param[in] TaskPtr Function descriptor + * @param[in] StdHeader Config handle for library and services + * @param[in] CpuEarlyParamsPtr Required input parameters for early CPU initialization + * + */ +VOID +ApUtilRunCodeOnAllLocalCoresAtEarly ( + IN AP_TASK *TaskPtr, + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr + ) +{ + UINT32 Core; + UINT32 Socket; + UINT32 IgnoredModule; + UINT32 IgnoredCore; + UINT32 ActiveCores; + AGESA_STATUS IgnoredSts; + + IdentifyCore (StdHeader, &Socket, &IgnoredModule, &IgnoredCore, &IgnoredSts); + GetActiveCoresInCurrentSocket (&ActiveCores, StdHeader); + + for (Core = 1; Core < (UINT8) ActiveCores; ++Core) { + ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, TaskPtr, StdHeader); + } + ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Get current condition, such as warm/cold reset, to determine if related function + * need to be performed at early stage + * + * @param[in, out] PerformEarlyFlag Perform early flag. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +STATIC +GetPerformEarlyFlag ( + IN OUT UINT32 *PerformEarlyFlag, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *PerformEarlyFlag = 0; + if (IsWarmReset (StdHeader)) { + *PerformEarlyFlag |= PERFORM_EARLY_WARM_RESET; + } else { + *PerformEarlyFlag |= PERFORM_EARLY_COLD_BOOT; + } + return; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h new file mode 100644 index 0000000..f101ab1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h @@ -0,0 +1,331 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Reset API, and related functions and structures. + * + * Contains code that initialized the CPU after early reset. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_EARLY_INIT_H_ +#define _CPU_EARLY_INIT_H_ + + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ +AGESA_FORWARD_DECLARATION (CPU_CORE_LEVELING_FAMILY_SERVICES); + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ +//---------------------------------------------------------------------------- +// CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS +// +//---------------------------------------------------------------------------- +#define CPU_BRAND_ID_LENGTH 48 // Total number of characters supported +#define LOW_NODE_DEVICEID 24 +#define NB_CAPABILITIES 0xE8 //Function 3 Registers +//---------------------------------------------------------------------------- +// CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS +// +//---------------------------------------------------------------------------- +/* All lengths are in bytes */ +#define MICROCODE_TRIADE_SIZE 28 +#define MICROCODE_HEADER_LENGTH 64 + +/** + * @page ucodeflag Microcode Patches Signature Guide + * + * We mark patches in the ROM with a signature so that they can be easily found + * + * @anchor Microcode Patch Signature + * @li @e Microcode Patch Signature @n + * Microcode patches are marked by adding a signature before patches in the ROM image to + * help identify where they are located. + * There're two kind of signatures. One is '$UCODE2K', it indicates there's a following patch with 2K size. + * The other is '$UCODE4K', it indicates there's a following patch with 4K size. + * If you want to know the patch level / equivalent ID, please consult the BKDG for patch header format. + * + * + */ +/// Microcode patch flag for replacement +typedef struct { + IN UINT8 MicrocodePatchesFlag[8]; ///< a flag followed by microcode +} MICROCODE_PATCHES_FLAG; + +#define UCODE_2K_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', '2', 'K'}}; +#define UCODE_4K_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', '4', 'K'}}; +#define UCODE_VS_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', 'V', 'S'}}; + +/* Offsets in UCODE PATCH Header */ +/* Note: Header is 64 bytes */ +#define DATE_CODE_OFFSET 0 // 4 bytes +#define PATCH_ID 4 // 4 bytes +#define MICROCODE_PATH_DATA_ID 8 // 2 bytes +#define MICROCODE_PATCH_DATA_LENGTH 10 // 1 byte +#define MICROCODE_PATCH_DATA_CHECKSUM 12 // 4 bytes +#define CHIPSET_1_DEVICE_ID 16 // 4 bytes +#define CHIPSET_2_DEVICE_ID 20 // 4 bytes +#define PROCESSOR_REV_ID 24 // 2 bytes +#define CHIPSET_1_REV_ID 26 // 1 byte +#define CHIPSET_2_REV_ID 27 // 1 byte + +#define MICROCODE_PATCH_2K_SIZE 2048 +#define MICROCODE_PATCH_4K_SIZE 4096 +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ +//---------------------------------------------------------------------------- +// CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS +// +//---------------------------------------------------------------------------- +/// A structure representing BrandId[15:0] from +/// CPUID Fn8000_0001_EBX +typedef struct { + UINT8 String1:4; ///< An index to a string value used to create the name string + UINT8 String2:4; ///< An index to a string value used to create the name string + UINT8 Page:1; ///< An index to the appropriate page for the String1, String2, and Model values + UINT8 Model:7; ///< A field used to create the model number in the name string + UINT8 Socket:4; ///< Specifies the package type + UINT8 Cores:4; ///< Identifies how many physical cores are present +} AMD_CPU_BRAND_DATA; + +/// A structure containing string1 and string2 values +/// as well as information pertaining to their usage +typedef struct { + IN UINT8 Cores; ///< Appropriate number of physical cores + IN UINT8 Page; ///< This string's page number + IN UINT8 Index; ///< String index + IN UINT8 Socket; ///< Package type information + IN CONST CHAR8 *Stringstart; ///< The literal string + IN UINT8 Stringlength; ///< Number of characters in the string +} AMD_CPU_BRAND; + +/// An entire CPU brand table. +typedef struct { + UINT8 NumberOfEntries; ///< The number of entries in the table. + CONST AMD_CPU_BRAND *Table; ///< The table entries. +} CPU_BRAND_TABLE; + +//---------------------------------------------------------------------------- +// CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS +// +//---------------------------------------------------------------------------- +/// Microcode patch field definitions +typedef struct { + UINT32 DateCode; ///< Date of patch creation + UINT32 PatchID; ///< Patch level + UINT16 MicrocodePatchDataID; ///< Internal use only + UINT8 MicrocodePatchDataLength; ///< Internal use only + UINT8 InitializationFlag; ///< Internal use only + UINT32 MicrocodePatchDataChecksum; ///< Doubleword sum of data block + UINT32 Chipset1DeviceID; ///< Device ID of 1st HT device to match + UINT32 Chipset2DeviceID; ///< Device ID of 2nd HT device to match + UINT16 ProcessorRevisionID; ///< Equivalent ID + UINT8 Chipset1RevisionID; ///< Revision level of 1st HT device to match + UINT8 Chipset2RevisionID; ///< Revision level of 2nd HT device to match + UINT8 BiosApiRevision; ///< BIOS INT 15 API revision required + UINT8 Reserved1[3]; ///< Reserved + UINT32 MatchRegister0; ///< Internal use only + UINT32 MatchRegister1; ///< Internal use only + UINT32 MatchRegister2; ///< Internal use only + UINT32 MatchRegister3; ///< Internal use only + UINT32 MatchRegister4; ///< Internal use only + UINT32 MatchRegister5; ///< Internal use only + UINT32 MatchRegister6; ///< Internal use only + UINT32 MatchRegister7; ///< Internal use only + UINT8 PatchDataBlock[896]; ///< Raw patch data + UINT8 Reserved2[896]; ///< Reserved + UINT8 X86CodePresent; ///< Boolean to determine if executable code exists + UINT8 X86CodeEntry[191]; ///< Code to execute if X86CodePresent != 0 +} MICROCODE_PATCH; + +/// Two kilobyte array containing the raw +/// microcode patch binary data +typedef struct { + IN UINT8 MicrocodePatches[MICROCODE_PATCH_2K_SIZE]; ///< 2k UINT8 elements +} MICROCODE_PATCHES; + +/// Four kilobyte array containing the raw +/// microcode patch binary data +typedef struct { + IN UINT8 MicrocodePatches[MICROCODE_PATCH_4K_SIZE]; ///< 4k UINT8 elements +} MICROCODE_PATCHES_4K; + +/** + * Set down core register + * + * @CpuServiceInstances + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] Socket Socket ID. + * @param[in] Module Module ID in socket. + * @param[in] LeveledCores Number of core. + * @param[in] CoreLevelMode Core level mode. + * @param[in] StdHeader Header for library and services. + * + * @retval TRUE Down Core register is updated. + * @retval FALSE Down Core register is not updated. + */ +typedef BOOLEAN (F_CPU_SET_DOWN_CORE_REGISTER) ( + IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices, + IN UINT32 *Socket, + IN UINT32 *Module, + IN UINT32 *LeveledCores, + IN CORE_LEVELING_TYPE CoreLevelMode, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a method +typedef F_CPU_SET_DOWN_CORE_REGISTER *PF_CPU_SET_DOWN_CORE_REGISTER; + +/** + * Provide the interface to the Core Leveling Family Specific Services. + * + * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). + * Each supported Family must provide an implementation for all methods in this interface, even if the + * implementation is a CommonReturn(). + */ +struct _CPU_CORE_LEVELING_FAMILY_SERVICES { // See Forward Declaration above + UINT16 Revision; ///< Interface version + // Public Methods. + PF_CPU_SET_DOWN_CORE_REGISTER SetDownCoreRegister; ///< Method: Set down core register. +}; + +//---------------------------------------------------------------------------- +// CPU PERFORM EARLY INIT ON CORE +// +//---------------------------------------------------------------------------- +/// Flag definition. +#define PERFORM_EARLY_WARM_RESET 0x1 // bit 0 --- the related function needs to be run if it's warm reset +#define PERFORM_EARLY_COLD_BOOT 0x2 // bit 1 --- the related function needs to be run if it's cold boot + +#define PERFORM_EARLY_ANY_CONDITION 0xFFFFFFFFul // the related function always needs to be run +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ + +// These are P U B L I C functions, used by IBVs +AGESA_STATUS +AmdCpuEarly ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig + ); + +// These are P U B L I C functions, used by AGESA +VOID +SetBrandIdRegisters ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PmInitializationAtEarly ( + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +LoadMicrocodePatch ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GetPatchEquivalentId ( + IN OUT UINT16 *ProcessorEquivalentId, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +ValidateMicrocode ( + IN MICROCODE_PATCH *MicrocodePatchPtr, + IN UINT16 ProcessorEquivalentId, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GetMicrocodeVersion ( + OUT UINT32 *pMicrocodeVersion, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +AmdCpuEarlyInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr + ); + +VOID +McaInitialization ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif // _CPU_EARLY_INIT_H_ + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEnvInit.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEnvInit.h new file mode 100644 index 0000000..0cd1d9d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEnvInit.h @@ -0,0 +1,100 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Env Init API functions Prototypes. + * + * Contains code for doing any Env CPU initialization + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_ENV_INIT_H_ +#define _CPU_ENV_INIT_H_ + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ +// HobTransfer +AGESA_STATUS +CopyHeapToMainRamAtPost ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +#endif // _CPU_ENV_INIT_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEventLog.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEventLog.c new file mode 100644 index 0000000..be8f8b7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEventLog.c @@ -0,0 +1,423 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Event (Error) Log APIs, and related functions. + * + * Contains code that records and returns the events and errors. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "heapManager.h" +#include "GeneralServices.h" +#include "Ids.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_CPUEVENTLOG_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define TOTAL_EVENT_LOG_BUFFERS 16 + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/** + * A wrapper for each Event Log entry. + */ +typedef struct { + UINT16 Count; ///< Entry number + AGESA_EVENT AgesaEvent; ///< The entry itself. +} AGESA_EVENT_STRUCT; + +/** + * The Event Log. + */ +typedef struct { + UINT16 ReadWriteFlag; ///< Read Write flag. + UINT16 Count; ///< The total number of active entries. + UINT16 ReadRecordPtr; ///< The next entry to read. + UINT16 WriteRecordPtr; ///< The next entry to write. + AGESA_EVENT_STRUCT AgesaEventStruct[TOTAL_EVENT_LOG_BUFFERS]; ///< The entries. +} AGESA_STRUCT_BUFFER; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +GetEventLogHeapPointer ( + OUT AGESA_STRUCT_BUFFER **EventLog, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------*/ +/** + * External AGESA interface to read an Event from the Event Log. + * + * This is the implementation of the external AGESA interface entry, as a thin wrapper + * around the internal log services. + * + * @param[in] Event The event class, id, and any associated data. + * + * @retval AGESA_SUCCESS Always Succeeds. + */ +AGESA_STATUS +AmdReadEventLog ( + IN EVENT_PARAMS *Event + ) +{ + AGESA_EVENT LogEvent; + AGESA_STATUS Status; + + AGESA_TESTPOINT (TpIfAmdReadEventLogEntry, &Event->StdHeader); + + ASSERT (Event != NULL); + Event->StdHeader.HeapBasePtr = HeapGetBaseAddress (&Event->StdHeader); + Status = GetEventLog (&LogEvent, &Event->StdHeader); + + Event->EventClass = LogEvent.EventClass; + Event->EventInfo = LogEvent.EventInfo; + Event->DataParam1 = LogEvent.DataParam1; + Event->DataParam2 = LogEvent.DataParam2; + Event->DataParam3 = LogEvent.DataParam3; + Event->DataParam4 = LogEvent.DataParam4; + + AGESA_TESTPOINT (TpIfAmdReadEventLogExit, &Event->StdHeader); + return Status; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * + * This function prepares the Event Log for use. + * + * Allocate the memory for an event log on the heap. Set the read pointer, write pointer, + * and count to reflect the log is empty. + * + * @param[in] StdHeader Our configuration, for passing to services. + * + * @retval AGESA_SUCCESS The event log is initialized. + * @retval AGESA_ERROR Allocate Heap Buffer returned an error. + * + */ +AGESA_STATUS +EventLogInitialization ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + ALLOCATE_HEAP_PARAMS AllocateHeapParams; + AGESA_STRUCT_BUFFER *AgesaEventAlloc; + AGESA_STATUS Status; + + AllocateHeapParams.BufferHandle = EVENT_LOG_BUFFER_HANDLE; + AllocateHeapParams.RequestedBufferSize = sizeof (AGESA_STRUCT_BUFFER); + AllocateHeapParams.Persist = HEAP_SYSTEM_MEM; + Status = HeapAllocateBuffer (&AllocateHeapParams, StdHeader); + AgesaEventAlloc = (AGESA_STRUCT_BUFFER *) AllocateHeapParams.BufferPtr; + AgesaEventAlloc->Count = 0; + AgesaEventAlloc->ReadRecordPtr = 0; + AgesaEventAlloc->WriteRecordPtr = 0; + AgesaEventAlloc->ReadWriteFlag = 1; + + return Status; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * + * This function logs AGESA events into the event log. + * + * It will put the information in a circular buffer consisting of 16 such log + * entries. If the buffer gets full, then the next event log entry will be written + * over the oldest event log entry. + * + * @param[in] EventClass The severity of the event, its associated AGESA_STATUS. + * @param[in] EventInfo Uniquely identifies the event. + * @param[in] DataParam1 Event specific additional data + * @param[in] DataParam2 Event specific additional data + * @param[in] DataParam3 Event specific additional data + * @param[in] DataParam4 Event specific additional data + * @param[in] StdHeader Header for library and services + * + */ +VOID +PutEventLog ( + IN AGESA_STATUS EventClass, + IN UINT32 EventInfo, + IN UINT32 DataParam1, + IN UINT32 DataParam2, + IN UINT32 DataParam3, + IN UINT32 DataParam4, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT16 Index; + AGESA_STRUCT_BUFFER *AgesaEventAlloc; + + IDS_HDT_CONSOLE (MAIN_FLOW, "\n * %s Event: %08x Data: %x, %x, %x, %x\n\n", + (EventClass == AGESA_FATAL) ? "FATAL" : + (EventClass == AGESA_CRITICAL) ? "CRITICAL" : + (EventClass == AGESA_ERROR) ? "ERROR" : + (EventClass == AGESA_WARNING) ? "WARNING" : + (EventClass == AGESA_ALERT) ? "ALERT" : + (EventClass == AGESA_BOUNDS_CHK) ? "BOUNDS_CHK" : + (EventClass == AGESA_UNSUPPORTED) ? "UNSUPPORTED" : + "SUCCESS", EventInfo, DataParam1, DataParam2, DataParam3, DataParam4); + + AgesaEventAlloc = NULL; + GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); + ASSERT (AgesaEventAlloc != NULL); + Index = AgesaEventAlloc->WriteRecordPtr; + + // Add the new event log data into a circular buffer + AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.EventClass = EventClass; + AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.EventInfo = EventInfo; + AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam1 = DataParam1; + AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam2 = DataParam2; + AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam3 = DataParam3; + AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam4 = DataParam4; + + if ((AgesaEventAlloc->WriteRecordPtr == AgesaEventAlloc->ReadRecordPtr) && + (AgesaEventAlloc->ReadWriteFlag == 0)) { + AgesaEventAlloc->WriteRecordPtr += 1; + AgesaEventAlloc->ReadRecordPtr += 1; + if (AgesaEventAlloc->WriteRecordPtr == TOTAL_EVENT_LOG_BUFFERS) { + AgesaEventAlloc->WriteRecordPtr = 0; + AgesaEventAlloc->ReadRecordPtr = 0; + } + } else { + AgesaEventAlloc->WriteRecordPtr += 1; + if (AgesaEventAlloc->WriteRecordPtr == TOTAL_EVENT_LOG_BUFFERS) { + AgesaEventAlloc->WriteRecordPtr = 0; + } + AgesaEventAlloc->ReadWriteFlag = 0; + } + AgesaEventAlloc->Count = AgesaEventAlloc->Count + 1; + + if (AgesaEventAlloc->Count <= TOTAL_EVENT_LOG_BUFFERS) { + AgesaEventAlloc->AgesaEventStruct[Index].Count = Index; + } +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * + * This function gets event logs from the circular buffer. + * + * It will read the oldest entry from the circular buffer and place that information to the structure + * pointed to by the parameter. The read pointers will be incremented to remove the entry from buffer + * so that a subsequent call will return the next entry from the buffer. If the buffer is empty the + * returned log event will have EventInfo zero, which is not a valid event id. + * + * @param[out] EventRecord The next log event. + * @param[in] StdHeader Header for library and services + * + * @retval AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +GetEventLog ( + OUT AGESA_EVENT *EventRecord, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT16 Index; + AGESA_STRUCT_BUFFER *AgesaEventAlloc; + + AgesaEventAlloc = NULL; + + GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); + ASSERT (AgesaEventAlloc != NULL); + + if ((AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) && + (AgesaEventAlloc->ReadWriteFlag == 1)) { + // EventInfo == zero, means no more data. + LibAmdMemFill (EventRecord, 0, sizeof (AGESA_EVENT), StdHeader); + } else { + Index = AgesaEventAlloc->ReadRecordPtr; + EventRecord->EventClass = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.EventClass; + EventRecord->EventInfo = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.EventInfo; + EventRecord->DataParam1 = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam1; + EventRecord->DataParam2 = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam2; + EventRecord->DataParam3 = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam3; + EventRecord->DataParam4 = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam4; + if (AgesaEventAlloc->ReadRecordPtr == (TOTAL_EVENT_LOG_BUFFERS - 1)) { + AgesaEventAlloc->ReadRecordPtr = 0; + } else { + AgesaEventAlloc->ReadRecordPtr = AgesaEventAlloc->ReadRecordPtr + 1; + } + if (AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) { + AgesaEventAlloc->ReadWriteFlag = 1; + } + } + return (AGESA_SUCCESS); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * + * This function gets event logs from the circular buffer without flushing the entry. + * + * It will read the desired entry from the circular buffer and place that information to the structure + * pointed to by the parameter. The read pointers will not be incremented to remove the entry from the + * buffer. If the buffer is empty, or the desired entry does not exist, FALSE will be returned. + * + * @param[out] EventRecord The next log event. + * @param[in] Index Zero-based unread entry index + * @param[in] StdHeader Header for library and services + * + * @retval TRUE Entry exists + * @retval FALSE Entry does not exist + * + */ +BOOLEAN +PeekEventLog ( + OUT AGESA_EVENT *EventRecord, + IN UINT16 Index, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT16 ActualIndex; + UINT16 UnreadEntries; + AGESA_STRUCT_BUFFER *AgesaEventAlloc; + + AgesaEventAlloc = NULL; + + GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); + ASSERT (AgesaEventAlloc != NULL); + + if ((AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) && + (AgesaEventAlloc->ReadWriteFlag == 1)) { + // EventInfo == zero, means no more data. + return FALSE; + } + if (AgesaEventAlloc->ReadRecordPtr < AgesaEventAlloc->WriteRecordPtr) { + UnreadEntries = AgesaEventAlloc->WriteRecordPtr - AgesaEventAlloc->ReadRecordPtr; + } else { + UnreadEntries = TOTAL_EVENT_LOG_BUFFERS - (AgesaEventAlloc->ReadRecordPtr - AgesaEventAlloc->WriteRecordPtr); + } + if (Index >= UnreadEntries) { + return FALSE; + } + ActualIndex = Index + AgesaEventAlloc->ReadRecordPtr; + if (ActualIndex >= TOTAL_EVENT_LOG_BUFFERS) { + ActualIndex -= TOTAL_EVENT_LOG_BUFFERS; + } + + EventRecord->EventClass = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.EventClass; + EventRecord->EventInfo = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.EventInfo; + EventRecord->DataParam1 = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.DataParam1; + EventRecord->DataParam2 = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.DataParam2; + EventRecord->DataParam3 = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.DataParam3; + EventRecord->DataParam4 = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.DataParam4; + + return TRUE; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * + * This function gets the Event Log pointer. + * + * It will locate the Event Log on the heap using the heap locate service. If the Event + * Log is not located, NULL is returned. + * + * @param[out] EventLog Pointer to the Event Log, or NULL. + * @param[in] StdHeader Our Configuration, for passing to services. + * + */ +VOID +STATIC +GetEventLogHeapPointer ( + OUT AGESA_STRUCT_BUFFER **EventLog, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + LOCATE_HEAP_PTR LocateHeapStruct; + + LocateHeapStruct.BufferHandle = EVENT_LOG_BUFFER_HANDLE; + LocateHeapStruct.BufferPtr = NULL; + if ((HeapLocateBuffer (&LocateHeapStruct, StdHeader)) == AGESA_SUCCESS) { + *EventLog = (AGESA_STRUCT_BUFFER *)LocateHeapStruct.BufferPtr; + } else { + *EventLog = NULL; + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.c new file mode 100644 index 0000000..c3659cb --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.c @@ -0,0 +1,510 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Family Translation functions. + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Interface + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "CommonReturns.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_CPUFAMILYTRANSLATION_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +CONST CPU_SPECIFIC_SERVICES ROMDATA cpuNullServices = +{ + 0, + (PF_CPU_DISABLE_PSTATE) CommonReturnAgesaSuccess, + (PF_CPU_TRANSITION_PSTATE) CommonReturnAgesaSuccess, + (PF_CPU_GET_IDD_MAX) CommonReturnFalse, + (PF_CPU_GET_TSC_RATE) CommonReturnAgesaSuccess, + (PF_CPU_GET_NB_FREQ) CommonReturnAgesaSuccess, + (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonReturnAgesaSuccess, + (PF_CPU_GET_NB_PSTATE_INFO) CommonReturnFalse, + (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnAgesaSuccess, + (PF_CPU_GET_NB_IDD_MAX) CommonReturnFalse, + (PF_CPU_AP_INITIAL_LAUNCH) CommonReturnFalse, + (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonReturnZero8, + (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonReturnAgesaSuccess, + (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid, + (PF_CPU_GET_AP_CORE_NUMBER) CommonReturnZero32, + (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid, + (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonReturnAgesaSuccess, + (PF_CPU_SAVE_FEATURES) CommonReturnAgesaSuccess, + (PF_CPU_WRITE_FEATURES) CommonReturnAgesaSuccess, + (PF_CPU_SET_WARM_RESET_FLAG) CommonReturnAgesaSuccess, + (PF_CPU_GET_WARM_RESET_FLAG) CommonReturnAgesaSuccess, + GetEmptyArray, + GetEmptyArray, + GetEmptyArray, + GetEmptyArray, + GetEmptyArray, + GetEmptyArray, + GetEmptyArray, + (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess, + (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse, + (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse, + (PF_SET_HT_PHY_REGISTER) CommonVoid, + (PF_GET_NEXT_HT_LINK_FEATURES) CommonVoid, + NULL, + NULL, + NULL, + NULL, + InitCacheDisabled, + (PF_GET_EARLY_INIT_TABLE) CommonVoid +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +GetCpuServices ( + IN CPU_FAMILY_SUPPORT_TABLE *FamilyTable, + IN UINT64 *MatchData, + OUT CONST VOID **CpuServices, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern CPU_FAMILY_SUPPORT_TABLE CpuSupportedFamiliesTable; +extern CPU_FAMILY_ID_XLAT_TABLE CpuSupportedFamilyIdTable; + +/*---------------------------------------------------------------------------------------*/ +/** + * + * Returns the logical ID of the desired processor. This will be obtained by + * reading the CPUID and converting it into a "logical ID" which is not package + * dependent. + * + * @param[in] Socket Socket + * @param[out] LogicalId The Processor's Logical ID + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +VOID +GetLogicalIdOfSocket ( + IN UINT32 Socket, + OUT CPU_LOGICAL_ID *LogicalId, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 RawCpuid; + PCI_ADDR PciAddress; + AGESA_STATUS AssumedSuccess; + + RawCpuid = 0; + + if (GetPciAddress (StdHeader, (UINT8)Socket, 0, &PciAddress, &AssumedSuccess)) { + PciAddress.Address.Function = FUNC_3; + PciAddress.Address.Register = CPUID_FMR; + LibAmdPciRead (AccessWidth32, PciAddress, &RawCpuid, StdHeader); + GetLogicalIdFromCpuid (RawCpuid, LogicalId, StdHeader); + } else { + LogicalId->Family = 0; + LogicalId->Revision = 0; + // Logical ID was not found. + IDS_ERROR_TRAP; + } +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * + * Returns the logical ID of the executing core. This will be obtained by reading + * the CPUID and converting it into a "logical ID" which is not package dependent. + * + * @param[out] LogicalId The Processor's Logical ID + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +VOID +GetLogicalIdOfCurrentCore ( + OUT CPU_LOGICAL_ID *LogicalId, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + CPUID_DATA CpuidDataStruct; + + LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuidDataStruct, StdHeader); + GetLogicalIdFromCpuid (CpuidDataStruct.EAX_Reg, LogicalId, StdHeader); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * + * Returns the logical ID of a processor with the given CPUID value. This + * will be obtained by converting it into a "logical ID" which is not package + * dependent. + * + * @param[in] RawCpuid The unprocessed CPUID value to be translated + * @param[out] LogicalId The Processor's Logical ID + * @param[in] StdHeader Handle of Header for calling lib functions and services + * + */ +VOID +GetLogicalIdFromCpuid ( + IN UINT32 RawCpuid, + OUT CPU_LOGICAL_ID *LogicalId, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + UINT8 k; + UINT8 NumberOfFamiliesSupported; + UINT8 NumberOfLogicalSubFamilies; + UINT8 LogicalIdEntries; + UINT32 j; + UINT32 RawFamily; + UINT32 CpuModelAndExtendedModel; + UINT64 LogicalFamily; + BOOLEAN IdNotFound; + BOOLEAN FamilyNotFound; + CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY *SubFamilyIdPtr; + CPU_LOGICAL_ID_XLAT *CpuLogicalIdAndRevPtr; + CONST CPU_LOGICAL_ID_FAMILY_XLAT *ImageSupportedId; + + IdNotFound = TRUE; + FamilyNotFound = TRUE; + CpuLogicalIdAndRevPtr = NULL; + ImageSupportedId = CpuSupportedFamilyIdTable.FamilyIdTable; + NumberOfFamiliesSupported = CpuSupportedFamilyIdTable.Elements; + + RawFamily = ((RawCpuid & 0xF00) >> 8) + ((RawCpuid & 0xFF00000) >> 20); + RawCpuid &= (UINT32) CPU_FMS_MASK; + CpuModelAndExtendedModel = (UINT16) ((RawCpuid >> 8) | RawCpuid); + + LogicalId->Family = 0; + LogicalId->Revision = 0; + + for (i = 0; i < NumberOfFamiliesSupported && FamilyNotFound; i++) { + if (ImageSupportedId[i].Family == RawFamily) { + FamilyNotFound = FALSE; + LogicalId->Family = ImageSupportedId[i].UnknownRevision.Family; + LogicalId->Revision = ImageSupportedId[i].UnknownRevision.Revision; + + NumberOfLogicalSubFamilies = ImageSupportedId[i].Elements; + SubFamilyIdPtr = ImageSupportedId[i].SubFamilyIdTable; + for (j = 0; j < NumberOfLogicalSubFamilies && IdNotFound; j++) { + SubFamilyIdPtr[j] ((CONST CPU_LOGICAL_ID_XLAT **)&CpuLogicalIdAndRevPtr, &LogicalIdEntries, &LogicalFamily, StdHeader); + ASSERT (CpuLogicalIdAndRevPtr != NULL); + for (k = 0; k < LogicalIdEntries; k++) { + if (CpuLogicalIdAndRevPtr[k].RawId == CpuModelAndExtendedModel) { + IdNotFound = FALSE; + LogicalId->Family = LogicalFamily; + LogicalId->Revision = CpuLogicalIdAndRevPtr[k].LogicalId; + break; + } + } + } + } + } +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * + * Retrieves a pointer to the desired processor's family specific services structure. + * + * @param[in] Socket The Processor in this Socket. + * @param[out] FunctionTable The Processor's Family Specific services. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +VOID +GetCpuServicesOfSocket ( + IN UINT32 Socket, + OUT CONST CPU_SPECIFIC_SERVICES **FunctionTable, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GetFeatureServicesOfSocket (&CpuSupportedFamiliesTable, + Socket, + (CONST VOID **) FunctionTable, + StdHeader); + if (*FunctionTable == NULL) { + *FunctionTable = &cpuNullServices; + } +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * + * Retrieves a pointer to the desired processor's family specific services structure. + * + * @param[in] FamilyTable The table to search in. + * @param[in] Socket The Processor in this Socket. + * @param[out] CpuServices The Processor's Family Specific services. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +VOID +GetFeatureServicesOfSocket ( + IN CPU_FAMILY_SUPPORT_TABLE *FamilyTable, + IN UINT32 Socket, + OUT CONST VOID **CpuServices, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + CPU_LOGICAL_ID CpuFamilyRevision; + + GetLogicalIdOfSocket (Socket, &CpuFamilyRevision, StdHeader); + GetFeatureServicesFromLogicalId (FamilyTable, &CpuFamilyRevision, CpuServices, StdHeader); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * + * Retrieves a pointer to the executing core's family specific services structure. + * + * @param[out] FunctionTable The Processor's Family Specific services. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +VOID +GetCpuServicesOfCurrentCore ( + OUT CONST CPU_SPECIFIC_SERVICES **FunctionTable, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GetFeatureServicesOfCurrentCore (&CpuSupportedFamiliesTable, + (CONST VOID **) FunctionTable, + StdHeader); + if (*FunctionTable == NULL) { + *FunctionTable = &cpuNullServices; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * + * Retrieves a pointer to the family specific services structure for a processor + * with the given logical ID. + * + * @param[in] FamilyTable The table to search in. + * @param[out] CpuServices The Processor's Family Specific services. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +VOID +GetFeatureServicesOfCurrentCore ( + IN CPU_FAMILY_SUPPORT_TABLE *FamilyTable, + OUT CONST VOID **CpuServices, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + CPU_LOGICAL_ID CpuFamilyRevision; + + GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); + GetFeatureServicesFromLogicalId (FamilyTable, &CpuFamilyRevision, CpuServices, StdHeader); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * + * Retrieves a pointer to the family specific services structure for a processor + * with the given logical ID. + * + * @param[in] LogicalId The Processor's logical ID. + * @param[out] FunctionTable The Processor's Family Specific services. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +VOID +GetCpuServicesFromLogicalId ( + IN CPU_LOGICAL_ID *LogicalId, + OUT CONST CPU_SPECIFIC_SERVICES **FunctionTable, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GetFeatureServicesFromLogicalId (&CpuSupportedFamiliesTable, + LogicalId, + (CONST VOID **) FunctionTable, + StdHeader); + if (*FunctionTable == NULL) { + *FunctionTable = &cpuNullServices; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * + * Retrieves a pointer to the family specific services structure for a processor + * with the given logical ID. + * + * @param[in] FamilyTable The table to search in. + * @param[in] LogicalId The Processor's logical ID. + * @param[out] CpuServices The Processor's Family Specific services. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +VOID +GetFeatureServicesFromLogicalId ( + IN CPU_FAMILY_SUPPORT_TABLE *FamilyTable, + IN CPU_LOGICAL_ID *LogicalId, + OUT CONST VOID **CpuServices, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GetCpuServices (FamilyTable, &LogicalId->Family, CpuServices, StdHeader); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * + * Finds a family match in the given table, and returns the pointer to the + * appropriate table. If no match is found in the table, NULL will be returned. + * + * @param[in] FamilyTable The table to search in. + * @param[in] MatchData Family data that must match. + * @param[out] CpuServices The Processor's Family Specific services. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +VOID +STATIC +GetCpuServices ( + IN CPU_FAMILY_SUPPORT_TABLE *FamilyTable, + IN UINT64 *MatchData, + OUT CONST VOID **CpuServices, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + BOOLEAN IsFamily; + UINT8 i; + UINT8 NumberOfFamiliesSupported; + CONST CPU_SPECIFIC_SERVICES_XLAT *ImageSupportedFamiliesPtr; + + ImageSupportedFamiliesPtr = FamilyTable->FamilyTable; + NumberOfFamiliesSupported = FamilyTable->Elements; + IsFamily = FALSE; + for (i = 0; i < NumberOfFamiliesSupported; i++) { + if ((ImageSupportedFamiliesPtr[i].Family & *MatchData) != 0) { + IsFamily = TRUE; + break; + } + } + if (IsFamily) { + *CpuServices = ImageSupportedFamiliesPtr[i].TablePtr; + } else { + *CpuServices = NULL; + } +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Used to stub out various family specific tables of information. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] Empty NULL, to indicate no data. + * @param[out] NumberOfElements Zero, to indicate no data. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +VOID +GetEmptyArray ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **Empty, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *NumberOfElements = 0; + *Empty = NULL; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h new file mode 100644 index 0000000..9abcfe4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h @@ -0,0 +1,1034 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Family Translation functions. + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_FAMILY_TRANSLATION_H_ +#define _CPU_FAMILY_TRANSLATION_H_ + +/** + * @page cpuimplfss CPU Family Specific Services Implementation Guide + * + * CPU Family Specific Services provides access to supported family service functions and data, + * in a manner that isolates calling code from knowledge about particular families or which + * families are supported in the current build. + * + * @par Adding a Method to Family Specific Services + * + * To add a new method to Family Specific Services, follow these steps. + * <ul> + * <li> Create a typedef for the Method with the correct parameters and return type. + * + * <ul> + * <li> Name the method typedef (*PF_METHOD_NAME)(), where METHOD_NAME is the same name as the method table item, + * but with "_"'s and UPPERCASE, rather than mixed case. + * @n <tt> typedef VOID (*PF_METHOD_NAME)(); </tt> @n + * + * <li> [Optionally make the type F_<name> and provide a separate: + * @n <tt> typedef F_METHOD_NAME *PF_METHOD_NAME> </tt> @n + * and provide a single line "///" doxygen comment brief description on the PF_ type.] + * </ul> + * + * <li> The first parameter to @b all Family Specific Service Methods is @b required to be a reference to + * their Family Service struct. + * @n <tt> IN CPU_SPECIFIC_SERVICES *FamilySpecificServices </tt> @n + * + * <li> Provide a standard doxygen function preamble for the Method typedef. Begin the + * detailed description by provide a reference to the method instances page by including + * the lines below: + * @code + * * + * * @CpuServiceInstances + * * + * @endcode + * @note It is important to provide documentation for the method type, because the method may not + * have an implementation in any families supported by the current package. @n + * + * <li> Add to the CPU_SPECIFIC_SERVICES struct an item for the Method: + * @n <tt> PF_METHOD_NAME MethodName; ///< Method: description. </tt> @n + * </ul> + * + * @par Implementing a Family Specific Instance of the method. + * + * To implement an instance of a method for a specific family follow these steps. + * + * - In appropriate files in the family specific directory, implement the method with the return type + * and parameters matching the method typedef. + * + * - Name the function FnnMethodName(), where nn is the family number. + * + * - Create a doxygen function preamble for the method instance. Begin the detailed description with + * an Implements command to reference the method type and add this instance to the Method Instances page. + * @code + * * + * * @CpuServiceMethod{::F_METHOD_NAME}. + * * + * @endcode + * + * - To access other family specific services as part of the method implementation, the function + * @b must use FamilySpecificServices->OtherMethod(). Do not directly call other family specific + * routines, because in the table there may be overrides or this routine may be shared by multiple families. + * + * - Do @b not call Family translation services from a family specific instance. Use the parameter. + * + * - Add the instance to the family specific CPU_SPECIFIC_SERVICES instance. + * + * - If a family does not need an instance of the method use one of the CommonReturns from + * CommonReturns.h with the same return type. + * + * @par Invoking Family Specific Services. + * + * The following example shows how to invoke a family specific method. + * @n @code + * CPU_SPECIFIC_SERVICES *FamilyServices; + * + * GetCpuServicesOfCurrentCore (&FamilyServices, StdHeader); + * ASSERT (FamilyServices != NULL); + * FamilyServices->MethodName (FamilyServices, StdHeader); + * @endcode + * + */ + + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ +#include "cpuPostInit.h" +#include "cpuEnvInit.h" +#include "cpuRegisters.h" +#include "cpuServices.h" +#include "Table.h" +#include "Ids.h" +#include "Topology.h" + +// Forward declaration needed for multi-structure mutual references. +AGESA_FORWARD_DECLARATION (CPU_SPECIFIC_SERVICES); +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ + +/** + * Disable the desired P-state. + * + * @CpuServiceInstances + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] StateNumber Hardware P-state number. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +typedef AGESA_STATUS F_CPU_DISABLE_PSTATE ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN UINT8 StateNumber, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_CPU_DISABLE_PSTATE *PF_CPU_DISABLE_PSTATE; + +/** + * Transition the current core to the desired P-state. + * + * @CpuServiceInstances + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] StateNumber Software P-state number. + * @param[in] WaitForChange Wait/don't wait for P-state change to complete. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +typedef AGESA_STATUS F_CPU_TRANSITION_PSTATE ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN UINT8 StateNumber, + IN BOOLEAN WaitForChange, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_CPU_TRANSITION_PSTATE *PF_CPU_TRANSITION_PSTATE; + +/** + * Get the desired P-state's maximum current required in milliamps. + * + * @CpuServiceInstances + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] StateNumber The desired hardware P-state number. + * @param[out] ProcIddMax The P-state's maximum current. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval TRUE The P-state is enabled, and ProcIddMax is valid. + * @retval FALSE The P-state is disabled. + * + */ +typedef BOOLEAN F_CPU_GET_IDD_MAX ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN UINT8 StateNumber, + OUT UINT32 *ProcIddMax, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_CPU_GET_IDD_MAX *PF_CPU_GET_IDD_MAX; + + +/** + * Returns the rate at which the current core's timestamp counter increments in megahertz. + * + * @CpuServiceInstances + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[out] FreqInMHz The rate at which the TSC increments in megahertz. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +typedef AGESA_STATUS F_CPU_GET_TSC_RATE ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT UINT32 *FreqInMHz, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_CPU_GET_TSC_RATE *PF_CPU_GET_TSC_RATE; + +/** + * Returns the processor north bridge's clock rate in megahertz. + * + * @CpuServiceInstances + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[out] FreqInMHz The desired node's frequency in megahertz. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval AGESA_SUCCESS FreqInMHz is valid. + */ +typedef AGESA_STATUS F_CPU_GET_NB_FREQ ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT UINT32 *FreqInMHz, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_CPU_GET_NB_FREQ *PF_CPU_GET_NB_FREQ; + +/** + * Returns the node's minimum and maximum northbridge frequency. + * + * @CpuServiceInstances + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] PlatformConfig Platform profile/build option config structure. + * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question. + * @param[out] MinFreqInMHz The minimum north bridge frequency. + * @param[out] MaxFreqInMHz The maximum north bridge frequency. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval AGESA_STATUS Northbridge frequency is valid + */ +typedef AGESA_STATUS F_CPU_GET_MIN_MAX_NB_FREQ ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PCI_ADDR *PciAddress, + OUT UINT32 *MinFreqInMHz, + OUT UINT32 *MaxFreqInMHz, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_CPU_GET_MIN_MAX_NB_FREQ *PF_CPU_GET_MIN_MAX_NB_FREQ; + +/** + * Returns the processor north bridge's P-state settings. + * + * @CpuServiceInstances + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] PlatformConfig Platform profile/build option config structure. + * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question. + * @param[in] NbPstate The NB P-state number to check. + * @param[out] FreqNumeratorInMHz The desired node's frequency numerator in megahertz. + * @param[out] FreqDivisor The desired node's frequency divisor. + * @param[out] VoltageInuV The desired node's voltage in microvolts. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval TRUE NbPstate is valid + * @retval FALSE NbPstate is disabled or invalid + */ +typedef BOOLEAN F_CPU_GET_NB_PSTATE_INFO ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PCI_ADDR *PciAddress, + IN UINT32 NbPstate, + OUT UINT32 *FreqNumeratorInMHz, + OUT UINT32 *FreqDivisor, + OUT UINT32 *VoltageInuV, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_CPU_GET_NB_PSTATE_INFO *PF_CPU_GET_NB_PSTATE_INFO; + +/** + * Returns whether or not the NB frequency initialization sequence is required + * to be performed by the BIOS. + * + * @CpuServiceInstances + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] PciAddress The northbridge to query by pci base address. + * @param[out] NbVidUpdateAll Do all NbVids need to be updated as well. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +typedef BOOLEAN F_CPU_IS_NBCOF_INIT_NEEDED ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PCI_ADDR *PciAddress, + OUT BOOLEAN *NbVidUpdateAll, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_CPU_IS_NBCOF_INIT_NEEDED *PF_CPU_IS_NBCOF_INIT_NEEDED; + +/** + * Get the desired NB P-state's maximum current required in milliamps. + * + * @CpuServiceInstances + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] StateNumber The desired hardware P-state number. + * @param[out] NbIddMax The NB P-state's maximum current. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval TRUE The NB P-state is enabled, and NbIddMax is valid. + * @retval FALSE The NB P-state is disabled. + * + */ +typedef BOOLEAN F_CPU_GET_NB_IDD_MAX ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN UINT8 StateNumber, + OUT UINT32 *NbIddMax, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_CPU_GET_NB_IDD_MAX *PF_CPU_GET_NB_IDD_MAX; + +/** + * Launches the desired core from the reset vector. + * + * @CpuServiceInstances + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] SocketNumber The desired core's socket number. + * @param[in] ModuleNumber The desired core's die number. + * @param[in] CoreNumber The desired core's die relative core number. + * @param[in] PrimaryCoreNumber SocketNumber / ModuleNumber's primary core number. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval TRUE The core was launched successfully. + * @retval FALSE The core was previously launched, or has a problem. + */ +typedef BOOLEAN F_CPU_AP_INITIAL_LAUNCH ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN UINT32 SocketNumber, + IN UINT32 ModuleNumber, + IN UINT32 CoreNumber, + IN UINT32 PrimaryCoreNumber, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_CPU_AP_INITIAL_LAUNCH *PF_CPU_AP_INITIAL_LAUNCH; + +/** + * Returns the appropriate number of physical processor cores + * + * @CpuServiceInstances + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @return One-based number of physical cores on current processor + */ +typedef UINT8 F_CPU_NUMBER_OF_PHYSICAL_CORES ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_CPU_NUMBER_OF_PHYSICAL_CORES *PF_CPU_NUMBER_OF_PHYSICAL_CORES; + +/** + * Returns a family specific table of information pointer and size. + * + * @CpuServiceInstances + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[out] FamilySpecificArray Pointer to the appropriate list for the core. + * @param[out] NumberOfElements Number of valid entries FamilySpecificArray. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +typedef VOID F_CPU_GET_FAMILY_SPECIFIC_ARRAY ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **FamilySpecificArray, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_CPU_GET_FAMILY_SPECIFIC_ARRAY *PF_CPU_GET_FAMILY_SPECIFIC_ARRAY; + +/** + * Returns a model specific list of logical IDs. + * + * @param[out] LogicalIdXlat Installed logical ID table. + * @param[out] NumberOfElements Number of entries in the Logical ID translate table. + * @param[out] LogicalFamily Base logical family bit mask. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +typedef VOID F_CPU_GET_SUBFAMILY_ID_ARRAY ( + OUT CONST CPU_LOGICAL_ID_XLAT **LogicalIdXlat, + OUT UINT8 *NumberOfElements, + OUT UINT64 *LogicalFamily, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a method. +typedef F_CPU_GET_SUBFAMILY_ID_ARRAY *PF_CPU_GET_SUBFAMILY_ID_ARRAY; + +/** + * Use the Mailbox Register to get the Ap Mailbox info for the current core. + * + * @CpuServiceInstances + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[out] ApMailboxInfo The AP Mailbox info + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +typedef VOID (F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT AP_MAILBOXES *ApMailboxInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a method +typedef F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE *PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE; + +/** + * Set the AP core number in the AP's Mailbox. + * + * @CpuServiceInstances + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] Socket The AP's socket + * @param[in] Module The AP's module + * @param[in] ApCoreNumber The AP's unique core number + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +typedef VOID (F_CPU_SET_AP_CORE_NUMBER) ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN UINT32 Socket, + IN UINT32 Module, + IN UINT32 ApCoreNumber, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a method +typedef F_CPU_SET_AP_CORE_NUMBER *PF_CPU_SET_AP_CORE_NUMBER; + +/** + * Get the AP core number from hardware. + * + * @CpuServiceInstances + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @return The AP's unique core number + */ +typedef UINT32 (F_CPU_GET_AP_CORE_NUMBER) ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a method +typedef F_CPU_GET_AP_CORE_NUMBER *PF_CPU_GET_AP_CORE_NUMBER; + +/** + * Move the AP's core number from the mailbox to hardware. + * + * @CpuServiceInstances + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @return The AP's unique core number + */ +typedef VOID (F_CPU_TRANSFER_AP_CORE_NUMBER) ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a method +typedef F_CPU_TRANSFER_AP_CORE_NUMBER *PF_CPU_TRANSFER_AP_CORE_NUMBER; + +/** + * Core ID position in the initial APIC ID, reflected as a number zero or one. + */ +typedef enum { + CoreIdPositionZero, ///< Zero, the Core Id bits are the Most Significant bits. + CoreIdPositionOne, ///< One, the Core Id bits are the Least Significant bits. + CoreIdPositionMax ///< Limit check. +} CORE_ID_POSITION; + +/** + * Return a number zero or one, based on the Core ID position in the initial APIC Id. + * + * @CpuServiceInstances + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval CoreIdPositionZero Core Id is not low + * @retval CoreIdPositionOne Core Id is low + */ +typedef CORE_ID_POSITION F_CORE_ID_POSITION_IN_INITIAL_APIC_ID ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a method +typedef F_CORE_ID_POSITION_IN_INITIAL_APIC_ID *PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID; + +/** + * Get least common features set of all CPUs and save them to CPU_FEATURES_LIST + * + * @CpuServiceInstances + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in,out] cpuFeatureListPtr The CPU Features List + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +typedef VOID (F_CPU_SAVE_FEATURES) ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN OUT CPU_FEATURES_LIST *cpuFeatureListPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a method +typedef F_CPU_SAVE_FEATURES *PF_CPU_SAVE_FEATURES; + +/** + * Get least common features from CPU_FEATURES_LIST and write them to CPU + * + * @CpuServiceInstances + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in,out] cpuFeatureListPtr The CPU Features List + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +typedef VOID (F_CPU_WRITE_FEATURES) ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN OUT CPU_FEATURES_LIST *cpuFeatureListPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a method +typedef F_CPU_WRITE_FEATURES *PF_CPU_WRITE_FEATURES; + +/** + * Set Warm Reset Flag + * + * @CpuServiceInstances + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] StdHeader Header for library and services. + * @param[in] Request Value to set the flags to. + * + */ +typedef VOID (F_CPU_SET_WARM_RESET_FLAG) ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CONFIG_PARAMS *StdHeader, + IN WARM_RESET_REQUEST *Request + ); + +/// Reference to a method +typedef F_CPU_SET_WARM_RESET_FLAG *PF_CPU_SET_WARM_RESET_FLAG; + +/** + * Get Warm Reset Flag + * + * @CpuServiceInstances + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] StdHeader Header for library and services. + * @param[out] BiosRstDet Indicate warm reset status. + * + */ +typedef VOID (F_CPU_GET_WARM_RESET_FLAG) ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CONFIG_PARAMS *StdHeader, + OUT WARM_RESET_REQUEST *Request + ); + +/// Reference to a method +typedef F_CPU_GET_WARM_RESET_FLAG *PF_CPU_GET_WARM_RESET_FLAG; + + +/** + * Get CPU Specific Platform Type Info. + * + * @CpuServiceInstances + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in,out] FeaturesUnion The Features supported by this platform. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +typedef AGESA_STATUS F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN OUT PLATFORM_FEATS *FeaturesUnion, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO *PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO; + +/** + * Is the Northbridge PState feature enabled? + * + * @CpuServiceInstances + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] PlatformConfig Platform profile/build option config structure. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval TRUE The NB PState feature is enabled. + * @retval FALSE The NB PState feature is not enabled. + */ +typedef BOOLEAN F_IS_NB_PSTATE_ENABLED ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a method +typedef F_IS_NB_PSTATE_ENABLED *PF_IS_NB_PSTATE_ENABLED; + +/** + * Gets the next link with features matching the HT phy register table entry type features. + * + * @CpuServiceInstances + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in,out] HtHostCapability Initially the PCI bus, device, function=0, offset=0; + * Each call returns the HT Host Capability function and offset; + * Caller may use it to access registers, but must @b not modify it; + * Each new call passes the previous value as input. + * @param[in,out] Link Initially zero, each call returns the link number; caller passes it back unmodified each call. + * @param[in] HtPhyLinkType Link type field from a register table entry to compare against + * @param[out] MatchedSublink1 TRUE: It is actually just sublink 1 that matches, FALSE: any other condition. + * @param[out] Frequency0 The frequency of sublink0 (200 MHz if not connected). + * @param[out] Frequency1 The frequency of sublink1 (200 MHz if not connected). + * @param[in] StdHeader Standard Head Pointer + * + * @retval TRUE Link matches + * @retval FALSE No more links + * + */ +typedef BOOLEAN F_NEXT_LINK_HAS_HTFPY_FEATS ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN OUT PCI_ADDR *HtHostCapability, + IN OUT UINT32 *Link, + IN HT_PHY_LINK_FEATS *HtPhyLinkType, + OUT BOOLEAN *MatchedSublink1, + OUT HT_FREQUENCIES *Frequency0, + OUT HT_FREQUENCIES *Frequency1, + IN AMD_CONFIG_PARAMS *StdHeader + ); +/// Reference to a Method. +typedef F_NEXT_LINK_HAS_HTFPY_FEATS *PF_NEXT_LINK_HAS_HTFPY_FEATS; + +/** + * Applies an HT Phy read-modify-write based on an HT Phy register table entry. + * + * @CpuServiceInstances + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] HtPhyEntry HT Phy register table entry to apply + * @param[in] CapabilitySet The link's HT Host base address. + * @param[in] Link Zero based, node, link number (not package link), always a sublink0 link. + * @param[in] StdHeader Config handle for library and services + * + */ +typedef VOID F_SET_HT_PHY_REGISTER ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN HT_PHY_TYPE_ENTRY_DATA *HtPhyEntry, + IN PCI_ADDR CapabilitySet, + IN UINT32 Link, + IN AMD_CONFIG_PARAMS *StdHeader + ); +/// Reference to a Method. +typedef F_SET_HT_PHY_REGISTER *PF_SET_HT_PHY_REGISTER; + +/** + * Performs an early initialization function on the executing core. + * + * @param[in] FamilyServices The current Family Specific Services. + * @param[in] EarlyParams CPU module early paramters. + * @param[in] StdHeader Config handle for library and services + * + */ +typedef VOID F_PERFORM_EARLY_INIT_ON_CORE ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); +/// Reference to a Method. +typedef F_PERFORM_EARLY_INIT_ON_CORE *PF_PERFORM_EARLY_INIT_ON_CORE; + +/** + * A struct that contains function pointer and function flag + * + * the flag indicates if the function need to be run. + */ +typedef struct _S_PERFORM_EARLY_INIT_ON_CORE { + PF_PERFORM_EARLY_INIT_ON_CORE PerformEarlyInitOnCore; ///< Function Pointer, which points to the function need to be run at early stage + UINT32 PerformEarlyInitFlag; ///< Function Flag, which indicates if the function need to be run. +} S_PERFORM_EARLY_INIT_ON_CORE; + +/** + * Returns the initialization steps that the executing core should + * perform at AmdInitEarly. + * + * @CpuServiceInstances + * + * @param[in] FamilyServices The current Family Specific Services. + * @param[out] Table Table of appropriate init steps for the executing core. + * @param[in] EarlyParams CPU module early paramters. + * @param[in] StdHeader Config handle for library and services + * + */ +typedef VOID F_GET_EARLY_INIT_TABLE ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); +/// Reference to a Method. +typedef F_GET_EARLY_INIT_TABLE *PF_GET_EARLY_INIT_TABLE; + +/** + * Provide the features of the next HT link. + * + * @CpuServiceInstances + * + * This method is different than the HT Phy Features method, because for the phy registers + * sublink 1 matches and should be programmed if the link is ganged but for PCI config + * registers sublink 1 is reserved if the link is ganged. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in,out] Link The link number, for accessing non-capability set registers. + * Zero on initial call, and passed back unmodified on each subsequent call. + * @param[in,out] LinkBase IN: initially the node's PCI config base address, passed back on each call. + * OUT: the base HT Host capability PCI address for the link. + * @param[out] HtHostFeats The link's features. + * @param[in] StdHeader Standard Head Pointer + * + * @retval TRUE Valid link and features found. + * @retval FALSE No more links. + */ +typedef BOOLEAN F_GET_NEXT_HT_LINK_FEATURES ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN OUT UINTN *Link, + IN OUT PCI_ADDR *LinkBase, + OUT HT_HOST_FEATS *HtHostFeats, + IN AMD_CONFIG_PARAMS *StdHeader + ); +/// Reference to a Method. +typedef F_GET_NEXT_HT_LINK_FEATURES *PF_GET_NEXT_HT_LINK_FEATURES; + +/// Cache Enable / Disable policy before giving control back to OS. +typedef enum { + InitCacheDisabled, ///<Disable cache CR0.CD bit + InitCacheEnabled ///<Enable cache CR0.CD bit +} FAMILY_CACHE_INIT_POLICY; + + +/*---------------------------------------------------------------------------------------*/ +/** + * Provide the interface to all cpu Family Specific Services. + * + * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). + * Each supported Family must provide an implementation for all methods in this interface, even if the + * implementation is a CommonReturn(). + * See CPU Family Specific Services Implementation Guide for adding new services. + */ +struct _CPU_SPECIFIC_SERVICES { // See the Forwaqrd Declaration above + UINT16 Revision; ///< Interface version + // Public Methods. + PF_CPU_DISABLE_PSTATE DisablePstate; ///< Method: Disable the desired P-state. + PF_CPU_TRANSITION_PSTATE TransitionPstate; ///< Method: Transition the current core to the desired P-state. + PF_CPU_GET_IDD_MAX GetProcIddMax; ///< Method: Gets P-state maximum current required + PF_CPU_GET_TSC_RATE GetTscRate; ///< Method: Returns the rate at which the current core's timestamp counter increments in megahertz. + PF_CPU_GET_NB_FREQ GetCurrentNbFrequency; ///< Method: Returns the processor north bridge's clock rate in megahertz. + PF_CPU_GET_MIN_MAX_NB_FREQ GetMinMaxNbFrequency; ///< Method: Returns the node's minimum and maximum northbridge frequency. + PF_CPU_GET_NB_PSTATE_INFO GetNbPstateInfo; ///< Method: Returns information about the processor north bridge's P-states. + PF_CPU_IS_NBCOF_INIT_NEEDED IsNbCofInitNeeded; ///< Method: Returns whether or not the NB frequency initialization sequence is required to be performed by the BIOS. + PF_CPU_GET_NB_IDD_MAX GetNbIddMax; ///< Method: Gets NB P-state maximum current required + PF_CPU_AP_INITIAL_LAUNCH LaunchApCore; ///< Method: Launches the desired core from the reset vector. + PF_CPU_NUMBER_OF_PHYSICAL_CORES GetNumberOfPhysicalCores; ///< Method: Get the number of physical cores of current processor. + PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE GetApMailboxFromHardware; ///< Method: Get the AP's topology info from the hardware mailbox. + PF_CPU_SET_AP_CORE_NUMBER SetApCoreNumber; ///< Method: Set the AP's core number to the hardware mailbox. + PF_CPU_GET_AP_CORE_NUMBER GetApCoreNumber; ///< Method: Get the AP's core number from hardware. + PF_CPU_TRANSFER_AP_CORE_NUMBER TransferApCoreNumber; ///< Method: Move the AP's core number from the mailbox to hardware. + PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID CoreIdPositionInInitialApicId; ///< Method: Which bits in initial APIC Id are the Core Id. + PF_CPU_SAVE_FEATURES SaveFeatures; ///< Method: Get least common features set of all CPUs and save them to CPU_FEATURES_LIST + PF_CPU_WRITE_FEATURES WriteFeatures; ///< Method: Get least common features from CPU_FEATURES_LIST and write them to CPU + PF_CPU_SET_WARM_RESET_FLAG SetWarmResetFlag; ///< Method: Set Warm Reset Flag + PF_CPU_GET_WARM_RESET_FLAG GetWarmResetFlag; ///< Method: Get Warm Reset Flag + PF_CPU_GET_FAMILY_SPECIFIC_ARRAY GetBrandString1; ///< Method: Get a Brand String table + PF_CPU_GET_FAMILY_SPECIFIC_ARRAY GetBrandString2; ///< Method: Get a Brand String table + PF_CPU_GET_FAMILY_SPECIFIC_ARRAY GetMicroCodePatchesStruct; ///< Method: Get microcode patches + PF_CPU_GET_FAMILY_SPECIFIC_ARRAY GetMicrocodeEquivalenceTable; ///< Method: Get CPU equivalence for loading microcode patches. + PF_CPU_GET_FAMILY_SPECIFIC_ARRAY GetCacheInfo; ///< Method: Get setup for cache use and initialization. + PF_CPU_GET_FAMILY_SPECIFIC_ARRAY GetSysPmTableStruct; ///< Method: Get Power Management settings. + PF_CPU_GET_FAMILY_SPECIFIC_ARRAY GetWheaInitData; ///< Method: Get Whea Initial Data. + PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO GetPlatformTypeSpecificInfo; ///< Method: Get Specific platform Type features. + PF_IS_NB_PSTATE_ENABLED IsNbPstateEnabled; ///< Method: Get whether Northbridge PStates feature is enabled. + PF_NEXT_LINK_HAS_HTFPY_FEATS NextLinkHasHtPhyFeats; ///< Method: Iterate over HT Links matching features, for HT PHY entries. + PF_SET_HT_PHY_REGISTER SetHtPhyRegister; ///< Method: Set an Ht Phy register based on table entry. + PF_GET_NEXT_HT_LINK_FEATURES GetNextHtLinkFeatures; ///< Method: Iterate over HT links, returning link features. + REGISTER_TABLE **RegisterTableList; ///< Public Data: The available register tables. + TABLE_ENTRY_TYPE_DESCRIPTOR *TableEntryTypeDescriptors; ///< Public Data: implemented register table entry types. + PACKAGE_HTLINK_MAP PackageLinkMap; ///< Public Data: translate northbridge HT links to package level links, or NULL. + CORE_PAIR_MAP *CorePairMap; ///< Public Data: translate compute unit core pairing, or NULL. + FAMILY_CACHE_INIT_POLICY InitCacheDisabled; ///< public Data: Family related information. + PF_GET_EARLY_INIT_TABLE GetEarlyInitOnCoreTable; ///< Method: Get the initialization steps needed at AmdInitEarly. +}; + +/** + * A Family Id and an interface to it's implementations of Family Specific Services. + * + * Note that this is a logical family id, which may specify family, model (or even stepping). + */ +typedef struct { + UINT64 Family; ///< The Family to which this interface belongs. + CONST VOID *TablePtr; ///< The interface to its Family Specific Services. +} CPU_SPECIFIC_SERVICES_XLAT; + +/** + * A collection of Family specific interfaces to Family Specific services. + */ +typedef struct { + UINT8 Elements; ///< The number of tables to search. + CONST CPU_SPECIFIC_SERVICES_XLAT *FamilyTable; ///< The family interfaces. +} CPU_FAMILY_SUPPORT_TABLE; + +/** + * Implement the translation of a logical CPU id to an id that can be used to get Family specific services. + */ +typedef struct { + UINT32 Family; ///< Provide translation for this family + CPU_LOGICAL_ID UnknownRevision; ///< In this family, unrecognized models (or steppings) are treated as though they were this model and stepping. + CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY *SubFamilyIdTable; ///< Method: Get family specific model (and stepping) resolution. + UINT8 Elements; ///< The number of family specific model tables pointed to by SubFamilyIdTable +} CPU_LOGICAL_ID_FAMILY_XLAT; + +/** + * A collection of all available family id translations. + */ +typedef struct { + UINT8 Elements; ///< The number of family translation items to search. + CONST CPU_LOGICAL_ID_FAMILY_XLAT *FamilyIdTable; ///< The family translation items. +} CPU_FAMILY_ID_XLAT_TABLE; + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ + +/** + * Get a logical identifier for the specified processor, based on CPUID, but independent of CPUID formatting. + */ +VOID +GetLogicalIdOfSocket ( + IN UINT32 Socket, + OUT CPU_LOGICAL_ID *LogicalId, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Get a logical identifier for the executing core, based on CPUID, but independent of CPUID formatting. + */ +VOID +GetLogicalIdOfCurrentCore ( + OUT CPU_LOGICAL_ID *LogicalId, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Get a logical identifier for the specified CPUID value. + */ +VOID +GetLogicalIdFromCpuid ( + IN UINT32 RawCpuid, + OUT CPU_LOGICAL_ID *LogicalId, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Retrieves a pointer to the desired processor's family specific services structure. + */ +VOID +GetCpuServicesOfSocket ( + IN UINT32 Socket, + OUT CONST CPU_SPECIFIC_SERVICES **FunctionTable, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Retrieves a pointer to the desired processor's family specific services structure. + */ +VOID +GetFeatureServicesOfSocket ( + IN CPU_FAMILY_SUPPORT_TABLE *FamilyTable, + IN UINT32 Socket, + OUT CONST VOID **CpuServices, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Retrieves a pointer to the executing core's family specific services structure. + */ +VOID +GetCpuServicesOfCurrentCore ( + OUT CONST CPU_SPECIFIC_SERVICES **FunctionTable, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Retrieves a pointer to the executing core's family specific services structure. + */ +VOID +GetFeatureServicesOfCurrentCore ( + IN CPU_FAMILY_SUPPORT_TABLE *FamilyTable, + OUT CONST VOID **CpuServices, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Retrieves a pointer to the family specific services structure for a processor + * with the given logical ID. + */ +VOID +GetCpuServicesFromLogicalId ( + IN CPU_LOGICAL_ID *LogicalId, + OUT CONST CPU_SPECIFIC_SERVICES **FunctionTable, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Retrieves a pointer to the family specific services structure for a processor + * with the given logical ID. + */ +VOID +GetFeatureServicesFromLogicalId ( + IN CPU_FAMILY_SUPPORT_TABLE *FamilyTable, + IN CPU_LOGICAL_ID *LogicalId, + OUT CONST VOID **CpuServices, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Used by logical families which don't need a certain register setting table or other data array. + */ +VOID +GetEmptyArray ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **Empty, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif // _CPU_FAMILY_TRANSLATION_H_ + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c new file mode 100644 index 0000000..378a89a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c @@ -0,0 +1,1263 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Implement External, AGESA Common, and CPU component General Services. + * + * Contains implementation of the interfaces: General Services API in AGESA.h, + * GeneralServices.h, and cpuServices.h. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Options.h" +#include "Topology.h" +#include "cpuRegisters.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "cpuServices.h" +#include "heapManager.h" +#include "cpuApicUtilities.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_CPUGENERALSERVICES_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern OPTIONS_CONFIG_TOPOLOGY TopologyConfiguration; +extern BUILD_OPT_CFG UserOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S - External General Services API + *---------------------------------------------------------------------------------------- + */ + +/** + * Get a specified Core's APIC ID. + * + * Invoke corresponding Cpu Service for external user. + * + * @param[in,out] AmdParamApic Our interface struct + * + * @return The most severe status of any called service. + */ +AGESA_STATUS +AmdGetApicId ( + IN OUT AMD_APIC_PARAMS *AmdParamApic + ) +{ + AGESA_STATUS AgesaStatus; + + AGESA_TESTPOINT (TpIfAmdGetApicIdEntry, &AmdParamApic->StdHeader); + AmdParamApic->StdHeader.HeapBasePtr = HeapGetBaseAddress (&AmdParamApic->StdHeader); + + AmdParamApic->IsPresent = GetApicId ( + &AmdParamApic->StdHeader, + AmdParamApic->Socket, + AmdParamApic->Core, + &AmdParamApic->ApicAddress, + &AgesaStatus + ); + + AGESA_TESTPOINT (TpIfAmdGetApicIdExit, &AmdParamApic->StdHeader); + return AgesaStatus; +} + +/** + * Get Processor Module's PCI Config Space address. + * + * Invoke corresponding Cpu Service for external user. + * + * @param[in,out] AmdParamGetPci Our interface struct + * + * @return The most severe status of any called service. + */ +AGESA_STATUS +AmdGetPciAddress ( + IN OUT AMD_GET_PCI_PARAMS *AmdParamGetPci + ) +{ + AGESA_STATUS AgesaStatus; + + AGESA_TESTPOINT (TpIfAmdGetPciAddressEntry, &AmdParamGetPci->StdHeader); + AmdParamGetPci->StdHeader.HeapBasePtr = HeapGetBaseAddress (&AmdParamGetPci->StdHeader); + + AmdParamGetPci->IsPresent = GetPciAddress ( + &AmdParamGetPci->StdHeader, + AmdParamGetPci->Socket, + AmdParamGetPci->Module, + &AmdParamGetPci->PciAddress, + &AgesaStatus + ); + + AGESA_TESTPOINT (TpIfAmdGetPciAddressExit, &AmdParamGetPci->StdHeader); + return AgesaStatus; +} + +/** + * "Who am I" for the current running core. + * + * Invoke corresponding Cpu Service for external user. + * + * @param[in,out] AmdParamIdentify Our interface struct + * + * @return The most severe status of any called service. + */ +AGESA_STATUS +AmdIdentifyCore ( + IN OUT AMD_IDENTIFY_PARAMS *AmdParamIdentify + ) +{ + AGESA_STATUS AgesaStatus; + UINT32 Socket; + UINT32 Module; + UINT32 Core; + + AGESA_TESTPOINT (TpIfAmdIdentifyCoreEntry, &AmdParamIdentify->StdHeader); + AmdParamIdentify->StdHeader.HeapBasePtr = HeapGetBaseAddress (&AmdParamIdentify->StdHeader); + + IdentifyCore ( + &AmdParamIdentify->StdHeader, + &Socket, + &Module, + &Core, + &AgesaStatus + ); + AmdParamIdentify->Socket = (UINT8)Socket; + AmdParamIdentify->Module = (UINT8)Module; + AmdParamIdentify->Core = (UINT8)Core; + + AGESA_TESTPOINT (TpIfAmdIdentifyCoreExit, &AmdParamIdentify->StdHeader); + return AgesaStatus; +} + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S - AGESA common General Services + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Get a specified Core's APIC ID. + * + * Code sync: This calculation MUST match the assignment + * calculation done in LocalApicInitializationAtEarly function. + * + * @param[in] StdHeader Header for library and services. + * @param[in] Socket The socket in which the Core's Processor is installed. + * @param[in] Core The Core id. + * @param[out] ApicAddress The Core's APIC ID. + * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. + * + * @retval TRUE The core is present, APIC Id valid + * @retval FALSE The core is not present, APIC Id not valid. +*/ +BOOLEAN +GetApicId ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT32 Socket, + IN UINT32 Core, + OUT UINT8 *ApicAddress, + OUT AGESA_STATUS *AgesaStatus + ) +{ + BOOLEAN ReturnValue; + UINT32 CoreCount; + UINT32 ApicID; + + ReturnValue = FALSE; + if (GetActiveCoresInGivenSocket (Socket, &CoreCount, StdHeader)) { + if (Core < CoreCount) { + ReturnValue = TRUE; + GetLocalApicIdForCore (Socket, Core, &ApicID, StdHeader); + *ApicAddress = (UINT8) ApicID; + } + } + + // Always Succeeds. + *AgesaStatus = AGESA_SUCCESS; + + return ReturnValue; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Get Processor Module's PCI Config Space address. + * + * @param[in] StdHeader Header for library and services. + * @param[in] Socket The Core's Socket. + * @param[in] Module The Module in that Processor + * @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0) + * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. + * + * @retval TRUE The core is present, PCI Address valid + * @retval FALSE The core is not present, PCI Address not valid. + */ +BOOLEAN +GetPciAddress ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT32 Socket, + IN UINT32 Module, + OUT PCI_ADDR *PciAddress, + OUT AGESA_STATUS *AgesaStatus + ) +{ + UINT8 Node; + BOOLEAN Result; + + ASSERT (Socket < MAX_SOCKETS); + ASSERT (Module < MAX_DIES); + + Result = TRUE; + // Always Succeeds. + *AgesaStatus = AGESA_SUCCESS; + + if (GetNodeId (Socket, Module, &Node, StdHeader)) { + // socket is populated + PciAddress->AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0); + PciAddress->Address.Device = PciAddress->Address.Device + Node; + } else { + // socket is not populated + PciAddress->AddressValue = ILLEGAL_SBDFO; + Result = FALSE; + } + return Result; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * "Who am I" for the current running core. + * + * @param[in] StdHeader Header for library and services. + * @param[out] Socket The current Core's Socket + * @param[out] Module The current Core's Processor Module + * @param[out] Core The current Core's core id. + * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. + * + */ +VOID +IdentifyCore ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT UINT32 *Socket, + OUT UINT32 *Module, + OUT UINT32 *Core, + OUT AGESA_STATUS *AgesaStatus + ) +{ + AP_MAIL_INFO ApMailboxInfo; + UINT32 CurrentCore; + + // Always Succeeds. + *AgesaStatus = AGESA_SUCCESS; + + GetApMailbox (&ApMailboxInfo.Info, StdHeader); + ASSERT (ApMailboxInfo.Fields.Socket < MAX_SOCKETS); + ASSERT (ApMailboxInfo.Fields.Module < MAX_DIES); + *Socket = (UINT8)ApMailboxInfo.Fields.Socket; + *Module = (UINT8)ApMailboxInfo.Fields.Module; + + // Get Core Id + GetCurrentCore (&CurrentCore, StdHeader); + *Core = (UINT8)CurrentCore; +} + + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S - cpu component General Services + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Get the current Platform's number of Sockets, regardless of how many are populated. + * + * The Options component can provide how many sockets are available in system. + * This can be used to avoid testing presence of Processors in Sockets which don't exist. + * The result can be one socket to the maximum possible sockets of any supported processor family. + * You cannot assume that all sockets contain a processor or that the sockets have processors + * installed in any particular order. Do not convert this number to a number of nodes. + * + * @return The number of available sockets for the platform. + * + */ +UINT32 +GetPlatformNumberOfSockets ( VOID ) +{ + return TopologyConfiguration.PlatformNumberOfSockets; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Get the number of Modules to check presence in each Processor. + * + * The Options component can provide how many modules need to be check for presence in each + * processor, regardless whether all, or any, processor have that many modules present on this boot. + * The result can be one module to the maximum possible modules of any supported processor family. + * You cannot assume that Modules are in any particular order, especially with respect to node id. + * + * @return The maximum number of modules in each processor. + * + */ +UINT32 +GetPlatformNumberOfModules ( VOID ) +{ + return TopologyConfiguration.PlatformNumberOfModules; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Is a processor present in Socket? + * + * Check to see if any possible module of the processor is present. This provides + * support for a few cases where a PCI address isn't needed, but code still needs to + * iterate by Socket. + * + * @param[in] Socket The socket which is being tested + * @param[in] StdHeader Header for library and services. + * + * @retval TRUE The socket has a processor installed + * @retval FALSE The socket is empty (or the processor is dead). + * + */ +BOOLEAN +IsProcessorPresent ( + IN UINT32 Socket, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + SOCKET_DIE_TO_NODE_MAP pSocketDieMap; + LOCATE_HEAP_PTR SocketDieHeapDataBlock; + BOOLEAN Result; + UINT32 Module; + AGESA_STATUS Status; + + ASSERT (Socket < MAX_SOCKETS); + Result = FALSE; + SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE; + + // Get data block from heap + Status = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader); + pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr; + ASSERT ((pSocketDieMap != NULL) && (Status == AGESA_SUCCESS)); + for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { + if ((*pSocketDieMap)[Socket][Module].Node != 0xFF) { + Result = TRUE; + break; + } + } + return Result; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Provide the number of installed processors (not Nodes! and not Sockets!) + * + * Iterate over the Socket, Module to Node Map, counting the number of present nodes. + * Do not use this as a Node Count! Do not use this as the number of Sockets! (This + * is for APIC ID utilities.) + * + * @param[in] StdHeader Header for library and services. + * + * @return the number of processors installed + * + */ +UINT32 +GetNumberOfProcessors ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + SOCKET_DIE_TO_NODE_MAP pSocketDieMap; + LOCATE_HEAP_PTR SocketDieHeapDataBlock; + UINT32 Result; + UINT32 Socket; + UINT32 Module; + AGESA_STATUS Status; + + Result = 0; + SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE; + + // Get data block from heap + Status = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader); + pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr; + ASSERT ((pSocketDieMap != NULL) && (Status == AGESA_SUCCESS)); + for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { + for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { + if ((*pSocketDieMap)[Socket][Module].Node != 0xFF) { + Result++; + break; + } + } + } + return Result; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * For a specific Node, get its Socket and Module ids. + * + * If asking for the current running Node, read the mailbox socket, module. Specific Node, + * locate the Node to Socket/Module Map in heap, and return the ids, if present. + * + * @param[in] Node What Socket and Module is this Node? + * @param[out] Socket The Socket containing that Node. + * @param[out] Module The Processor Module of that Node. + * @param[in] StdHeader Header for library and services. + * + * @retval TRUE Node is present, Socket, Module are valid. + * @retval FALSE Node is not present, why do you ask? + */ +BOOLEAN +GetSocketModuleOfNode ( + IN UINT32 Node, + OUT UINT32 *Socket, + OUT UINT32 *Module, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + NODE_TO_SOCKET_DIE_MAP pNodeMap; + LOCATE_HEAP_PTR SocketDieHeapDataBlock; + BOOLEAN Result; + AGESA_STATUS Status; + + Result = FALSE; + + ASSERT (Node < MAX_NODES); + + // Get Map from heap + SocketDieHeapDataBlock.BufferHandle = NODE_ID_MAP_HANDLE; + Status = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader); + pNodeMap = (NODE_TO_SOCKET_DIE_MAP)SocketDieHeapDataBlock.BufferPtr; + ASSERT ((pNodeMap != NULL) && (Status == AGESA_SUCCESS)); + *Socket = (*pNodeMap)[Node].Socket; + *Module = (*pNodeMap)[Node].Die; + if ((*pNodeMap)[Node].Socket != 0xFF) { + Result = TRUE; + } + return Result; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Get the current core's Processor APIC Index. + * + * The Processor APIC Index is the position of the current processor in the APIC id + * assignment. Processors are ordered in node id order. This is not the same, however, + * as the node id of the current socket and module or the current socket id. + * + * @param[in] Node The current desired core's node id (usually the current core). + * @param[in] StdHeader Header for library and services. + * + * @return Processor APIC Index + * + */ +UINT32 +GetProcessorApicIndex ( + IN UINT32 Node, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 ProcessorApicIndex; + UINT32 PreviousSocket; + UINT32 CurrentSocket; + UINT32 Ignored; + UINT32 i; + + ASSERT (Node < MAX_NODES); + + // Calculate total APIC devices up to Current Node, Core. + ProcessorApicIndex = 0; + PreviousSocket = 0xFF; + for (i = 0; i < (Node + 1); i++) { + GetSocketModuleOfNode (i, &CurrentSocket, &Ignored, StdHeader); + if (CurrentSocket != PreviousSocket) { + ProcessorApicIndex++; + PreviousSocket = CurrentSocket; + } + } + // Convert to Index (zero based) from count (one based). + ProcessorApicIndex--; + return ProcessorApicIndex; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns current node number + * + * @param[out] Node This Core's Node id + * @param[in] StdHeader Header for library and services. + * + */ +VOID +GetCurrentNodeNum ( + OUT UINT32 *Node, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AP_MAIL_INFO ApMailboxInfo; + + // Get the Node Id from the Mailbox. + GetApMailbox (&ApMailboxInfo.Info, StdHeader); + ASSERT (ApMailboxInfo.Fields.Node < MAX_NODES); + *Node = ApMailboxInfo.Fields.Node; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns Total number of active cores in the current socket + * + * @param[out] CoreCount The cores in this processor. + * @param[in] StdHeader Header for library and services. + * + */ +VOID +GetActiveCoresInCurrentSocket ( + OUT UINT32 *CoreCount, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + CPUID_DATA CpuidDataStruct; + UINT32 TotalCoresCount; + + LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuidDataStruct, StdHeader); + TotalCoresCount = (CpuidDataStruct.ECX_Reg & 0x000000FF) + 1; + *CoreCount = TotalCoresCount; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Provides the Total number of active cores in the current core's node. + * + * @param[in] StdHeader Header for library and services. + * + * @return The current node core count + */ +UINTN +GetActiveCoresInCurrentModule ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Socket; + UINT32 Module; + UINT32 Core; + UINT32 LowCore; + UINT32 HighCore; + UINT32 ProcessorCoreCount; + AGESA_STATUS AgesaStatus; + + ProcessorCoreCount = 0; + + IdentifyCore (StdHeader, &Socket, &Module, &Core, &AgesaStatus); + if (GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader)) { + ProcessorCoreCount = ((HighCore - LowCore) + 1); + } + return ProcessorCoreCount; +} + +/** + * Provide the number of compute units on current module. + * + * + * @param[in] StdHeader Header for library and services. + * + * @return The current compute unit counts. + * + */ +UINTN +GetNumberOfCompUnitsInCurrentModule ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Socket; + UINT32 Module; + UINT32 CurrentCore; + UINT32 ComputeUnitCount; + UINT32 Enabled; + AGESA_STATUS IgnoredSts; + LOCATE_HEAP_PTR SocketDieHeapDataBlock; + SOCKET_DIE_TO_NODE_MAP pSocketDieMap; + + ComputeUnitCount = 0; + + ASSERT ((GetComputeUnitMapping (StdHeader) == AllCoresMapping) || + (GetComputeUnitMapping (StdHeader) == EvenCoresMapping)); + + IdentifyCore (StdHeader, &Socket, &Module, &CurrentCore, &IgnoredSts); + // Get data block from heap + SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE; + IgnoredSts = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader); + pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr; + ASSERT ((pSocketDieMap != NULL) && (IgnoredSts == AGESA_SUCCESS)); + // Current Core's socket, module must be present. + ASSERT ((*pSocketDieMap)[Socket][Module].Node != 0xFF); + // Process compute unit info + Enabled = (*pSocketDieMap)[Socket][Module].EnabledComputeUnits; + + while (Enabled > 0) { + if ((Enabled & 0x1) != 0) { + ComputeUnitCount++; + } + Enabled >>= 1; + } + + return ComputeUnitCount; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Provides the Total number of active cores in the given socket. + * + * @param[in] Socket Get a core count for the processor in this socket. + * @param[out] CoreCount Its core count + * @param[in] StdHeader Header for library and services. + * + * @retval TRUE A processor is present in the Socket and the CoreCount is valid. + * @retval FALSE The Socket does not have a Processor + */ +BOOLEAN +GetActiveCoresInGivenSocket ( + IN UINT32 Socket, + OUT UINT32 *CoreCount, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Module; + UINT32 LowCore; + UINT32 HighCore; + UINT32 ProcessorCoreCount; + BOOLEAN Result; + + Result = FALSE; + ProcessorCoreCount = 0; + + for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { + if (GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader)) { + ProcessorCoreCount = ProcessorCoreCount + ((HighCore - LowCore) + 1); + Result = TRUE; + } else { + break; + } + } + *CoreCount = ProcessorCoreCount; + return Result; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Provides the range of Cores in a Processor which are in a Module. + * + * Cores are named uniquely in a processor, 0 to TotalCores. Any module in the processor has + * a set of those cores, named from LowCore to HighCore. + * + * @param[in] Socket Get a core range for the processor in this socket. + * @param[in] Module Get a core range for this Module in the processor. + * @param[out] LowCore The lowest Processor Core in the Module. + * @param[out] HighCore The highest Processor Core in the Module. + * @param[in] StdHeader Header for library and services. + * + * @retval TRUE A processor is present in the Socket and the Core Range is valid. + * @retval FALSE The Socket does not have a Processor + */ +BOOLEAN +GetGivenModuleCoreRange ( + IN UINT32 Socket, + IN UINT32 Module, + OUT UINT32 *LowCore, + OUT UINT32 *HighCore, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + SOCKET_DIE_TO_NODE_MAP pSocketDieMap; + LOCATE_HEAP_PTR SocketDieHeapDataBlock; + BOOLEAN Result; + AGESA_STATUS Status; + + ASSERT (Socket < MAX_SOCKETS); + ASSERT (Module < MAX_DIES); + Result = FALSE; + SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE; + + // Get data block from heap + Status = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader); + pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr; + ASSERT ((pSocketDieMap != NULL) && (Status == AGESA_SUCCESS)); + *LowCore = (*pSocketDieMap)[Socket][Module].LowCore; + *HighCore = (*pSocketDieMap)[Socket][Module].HighCore; + if ((*pSocketDieMap)[Socket][Module].Node != 0xFF) { + Result = TRUE; + } + return Result; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the current running core number. + * + * @param[out] Core The core id. + * @param[in] StdHeader Header for library and services. + * + */ +VOID +GetCurrentCore ( + OUT UINT32 *Core, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + CPUID_DATA CpuidDataStruct; + UINT32 LocalApicId; + UINT32 ApicIdCoreIdSize; + CORE_ID_POSITION InitApicIdCpuIdLo; + CPU_SPECIFIC_SERVICES *FamilyServices; + + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader); + ASSERT (FamilyServices != NULL); + + // Read CPUID ebx[31:24] to get initial APICID + LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuidDataStruct, StdHeader); + LocalApicId = (CpuidDataStruct.EBX_Reg & 0xFF000000) >> 24; + + // Find the core ID size. + LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuidDataStruct, StdHeader); + ApicIdCoreIdSize = (CpuidDataStruct.ECX_Reg & 0x0000F000) >> 12; + + InitApicIdCpuIdLo = FamilyServices->CoreIdPositionInInitialApicId (FamilyServices, StdHeader); + ASSERT (InitApicIdCpuIdLo < CoreIdPositionMax); + + // Now extract the core ID from the Apic ID by right justifying the id and masking off non-core Id bits. + *Core = ((LocalApicId >> ((1 - (UINT32)InitApicIdCpuIdLo) * (MAX_CORE_ID_SIZE - ApicIdCoreIdSize))) & + (MAX_CORE_ID_MASK >> (MAX_CORE_ID_SIZE - ApicIdCoreIdSize))); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns current node, and core number. + * + * @param[out] Node The node id of the current core's node. + * @param[out] Core The core id if the current core. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +GetCurrentNodeAndCore ( + OUT UINT32 *Node, + OUT UINT32 *Core, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + // Get Node Id + GetCurrentNodeNum (Node, StdHeader); + + // Get Core Id + GetCurrentCore (Core, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Is the current core a primary core of it's node? + * + * @param[in] StdHeader Config handle for library and services. + * + * @retval TRUE Is Primary Core + * @retval FALSE Is not Primary Core + * + */ +BOOLEAN +IsCurrentCorePrimary ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + BOOLEAN Result; + UINT32 Core; + UINT32 Socket; + UINT32 Module; + UINT32 PrimaryCore; + UINT32 IgnoredCore; + AGESA_STATUS IgnoredSts; + + Result = FALSE; + + IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); + GetGivenModuleCoreRange (Socket, Module, &PrimaryCore, &IgnoredCore, StdHeader); + if (Core == PrimaryCore) { + Result = TRUE; + } + return Result; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns node id based on SocketId and ModuleId. + * + * @param[in] SocketId The socket to look up + * @param[in] ModuleId The module in that socket + * @param[out] NodeId Provide the corresponding Node Id. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval TRUE The socket is populated + * @retval FALSE The socket is not populated + * + */ +BOOLEAN +GetNodeId ( + IN UINT32 SocketId, + IN UINT32 ModuleId, + OUT UINT8 *NodeId, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + SOCKET_DIE_TO_NODE_MAP pSocketDieMap; + LOCATE_HEAP_PTR SocketDieHeapDataBlock; + BOOLEAN Result; + AGESA_STATUS Status; + + Result = FALSE; + SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE; + + // Get data block from heap + Status = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader); + pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr; + ASSERT ((pSocketDieMap != NULL) && (Status == AGESA_SUCCESS)); + *NodeId = (*pSocketDieMap)[SocketId][ModuleId].Node; + if ((*pSocketDieMap)[SocketId][ModuleId].Node != 0xFF) { + Result = TRUE; + } + return Result; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Get the cached AP Mailbox Info if available, or read the info from the hardware. + * + * Locate the known AP Mailbox Info Cache buffer in this core's local heap. If it + * doesn't exist, read the hardware to get the info. + * This routine gets the main AP mailbox, not the system degree. + * + * @param[out] ApMailboxInfo Provide the info in this AP core's mailbox + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +GetApMailbox ( + OUT UINT32 *ApMailboxInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Ignored; + LOCATE_HEAP_PTR LocalApMailboxCache; + CPU_SPECIFIC_SERVICES *FamilyServices; + AP_MAILBOXES ApMailboxes; + BOOLEAN IamBsp; + + IamBsp = IsBsp (StdHeader, &Ignored); + LocalApMailboxCache.BufferHandle = LOCAL_AP_MAIL_BOX_CACHE_HANDLE; + if (((StdHeader->HeapStatus == HEAP_LOCAL_CACHE) || IamBsp) && + (HeapLocateBuffer (&LocalApMailboxCache, StdHeader) == AGESA_SUCCESS)) { + // If during HEAP_LOCAL_CACHE stage, we always try to get ApMailbox from heap + // If we're not in HEAP_LOCAL_CACHE stage, only BSP can get ApMailbox from heap + *ApMailboxInfo = ((AP_MAILBOXES *) LocalApMailboxCache.BufferPtr)->ApMailInfo.Info; + } else if (!IamBsp) { + // If this is an AP, the hardware register should be good. + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader); + ASSERT (FamilyServices != NULL); + FamilyServices->GetApMailboxFromHardware (FamilyServices, &ApMailboxes, StdHeader); + *ApMailboxInfo = ApMailboxes.ApMailInfo.Info; + } else { + // This is the BSC. The hardware mailbox has not been set up yet. + ASSERT (FALSE); + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Cache the Ap Mailbox info in our local heap for later use. + * + * This enables us to use the info even after the mailbox register is initialized + * with operational values. Get all the AP mailboxes and keep them in one buffer. + * + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +CacheApMailbox ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + ALLOCATE_HEAP_PARAMS AllocHeapParams; + AP_MAILBOXES ApMailboxes; + CPU_SPECIFIC_SERVICES *FamilyServices; + + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader); + ASSERT (FamilyServices != NULL); + + // Get mailbox from hardware. + FamilyServices->GetApMailboxFromHardware (FamilyServices, &ApMailboxes, StdHeader); + + // Allocate heap for the info + AllocHeapParams.RequestedBufferSize = sizeof (AP_MAILBOXES); + AllocHeapParams.BufferHandle = LOCAL_AP_MAIL_BOX_CACHE_HANDLE; + AllocHeapParams.Persist = HEAP_SYSTEM_MEM; + if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { + *(AP_MAILBOXES *)AllocHeapParams.BufferPtr = ApMailboxes; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Compute the degree of the system. + * + * The degree of a system is the maximum degree of any node. The degree of a node is the + * number of nodes to which it is directly connected (not considering width or redundant + * links). + * + * @param[in] StdHeader Config handle for library and services. + * + */ +UINTN +GetSystemDegree ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AP_MAILBOXES *ApMailboxes; + LOCATE_HEAP_PTR LocalApMailboxCache; + AGESA_STATUS Status; + + // Get data block from heap + LocalApMailboxCache.BufferHandle = LOCAL_AP_MAIL_BOX_CACHE_HANDLE; + Status = HeapLocateBuffer (&LocalApMailboxCache, StdHeader); + // non-Success handled by ASSERT not NULL below. + ApMailboxes = (AP_MAILBOXES *)LocalApMailboxCache.BufferPtr; + ASSERT ((ApMailboxes != NULL) && (Status == AGESA_SUCCESS)); + return ApMailboxes->ApMailExtInfo.Fields.SystemDegree; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Spins until the number of microseconds specified have + * expired regardless of CPU operational frequency. + * + * @param[in] Microseconds Wait time in microseconds + * @param[in] StdHeader Header for library and services + * + */ +VOID +WaitMicroseconds ( + IN UINT32 Microseconds, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TscRateInMhz; + UINT64 NumberOfTicks; + UINT64 InitialTsc; + UINT64 CurrentTsc; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + LibAmdMsrRead (TSC, &InitialTsc, StdHeader); + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, StdHeader); + NumberOfTicks = Microseconds * TscRateInMhz; + do { + LibAmdMsrRead (TSC, &CurrentTsc, StdHeader); + } while ((CurrentTsc - InitialTsc) < NumberOfTicks); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * A boolean function determine executed CPU is BSP core. + * + * @param[in,out] StdHeader Header for library and services + * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. + * + */ +BOOLEAN +IsBsp ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + OUT AGESA_STATUS *AgesaStatus + ) +{ + UINT64 MsrData; + + // Always Succeeds. + *AgesaStatus = AGESA_SUCCESS; + + // Read APIC_BASE register (0x1B), bit[8] returns 1 for BSP + LibAmdMsrRead (MSR_APIC_BAR, &MsrData, StdHeader); + if ((MsrData & BIT8) != 0 ) { + return TRUE; + } else { + return FALSE; + } + +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Get the compute unit mapping algorithm. + * + * Look up the compute unit values for the current core's socket/module and find the matching + * core pair map item. This will tell us how to determine the core's status. + * + * @param[in] StdHeader Header for library and services + * + * @retval AllCoresMapping Each core is in a compute unit of its own. + * @retval EvenCoresMapping Even/Odd pairs of cores are in each compute unit. + */ +COMPUTE_UNIT_MAPPING +GetComputeUnitMapping ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 CurrentCore; + UINT32 Module; + UINT32 Socket; + UINT8 Enabled; + UINT8 DualCore; + AGESA_STATUS IgnoredSts; + SOCKET_DIE_TO_NODE_MAP pSocketDieMap; + LOCATE_HEAP_PTR SocketDieHeapDataBlock; + CPU_SPECIFIC_SERVICES *FamilyServices; + CORE_PAIR_MAP *CorePairMap; + COMPUTE_UNIT_MAPPING Result; + + // Invalid mapping, unless we find one. + Result = MaxComputeUnitMapping; + + IdentifyCore (StdHeader, &Socket, &Module, &CurrentCore, &IgnoredSts); + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader); + ASSERT (FamilyServices != NULL); + + // Get data block from heap + SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE; + IgnoredSts = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader); + pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr; + ASSERT ((pSocketDieMap != NULL) && (IgnoredSts == AGESA_SUCCESS)); + // Current Core's socket, module must be present. + ASSERT ((*pSocketDieMap)[Socket][Module].Node != 0xFF); + + // Process compute unit info + Enabled = (*pSocketDieMap)[Socket][Module].EnabledComputeUnits; + DualCore = (*pSocketDieMap)[Socket][Module].DualCoreComputeUnits; + CorePairMap = FamilyServices->CorePairMap; + if ((Enabled != 0) && (CorePairMap != NULL)) { + while (CorePairMap->Enabled != 0xFF) { + if ((Enabled == CorePairMap->Enabled) && (DualCore == CorePairMap->DualCore)) { + break; + } + CorePairMap++; + } + // The assert is for finding a processor configured in a way the core pair map doesn't support. + ASSERT (CorePairMap->Enabled != 0xFF); + Result = CorePairMap->Mapping; + } else { + // Families that don't have compute units act as though each core is in its own compute unit + // and all cores are primary + Result = AllCoresMapping; + } + return Result; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Is current core the primary core of its compute unit? + * + * Get the mapping algorithm and the current core number. Selecting First/Last ordering for + * primary @b ASSUMES cores are launched in ascending core number order. + * + * @param[in] Selector Select whether first or last core has the primary core role. + * @param[in] StdHeader Header for library and services + * + * @retval TRUE This is the primary core of a compute unit. + * @retval FALSE This is the second shared core of a compute unit. + * + */ +BOOLEAN +IsCorePairPrimary ( + IN COMPUTE_UNIT_PRIMARY_SELECTOR Selector, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + BOOLEAN Result; + UINT32 CurrentCore; + UINT32 Module; + UINT32 Socket; + AGESA_STATUS IgnoredSts; + + IdentifyCore (StdHeader, &Socket, &Module, &CurrentCore, &IgnoredSts); + + Result = FALSE; + switch (GetComputeUnitMapping (StdHeader)) { + case AllCoresMapping: + // All cores are primaries + Result = TRUE; + break; + case EvenCoresMapping: + // Even core numbers are first to execute, odd cores are last to execute + if (Selector == FirstCoreIsComputeUnitPrimary) { + Result = (BOOLEAN) ((CurrentCore & 1) == 0); + } else { + Result = (BOOLEAN) ((CurrentCore & 1) != 0); + } + break; + default: + ASSERT (FALSE); + } + return Result; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Are the two specified cores shared in a compute unit? + * + * Look up the compute unit values for the current core's socket/module and find the matching + * core pair map item. This will tell us how to determine the core's status. + * + * @param[in] Socket The processor in this socket is to be checked + * @param[in] Module The processor in this module is to be checked + * @param[in] CoreA One of the two cores to check + * @param[in] CoreB The other core to be checked + * @param[in] StdHeader Header for library and services + * + * @retval TRUE The cores are in the same compute unit. + * @retval FALSE The cores are not in the same compute unit, or the processor does + * not have compute units. + * + */ +BOOLEAN +AreCoresPaired ( + IN UINT32 Socket, + IN UINT32 Module, + IN UINT32 CoreA, + IN UINT32 CoreB, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + BOOLEAN Result; + + Result = FALSE; + switch (GetComputeUnitMapping (StdHeader)) { + case AllCoresMapping: + // No cores are sharing a compute unit + Result = FALSE; + break; + case EvenCoresMapping: + // Even core numbers are paired with odd core numbers, n with n + 1 + if ((CoreA & 1) == 0) { + Result = (BOOLEAN) (CoreA == (CoreB - 1)); + } else { + Result = (BOOLEAN) (CoreA == (CoreB + 1)); + } + break; + default: + ASSERT (FALSE); + } + return Result; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * + * This routine programs the registers necessary to get the PCI MMIO mechanism + * up and functioning. + * + * @param[in] StdHeader Pointer to structure containing the function call + * whose parameter structure is to be created, the + * allocation method, and a pointer to the newly + * created structure. + * + */ +VOID +InitializePciMmio ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 EncodedSize; + UINT64 LocalMsrRegister; + + // Make sure that Standard header is valid + ASSERT (StdHeader != NULL); + + if ((UserOptions.CfgPciMmioAddress != 0) && (UserOptions.CfgPciMmioSize != 0)) { + EncodedSize = LibAmdBitScanForward (UserOptions.CfgPciMmioSize); + LocalMsrRegister = ((UserOptions.CfgPciMmioAddress | BIT0) | (EncodedSize << 2)); + LibAmdMsrWrite (MSR_MMIO_Cfg_Base, &LocalMsrRegister, StdHeader); + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuInitEarlyTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuInitEarlyTable.c new file mode 100644 index 0000000..c832be4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuInitEarlyTable.c @@ -0,0 +1,151 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize the 'common' way of running early initialization. + * + * Returns the table of initialization steps to perform at + * AmdInitEarly. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +#include "cpuEarlyInit.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_CPUINITEARLYTABLE_FILECODE + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +GetCommonEarlyInitOnCoreTable ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern F_PERFORM_EARLY_INIT_ON_CORE McaInitializationAtEarly; +extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAtEarly; +extern F_PERFORM_EARLY_INIT_ON_CORE SetBrandIdRegistersAtEarly; +extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly; +extern F_PERFORM_EARLY_INIT_ON_CORE LoadMicrocodePatchAtEarly; + +CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA CommonEarlyInitOnCoreTable[] = +{ + {McaInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION}, + {SetRegistersFromTablesAtEarly, PERFORM_EARLY_ANY_CONDITION}, + {SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION}, + {LocalApicInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION}, + {LoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION}, + {NULL, 0} +}; + +/*------------------------------------------------------------------------------------*/ +/** + * Initializer routine that may be invoked at AmdCpuEarly to return the steps that a + * processor that uses the standard initialization steps should take. + * + * @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}. + * + * @param[in] FamilyServices The current Family Specific Services. + * @param[out] Table Table of appropriate init steps for the executing core. + * @param[in] EarlyParams Service Interface structure to initialize. + * @param[in] StdHeader Opaque handle to standard config header. + * + */ +VOID +GetCommonEarlyInitOnCoreTable ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *Table = CommonEarlyInitOnCoreTable; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.c new file mode 100644 index 0000000..a9a5631 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.c @@ -0,0 +1,420 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Late Init API + * + * Contains code for doing any late CPU initialization. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuLateInit.h" +#include "cpuRegisters.h" +#include "GeneralServices.h" +#include "cpuServices.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_CPULATEINIT_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +DisableCf8ExtCfg ( + IN AMD_CONFIG_PARAMS *StdHeader + ); +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------*/ +/** + * Performs CPU related initialization at the late entry point + * + * This function should be the last function run by the AGESA + * CPU module and prepares the processor for the operating system + * bootstrap load process. + * + * @param[in] StdHeader Config handle for library and services + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * + * @retval AGESA_SUCCESS + * + */ +AGESA_STATUS +AmdCpuLate ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig + ) +{ + AP_EXE_PARAMS ApParams; + + if ((PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.HardwarePrefetchMode != HARDWARE_PREFETCHER_AUTO) || + (PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.SoftwarePrefetchMode != SOFTWARE_PREFETCHES_AUTO)) { + ApParams.StdHeader = *StdHeader; + ApParams.FunctionNumber = AP_LATE_TASK_CPU_LATE_INIT; + ApParams.RelatedDataBlock = (VOID *) PlatformConfig; + ApParams.RelatedBlockLength = sizeof (PLATFORM_CONFIGURATION); + RunLateApTaskOnAllAPs (&ApParams, StdHeader); + CpuLateInitApTask (&ApParams); + } + DisableCf8ExtCfg (StdHeader); + return (AGESA_SUCCESS); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * CpuLateInitApTask + * + * Description: + * This is the last function run on all APs + * + * Parameters: + * @param[in] ApExeParams Handle to config for library and services. + * + * @retval AGESA_STATUS + * + * Processing: + * + */ +AGESA_STATUS +CpuLateInitApTask ( + IN AP_EXE_PARAMS *ApExeParams + ) +{ + UINT64 LocalMsrRegister; + PLATFORM_CONFIGURATION *PlatformConfig; + BOOLEAN CuCfg3Exist; + + PlatformConfig = (PLATFORM_CONFIGURATION *) ApExeParams->RelatedDataBlock; + // The processor that has compute unit has CU_CFG3 MSR + switch (GetComputeUnitMapping (&(ApExeParams->StdHeader))) { + case AllCoresMapping: + CuCfg3Exist = FALSE; + break; + case EvenCoresMapping: + CuCfg3Exist = TRUE; + break; + default: + CuCfg3Exist = FALSE; + } + + // DISABLE_HARDWARE_PREFETCH + if (PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.HardwarePrefetchMode == DISABLE_HARDWARE_PREFETCH) { + // DC_CFG (MSR_C001_1022) + // [13] = 1 + // [15] = 1 + LibAmdMsrRead (MSR_DC_CFG, &LocalMsrRegister, &(ApExeParams->StdHeader)); + LocalMsrRegister |= (BIT13 | BIT15); + LibAmdMsrWrite (MSR_DC_CFG, &LocalMsrRegister, &(ApExeParams->StdHeader)); + // CU_CFG3 (MSR_C001_102B) + // [3] = 1 + // [16] = 1 + // [17] = 1 + // [18] = 1 + if ((CuCfg3Exist) && (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, &(ApExeParams->StdHeader)))) { + LibAmdMsrRead (MSR_CU_CFG3, &LocalMsrRegister, &(ApExeParams->StdHeader)); + LocalMsrRegister |= (BIT3 | BIT16 | BIT17 | BIT18); + LibAmdMsrWrite (MSR_CU_CFG3, &LocalMsrRegister, &(ApExeParams->StdHeader)); + } + } + + // DISABLE_L1_PREFETCHER + if ((PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.HardwarePrefetchMode == DISABLE_L1_PREFETCHER) || + (PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.HardwarePrefetchMode == DISABLE_L1_PREFETCHER_AND_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES )) { + // CU_CFG3 (MSR_C001_102B) + // [3] = 1 + if ((CuCfg3Exist) && (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, &(ApExeParams->StdHeader)))) { + LibAmdMsrRead (MSR_CU_CFG3, &LocalMsrRegister, &(ApExeParams->StdHeader)); + LocalMsrRegister |= BIT3; + LibAmdMsrWrite (MSR_CU_CFG3, &LocalMsrRegister, &(ApExeParams->StdHeader)); + } + + } + + // DISABLE_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES + if ((PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.HardwarePrefetchMode == DISABLE_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES ) || + (PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.HardwarePrefetchMode == DISABLE_L1_PREFETCHER_AND_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES )) { + // DC_CFG (MSR_C001_1022) + // [15] = 1 + LibAmdMsrRead (MSR_DC_CFG, &LocalMsrRegister, &(ApExeParams->StdHeader)); + LocalMsrRegister |= BIT15; + LibAmdMsrWrite (MSR_DC_CFG, &LocalMsrRegister, &(ApExeParams->StdHeader)); + + } + + // DISABLE_SOFTWARE_PREFETCHES + if (PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.SoftwarePrefetchMode == DISABLE_SOFTWARE_PREFETCHES) { + // MSR_DE_CFG (MSR_C001_1029) + // [7:2] = 0x3F + if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, &(ApExeParams->StdHeader))) { + LibAmdMsrRead (MSR_DE_CFG, &LocalMsrRegister, &(ApExeParams->StdHeader)); + LocalMsrRegister |= 0xFC; + LibAmdMsrWrite (MSR_DE_CFG, &LocalMsrRegister, &(ApExeParams->StdHeader)); + } + } + + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Clear EnableCf8ExtCfg on all socket + * + * Clear F3x8C bit 14 EnableCf8ExtCfg + * + * @param[in] StdHeader Config handle for library and services + * + * + */ +VOID +DisableCf8ExtCfg ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + PCI_ADDR PciAddress; + UINT32 Socket; + UINT32 Module; + UINT32 PciData; + UINT32 LegacyPciAccess; + + ASSERT (IsBsp (StdHeader, &AgesaStatus)); + + for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { + for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { + if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) { + PciAddress.Address.Function = FUNC_3; + PciAddress.Address.Register = NB_CFG_HIGH_REG; + LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8))); + // read from PCI register + LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader); + LibAmdIoRead (AccessWidth32, IOCFC, &PciData, StdHeader); + // Disable Cf8ExtCfg + PciData &= 0xFFFFBFFF; + // write to PCI register + LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader); + LibAmdIoWrite (AccessWidth32, IOCFC, &PciData, StdHeader); + } + } + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Calculate an ACPI style checksum + * + * Computes the checksum and stores the value to the checksum + * field of the passed in ACPI table's header. + * + * @param[in] Table ACPI table to checksum + * @param[in] StdHeader Config handle for library and services + * + */ +VOID +ChecksumAcpiTable ( + IN OUT ACPI_TABLE_HEADER *Table, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 *BuffTempPtr; + UINT8 Checksum; + UINT32 BufferOffset; + + Table->Checksum = 0; + Checksum = 0; + BuffTempPtr = (UINT8 *) Table; + for (BufferOffset = 0; BufferOffset < Table->TableLength; BufferOffset++) { + Checksum = Checksum - *(BuffTempPtr + BufferOffset); + } + + Table->Checksum = Checksum; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * + * Run code on every AP in the system. + * + * @param[in] ApParams AP task pointer. + * @param[in] StdHeader Handle to config for library and services + * + * @return The most severe AGESA_STATUS returned by an AP. + * + */ +AGESA_STATUS +RunLateApTaskOnAllAPs ( + IN AP_EXE_PARAMS *ApParams, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 NumberOfSockets; + UINT32 NumberOfCores; + UINT8 Socket; + UINT8 Core; + UINT8 ApicId; + UINT32 BscSocket; + UINT32 Ignored; + UINT32 BscCoreNum; + AGESA_STATUS CalledStatus; + AGESA_STATUS IgnoredStatus; + AGESA_STATUS AgesaStatus; + + ASSERT (IsBsp (StdHeader, &IgnoredStatus)); + + AgesaStatus = AGESA_SUCCESS; + + IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredStatus); + NumberOfSockets = GetPlatformNumberOfSockets (); + + for (Socket = 0; Socket < NumberOfSockets; Socket++) { + if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { + for (Core = 0; Core < NumberOfCores; Core++) { + if ((Socket != BscSocket) || (Core != BscCoreNum)) { + GetApicId (StdHeader, Socket, Core, &ApicId, &IgnoredStatus); + AGESA_TESTPOINT (TpIfBeforeRunApFromAllAps, StdHeader); + CalledStatus = AgesaRunFcnOnAp ((UINTN) ApicId, ApParams); + AGESA_TESTPOINT (TpIfAfterRunApFromAllAps, StdHeader); + if (CalledStatus > AgesaStatus) { + AgesaStatus = CalledStatus; + } + } + } + } + } + return AgesaStatus; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * + * Run code on core 0 of every socket in the system. + * + * @param[in] ApParams AP task pointer. + * @param[in] StdHeader Handle to config for library and services + * + * @return The most severe AGESA_STATUS returned by an AP. + * + */ +AGESA_STATUS +RunLateApTaskOnAllCore0s ( + IN AP_EXE_PARAMS *ApParams, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 NumberOfSockets; + UINT8 Socket; + UINT8 ApicId; + UINT32 BscSocket; + UINT32 IgnoredModule; + UINT32 IgnoredCore; + AGESA_STATUS CalledStatus; + AGESA_STATUS IgnoredStatus; + AGESA_STATUS AgesaStatus; + + ASSERT (IsBsp (StdHeader, &IgnoredStatus)); + + AgesaStatus = AGESA_SUCCESS; + + IdentifyCore (StdHeader, &BscSocket, &IgnoredModule, &IgnoredCore, &IgnoredStatus); + NumberOfSockets = GetPlatformNumberOfSockets (); + + for (Socket = 0; Socket < NumberOfSockets; Socket++) { + if (IsProcessorPresent (Socket, StdHeader)) { + if (Socket != BscSocket) { + GetApicId (StdHeader, Socket, 0, &ApicId, &IgnoredStatus); + AGESA_TESTPOINT (TpIfBeforeRunApFromAllCore0s, StdHeader); + CalledStatus = AgesaRunFcnOnAp ((UINTN) ApicId, ApParams); + AGESA_TESTPOINT (TpIfAfterRunApFromAllCore0s, StdHeader); + if (CalledStatus > AgesaStatus) { + AgesaStatus = CalledStatus; + } + } + } + } + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.h new file mode 100644 index 0000000..59d396d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.h @@ -0,0 +1,1160 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Late Init API functions Prototypes. + * + * Contains code for doing any late CPU initialization + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 64351 $ @e $Date: 2012-01-19 03:50:41 -0600 (Thu, 19 Jan 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_LATE_INIT_H_ +#define _CPU_LATE_INIT_H_ + +#include "Filecode.h" + +// Forward declaration needed for multi-structure mutual references. +AGESA_FORWARD_DECLARATION (PROC_FAMILY_TABLE); +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +CpuLateInitApTask ( + IN AP_EXE_PARAMS *ApExeParams + ); + +#define AP_LATE_TASK_CPU_LATE_INIT (PROC_CPU_CPULATEINIT_FILECODE) +#define CPU_LATE_INIT_AP_TASK {AP_LATE_TASK_CPU_LATE_INIT, (IMAGE_ENTRY) CpuLateInitApTask}, + +//---------------------------------------------------------------------------- +// DMI DEFINITIONS AND MACROS +// +//---------------------------------------------------------------------------- +#define AP_LATE_TASK_GET_TYPE4_TYPE7 (PROC_CPU_FEATURE_CPUDMI_FILECODE) +// SMBIOS constant definition +#define CENTRAL_PROCESSOR 0x03 +#define EXTERNAL_CLOCK_DFLT 200 +#define EXTERNAL_CLOCK_100MHZ 100 +#define P_FAMILY_UNKNOWN 0x02 +#define P_ENGINEERING_SAMPLE 0x00 +#define P_CHARACTERISTICS 0x4 +#define CACHE_CFG_L1 0x180 +#define CACHE_CFG_L2 0x181 +#define CACHE_CFG_L3 0x182 +#define SRAM_TYPE 0x10 +#define ERR_CORRECT_TYPE 0x06 +#define CACHE_TYPE 0x05 +#define DMI_ASSOCIATIVE_OTHER 0x01 +#define DMI_ASSOCIATIVE_UNKNOWN 0x02 +#define DMI_ASSOCIATIVE_DIRECT_MAPPED 0x03 +#define DMI_ASSOCIATIVE_2_WAY 0x04 +#define DMI_ASSOCIATIVE_4_WAY 0x05 +#define DMI_ASSOCIATIVE_FULLY 0x06 +#define DMI_ASSOCIATIVE_8_WAY 0x07 +#define DMI_ASSOCIATIVE_16_WAY 0x08 +#define DMI_ASSOCIATIVE_12_WAY 0x09 +#define DMI_ASSOCIATIVE_24_WAY 0x0A +#define DMI_ASSOCIATIVE_32_WAY 0x0B +#define DMI_ASSOCIATIVE_48_WAY 0x0C +#define DMI_ASSOCIATIVE_64_WAY 0x0D +#define DMI_ASSOCIATIVE_20_WAY 0x0E +#define SOCKET_POPULATED 0x40 +#define CPU_STATUS_UNKNOWN 0x00 +#define CPU_STATUS_ENABLED 0x01 + +// Processor Upgrade Definition +#define P_UPGRADE_UNKNOWN 0x02 +#define P_UPGRADE_NONE 0x06 +#define P_UPGRADE_S1GX 0x16 +#define P_UPGRADE_AM2 0x17 +#define P_UPGRADE_F1207 0x18 +#define P_UPGRADE_G34 0x1A +#define P_UPGRADE_AM3 0x1B +#define P_UPGRADE_C32 0x1C +#define P_UPGRADE_FS1 0x27 +#define P_UPGRADE_FM1 0x29 +#define P_UPGRADE_FM2 0x2A + +//---------------------------------------------------------------------------- +// SRAT DEFINITIONS AND MACROS +// +//---------------------------------------------------------------------------- +#define NorthbridgeCapabilities 0xE8 +#define DRAMBase0 0x40 +#define MMIOBase0 0x80 +#define TOP_MEM 0xC001001Aul +#define LOW_NODE_DEVICEID 24 +#define LOW_APICID 0 + + +// Miscellaneous AMD related values +#define MAX_NUMBER_NODES 8 + +// Flags +#define ENABLED 1 // Bit 0 +#define DISABLED 0 // Bit 0 +#define HOTPLUGGABLE 2 // Bit 1 + +// Affinity Entry Structures +#define AE_APIC 0 +#define AE_MEMORY 1 + + +// Memory Types +#define TYPE_MEMORY 1 +#define TYPE_RESERVED 2 +#define TYPE_ACPI 3 +#define TYPE_NVS 4 + +//---------------------------------------------------------------------------- +// SLIT DEFINITIONS AND MACROS +// +//---------------------------------------------------------------------------- +#define PROBE_FILTER_CTRL_REG 0x1D4 +#define AMD_ACPI_SLIT_SOCKET_NUM_LENGTH 8 + +//---------------------------------------------------------------------------- +// CDIT DEFINITIONS AND MACROS +// +//---------------------------------------------------------------------------- +#define AMD_ACPI_CDIT_NUM_DOMAINS_LENGTH 4 // Num domains is a 4-bytes unsigned integer + + +//---------------------------------------------------------------------------- +// P-STATE DEFINITIONS AND MACROS +// +//---------------------------------------------------------------------------- +//------------------------------------- +// ERROR Codes +//------------------------------------- +#define NO_ERROR 0x0 +#define USER_DISABLE_ERROR 0x01 // User disabled SSDT generation +#define CORES_MISSMATCH_PSS_ERROR 0x02 // No PSS match +#define PNOW_SUPPORT_ERROR 0x04 // One of the Cores do not support PNOW! +#define PWR_FREQ_MATCH_ERROR 0x08 // FREQ and PWR mismatch +#define NO_PSS_SIZE_ERROR 0x10 // Error in PSS Size +#define INVALID_PSTATE_ERROR 0x20 // Invalid Max or only 1 P-State available +#define NO_PSS_ENTRY 0x0FFFFul +#define INVALID_FREQ 0x0FFFFFFFFul + +//------------------------- +// Default definitions +// AMD BKDG default values +//------------------------- +#define DEFAULT_ISOCH_RELIEF_TIME IRT_80uS +#define DEFAULT_RAMP_VOLTAGE_OFFSET RVO_50mV +#define DEFAULT_MAX_VOLTAGE_STEP MVS_25mV +#define DEFAULT_PERF_PRESENT_CAP 0 // default for Desktop +#define DEFAULT_VOLTAGE_STABLE_TIME (100 / 20) // 100uS +#define DEFAULT_PLL_LOCK_TIME 2 // 2uS +#define DEFAULT_TRANSITION_LATENCY 100 // 100uS +#define DEFAULT_BUS_MASTER_LATENCY 9 // 9uS +#define DEFAULT_CPU_SCOPE_NUMBER "0UPC" + +// Defines for Common ACPI +// ----------------------------- +#define SCOPE_OPCODE 0x10 +#define NAME_OPCODE 0x08 +#define METHOD_OPCODE 0x14 +#define PACKAGE_OPCODE 0x12 +#define BUFFER_OPCODE 0x11 +#define BYTE_PREFIX_OPCODE 0x0A +#define WORD_PREFIX_OPCODE 0x0B +#define DWORD_PREFIX_OPCODE 0x0C +#define RETURN_OPCODE 0xA4 +#define ACPI_BUFFER 0x080A0B11ul + +// Generic Register Descriptor (GDR) Fields +#define GDR_ASI_SYSTEM_IO 0x01 // Address Space ID +#define GDR_ASZ_BYTE_ACCESS 0x01 // Address Size + +// Defines for ACPI Scope Table +// ---------------------------- +#define SCOPE_LENGTH (SCOPE_STRUCT_SIZE + \ + PCT_STRUCT_SIZE + \ + PSS_HEADER_STRUCT_SIZE + \ + PSS_BODY_STRUCT_SIZE + \ + PPC_HEADER_BODY_STRUCT_SIZE) +#define SCOPE_VALUE1 0x5C +#define SCOPE_VALUE2 0x2E +#define SCOPE_NAME__ '_' +#define SCOPE_NAME_P 'P' +#define SCOPE_NAME_R 'R' +#define SCOPE_NAME_S 'S' +#define SCOPE_NAME_B 'B' +#define SCOPE_NAME_C 'C' +#define SCOPE_NAME_U 'U' +#define SCOPE_NAME_0 '0' +#define SCOPE_NAME_1 '1' +#define SCOPE_NAME_2 '2' +#define SCOPE_NAME_3 '3' +#define SCOPE_NAME_A 'A' + +#ifdef OEM_SCOPE_NAME + #if (OEM_SCOPE_NAME > 'Z') || (OEM_SCOPE_NAME < 'A') + #error "OEM_SCOPE_NAME: it should be only one char long AND a valid letter (A~Z)" + #endif + #define SCOPE_NAME_VALUE OEM_SCOPE_NAME +#else + #define SCOPE_NAME_VALUE SCOPE_NAME_C +#endif // OEM_SCOPE_NAME + +#ifdef OEM_SCOPE_NAME1 + #if (!(((OEM_SCOPE_NAME1 >= 'A') && (OEM_SCOPE_NAME1 <= 'Z')) || \ + ((OEM_SCOPE_NAME1 >= '0') && (OEM_SCOPE_NAME1 <= '9')) || \ + (OEM_SCOPE_NAME1 == '_'))) + #error "OEM_SCOPE_NAME1: it should be only one char long AND a valid letter (0~9, A~F)" + #endif + #define SCOPE_NAME_VALUE1 OEM_SCOPE_NAME1 +#else + #define SCOPE_NAME_VALUE1 SCOPE_NAME_0 +#endif // OEM_SCOPE_NAME + +// Defines for PCT Control and Status Table +// ---------------------------------------- +#define PCT_NAME__ '_' +#define PCT_NAME_P 'P' +#define PCT_NAME_C 'C' +#define PCT_NAME_T 'T' +#define PCT_VALUE1 0x11022C12ul +#define PCT_VALUE2 0x0A14 +#define PCT_VALUE3 0x11 +#define GENERIC_REG_DESCRIPTION 0x82 +#define PCT_LENGTH 0x0C +#define PCT_ADDRESS_SPACE_ID 0x7F +#define PCT_REGISTER_BIT_WIDTH 0x40 +#define PCT_REGISTER_BIT_OFFSET 0x00 +#define PCT_RESERVED 0x00 +#define PCT_CONTROL_REG_LO 0xC0010062ul +#define PCT_CONTROL_REG_HI 0x00 +#define PCT_VALUE4 0x14110079ul +#define PCT_VALUE5 0x110A +#define PCT_STATUS_REG_LO 0x00 +#define PCT_STATUS_REG_HI 0x00 +#define PCT_VALUE6 0x0079 + + +// Defines for PSS Header Table +// ---------------------------- +#define PSS_NAME__ '_' +#define PSS_NAME_X 'X' +#define PSS_NAME_P 'P' +#define PSS_NAME_S 'S' +#define PSS_LENGTH (sizeof pssBodyStruct + 3) +#define NUM_OF_ITEMS_IN_PSS 0x00 + + +// Defines for PSS Header Table +// ---------------------------- +#define PSS_PKG_LENGTH 0x20 // PSS_BODY_STRUCT_SIZE - 1 +#define PSS_NUM_OF_ELEMENTS 0x06 +#define PSS_FREQUENCY 0x00 +#define PSS_POWER 0x00 +#define PSS_TRANSITION_LATENCY DEFAULT_TRANSITION_LATENCY +#define PSS_BUS_MASTER_LATENCY DEFAULT_BUS_MASTER_LATENCY +#define PSS_CONTROL ((DEFAULT_ISOCH_RELIEF_TIME << 30) + \ + (DEFAULT_RAMP_VOLTAGE_OFFSET << 28) + \ + (DEFAULT_EXT_TYPE << 27) + \ + (DEFAULT_PLL_LOCK_TIME << 20) + \ + (DEFAULT_MAX_VOLTAGE_STEP << 18) + \ + (DEFAULT_VOLTAGE_STABLE_TIME << 11) + \ + (PSS_VID << 6) + PSS_FID) +#define PSS_STATUS (DEFAULT_EXTENDED_TYPE << 11) + (PSS_VID << 6) + (PSS_FID) + +// Defines for XPSS Header Table +// ---------------------------- +#define XPSS_PKG_LENGTH 0x47 // XPSS_BODY_STRUCT_SIZE - 1 +#define XPSS_NUM_OF_ELEMENTS 0x08 +#define XPSS_ACPI_BUFFER 0x080A0B11ul + + +// Defines for PPC Header Table +// ---------------------------- +#define PPC_NAME__ '_' +#define PPC_NAME_P 'P' +#define PPC_NAME_C 'C' +#define PPC_NAME_V 'V' +#define PPC_METHOD_FLAGS 0x00; +#define PPC_VALUE1 0x0A; + +// Defines for PSD Header Table +// ---------------------------- +#define PSD_NAME__ '_' +#define PSD_NAME_P 'P' +#define PSD_NAME_S 'S' +#define PSD_NAME_D 'D' +#define PSD_HEADER_LENGTH (PSD_BODY_STRUCT_SIZE + 2) +#define PSD_VALUE1 0x01 + + +// Defines for PSD Header Table +// ---------------------------- +#define PSD_PKG_LENGTH (PSD_BODY_STRUCT_SIZE - 1) +#define NUM_OF_ENTRIES 0x05 +#define PSD_NUM_OF_ENTRIES 0x05 +#define PSD_REVISION 0x00 +#define PSD_DEPENDENCY_DOMAIN 0x00 +#define PSD_COORDINATION_TYPE_HW_ALL 0xFE +#define PSD_COORDINATION_TYPE_SW_ANY 0xFD +#define PSD_COORDINATION_TYPE_SW_ALL 0xFC +#define PSD_NUM_OF_PROCESSORS 0x01 +#define PSD_CORE_NUM_PER_COMPUTE_UNIT 0x02 +#define PSD_DOMAIN_COMPUTE_UNIT_MASK 0x7F + + +#define CUSTOM_PSTATE_FLAG 0x55 +#define PSTATE_FLAG_1 0x55 +#define TARGET_PSTATE_FLAG 0xAA +#define PSTATE_FLAG_2 0xAA + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *---------------------------------------------------------------------------------------- + */ +//---------------------------------------------------------------------------- +// ACPI P-States AML TYPEDEFS, STRUCTURES, ENUMS +// +//---------------------------------------------------------------------------- + +//-------------------------------------------- +// AML code definition +// (Scope) +//--------------------------------------------- +/// SCOPE +typedef struct _SCOPE { + UINT8 ScopeOpcode; ///< Opcode + UINT16 ScopeLength; ///< Scope Length + UINT8 ScopeValue1; ///< Value1 + UINT8 ScopeValue2; ///< Value2 + UINT8 ScopeNamePt1a__; ///< Name Pointer + UINT8 ScopeNamePt1a_P; ///< Name Pointer + UINT8 ScopeNamePt1a_R; ///< Name Pointer + UINT8 ScopeNamePt1b__; ///< Name Pointer + UINT8 ScopeNamePt2a_C; ///< Name Pointer + UINT8 ScopeNamePt2a_P; ///< Name Pointer + UINT8 ScopeNamePt2a_U; ///< Name Pointer + UINT8 ScopeNamePt2a_0; ///< Name Pointer +} SCOPE; +#define SCOPE_STRUCT_SIZE 13 // 13 Bytes + +//-------------------------------------------- +// AML code definition +// (PCT Header and Body) +//--------------------------------------------- + +///Performance Control Header +typedef struct _PCT_HEADER_BODY { + UINT8 NameOpcode; ///< Opcode + UINT8 PctName_a__; ///< String "_" + UINT8 PctName_a_P; ///< String "P" + UINT8 PctName_a_C; ///< String "C" + UINT8 PctName_a_T; ///< String "T" + UINT32 Value1; ///< Value1 + UINT16 Value2; ///< Value2 + UINT8 Value3; ///< Value3 + UINT8 GenericRegDescription1; ///< Generic Reg Description + UINT16 Length1; ///< Length1 + UINT8 AddressSpaceId1; ///< PCT Address Space ID + UINT8 RegisterBitWidth1; ///< PCT Register Bit Width + UINT8 RegisterBitOffset1; ///< PCT Register Bit Offset + UINT8 Reserved1; ///< Reserved + UINT32 ControlRegAddressLo; ///< Control Register Address Low + UINT32 ControlRegAddressHi; ///< Control Register Address High + UINT32 Value4; ///< Value4 + UINT16 Value5; ///< Value 5 + UINT8 GenericRegDescription2; ///< Generic Reg Description + UINT16 Length2; ///< Length2 + UINT8 AddressSpaceId2; ///< PCT Address Space ID + UINT8 RegisterBitWidth2; ///< PCT Register Bit Width + UINT8 RegisterBitOffset2; ///< PCT Register Bit Offset + UINT8 Reserved2; ///< Reserved + UINT32 StatusRegAddressLo; ///< Control Register Address Low + UINT32 StatusRegAddressHi; ///< Control Register Address High + UINT16 Value6; ///< Values +} PCT_HEADER_BODY; +#define PCT_STRUCT_SIZE 50 // 50 Bytes + + +//-------------------------------------------- +// AML code definition +// (PSS Header) +//-------------------------------------------- +///Performance Supported States Header +typedef struct _PSS_HEADER { + UINT8 NameOpcode; ///< Opcode + UINT8 PssName_a__; ///< String "_" + UINT8 PssName_a_P; ///< String "P" + UINT8 PssName_a_S; ///< String "S" + UINT8 PssName_b_S; ///< String "S" + UINT8 PkgOpcode; ///< Package Opcode + UINT16 PssLength; ///< PSS Length + UINT8 NumOfItemsInPss; ///< Number of Items in PSS +} PSS_HEADER; +#define PSS_HEADER_STRUCT_SIZE 9 // 9 Bytes + + +//-------------------------------------------- +// AML code definition +// (PSS Body) +//-------------------------------------------- +///Performance Supported States Body +typedef struct _PSS_BODY { + UINT8 PkgOpcode; ///< Package Opcode + UINT8 PkgLength; ///< Package Length + UINT8 NumOfElements; ///< Number of Elements + UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1 + UINT32 Frequency; ///< Frequency + UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2 + UINT32 Power; ///< Power + UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3 + UINT32 TransitionLatency; ///< Transition Latency + UINT8 DwordPrefixOpcode4; ///< Prefix Opcode4 + UINT32 BusMasterLatency; ///< Bus Master Latency + UINT8 DwordPrefixOpcode5; ///< Prefix Opcode5 + UINT32 Control; ///< Control + UINT8 DwordPrefixOpcode6; ///< Prefix Opcode6 + UINT32 Status; ///< Status +} PSS_BODY; +#define PSS_BODY_STRUCT_SIZE 33 // 33 Bytes + + +/*-------------------------------------------- + * AML code definition + * (XPSS Header) + *-------------------------------------------- + */ +/// Extended PSS Header +typedef struct _XPSS_HEADER { + UINT8 NameOpcode; ///< 08h + UINT8 XpssName_a_X; ///< String "X" + UINT8 XpssName_a_P; ///< String "P" + UINT8 XpssName_a_S; ///< String "S" + UINT8 XpssName_b_S; ///< String "S" + UINT8 PkgOpcode; ///< 12h + UINT16 XpssLength; ///< XPSS Length + UINT8 NumOfItemsInXpss; ///< Number of Items in XPSS +} XPSS_HEADER; +#define XPSS_HEADER_STRUCT_SIZE 9 // 9 Bytes + +/*-------------------------------------------- + * AML code definition + * (XPSS Body) + *-------------------------------------------- + */ +/// Extended PSS Body +typedef struct _XPSS_BODY { + UINT8 PkgOpcode; ///< 12h + UINT8 PkgLength; ///< Package Length + UINT8 XpssValueTbd; ///< XPSS Value + UINT8 NumOfElements; ///< Number of Elements + UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1 + UINT32 Frequency; ///< Frequency + UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2 + UINT32 Power; ///< Power + UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3 + UINT32 TransitionLatency; ///< Transition Latency + UINT8 DwordPrefixOpcode4; ///< Prefix Opcode4 + UINT32 BusMasterLatency; ///< Bus Master Latency + UINT32 ControlBuffer; ///< Control Buffer + UINT32 ControlLo; ///< Control Low + UINT32 ControlHi; ///< Control High + UINT32 StatusBuffer; ///< Status Buffer + UINT32 StatusLo; ///< Status Low + UINT32 StatusHi; ///< Status High + UINT32 ControlMaskBuffer; ///< Control Mask Buffer + UINT32 ControlMaskLo; ///< Control Mask Low + UINT32 ControlMaskHi; ///< Control Mask High + UINT32 StatusMaskBuffer; ///< Status Mask Buffer + UINT32 StatusMaskLo; ///< Status Mask Low + UINT32 StatusMaskHi; ///< Status Mask High +} XPSS_BODY; +#define XPSS_BODY_STRUCT_SIZE 72 // 72 Bytes + +/*-------------------------------------------- + * AML code definition + * (PPC Header and Body) + *-------------------------------------------- + */ +/// Performance Present Capabilities Header +typedef struct _PPC_HEADER_BODY { + UINT8 NameOpcode; ///< Name Opcode + UINT8 PpcName_a_P; ///< String "P" + UINT8 PpcName_b_P; ///< String "P" + UINT8 PpcName_a_C; ///< String "C" + UINT8 PpcName_a_V; ///< String "V" + UINT8 Value1; ///< Value + UINT8 DefaultPerfPresentCap; ///< Default Perf Present Cap + UINT8 MethodOpcode; ///< Method Opcode + UINT8 PpcLength; ///< Method Length + UINT8 PpcName_a__; ///< String "_" + UINT8 PpcName_c_P; ///< String "P" + UINT8 PpcName_d_P; ///< String "P" + UINT8 PpcName_b_C; ///< String "C" + UINT8 MethodFlags; ///< Method Flags + UINT8 ReturnOpcode; ///< Return Opcoce + UINT8 PpcName_e_P; ///< String "P" + UINT8 PpcName_f_P; ///< String "P" + UINT8 PpcName_c_C; ///< String "C" + UINT8 PpcName_b_V; ///< String "V" + +} PPC_HEADER_BODY; +#define PPC_HEADER_BODY_STRUCT_SIZE 19 // 19 Bytes +#define PPC_METHOD_LENGTH 11 // 11 Bytes + + +/*-------------------------------------------- + * AML code definition + * (PSD Header) + *-------------------------------------------- + */ +/// P-State Dependency Header +typedef struct _PSD_HEADER { + UINT8 NameOpcode; ///< Name Opcode + UINT8 PsdName_a__; ///< String "_" + UINT8 PsdName_a_P; ///< String "P" + UINT8 PsdName_a_S; ///< String "S" + UINT8 PsdName_a_D; ///< String "D" + UINT8 PkgOpcode; ///< Package Opcode + UINT8 PsdLength; ///< PSD Length + UINT8 Value1; ///< Value +} PSD_HEADER; +#define PSD_HEADER_STRUCT_SIZE 8 // 8 Bytes + +/*-------------------------------------------- + * AML code definition + * (PSD Body) + *-------------------------------------------- + */ +/// P-State Dependency Body +typedef struct _PSD_BODY { + UINT8 PkgOpcode; ///< Package Opcode + UINT8 PkgLength; ///< Package Length + UINT8 NumOfEntries; ///< Number of Entries + UINT8 BytePrefixOpcode1; ///< Prefix Opcode1 in Byte + UINT8 PsdNumOfEntries; ///< PSD Number of Entries + UINT8 BytePrefixOpcode2; ///< Prefix Opcode2 in Byte + UINT8 PsdRevision; ///< PSD Revision + UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1 in DWord + UINT32 DependencyDomain; ///< Dependency Domain + UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2 in DWord + UINT32 CoordinationType; ///< (0xFC = SW_ALL, 0xFD = SW_ANY, 0xFE = HW_ALL) + UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3 in DWord + UINT32 NumOfProcessors; ///< Number of Processors +} PSD_BODY; +#define PSD_BODY_STRUCT_SIZE 22 // 22 Bytes + +//---------------------------------------------------------------------------- +// WHEA TYPEDEFS, STRUCTURES, ENUMS +// +//---------------------------------------------------------------------------- + +/// HEST MCE TABLE +typedef struct _AMD_HEST_MCE_TABLE { + UINT16 TblLength; ///< Length, in bytes, of entire AMD_HEST_MCE structure. + UINT32 GlobCapInitDataLSD; ///< Holds the value that the OS will program into + UINT32 GlobCapInitDataMSD; ///< the machine check global capability register(MCG_CAP). + UINT32 GlobCtrlInitDataLSD; ///< Holds the value that the OS will program into + UINT32 GlobCtrlInitDataMSD; ///< the machine check global control register(MCG_CTL). + UINT8 NumHWBanks; ///< The number of hardware error reporting banks. + UINT8 Rsvd[7]; ///< reserve 7 bytes as spec's required +} AMD_HEST_MCE_TABLE; + +/// HEST CMC TABLE +typedef struct _AMD_HEST_CMC_TABLE { + UINT16 TblLength; ///< Length, in bytes, of entire AMD_HEST_CMC structure. + UINT8 NumHWBanks; ///< The number of hardware error reporting banks. + UINT8 Rsvd[3]; ///< reserve 3 bytes as spec's required +} AMD_HEST_CMC_TABLE; + +/// HEST BANK +typedef struct _AMD_HEST_BANK { + UINT8 BankNum; ///< Zero-based index identifies the machine check error bank. + UINT8 ClrStatusOnInit; ///< Indicates if the status information in this machine check bank + ///< is to be cleared during system initialization. + UINT8 StatusDataFormat; ///< Indicates the format of the data in the status register + UINT8 ConfWriteEn; ///< This field indicates whether configuration parameters may be + ///< modified by the OS. If the bit for the associated parameter is + ///< set, the parameter is writable by the OS. + UINT32 CtrlRegMSRAddr; ///< Address of the hardware bank's control MSR. Ignored if zero. + + UINT32 CtrlInitDataLSD; ///< This is the value the OS will program into the machine check + UINT32 CtrlInitDataMSD; ///< bank's control register + UINT32 StatRegMSRAddr; ///< Address of the hardware bank's MCi_STAT MSR. Ignored if zero. + UINT32 AddrRegMSRAddr; ///< Address of the hardware bank's MCi_ADDR MSR. Ignored if zero. + UINT32 MiscRegMSRAddr; ///< Address of the hardware bank's MCi_MISC MSR. Ignored if zero. +} AMD_HEST_BANK; + +/// Initial data of AMD_HEST_BANK +typedef struct _AMD_HEST_BANK_INIT_DATA { + UINT32 CtrlInitDataLSD; ///< Initial data of CtrlInitDataLSD + UINT32 CtrlInitDataMSD; ///< Initial data of CtrlInitDataMSD + UINT32 CtrlRegMSRAddr; ///< Initial data of CtrlRegMSRAddr + UINT32 StatRegMSRAddr; ///< Initial data of StatRegMSRAddr + UINT32 AddrRegMSRAddr; ///< Initial data of AddrRegMSRAddr + UINT32 MiscRegMSRAddr; ///< Initial data of MiscRegMSRAddr +} AMD_HEST_BANK_INIT_DATA; + +/// MSR179 Global Machine Check Capabilities data struct +typedef struct _MSR_MCG_CAP_STRUCT { + UINT64 Count:8; ///< Indicates the number of + ///< error-reporting banks visible to each core + UINT64 McgCtlP:1; ///< 1=The machine check control registers + UINT64 Rsvd:55; ///< reserved +} MSR_MCG_CAP_STRUCT; + +/// Initial data of WHEA +typedef struct _AMD_WHEA_INIT_DATA { + UINT32 GlobCapInitDataLSD; ///< Holds the value that the OS will program into the machine + UINT32 GlobCapInitDataMSD; ///< Check global capability register + UINT32 GlobCtrlInitDataLSD; ///< Holds the value that the OS will grogram into the machine + UINT32 GlobCtrlInitDataMSD; ///< Check global control register + UINT8 ClrStatusOnInit; ///< Indicates if the status information in this machine check + ///< bank is to be cleared during system initialization + UINT8 StatusDataFormat; ///< Indicates the format of the data in the status register + UINT8 ConfWriteEn; ///< This field indicates whether configuration parameters may be + ///< modified by the OS. If the bit for the associated parameter is + ///< set, the parameter is writable by the OS. + UINT8 HestBankNum; ///< Number of HEST Bank + AMD_HEST_BANK_INIT_DATA *HestBankInitData; ///< Pointer to Initial data of HEST Bank +} AMD_WHEA_INIT_DATA; + +//---------------------------------------------------------------------------- +// DMI TYPEDEFS, STRUCTURES, ENUMS +// +//---------------------------------------------------------------------------- +/// DMI brand information +typedef struct { + UINT16 String1:4; ///< String1 + UINT16 String2:4; ///< String2 + UINT16 Model:7; ///< Model + UINT16 Pg:1; ///< Page +} BRAND_ID; + +/// DMI cache information +typedef struct { + UINT32 L1CacheSize; ///< L1 cache size + UINT8 L1CacheAssoc; ///< L1 cache associativity + UINT32 L2CacheSize; ///< L2 cache size + UINT8 L2CacheAssoc; ///< L2 cache associativity + UINT32 L3CacheSize; ///< L3 cache size + UINT8 L3CacheAssoc; ///< L3 cache associativity +} CPU_CACHE_INFO; + +/// DMI processor information +typedef struct { + UINT8 ExtendedFamily; ///< Extended Family + UINT8 ExtendedModel; ///< Extended Model + UINT8 BaseFamily; ///< Base Family + UINT8 BaseModel; ///< Base Model + UINT8 Stepping; ///< Stepping + UINT8 PackageType; ///< PackageType + BRAND_ID BrandId; ///< BrandId which contains information about String1, String2, Model and Page + UINT8 TotalCoreNumber; ///< Number of total cores + UINT8 EnabledCoreNumber; ///< Number of enabled cores + UINT8 ProcUpgrade; ///< ProcUpdrade + CPU_CACHE_INFO CacheInfo; ///< CPU cache info +} CPU_TYPE_INFO; + +/// A structure containing processor name string and +/// the value that should be provide to DMI type 4 processor family +typedef struct { + IN CONST CHAR8 *Stringstart; ///< The literal string + IN UINT8 T4ProcFamilySetting; ///< The value set to DMI type 4 processor family +} CPU_T4_PROC_FAMILY; + +/// DMI ECC information +typedef struct { + BOOLEAN EccCapable; ///< ECC Capable +} CPU_GET_MEM_INFO; + +/* Transfer vectors for DMI family specific routines */ +typedef VOID OPTION_DMI_GET_CPU_INFO ( + IN OUT CPU_TYPE_INFO *CpuInfoPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef VOID OPTION_DMI_GET_PROC_FAMILY ( + IN OUT UINT8 *T4ProcFamily, + IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable, + IN CPU_TYPE_INFO *CpuInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef UINT8 OPTION_DMI_GET_VOLTAGE ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef UINT16 OPTION_DMI_GET_MAX_SPEED ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef UINT16 OPTION_DMI_GET_EXT_CLOCK ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef VOID OPTION_DMI_GET_MEM_INFO ( + IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Brand table entry format +typedef struct { + UINT8 PackageType; ///< Package type + UINT8 PgOfBrandId; ///< Page + UINT8 NumberOfCores; ///< Number of cores + UINT8 String1ofBrandId; ///< String1 + UINT8 ValueSetToDmiTable; ///< The value which will should be set to DMI table +} DMI_BRAND_ENTRY; + +/// Family specific data table structure +struct _PROC_FAMILY_TABLE { + UINT64 ProcessorFamily; ///< processor + OPTION_DMI_GET_CPU_INFO *DmiGetCpuInfo; ///< transfer vectors + OPTION_DMI_GET_PROC_FAMILY *DmiGetT4ProcFamily; ///< Get DMI type 4 processor family information + OPTION_DMI_GET_VOLTAGE *DmiGetVoltage; ///< vector for reading voltage + OPTION_DMI_GET_MAX_SPEED *DmiGetMaxSpeed; ///< vector for reading speed + OPTION_DMI_GET_EXT_CLOCK *DmiGetExtClock; ///< vector for reading external clock speed + OPTION_DMI_GET_MEM_INFO *DmiGetMemInfo; ///< Get memory information + UINT8 LenBrandList; ///< size of brand table + CONST DMI_BRAND_ENTRY *DmiBrandList; ///< translate brand info to DMI identifier +}; + +//---------------------------------------------------------------------------- +// SLIT TYPEDEFS, STRUCTURES, ENUMS +// +//---------------------------------------------------------------------------- +/// Format for SRAT Header +typedef struct { + UINT8 Sign[4]; ///< Signature + UINT32 TableLength; ///< Table Length + UINT8 Revision; ///< Revision + UINT8 Checksum; ///< Checksum + UINT8 OemId[6]; ///< OEM ID + UINT8 OemTableId[8]; ///< OEM Tabled ID + UINT32 OemRev; ///< OEM Revision + UINT8 CreatorId[4]; ///< Creator ID + UINT32 CreatorRev; ///< Creator Revision +} ACPI_TABLE_HEADER; + +//---------------------------------------------------------------------------- +// SRAT TYPEDEFS, STRUCTURES, ENUMS +// +//---------------------------------------------------------------------------- +/// Format for SRAT Header +typedef struct _CPU_SRAT_HEADER { + UINT8 Sign[4]; ///< Signature + UINT32 TableLength; ///< Table Length + UINT8 Revision; ///< Revision + UINT8 Checksum; ///< Checksum + UINT8 OemId[6]; ///< OEM ID + UINT8 OemTableId[8]; ///< OEM Tabled ID + UINT32 OemRev; ///< OEM Revision + UINT8 CreatorId[4]; ///< Creator ID + UINT32 CreatorRev; ///< Creator Revision + UINT32 TableRev; ///< Table Revision + UINT8 Reserved[8]; ///< Reserved +} CPU_SRAT_HEADER; + + +/// Format for SRAT APIC Affinity Entry +typedef struct _CPU_SRAT_APIC_ENTRY { + UINT8 Type; ///< Type + UINT8 Length; ///< Length + UINT8 Domain; ///< Domain + UINT8 ApicId; ///< Apic ID + UINT32 Flags; ///< Flags + UINT8 LSApicEid; ///< Local SAPIC EID + UINT8 Reserved[7]; ///< Reserved +} CPU_SRAT_APIC_ENTRY; + + +/// Format for SRAT Memory Affinity Entry +typedef struct _CPU_SRAT_MEMORY_ENTRY { + UINT8 Type; ///< 0: Memory affinity = 1 + UINT8 Length; ///< 1: Length = 40 bytes + UINT32 Domain; ///< 2: Proximity domain + UINT8 Reserved1[2]; ///< 6: Reserved + UINT32 BaseAddrLow; ///< 8: Low 32bits address base + UINT32 BaseAddrHigh; ///< 12: High 32bits address base + UINT32 LengthAddrLow; ///< 16: Low 32bits address limit + UINT32 LengthAddrHigh; ///< 20: High 32bits address limit + UINT8 Reserved2[4]; ///< 24: Memory Type + UINT32 Flags; ///< 28: Flags + UINT8 Reserved3[8]; ///< 32: Reserved +} CPU_SRAT_MEMORY_ENTRY; + +//---------------------------------------------------------------------------- +// CRAT TYPEDEFS, STRUCTURES, ENUMS +// Component Resource Affinity Table +//---------------------------------------------------------------------------- +/// Format for CRAT Header +typedef struct { + UINT8 Sign[4]; ///< CRAT, Signature for the Component Resource Affinity Table. + UINT32 Length; ///< Length, in bytes, of the entire CRAT + UINT8 Revision; ///< 0 + UINT8 Checksum; ///< Entire table must sum to zero. + UINT8 OemId[6]; ///< OEM ID + UINT8 OemTableId[8]; ///< OEM Tabled ID + UINT32 OemRev; ///< OEM Revision + UINT8 CreatorId[4]; ///< Creator ID + UINT32 CreatorRev; ///< Creator Revision + UINT32 TotalEntries; ///< total number[n] of entries in the CRAT + UINT16 NumDomains; ///< Number of HSA proximity domains + UINT8 Reserved[6]; ///< Reserved +} CRAT_HEADER; + +/// Flags field of the CRAT HSA Processing Unit Affinity Structure +typedef struct { + UINT32 Enabled:1; ///< Enabled + UINT32 HotPluggable:1; ///< Hot Pluggable + UINT32 CpuPresent:1; ///< Cpu Present + UINT32 GpuPresent:1; ///< Gpu Present + UINT32 IommuPresent:1; ///< IOMMU Present + UINT32 :27; ///< Reserved +} CRAT_HSA_PROCESSING_UNIT_FLAG; + +/// CRAT HSA Processing Unit Affinity Structure +typedef struct { + UINT8 Type; ///< 0 - CRAT HSA Processing Unit Structure + UINT8 Length; ///< 40 + UINT16 Reserved; ///< Reserved + CRAT_HSA_PROCESSING_UNIT_FLAG Flags; ///< Flags - HSA Processing Unit Affinity Structure + UINT32 ProximityDomain; ///< Integer that represents the proximity domain to which the node belongs to + UINT32 ProcessorIdLow; ///< Low value of the logical processor included in this HSA proximity domain + UINT16 CpuCoreCount; ///< Indicates overall count of x86(-64) -compatible execution units (CPU cores) are present in this (APU-) node (identifiable by SW). + UINT16 SimdCount; ///< Indicates overall count of GPU SIMDs present in this node (identifiable by SW). + UINT16 SimdWidth; ///< "Width" of a single SIMD unit. SIMDCount*SIMDWidth determines the total number of non-x86 execution units. + UINT16 IoCount; ///< Number of discoverable IO Interfaces connecting this node to other components. + UINT8 Reserved1[16]; ///< Reserved +} CRAT_HSA_PROCESSING_UNIT; + +/// Flags field of the CRAT Memory Affinity Structure +typedef struct { + UINT32 Enabled:1; ///< Enabled + UINT32 HotPluggable:1; ///< Hot Pluggable + UINT32 NonVolatile:1; ///< If set, the memory region represents Non-Volatile memory + UINT32 :29; ///< Reserved +} CRAT_MEMORY_FLAG; + +/// CRAT Memory Affinity Structure +typedef struct { + UINT8 Type; ///< 1 - CRAT Memory Affinity Structure + UINT8 Length; ///< 40 + UINT16 Reserved; ///< Reserved + CRAT_MEMORY_FLAG Flags; ///< Flags - Memory Affinity Structure. Indicates whether the region of memory is enabled and can be hot plugged + UINT32 ProximityDomain; ///< Integer that represents the proximity domain to which the node belongs to + UINT32 BaseAddressLow; ///< Low 32Bits of the Base Address of the memory range + UINT32 BaseAddressHigh; ///< High 32Bits of the Base Address of the memory range + UINT32 LengthLow; ///< Low 32Bits of the length of the memory range + UINT32 LengthHigh; ///< High 32Bits of the length of the memory range + UINT32 Width; ///< Memory width - Specifies the number of parallel bits of the memory interface + UINT8 Reserved1[8]; ///< Reserved +} CRAT_MEMORY; + +/// Flags field of the CRAT Cache Affinity structure +typedef struct { + UINT32 Enabled:1; ///< Enabled + UINT32 DataCache:1; ///< 1 if cache includes data + UINT32 InstructionCache:1; ///< 1 if cache includes instructions + UINT32 CpuCache:1; ///< 1 if cache is part of CPU functionality + UINT32 SimdCache:1; ///< 1 if cache is part of SIMD functionality + UINT32 :27; ///< Reserved +} CRAT_CACHE_FLAG; + +/// CRAT Cache Affinity Structure +typedef struct { + UINT8 Type; ///< 2 - CRAT Cache Affinity Structure + UINT8 Length; ///< 64 + UINT16 Reserved; ///< Reserved + CRAT_CACHE_FLAG Flags; ///< Flags - Cache Affinity Structure. Indicates whether the region of cache is enabled + UINT32 ProcessorIdLow; ///< Low value of a logical processor which includes this component + UINT8 SiblingMap[32]; ///< Bitmask of Processor Id sharing this component. 1 bit per logical processor + UINT32 CacheSize; ///< Cache size in KB + UINT8 CacheLevel; ///< Integer representing level: 1, 2, 3, 4, etc. + UINT8 LinesPerTag; ///< Cache Lines per tag + UINT16 CacheLineSize; ///< Cache line size in bytes + UINT8 Associativity; ///< Cache associativity + ///< The associativity fields are encoded as follows: + ///< 00h: Reserved. + ///< 01h: Direct mapped. + ///< 02h-FEh: Associativity. (e.g., 04h = 4-way associative.) + ///< FFh: Fully associative + UINT8 CacheProperties; ///< Cache Properties bits [2:0] represent Inclusive/Exclusive property encoded. + ///< 0: Cache is strictly exclusive to lower level caches. + ///< 1: Cache is mostly exclusive to lower level caches. + ///< 2: Cache is strictly inclusive to lower level caches. + ///< 3: Cache is mostly inclusive to lower level caches. + ///< 4: Cache is a "constant cache" (= explicit update) + ///< 5: Cache is a "specialty cache" (e.g. Texture cache) + ///< 6-7: Reserved + ///< CacheProperties bits [7:3] are reserved + UINT16 CacheLatency; ///< Cost of time to access cache described in nanoseconds. + UINT8 Reserved1[8]; ///< Reserved +} CRAT_CACHE; + +/// Flags field of the CRAT TLB Affinity structure +typedef struct { + UINT32 Enabled:1; ///< Enabled + UINT32 DataTLB:1; ///< 1 if TLB includes translation information for data. + UINT32 InstructionTLB:1; ///< 1 if TLB includes translation information for instructions. + UINT32 CpuTLB:1; ///< 1 if TLB is part of CPU functionality + UINT32 SimdTLB:1; ///< 1 if TLB is part of SIMD functionality + UINT32 :27; ///< Reserved +} CRAT_TLB_FLAG; + +/// CRAT TLB Affinity Structure +typedef struct { + UINT8 Type; ///< 3 - CRAT TLB Affinity Structure + UINT8 Length; ///< 64 + UINT16 Reserved; ///< Reserved + CRAT_TLB_FLAG Flags; ///< Flags - TLB Affinity Structure. Indicates whether the TLB is enabled and defined + UINT32 ProcessorIdLow; ///< Low value of a logical processor which includes this component. + UINT8 SiblingMap[32]; ///< Bitmask of Processor Id sharing this component. 1 bit per logical processor + UINT32 TLBLevel; ///< Integer representing level: 1, 2, 3, 4, etc. + UINT8 DataTLBAssociativity2MB; ///< Data TLB associativity for 2MB pages + ///< The associativity fields are encoded as follows: + ///< 00h: Reserved. + ///< 01h: Direct mapped. + ///< 02h-FEh: Associativity. (e.g., 04h = 4-way associative.) + ///< FFh: Fully associative. + UINT8 DataTLBSize2MB; ///< Data TLB number of entries for 2MB. + UINT8 InstructionTLBAssoc2MB; ///< Instruction TLB associativity for 2MB pages + ///< The associativity fields are encoded as follows: + ///< 00h: Reserved. + ///< 01h: Direct mapped. + ///< 02h-FEh: Associativity. (e.g., 04h = 4-way associative.) + ///< FFh: Fully associative. + UINT8 InstructionTLBSize2MB; ///< Instruction TLB number of entries for 2MB pages. + UINT8 DTLB4KAssoc; ///< Data TLB Associativity for 4KB pages + UINT8 DTLB4KSize; ///< Data TLB number of entries for 4KB pages + UINT8 ITLB4KAssoc; ///< Instruction TLB Associativity for 4KB pages + UINT8 ITLB4KSize; ///< Instruction TLB number of entries for 4KB pages + UINT8 DTLB1GAssoc; ///< Data TLB Associativity for 1GB pages + UINT8 DTLB1GSize; ///< Data TLB number of entries for 1GB pages + UINT8 ITLB1GAssoc; ///< Instruction TLB Associativity for 1GB pages + UINT8 ITLB1GSize; ///< Instruction TLB number of entries for 1GB pages + UINT8 Reserved1[4]; ///< Reserved +} CRAT_TLB; + +/// Flags field of the CRAT FPU Affinity structure +typedef struct { + UINT32 Enabled:1; ///< Enabled + UINT32 :31; ///< Reserved +} CRAT_FPU_FLAG; + +/// CRAT FPU Affinity Structure +typedef struct { + UINT8 Type; ///< 4 - CRAT FPU Affinity Structure + UINT8 Length; ///< 64 + UINT16 Reserved; ///< Reserved + CRAT_FPU_FLAG Flags; ///< Flags - FPU Affinity Structure. Indicates whether the region of FPU affinity structure is enabled and defined + UINT32 ProcessorIdLow; ///< Low value of a logical processor which includes this component. + UINT8 SiblingMap[32]; ///< Bitmask of Processor Id sharing this component. 1 bit per logical processor + UINT32 FPUSize; ///< Product specific + UINT8 Reserved1[16]; ///< Reserved +} CRAT_FPU; + +/// Flags field of the CRAT IO Affinity structure +typedef struct { + UINT32 Enabled:1; ///< Enabled + UINT32 Coherency:1; ///< If set, IO interface supports coherent transactions (natively or through protocol extensions) + UINT32 :30; ///< Reserved +} CRAT_IO_FLAG; + +/// CRAT IO Affinity Structure +typedef struct { + UINT8 Type; ///< 5 - CRAT IO Affinity Structure + UINT8 Length; ///< 64 + UINT16 Reserved; ///< Reserved + CRAT_IO_FLAG Flags; ///< Flags - IO Affinity Structure. Indicates whether the region of IO affinity structure is enabled and defined. + UINT32 ProximityDomainFrom; ///< Integer that represents the proximity domain to which the IO Interface belongs to + UINT32 ProximityDomainTo; ///< Integer that represents the other proximity domain to which the IO Interface belongs to + UINT8 IoType; ///< IO Interface type. Values defined are + ///< 0: Undefined + ///< 1: Hypertransport + ///< 2: PCI Express + ///< 3: Other (e.g. internal) + ///< 4-255: Reserved + UINT8 VersionMajor; ///< Major version of the Bus interface + UINT16 VersionMinor; ///< Minor version of the Bus interface ((optional) + UINT32 MinimumLatency; ///< Cost of time to transfer, described in nanoseconds. + UINT32 MaximumLatency; ///< Cost of time to transfer, described in nanoseconds. + UINT32 MinimumBandwidth; ///< Minimum interface Bandwidth in MB/s + UINT32 MaximumBandwidth; ///< Maximum interface Bandwidth in MB/s + UINT32 RecommendedTransferSize; ///< Recommended transfer size to reach maximum interface bandwidth in Bytes + UINT8 Reserved1[24]; ///< Reserved +} CRAT_IO; + +#define CRAT_MAX_LENGTH 0x400ul ///< Reserve 1K for CRAT +/// CRAT entry type +typedef enum { + CRAT_TYPE_HSA_PROC_UNIT = 0, ///< 0 - CRAT HSA Processing Unit Structure + CRAT_TYPE_MEMORY, ///< 1 - CRAT Memory Affinity Structure + CRAT_TYPE_CACHE, ///< 2 - CRAT Cache Affinity Structure + CRAT_TYPE_TLB, ///< 3 - CRAT TLB Affinity Structure + CRAT_TYPE_FPU, ///< 4 - CRAT FPU Affinity Structure + CRAT_TYPE_IO, ///< 5 - CRAT IO Affinity Structure +} CRAT_ENTRY_TYPE; + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +AmdCpuLate ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig + ); + +AGESA_STATUS +CreateAcpiWhea ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT VOID **WheaMcePtr, + IN OUT VOID **WheaCmcPtr + ); + +AGESA_STATUS +CreateDmiRecords ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT DMI_INFO **DmiTable + ); + +AGESA_STATUS +GetType4Type7Info ( + IN AP_EXE_PARAMS *ApExeParams + ); + +VOID +DmiGetT4ProcFamilyFromBrandId ( + IN OUT UINT8 *T4ProcFamily, + IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable, + IN CPU_TYPE_INFO *CpuInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GetNameString ( + IN OUT CHAR8 *String, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +IsSourceStrContainTargetStr ( + IN OUT CHAR8 *SourceStr, + IN OUT CONST CHAR8 *TargetStr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +CreateAcpiCrat ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + OUT VOID **CratPtr + ); + +AGESA_STATUS +CreateAcpiCdit ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + OUT VOID **CditPtr + ); + +AGESA_STATUS +CreateAcpiSrat ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT VOID **SratPtr + ); + +AGESA_STATUS +CreateAcpiSlit ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT VOID **SlitPtr + ); + +VOID +ChecksumAcpiTable ( + IN OUT ACPI_TABLE_HEADER *Table, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +RunLateApTaskOnAllAPs ( + IN AP_EXE_PARAMS *ApParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +RunLateApTaskOnAllCore0s ( + IN AP_EXE_PARAMS *ApParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif // _CPU_LATE_INIT_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuMicrocodePatch.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuMicrocodePatch.c new file mode 100644 index 0000000..1ccc7e7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuMicrocodePatch.c @@ -0,0 +1,456 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Microcode Patch Related Functions + * + * Contains code to program a microcode into the CPU + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*--------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *--------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuFamilyTranslation.h" +#include "cpuEarlyInit.h" +#include "GeneralServices.h" +#include "cpuServices.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_CPUMICROCODEPATCH_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +typedef union { + UINT64 RawData; + PATCH_LOADER_MSR BitFields; +} PATCH_LOADER; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +LoadMicrocode ( + IN MICROCODE_PATCH *MicrocodePatchPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +LoadMicrocodePatchAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/* -----------------------------------------------------------------------------*/ +/** + * Update microcode patch in current processor. + * + * Then reads the patch id, and compare it to the expected, in the Microprocessor + * patch block. + * + * @param[in] StdHeader - Config handle for library and services. + * + * @retval TRUE - Patch Loaded Successfully. + * @retval FALSE - Patch Did Not Get Loaded. + * + */ +BOOLEAN +LoadMicrocodePatch ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 PatchNumber; + UINT8 TotalPatches; + UINT16 ProcessorEquivalentId; + BOOLEAN Status; + MICROCODE_PATCH **MicrocodePatchPtr; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + MICROCODE_PATCH *ForceLoadMicrocodePatchPtr; + Status = FALSE; + + if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) { + // Get the patch pointer + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->GetMicroCodePatchesStruct (FamilySpecificServices, (CONST VOID **) &MicrocodePatchPtr, &TotalPatches, StdHeader); + ForceLoadMicrocodePatchPtr = NULL; + IDS_SKIP_HOOK (IDS_UCODE, &ForceLoadMicrocodePatchPtr, StdHeader) { + if (ForceLoadMicrocodePatchPtr == NULL) { + // Get the processor microcode path equivalent ID + if (GetPatchEquivalentId (&ProcessorEquivalentId, StdHeader)) { + // parse the patch table to see if we have one for the current cpu + for (PatchNumber = 0; PatchNumber < TotalPatches; PatchNumber++) { + if (ValidateMicrocode (MicrocodePatchPtr[PatchNumber], ProcessorEquivalentId, StdHeader)) { + if (LoadMicrocode (MicrocodePatchPtr[PatchNumber], StdHeader)) { + Status = TRUE; + } else { + PutEventLog (AGESA_ERROR, + CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED, + 0, 0, 0, 0, StdHeader); + } + break; // Once we find a microcode patch that matches the processor, exit the for loop + } + } + } + } else { + if (LoadMicrocode (ForceLoadMicrocodePatchPtr, StdHeader)) { + Status = TRUE; + } else { + PutEventLog (AGESA_ERROR, + CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED, + 0, 0, 0, 0, StdHeader); + } + } + } + } + return Status; +} + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * LoadMicrocode + * + * Update microcode patch in current processor, then reads the + * patch id, and compare it to the expected, in the Microprocessor + * patch block. + * + * @param[in] MicrocodePatchPtr - Pointer to Microcode Patch. + * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. + * + * @retval TRUE - Patch Loaded Successfully. + * @retval FALSE - Patch Did Not Get Loaded. + * + */ +BOOLEAN +STATIC +LoadMicrocode ( + IN MICROCODE_PATCH *MicrocodePatchPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 MicrocodeVersion; + PATCH_LOADER PatchLoaderMsr; + + // Load microcode patch into CPU + PatchLoaderMsr.RawData = (UINT64) (UINTN) MicrocodePatchPtr; + PatchLoaderMsr.BitFields.SBZ = 0; + LibAmdMsrWrite (0xC0010020ul , &PatchLoaderMsr.RawData, StdHeader); + + // Do ucode patch Authentication + // Read microcode version back from CPU, determine if + // it is the same patch level as contained in the source + // microprocessor patch block passed in + GetMicrocodeVersion (&MicrocodeVersion, StdHeader); + if (MicrocodeVersion == MicrocodePatchPtr->PatchID) { + return (TRUE); + } else { + return (FALSE); + } +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * GetPatchEquivalentId + * + * Return the equivalent ID for microcode patching + * + * @param[in,out] ProcessorEquivalentId - Pointer to Processor Equivalent ID table. + * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. + * + * @retval TRUE - ID Found. + * @retval FALSE - ID Not Found. + * + */ +BOOLEAN +GetPatchEquivalentId ( + IN OUT UINT16 *ProcessorEquivalentId, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + UINT8 EquivalencyEntries; + UINT16 ProcessorRevisionId; + UINT16 *MicrocodeEquivalenceTable; + CPUID_DATA CpuIdData; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + // + // compute the processor revision ID + // + LibAmdCpuidRead (AMD_CPUID_FMF, &CpuIdData, StdHeader); + // high byte contains extended model and extended family + ProcessorRevisionId = (UINT16) ((CpuIdData.EAX_Reg & (CPU_EMODEL | CPU_EFAMILY)) >> 8); + // low byte contains model and family + ProcessorRevisionId |= (CpuIdData.EAX_Reg & (CPU_STEPPING | CPU_MODEL)); + + // + // find the equivalent ID for microcode purpose using the equivalence table + // + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + + FamilySpecificServices->GetMicrocodeEquivalenceTable (FamilySpecificServices, + (CONST VOID **) &MicrocodeEquivalenceTable, + &EquivalencyEntries, + StdHeader); + + // parse the equivalence table + for (i = 0; i < (EquivalencyEntries * 2); i += 2) { + // check for equivalence + if (ProcessorRevisionId == MicrocodeEquivalenceTable[i]) { + *ProcessorEquivalentId = MicrocodeEquivalenceTable[i + 1]; + return (TRUE); + } + } + // end of table reach, this processor is not supported + *ProcessorEquivalentId = 0x0000; + return (FALSE); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * + * ValidateMicrocode + * + * Determine if the microcode patch block, currently pointed to + * is valid, and is appropriate for the current processor + + * @param[in] MicrocodePatchPtr - Pointer to Microcode Patch. + * @param[in] ProcessorEquivalentId - Pointer to Processor Equivalent ID table. + * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. + * + * @retval TRUE - Patch Found. + * @retval FALSE - Patch Not Found. + * + */ +BOOLEAN +ValidateMicrocode ( + IN MICROCODE_PATCH *MicrocodePatchPtr, + IN UINT16 ProcessorEquivalentId, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + BOOLEAN Chipset1Matched; + BOOLEAN Chipset2Matched; + PCI_ADDR PciAddress; + UINT32 PciDeviceVidDid; + UINT8 PciDeviceRevision; + UINT8 DevCount; + UINT8 FunCount; + UINT32 Chipset1DeviceID; + UINT32 Chipset2DeviceID; + UINT8 MulitFunction; + + Chipset1Matched = FALSE; + Chipset2Matched = FALSE; + PciDeviceVidDid = 0; + PciDeviceRevision = 0; + Chipset1DeviceID = MicrocodePatchPtr->Chipset1DeviceID; + Chipset2DeviceID = MicrocodePatchPtr->Chipset2DeviceID; + MulitFunction = 0; + + // + // parse the supplied microcode to see if it is compatible with the processor + // + if (MicrocodePatchPtr->ProcessorRevisionID != ProcessorEquivalentId) { + return (FALSE); + } + + if (Chipset1DeviceID == 0) { + Chipset1Matched = TRUE; + } + if (Chipset2DeviceID == 0) { + Chipset2Matched = TRUE; + } + + if ((!Chipset1Matched) || (!Chipset2Matched)) { + // + // Scan all PCI devices in Bus 0, try to find out matched case. + // + for (DevCount = 0; DevCount < 32; DevCount++) { + for (FunCount = 0; FunCount < 8; FunCount++) { + PciAddress.AddressValue = MAKE_SBDFO (0, 0, DevCount, FunCount, 0); + LibAmdPciRead (AccessWidth32, PciAddress, &PciDeviceVidDid, StdHeader); + if (PciDeviceVidDid == 0xFFFFFFFF) { + if (FunCount == 0) { + break; + } else { + continue; + } + } + PciAddress.Address.Register = 0x8; + LibAmdPciRead (AccessWidth8, PciAddress, &PciDeviceRevision, StdHeader); + if ((!Chipset1Matched) && (PciDeviceVidDid == Chipset1DeviceID)) { + if (PciDeviceRevision == MicrocodePatchPtr->Chipset1RevisionID) { + Chipset1Matched = TRUE; + } + } + if ((!Chipset2Matched) && (PciDeviceVidDid == Chipset2DeviceID)) { + if (PciDeviceRevision == MicrocodePatchPtr->Chipset2RevisionID) { + Chipset2Matched = TRUE; + } + } + if (Chipset1Matched && Chipset2Matched) { + break; + } + // + // Check multi-function. If it doesen't exist, we don't have to loop functions to 7. + // + if (FunCount == 0) { + MulitFunction = 0; + PciAddress.Address.Register = 0xE; + LibAmdPciRead (AccessWidth8, PciAddress, &MulitFunction, StdHeader); + if ((MulitFunction & 0x80) == 0) { + break; + } + } + } // end FunCount for loop. + + if (Chipset1Matched && Chipset2Matched) { + break; + } + } // end DevCount for loop. + } + + return (Chipset1Matched && Chipset2Matched); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * + * GetMicrocodeVersion + * + * Return the version of the currently loaded microcode patch, if any. + * Read from the patch level MSR, return the value in eax. If no patch + * has been loaded, 0 will be returned. + * + * @param[out] pMicrocodeVersion - Pointer to Microcode Version. + * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct. + * + */ +VOID +GetMicrocodeVersion ( + OUT UINT32 *pMicrocodeVersion, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 MsrData; + + MsrData = 0; + LibAmdMsrRead (0x0000008Bul , &MsrData, StdHeader); + + *pMicrocodeVersion = (UINT32) MsrData; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Update microcode patch in current processor. + * + * This function acts as a wrapper for calling the LoadMicrocodePatch + * routine at AmdInitEarly. + * + * @param[in] FamilyServices The current Family Specific Services. + * @param[in] EarlyParams Service parameters. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +LoadMicrocodePatchAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_TESTPOINT (TpProcCpuLoadUcode, StdHeader); + LoadMicrocodePatch (StdHeader); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPage.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPage.h new file mode 100644 index 0000000..27e25c5 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPage.h @@ -0,0 +1,88 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Create outline and references for CPU Component mainpage documentation. + * + * Design guides, maintenance guides, and general documentation, are + * collected using this file onto the documentation mainpage. + * This file contains doxygen comment blocks, only. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Documentation + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/** + * @page cpumain CPU Component Documentation + * + * Additional documentation for the CPU component consists of + * + * - Maintenance Guides: + * - @subpage cpuimplfss "CPU Family Specific Services Implementation Guide" + * - @subpage regtableimpl "Register Table Implementation Guide" + * - @subpage cpufeatimpl "CPU Generic Feature Implementation Guide" + * - @subpage ucodeflag "Microcode Patches Signature Guide" + * - add here >>> + * - Design Guides: + * - add here >>> + * + */ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c new file mode 100644 index 0000000..5eda346 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c @@ -0,0 +1,519 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU POST API, and related functions. + * + * Contains code that initialized the CPU after memory init. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + **************************************************************************** + * AMD Generic Encapsulated Software Architecture + * + * Description: cpuPostInit.c - Cpu POST Initialization Functions. + * + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Options.h" +#include "cpuRegisters.h" +#include "cpuApicUtilities.h" +#include "heapManager.h" +#include "cpuServices.h" +#include "cpuFeatures.h" +#include "GeneralServices.h" +#include "cpuPostInit.h" +#include "cpuPstateTables.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) +#define FILECODE PROC_CPU_CPUPOSTINIT_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +SyncVariableMTRR ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern BUILD_OPT_CFG UserOptions; +extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; + +extern +VOID +ExecuteWbinvdInstruction ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PstateCreateHeapInfo ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------*/ +/** + * Performs CPU related initialization at the POST entry point + * + * This function performs a large list of initialization items. These items + * include: + * + * -1 AP MTRR sync + * -2 feature leveling + * -3 P-state data gather + * -4 P-state leveling + * -5 AP cache breakdown & release + * + * @param[in] StdHeader Config handle for library and services + * @param[in] PlatformConfig Config handle for platform specific information + * + * @retval AGESA_SUCCESS + * + */ +AGESA_STATUS +AmdCpuPost ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS CalledStatus; + + AgesaStatus = AGESA_SUCCESS; + // + // Sync variable MTRR + // + AGESA_TESTPOINT (TpProcCpuApMtrrSync, StdHeader); + SyncVariableMTRR (StdHeader); + + AGESA_TESTPOINT (TpProcCpuPostFeatureInit, StdHeader); + IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features after AP MTRR sync\n"); + CalledStatus = DispatchCpuFeatures (CPU_FEAT_AFTER_POST_MTRR_SYNC, PlatformConfig, StdHeader); + if (CalledStatus > AgesaStatus) { + AgesaStatus = CalledStatus; + } + // + // Feature Leveling + // + AGESA_TESTPOINT (TpProcCpuFeatureLeveling, StdHeader); + IDS_HDT_CONSOLE (CPU_TRACE, " Perform feature leveling\n"); + FeatureLeveling (StdHeader); + // + // P-state Gathered and set heap info + // + IDS_HDT_CONSOLE (CPU_TRACE, " Create P-state info in the heap\n"); + PstateCreateHeapInfo (PlatformConfig, StdHeader); + + // Set TscFreqSel at the rate specified by the core P0 after core frequency leveling. + SetCoresTscFreqSel (StdHeader); + + // Dispatch CPU features before relinquishing control of APs + AGESA_TESTPOINT (TpProcCpuBeforeRelinquishAPsFeatureInit, StdHeader); + IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features before Relinquishing control of APs\n"); + CalledStatus = DispatchCpuFeatures (CPU_FEAT_BEFORE_RELINQUISH_AP, PlatformConfig, StdHeader); + if (CalledStatus > AgesaStatus) { + AgesaStatus = CalledStatus; + } + + // Relinquish control of all APs to IBV. + IDS_HDT_CONSOLE (CPU_TRACE, " Relinquish control of APs\n"); + RelinquishControlOfAllAPs (StdHeader); + + return (AgesaStatus); +} + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Determines the address in system DRAM that should be used for p-state data + * gather and leveling. + * + * @param[out] Ptr Address to utilize + * @param[in] StdHeader Config handle for library and services + * + * @retval AGESA_SUCCESS + * + */ +AGESA_STATUS +GetPstateGatherDataAddressAtPost ( + OUT UINT64 **Ptr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 AddressValue; + + AddressValue = P_STATE_DATA_GATHER_TEMP_ADDR; + + *Ptr = (UINT64 *)(AddressValue); + + return AGESA_SUCCESS; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * AP task to sync memory subsystem MSRs with the BSC + * + * This function processes a list of MSRs and the BSC's current values for those + * MSRs. This will allow the APs to see system RAM. + * + * @param[in] MtrrTable Memory related MSR table + * @param[in] StdHeader Config handle for library and services + * + */ +VOID +SyncAllApMtrrToBsc ( + IN VOID *MtrrTable, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + + for (i = 0; ((BSC_AP_MSR_SYNC *) MtrrTable)[i].RegisterAddress != 0; i++) { + LibAmdMsrWrite (((BSC_AP_MSR_SYNC *) MtrrTable)[i].RegisterAddress, + &((BSC_AP_MSR_SYNC *) MtrrTable)[i].RegisterValue, + StdHeader); + } +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Creates p-state information on the heap + * + * This function gathers p-state information from all processors in the system, + * determines a level set of p-states, and places that information into the + * heap. This heap data will be used by GenerateSsdt to generate the + * final _PSS and XPSS objects. + * + * @param[in] PlatformConfig Pointer to runtime configuration options + * @param[in] StdHeader Config handle for library and services + * + * @retval AGESA_SUCCESS No error + * @retval AGESA_ERROR CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE + */ +AGESA_STATUS +PstateCreateHeapInfo ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + S_CPU_AMD_PSTATE *PStateBufferPtr; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + UINT8 *PStateBufferPtrInHeap; + + ASSERT (IsBsp (StdHeader, &AgesaStatus)); + + // + //Get proper address for gather data pool address + //Zero P-state gather data pool + // + GetPstateGatherDataAddressAtPost ((UINT64 **)&PStateBufferPtr, StdHeader); + LibAmdMemFill (PStateBufferPtr, 0, sizeof (S_CPU_AMD_PSTATE), StdHeader); + + // + //Get all the CPUs P-States and fill the PStateBufferPtr for each core + // + AgesaStatus = PStateGatherData (PlatformConfig, PStateBufferPtr, StdHeader); + if (AgesaStatus != AGESA_SUCCESS) { + return AgesaStatus; + } + + // + //Do Pstate Leveling for each core if needed. + // + AgesaStatus = PStateLeveling (PStateBufferPtr, StdHeader); + + // + //Create Heap and store p-state data for ACPI table in CpuLate + // + AllocHeapParams.RequestedBufferSize = PStateBufferPtr->SizeOfBytes; + AllocHeapParams.BufferHandle = AMD_PSTATE_DATA_BUFFER_HANDLE; + AllocHeapParams.Persist = HEAP_SYSTEM_MEM; + AgesaStatus = HeapAllocateBuffer (&AllocHeapParams, StdHeader); + if (AgesaStatus == AGESA_SUCCESS) { + // + // Zero Buffer + // + PStateBufferPtrInHeap = (UINT8 *) AllocHeapParams.BufferPtr; + LibAmdMemFill (PStateBufferPtrInHeap, 0, PStateBufferPtr->SizeOfBytes, StdHeader); + LibAmdMemCopy (PStateBufferPtrInHeap, PStateBufferPtr, PStateBufferPtr->SizeOfBytes, StdHeader); + + } else { + PutEventLog (AGESA_ERROR, + CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE, + 0, 0, 0, 0, StdHeader); + } + + return AgesaStatus; +} + +VOID +SyncApMsrsToBsc ( + IN OUT BSC_AP_MSR_SYNC *ApMsrSync, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AP_TASK TaskPtr; + UINT16 i; + UINT32 BscSocket; + UINT32 Ignored; + UINT32 BscCoreNum; + UINT32 Core; + UINT32 Socket; + UINT32 NumberOfSockets; + UINT32 NumberOfCores; + AGESA_STATUS IgnoredSts; + + ASSERT (IsBsp (StdHeader, &IgnoredSts)); + + IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); + NumberOfSockets = GetPlatformNumberOfSockets (); + + // + //Sync all MTRR settings with BSP + // + for (i = 0; ApMsrSync[i].RegisterAddress != 0; i++) { + LibAmdMsrRead (ApMsrSync[i].RegisterAddress, &ApMsrSync[i].RegisterValue, StdHeader); + } + + TaskPtr.FuncAddress.PfApTaskI = SyncAllApMtrrToBsc; + TaskPtr.DataTransfer.DataSizeInDwords = (UINT16) ((((sizeof (BSC_AP_MSR_SYNC)) * i) + 4) >> 2); + TaskPtr.ExeFlags = WAIT_FOR_CORE; + TaskPtr.DataTransfer.DataPtr = ApMsrSync; + TaskPtr.DataTransfer.DataTransferFlags = 0; + + for (Socket = 0; Socket < NumberOfSockets; Socket++) { + if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { + for (Core = 0; Core < NumberOfCores; Core++) { + if ((Socket != BscSocket) || (Core != BscCoreNum)) { + ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); + } + } + } + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * SyncVariableMTRR + * + * Sync variable MTRR + * + * @param[in] StdHeader Config handle for library and services + * + */ +VOID +STATIC +SyncVariableMTRR ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + BSC_AP_MSR_SYNC ApMsrSync[20]; + + ApMsrSync[0].RegisterAddress = SYS_CFG; + ApMsrSync[1].RegisterAddress = TOP_MEM; + ApMsrSync[2].RegisterAddress = TOP_MEM2; + ApMsrSync[3].RegisterAddress = 0x200; + ApMsrSync[4].RegisterAddress = 0x201; + ApMsrSync[5].RegisterAddress = 0x202; + ApMsrSync[6].RegisterAddress = 0x203; + ApMsrSync[7].RegisterAddress = 0x204; + ApMsrSync[8].RegisterAddress = 0x205; + ApMsrSync[9].RegisterAddress = 0x206; + ApMsrSync[10].RegisterAddress = 0x207; + ApMsrSync[11].RegisterAddress = 0x208; + ApMsrSync[12].RegisterAddress = 0x209; + ApMsrSync[13].RegisterAddress = 0x20A; + ApMsrSync[14].RegisterAddress = 0x20B; + ApMsrSync[15].RegisterAddress = 0xC0010016; + ApMsrSync[16].RegisterAddress = 0xC0010017; + ApMsrSync[17].RegisterAddress = 0xC0010018; + ApMsrSync[18].RegisterAddress = 0xC0010019; + ApMsrSync[19].RegisterAddress = 0; + SyncApMsrsToBsc (ApMsrSync, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * The function suppose to do any thing need to be done at the end of AmdInitPost. + * + * @param[in] StdHeader Config handle for library and services + * + * @retval AGESA_SUCCESS + * + */ +AGESA_STATUS +FinalizeAtPost ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + // + // Execute wbinvd to ensure heap data in cache write back to memory. + // + ExecuteWbinvdInstruction (StdHeader); + + return AGESA_SUCCESS; +} +/*---------------------------------------------------------------------------------------*/ +/** + * Set TSC Frequency Selection. + * + * This function set TSC Frequency Selection. + * + * @param[in] StdHeader Config handle for library and services + * + */ +VOID +STATIC +SetTscFreqSel ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PSTATE_CPU_FAMILY_SERVICES *FamilyServices; + + FamilyServices = NULL; + + GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); + if (FamilyServices != NULL) { + FamilyServices->CpuSetTscFreqSel (FamilyServices, StdHeader); + } + +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Set TSC Frequency Selection to all cores. + * + * This function set TscFreqSel to all cores in the system. + * + * @param[in] StdHeader Config handle for library and services + * + */ +VOID +SetCoresTscFreqSel ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AP_TASK TaskPtr; + UINT32 BscSocket; + UINT32 Ignored; + UINT32 BscCoreNum; + UINT32 Core; + UINT32 Socket; + UINT32 NumberOfSockets; + UINT32 NumberOfCores; + AGESA_STATUS IgnoredSts; + + ASSERT (IsBsp (StdHeader, &IgnoredSts)); + + IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); + NumberOfSockets = GetPlatformNumberOfSockets (); + + SetTscFreqSel (StdHeader); + + TaskPtr.FuncAddress.PfApTask = SetTscFreqSel; + TaskPtr.ExeFlags = WAIT_FOR_CORE; + TaskPtr.DataTransfer.DataTransferFlags = 0; + TaskPtr.DataTransfer.DataSizeInDwords = 0; + TaskPtr.DataTransfer.DataPtr = NULL; + + for (Socket = 0; Socket < NumberOfSockets; Socket++) { + if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { + for (Core = 0; Core < NumberOfCores; Core++) { + if ((Socket != BscSocket) || (Core != BscCoreNum)) { + ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); + } + } + } + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.h new file mode 100644 index 0000000..91bc28a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.h @@ -0,0 +1,265 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Reset API, and related functions and structures. + * + * Contains code that initialized the CPU after early reset. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_POST_INIT_H_ +#define _CPU_POST_INIT_H_ + + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ +// Forward declaration needed for multi-structure mutual references +AGESA_FORWARD_DECLARATION (CPU_CFOH_FAMILY_SERVICES); + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ +#define P_STATE_DATA_GATHER_TEMP_ADDR 0x200000ul ///< Fixed the row data at 2M memory address. +#define GLOBAL_CPU_FEATURE_LIST_TEMP_ADDR 0x200000ul ///< Fixed the row data at 2M memory address. +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ +//---------------------------------------------------------------------------- +// CPU FEATURE LEVELING TYPEDEFS, STRUCTURES, ENUMS +// +//---------------------------------------------------------------------------- +/// CPU FEATURE LIST +typedef struct { + UINT8 ABM:1; ///< byte 0 bit 0 + UINT8 AES:1; ///< byte 0 bit 1 + UINT8 AltMovCr8:1; ///< byte 0 bit 2 + UINT8 APIC:1; ///< byte 0 bit 3 + UINT8 AVX:1; ///< byte 0 bit 4 + UINT8 CLFSH:1; ///< byte 0 bit 5 + UINT8 CMOV:1; ///< byte 0 bit 6 + UINT8 CmpLegacy:1; ///< byte 0 bit 7 + UINT8 CMPXCHG8B:1; ///< byte 1 bit 0 + UINT8 CMPXCHG16B:1; ///< byte 1 bit 1 + UINT8 F16C :1; ///< byte 1 bit 2 + UINT8 DE:1; ///< byte 1 bit 3 + UINT8 ExtApicSpace:1; ///< byte 1 bit 4 + UINT8 FFXSR:1; ///< byte 1 bit 5 + UINT8 FMA:1; ///< byte 1 bit 6 + UINT8 FMA4:1; ///< byte 1 bit 7 + UINT8 FPU:1; ///< byte 2 bit 0 + UINT8 FXSR:1; ///< byte 2 bit 1 + UINT8 HTT:1; ///< byte 2 bit 2 + UINT8 IBS:1; ///< byte 2 bit 3 + UINT8 LahfSahf:1; ///< byte 2 bit 4 + UINT8 LM:1; ///< byte 2 bit 5 + UINT8 LWP:1; ///< byte 2 bit 6 + UINT8 MCA:1; ///< byte 2 bit 7 + UINT8 MCE:1; ///< byte 3 bit 0 + UINT8 MisAlignSse:1; ///< byte 3 bit 1 + UINT8 MMX:1; ///< byte 3 bit 2 + UINT8 MmxExt:1; ///< byte 3 bit 3 + UINT8 Monitor:1; ///< byte 3 bit 4 + UINT8 MSR:1; ///< byte 3 bit 5 + UINT8 MTRR:1; ///< byte 3 bit 6 + UINT8 NodeId:1; ///< byte 3 bit 7 + UINT8 NX:1; ///< byte 4 bit 0 + UINT8 OSVW:1; ///< byte 4 bit 1 + UINT8 OSXSAVE:1; ///< byte 4 bit 2 + UINT8 PAE:1; ///< byte 4 bit 3 + UINT8 Page1GB:1; ///< byte 4 bit 4 + UINT8 PAT:1; ///< byte 4 bit 5 + UINT8 PCLMULQDQ:1; ///< byte 4 bit 6 + UINT8 PGE:1; ///< byte 4 bit 7 + UINT8 POPCNT:1; ///< byte 5 bit 0 + UINT8 PSE:1; ///< byte 5 bit 1 + UINT8 PSE36:1; ///< byte 5 bit 2 + UINT8 RDTSCP:1; ///< byte 5 bit 3 + UINT8 SKINIT:1; ///< byte 5 bit 4 + UINT8 SSE:1; ///< byte 5 bit 5 + UINT8 SSE2:1; ///< byte 5 bit 6 + UINT8 SSE3:1; ///< byte 5 bit 7 + UINT8 SSE4A:1; ///< byte 6 bit 0 + UINT8 SSE41:1; ///< byte 6 bit 1 + UINT8 SSE42:1; ///< byte 6 bit 2 + UINT8 SSE5:1; ///< byte 6 bit 3 + UINT8 SSSE3:1; ///< byte 6 bit 4 + UINT8 SVM:1; ///< byte 6 bit 5 + UINT8 SysCallSysRet:1; ///< byte 6 bit 6 + UINT8 SysEnterSysExit:1; ///< byte 6 bit 7 + UINT8 bit56 :1; ///< byte 7 bit 0 + UINT8 TCE:1; ///< byte 7 bit 1 + UINT8 ThreeDNow:1; ///< byte 7 bit 2 + UINT8 ThreeDNowExt:1; ///< byte 7 bit 3 + UINT8 ThreeDNowPrefetch:1; ///< byte 7 bit 4 + UINT8 TimeStampCounter:1; ///< byte 7 bit 5 + UINT8 VME:1; ///< byte 7 bit 6 + UINT8 WDT:1; ///< byte 7 bit 7 + UINT8 X2APIC:1; ///< byte 8 bit 0 + UINT8 XOP:1; ///< byte 8 bit 1 + UINT8 XSAVE:1; ///< byte 8 bit 2 + UINT8 Reserve:5; ///< Reserved +} CPU_FEATURES_LIST; + +//---------------------------------------------------------------------------- +// POST INIT TYPEDEFS, STRUCTURES, ENUMS +// +//---------------------------------------------------------------------------- +/// BSC to AP MSR sync up +typedef struct { + UINT32 RegisterAddress; ///< MSR Address + UINT64 RegisterValue; ///< BSC's MSR Value +} BSC_AP_MSR_SYNC; + +/** + * Set Cache Flush On Halt Register. + * + * @CpuServiceInstances + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +typedef VOID (F_CPU_SET_CFOH_REG) ( + IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices, + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + + /// Reference to a Method. +typedef F_CPU_SET_CFOH_REG *PF_CPU_SET_CFOH_REG; + +/** + * Provide the interface to the Cache Flush On Halt Family Specific Services. + * + * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). + * Each supported Family must provide an implementation for all methods in this interface, even if the + * implementation is a CommonReturn(). + */ +struct _CPU_CFOH_FAMILY_SERVICES { // See forward reference above + UINT16 Revision; ///< Interface version + // Public Methods. + PF_CPU_SET_CFOH_REG SetCacheFlushOnHaltRegister; ///< Method: Set Cache Flush On Halt register. +}; + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ + +// These are P U B L I C functions, used by IBVs +AGESA_STATUS +AmdCpuPost ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig + ); + +// These are P U B L I C functions, used by AGESA + +VOID +FeatureLeveling ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +CopyHeapToTempRamAtPost ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +SyncApMsrsToBsc ( + IN OUT BSC_AP_MSR_SYNC *ApMsrSync, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +FinalizeAtPost ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +SetCoresTscFreqSel ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GetPstateGatherDataAddressAtPost ( + OUT UINT64 **Ptr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +SyncAllApMtrrToBsc ( + IN VOID *MtrrTable, + IN AMD_CONFIG_PARAMS *StdHeader + ); +#endif // _CPU_POST_INIT_H_ + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmt.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmt.c new file mode 100644 index 0000000..52e8e1e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmt.c @@ -0,0 +1,302 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Power Management functions. + * + * Contains code for doing early power management + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + **************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "cpuRegisters.h" +#include "cpuFamilyTranslation.h" +#include "OptionMultiSocket.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "cpuPowerMgmtSystemTables.h" +#include "cpuServices.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_CPUPOWERMGMT_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +PerformThisPmStep ( + IN VOID *Step, + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr + ); + +VOID +STATIC +GoToMemInitPstateCore0 ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr + ); + +VOID +STATIC +GoToMemInitPstateCore ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; + +/*---------------------------------------------------------------------------------------*/ +/** + * Perform the "BIOS Requirements for P-State Initialization and Transitions." + * + * This is the generic arbiter code to be executed by the BSC. The system power + * management init tables will be traversed. This must be run by the system BSC + * only. + * + * @param[in] CpuEarlyParams Required input parameters for early CPU initialization + * @param[in] StdHeader Config handle for library and services + * + * @return Most severe AGESA_STATUS level that any system processor encountered + * + */ +AGESA_STATUS +PmInitializationAtEarly ( + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + UINT8 NumberOfSystemWideSteps; + AP_TASK TaskPtr; + AGESA_STATUS ReturnCode; + WARM_RESET_REQUEST Request; + + // Determine the number of steps to perform + OptionMultiSocketConfiguration.GetNumberOfSystemPmSteps (&NumberOfSystemWideSteps, StdHeader); + + // Traverse the PM init table + TaskPtr.FuncAddress.PfApTaskIC = PerformThisPmStep; + TaskPtr.DataTransfer.DataSizeInDwords = 1; + TaskPtr.DataTransfer.DataPtr = &i; + TaskPtr.DataTransfer.DataTransferFlags = 0; + TaskPtr.ExeFlags = PASS_EARLY_PARAMS; + for (i = 0; i < NumberOfSystemWideSteps; ++i) { + IDS_HDT_CONSOLE (CPU_TRACE, " Perform PM init step %d\n", i); + OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, CpuEarlyParams); + } + + // GoToMemInitPstateCore0 only if there is no pending warm reset. + GetWarmResetFlag (StdHeader, &Request); + if (Request.RequestBit == FALSE) { + TaskPtr.FuncAddress.PfApTaskC = GoToMemInitPstateCore0; + TaskPtr.DataTransfer.DataSizeInDwords = 0; + TaskPtr.ExeFlags = PASS_EARLY_PARAMS; + IDS_HDT_CONSOLE (CPU_TRACE, " Transition all cores to POST P-state\n"); + OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, CpuEarlyParams); + } + + // Retrieve/Process any errors + ReturnCode = OptionMultiSocketConfiguration.BscRetrievePmEarlyInitErrors (StdHeader); + + return (ReturnCode); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Performs the next step in the executing core 0's family specific power + * management table. + * + * This function determines if the input step is valid, and invokes the power + * management step if appropriate. This must be run by processor core 0s only. + * + * @param[in] Step Zero based step number + * @param[in] StdHeader Config handle for library and services + * @param[in] CpuEarlyParamsPtr Required input parameters for early CPU initialization + * + */ +VOID +STATIC +PerformThisPmStep ( + IN VOID *Step, + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr + ) +{ + UINT8 MyNumberOfSteps; + UINT32 ExeResetFlags; + SYS_PM_TBL_STEP *FamilyTablePtr; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + BOOLEAN ThisIsWarmReset; + BOOLEAN NoResetLimit; + BOOLEAN NotConflictResetLimit; + BOOLEAN WarmResetOnly; + BOOLEAN ColdResetOnly; + + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, (CONST VOID **) &FamilyTablePtr, &MyNumberOfSteps, StdHeader); + + if (*(UINT8 *)Step < MyNumberOfSteps) { + if (FamilyTablePtr[*(UINT8 *)Step].FuncPtr != NULL) { + ExeResetFlags = FamilyTablePtr[*(UINT8 *)Step].ExeFlags & (PM_EXEFLAGS_COLD_ONLY | PM_EXEFLAGS_WARM_ONLY); + ThisIsWarmReset = IsWarmReset (StdHeader); + NoResetLimit = (ExeResetFlags == 0) ? TRUE : FALSE; + NotConflictResetLimit = (BOOLEAN) (ExeResetFlags != (PM_EXEFLAGS_COLD_ONLY | PM_EXEFLAGS_WARM_ONLY)); + WarmResetOnly = (BOOLEAN) ((ExeResetFlags & PM_EXEFLAGS_WARM_ONLY) == PM_EXEFLAGS_WARM_ONLY); + ColdResetOnly = (BOOLEAN) ((ExeResetFlags & PM_EXEFLAGS_COLD_ONLY) == PM_EXEFLAGS_COLD_ONLY); + + IDS_HDT_CONSOLE (CPU_TRACE, " \tIsWarmReset = %d.\n", ThisIsWarmReset); + IDS_HDT_CONSOLE (CPU_TRACE, " \tNoResetLimit = %d\n", NoResetLimit); + IDS_HDT_CONSOLE (CPU_TRACE, " \tNotConflictResetLimit = %d\n", NotConflictResetLimit); + IDS_HDT_CONSOLE (CPU_TRACE, " \tWarmResetOnly = %d\n", WarmResetOnly); + IDS_HDT_CONSOLE (CPU_TRACE, " \tColdResetOnly = %d\n", ColdResetOnly); + + ASSERT (NotConflictResetLimit); + + if (NoResetLimit || + (NotConflictResetLimit && + ((WarmResetOnly && ThisIsWarmReset) || (ColdResetOnly && !ThisIsWarmReset)))) { + FamilyTablePtr[*(UINT8 *)Step].FuncPtr (FamilySpecificServices, CpuEarlyParamsPtr, StdHeader); + } else { + IDS_HDT_CONSOLE (CPU_TRACE, " \t\tThis PM init step was skipped!\n"); + } + } + } +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Transitions the executing processor to the desired P-state. + * + * This function implements the AMD_CPU_EARLY_PARAMS.MemInitPState parameter, and is + * run by all processor core 0s. + * + * @param[in] StdHeader Config handle for library and services + * @param[in] CpuEarlyParamsPtr Required input parameters for early CPU initialization + * + */ +VOID +STATIC +GoToMemInitPstateCore0 ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr + ) +{ + AP_TASK TaskPtr; + + TaskPtr.FuncAddress.PfApTaskC = GoToMemInitPstateCore; + TaskPtr.DataTransfer.DataSizeInDwords = 0; + TaskPtr.ExeFlags = WAIT_FOR_CORE | PASS_EARLY_PARAMS; + ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Transitions the executing core to the desired P-state. + * + * This function implements the AMD_CPU_EARLY_PARAMS.MemInitPState parameter, and is + * run by all system cores. + * + * @param[in] StdHeader Config handle for library and services + * @param[in] CpuEarlyParamsPtr Required input parameters for early CPU initialization + * + */ +VOID +STATIC +GoToMemInitPstateCore ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr + ) +{ + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->TransitionPstate (FamilySpecificServices, CpuEarlyParamsPtr->MemInitPState, (BOOLEAN) FALSE, StdHeader); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtMultiSocket.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtMultiSocket.c new file mode 100644 index 0000000..fb3d08e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtMultiSocket.c @@ -0,0 +1,613 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Power Management Multisocket Functions. + * + * Contains code for doing power management for multisocket CPUs + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "GeneralServices.h" +#include "cpuServices.h" +#include "cpuApicUtilities.h" +#include "cpuFamilyTranslation.h" +#include "cpuPowerMgmtSystemTables.h" +#include "cpuPowerMgmtMultiSocket.h" +#include "GeneralServices.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_CPUPOWERMGMTMULTISOCKET_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +GetNextEvent ( + IN OUT VOID *EventLogEntryPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Multisocket BSC call to start all system core 0s to perform a standard AP_TASK. + * + * This function loops through all possible socket locations, starting core 0 of + * each populated socket to perform the passed in AP_TASK. After starting all + * other core 0s, the BSC will perform the AP_TASK as well. This must be run by + * the system BSC only. + * + * @param[in] TaskPtr Function descriptor + * @param[in] StdHeader Config handle for library and services + * @param[in] ConfigParams AMD entry point's CPU parameter structure + * + * @return The most severe error code from AP_TASK + * + */ +AGESA_STATUS +RunCodeOnAllSystemCore0sMulti ( + IN AP_TASK *TaskPtr, + IN AMD_CONFIG_PARAMS *StdHeader, + IN VOID *ConfigParams + ) +{ + UINT32 BscSocket; + UINT32 BscModule; + UINT32 BscCoreNum; + UINT8 Socket; + UINT32 NumberOfSockets; + AGESA_STATUS DummyStatus; + AGESA_STATUS AgesaStatus; + AGESA_STATUS CalledStatus; + + + ASSERT (IsBsp (StdHeader, &DummyStatus)); + + NumberOfSockets = GetPlatformNumberOfSockets (); + + IdentifyCore (StdHeader, &BscSocket, &BscModule, &BscCoreNum, &DummyStatus); + AgesaStatus = AGESA_SUCCESS; + + for (Socket = 0; Socket < NumberOfSockets; Socket++) { + if (Socket != BscSocket) { + if (IsProcessorPresent (Socket, StdHeader)) { + CalledStatus = ApUtilRunCodeOnSocketCore (Socket, 0, TaskPtr, StdHeader); + if (CalledStatus > AgesaStatus) { + AgesaStatus = CalledStatus; + } + } + } + } + CalledStatus = ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, ConfigParams); + if (CalledStatus > AgesaStatus) { + AgesaStatus = CalledStatus; + } + + return AgesaStatus; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Multisocket BSC call to determine the maximum number of steps that any single + * processor needs to execute. + * + * This function loops through all possible socket locations, gathering the number + * of power management steps each populated socket requires, and returns the + * highest number. + * + * @param[out] NumSystemSteps Maximum number of system steps required + * @param[in] StdHeader Config handle for library and services + * + */ +VOID +GetNumberOfSystemPmStepsPtrMulti ( + OUT UINT8 *NumSystemSteps, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 NumberOfSteps; + UINT32 NumberOfSockets; + UINT32 Socket; + SYS_PM_TBL_STEP *Ignored; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + NumberOfSockets = GetPlatformNumberOfSockets (); + *NumSystemSteps = 0; + + for (Socket = 0; Socket < NumberOfSockets; Socket++) { + if (IsProcessorPresent (Socket, StdHeader)) { + GetCpuServicesOfSocket (Socket, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, (CONST VOID **) &Ignored, &NumberOfSteps, StdHeader); + if (NumberOfSteps > *NumSystemSteps) { + *NumSystemSteps = NumberOfSteps; + } + } + } +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Multisocket call to determine the frequency that the northbridges must run. + * + * This function loops through all possible socket locations, comparing the + * maximum NB frequencies to determine the slowest. This function also + * determines if all coherent NB frequencies are equivalent. + * + * @param[in] NbPstate NB P-state number to check (0 = fastest) + * @param[in] PlatformConfig Platform profile/build option config structure. + * @param[out] SystemNbCofNumerator NB frequency numerator for the system in MHz + * @param[out] SystemNbCofDenominator NB frequency denominator for the system + * @param[out] SystemNbCofsMatch Whether or not all NB frequencies are equivalent + * @param[out] NbPstateIsEnabledOnAllCPUs Whether or not NbPstate is valid on all CPUs + * @param[in] StdHeader Config handle for library and services + * + * @retval TRUE At least one processor has NbPstate enabled. + * @retval FALSE NbPstate is disabled on all CPUs + * + */ +BOOLEAN +GetSystemNbCofMulti ( + IN UINT32 NbPstate, + IN PLATFORM_CONFIGURATION *PlatformConfig, + OUT UINT32 *SystemNbCofNumerator, + OUT UINT32 *SystemNbCofDenominator, + OUT BOOLEAN *SystemNbCofsMatch, + OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Socket; + UINT8 Module; + UINT32 CurrentNbCof; + UINT32 CurrentDivisor; + UINT32 CurrentFreq; + UINT32 LowFrequency; + UINT32 Ignored32; + BOOLEAN FirstCofNotFound; + BOOLEAN NbPstateDisabled; + BOOLEAN IsNbPstateEnabledOnAny; + PCI_ADDR PciAddress; + AGESA_STATUS Ignored; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + // Find the slowest NB COF in the system & whether or not all are equivalent + LowFrequency = 0xFFFFFFFF; + *SystemNbCofsMatch = TRUE; + *NbPstateIsEnabledOnAllCPUs = FALSE; + IsNbPstateEnabledOnAny = FALSE; + FirstCofNotFound = TRUE; + NbPstateDisabled = FALSE; + for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { + if (IsProcessorPresent (Socket, StdHeader)) { + GetCpuServicesOfSocket (Socket, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { + if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &Ignored)) { + break; + } + } + if (FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices, + PlatformConfig, + &PciAddress, + NbPstate, + &CurrentNbCof, + &CurrentDivisor, + &Ignored32, + StdHeader)) { + ASSERT (CurrentDivisor != 0); + CurrentFreq = (CurrentNbCof / CurrentDivisor); + if (FirstCofNotFound) { + *SystemNbCofNumerator = CurrentNbCof; + *SystemNbCofDenominator = CurrentDivisor; + LowFrequency = CurrentFreq; + IsNbPstateEnabledOnAny = TRUE; + if (!NbPstateDisabled) { + *NbPstateIsEnabledOnAllCPUs = TRUE; + } + FirstCofNotFound = FALSE; + } else { + if (CurrentFreq != LowFrequency) { + *SystemNbCofsMatch = FALSE; + if (CurrentFreq < LowFrequency) { + LowFrequency = CurrentFreq; + *SystemNbCofNumerator = CurrentNbCof; + *SystemNbCofDenominator = CurrentDivisor; + } + } + } + } else { + NbPstateDisabled = TRUE; + *NbPstateIsEnabledOnAllCPUs = FALSE; + } + } + } + return IsNbPstateEnabledOnAny; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Multisocket call to determine if the BIOS is responsible for updating the + * northbridge operating frequency and voltage. + * + * This function loops through all possible socket locations, checking whether + * any populated sockets require NB COF VID programming. + * + * @param[in] StdHeader Config handle for library and services + * + * @retval TRUE BIOS needs to set up NB frequency and voltage + * @retval FALSE BIOS does not need to set up NB frequency and voltage + * + */ +BOOLEAN +GetSystemNbCofVidUpdateMulti ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 Module; + UINT32 Socket; + UINT32 NumberOfSockets; + BOOLEAN IgnoredBool; + BOOLEAN AtLeast1RequiresUpdate; + PCI_ADDR PciAddress; + AGESA_STATUS Ignored; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + NumberOfSockets = GetPlatformNumberOfSockets (); + + AtLeast1RequiresUpdate = FALSE; + for (Socket = 0; Socket < NumberOfSockets; Socket++) { + if (IsProcessorPresent (Socket, StdHeader)) { + GetCpuServicesOfSocket (Socket, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { + if (GetPciAddress (StdHeader, (UINT8) Socket, Module, &PciAddress, &Ignored)) { + break; + } + } + if (FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &IgnoredBool, StdHeader)) { + AtLeast1RequiresUpdate = TRUE; + break; + } + } + } + return AtLeast1RequiresUpdate; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Multisocket call to determine the most severe AGESA_STATUS return value after + * processing the power management initialization tables. + * + * This function loops through all possible socket locations, collecting any + * power management initialization errors that may have occurred. These errors + * are transferred from the core 0s of the socket in which the errors occurred + * to the BSC's heap. The BSC's heap is then searched for the most severe error + * that occurred, and returns it. This function must be called by the BSC only. + * + * @param[in] StdHeader Config handle for library and services + * + * @return The most severe error code from power management init + * + */ +AGESA_STATUS +GetEarlyPmErrorsMulti ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT16 i; + UINT32 BscSocket; + UINT32 BscModule; + UINT32 BscCoreNum; + UINT32 Socket; + UINT32 NumberOfSockets; + AP_TASK TaskPtr; + AGESA_EVENT EventLogEntry; + AGESA_STATUS ReturnCode; + AGESA_STATUS DummyStatus; + + ASSERT (IsBsp (StdHeader, &ReturnCode)); + + ReturnCode = AGESA_SUCCESS; + EventLogEntry.EventClass = AGESA_SUCCESS; + EventLogEntry.EventInfo = 0; + EventLogEntry.DataParam1 = 0; + EventLogEntry.DataParam2 = 0; + EventLogEntry.DataParam3 = 0; + EventLogEntry.DataParam4 = 0; + + NumberOfSockets = GetPlatformNumberOfSockets (); + IdentifyCore (StdHeader, &BscSocket, &BscModule, &BscCoreNum, &DummyStatus); + + TaskPtr.FuncAddress.PfApTaskI = GetNextEvent; + TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (AGESA_EVENT); + TaskPtr.DataTransfer.DataPtr = &EventLogEntry; + TaskPtr.DataTransfer.DataTransferFlags = 0; + TaskPtr.ExeFlags = WAIT_FOR_CORE | RETURN_PARAMS; + for (Socket = 0; Socket < NumberOfSockets; Socket++) { + if (Socket != BscSocket) { + if (IsProcessorPresent (Socket, StdHeader)) { + do { + ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8) 0, &TaskPtr, StdHeader); + if ((EventLogEntry.EventInfo & CPU_EVENT_PM_EVENT_MASK) == CPU_EVENT_PM_EVENT_CLASS) { + PutEventLog ( + EventLogEntry.EventClass, + EventLogEntry.EventInfo, + EventLogEntry.DataParam1, + EventLogEntry.DataParam2, + EventLogEntry.DataParam3, + EventLogEntry.DataParam4, + StdHeader + ); + } + } while (EventLogEntry.EventInfo != 0); + } + } + } + + for (i = 0; PeekEventLog (&EventLogEntry, i, StdHeader); i++) { + if ((EventLogEntry.EventInfo & CPU_EVENT_PM_EVENT_MASK) == CPU_EVENT_PM_EVENT_CLASS) { + if (EventLogEntry.EventClass > ReturnCode) { + ReturnCode = EventLogEntry.EventClass; + } + } + } + return (ReturnCode); +} + +/** + * Multisocket call to loop through all possible socket locations and Nb Pstates, + * comparing the NB frequencies to determine the slowest system and P0 frequency + * + * @param[in] PlatformConfig Platform profile/build option config structure. + * @param[out] MinSysNbFreq NB frequency numerator for the system in MHz + * @param[out] MinP0NbFreq NB frequency numerator for P0 in MHz + * @param[in] StdHeader Config handle for library and services + */ +VOID +GetMinNbCofMulti ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + OUT UINT32 *MinSysNbFreq, + OUT UINT32 *MinP0NbFreq, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Socket; + UINT32 Module; + UINT32 CurrMinFreq; + UINT32 CurrMaxFreq; + PCI_ADDR PciAddress; + AGESA_STATUS Ignored; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + AGESA_STATUS AgesaStatus; + + *MinSysNbFreq = 0xFFFFFFFF; + *MinP0NbFreq = 0xFFFFFFFF; + + for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { + if (IsProcessorPresent (Socket, StdHeader)) { + GetCpuServicesOfSocket (Socket, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { + if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &Ignored )) { + break; + } + } + + + AgesaStatus = FamilySpecificServices->GetMinMaxNbFrequency (FamilySpecificServices, + PlatformConfig, + &PciAddress, + &CurrMinFreq, + &CurrMaxFreq, + StdHeader); + ASSERT (AgesaStatus == AGESA_SUCCESS); + ASSERT ((CurrMinFreq != 0) && (CurrMaxFreq != 0)); + // Determine the slowest NB Pmin frequency + if (CurrMinFreq < *MinSysNbFreq) { + *MinSysNbFreq = CurrMinFreq; + } + + // Determine the slowest NB P0 frequency + if (CurrMaxFreq < *MinP0NbFreq) { + *MinP0NbFreq = CurrMaxFreq; + } + } + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Get PCI Config Space Address for the current running core. + * + * @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0) + * @param[in] StdHeader Header for library and services. + * + * @retval TRUE The core is present, PCI Address valid + * @retval FALSE The core is not present, PCI Address not valid. + */ +BOOLEAN +GetCurrPciAddrMulti ( + OUT PCI_ADDR *PciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 Node; + UINT32 Socket; + UINT32 Module; + UINT32 Core; + BOOLEAN Result; + AGESA_STATUS IgnoredSts; + + Result = TRUE; + + IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); + + ASSERT (Socket < MAX_SOCKETS); + ASSERT (Module < MAX_DIES); + + if (GetNodeId (Socket, Module, &Node, StdHeader)) { + // Socket is populated + PciAddress->AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0); + PciAddress->Address.Device = PciAddress->Address.Device + Node; + } else { + // Socket is not populated + PciAddress->AddressValue = ILLEGAL_SBDFO; + Result = FALSE; + } + + return Result; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Writes to all nodes on the executing core's socket. + * + * @param[in] PciAddress The Function and Register to update + * @param[in] Mask The bitwise AND mask to apply to the current register value + * @param[in] Data The bitwise OR mask to apply to the current register value + * @param[in] StdHeader Header for library and services. + * + */ +VOID +ModifyCurrSocketPciMulti ( + IN PCI_ADDR *PciAddress, + IN UINT32 Mask, + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Socket; + UINT32 Module; + UINT32 Core; + UINT32 LocalPciRegister; + AGESA_STATUS AgesaStatus; + PCI_ADDR Reg; + + IdentifyCore (StdHeader, &Socket, &Module, &Core, &AgesaStatus); + + for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) { + if (GetPciAddress (StdHeader, Socket, Module, &Reg, &AgesaStatus)) { + Reg.Address.Function = PciAddress->Address.Function; + Reg.Address.Register = PciAddress->Address.Register; + LibAmdPciRead (AccessWidth32, Reg, &LocalPciRegister, StdHeader); + LocalPciRegister &= Mask; + LocalPciRegister |= Data; + LibAmdPciWrite (AccessWidth32, Reg, &LocalPciRegister, StdHeader); + } + } +} + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * AP task to return the next event log entry to the BSC. + * + * This function calls to the event log manager to retrieve the next error out + * of the heap. + * + * @param[out] EventLogEntryPtr The AP's next event log entry + * @param[in] StdHeader Config handle for library and services + * + */ +VOID +STATIC +GetNextEvent ( + IN OUT VOID *EventLogEntryPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GetEventLog ((AGESA_EVENT *) EventLogEntryPtr, StdHeader); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtMultiSocket.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtMultiSocket.h new file mode 100644 index 0000000..3298b6b --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtMultiSocket.h @@ -0,0 +1,153 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Power Management Multisocket Functions. + * + * Contains code for doing power management for multisocket CPUs + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_POWER_MGMT_MULTI_SOCKET_H_ +#define _CPU_POWER_MGMT_MULTI_SOCKET_H_ + + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ +AGESA_STATUS +RunCodeOnAllSystemCore0sMulti ( + IN AP_TASK *TaskPtr, + IN AMD_CONFIG_PARAMS *StdHeader, + IN VOID *ConfigParams + ); + +VOID +GetNumberOfSystemPmStepsPtrMulti ( + OUT UINT8 *NumSystemSteps, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GetSystemNbCofMulti ( + IN UINT32 NbPstate, + IN PLATFORM_CONFIGURATION *PlatformConfig, + OUT UINT32 *SystemNbCofNumerator, + OUT UINT32 *SystemNbCofDenominator, + OUT BOOLEAN *SystemNbCofsMatch, + OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GetSystemNbCofVidUpdateMulti ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GetMinNbCofMulti ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + OUT UINT32 *MinSysNbFreq, + OUT UINT32 *MinP0NbFreq, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GetCurrPciAddrMulti ( + OUT PCI_ADDR *PciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +ModifyCurrSocketPciMulti ( + IN PCI_ADDR *PciAddress, + IN UINT32 Mask, + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GetEarlyPmErrorsMulti ( + IN AMD_CONFIG_PARAMS *StdHeader + ); +#endif // _CPU_POWER_MGMT_MULTI_SOCKET_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtSingleSocket.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtSingleSocket.c new file mode 100644 index 0000000..1ed05a6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtSingleSocket.c @@ -0,0 +1,359 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Power Management Single Socket Functions. + * + * Contains code for doing power management for single socket CPU + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "GeneralServices.h" +#include "cpuRegisters.h" +#include "cpuApicUtilities.h" +#include "cpuFamilyTranslation.h" +#include "cpuPowerMgmtSystemTables.h" +#include "cpuPowerMgmtSingleSocket.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_CPUPOWERMGMTSINGLESOCKET_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Single socket BSC call to start all system core 0s to perform a standard AP_TASK. + * + * This function will simply invoke the task on the executing core. This must be + * run by the system BSC only. + * + * @param[in] TaskPtr Function descriptor + * @param[in] StdHeader Config handle for library and services + * @param[in] ConfigParams AMD entry point's CPU parameter structure + * + * @return The severe error code from AP_TASK + * + */ +AGESA_STATUS +RunCodeOnAllSystemCore0sSingle ( + IN AP_TASK *TaskPtr, + IN AMD_CONFIG_PARAMS *StdHeader, + IN VOID *ConfigParams + ) +{ + AGESA_STATUS CalledStatus; + + CalledStatus = ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, ConfigParams); + return CalledStatus; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Single socket BSC call to determine the maximum number of steps that any single + * processor needs to execute. + * + * This function simply returns the number of steps that the BSC needs. + * + * @param[out] NumSystemSteps Maximum number of system steps required + * @param[in] StdHeader Config handle for library and services + * + */ +VOID +GetNumberOfSystemPmStepsPtrSingle ( + OUT UINT8 *NumSystemSteps, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + SYS_PM_TBL_STEP *Ignored; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, (CONST VOID **) &Ignored, NumSystemSteps, StdHeader); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Single socket call to determine the frequency that the northbridges must run. + * + * This function simply returns the executing core's NB frequency, and that all + * NB frequencies are equivalent. + * + * @param[in] NbPstate NB P-state number to check (0 = fastest) + * @param[in] PlatformConfig Platform profile/build option config structure. + * @param[out] SystemNbCofNumerator NB frequency numerator for the system in MHz + * @param[out] SystemNbCofDenominator NB frequency denominator for the system + * @param[out] SystemNbCofsMatch Whether or not all NB frequencies are equivalent + * @param[out] NbPstateIsEnabledOnAllCPUs Whether or not NbPstate is valid on all CPUs + * @param[in] StdHeader Config handle for library and services + * + * @retval TRUE At least one processor has NbPstate enabled. + * @retval FALSE NbPstate is disabled on all CPUs + * + */ +BOOLEAN +GetSystemNbCofSingle ( + IN UINT32 NbPstate, + IN PLATFORM_CONFIGURATION *PlatformConfig, + OUT UINT32 *SystemNbCofNumerator, + OUT UINT32 *SystemNbCofDenominator, + OUT BOOLEAN *SystemNbCofsMatch, + OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Ignored; + PCI_ADDR PciAddress; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0); + *SystemNbCofsMatch = TRUE; + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + *NbPstateIsEnabledOnAllCPUs = FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices, + PlatformConfig, + &PciAddress, + NbPstate, + SystemNbCofNumerator, + SystemNbCofDenominator, + &Ignored, + StdHeader); + return *NbPstateIsEnabledOnAllCPUs; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Single socket call to determine if the BIOS is responsible for updating the + * northbridge operating frequency and voltage. + * + * This function simply returns whether or not the executing core needs NB COF + * VID programming. + * + * @param[in] StdHeader Config handle for library and services + * + * @retval TRUE BIOS needs to set up NB frequency and voltage + * @retval FALSE BIOS does not need to set up NB frequency and voltage + * + */ +BOOLEAN +GetSystemNbCofVidUpdateSingle ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + BOOLEAN Ignored; + PCI_ADDR PciAddress; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0); + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + return (FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &Ignored, StdHeader)); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Single socket call to determine the most severe AGESA_STATUS return value after + * processing the power management initialization tables. + * + * This function searches the event log for the most severe error and returns + * the status code. This function must be called by the BSC only. + * + * @param[in] StdHeader Config handle for library and services + * + * @return The most severe error code from power management init + * + */ +AGESA_STATUS +GetEarlyPmErrorsSingle ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT16 i; + AGESA_EVENT EventLogEntry; + AGESA_STATUS ReturnCode; + + ASSERT (IsBsp (StdHeader, &ReturnCode)); + + ReturnCode = AGESA_SUCCESS; + for (i = 0; PeekEventLog (&EventLogEntry, i, StdHeader); i++) { + if ((EventLogEntry.EventInfo & CPU_EVENT_PM_EVENT_MASK) == CPU_EVENT_PM_EVENT_CLASS) { + if (EventLogEntry.EventClass > ReturnCode) { + ReturnCode = EventLogEntry.EventClass; + } + } + } + + return (ReturnCode); +} + +/** + * Single socket call to loop through all Nb Pstates, comparing the NB frequencies + * to determine the slowest in the system. This routine also returns the NB P0 frequency. + * + * @param[in] PlatformConfig Platform profile/build option config structure. + * @param[out] MinSysNbFreq NB frequency numerator for the system in MHz + * @param[out] MinP0NbFreq NB frequency numerator for P0 in MHz + * @param[in] StdHeader Config handle for library and services + */ +VOID +GetMinNbCofSingle ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + OUT UINT32 *MinSysNbFreq, + OUT UINT32 *MinP0NbFreq, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + AGESA_STATUS AgesaStatus; + + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0); + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + AgesaStatus = FamilySpecificServices->GetMinMaxNbFrequency (FamilySpecificServices, + PlatformConfig, + &PciAddress, + MinSysNbFreq, + MinP0NbFreq, + StdHeader); + ASSERT (AgesaStatus == AGESA_SUCCESS); + ASSERT ((MinSysNbFreq != 0) && (MinP0NbFreq != 0)); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Get PCI Config Space Address for the current running core. + * + * @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0) + * @param[in] StdHeader Header for library and services. + * + * @retval TRUE The core is present, PCI Address valid + * @retval FALSE The core is not present, PCI Address not valid. + */ +BOOLEAN +GetCurrPciAddrSingle ( + OUT PCI_ADDR *PciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PciAddress->AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0); + + return TRUE; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Writes to all nodes on the executing core's socket. + * + * @param[in] PciAddress The Function and Register to update + * @param[in] Mask The bitwise AND mask to apply to the current register value + * @param[in] Data The bitwise OR mask to apply to the current register value + * @param[in] StdHeader Header for library and services. + * + */ +VOID +ModifyCurrSocketPciSingle ( + IN PCI_ADDR *PciAddress, + IN UINT32 Mask, + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 LocalPciRegister; + PCI_ADDR Reg; + + Reg.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0); + Reg.Address.Function = PciAddress->Address.Function; + Reg.Address.Register = PciAddress->Address.Register; + LibAmdPciRead (AccessWidth32, Reg, &LocalPciRegister, StdHeader); + LocalPciRegister &= Mask; + LocalPciRegister |= Data; + LibAmdPciWrite (AccessWidth32, Reg, &LocalPciRegister, StdHeader); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtSingleSocket.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtSingleSocket.h new file mode 100644 index 0000000..3572d07 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtSingleSocket.h @@ -0,0 +1,154 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Power Management Single Socket Functions. + * + * Contains code for doing power management for single socket CPU + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_POWER_MGMT_SINGLE_SOCKET_H_ +#define _CPU_POWER_MGMT_SINGLE_SOCKET_H_ + + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ +AGESA_STATUS +RunCodeOnAllSystemCore0sSingle ( + IN AP_TASK *TaskPtr, + IN AMD_CONFIG_PARAMS *StdHeader, + IN VOID *ConfigParams + ); + +VOID +GetNumberOfSystemPmStepsPtrSingle ( + OUT UINT8 *NumSystemSteps, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GetSystemNbCofSingle ( + IN UINT32 NbPstate, + IN PLATFORM_CONFIGURATION *PlatformConfig, + OUT UINT32 *SystemNbCofNumerator, + OUT UINT32 *SystemNbCofDenominator, + OUT BOOLEAN *SystemNbCofsMatch, + OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GetSystemNbCofVidUpdateSingle ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GetMinNbCofSingle ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + OUT UINT32 *MinSysNbFreq, + OUT UINT32 *MinP0NbFreq, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GetCurrPciAddrSingle ( + OUT PCI_ADDR *PciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +ModifyCurrSocketPciSingle ( + IN PCI_ADDR *PciAddress, + IN UINT32 Mask, + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GetEarlyPmErrorsSingle ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif // _CPU_POWER_MGMT_SINGLE_SOCKET_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtSystemTables.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtSystemTables.h new file mode 100644 index 0000000..be5f341 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPowerMgmtSystemTables.h @@ -0,0 +1,120 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Power Management Table declarations. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_POWER_MGMT_SYSTEM_TABLES_H_ +#define _CPU_POWER_MGMT_SYSTEM_TABLES_H_ + + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ +#define PM_EXEFLAGS_WARM_ONLY 0x00000001ul /* Skip step if set && cold reset */ +#define PM_EXEFLAGS_COLD_ONLY 0x00000002ul /* Skip step if set && warm reset */ +#define PM_EXEFLAGS_NOT_ON_S3 0x00000004ul /* Skip step if S3 resume */ +#define PM_EXEFLAGS_SYSTEM_TASK 0x00000008ul /* Future use */ +#define PM_EXEFLAGS_SERIAL_EXE 0x00000010ul /* BSC will wait for remote core 0 to complete the step*/ + + +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ +typedef VOID F_PM_STEP_FUNCTION ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a Method. +typedef F_PM_STEP_FUNCTION *PF_PM_STEP_FUNCTION; + + +/// A structure representing a step in a power management +/// initialization process to be invoked at AmdInitEarly +typedef struct { + UINT32 ExeFlags; ///< Execution flags + PF_PM_STEP_FUNCTION FuncPtr; ///< Function pointer +} SYS_PM_TBL_STEP; + + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ + + +#endif // _CPU_POWER_MGMT_SYSTEM_TABLES_H_/ + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h new file mode 100644 index 0000000..173044c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h @@ -0,0 +1,441 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Register Table Related Functions + * + * Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 64348 $ @e $Date: 2012-01-19 03:43:52 -0600 (Thu, 19 Jan 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_REGISTERS_H_ +#define _CPU_REGISTERS_H_ + +#include "cpuFamRegisters.h" +/* + *-------------------------------------------------------------- + * + * M O D U L E S U S E D + * + *--------------------------------------------------------------- + */ + +/* + *-------------------------------------------------------------- + * + * D E F I N I T I O N S / M A C R O S + * + *--------------------------------------------------------------- + */ + +#define BIT0 0x0000000000000001ull +#define BIT1 0x0000000000000002ull +#define BIT2 0x0000000000000004ull +#define BIT3 0x0000000000000008ull +#define BIT4 0x0000000000000010ull +#define BIT5 0x0000000000000020ull +#define BIT6 0x0000000000000040ull +#define BIT7 0x0000000000000080ull +#define BIT8 0x0000000000000100ull +#define BIT9 0x0000000000000200ull +#define BIT10 0x0000000000000400ull +#define BIT11 0x0000000000000800ull +#define BIT12 0x0000000000001000ull +#define BIT13 0x0000000000002000ull +#define BIT14 0x0000000000004000ull +#define BIT15 0x0000000000008000ull +#define BIT16 0x0000000000010000ull +#define BIT17 0x0000000000020000ull +#define BIT18 0x0000000000040000ull +#define BIT19 0x0000000000080000ull +#define BIT20 0x0000000000100000ull +#define BIT21 0x0000000000200000ull +#define BIT22 0x0000000000400000ull +#define BIT23 0x0000000000800000ull +#define BIT24 0x0000000001000000ull +#define BIT25 0x0000000002000000ull +#define BIT26 0x0000000004000000ull +#define BIT27 0x0000000008000000ull +#define BIT28 0x0000000010000000ull +#define BIT29 0x0000000020000000ull +#define BIT30 0x0000000040000000ull +#define BIT31 0x0000000080000000ull +#define BIT32 0x0000000100000000ull +#define BIT33 0x0000000200000000ull +#define BIT34 0x0000000400000000ull +#define BIT35 0x0000000800000000ull +#define BIT36 0x0000001000000000ull +#define BIT37 0x0000002000000000ull +#define BIT38 0x0000004000000000ull +#define BIT39 0x0000008000000000ull +#define BIT40 0x0000010000000000ull +#define BIT41 0x0000020000000000ull +#define BIT42 0x0000040000000000ull +#define BIT43 0x0000080000000000ull +#define BIT44 0x0000100000000000ull +#define BIT45 0x0000200000000000ull +#define BIT46 0x0000400000000000ull +#define BIT47 0x0000800000000000ull +#define BIT48 0x0001000000000000ull +#define BIT49 0x0002000000000000ull +#define BIT50 0x0004000000000000ull +#define BIT51 0x0008000000000000ull +#define BIT52 0x0010000000000000ull +#define BIT53 0x0020000000000000ull +#define BIT54 0x0040000000000000ull +#define BIT55 0x0080000000000000ull +#define BIT56 0x0100000000000000ull +#define BIT57 0x0200000000000000ull +#define BIT58 0x0400000000000000ull +#define BIT59 0x0800000000000000ull +#define BIT60 0x1000000000000000ull +#define BIT61 0x2000000000000000ull +#define BIT62 0x4000000000000000ull +#define BIT63 0x8000000000000000ull + +/// CPUID related registers +#define AMD_CPUID_FMF 0x80000001ul // Family Model Features information +#define AMD_CPUID_APICID_LPC_BID 0x00000001ul // Local APIC ID, Logical Processor Count, Brand ID +#define AMD_CPUID_L2L3Cache_L2TLB 0x80000006ul +#define CPUID_ASSOCIATIVITY_DISABLED 0x00 +#define CPUID_ASSOCIATIVITY_1_WAY 0x01 +#define CPUID_ASSOCIATIVITY_2_WAY 0x02 +#define CPUID_ASSOCIATIVITY_4_WAY 0x04 +#define CPUID_ASSOCIATIVITY_8_WAY 0x06 +#define CPUID_ASSOCIATIVITY_16_WAY 0x08 +#define CPUID_ASSOCIATIVITY_32_WAY 0x0A +#define CPUID_ASSOCIATIVITY_48_WAY 0x0B +#define CPUID_ASSOCIATIVITY_64_WAY 0x0C +#define CPUID_ASSOCIATIVITY_96_WAY 0x0D +#define CPUID_ASSOCIATIVITY_128_WAY 0x0E +#define CPUID_ASSOCIATIVITY_FULLY 0x0F +#define AMD_CPUID_TLB_L1Cache 0x80000005ul +#define AMD_CPUID_APM 0x80000007ul +#define LOCAL_APIC_ID 24 +#define LOGICAL_PROCESSOR_COUNT 16 +#define AMD_CPUID_ASIZE_PCCOUNT 0x80000008ul // Address Size, Physical Core Count + +/// CPU Logical ID Transfer +typedef struct { + UINT32 RawId; ///< RawID + UINT64 LogicalId; ///< LogicalID +} CPU_LOGICAL_ID_XLAT; + +/// Logical CPU ID Table +typedef struct { + IN UINT32 Elements; ///< Number of Elements + IN CPU_LOGICAL_ID_XLAT *LogicalIdTable; ///< CPU Logical ID Transfer table Pointer +} LOGICAL_ID_TABLE; + +// MSRs +// ------------------------ +#define MCG_CTL_P 0x00000100ul // bit 8 for MCG_CTL_P under MSRR +#define MSR_MCG_CAP 0x00000179ul +#define MSR_MC0_CTL 0x00000400ul +#define MSR_MC0_STATUS 0x00000401ul +#define MSR_MC5_STATUS 0x00000415ul +#define MSR_MC6_STATUS 0x00000419ul + +#define MSR_APIC_BAR 0x0000001Bul + +#define CPUID_LONG_MODE_ADDR 0x80000008ul +#define AMD_CPUID_FMF 0x80000001ul + +#define MSR_EXTENDED_FEATURE_EN 0xC0000080ul +#define MSR_MC_MISC_LINK_THRESHOLD 0xC0000408ul +#define MSR_MC_MISC_L3_THRESHOLD 0xC0000409ul + +/// Patch Loader Register +typedef struct { + UINT64 PatchBase:32; ///< Linear address of patch header address block + UINT64 SBZ:32; ///< Should be zero +} PATCH_LOADER_MSR; + +#define MSR_SYS_CFG 0xC0010010ul // SYSCFG - F15 Shared +#define MSR_TOM2 0xC001001Dul // TOP_MEM2 - F15 Shared +#define MSR_MC0_CTL_MASK 0xC0010044ul // MC0 Control Mask +#define MSR_MC1_CTL_MASK 0xC0010045ul // MC1 Control Mask +#define MSR_MC2_CTL_MASK 0xC0010046ul // MC2 Control Mask +#define MSR_MC4_CTL_MASK 0xC0010048ul // MC4 Control Mask + +#define MSR_CPUID_FEATS 0xC0011004ul // CPUID Features +#define MSR_CPUID_EXT_FEATS 0xC0011005ul // CPUID Extended Features +#define MSR_HWCR 0xC0010015ul +#define MSR_NB_CFG 0xC001001Ful // NB Config +#define ENABLE_CF8_EXT_CFG 0x00004000ul // [46] +#define INIT_APIC_CPUID_LO 0x00400000ul // [54] +#define MSR_LS_CFG 0xC0011020ul +#define MSR_IC_CFG 0xC0011021ul // ICache Config - F15 Shared +#define MSR_DC_CFG 0xC0011022ul +#define MSR_ME_CFG 0xC0011029ul +#define MSR_CU_CFG 0xC0011023ul // F15 Shared +#define MSR_DE_CFG 0xC0011029ul // F15 Shared +#define MSR_CU_CFG2 0xC001102Aul // F15 Shared +#define MSR_CU_CFG3 0xC001102Bul // F15 Shared +#define MSR_LS_CFG2 0xC001102Dul +#define MSR_IBS_OP_DATA3 0xC0011037ul + + +#define MSR_CPUID_NAME_STRING0 0xC0010030ul // First CPUID namestring register +#define MSR_CPUID_NAME_STRING1 0xC0010031ul +#define MSR_CPUID_NAME_STRING2 0XC0010032ul +#define MSR_CPUID_NAME_STRING3 0xC0010033ul +#define MSR_CPUID_NAME_STRING4 0xC0010034ul +#define MSR_CPUID_NAME_STRING5 0xC0010035ul // Last CPUID namestring register +#define MSR_MMIO_Cfg_Base 0xC0010058ul // MMIO Configuration Base Address Register +#define MSR_BIST 0xC0010060ul // BIST Results register +#define MSR_OSVW_ID_Length 0xC0010140ul +#define MSR_OSVW_Status 0xC0010141ul +#define MSR_NB_PERF_CTL0 0xC0010240ul +#define MSR_NB_PERF_CTR0 0xC0010241ul +#define MSR_NB_PERF_CTL1 0xC0010242ul +#define MSR_NB_PERF_CTR1 0xC0010243ul +#define MSR_NB_PERF_CTL2 0xC0010244ul +#define MSR_NB_PERF_CTR2 0xC0010245ul +#define MSR_NB_PERF_CTL3 0xC0010246ul +#define MSR_NB_PERF_CTR3 0xC0010247ul +#define MSR_PERF_CONTROL3 0xC0010003ul // Perfromance control register number 3 +#define MSR_PERF_COUNTER3 0xC0010007ul // Performance counter register number 3 +#define PERF_RESERVE_BIT_MASK 0x030FFFDFFFFFull // Mask of the Performance control Reserve bits +#define PERF_CAR_CORRUPTION_EVENT 0x040040F0E2ul // Configure the controller to capture the + // CAR Corruption +// FUNC_0 registers +// ---------------- +#define HT_LINK_FREQ_OFFSET 8 // Link HT Frequency from capability base +#define HT_LINK_CONTROL_REG_OFFSET 4 +#define HT_LINK_TYPE_REG_OFFSET 0x18 +#define HT_LINK_EXTENDED_FREQ 0x1C +#define HT_LINK_HOST_CAP_MAX 0x20 // HT Host Capability offsets are less than its size. +#define HT_CAPABILITIES_POINTER 0x34 +#define NODE_ID 0x60 +#define HT_INIT_CTRL 0x6C +#define HT_INIT_CTRL_REQ_DIS 0x02 // [1] = ReqDis +#define HT_INIT_COLD_RST_DET BIT4 +#define HT_INIT_BIOS_RST_DET_0 BIT5 +#define HT_INIT_BIOS_RST_DET_1 BIT9 +#define HT_INIT_BIOS_RST_DET_2 BIT10 +#define HT_INIT_BIOS_RST_DET BIT9 | BIT10 +#define HT_TRANS_CTRL 0x68 +#define HT_TRANS_CTRL_CPU1_EN 0x00000020ul // [5] = CPU1 Enable +#define HT_LINK_CONTROL_0 0x84 +#define HT_LINK_FREQ_0 0x88 // Link HT Frequency +#define EXTENDED_NODE_ID 0x160 +#define ECS_HT_TRANS_CTRL 0x168 +#define ECS_HT_TRANS_CTRL_CPU2_EN 0x00000001ul // [0] = CPU2 Enable +#define ECS_HT_TRANS_CTRL_CPU3_EN 0x00000002ul // [1] = CPU3 Enable +#define ECS_HT_TRANS_CTRL_CPU4_EN 0x00000004ul // [2] = CPU4 Enable +#define ECS_HT_TRANS_CTRL_CPU5_EN 0x00000008ul // [3] = CPU5 Enable + +#define CORE_CTRL 0x1DC +#define CORE_CTRL_CORE1_EN 0x00000002ul +#define CORE_CTRL_CORE2_EN 0x00000004ul +#define CORE_CTRL_CORE3_EN 0x00000008ul +#define CORE_CTRL_CORE4_EN 0x00000010ul +#define CORE_CTRL_CORE5_EN 0x00000020ul +#define CORE_CTRL_CORE6_EN 0x00000040ul +#define CORE_CTRL_CORE7_EN 0x00000080ul +#define CORE_CTRL_CORE8_EN 0x00000100ul +#define CORE_CTRL_CORE9_EN 0x00000200ul + +// FUNC_3 registers +// ---------------- +#define HARDWARE_THERMAL_CTRL_REG 0x64 +#define SOFTWARE_THERMAL_CTRL_REG 0x68 + +#define ACPI_PSC_0_REG 0x80 // ACPI Power State Control Registers +#define ACPI_PSC_4_REG 0x84 + +#define NB_CFG_HIGH_REG 0x8C +#define POWER_CTRL_MISCELLANEOUS_REG 0xA0 +#define CLOCK_POWER_TIMING_CTRL2_REG 0xDC +#define NORTH_BRIDGE_CAPABILITIES_REG 0xE8 +#define MULTI_NODE_CPU 29 +#define CPUID_FMR 0xFC // Family / Model registers +#define DOWNCORE_CTRL 0x190 // Downcore Control Register + +#define LINK_TO_XCS_TOKEN_COUNT_REG_3X148 0x148 +#define REG_HT4_PHY_OFFSET_BASE_4X180 0x180 +#define REG_HT4_PHY_DATA_PORT_BASE_4X184 0x184 + +#define HTPHY_OFFSET_MASK 0xE00001FFul +#define HTPHY_WRITE_CMD 0x40000000ul +#define HTPHY_IS_COMPLETE_MASK 0x80000000ul +#define HTPHY_DIRECT_MAP 0x20000000ul +#define HTPHY_DIRECT_OFFSET_MASK 0x6000FFFFul + +// FUNC_5 registers +// ---------------- +#define COMPUTE_UNIT_STATUS 0x80 +#define NORTH_BRIDGE_CAPABILITIES_2_REG 0x84 + + +// Misc. defines. +#define PCI_DEV_BASE 24 + +#define CPU_STEPPING 0x0000000Ful +#define CPU_MODEL 0x000000F0ul +#define CPU_EMODEL 0x000F0000ul +#define CPU_EFAMILY 0x00F00000ul +#define CPU_FMS_MASK CPU_EFAMILY | CPU_EMODEL | CPU_MODEL | CPU_STEPPING + +#define HTPHY_SELECT 2 +#define PCI_SELECT 1 +#define MSR_SELECT 0 + +#define LOGICAL_ID 1 +#define F_SCHEME 0 +#define DR_SCHEME 1 +#define GR_SCHEME 2 + +#define DR_NO_STRING 0 +#define DR_SOCKET_C32 5 +#define DR_SOCKET_ASB2 4 +#define DR_SOCKET_G34 3 +#define DR_SOCKET_S1G3 2 +#define DR_SOCKET_S1G4 2 +#define DR_SOCKET_AM3 1 +#define DR_SOCKET_1207 0 +#define LN_SOCKET_FM1 2 +#define LN_SOCKET_FS1 1 +#define LN_SOCKET_FP1 0 +#define ON_SOCKET_FT1 0 +#define KR_SOCKET_FT2 0 +#define OR_SOCKET_AM3 1 +#define OR_SOCKET_G34 3 +#define OR_SOCKET_C32 5 +#define TN_SOCKET_FP2 0 +#define TN_SOCKET_FS1 1 +#define TN_SOCKET_FM2 2 +#define KV_SOCKET_FS2 1 +#define KV_SOCKET_FM3 2 +#define KB_SOCKET_FT2 0 +#define SOCKET_IGNORE 0xF + +#define LAPIC_BASE_ADDR_MASK 0x0000FFFFFFFFF000ull +#define APIC_EXT_BRDCST_MASK 0x000E0000ul +#define APIC_ENABLE_BIT 0x00000800ul +#define LOCAL_APIC_ADDR 0xFEE00000ul +#define INT_CMD_REG_LO 0x300 +#define INT_CMD_REG_HI 0x310 +#define REMOTE_MSG_REG 0x380 +#define REMOTE_READ_REG 0xC0 +#define APIC_ID_REG 0x20 +#define APIC20_ApicId 24 +#define CMD_REG_TO_READ_DATA 0x338 + +#define MAX_CORE_ID_SIZE 8 +#define MAX_CORE_ID_MASK ((1 << MAX_CORE_ID_SIZE) - 1) + +/*------------------------- + * Default definitions + *------------------------- + */ +#define DOWNCORE_MASK_SINGLE 0xFFFFFFFEul +#define DOWNCORE_MASK_DUAL 0xFFFFFFFCul +#define DOWNCORE_MASK_TRI 0xFFFFFFF8ul +#define DOWNCORE_MASK_FOUR 0xFFFFFFF0ul +#define DOWNCORE_MASK_FIVE 0xFFFFFFE0ul +#define DOWNCORE_MASK_SIX 0xFFFFFFC0ul +#define DOWNCORE_MASK_DUAL_COMPUTE_UNIT 0xFFFFFFFAul +#define DOWNCORE_MASK_TRI_COMPUTE_UNIT 0xFFFFFFEAul +#define DOWNCORE_MASK_FOUR_COMPUTE_UNIT 0xFFFFFFAAul + +#define DELIVERY_STATUS BIT13 +#define REMOTE_READ_STAT_MASK 0x00030000ul +#define REMOTE_DELIVERY_PENDING 0x00010000ul +#define REMOTE_DELIVERY_DONE 0x00020000ul + +/* + * -------------------------------------------------------------------------------------- + * + * D E F I N E S / T Y P E D E F S / S T R U C T U R E S + * + * -------------------------------------------------------------------------------------- + */ + +/// CpuEarly param type +typedef struct { + IN UINT8 MemInitPState; ///< Pstate value during memory initial + IN PLATFORM_CONFIGURATION PlatformConfig; ///< Runtime configurable user options +} AMD_CPU_EARLY_PARAMS; + +/// Enum - Will be used to access each structure +/// related to each CPU family +typedef enum { + REVF, ///< NPT, RevF + REVG, ///< NPT, RevG + DEERHOUND, ///< Family 10h, Deerhound + GRIFFIN ///< Family 11h, Griffin +} CPU_FAMILY; + +/// CPUID +typedef enum { + REG_EAX, ///< EAX + REG_EBX, ///< EBX + REG_ECX, ///< ECX + REG_EDX ///< EDX +} CPUID_REG; + +#endif // _CPU_REGISTERS_H_ + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuServices.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuServices.h new file mode 100644 index 0000000..bbc0e32 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuServices.h @@ -0,0 +1,360 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Services + * + * Related to the General Services API's, but for the CPU component. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_SERVICES_H_ +#define _CPU_SERVICES_H_ + +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + /// WARM RESET STATE_BITS +#define WR_STATE_COLD 00 +#define WR_STATE_RESET 01 +#define WR_STATE_EARLY 02 +#define WR_STATE_POST 03 + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *---------------------------------------------------------------------------------------- + */ + +/** + * The role of primary core for each compute unit can be relative to the cores' launch order. + * + * One core of a compute unit is always given the role as primary. In different feature algorithms + * the core performing the primary core role can be designated relative to compute order. In most cases, + * the primary core is the first core of a compute unit to execute. However, in some cases the primary core + * role is associated with the last core to execute. + * + * If the launch order is strictly ascending, then first core is the lowest number and last core is highest. + * But if the launch order is not ascending, the first and last core follow the launch order, not the numbering order. + * + * Note that for compute units with only one core (AllCoresMapping), that core is primary for both orderings. + * (This includes processors without hardware compute units.) + * + */ +typedef enum { + FirstCoreIsComputeUnitPrimary, ///< the primary core role associates with the first core. + LastCoreIsComputeUnitPrimary, ///< the primary core role associates with the last core. + MaxComputeUnitPrimarySelector, ///< limit check. +} COMPUTE_UNIT_PRIMARY_SELECTOR; + +/** + * The supported Core to Compute unit mappings. + */ +typedef enum { + AllCoresMapping, ///< All Cores are primary cores + EvenCoresMapping, ///< Compute units are even/odd core pairs. + BitMapMapping, ///< Currently not supported by any family, arbitrary core + ///< to compute unit mapping. + MaxComputeUnitMapping ///< Not a mapping, use for limit check. +} COMPUTE_UNIT_MAPPING; + +/** + * Core Pair Map entry. + * Provide for interpreting the core pairing for the processor's compute units. + * + * HT_LIST_TERMINAL as an Enabled value means the end of a list of map structs. + * Zero as an Enabled value implies Compute Units are not supported by the processor + * and the mapping is assumed to be AllCoresMapping. + * + */ +typedef struct { + UINT8 Enabled; ///< The value of the Enabled Compute Units + UINT8 DualCore; ///< The value of the Dual Core Compute Units + COMPUTE_UNIT_MAPPING Mapping; ///< When the processor module matches these values, use this mapping method. +} CORE_PAIR_MAP; + +//---------------------------------------------------------------------------- +// CPU SYSTEM INFO TYPEDEFS, STRUCTURES, ENUMS +// +//---------------------------------------------------------------------------- +/// SYSTEM INFO +typedef struct _SYSTEM_INFO { + UINT32 TotalNumberOfSockets; ///< Total Number of Sockets + UINT32 TotalNumberOfCores; ///< Total Number Of Cores + UINT32 CurrentSocketNum; ///< Current Socket Number + UINT32 CurrentCoreNum; ///< Current Core Number + UINT32 CurrentCoreApicId; ///< Current Core Apic ID + UINT32 CurrentLogicalCpuId; ///< Current Logical CPU ID +} SYSTEM_INFO; + +/// WARM_RESET_REQUEST +typedef struct _WARM_RESET_REQUEST { + UINT8 RequestBit:1; ///< Request Bit + UINT8 StateBits:2; ///< State Bits + UINT8 PostStage:2; ///< Post Stage + UINT8 Reserved:(8 - 5); ///< Reserved +} WARM_RESET_REQUEST; +/*---------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ + +VOID +GetCurrentNodeNum ( + OUT UINT32 *Node, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Get the current Platform's number of Sockets, regardless of how many are populated. + * + */ +UINT32 +GetPlatformNumberOfSockets ( VOID ); + +/** + * Get the number of Modules to check presence in each Processor. + * + */ +UINT32 +GetPlatformNumberOfModules ( VOID ); + +BOOLEAN +IsProcessorPresent ( + IN UINT32 Socket, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * For a specific Node, get its Socket and Module ids. + * + */ +BOOLEAN +GetSocketModuleOfNode ( + IN UINT32 Node, + OUT UINT32 *Socket, + OUT UINT32 *Module, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Get the current core's Processor APIC Index. + */ +UINT32 +GetProcessorApicIndex ( + IN UINT32 Node, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Provide the number of installed processors (not Nodes! and not Sockets!) + */ +UINT32 +GetNumberOfProcessors ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GetActiveCoresInCurrentSocket ( + OUT UINT32 *CoreCount, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GetActiveCoresInGivenSocket ( + IN UINT32 Socket, + OUT UINT32 *CoreCount, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINTN +GetActiveCoresInCurrentModule ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINTN +GetNumberOfCompUnitsInCurrentModule ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GetGivenModuleCoreRange ( + IN UINT32 Socket, + IN UINT32 Module, + OUT UINT32 *LowCore, + OUT UINT32 *HighCore, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GetCurrentCore ( + OUT UINT32 *Core, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GetCurrentNodeAndCore ( + OUT UINT32 *Node, + OUT UINT32 *Core, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +IsCurrentCorePrimary ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GetApMailbox ( + OUT UINT32 *ApMailboxInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +CacheApMailbox ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINTN +GetSystemDegree ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GetNodeId ( + IN UINT32 SocketId, + IN UINT32 ModuleId, + OUT UINT8 *NodeId, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +WaitMicroseconds ( + IN UINT32 Microseconds, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Get the compute unit mapping algorithm. + */ +COMPUTE_UNIT_MAPPING +GetComputeUnitMapping ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Does the current core have the role of primary core for the compute unit? + */ +BOOLEAN +IsCorePairPrimary ( + IN COMPUTE_UNIT_PRIMARY_SELECTOR Selector, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * Are the two specified cores shared in a compute unit? + */ +BOOLEAN +AreCoresPaired ( + IN UINT32 Socket, + IN UINT32 Module, + IN UINT32 CoreA, + IN UINT32 CoreB, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +SetWarmResetFlag ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN WARM_RESET_REQUEST *Request + ); + +VOID +GetWarmResetFlag ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT WARM_RESET_REQUEST *Request + ); + +BOOLEAN +IsWarmReset ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +CheckBistStatus ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +SetWarmResetAtEarly ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader +); + +#endif // _CPU_SERVICES_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuWarmReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuWarmReset.c new file mode 100644 index 0000000..a7af298 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuWarmReset.c @@ -0,0 +1,261 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Warm Reset Implementation. + * + * Implement Warm Reset Interface. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "cpuRegisters.h" +#include "cpuServices.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_CPUWARMRESET_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * This function will set the CPU register warm reset bits. + * + * Note: This function will be called by UEFI BIOS's + * The UEFI wrapper code should register this function, to be called back later point + * in time, before the wrapper code does warm reset. + * + * @param[in] StdHeader Config handle for library and services + * @param[in] Request Indicate warm reset status + * + *--------------------------------------------------------------------------------------- + **/ +VOID +SetWarmResetFlag ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN WARM_RESET_REQUEST *Request + ) +{ + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + FamilySpecificServices = NULL; + + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->SetWarmResetFlag (FamilySpecificServices, StdHeader, Request); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * This function will get the CPU register warm reset bits. + * + * Note: This function will be called by UEFI BIOS's + * The UEFI wrapper code should register this function, to be called back later point + * in time, before the wrapper code does warm reset. + * + * @param[in] StdHeader Config handle for library and services + * @param[out] Request Indicate warm reset status + * + *--------------------------------------------------------------------------------------- + **/ +VOID +GetWarmResetFlag ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT WARM_RESET_REQUEST *Request + ) +{ + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + FamilySpecificServices = NULL; + + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->GetWarmResetFlag (FamilySpecificServices, StdHeader, Request); + + switch (StdHeader->Func) { + case AMD_INIT_RESET: + Request->PostStage = (UINT8) WR_STATE_RESET; + break; + case AMD_INIT_EARLY: + Request->PostStage = (UINT8) WR_STATE_EARLY; + break; + case AMD_INIT_POST: + // Fall through to default case + default: + Request->PostStage = (UINT8) WR_STATE_POST; + break; + } +} +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S - (AGESA ONLY) + *---------------------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------------------*/ +/** + * Is this boot a warm reset? + * + * This function reads the CPU register warm reset bit that is preserved after a warm reset. + * Which in fact gets set before issuing warm reset. We just use the BSP's register always. + * + * @param[in] StdHeader Config handle for library and services + * + * @retval TRUE Warm Reset + * @retval FALSE Not Warm Reset + * + */ +BOOLEAN +IsWarmReset ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 PostStage; + WARM_RESET_REQUEST Request; + BOOLEAN WarmReset; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + FamilySpecificServices = NULL; + + switch (StdHeader->Func) { + case AMD_INIT_RESET: + PostStage = WR_STATE_RESET; + break; + case AMD_INIT_EARLY: + PostStage = WR_STATE_EARLY; + break; + case AMD_INIT_POST: + default: + PostStage = WR_STATE_POST; + break; + } + + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->GetWarmResetFlag (FamilySpecificServices, StdHeader, &Request); + + if (Request.StateBits >= PostStage) { + WarmReset = TRUE; + } else { + WarmReset = FALSE; + } + + return WarmReset; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * This function will set the CPU register warm reset bits at AmdInitEarly if it is + * currently in cold boot. To request for a warm reset, set the RequestBit to TRUE + * and the StateBits to (current poststage - 1) + * + * @param[in] Data The table data value (unused in this routine) + * @param[in] StdHeader Config handle for library and services + * + *--------------------------------------------------------------------------------------- + **/ +VOID +SetWarmResetAtEarly ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + WARM_RESET_REQUEST Request; + + if (!IsWarmReset (StdHeader)) { + GetWarmResetFlag (StdHeader, &Request); + + Request.RequestBit = TRUE; + Request.StateBits = (Request.PostStage - 1); + + SetWarmResetFlag (StdHeader, &Request); + } +} + +/*---------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c new file mode 100644 index 0000000..a59a45e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c @@ -0,0 +1,911 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Heap Manager and Heap Allocation APIs, and related functions. + * + * Contains code that initialize, maintain, and allocate the heap space. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/******************************************************************************* + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "heapManager.h" +#include "cpuCacheInit.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_HEAPMANAGER_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +UINT64 +STATIC +HeapGetCurrentBase ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +DeleteFreeSpaceNode ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT32 OffsetOfDeletedNode + ); + +VOID +STATIC +InsertFreeSpaceNode ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT32 OffsetOfInsertNode + ); + +/*---------------------------------------------------------------------------------------- + * P U B L I C F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern BUILD_OPT_CFG UserOptions; + +/*---------------------------------------------------------------------------------------*/ +/** + * This function initializes the heap for each CPU core. + * + * Check for already initialized. If not, determine offset of local heap in CAS and + * setup initial heap markers and bookkeeping status. Initialize a couple heap items + * all cores need, for convenience. Currently these are caching the AP mailbox info and + * an initial event log. + * + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval AGESA_SUCCESS This core's heap is initialized + * @retval AGESA_FATAL This core's heap cannot be initialized due to any reasons below: + * - current processor family cannot be identified. + * + */ +AGESA_STATUS +HeapManagerInit ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + // First Time Initialization + // Note: First 16 bytes of buffer is reserved for Heap Manager use + UINT16 HeapAlreadyInitSizeDword; + UINT32 HeapAlreadyRead; + UINT8 L2LineSize; + UINT8 *HeapBufferPtr; + UINT8 *HeapInitPtr; + UINT32 *HeapDataPtr; + UINT64 MsrData; + UINT64 MsrMask; + UINT8 Ignored; + CPUID_DATA CpuId; + BUFFER_NODE *FreeSpaceNode; + CACHE_INFO *CacheInfoPtr; + AGESA_STATUS IgnoredSts; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + CPU_LOGICAL_ID CpuFamilyRevision; + + // Check whether this is a known processor family. + GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); + if ((CpuFamilyRevision.Family == 0) && (CpuFamilyRevision.Revision == 0)) { + IDS_ERROR_TRAP; + return AGESA_FATAL; + } + + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader); + HeapBufferPtr = (UINT8 *)(UINT32) StdHeader->HeapBasePtr; + + // Check whether the heap manager is already initialized + LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_MASK, &MsrData, StdHeader); + if (MsrData == (CacheInfoPtr->VariableMtrrMask & AMD_HEAP_MTRR_MASK)) { + LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_BASE, &MsrData, StdHeader); + if ((MsrData & CacheInfoPtr->HeapBaseMask) == ((UINT64) (UINTN) HeapBufferPtr & CacheInfoPtr->HeapBaseMask)) { + if (((HEAP_MANAGER *) HeapBufferPtr)->Signature == HEAP_SIGNATURE_VALID) { + // This is not a bug, there are multiple premem basic entry points, + // and each will call heap init to make sure create struct will succeed. + // If that is later deemed a problem, there needs to be a reasonable test + // for the calling code to make to determine if it needs to init heap or not. + // In the mean time, add this to the event log + PutEventLog (AGESA_SUCCESS, + CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED, + 0, 0, 0, 0, StdHeader); + return AGESA_SUCCESS; + } + } + } + + // Set variable MTRR base and mask + MsrData = ((UINT64) (UINTN) HeapBufferPtr & CacheInfoPtr->HeapBaseMask); + MsrMask = CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK; + + MsrData |= 0x06; + LibAmdMsrWrite (AMD_MTRR_VARIABLE_HEAP_BASE, &MsrData, StdHeader); + LibAmdMsrWrite (AMD_MTRR_VARIABLE_HEAP_MASK, &MsrMask, StdHeader); + + // Set top of memory to a temp value + MsrData = (UINT64) (AMD_TEMP_TOM); + LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader); + + // Enable variable MTTRs + LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader); + MsrData |= AMD_VAR_MTRR_ENABLE_BIT; + LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader); + + // Initialize Heap Space + // BIOS may store to a line only after it has been allocated by a load + LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuId, StdHeader); + L2LineSize = (UINT8) (CpuId.ECX_Reg); + HeapInitPtr = HeapBufferPtr ; + for (HeapAlreadyRead = 0; HeapAlreadyRead < AMD_HEAP_SIZE_PER_CORE; + (HeapAlreadyRead = HeapAlreadyRead + L2LineSize)) { + Ignored = *HeapInitPtr; + HeapInitPtr += L2LineSize; + } + + HeapDataPtr = (UINT32 *) HeapBufferPtr; + for (HeapAlreadyInitSizeDword = 0; HeapAlreadyInitSizeDword < AMD_HEAP_SIZE_DWORD_PER_CORE; HeapAlreadyInitSizeDword++) { + *HeapDataPtr = 0; + HeapDataPtr++; + } + + // Note: We are reserving the first 16 bytes for Heap Manager use + // UsedSize indicates the size of heap spaced is used for HEAP_MANAGER, BUFFER_NODE, + // Pad for 16-byte alignment, buffer data, and IDS SENTINEL. + // FirstActiveBufferOffset is initalized as invalid heap offset, AMD_HEAP_INVALID_HEAP_OFFSET. + // FirstFreeSpaceOffset is initalized as the byte right after HEAP_MANAGER header. + // Then we set Signature of HEAP_MANAGER header as valid, HEAP_SIGNATURE_VALID. + ((HEAP_MANAGER*) HeapBufferPtr)->UsedSize = sizeof (HEAP_MANAGER); + ((HEAP_MANAGER*) HeapBufferPtr)->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET; + ((HEAP_MANAGER*) HeapBufferPtr)->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER); + ((HEAP_MANAGER*) HeapBufferPtr)->Signature = HEAP_SIGNATURE_VALID; + // Create free space link + FreeSpaceNode = (BUFFER_NODE *) (HeapBufferPtr + sizeof (HEAP_MANAGER)); + FreeSpaceNode->BufferSize = AMD_HEAP_SIZE_PER_CORE - sizeof (HEAP_MANAGER) - sizeof (BUFFER_NODE); + FreeSpaceNode->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; + + StdHeader->HeapStatus = HEAP_LOCAL_CACHE; + if (!IsBsp (StdHeader, &IgnoredSts)) { + // The BSP's hardware mailbox has not been initialized, so only APs + // can do this at this point. + CacheApMailbox (StdHeader); + } + EventLogInitialization (StdHeader); + return AGESA_SUCCESS; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Allocates space for a new buffer in the heap + * + * This function will allocate new buffer either by using internal 'AGESA' heapmanager + * or by using externa (IBV) heapmanager. This function will also determine if whether or not + * there is enough space for the new structure. If so, it will zero out the buffer, + * and return a pointer to the region. + * + * @param[in,out] AllocateHeapParams structure pointer containing the size of the + * desired new region, its handle, and the + * return pointer. + * @param[in,out] StdHeader Config handle for library and services. + * + * @retval AGESA_SUCCESS No error + * @retval AGESA_BOUNDS_CHK Handle already exists, or not enough + * free space + * @retval AGESA_UNSUPPORTED Do not support this kind of heap allocation + * @retval AGESA_ERROR Heap is invaild + * + */ +AGESA_STATUS +HeapAllocateBuffer ( + IN OUT ALLOCATE_HEAP_PARAMS *AllocateHeapParams, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 *BaseAddress; + UINT8 AlignTo16Byte; + UINT8 CalloutFcnData; + UINT32 RemainSize; + UINT32 OffsetOfSplitNode; + UINT32 OffsetOfNode; + HEAP_MANAGER *HeapManager; + BUFFER_NODE *FreeSpaceNode; + BUFFER_NODE *SplitFreeSpaceNode; + BUFFER_NODE *CurrentBufferNode; + BUFFER_NODE *NewBufferNode; + AGESA_BUFFER_PARAMS AgesaBuffer; + + ASSERT (StdHeader != NULL); + if (AllocateHeapParams->Persist == HEAP_RUNTIME_SYSTEM_MEM) { + ASSERT (StdHeader->HeapStatus == HEAP_SYSTEM_MEM); + if (StdHeader->HeapStatus != HEAP_SYSTEM_MEM) { + return AGESA_UNSUPPORTED; + } + } + + // At this stage we will decide to either use external (IBV) heap manger + // or internal (AGESA) heap manager. + + // If (HeapStatus == HEAP_SYSTEM_MEM), then use the call function to call + // external heap manager + if (StdHeader->HeapStatus == HEAP_SYSTEM_MEM) { + AgesaBuffer.StdHeader = *StdHeader; + AgesaBuffer.BufferHandle = AllocateHeapParams->BufferHandle; + AgesaBuffer.BufferLength = AllocateHeapParams->RequestedBufferSize; + + if (AllocateHeapParams->Persist == HEAP_RUNTIME_SYSTEM_MEM) { + CalloutFcnData = HEAP_CALLOUT_RUNTIME; + } else { + CalloutFcnData = HEAP_CALLOUT_BOOTTIME; + } + AGESA_TESTPOINT (TpIfBeforeAllocateHeapBuffer, StdHeader); + if (AgesaAllocateBuffer (CalloutFcnData, &AgesaBuffer) != AGESA_SUCCESS) { + AllocateHeapParams->BufferPtr = NULL; + return AGESA_ERROR; + } + AGESA_TESTPOINT (TpIfAfterAllocateHeapBuffer, StdHeader); + + AllocateHeapParams->BufferPtr = (UINT8 *) (AgesaBuffer.BufferPointer); + return AGESA_SUCCESS; + } + + // If (StdHeader->HeapStatus != HEAP_SYSTEM_MEM), then allocated buffer + // using following AGESA Heap Manager code. + + // Buffer pointer is NULL unless we return a buffer. + AlignTo16Byte = 0; + AllocateHeapParams->BufferPtr = NULL; + AllocateHeapParams->RequestedBufferSize += NUM_OF_SENTINEL * SIZE_OF_SENTINEL; + + // Get base address + BaseAddress = (UINT8 *) (UINTN) StdHeader->HeapBasePtr; + HeapManager = (HEAP_MANAGER *) BaseAddress; + + // Check Heap database is valid + if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { + // The base address in StdHeader is incorrect, get base address by itself + BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader); + HeapManager = (HEAP_MANAGER *) BaseAddress; + if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { + // Heap is not available, ASSERT here + ASSERT (FALSE); + return AGESA_ERROR; + } + StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress; + } + + // Allocate + CurrentBufferNode = (BUFFER_NODE *) (BaseAddress + sizeof (HEAP_MANAGER)); + // If there already has been a heap with the incoming BufferHandle, we return AGESA_BOUNDS_CHK. + if (HeapManager->FirstActiveBufferOffset != AMD_HEAP_INVALID_HEAP_OFFSET) { + CurrentBufferNode = (BUFFER_NODE *) (BaseAddress + HeapManager->FirstActiveBufferOffset); + while (CurrentBufferNode->OffsetOfNextNode != AMD_HEAP_INVALID_HEAP_OFFSET) { + if (CurrentBufferNode->BufferHandle == AllocateHeapParams->BufferHandle) { + PutEventLog (AGESA_BOUNDS_CHK, + CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED, + AllocateHeapParams->BufferHandle, 0, 0, 0, StdHeader); + return AGESA_BOUNDS_CHK; + } else { + CurrentBufferNode = (BUFFER_NODE *) (BaseAddress + CurrentBufferNode->OffsetOfNextNode); + } + } + if (CurrentBufferNode->BufferHandle == AllocateHeapParams->BufferHandle) { + PutEventLog (AGESA_BOUNDS_CHK, + CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED, + AllocateHeapParams->BufferHandle, 0, 0, 0, StdHeader); + return AGESA_BOUNDS_CHK; + } + } + + // Find the buffer size that first matches the requested buffer size (i.e. the first free buffer of greater size). + OffsetOfNode = HeapManager->FirstFreeSpaceOffset; + FreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfNode); + while (OffsetOfNode != AMD_HEAP_INVALID_HEAP_OFFSET) { + AlignTo16Byte = (UINT8) ((0x10 - (((UINTN) (VOID *) FreeSpaceNode + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF); + AllocateHeapParams->RequestedBufferSize = (UINT32) (AllocateHeapParams->RequestedBufferSize + AlignTo16Byte); + if (FreeSpaceNode->BufferSize >= AllocateHeapParams->RequestedBufferSize) { + break; + } + AllocateHeapParams->RequestedBufferSize = (UINT32) (AllocateHeapParams->RequestedBufferSize - AlignTo16Byte); + OffsetOfNode = FreeSpaceNode->OffsetOfNextNode; + FreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfNode); + } + if (OffsetOfNode == AMD_HEAP_INVALID_HEAP_OFFSET) { + // We don't find any free space buffer that matches the requested buffer size. + PutEventLog (AGESA_BOUNDS_CHK, + CPU_ERROR_HEAP_IS_FULL, + AllocateHeapParams->BufferHandle, 0, 0, 0, StdHeader); + return AGESA_BOUNDS_CHK; + } else { + // We find one matched free space buffer. + DeleteFreeSpaceNode (StdHeader, OffsetOfNode); + NewBufferNode = FreeSpaceNode; + // Add new buffer node to the buffer chain + if (HeapManager->FirstActiveBufferOffset == AMD_HEAP_INVALID_HEAP_OFFSET) { + HeapManager->FirstActiveBufferOffset = sizeof (HEAP_MANAGER); + } else { + CurrentBufferNode->OffsetOfNextNode = OffsetOfNode; + } + // New buffer size + RemainSize = FreeSpaceNode->BufferSize - AllocateHeapParams->RequestedBufferSize; + if (RemainSize > sizeof (BUFFER_NODE)) { + NewBufferNode->BufferSize = AllocateHeapParams->RequestedBufferSize; + OffsetOfSplitNode = OffsetOfNode + sizeof (BUFFER_NODE) + NewBufferNode->BufferSize; + SplitFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfSplitNode); + SplitFreeSpaceNode->BufferSize = RemainSize - sizeof (BUFFER_NODE); + InsertFreeSpaceNode (StdHeader, OffsetOfSplitNode); + } else { + // Remain size is less than BUFFER_NODE, we use whole size instead of requested size. + NewBufferNode->BufferSize = FreeSpaceNode->BufferSize; + } + } + + // Initialize BUFFER_NODE structure of NewBufferNode + NewBufferNode->BufferHandle = AllocateHeapParams->BufferHandle; + if ((AllocateHeapParams->Persist == HEAP_TEMP_MEM) || (AllocateHeapParams->Persist == HEAP_SYSTEM_MEM)) { + NewBufferNode->Persist = AllocateHeapParams->Persist; + } else { + NewBufferNode->Persist = HEAP_LOCAL_CACHE; + } + NewBufferNode->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; + NewBufferNode->PadSize = AlignTo16Byte; + + // Clear to 0x00 + LibAmdMemFill ((VOID *) ((UINT8 *) NewBufferNode + sizeof (BUFFER_NODE)), 0x00, NewBufferNode->BufferSize, StdHeader); + + // Debug feature + SET_SENTINEL_BEFORE (NewBufferNode, AlignTo16Byte); + SET_SENTINEL_AFTER (NewBufferNode); + + // Update global variables + HeapManager->UsedSize += NewBufferNode->BufferSize + sizeof (BUFFER_NODE); + + // Now fill in the incoming structure + AllocateHeapParams->BufferPtr = (UINT8 *) ((UINT8 *) NewBufferNode + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL + AlignTo16Byte); + AllocateHeapParams->RequestedBufferSize -= (NUM_OF_SENTINEL * SIZE_OF_SENTINEL + AlignTo16Byte); + + return AGESA_SUCCESS; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Deallocates a previously allocated buffer in the heap + * + * This function will deallocate buffer either by using internal 'AGESA' heapmanager + * or by using externa (IBV) heapmanager. + * + * @param[in] BufferHandle Handle of the buffer to free. + * @param[in] StdHeader Config handle for library and services. + * + * @retval AGESA_SUCCESS No error + * @retval AGESA_BOUNDS_CHK Handle does not exist on the heap + * + */ +AGESA_STATUS +HeapDeallocateBuffer ( + IN UINT32 BufferHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 *BaseAddress; + UINT32 NodeSize; + UINT32 OffsetOfFreeSpaceNode; + UINT32 OffsetOfPreviousNode; + UINT32 OffsetOfCurrentNode; + BOOLEAN HeapLocateFlag; + HEAP_MANAGER *HeapManager; + BUFFER_NODE *CurrentNode; + BUFFER_NODE *PreviousNode; + BUFFER_NODE *FreeSpaceNode; + AGESA_BUFFER_PARAMS AgesaBuffer; + + ASSERT (StdHeader != NULL); + + HeapLocateFlag = TRUE; + BaseAddress = (UINT8 *) (UINTN) StdHeader->HeapBasePtr; + HeapManager = (HEAP_MANAGER *) BaseAddress; + + // Check Heap database is valid + if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { + // The base address in StdHeader is incorrect, get base address by itself + BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader); + HeapManager = (HEAP_MANAGER *) BaseAddress; + if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { + // Heap is not available, ASSERT here + ASSERT (FALSE); + return AGESA_ERROR; + } + StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress; + } + + OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET; + OffsetOfCurrentNode = HeapManager->FirstActiveBufferOffset; + CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); + + // Locate heap + if ((BaseAddress != NULL) && (HeapManager->Signature == HEAP_SIGNATURE_VALID)) { + if (OffsetOfCurrentNode == AMD_HEAP_INVALID_HEAP_OFFSET) { + HeapLocateFlag = FALSE; + } else { + while (CurrentNode->BufferHandle != BufferHandle) { + if (CurrentNode->OffsetOfNextNode == AMD_HEAP_INVALID_HEAP_OFFSET) { + HeapLocateFlag = FALSE; + break; + } else { + OffsetOfPreviousNode = OffsetOfCurrentNode; + OffsetOfCurrentNode = CurrentNode->OffsetOfNextNode; + CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); + } + } + } + } else { + HeapLocateFlag = FALSE; + } + + if (HeapLocateFlag == TRUE) { + // CurrentNode points to the buffer which wanted to be deallocated. + // Remove deallocated heap from active buffer chain. + if (OffsetOfPreviousNode == AMD_HEAP_INVALID_HEAP_OFFSET) { + HeapManager->FirstActiveBufferOffset = CurrentNode->OffsetOfNextNode; + } else { + PreviousNode = (BUFFER_NODE *) (BaseAddress + OffsetOfPreviousNode); + PreviousNode->OffsetOfNextNode = CurrentNode->OffsetOfNextNode; + } + // Now, CurrentNode become a free space node. + HeapManager->UsedSize -= CurrentNode->BufferSize + sizeof (BUFFER_NODE); + // Loop free space chain to see if any free space node is just before/after CurrentNode, then merge them. + OffsetOfFreeSpaceNode = HeapManager->FirstFreeSpaceOffset; + FreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfFreeSpaceNode); + while (OffsetOfFreeSpaceNode != AMD_HEAP_INVALID_HEAP_OFFSET) { + if ((OffsetOfFreeSpaceNode + sizeof (BUFFER_NODE) + FreeSpaceNode->BufferSize) == OffsetOfCurrentNode) { + DeleteFreeSpaceNode (StdHeader, OffsetOfFreeSpaceNode); + NodeSize = FreeSpaceNode->BufferSize + CurrentNode->BufferSize + sizeof (BUFFER_NODE); + OffsetOfCurrentNode = OffsetOfFreeSpaceNode; + CurrentNode = FreeSpaceNode; + CurrentNode->BufferSize = NodeSize; + } else if (OffsetOfFreeSpaceNode == (OffsetOfCurrentNode + sizeof (BUFFER_NODE) + CurrentNode->BufferSize)) { + DeleteFreeSpaceNode (StdHeader, OffsetOfFreeSpaceNode); + NodeSize = FreeSpaceNode->BufferSize + CurrentNode->BufferSize + sizeof (BUFFER_NODE); + CurrentNode->BufferSize = NodeSize; + } + OffsetOfFreeSpaceNode = FreeSpaceNode->OffsetOfNextNode; + FreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfFreeSpaceNode); + } + InsertFreeSpaceNode (StdHeader, OffsetOfCurrentNode); + return AGESA_SUCCESS; + } else { + // If HeapStatus == HEAP_SYSTEM_MEM, try callout function + if (StdHeader->HeapStatus == HEAP_SYSTEM_MEM) { + AgesaBuffer.StdHeader = *StdHeader; + AgesaBuffer.BufferHandle = BufferHandle; + + AGESA_TESTPOINT (TpIfBeforeDeallocateHeapBuffer, StdHeader); + if (AgesaDeallocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) { + return AGESA_ERROR; + } + AGESA_TESTPOINT (TpIfAfterDeallocateHeapBuffer, StdHeader); + + return AGESA_SUCCESS; + } + // If we are still unable to locate the buffer handle, return AGESA_BOUNDS_CHK + if ((BaseAddress != NULL) && (HeapManager->Signature == HEAP_SIGNATURE_VALID)) { + PutEventLog (AGESA_BOUNDS_CHK, + CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT, + BufferHandle, 0, 0, 0, StdHeader); + } else { + ASSERT (FALSE); + } + return AGESA_BOUNDS_CHK; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Locates a previously allocated buffer on the heap. + * + * This function searches the heap for a buffer with the desired handle, and + * returns a pointer to the buffer. + * + * @param[in,out] LocateHeap Structure containing the buffer's handle, + * and the return pointer. + * @param[in] StdHeader Config handle for library and services. + * + * @retval AGESA_SUCCESS No error + * @retval AGESA_BOUNDS_CHK Handle does not exist on the heap + * + */ +AGESA_STATUS +HeapLocateBuffer ( + IN OUT LOCATE_HEAP_PTR *LocateHeap, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 *BaseAddress; + UINT8 AlignTo16Byte; + UINT32 OffsetOfCurrentNode; + BOOLEAN HeapLocateFlag; + HEAP_MANAGER *HeapManager; + BUFFER_NODE *CurrentNode; + AGESA_BUFFER_PARAMS AgesaBuffer; + + ASSERT (StdHeader != NULL); + + HeapLocateFlag = TRUE; + BaseAddress = (UINT8 *) (UINTN) StdHeader->HeapBasePtr; + HeapManager = (HEAP_MANAGER *) BaseAddress; + + // Check Heap database is valid + if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { + // The base address in StdHeader is incorrect, get base address by itself + BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader); + HeapManager = (HEAP_MANAGER *) BaseAddress; + if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) { + // Heap is not available, ASSERT here + ASSERT (FALSE); + return AGESA_ERROR; + } + StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress; + } + OffsetOfCurrentNode = HeapManager->FirstActiveBufferOffset; + CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); + + // Find buffer using internal heap manager + // Locate the heap using handle = LocateHeap-> BufferHandle + // If HeapStatus != HEAP_SYSTEM_ MEM + if ((BaseAddress != NULL) && (HeapManager->Signature == HEAP_SIGNATURE_VALID)) { + if (OffsetOfCurrentNode == AMD_HEAP_INVALID_HEAP_OFFSET) { + HeapLocateFlag = FALSE; + } else { + while (CurrentNode->BufferHandle != LocateHeap->BufferHandle) { + if (CurrentNode->OffsetOfNextNode == AMD_HEAP_INVALID_HEAP_OFFSET) { + HeapLocateFlag = FALSE; + break; + } else { + OffsetOfCurrentNode = CurrentNode->OffsetOfNextNode; + CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); + } + } + } + } else { + HeapLocateFlag = FALSE; + } + + if (HeapLocateFlag) { + AlignTo16Byte = CurrentNode->PadSize; + LocateHeap->BufferPtr = (UINT8 *) ((UINT8 *) CurrentNode + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL + AlignTo16Byte); + LocateHeap->BufferSize = CurrentNode->BufferSize - NUM_OF_SENTINEL * SIZE_OF_SENTINEL - AlignTo16Byte; + return AGESA_SUCCESS; + } else { + // If HeapStatus == HEAP_SYSTEM_MEM, try callout function + if (StdHeader->HeapStatus == HEAP_SYSTEM_MEM) { + AgesaBuffer.StdHeader = *StdHeader; + AgesaBuffer.BufferHandle = LocateHeap->BufferHandle; + + AGESA_TESTPOINT (TpIfBeforeLocateHeapBuffer, StdHeader); + if (AgesaLocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) { + LocateHeap->BufferPtr = NULL; + return AGESA_ERROR; + } + LocateHeap->BufferSize = AgesaBuffer.BufferLength; + AGESA_TESTPOINT (TpIfAfterLocateHeapBuffer, StdHeader); + + LocateHeap->BufferPtr = (UINT8 *) (AgesaBuffer.BufferPointer); + return AGESA_SUCCESS; + } + + // If we are still unable to deallocate the buffer handle, return AGESA_BOUNDS_CHK + LocateHeap->BufferPtr = NULL; + LocateHeap->BufferSize = 0; + if ((BaseAddress != NULL) && (HeapManager->Signature == HEAP_SIGNATURE_VALID)) { + PutEventLog (AGESA_BOUNDS_CHK, + CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT, + LocateHeap->BufferHandle, 0, 0, 0, StdHeader); + } else { + ASSERT (FALSE); + } + return AGESA_BOUNDS_CHK; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Get the heap base address + * + * This function will try to locate heap from cache, temp memory, main memory. + * The heap signature will be checked for validity on each possible location. + * Firstly, try if heap base is in cache by calling the function HeapGetCurrentBase. + * Secondly, try if heap base is temp memory by UserOptoions.CfgHeapDramAddress. + * Thirdly, try if heap base is in main memory by doing a buffer locate with buffer handle + * AMD_HEAP_IN_MAIN_MEMORY_HANDLE. + * If no valid heap signature is found in each possible location above, a NULL pointer is returned. + * + * @param[in] StdHeader Config handle for library and services. + * + * @return Heap base address of the executing core's heap. + * + */ +UINT64 +HeapGetBaseAddress ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 BaseAddress; + HEAP_MANAGER *HeapManager; + AGESA_BUFFER_PARAMS AgesaBuffer; + + // Firstly, we try to see if heap is in cache + BaseAddress = HeapGetCurrentBase (StdHeader); + HeapManager = (HEAP_MANAGER *) (UINTN) BaseAddress; + + if ((HeapManager->Signature != HEAP_SIGNATURE_VALID) && + (StdHeader->HeapStatus != HEAP_DO_NOT_EXIST_YET) && + (StdHeader->HeapStatus != HEAP_LOCAL_CACHE)) { + // Secondly, we try to see if heap is in temp memory + BaseAddress = UserOptions.CfgHeapDramAddress; + HeapManager = (HEAP_MANAGER *) (UINTN) BaseAddress; + if (HeapManager->Signature != HEAP_SIGNATURE_VALID) { + // Thirdly, we try to see if heap in main memory + // by locating with external buffer manager (IBV) + AgesaBuffer.StdHeader = *StdHeader; + AgesaBuffer.BufferHandle = AMD_HEAP_IN_MAIN_MEMORY_HANDLE; + if (AgesaLocateBuffer (0, &AgesaBuffer) == AGESA_SUCCESS) { + BaseAddress = (UINT64) (UINTN) AgesaBuffer.BufferPointer; + HeapManager = (HEAP_MANAGER *) (UINTN) BaseAddress; + if (HeapManager->Signature != HEAP_SIGNATURE_VALID) { + // No valid heap signature ever found, return a NULL pointer + BaseAddress = (UINT64) (UINTN) NULL; + } + } else { + // No heap buffer is allocated by external manager (IBV), return a NULL pointer + BaseAddress = (UINT64) (UINTN) NULL; + } + } + } + + return BaseAddress; +} + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * DeleteFreeSpaceNode + * + * Description: + * Delete a free space node from free space chain + * + * Parameters: + * @param[in] StdHeader Config handle for library and services. + * @param[in] OffsetOfDeletedNode Offset of deleted node. + * + * Processing: + * + */ +VOID +STATIC +DeleteFreeSpaceNode ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT32 OffsetOfDeletedNode + ) +{ + UINT8 *BaseAddress; + UINT32 OffsetOfPreviousNode; + UINT32 OffsetOfCurrentNode; + HEAP_MANAGER *HeapManager; + BUFFER_NODE *CurrentFreeSpaceNode; + BUFFER_NODE *PreviousFreeSpaceNode; + + + BaseAddress = (UINT8 *) (UINTN) StdHeader->HeapBasePtr; + HeapManager = (HEAP_MANAGER *) BaseAddress; + + OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET; + OffsetOfCurrentNode = HeapManager->FirstFreeSpaceOffset; + // + // After AmdInitEnv, there is no free space provided for HeapAllocateBuffer. + // Hence if the FirstFreeSpaceOffset is AMD_HEAP_INVALID_HEAP_OFFSET, then + // no need to do more on delete node. + // + if (OffsetOfCurrentNode != AMD_HEAP_INVALID_HEAP_OFFSET) { + CurrentFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); + while ((OffsetOfCurrentNode != AMD_HEAP_INVALID_HEAP_OFFSET) && (OffsetOfCurrentNode != OffsetOfDeletedNode)) { + OffsetOfPreviousNode = OffsetOfCurrentNode; + OffsetOfCurrentNode = CurrentFreeSpaceNode->OffsetOfNextNode; + CurrentFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); + } + if (OffsetOfCurrentNode != AMD_HEAP_INVALID_HEAP_OFFSET) { + if (OffsetOfPreviousNode == AMD_HEAP_INVALID_HEAP_OFFSET) { + HeapManager->FirstFreeSpaceOffset = CurrentFreeSpaceNode->OffsetOfNextNode; + } else { + PreviousFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfPreviousNode); + PreviousFreeSpaceNode->OffsetOfNextNode = CurrentFreeSpaceNode->OffsetOfNextNode; + } + } + } + return; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * InsertFreeSpaceNode + * + * Description: + * Insert a free space node to free space chain, size order + * + * Parameters: + * @param[in] StdHeader Config handle for library and services. + * @param[in] OffsetOfInsertNode Offset of inserted node. + * + * Processing: + * + */ +VOID +STATIC +InsertFreeSpaceNode ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT32 OffsetOfInsertNode + ) +{ + UINT8 *BaseAddress; + UINT32 OffsetOfPreviousNode; + UINT32 OffsetOfCurrentNode; + HEAP_MANAGER *HeapManager; + BUFFER_NODE *CurrentFreeSpaceNode; + BUFFER_NODE *PreviousFreeSpaceNode; + BUFFER_NODE *InsertedFreeSpaceNode; + + BaseAddress = (UINT8 *) (UINTN) StdHeader->HeapBasePtr; + HeapManager = (HEAP_MANAGER *) BaseAddress; + + OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET; + OffsetOfCurrentNode = HeapManager->FirstFreeSpaceOffset; + CurrentFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); + InsertedFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfInsertNode); + while ((OffsetOfCurrentNode != AMD_HEAP_INVALID_HEAP_OFFSET) && + (CurrentFreeSpaceNode->BufferSize < InsertedFreeSpaceNode->BufferSize)) { + OffsetOfPreviousNode = OffsetOfCurrentNode; + OffsetOfCurrentNode = CurrentFreeSpaceNode->OffsetOfNextNode; + CurrentFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); + } + InsertedFreeSpaceNode->OffsetOfNextNode = OffsetOfCurrentNode; + if (OffsetOfPreviousNode == AMD_HEAP_INVALID_HEAP_OFFSET) { + HeapManager->FirstFreeSpaceOffset = OffsetOfInsertNode; + } else { + PreviousFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfPreviousNode); + PreviousFreeSpaceNode->OffsetOfNextNode = OffsetOfInsertNode; + } + return; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Determines the base address of the executing core's heap. + * + * This function uses the executing core's socket/core numbers to determine + * where it's heap should be located. + * + * @param[in] StdHeader Config handle for library and services. + * + * @return A pointer to the executing core's heap. + * + */ +UINT64 +STATIC +HeapGetCurrentBase ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 SystemCoreNumber; + UINT64 ReturnPtr; + AGESA_STATUS IgnoredStatus; + CPU_SPECIFIC_SERVICES *FamilyServices; + + if (IsBsp (StdHeader, &IgnoredStatus)) { + ReturnPtr = AMD_HEAP_START_ADDRESS; + } else { + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader); + ASSERT (FamilyServices != NULL); + + SystemCoreNumber = FamilyServices->GetApCoreNumber (FamilyServices, StdHeader); + ASSERT (SystemCoreNumber != 0); + ASSERT (SystemCoreNumber < 64); + ReturnPtr = ((SystemCoreNumber * AMD_HEAP_SIZE_PER_CORE) + AMD_HEAP_START_ADDRESS); + } + ASSERT (ReturnPtr <= ((AMD_HEAP_REGION_END_ADDRESS + 1) - AMD_HEAP_SIZE_PER_CORE)); + return ReturnPtr; +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h new file mode 100644 index 0000000..9bbb652 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h @@ -0,0 +1,274 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Heap Manager and Heap Allocation APIs, and related functions. + * + * Contains code that initialize, maintain, and allocate the heap space. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 64574 $ @e $Date: 2012-01-25 01:01:51 -0600 (Wed, 25 Jan 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _HEAP_MANAGER_H_ +#define _HEAP_MANAGER_H_ + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ +#define AMD_MTRR_VARIABLE_BASE0 0x200 +#define AMD_MTRR_VARIABLE_HEAP_BASE 0x20A +#define AMD_MTRR_VARIABLE_HEAP_MASK (AMD_MTRR_VARIABLE_HEAP_BASE + 1) + +#define AMD_HEAP_START_ADDRESS 0x400000ul +#define AMD_HEAP_REGION_END_ADDRESS 0xBFFFFFul +#define AMD_HEAP_SIZE_PER_CORE 0x010000ul +#define AMD_HEAP_INVALID_HEAP_OFFSET 0xFFFFFFFFul +#define AMD_HEAP_MTRR_MASK ((0xFFFFFFFFFFFFF800ull & (((UINT64)AMD_HEAP_SIZE_PER_CORE ^ (-1)) + 1)) | 0x800) +#define AMD_HEAP_SIZE_DWORD_PER_CORE (AMD_HEAP_SIZE_PER_CORE / 4) + +#define AMD_TEMP_TOM 0x20000000ul // Set TOM to 512 MB (temporary value) +#define AMD_VAR_MTRR_ENABLE_BIT 0x100000ul // bit 20 + +#define AMD_HEAP_RAM_ADDRESS 0xB0000ul + +#define HEAP_SIGNATURE_VALID 0x50414548ul // Signature: 'HEAP' +#define HEAP_SIGNATURE_INVALID 0x00000000ul // Signature cleared + +///Heap Manager Life cycle +#define HEAP_DO_NOT_EXIST_YET 1 +#define HEAP_LOCAL_CACHE 2 +#define HEAP_TEMP_MEM 3 +#define HEAP_SYSTEM_MEM 4 +#define HEAP_DO_NOT_EXIST_ANYMORE 5 +#define HEAP_S3_RESUME 6 +#define HEAP_RUNTIME_SYSTEM_MEM 7 + +///Heap callout +#define HEAP_CALLOUT_BOOTTIME 0 +#define HEAP_CALLOUT_RUNTIME 1 + +#define AMD_MTRR_FIX64k_00000 0x250 +#define AMD_MTRR_FIX16k_80000 0x258 +#define AMD_MTRR_FIX16k_A0000 0x259 +#define AMD_MTRR_FIX4k_C0000 0x268 +#define AMD_MTRR_FIX4k_C8000 0x269 +#define AMD_MTRR_FIX4k_D0000 0x26A +#define AMD_MTRR_FIX4k_D8000 0x26B +#define AMD_MTRR_FIX4k_E0000 0x26C +#define AMD_MTRR_FIX4k_E8000 0x26D +#define AMD_MTRR_FIX4k_F0000 0x26E +#define AMD_MTRR_FIX4k_F8000 0x26F + +#define AMD_MTRR_FIX64K_WB_DRAM 0x1E +#define AMD_MTRR_FIX64K_WT_DRAM 0x1C +#define AMD_MTRR_FIX64K_UC_DRAM 0x18 +#define AMD_MTRR_FIX16K_WB_DRAM 0x1E1E1E1E1E1E1E1Eull +#define AMD_MTRR_FIX16K_WT_DRAM 0x1C1C1C1C1C1C1C1Cull +#define AMD_MTRR_FIX16K_UC_DRAM 0x1818181818181818ull +#define AMD_MTRR_FIX4K_WB_DRAM 0x1E1E1E1E1E1E1E1Eull +#define AMD_MTRR_FIX4K_WT_DRAM 0x1C1C1C1C1C1C1C1Cull +#define AMD_MTRR_FIX4K_UC_DRAM 0x1818181818181818ull + +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ +/// Allocate Heap Parameters +typedef struct _ALLOCATE_HEAP_PARAMS { + UINT32 RequestedBufferSize; ///< Size of buffer. + UINT32 BufferHandle; ///< An unique ID of buffer. + UINT8 Persist; ///< A flag. If marked, to be stored and passed to AmdInitLate. + UINT8 *BufferPtr; ///< Pointer to buffer. +} ALLOCATE_HEAP_PARAMS; + +/// Locate Heap Parameters +typedef struct _LOCATE_HEAP_PTR { + UINT32 BufferHandle; ///< An unique ID of buffer. + UINT32 BufferSize; ///< Data buffer size. + UINT8 *BufferPtr; ///< Pointer to buffer. +} LOCATE_HEAP_PTR; + +/// Heap Node Header +typedef struct _BUFFER_NODE { + UINT32 BufferHandle; ///< An unique ID of buffer. + UINT32 BufferSize; ///< Size of buffer. + UINT8 Persist; ///< A flag. If marked, to be stored and passed to AmdInitLate. + UINT8 PadSize; ///< Size of pad. + UINT32 OffsetOfNextNode; ///< Offset of next node (relative to the base). +} BUFFER_NODE; + +/// Heap Manager +typedef struct _HEAP_MANAGER { + UINT32 Signature; ///< a signature to indicate if the heap is valid. + UINT32 UsedSize; ///< Used size of heap. + UINT32 FirstActiveBufferOffset; ///< Offset of the first active buffer. + UINT32 FirstFreeSpaceOffset; ///< Offset of the first free space. +} HEAP_MANAGER; + +/// AGESA Buffer Handles (These are reserved) +typedef enum { + AMD_INIT_RESET_HANDLE = 0x000A000, ///< Assign 0x000A000 buffer handle to AmdInitReset routine. + AMD_INIT_EARLY_HANDLE, ///< Assign 0x000A001 buffer handle to AmdInitEarly routine. + AMD_INIT_POST_HANDLE, ///< Assign 0x000A002 buffer handle to AmdInitPost routine. + AMD_INIT_ENV_HANDLE, ///< Assign 0x000A003 buffer handle to AmdInitEnv routine. + AMD_INIT_MID_HANDLE, ///< Assign 0x000A004 buffer handle to AmdInitMid routine. + AMD_INIT_LATE_HANDLE, ///< Assign 0x000A005 buffer handle to AmdInitLate routine. + AMD_INIT_RESUME_HANDLE, ///< Assign 0x000A006 buffer handle to AmdInitResume routine. + AMD_LATE_RUN_AP_TASK_HANDLE, ///< Assign 0x000A007 buffer handle to AmdLateRunApTask routine. + AMD_S3_SAVE_HANDLE, ///< Assign 0x000A008 buffer handle to AmdS3Save routine. + AMD_S3_LATE_RESTORE_HANDLE, ///< Assign 0x000A009 buffer handle to AmdS3LateRestore routine. + AMD_S3_SCRIPT_SAVE_TABLE_HANDLE, ///< Assign 0x000A00A buffer handle to be used for S3 save table + AMD_S3_SCRIPT_TEMP_BUFFER_HANDLE, ///< Assign 0x000A00B buffer handle to be used for S3 save table + AMD_CPU_AP_TASKING_HANDLE, ///< Assign 0x000A00C buffer handle to AP tasking input parameters. + AMD_REC_MEM_SOCKET_HANDLE, ///< Assign 0x000A00D buffer handle to save socket with memory in memory recovery mode. + AMD_MEM_AUTO_HANDLE, ///< Assign 0x000A00E buffer handle to AmdMemAuto routine. + AMD_MEM_SPD_HANDLE, ///< Assign 0x000A00F buffer handle to AmdMemSpd routine. + AMD_MEM_DATA_HANDLE, ///< Assign 0x000A010 buffer handle to MemData + AMD_MEM_TRAIN_BUFFER_HANDLE, ///< Assign 0x000A011 buffer handle to allocate buffer for training + AMD_MEM_S3_DATA_HANDLE, ///< Assign 0x000A012 buffer handle to special case register for S3 + AMD_MEM_S3_NB_HANDLE, ///< Assign 0x000A013 buffer handle to NB block for S3 + AMD_MEM_S3_MR0_DATA_HANDLE, ///< Assign 0x000A014 buffer handle to MR0 data block for S3 + AMD_UMA_INFO_HANDLE, ///< Assign 0x000A015 buffer handle to be used for Uma information + AMD_DMI_MEM_DEV_INFO_HANDLE, ///< Assign 0x000A016 buffer handle to DMI Type16 17 19 20 information + HT_STATE_DATA_HANDLE, ///< Assign 0x000A017 buffer handle to HT State Data + PRESERVE_MAIL_BOX_HANDLE, ///< Assign 0x000A018 buffer handle for Preserve Mailbox Feature. + EVENT_LOG_BUFFER_HANDLE, ///< Assign 0x000A019 buffer handle to Event Log + IDS_CONTROL_HANDLE, ///< Assign 0x000A01A buffer handle to AmdIds routine. + IDS_HT_DATA_HANDLE, ///< Assign 0x000A01B buffer handle to Ht IDS control + IDS_HDT_OUT_BUFFER_HANDLE, ///< Assign 0x000A01C buffer handle to be used for HDTOUT support. + IDS_CHECK_POINT_PERF_HANDLE, ///< Assign 0x000A01D buffer handle to Performance analysis + AMD_PCIE_COMPLEX_DATA_HANDLE, ///< Assign 0x000A01E buffer handle to be used for PCIe support + AMD_MEM_SYS_DATA_HANDLE, ///< Assign 0x000A01F buffer handle to be used for memory data structure + AMD_GNB_SMU_CONFIG_HANDLE, ///< Assign 0x000A020 buffer handle to be used for GNB SMU configuration + AMD_PP_FUSE_TABLE_HANDLE, ///< Assign 0x000A021 buffer handle to be used for TT fuse table + AMD_GFX_PLATFORM_CONFIG_HANDLE, ///< Assign 0x000A022 buffer handle to be used for Gfx platform configuration + AMD_GNB_TEMP_DATA_HANDLE, ///< Assign 0x000A024 buffer handle for GNB general purpose data block + AMD_MEM_2D_RDQS_HANDLE, ///< Assign 0x000A025 buffer handle for 2D training + AMD_GNB_IOMMU_SCRATCH_MEM_HANDLE, ///< Assign 0x000A026 buffer handle to be used for GNB IOMMU scratch memory + AMD_MEM_S3_SAVE_HANDLE, ///< Assign 0x000A027 buffer handle for memory data saved right after memory init + AMD_MEM_2D_RDQS_RIM_HANDLE, ///< Assign 0x000A028 buffer handle for 2D training Eye RIM Search + AMD_CPU_NB_PSTATE_FIXUP_HANDLE, ///< Assign 0x000A029 buffer handle for an NB P-state workaround + AMD_MEM_CRAT_INFO_BUFFER_HANDLE, ///< Assign 0x000A02B buffer handle for CRAT Memory affinity component structure + AMD_MEM_MISC_HANDLES_START = 0x1000000, ///< Reserve 0x1000000 to 0x1FFFFFF buffer handle + AMD_MEM_MISC_HANDLES_END = 0x1FFFFFF, ///< miscellaneous memory init tasks' buffers. + AMD_HEAP_IN_MAIN_MEMORY_HANDLE = 0x8000000, ///< Assign 0x8000000 to AMD_HEAP_IN_MAIN_MEMORY_HANDLE. + SOCKET_DIE_MAP_HANDLE = 0x534F4B54, ///< 'sokt' + NODE_ID_MAP_HANDLE = 0x4E4F4445, ///< 'node' + HOP_COUNT_TABLE_HANDLE = 0x484F5053, ///< 'hops' + LOCAL_AP_MAIL_BOX_CACHE_HANDLE = 0x414D4258, ///< 'ambx' + AMD_FCH_RESET_DATA_BLOCK_HANDLE = 0x46434852, ///< 'FCHR' Buffer handle for FCH private data block at InitReset + AMD_FCH_DATA_BLOCK_HANDLE = 0x46434845, ///< 'FCHE' Buffer handle for FCH private data block at InitEnv + IDS_TRAP_TABLE_HANDLE = 0x49524547, ///< 'IREG' Handle for IDS register table + IDS_SAVE_IDTR_HANDLE = 0x49445452, ///< 'IDTR' + IDS_BSC_IDT_HANDLE = 0x42534349, ///< 'BSCI' BSC Idt table + IDS_NV_TO_CMOS_HANDLE = 0x534D4349, ///< 'ICMS' Handle for IDS CMOS save + IDS_GRA_HANDLE = 0x41524749, ///< 'IGRA' Handle for IDS GRA save + IDS_EXTEND_HANDLE = 0x54584549 ///< 'IEXT' Handle for IDS extend module +} AGESA_BUFFER_HANDLE; + + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +HeapManagerInit ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +HeapAllocateBuffer ( + IN OUT ALLOCATE_HEAP_PARAMS *AllocateHeapParams, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +HeapDeallocateBuffer ( + IN UINT32 BufferHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +HeapLocateBuffer ( + IN OUT LOCATE_HEAP_PTR *LocateHeap, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT64 +HeapGetBaseAddress ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +EventLogInitialization ( + IN AMD_CONFIG_PARAMS *StdHeader + ); +#endif // _HEAP_MANAGER_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/mmioMapManager.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/mmioMapManager.c new file mode 100644 index 0000000..768f2cd --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/mmioMapManager.c @@ -0,0 +1,143 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD MMIO Map Manager APIs, and related functions. + * + * Contains code that manage MMIO base/limit registers + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63522 $ @e $Date: 2011-12-25 20:25:03 -0600 (Sun, 25 Dec 2011) $ + * + */ +/******************************************************************************* + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuServices.h" +#include "cpuFamilyTranslation.h" +#include "mmioMapManager.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_MMIOMAPMANAGER_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern CPU_FAMILY_SUPPORT_TABLE MmioMapFamilyServiceTable; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P U B L I C F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * MMIO map manager + * + * @param[in] AmdAddMmioParams Pointer to a data structure containing the parameter information. + * + * @retval AGESA_STATUS AGESA_ERROR - The requested range could not be added because there are not + * enough mapping resources. + * AGESA_UNSUPPORTED - not support on currect processor + * AGESA_BOUNDS_CHK - One or more input parameters are invalid. For example, the + * TargetAddress does not correspond to any device in the system. + * AGESA_SUCCESS - Adding MMIO map succeeds + * + */ +AGESA_STATUS +AmdAddMmioMapping ( + IN AMD_ADD_MMIO_PARAMS AmdAddMmioParams + ) +{ + MMIO_MAP_FAMILY_SERVICES *FamilyServices; + + GetFeatureServicesOfCurrentCore (&MmioMapFamilyServiceTable, (CONST VOID **)&FamilyServices, &(AmdAddMmioParams.StdHeader)); + if (FamilyServices != NULL) { + return (FamilyServices->addingMmioMap (FamilyServices, AmdAddMmioParams)); + } else { + return AGESA_UNSUPPORTED; + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/mmioMapManager.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/mmioMapManager.h new file mode 100644 index 0000000..d4cb6e5 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/mmioMapManager.h @@ -0,0 +1,169 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD MMIO Map Manager APIs, and related functions. + * + * Contains code that manage MMIO base/limit registers + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e $Revision: 63522 $ @e $Date: 2011-12-25 20:25:03 -0600 (Sun, 25 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _MMIO_MAP_MANAGER_H_ +#define _MMIO_MAP_MANAGER_H_ + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ +// Forward declaration needed for multi-structure mutual references +AGESA_FORWARD_DECLARATION (MMIO_MAP_FAMILY_SERVICES); + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ +/// MMIO attribute +typedef struct _AMD_MMIO_ATTRIBUTE { + UINT8 MmioReadableRange:1; ///< Indicator whether the range is readable + UINT8 MmioWritableRange:1; ///< Indicator whether the range is writable + UINT8 MmioPostedRange:1; ///< Indicator whether the range is posted + UINT8 MmioSecuredRange:1; ///< Indicator whether the range is locked + UINT8 :4; ///< Reserved +} AMD_MMIO_ATTRIBUTE; + +/// MMIO destination +typedef struct _AMD_MMIO_DST { + UINT32 DstNode:3; ///< Destination node ID bits + UINT32 DstLink:2; ///< Destination link ID + UINT32 DstSubLink:1; ///< Destination sublink +} AMD_MMIO_DST; + +/// MMIO range +typedef struct _MMIO_RANGE { + UINT64 Base; ///< Base + UINT64 Limit; ///< Limit + AMD_MMIO_ATTRIBUTE Attribute; ///< Attribute + AMD_MMIO_DST Destination; ///< Destination + UINT8 RangeNum; ///< Range No. + BOOLEAN Modified; ///< if this MMIO base/limit registers need to be updated +} MMIO_RANGE; + +/// AMD_ADD_MMIO_PARAMS +typedef struct _AMD_ADD_MMIO_PARAMS { + AMD_CONFIG_PARAMS StdHeader; ///< Config Handle for library, services. + UINT64 BaseAddress; ///< This is the starting address of the requested MMIO range. + UINT64 Length; ///< This is the length of the range to allocate, in bytes. + PCI_ADDR TargetAddress; ///< This is the PCIe address of the device for which this range is allocated, and it + ///< provides the bus, device, and function of the target device. + AMD_MMIO_ATTRIBUTE Attributes;///< This indicates the attributes of the requested range. +} AMD_ADD_MMIO_PARAMS; + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to MMIO map manager. + * + * @param[in] MmioMapServices MMIO map manager services. + * @param[in] AmdAddMmioParams Pointer to a data structure containing the parameter information. + * + * @return Family specific error value. + * + */ +typedef AGESA_STATUS F_MMIO_MAP_ADDING_MAP ( + IN MMIO_MAP_FAMILY_SERVICES *MmioMapServices, + IN AMD_ADD_MMIO_PARAMS AmdAddMmioParams + ); + +/// Reference to a Method. +typedef F_MMIO_MAP_ADDING_MAP *PF_MMIO_MAP_ADDING_MAP; + +/** + * Provide the interface to the MMIO map manager Family Specific Services. + * + * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). + * Each supported Family must provide an implementation for all methods in this interface, even if the + * implementation is a CommonReturn(). + */ +struct _MMIO_MAP_FAMILY_SERVICES { + UINT16 Revision; ///< Interface version + // Public Methods. + PF_MMIO_MAP_ADDING_MAP addingMmioMap; ///< Method: Family specific call to adding MMIO map. +}; + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +AmdAddMmioMapping ( + IN AMD_ADD_MMIO_PARAMS AmdAddMmioParams + ); + +#endif // _MMIO_MAP_MANAGER_H_ + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdFch.h b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdFch.h new file mode 100644 index 0000000..5e4a66f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdFch.h @@ -0,0 +1,92 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD FCH Component + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _AMD_FCH_H_ +#define _AMD_FCH_H_ + +typedef AGESA_STATUS FCH_INIT (IN VOID *DataPtr); +typedef VOID FCH_TASK_ENTRY (IN VOID *FchCfg); + + +/// FCH API build options +typedef struct { + FCH_INIT *InitReset; ///< InitReset + FCH_INIT *InitResetConstructor; ///< InitResetConstructor + FCH_INIT *InitEnv; ///< InitEnv + FCH_INIT *InitEnvConstructor; ///< InitEnvConstructor + FCH_INIT *InitMid; ///< InitMid + FCH_INIT *InitMidConstructor; ///< InitMidConstructor + FCH_INIT *InitLate; ///< InitLate + FCH_INIT *InitLateConstructor; ///< InitLateConstructor +} BLDOPT_FCH_FUNCTION; + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEarly.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEarly.c new file mode 100644 index 0000000..a56cc1b --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEarly.c @@ -0,0 +1,346 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA Basic Level Public APIs + * + * Contains basic Level Initialization routines. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Interface + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuCacheInit.h" +#include "cpuRegisters.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "AdvancedApi.h" +#include "cpuServices.h" +#include "CommonInits.h" +#include "GnbInterface.h" +#include "Filecode.h" +#include "heapManager.h" +#include "CreateStruct.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_COMMON_AMDINITEARLY_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +EXECUTION_CACHE_REGION InitExeCacheMap[] = +{ + {0x00000000, 0x00000000}, + {0x00000000, 0x00000000}, + {0x00000000, 0x00000000} +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +AmdEarlyPlatformConfigInit ( + IN OUT PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +AllocateExecutionCacheInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr + ); +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern BUILD_OPT_CFG UserOptions; +/*------------------------------------------------------------------------------------*/ +/** + * Initialize AmdInitEarly stage platform profile and user option input. + * + * @param[in,out] PlatformConfig Platform profile/build option config structure + * @param[in,out] StdHeader AMD standard header config param + * + * @retval AGESA_SUCCESS Always Succeeds. + * + */ +AGESA_STATUS +AmdEarlyPlatformConfigInit ( + IN OUT PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + CommonPlatformConfigInit (PlatformConfig, StdHeader); + + return AGESA_SUCCESS; +} +/*------------------------------------------------------------------------------------*/ +/** + * Initializer routine that will be invoked by the wrapper to initialize the input + * structure for the AllocateExecutionCache. + * + * @param[in] StdHeader Opaque handle to standard config header + * @param[in] AmdExeAddrMapPtr Our Service interface struct + * + * @retval AGESA_SUCCESS Always Succeeds. + * + */ +AGESA_STATUS +AllocateExecutionCacheInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr + ) +{ + UINT8 i; + ASSERT (AmdExeAddrMapPtr != NULL); + + for (i = 0; i < MAX_CACHE_REGIONS; ++i) { + AmdExeAddrMapPtr[i].ExeCacheStartAddr = InitExeCacheMap[i].ExeCacheStartAddr; + AmdExeAddrMapPtr[i].ExeCacheSize = InitExeCacheMap[i].ExeCacheSize; + } + + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * + * Initializer routine that will be invoked by the wrapper to initialize the input + * structure for the AmdInitEarly. + * + * @param[in] StdHeader AMD standard header config param. + * @param[in,out] EarlyParams The service interface struct to initialize. + * + * @retval AGESA_SUCCESS Always succeeds. + */ +AGESA_STATUS +AmdInitEarlyInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT AMD_EARLY_PARAMS *EarlyParams + ) +{ + ASSERT (StdHeader != NULL); + ASSERT (EarlyParams != NULL); + + EarlyParams->StdHeader = *StdHeader; + + // We don't check any AGESA_STATUS from the called constructors, since they MUST all SUCCEED. + // + + AllocateExecutionCacheInitializer (&EarlyParams->StdHeader, &EarlyParams->CacheRegion[0]); + + AmdHtInterfaceConstructor (&EarlyParams->StdHeader, &EarlyParams->HtConfig); + + AmdEarlyPlatformConfigInit (&EarlyParams->PlatformConfig, &EarlyParams->StdHeader); + + return AGESA_SUCCESS; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Perform initialization services required at the Early Init POST time point. + * + * Execution Cache, HyperTransport, and AP Init advanced services are performed. + * + * @param[in] EarlyParams The interface struct for all early services + * + * @return The most severe AGESA_STATUS returned by any called service. + * + */ +AGESA_STATUS +AmdInitEarly ( + IN OUT AMD_EARLY_PARAMS *EarlyParams + ) +{ + AGESA_STATUS CalledAgesaStatus; + AGESA_STATUS EarlyInitStatus; + WARM_RESET_REQUEST Request; + UINT8 PrevRequestBit; + UINT8 PrevStateBits; + + IDS_PERF_TIMESTAMP (&EarlyParams->StdHeader); + + AGESA_TESTPOINT (TpIfAmdInitEarlyEntry, &EarlyParams->StdHeader); + + EarlyInitStatus = AGESA_SUCCESS; + + // Setup ROM execution cache + IDS_HDT_CONSOLE (MAIN_FLOW, "AllocateExecutionCache: Start\n"); + CalledAgesaStatus = AllocateExecutionCache (&EarlyParams->StdHeader, &EarlyParams->CacheRegion[0]); + IDS_HDT_CONSOLE (MAIN_FLOW, "AllocateExecutionCache: End\n"); + if (CalledAgesaStatus > EarlyInitStatus) { + EarlyInitStatus = CalledAgesaStatus; + } + + IDS_HDT_CONSOLE_DEBUG_CODE ( + { + extern CHAR8 *BldOptDebugOutput[]; + + UINT8 i; + for (i = 0; BldOptDebugOutput[i] != NULL; i++) { + IDS_HDT_CONSOLE (MAIN_FLOW, "\t%s\n", BldOptDebugOutput[i]); + } + } + ) + + // + // WARNING: AGESA's own IDT is at heap which would be moved from one place to another + // so we MUST restore IDT every time before moving heap. + // + IDS_EXCEPTION_TRAP (IDS_IDT_REPLACE_IDTR_FOR_BSC, NULL, &EarlyParams->StdHeader); + ASSERT (EarlyParams != NULL); + PrevRequestBit = FALSE; + PrevStateBits = WR_STATE_COLD; + IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitEarly: Start %x \n\n", PrevStateBits); + // If a previously requested warm reset cannot be triggered in the + // current stage, store the previous state of request and reset the + // request struct to the current post stage + GetWarmResetFlag (&EarlyParams->StdHeader, &Request); + if (Request.RequestBit == TRUE) { + if (Request.StateBits >= Request.PostStage) { + PrevRequestBit = Request.RequestBit; + PrevStateBits = Request.StateBits; + Request.RequestBit = FALSE; + Request.StateBits = Request.PostStage - 1; + SetWarmResetFlag (&EarlyParams->StdHeader, &Request); + } + } + + IDS_OPTION_HOOK (IDS_INIT_EARLY_BEFORE, EarlyParams, &EarlyParams->StdHeader); + + // Full Hypertransport Initialization + // IMPORTANT: All AP cores call Ht Init. HT Init handles full init for the BSC, and map init for APs. + IDS_PERF_TIMESTAMP (&EarlyParams->StdHeader); + IDS_HDT_CONSOLE (MAIN_FLOW, "AmdHtInitialize: Start\n"); + CalledAgesaStatus = AmdHtInitialize (&EarlyParams->StdHeader, &EarlyParams->PlatformConfig, &EarlyParams->HtConfig); + IDS_HDT_CONSOLE (MAIN_FLOW, "AmdHtInitialize: End\n"); + if (CalledAgesaStatus > EarlyInitStatus) { + EarlyInitStatus = CalledAgesaStatus; + } + + IDS_PERF_TIMESTAMP (&EarlyParams->StdHeader); + CalledAgesaStatus = GnbInitAtEarlier (EarlyParams); + if (CalledAgesaStatus > EarlyInitStatus) { + EarlyInitStatus = CalledAgesaStatus; + } + + // AP launch + IDS_PERF_TIMESTAMP (&EarlyParams->StdHeader); + IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuEarly: Start\n"); + CalledAgesaStatus = AmdCpuEarly (&EarlyParams->StdHeader, &EarlyParams->PlatformConfig); + IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuEarly: End\n"); + if (CalledAgesaStatus > EarlyInitStatus) { + EarlyInitStatus = CalledAgesaStatus; + } + + // Warm Reset, should be at the end of AmdInitEarly + GetWarmResetFlag (&EarlyParams->StdHeader, &Request); + // If a warm reset is requested in the current post stage, trigger the + // warm reset and ignore the previous request + if (Request.RequestBit == TRUE) { + if (Request.StateBits < Request.PostStage) { + AgesaDoReset (WARM_RESET_WHENEVER, &EarlyParams->StdHeader); + } + } else { + // Otherwise, if there's a previous request, restore it + // so that the subsequent post stage can trigger the warm reset + if (PrevRequestBit == TRUE) { + Request.RequestBit = PrevRequestBit; + Request.StateBits = PrevStateBits; + SetWarmResetFlag (&EarlyParams->StdHeader, &Request); + } + } + + IDS_PERF_TIMESTAMP (&EarlyParams->StdHeader); + CalledAgesaStatus = GnbInitAtEarly (EarlyParams); + if (CalledAgesaStatus > EarlyInitStatus) { + EarlyInitStatus = CalledAgesaStatus; + } + // Check for Cache As Ram Corruption + IDS_CAR_CORRUPTION_CHECK (&EarlyParams->StdHeader); + + IDS_OPTION_HOOK (IDS_INIT_EARLY_AFTER, EarlyParams, &EarlyParams->StdHeader); + AGESA_TESTPOINT (TpIfAmdInitEarlyExit, &EarlyParams->StdHeader); + IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitEarly: End\n\n"); + + // Flush out all debug contents in case warm reset is triggered after this point + IDS_HDT_CONSOLE_FLUSH_BUFFER (&EarlyParams->StdHeader); + IDS_PERF_TIMESTAMP (&EarlyParams->StdHeader); + + return EarlyInitStatus; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEnv.c new file mode 100644 index 0000000..b1d3c1b --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEnv.c @@ -0,0 +1,213 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA Basic Level Public APIs + * + * Contains basic Level Initialization routines. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Interface + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "cpuEnvInit.h" +#include "heapManager.h" +#include "GnbInterface.h" +#include "CommonInits.h" +#include "AmdFch.h" +#include "S3SaveState.h" +#include "Filecode.h" +#include "CreateStruct.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_COMMON_AMDINITENV_FILECODE + +extern BLDOPT_FCH_FUNCTION BldoptFchFunction; + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +/* + *--------------------------------------------------------------------------------------- + * + * Initializer routine that will be invoked by the wrapper + * to initialize the input structure for the AmdInitEnv + * + * @param[in,out] EnvParamsPtr Newly created interface parameters for AmdInitEnv + * + * @retval AGESA_SUCCESS Always succeeds + * + *--------------------------------------------------------------------------------------- + */ +AGESA_STATUS +AmdInitEnvInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT AMD_ENV_PARAMS *EnvParamsPtr + ) +{ + ASSERT (StdHeader != NULL); + ASSERT (EnvParamsPtr != NULL); + + EnvParamsPtr->StdHeader = *StdHeader; + + CommonPlatformConfigInit (&EnvParamsPtr->PlatformConfig, &EnvParamsPtr->StdHeader); + BldoptFchFunction.InitEnvConstructor (EnvParamsPtr); + GnbInitDataStructAtEnvDef (&EnvParamsPtr->GnbEnvConfiguration, EnvParamsPtr); + + return AGESA_SUCCESS; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Main entry point for the AMD_INIT_ENV function. + * + * This entry point is responsible for copying the heap contents from the + * temp RAM area to main memory. + * + * @param[in,out] EnvParams Required input parameters for the AMD_INIT_ENV + * entry point. + * + * @return Aggregated status across all internal AMD env calls invoked. + * + */ +AGESA_STATUS +AmdInitEnv ( + IN OUT AMD_ENV_PARAMS *EnvParams + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS AmdInitEnvStatus; + + AGESA_TESTPOINT (TpIfAmdInitEnvEntry, &EnvParams->StdHeader); + + ASSERT (EnvParams != NULL); + AmdInitEnvStatus = AGESA_SUCCESS; + + + //Copy Temp Ram heap content to Main Ram + AgesaStatus = CopyHeapToMainRamAtPost (&(EnvParams->StdHeader)); + if (AgesaStatus > AmdInitEnvStatus) { + AmdInitEnvStatus = AgesaStatus; + } + EnvParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + EnvParams->StdHeader.HeapBasePtr = HeapGetBaseAddress (&EnvParams->StdHeader); + // Any heap allocate/deallocat/locate buffer should be used after heap is rebuild from here. + // After persist heaps are tansfer and rebuild, HeapLocateBuffer can start to be used in IDS hook. + + //Heap have been relocated, so Debug Print need be init again to get new address + IDS_PERF_TIMESTAMP (&EnvParams->StdHeader); + IDS_HDT_CONSOLE_INIT (&EnvParams->StdHeader); + IDS_HDT_CONSOLE (MAIN_FLOW, "Heap transfer End\n"); + IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitEnv: Start\n\n"); + IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, &EnvParams->PlatformConfig, &(EnvParams->StdHeader)); + IDS_OPTION_HOOK (IDS_BEFORE_PCI_INIT, EnvParams, &(EnvParams->StdHeader)); + + AgesaStatus = S3ScriptInit (&EnvParams->StdHeader); + if (AgesaStatus > AmdInitEnvStatus) { + AmdInitEnvStatus = AgesaStatus; + } + + IDS_PERF_TIMESTAMP (&EnvParams->StdHeader); + AgesaStatus = BldoptFchFunction.InitEnv (EnvParams); + AmdInitEnvStatus = (AgesaStatus > AmdInitEnvStatus) ? AgesaStatus : AmdInitEnvStatus; + + IDS_PERF_TIMESTAMP (&EnvParams->StdHeader); + AgesaStatus = GnbInitAtEnv (EnvParams); + if (AgesaStatus > AmdInitEnvStatus) { + AmdInitEnvStatus = AgesaStatus; + } + + AGESA_TESTPOINT (TpIfAmdInitEnvExit, &EnvParams->StdHeader); + IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitEnv: End\n"); + IDS_PERF_TIMESTAMP (&EnvParams->StdHeader); + IDS_HDT_CONSOLE_FLUSH_BUFFER (&EnvParams->StdHeader); + return AmdInitEnvStatus; +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitLate.c new file mode 100644 index 0000000..9dd2d0d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitLate.c @@ -0,0 +1,331 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA Basic Level Public APIs + * + * Contains basic Level Initialization routines. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Interface + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionDmi.h" +#include "OptionSlit.h" +#include "cpuLateInit.h" +#include "cpuFeatures.h" +#include "CommonInits.h" +#include "GnbInterface.h" +#include "OptionPstate.h" +#include "Filecode.h" +#include "heapManager.h" +#include "CreateStruct.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_COMMON_AMDINITLATE_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern OPTION_DMI_CONFIGURATION OptionDmiConfiguration; // global user config record +extern OPTION_SLIT_CONFIGURATION OptionSlitConfiguration; // global user config record +extern OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +AmdLatePlatformConfigInit ( + IN OUT PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern BUILD_OPT_CFG UserOptions; + +/*------------------------------------------------------------------------------------*/ +/** + * Initialize AmdInitLate stage platform profile and user option input. + * + * @param[in,out] PlatformConfig Platform profile/build option config structure + * @param[in,out] StdHeader AMD standard header config param + * + * @retval AGESA_SUCCESS Always Succeeds. + * + */ +AGESA_STATUS +AmdLatePlatformConfigInit ( + IN OUT PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + CommonPlatformConfigInit (PlatformConfig, StdHeader); + + return AGESA_SUCCESS; +} + +/* + *--------------------------------------------------------------------------------------- + * + * AmdInitLateInitializer + * + * Initializer routine that will be invoked by the wrapper + * to initialize the input structure for the AmdInitLate + * + * @param[in, out] IN OUT AMD_LATE_PARAMS *LateParamsPtr + * + * @retval AGESA_STATUS + * + *--------------------------------------------------------------------------------------- + */ +AGESA_STATUS +AmdInitLateInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT AMD_LATE_PARAMS *LateParamsPtr + ) +{ + ASSERT (StdHeader != NULL); + ASSERT (LateParamsPtr != NULL); + + LateParamsPtr->StdHeader = *StdHeader; + + AmdLatePlatformConfigInit (&LateParamsPtr->PlatformConfig, &LateParamsPtr->StdHeader); + + LateParamsPtr->AcpiSlit = NULL; + + LateParamsPtr->AcpiSrat = NULL; + + LateParamsPtr->AcpiWheaMce = NULL; + LateParamsPtr->AcpiWheaCmc = NULL; + + LateParamsPtr->AcpiPState = NULL; + + LateParamsPtr->DmiTable = NULL; + + LateParamsPtr->AcpiAlib = NULL; + + LateParamsPtr->IvrsExclusionRangeList = UserOptions.CfgIvrsExclusionRangeList; + + return AGESA_SUCCESS; +} + +/* + *--------------------------------------------------------------------------------------- + * + * AmdInitLateDestructor + * + * Destruct routine that provide a chance if something need to be done + * before the end of AmdInitLate. + * + * @param[in] StdHeader The standard header. + * @param[in] LateParamsPtr AMD init late param. + * + * @retval AGESA_STATUS + * + *--------------------------------------------------------------------------------------- + */ +AGESA_STATUS +AmdInitLateDestructor ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_LATE_PARAMS *LateParamsPtr + ) +{ + + ASSERT (LateParamsPtr != NULL); + + (*(OptionDmiConfiguration.DmiReleaseBuffer)) (StdHeader); + (*(OptionSlitConfiguration.SlitReleaseBuffer)) (StdHeader); + + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Main entry point for the AMD_INIT_LATE function. + * + * This entry point is responsible for creating any desired ACPI tables, providing + * information for DMI, and to prepare the processors for the operating system + * bootstrap load process. + * + * @param[in,out] LateParams Required input parameters for the AMD_INIT_LATE + * entry point. + * + * @return Aggregated status across all internal AMD late calls invoked. + * + */ +AGESA_STATUS +AmdInitLate ( + IN OUT AMD_LATE_PARAMS *LateParams + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS AmdInitLateStatus; + + IDS_PERF_TIMESTAMP (&LateParams->StdHeader); + IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitLate: Start\n\n"); + AGESA_TESTPOINT (TpIfAmdInitLateEntry, &LateParams->StdHeader); + + ASSERT (LateParams != NULL); + AmdInitLateStatus = AGESA_SUCCESS; + + IDS_OPTION_HOOK (IDS_INIT_LATE_BEFORE, LateParams, &LateParams->StdHeader); + + IDS_PERF_TIMESTAMP (&LateParams->StdHeader); + IDS_HDT_CONSOLE (MAIN_FLOW, "CreatSystemTable: Start\n"); + // _PSS, XPSS, _PCT, _PSD, _PPC, _CST, _CSD Tables + if ((LateParams->PlatformConfig.UserOptionPState) || (IsFeatureEnabled (IoCstate, &LateParams->PlatformConfig, &LateParams->StdHeader))) { + AgesaStatus = ((*(OptionPstateLateConfiguration.SsdtFeature)) (&LateParams->StdHeader, &LateParams->PlatformConfig, &LateParams->AcpiPState)); + if (AgesaStatus > AmdInitLateStatus) { + AmdInitLateStatus = AgesaStatus; + } + } + + + + // SRAT Table Generation + if (LateParams->PlatformConfig.UserOptionSrat) { + AgesaStatus = CreateAcpiSrat (&LateParams->StdHeader, &LateParams->AcpiSrat); + if (AgesaStatus > AmdInitLateStatus) { + AmdInitLateStatus = AgesaStatus; + } + } + + // SLIT Table Generation + if (LateParams->PlatformConfig.UserOptionSlit) { + AgesaStatus = CreateAcpiSlit (&LateParams->StdHeader, &LateParams->PlatformConfig, &LateParams->AcpiSlit); + if (AgesaStatus > AmdInitLateStatus) { + AmdInitLateStatus = AgesaStatus; + } + } + + // WHEA Table Generation + if (LateParams->PlatformConfig.UserOptionWhea) { + AgesaStatus = CreateAcpiWhea (&LateParams->StdHeader, &LateParams->AcpiWheaMce, &LateParams->AcpiWheaCmc); + if (AgesaStatus > AmdInitLateStatus) { + AmdInitLateStatus = AgesaStatus; + } + } + + // DMI Table Generation + if (LateParams->PlatformConfig.UserOptionDmi) { + AgesaStatus = CreateDmiRecords (&LateParams->StdHeader, &LateParams->DmiTable); + if (AgesaStatus > AmdInitLateStatus) { + AmdInitLateStatus = AgesaStatus; + } + } + IDS_HDT_CONSOLE (MAIN_FLOW, "CreatSystemTable: End\n"); + + // Cpu Features + IDS_PERF_TIMESTAMP (&LateParams->StdHeader); + IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: LateStart\n"); + AgesaStatus = DispatchCpuFeatures (CPU_FEAT_INIT_LATE_END, &LateParams->PlatformConfig, &LateParams->StdHeader); + IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: LateEnd\n"); + if (AgesaStatus > AmdInitLateStatus) { + AmdInitLateStatus = AgesaStatus; + } + + // It is the last function run by the AGESA CPU module and prepares the processor + // for the operating system bootstrap load process. + IDS_PERF_TIMESTAMP (&LateParams->StdHeader); + IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuLate: Start\n"); + AgesaStatus = AmdCpuLate (&LateParams->StdHeader, &LateParams->PlatformConfig); + IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuLate: End\n"); + if (AgesaStatus > AmdInitLateStatus) { + AmdInitLateStatus = AgesaStatus; + } + + IDS_PERF_TIMESTAMP (&LateParams->StdHeader); + AgesaStatus = GnbInitAtLate (LateParams); + if (AgesaStatus > AmdInitLateStatus) { + AmdInitLateStatus = AgesaStatus; + } + + IDS_OPTION_HOOK (IDS_INIT_LATE_AFTER, LateParams, &LateParams->StdHeader); + AGESA_TESTPOINT (TpIfAmdInitLateExit, &LateParams->StdHeader); + IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitLate: End\n\n"); + AGESA_TESTPOINT (EndAgesaTps, &LateParams->StdHeader); +//End Debug Print Service + IDS_HDT_CONSOLE_EXIT (&LateParams->StdHeader); + IDS_PERF_TIMESTAMP (&LateParams->StdHeader); + IDS_PERF_ANALYSE (&LateParams->StdHeader); + + return AmdInitLateStatus; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitMid.c new file mode 100644 index 0000000..f4b0b45 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitMid.c @@ -0,0 +1,201 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA Basic Level Public APIs + * + * Contains basic Level Initialization routines. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Interface + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "cpuFeatures.h" +#include "CommonInits.h" +#include "GnbInterface.h" +#include "AmdFch.h" +#include "Filecode.h" +#include "heapManager.h" +#include "CreateStruct.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_COMMON_AMDINITMID_FILECODE + +extern BLDOPT_FCH_FUNCTION BldoptFchFunction; + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +/* + *--------------------------------------------------------------------------------------- + * + * Initializer routine that will be invoked by the wrapper + * to initialize the input structure for the AmdInitMid + * + * @param[in,out] MidParamsPtr Newly created interface parameters for AmdInitMid + * + * @retval AGESA_SUCCESS Always succeeds + * + *--------------------------------------------------------------------------------------- + */ +AGESA_STATUS +AmdInitMidInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT AMD_MID_PARAMS *MidParamsPtr + ) +{ + ASSERT (StdHeader != NULL); + ASSERT (MidParamsPtr != NULL); + + MidParamsPtr->StdHeader = *StdHeader; + CommonPlatformConfigInit (&MidParamsPtr->PlatformConfig, &MidParamsPtr->StdHeader); + BldoptFchFunction.InitMidConstructor (MidParamsPtr); + + return AGESA_SUCCESS; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Main entry point for the AMD_INIT_MID function. + * + * This entry point is responsible for performing any necessary functions needed + * after PCI bus enumeration and just before control is passed to the video option ROM. + * + * @param[in,out] MidParams Required input parameters for the AMD_INIT_MID + * entry point. + * + * @return Aggregated status across all internal AMD mid calls invoked. + * + */ +AGESA_STATUS +AmdInitMid ( + IN OUT AMD_MID_PARAMS *MidParams + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS CalledStatus; + + IDS_PERF_TIMESTAMP (&MidParams->StdHeader); + IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitMid: Start\n\n"); + AGESA_TESTPOINT (TpIfAmdInitMidEntry, &MidParams->StdHeader); + + AgesaStatus = AGESA_SUCCESS; + + ASSERT (MidParams != NULL); + IDS_OPTION_HOOK (IDS_INIT_MID_BEFORE, MidParams, &MidParams->StdHeader); + + IDS_PERF_TIMESTAMP (&MidParams->StdHeader); + IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: MidStart\n"); + CalledStatus = DispatchCpuFeatures (CPU_FEAT_INIT_MID_END, &MidParams->PlatformConfig, &MidParams->StdHeader); + IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: MidEnd\n"); + if (CalledStatus > AgesaStatus) { + AgesaStatus = CalledStatus; + } + + IDS_PERF_TIMESTAMP (&MidParams->StdHeader); + CalledStatus = BldoptFchFunction.InitMid (MidParams); + AgesaStatus = (CalledStatus > AgesaStatus) ? CalledStatus : AgesaStatus; + + IDS_PERF_TIMESTAMP (&MidParams->StdHeader); + CalledStatus = GnbInitAtMid (MidParams); + if (CalledStatus > AgesaStatus) { + AgesaStatus = CalledStatus; + } + + IDS_OPTION_HOOK (IDS_INIT_MID_AFTER, MidParams, &MidParams->StdHeader); + + AGESA_TESTPOINT (TpIfAmdInitMidExit, &MidParams->StdHeader); + IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitMid: End\n\n"); + IDS_HDT_CONSOLE_FLUSH_BUFFER (&MidParams->StdHeader); + IDS_PERF_TIMESTAMP (&MidParams->StdHeader); + + return AgesaStatus; +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitPost.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitPost.c new file mode 100644 index 0000000..1dd6719 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitPost.c @@ -0,0 +1,373 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA Basic Level Public APIs + * + * Contains basic Level Initialization routines. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Interface + * @e $Revision: 63692 $ @e $Date: 2012-01-03 22:13:28 -0600 (Tue, 03 Jan 2012) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "mm.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuServices.h" +#include "cpuPostInit.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CommonInits.h" +#include "cpuServices.h" +#include "GnbInterface.h" +#include "Filecode.h" +#include "CreateStruct.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_COMMON_AMDINITPOST_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +AmdPostPlatformConfigInit ( + IN OUT PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/*------------------------------------------------------------------------------------*/ +/** + * Initialize AmdInitPost stage platform profile and user option input. + * + * @param[in,out] PlatformConfig Platform profile/build option config structure + * @param[in,out] StdHeader AMD standard header config param + * + * @retval AGESA_SUCCESS Always Succeeds. + * + */ +AGESA_STATUS +AmdPostPlatformConfigInit ( + IN OUT PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + CommonPlatformConfigInit (PlatformConfig, StdHeader); + + return AGESA_SUCCESS; +} + +/* + *--------------------------------------------------------------------------------------- + * + * AmdInitPostInitializer + * + * Initializer routine that will be invoked by the wrapper + * to initialize the input structure for the AmdInitPost + * + * @param[in, out] IN OUT AMD_POST_PARAMS *PostParamsPtr + * + * @retval AGESA_STATUS + * + *--------------------------------------------------------------------------------------- + */ +AGESA_STATUS +AmdInitPostInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT AMD_POST_PARAMS *PostParamsPtr + ) +{ + AGESA_STATUS AgesaStatus; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + ASSERT (StdHeader != NULL); + ASSERT (PostParamsPtr != NULL); + + PostParamsPtr->StdHeader = *StdHeader; + + AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT); + AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + AgesaStatus = HeapAllocateBuffer (&AllocHeapParams, &PostParamsPtr->StdHeader); + + if (AgesaStatus == AGESA_SUCCESS) { + PostParamsPtr->MemConfig.MemData = (MEM_DATA_STRUCT *) AllocHeapParams.BufferPtr; + PostParamsPtr->MemConfig.MemData->ParameterListPtr = &(PostParamsPtr->MemConfig); + PostParamsPtr->MemConfig.MemData->StdHeader = PostParamsPtr->StdHeader; + AmdPostPlatformConfigInit (&PostParamsPtr->PlatformConfig, &PostParamsPtr->StdHeader); + AmdMemInitDataStructDef (PostParamsPtr->MemConfig.MemData, &PostParamsPtr->PlatformConfig); + GnbInitDataStructAtPostDef (&PostParamsPtr->GnbPostConfig, PostParamsPtr); + } + return AgesaStatus; +} + +/* + *--------------------------------------------------------------------------------------- + * + * AmdInitPostDestructor + * + * Destruct routine that provide a chance if something need to be done + * before the end of AmdInitPost. + * + * @param[in] StdHeader The standard header. + * @param[in] PostParamsPtr AMD init post param. + * + * @retval AGESA_STATUS + * + *--------------------------------------------------------------------------------------- + */ +AGESA_STATUS +AmdInitPostDestructor ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_POST_PARAMS *PostParamsPtr + ) +{ + + ASSERT (PostParamsPtr != NULL); + + PostParamsPtr->StdHeader = *StdHeader; + PostParamsPtr->MemConfig.MemData->StdHeader = *StdHeader; + + // + // AmdMemAuto completed. Here, release heap space which is used for memory init. + // + MemAmdFinalize (PostParamsPtr->MemConfig.MemData); + HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader); + + // + // AmdCpuPost completed. + // + if (PostParamsPtr->MemConfig.SysLimit != 0) { + // WBINVD can only be executed when memory is available + FinalizeAtPost (StdHeader); + } + + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Main entry point for the AMD_INIT_POST function. + * + * This entry point is responsible for initializing all system memory, + * gathering important data out of the pre-memory cache storage into a + * temporary holding buffer in main memory. After that APs will be + * shutdown in preparation for the host environment to take control. + * Note: pre-memory stack will be disabled also. + * + * @param[in,out] PostParams Required input parameters for the AMD_INIT_POST + * entry point. + * + * @return Aggregated status across all internal AMD POST calls invoked. + * + */ +AGESA_STATUS +AmdInitPost ( + IN OUT AMD_POST_PARAMS *PostParams + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS AmdInitPostStatus; + WARM_RESET_REQUEST Request; + UINT8 PrevRequestBit; + UINT8 PrevStateBits; + + IDS_PERF_TIMESTAMP (&PostParams->StdHeader); + AGESA_TESTPOINT (TpIfAmdInitPostEntry, &PostParams->StdHeader); + IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitPost: Start\n\n"); + + ASSERT (PostParams != NULL); + AmdInitPostStatus = AGESA_SUCCESS; + PrevRequestBit = FALSE; + PrevStateBits = WR_STATE_COLD; + + IDS_OPTION_HOOK (IDS_INIT_POST_BEFORE, PostParams, &PostParams->StdHeader); + + // If a previously requested warm reset cannot be triggered in the + // current stage, store the previous state of request and reset the + // request struct to the current post stage + GetWarmResetFlag (&PostParams->StdHeader, &Request); + if (Request.RequestBit == TRUE) { + if (Request.StateBits >= Request.PostStage) { + PrevRequestBit = Request.RequestBit; + PrevStateBits = Request.StateBits; + Request.RequestBit = FALSE; + Request.StateBits = Request.PostStage - 1; + SetWarmResetFlag (&PostParams->StdHeader, &Request); + } + } + + IDS_PERF_TIMESTAMP (&PostParams->StdHeader); + AgesaStatus = GnbInitAtPost (PostParams); + if (AgesaStatus > AmdInitPostStatus) { + AmdInitPostStatus = AgesaStatus; + } + + IDS_PERF_TIMESTAMP (&PostParams->StdHeader); + IDS_HDT_CONSOLE (MAIN_FLOW, "AmdMemAuto: Start\n"); + AgesaStatus = AmdMemAuto (PostParams->MemConfig.MemData); + IDS_HDT_CONSOLE (MAIN_FLOW, "AmdMemAuto: End\n"); + if (AgesaStatus > AmdInitPostStatus) { + AmdInitPostStatus = AgesaStatus; + } + + // Check BIST status + AgesaStatus = CheckBistStatus (&PostParams->StdHeader); + if (AgesaStatus > AmdInitPostStatus) { + AmdInitPostStatus = AgesaStatus; + } + + // + // P-State data gathered, then, Relinquish APs + // + IDS_PERF_TIMESTAMP (&PostParams->StdHeader); + IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuPost: Start\n"); + AgesaStatus = AmdCpuPost (&PostParams->StdHeader, &PostParams->PlatformConfig); + IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuPost: End\n"); + if (AgesaStatus > AmdInitPostStatus) { + AmdInitPostStatus = AgesaStatus; + } + + if (AgesaStatus != AGESA_FATAL) { + + // Warm Reset + GetWarmResetFlag (&PostParams->StdHeader, &Request); + // If a warm reset is requested in the current post stage, trigger the + // warm reset and ignore the previous request + if (Request.RequestBit == TRUE) { + if (Request.StateBits < Request.PostStage) { + AgesaDoReset (WARM_RESET_WHENEVER, &PostParams->StdHeader); + } + } else { + // Otherwise, if there's a previous request, restore it + // so that the subsequent post stage can trigger the warm reset + if (PrevRequestBit == TRUE) { + Request.RequestBit = PrevRequestBit; + Request.StateBits = PrevStateBits; + SetWarmResetFlag (&PostParams->StdHeader, &Request); + } + } + + IDS_PERF_TIMESTAMP (&PostParams->StdHeader); + AgesaStatus = GnbInitAtPostAfterDram (PostParams); + if (AgesaStatus > AmdInitPostStatus) { + AmdInitPostStatus = AgesaStatus; + } + + IDS_OPTION_HOOK (IDS_INIT_POST_AFTER, PostParams, &PostParams->StdHeader); + + AGESA_TESTPOINT (TpIfAmdInitPostExit, &PostParams->StdHeader); + IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitPost: End\n\n"); + IDS_HDT_CONSOLE (MAIN_FLOW, "Heap transfer Start ...\n\n"); + + //For Heap will be relocate to new address in next stage, flush out debug print buffer if needed + IDS_HDT_CONSOLE_FLUSH_BUFFER (&PostParams->StdHeader); + + // WARNING: IDT will be moved from local cache to temp memory, so restore IDTR for BSP here + IDS_EXCEPTION_TRAP (IDS_IDT_RESTORE_IDTR_FOR_BSC, NULL, &PostParams->StdHeader); + IDS_PERF_TIMESTAMP (&PostParams->StdHeader); + + // Copies BSP heap content to RAM, and it should be at the end of AmdInitPost + AgesaStatus = CopyHeapToTempRamAtPost (&(PostParams->StdHeader)); + if (AgesaStatus > AmdInitPostStatus) { + AmdInitPostStatus = AgesaStatus; + } + PostParams->StdHeader.HeapStatus = HEAP_TEMP_MEM; + } + // Check for Cache As Ram Corruption + IDS_CAR_CORRUPTION_CHECK (&PostParams->StdHeader); + + // At the end of AmdInitPost, set StateBits to POST to allow any warm reset that occurs outside + // of AGESA to be recognized by IsWarmReset() + GetWarmResetFlag (&PostParams->StdHeader, &Request); + Request.StateBits = Request.PostStage; + SetWarmResetFlag (&PostParams->StdHeader, &Request); + + return AmdInitPostStatus; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitRecovery.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitRecovery.c new file mode 100644 index 0000000..12b2d76 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitRecovery.c @@ -0,0 +1,195 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA Basic Level Public APIs + * + * Contains basic Level Initialization routines. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Common + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "mm.h" +#include "GnbInterface.h" +#include "cpuRecovery.h" +#include "cpuCacheInit.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_COMMON_AMDINITRECOVERY_FILECODE + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Perform initialization services required at the Early Init POST time point. + * + * Execution Cache, HyperTransport, C1e, and AP Init advanced services are performed. + * + * @param[in, out] RecoveryParams The interface struct for Recovery services + * + * @return The most severe AGESA_STATUS returned by any called service. + * + */ +AGESA_STATUS +AmdInitRecovery ( + IN OUT AMD_RECOVERY_PARAMS *RecoveryParams + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS CalledAgesaStatus; + + AGESA_TESTPOINT (TpIfAmdInitRecoveryEntry, &RecoveryParams->StdHeader); + + ASSERT (RecoveryParams != NULL); + + AgesaStatus = AGESA_SUCCESS; + + // Setup ROM execution cache + CalledAgesaStatus = AllocateExecutionCache (&RecoveryParams->StdHeader, &RecoveryParams->CacheRegion[0]); + if (CalledAgesaStatus > AgesaStatus) { + AgesaStatus = CalledAgesaStatus; + } + + CalledAgesaStatus = AmdHtInitRecovery (&RecoveryParams->StdHeader); + if (CalledAgesaStatus > AgesaStatus) { + AgesaStatus = CalledAgesaStatus; + } + + CalledAgesaStatus = AmdCpuRecovery ((AMD_CPU_RECOVERY_PARAMS *) &RecoveryParams->StdHeader); + if (CalledAgesaStatus > AgesaStatus) { + AgesaStatus = CalledAgesaStatus; + } + + CalledAgesaStatus = AmdMemRecovery (RecoveryParams->MemConfig.MemData); + if (CalledAgesaStatus > AgesaStatus) { + AgesaStatus = CalledAgesaStatus; + } + + CalledAgesaStatus = AmdGnbRecovery (&RecoveryParams->StdHeader); + if (CalledAgesaStatus > AgesaStatus) { + AgesaStatus = CalledAgesaStatus; + } + + AGESA_TESTPOINT (TpIfAmdInitRecoveryExit, &RecoveryParams->StdHeader); + return AgesaStatus; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * + * Initialize defaults and options for Amd Init Reset. + * + * @param[in] StdHeader AMD standard header config param. + * @param[in] AmdRecoveryParamsPtr The Reset Init interface to initialize. + * + * @retval AGESA_SUCCESS Always Succeeds. + */ +AGESA_STATUS +AmdInitRecoveryInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT AMD_RECOVERY_PARAMS *AmdRecoveryParamsPtr + ) +{ + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + ASSERT (StdHeader != NULL); + ASSERT (AmdRecoveryParamsPtr != NULL); + + AmdRecoveryParamsPtr->StdHeader = *StdHeader; + + AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT); + AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, &AmdRecoveryParamsPtr->StdHeader) == AGESA_SUCCESS) { + AmdRecoveryParamsPtr->MemConfig.MemData = (MEM_DATA_STRUCT *) AllocHeapParams.BufferPtr; + AmdRecoveryParamsPtr->MemConfig.MemData->ParameterListPtr = &(AmdRecoveryParamsPtr->MemConfig); + LibAmdMemCopy ((VOID *) AmdRecoveryParamsPtr->MemConfig.MemData, + (VOID *) AmdRecoveryParamsPtr, + (UINTN) sizeof (AmdRecoveryParamsPtr->StdHeader), + &AmdRecoveryParamsPtr->StdHeader + ); + AmdMemInitDataStructDefRecovery (AmdRecoveryParamsPtr->MemConfig.MemData); + return AGESA_SUCCESS; + } else { + return AGESA_ERROR; + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitReset.c new file mode 100644 index 0000000..a15855f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitReset.c @@ -0,0 +1,283 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA Basic Level Public APIs + * + * Contains basic Level Initialization routines. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Interface + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuCacheInit.h" +#include "cpuServices.h" +#include "AdvancedApi.h" +#include "GeneralServices.h" +#include "OptionsHt.h" +#include "AmdFch.h" +#include "Filecode.h" +#include "heapManager.h" +#include "CreateStruct.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_COMMON_AMDINITRESET_FILECODE + +extern BLDOPT_FCH_FUNCTION BldoptFchFunction; + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern CONST OPTION_HT_INIT_RESET HtOptionInitReset; +extern BUILD_OPT_CFG UserOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +AmdInitResetExecutionCacheAllocateInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr + ); +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*------------------------------------------------------------------------------------*/ +/** + * Initializer routine that will be invoked by the wrapper to initialize the input + * structure for the AllocateExecutionCache. + * + * Parameters: + * @param[in] StdHeader Opaque handle to standard config header + * @param[in] AmdExeAddrMapPtr Our Service interface struct + * + * @retval AGESA_SUCCESS Always Succeeds. + * + */ +AGESA_STATUS +AmdInitResetExecutionCacheAllocateInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr + ) +{ + ASSERT (AmdExeAddrMapPtr != NULL); + + LibAmdMemFill (AmdExeAddrMapPtr, 0, sizeof (EXECUTION_CACHE_REGION) * MAX_CACHE_REGIONS, StdHeader); + + return AGESA_SUCCESS; +} +/*---------------------------------------------------------------------------------------*/ +/** + * Main entry point for the AMD_INIT_RESET function. + * + * This entry point is responsible for establishing the HT links to the program + * ROM and for performing basic processor initialization. + * + * @param[in,out] ResetParams Required input parameters for the AMD_INIT_RESET + * entry point. + * + * @return Aggregated status across all internal AMD reset calls invoked. + * + */ +AGESA_STATUS +AmdInitReset ( + IN OUT AMD_RESET_PARAMS *ResetParams + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS CalledAgesaStatus; + WARM_RESET_REQUEST Request; + UINT8 PrevRequestBit; + UINT8 PrevStateBits; + + IDS_PERF_TIMESTAMP (&ResetParams->StdHeader); + AgesaStatus = AGESA_SUCCESS; + + // Setup ROM execution cache + CalledAgesaStatus = AllocateExecutionCache (&ResetParams->StdHeader, &ResetParams->CacheRegion[0]); + if (CalledAgesaStatus > AgesaStatus) { + AgesaStatus = CalledAgesaStatus; + } + + //IDS_EXTENDED_HOOK (IDS_INIT_RESET_BEFORE, NULL, NULL, &ResetParams->StdHeader); + + // Init Debug Print function + IDS_HDT_CONSOLE_INIT (&ResetParams->StdHeader); + + IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitReset: Start\n\n"); + + IDS_HDT_CONSOLE (MAIN_FLOW, "\n*** %s ***\n\n", &UserOptions.VersionString); + + AGESA_TESTPOINT (TpIfAmdInitResetEntry, &ResetParams->StdHeader); + ASSERT (ResetParams != NULL); + + PrevRequestBit = FALSE; + PrevStateBits = WR_STATE_COLD; + + IDS_PERF_TIMESTAMP (&ResetParams->StdHeader); + if (IsBsp (&ResetParams->StdHeader, &AgesaStatus)) { + CalledAgesaStatus = BldoptFchFunction.InitReset (ResetParams); + AgesaStatus = (CalledAgesaStatus > AgesaStatus) ? CalledAgesaStatus : AgesaStatus; + } + + // If a previously requested warm reset cannot be triggered in the + // current stage, store the previous state of request and reset the + // request struct to the current post stage + GetWarmResetFlag (&ResetParams->StdHeader, &Request); + if (Request.RequestBit == TRUE) { + if (Request.StateBits >= Request.PostStage) { + PrevRequestBit = Request.RequestBit; + PrevStateBits = Request.StateBits; + Request.RequestBit = FALSE; + Request.StateBits = Request.PostStage - 1; + SetWarmResetFlag (&ResetParams->StdHeader, &Request); + } + } + + // Initialize the PCI MMIO access mechanism + InitializePciMmio (&ResetParams->StdHeader); + + IDS_PERF_TIMESTAMP (&ResetParams->StdHeader); + // Initialize Hyper Transport Registers + if (HtOptionInitReset.HtInitReset != NULL) { + IDS_HDT_CONSOLE (MAIN_FLOW, "HtInitReset: Start\n"); + CalledAgesaStatus = HtOptionInitReset.HtInitReset (&ResetParams->StdHeader, &ResetParams->HtConfig); + IDS_HDT_CONSOLE (MAIN_FLOW, "HtInitReset: End\n"); + if (CalledAgesaStatus > AgesaStatus) { + AgesaStatus = CalledAgesaStatus; + } + } + + // Warm Reset, should be at the end of AmdInitReset + GetWarmResetFlag (&ResetParams->StdHeader, &Request); + // If a warm reset is requested in the current post stage, trigger the + // warm reset and ignore the previous request + if (Request.RequestBit == TRUE) { + if (Request.StateBits < Request.PostStage) { + AgesaDoReset (WARM_RESET_WHENEVER, &ResetParams->StdHeader); + } + } else { + // Otherwise, if there's a previous request, restore it + // so that the subsequent post stage can trigger the warm reset + if (PrevRequestBit == TRUE) { + Request.RequestBit = PrevRequestBit; + Request.StateBits = PrevStateBits; + SetWarmResetFlag (&ResetParams->StdHeader, &Request); + } + } + // Check for Cache As Ram Corruption + IDS_CAR_CORRUPTION_CHECK (&ResetParams->StdHeader); + IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitReset: End\n\n"); + + AGESA_TESTPOINT (TpIfAmdInitResetExit, &ResetParams->StdHeader); + + IDS_PERF_TIMESTAMP (&ResetParams->StdHeader); + + return AgesaStatus; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Initialize defaults and options for Amd Init Reset. + * + * @param[in] StdHeader Header + * @param[in] AmdResetParams The Reset Init interface to initialize. + * + * @retval AGESA_SUCCESS Always Succeeds. + */ +AGESA_STATUS +AmdInitResetConstructor ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_RESET_PARAMS *AmdResetParams + ) +{ + ASSERT (AmdResetParams != NULL); + + AmdResetParams->StdHeader = *StdHeader; + + AmdInitResetExecutionCacheAllocateInitializer (&AmdResetParams->StdHeader, &AmdResetParams->CacheRegion[0]); + // Initialize Hyper Transport input structure + if (HtOptionInitReset.HtResetConstructor != NULL) { + HtOptionInitReset.HtResetConstructor (&AmdResetParams->StdHeader, &AmdResetParams->HtConfig); + } + BldoptFchFunction.InitResetConstructor (AmdResetParams); + + return AGESA_SUCCESS; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitResume.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitResume.c new file mode 100644 index 0000000..a86fb2a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitResume.c @@ -0,0 +1,272 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA Basic Level Public APIs + * + * Contains basic Level Initialization routines. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Interface + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "S3.h" +#include "mfs3.h" +#include "Filecode.h" +#include "cpuRegisters.h" +#include "cpuApicUtilities.h" +#include "cpuPostInit.h" +#include "CommonInits.h" +#include "cpuFeatures.h" +#include "heapManager.h" +#include "CreateStruct.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_COMMON_AMDINITRESUME_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Main entry point for the AMD_INIT_RESUME function. + * + * This entry point is responsible for performing silicon device and memory + * re-initialization for the resume boot path. + * + * @param[in] ResumeParams Required input parameters for the AMD_INIT_RESUME + * entry point. + * + * @return Aggregated status across all internal AMD resume calls invoked. + * + */ +AGESA_STATUS +AmdInitResume ( + IN AMD_RESUME_PARAMS *ResumeParams + ) +{ + VOID *OrMaskPtr; + AGESA_STATUS ReturnStatus; + AGESA_STATUS AmdInitResumeStatus; + BSC_AP_MSR_SYNC ApMsrSync[4]; + + IDS_PERF_TIMESTAMP (&ResumeParams->StdHeader); + AGESA_TESTPOINT (TpIfAmdInitResumeEntry, &ResumeParams->StdHeader); + IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitResume Start\n"); + + AmdInitResumeStatus = AGESA_SUCCESS; + + ASSERT (ResumeParams != NULL); + + if (ResumeParams->S3DataBlock.NvStorage != NULL) { + + MemS3ResumeInitNB (&ResumeParams->StdHeader); + + // Restore registers before exiting self refresh + RestorePreESRContext (&OrMaskPtr, + ResumeParams->S3DataBlock.NvStorage, + INIT_RESUME, + &ResumeParams->StdHeader); + // Exit self refresh + ReturnStatus = AmdMemS3Resume (&ResumeParams->StdHeader); + IDS_PERF_TIMESTAMP (&ResumeParams->StdHeader); + if (ReturnStatus > AmdInitResumeStatus) { + AmdInitResumeStatus = ReturnStatus; + } + if (ReturnStatus == AGESA_SUCCESS) { + + // Restore registers after exiting self refresh + RestorePostESRContext (OrMaskPtr, + ResumeParams->S3DataBlock.NvStorage, + INIT_RESUME, + &ResumeParams->StdHeader); + + ApMsrSync[0].RegisterAddress = SYS_CFG; + ApMsrSync[1].RegisterAddress = TOP_MEM; + ApMsrSync[2].RegisterAddress = TOP_MEM2; + ApMsrSync[3].RegisterAddress = 0; + SyncApMsrsToBsc (ApMsrSync, &ResumeParams->StdHeader); + IDS_PERF_TIMESTAMP (&ResumeParams->StdHeader); + + IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features after S3 AP MTRR sync\n"); + ReturnStatus = DispatchCpuFeatures (CPU_FEAT_AFTER_RESUME_MTRR_SYNC, &ResumeParams->PlatformConfig, &ResumeParams->StdHeader); + IDS_PERF_TIMESTAMP (&ResumeParams->StdHeader); + if (ReturnStatus > AmdInitResumeStatus) { + AmdInitResumeStatus = ReturnStatus; + } + } + } + + // Set TscFreqSel at the rate specified by the core P0 + SetCoresTscFreqSel (&ResumeParams->StdHeader); + + IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitResume End\n"); + // HDT out of All Aps + IDS_HDT_CONSOLE_FLUSH_BUFFER (&ResumeParams->StdHeader); + // Relinquish control of all APs to IBV + RelinquishControlOfAllAPs (&ResumeParams->StdHeader); + + // Restore IDT + IDS_EXCEPTION_TRAP (IDS_IDT_RESTORE_IDTR_FOR_BSC, NULL, &ResumeParams->StdHeader); + IDS_OPTION_HOOK (IDS_AFTER_S3_RESUME, NULL, &ResumeParams->StdHeader); + AGESA_TESTPOINT (TpIfAmdInitResumeExit, &ResumeParams->StdHeader); + IDS_PERF_TIMESTAMP (&ResumeParams->StdHeader); + IDS_PERF_ANALYSE (&ResumeParams->StdHeader); + + return (AmdInitResumeStatus); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Constructor for the AMD_INIT_RESUME function. + * + * This routine is responsible for setting default values for the + * input parameters needed by the AMD_INIT_RESUME entry point. + * + * @param[in] StdHeader The standard header. + * @param[in,out] ResumeParams Required input parameters for the AMD_INIT_RESUME + * entry point. + * + * @retval AGESA_SUCCESS Always Succeeds. + * + */ +AGESA_STATUS +AmdInitResumeInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT AMD_RESUME_PARAMS *ResumeParams + ) +{ + ASSERT (StdHeader != NULL); + ASSERT (ResumeParams != NULL); + + ResumeParams->StdHeader = *StdHeader; + + AmdS3ParamsInitializer (&ResumeParams->S3DataBlock); + CommonPlatformConfigInit (&ResumeParams->PlatformConfig, &ResumeParams->StdHeader); + + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Destructor for the AMD_INIT_RESUME function. + * + * This routine is responsible for deallocation of heap space allocated during + * AMD_INIT_RESUME entry point. + * + * @param[in] StdHeader The standard header. + * @param[in,out] ResumeParams Required input parameters for the AMD_INIT_RESUME + * entry point. + * + * @retval AGESA_STATUS + * + */ +AGESA_STATUS +AmdInitResumeDestructor ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT AMD_RESUME_PARAMS *ResumeParams + ) +{ + AGESA_STATUS ReturnStatus; + AGESA_STATUS RetVal; + + ASSERT (ResumeParams != NULL); + + ReturnStatus = AGESA_SUCCESS; + + // Deallocate heap space allocated during memory S3 resume + RetVal = MemS3Deallocate (&ResumeParams->StdHeader); + if (RetVal > ReturnStatus) { + ReturnStatus = RetVal; + } + + return ReturnStatus; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdLateRunApTask.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdLateRunApTask.c new file mode 100644 index 0000000..b9cf7a9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdLateRunApTask.c @@ -0,0 +1,186 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA Basic Level Public APIs + * + * Contains basic Level Initialization routines. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Interface + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Options.h" +#include "Filecode.h" +#include "heapManager.h" +#include "CreateStruct.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_COMMON_AMDLATERUNAPTASK_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern CONST DISPATCH_TABLE ApDispatchTable[]; + +/*---------------------------------------------------------------------------------------*/ +/** + * Application Processor perform a function as directed by the BSC. + * + * This is needed for an AP task that must run after AGESA has relinquished control + * of the APs to the IBV. + * + * @param[in] AmdApExeParams The interface struct for any required routine. + * + * @return The most severe AGESA_STATUS returned by any called service. Note + * that this will be the return value passed back to the BSC as the + * return value for the call out. + * + */ +AGESA_STATUS +AmdLateRunApTask ( + IN AP_EXE_PARAMS *AmdApExeParams + ) +{ + AGESA_STATUS CalledAgesaStatus; + AGESA_STATUS ApLateTaskStatus; + DISPATCH_TABLE *Entry; + + AGESA_TESTPOINT (TpIfAmdLateRunApTaskEntry, &AmdApExeParams->StdHeader); + + ASSERT (AmdApExeParams != NULL); + ApLateTaskStatus = AGESA_SUCCESS; + CalledAgesaStatus = AGESA_UNSUPPORTED; + + // Dispatch, if valid + Entry = (DISPATCH_TABLE *) ApDispatchTable; + while (Entry->FunctionId != 0) { + if (AmdApExeParams->FunctionNumber == Entry->FunctionId) { + CalledAgesaStatus = Entry->EntryPoint (AmdApExeParams); + break; + } + Entry++; + } + + if (CalledAgesaStatus > ApLateTaskStatus) { + ApLateTaskStatus = CalledAgesaStatus; + } + + AGESA_TESTPOINT (TpIfAmdLateRunApTaskExit, &AmdApExeParams->StdHeader); + return ApLateTaskStatus; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Constructor for the AMD_LATE_RUN_AP_TASK function. + * + * This routine is responsible for setting default values for the + * input parameters needed by the AMD_S3_SAVE entry point. + * + * @param[in] StdHeader The standard header. + * @param[in,out] AmdApExeParams Required input parameters for the AMD_LATE_RUN_AP_TASK + * entry point. + * + * @retval AGESA_SUCCESS Always Succeeds. + * + */ +AGESA_STATUS +AmdLateRunApTaskInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT AP_EXE_PARAMS *AmdApExeParams + ) +{ + ASSERT (StdHeader != NULL); + ASSERT (AmdApExeParams != NULL); + + AmdApExeParams->StdHeader = *StdHeader; + AmdApExeParams->FunctionNumber = 0; + AmdApExeParams->RelatedDataBlock = NULL; + AmdApExeParams->RelatedBlockLength = 0; + return AGESA_SUCCESS; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3LateRestore.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3LateRestore.c new file mode 100644 index 0000000..6b2dfd8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3LateRestore.c @@ -0,0 +1,244 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA Basic Level Public APIs + * + * Contains basic Level Initialization routines. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Interface + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "S3.h" +#include "cpuFeatures.h" +#include "S3SaveState.h" +#include "CommonInits.h" +#include "Filecode.h" +#include "heapManager.h" +#include "CreateStruct.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_COMMON_AMDS3LATERESTORE_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +AmdS3LateRestorePlatformConfigInit ( + IN OUT PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern BUILD_OPT_CFG UserOptions; + +/*---------------------------------------------------------------------------------------*/ +/** + * Main entry point for the AMD_S3LATE_RESTORE function. + * + * This entry point is responsible for restoring saved registers and preparing the + * silicon components for OS restart. + * + * @param[in,out] S3LateParams Required input parameters for the AMD_S3LATE_RESTORE + * entry point. + * + * @return Aggregated status across all internal AMD S3 late restore calls invoked. + * + */ +AGESA_STATUS +AmdS3LateRestore ( + IN OUT AMD_S3LATE_PARAMS *S3LateParams + ) +{ + UINT8 *BufferPointer; + VOID *OrMaskPtr; + VOID *LateContextPtr; + AGESA_STATUS ReturnStatus; + AGESA_STATUS CalledStatus; + + AGESA_TESTPOINT (TpIfAmdS3LateRestoreEntry, &S3LateParams->StdHeader); + + ReturnStatus = AGESA_SUCCESS; + + ASSERT (S3LateParams != NULL); + + BufferPointer = (UINT8 *) S3LateParams->S3DataBlock.VolatileStorage; + S3LateParams->StdHeader.HeapBasePtr = (UINT32) &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset]; + ASSERT (S3LateParams->StdHeader.HeapBasePtr != 0); + + IDS_HDT_CONSOLE_INIT (&S3LateParams->StdHeader); + IDS_HDT_CONSOLE (MAIN_FLOW, "AmdS3LateRestore: Start\n\n"); + + IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, &S3LateParams->PlatformConfig, &S3LateParams->StdHeader); + IDS_OPTION_HOOK (IDS_BEFORE_S3_RESTORE, S3LateParams, &(S3LateParams->StdHeader)); + + if (((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->RegisterDataSize != 0) { + LateContextPtr = &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->RegisterDataOffset]; + // Restore registers before exiting self refresh + RestorePreESRContext (&OrMaskPtr, + LateContextPtr, + S3_LATE_RESTORE, + &S3LateParams->StdHeader); + // Restore registers after exiting self refresh + RestorePostESRContext (OrMaskPtr, + LateContextPtr, + S3_LATE_RESTORE, + &S3LateParams->StdHeader); + } + + // Dispatch any features needing to run at this time point + IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features at S3 late restore end\n"); + CalledStatus = DispatchCpuFeatures (CPU_FEAT_S3_LATE_RESTORE_END, + &S3LateParams->PlatformConfig, + &S3LateParams->StdHeader); + if (CalledStatus > ReturnStatus) { + ReturnStatus = CalledStatus; + } + + CalledStatus = S3ScriptRestore (&S3LateParams->StdHeader); + if (CalledStatus > ReturnStatus) { + ReturnStatus = CalledStatus; + } + + IDS_OPTION_HOOK (IDS_AFTER_S3_RESTORE, S3LateParams, &S3LateParams->StdHeader); + AGESA_TESTPOINT (TpIfAmdS3LateRestoreExit, &S3LateParams->StdHeader); + IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdS3LateRestore: End\n\n"); + IDS_HDT_CONSOLE_S3_EXIT (&S3LateParams->StdHeader); + return ReturnStatus; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Constructor for the AMD_S3LATE_RESTORE function. + * + * This routine is responsible for setting default values for the + * input parameters needed by the AMD_S3LATE_RESTORE entry point. + * + * @param[in] StdHeader AMD standard header config param. + * @param[in,out] S3LateParams Required input parameters for the + * AMD_S3LATE_RESTORE entry point. + * + * @retval AGESA_SUCCESS Always Succeeds. + * + */ +AGESA_STATUS +AmdS3LateRestoreInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT AMD_S3LATE_PARAMS *S3LateParams + ) +{ + ASSERT (StdHeader != NULL); + ASSERT (S3LateParams != NULL); + + S3LateParams->StdHeader = *StdHeader; + + AmdS3ParamsInitializer (&S3LateParams->S3DataBlock); + + AmdS3LateRestorePlatformConfigInit (&S3LateParams->PlatformConfig, &S3LateParams->StdHeader); + + return AGESA_SUCCESS; +} + +/*------------------------------------------------------------------------------------*/ +/** + * Initialize AmdS3LateRestore stage platform profile and user option input. + * + * @param[in,out] PlatformConfig Platform profile/build option config structure + * @param[in,out] StdHeader AMD standard header config param + * + * @retval AGESA_SUCCESS Always Succeeds. + * + */ +AGESA_STATUS +AmdS3LateRestorePlatformConfigInit ( + IN OUT PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + CommonPlatformConfigInit (PlatformConfig, StdHeader); + + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3Save.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3Save.c new file mode 100644 index 0000000..78f9d47 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3Save.c @@ -0,0 +1,444 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA Basic Level Public APIs + * + * Contains basic Level Initialization routines. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Interface + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "S3.h" +#include "mfs3.h" +#include "CommonInits.h" +#include "AmdFch.h" +#include "GnbInterface.h" +#include "Filecode.h" +#include "heapManager.h" +#include "CreateStruct.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_COMMON_AMDS3SAVE_FILECODE + +extern BLDOPT_FCH_FUNCTION BldoptFchFunction; + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +CONST UINT32 ROMDATA S3LateHeapTable[] = +{ + EVENT_LOG_BUFFER_HANDLE, + SOCKET_DIE_MAP_HANDLE, + NODE_ID_MAP_HANDLE, + LOCAL_AP_MAIL_BOX_CACHE_HANDLE, + IDS_CONTROL_HANDLE, + AMD_S3_SCRIPT_SAVE_TABLE_HANDLE, + AMD_PCIE_COMPLEX_DATA_HANDLE +}; + +#define S3LATE_TABLE_SIZE (sizeof (S3LateHeapTable) / sizeof (UINT32)) //(sizeof (S3LateHeapTable) / sizeof (S3LATE_HEAP_ELEMENT)) + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +AmdS3SavePlatformConfigInit ( + IN OUT PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern BUILD_OPT_CFG UserOptions; + +/*---------------------------------------------------------------------------------------*/ +/** + * Main entry point for the AMD_S3_SAVE function. + * + * This entry point is responsible for saving silicon component registers to the + * SMM save area in preparation of entering system suspend-to-RAM mode. + * + * @param[in,out] AmdS3SaveParams Required input parameters for the AMD_S3_SAVE + * entry point. + * + * @return Aggregated status across all internal AMD S3 save calls invoked. + * + */ +AGESA_STATUS +AmdS3Save ( + IN OUT AMD_S3SAVE_PARAMS *AmdS3SaveParams + ) +{ + UINTN i; + UINT32 EarlyBufferSize; + UINT32 LateBufferSize; + UINT32 LateContextSize; + UINT32 HeapSize; + UINT8 *BufferPointer; + UINT8 HeapStatus; + ALLOCATE_HEAP_PARAMS HeapParams; + LOCATE_HEAP_PTR LocateHeap; + BUFFER_NODE *FreeSpaceNode; + ALLOCATE_HEAP_PARAMS AllocParams; + DEVICE_BLOCK_HEADER *MemoryRelatedDeviceList; + DEVICE_BLOCK_HEADER *NonMemoryRelatedDeviceList; + AGESA_STATUS ReturnStatus; + AGESA_STATUS AgesaStatus; + VOID *HeapPtrs[S3LATE_TABLE_SIZE]; + UINT32 HeapSizes[S3LATE_TABLE_SIZE]; + UINT32 HeapBuffersPresent; + HEAP_MANAGER *HeapPtr; + VOID *MemDataPointer; + + AGESA_TESTPOINT (TpIfAmdS3SaveEntry, &AmdS3SaveParams->StdHeader); + + ASSERT (AmdS3SaveParams != NULL); + + HeapBuffersPresent = 0; + EarlyBufferSize = 0; + LateBufferSize = 0; + LateContextSize = 0; + HeapSize = 0; + NonMemoryRelatedDeviceList = NULL; + MemoryRelatedDeviceList = NULL; + ReturnStatus = AGESA_SUCCESS; + MemDataPointer = NULL; + + IDS_SKIP_HOOK (IDS_BEFORE_S3_SAVE, AmdS3SaveParams, &(AmdS3SaveParams->StdHeader)) { + AgesaStatus = GnbInitAtS3Save (AmdS3SaveParams); + if (AgesaStatus > ReturnStatus) { + ReturnStatus = AgesaStatus; + } + + LocateHeap.BufferHandle = AMD_MEM_S3_SAVE_HANDLE; + if (HeapLocateBuffer (&LocateHeap, &AmdS3SaveParams->StdHeader) == AGESA_SUCCESS) { + // Memory data has been saved and stored in the heap. + // Just copy data from heap. + // First 4 bytes in the heap store the size of the saved memory data. + EarlyBufferSize = *(UINT32 *) LocateHeap.BufferPtr; + MemDataPointer = LocateHeap.BufferPtr + 4; + } else { + // Get memory device list + MemFS3GetDeviceList (&MemoryRelatedDeviceList, &AmdS3SaveParams->StdHeader); + if (MemoryRelatedDeviceList != NULL) { + // Determine size needed + EarlyBufferSize = GetWorstCaseContextSize (MemoryRelatedDeviceList, INIT_RESUME, &AmdS3SaveParams->StdHeader); + } + } + + if (UserOptions.CfgS3LateRestore) { + for (i = 0; i < S3LATE_TABLE_SIZE; i++) { + LocateHeap.BufferHandle = S3LateHeapTable[i]; + if (HeapLocateBuffer (&LocateHeap, &AmdS3SaveParams->StdHeader) == AGESA_SUCCESS) { + HeapBuffersPresent++; + HeapSize += LocateHeap.BufferSize; + HeapPtrs[i] = LocateHeap.BufferPtr; + HeapSizes[i] = LocateHeap.BufferSize; + } else { + HeapPtrs[i] = NULL; + HeapSizes[i] = 0; + } + } + + // Determine heap data size requirements + if (HeapBuffersPresent != 0) { + HeapSize += ((sizeof (HEAP_MANAGER)) + (HeapBuffersPresent * ((sizeof (BUFFER_NODE)) + (NUM_OF_SENTINEL * SIZE_OF_SENTINEL) + 0xF))); // reserve 0xF per buffer node for 16 byte alignment + } + + // Get non memory device list + GetNonMemoryRelatedDeviceList (&NonMemoryRelatedDeviceList, &AmdS3SaveParams->StdHeader); + + if (NonMemoryRelatedDeviceList != NULL) { + // Determine size needed + LateContextSize = GetWorstCaseContextSize (NonMemoryRelatedDeviceList, S3_LATE_RESTORE, &AmdS3SaveParams->StdHeader); + } + LateBufferSize = HeapSize + LateContextSize; + if (LateBufferSize != 0) { + LateBufferSize += sizeof (S3_VOLATILE_STORAGE_HEADER); + } + } + + if ((EarlyBufferSize != 0) || (LateBufferSize != 0)) { + // + // Allocate a buffer + // + AllocParams.RequestedBufferSize = EarlyBufferSize + LateBufferSize; + AllocParams.BufferHandle = AMD_S3_INFO_BUFFER_HANDLE; + AllocParams.Persist = 0; + AGESA_TESTPOINT (TpIfBeforeAllocateS3SaveBuffer, &AmdS3SaveParams->StdHeader); + if (HeapAllocateBuffer (&AllocParams, &AmdS3SaveParams->StdHeader) != AGESA_SUCCESS) { + if (AGESA_ERROR > ReturnStatus) { + ReturnStatus = AGESA_ERROR; + } + } + AGESA_TESTPOINT (TpIfAfterAllocateS3SaveBuffer, &AmdS3SaveParams->StdHeader); + + if (EarlyBufferSize != 0) { + AmdS3SaveParams->S3DataBlock.NvStorage = AllocParams.BufferPtr; + if (MemDataPointer != NULL) { + LibAmdMemCopy (AmdS3SaveParams->S3DataBlock.NvStorage, + MemDataPointer, + EarlyBufferSize, + &AmdS3SaveParams->StdHeader); + } else { + SaveDeviceListContext (MemoryRelatedDeviceList, + AmdS3SaveParams->S3DataBlock.NvStorage, + INIT_RESUME, + &EarlyBufferSize, + &AmdS3SaveParams->StdHeader); + } + AmdS3SaveParams->S3DataBlock.NvStorageSize = EarlyBufferSize; + } + + if (LateBufferSize != 0) { + BufferPointer = AllocParams.BufferPtr; + AmdS3SaveParams->S3DataBlock.VolatileStorage = &(BufferPointer[EarlyBufferSize]); + + ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapOffset = 0; + ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapSize = HeapSize; + ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataOffset = 0; + ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataSize = LateContextSize; + + if (HeapSize != 0) { + // Transfer heap contents + ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapOffset = sizeof (S3_VOLATILE_STORAGE_HEADER); + HeapPtr = (HEAP_MANAGER *) &BufferPointer[EarlyBufferSize + sizeof (S3_VOLATILE_STORAGE_HEADER)]; + HeapPtr->UsedSize = sizeof (HEAP_MANAGER); + HeapPtr->Signature = HEAP_SIGNATURE_VALID; + HeapPtr->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET; + HeapPtr->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER); + FreeSpaceNode = (BUFFER_NODE *) ((UINT8 *) HeapPtr + sizeof (HEAP_MANAGER)); + FreeSpaceNode->BufferSize = HeapSize - sizeof (HEAP_MANAGER) - sizeof (BUFFER_NODE); + FreeSpaceNode->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET; + + HeapStatus = AmdS3SaveParams->StdHeader.HeapStatus; + AmdS3SaveParams->StdHeader.HeapStatus = HEAP_S3_RESUME; + AmdS3SaveParams->StdHeader.HeapBasePtr = (UINT64) (UINTN) HeapPtr; + + for (i = 0; i < S3LATE_TABLE_SIZE; i++) { + if (HeapPtrs[i] != NULL) { + HeapParams.RequestedBufferSize = HeapSizes[i]; // S3LateHeapTable[i].BufferLength; + HeapParams.BufferHandle = S3LateHeapTable[i]; + HeapParams.Persist = HEAP_S3_RESUME; + if (HeapAllocateBuffer (&HeapParams, &AmdS3SaveParams->StdHeader) == AGESA_SUCCESS) { + LibAmdMemCopy ((VOID *) HeapParams.BufferPtr, HeapPtrs[i], HeapSizes[i], &AmdS3SaveParams->StdHeader); + } + } + } + + AmdS3SaveParams->StdHeader.HeapStatus = HeapStatus; + } + + + if (LateContextSize != 0) { + + ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataOffset = HeapSize + sizeof (S3_VOLATILE_STORAGE_HEADER); + + SaveDeviceListContext (NonMemoryRelatedDeviceList, + &(BufferPointer[EarlyBufferSize + HeapSize + sizeof (S3_VOLATILE_STORAGE_HEADER)]), + S3_LATE_RESTORE, + &LateContextSize, + &AmdS3SaveParams->StdHeader); + } + + AmdS3SaveParams->S3DataBlock.VolatileStorageSize = HeapSize + LateContextSize + sizeof (S3_VOLATILE_STORAGE_HEADER); + } + } + } + + AgesaStatus = BldoptFchFunction.InitLate (AmdS3SaveParams); + if (AgesaStatus > ReturnStatus) { + ReturnStatus = AgesaStatus; + } + IDS_OPTION_HOOK (IDS_AFTER_S3_SAVE, AmdS3SaveParams, &AmdS3SaveParams->StdHeader); + AGESA_TESTPOINT (TpIfAmdS3SaveExit, &AmdS3SaveParams->StdHeader); + return ReturnStatus; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Constructor for the AMD_S3_SAVE function. + * + * This routine is responsible for setting default values for the + * input parameters needed by the AMD_S3_SAVE entry point. + * + * @param[in] StdHeader The standard header. + * @param[in,out] S3SaveParams Required input parameters for the AMD_S3_SAVE + * entry point. + * + * @retval AGESA_SUCCESS Always Succeeds. + * + */ +AGESA_STATUS +AmdS3SaveInitializer ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT AMD_S3SAVE_PARAMS *S3SaveParams + ) +{ + ASSERT (StdHeader != NULL); + ASSERT (S3SaveParams != NULL); + + S3SaveParams->StdHeader = *StdHeader; + + AmdS3ParamsInitializer (&S3SaveParams->S3DataBlock); + + AmdS3SavePlatformConfigInit (&S3SaveParams->PlatformConfig, &S3SaveParams->StdHeader); + BldoptFchFunction.InitLateConstructor (S3SaveParams); + + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Destructor for the AMD_S3_SAVE function. + * + * This routine is responsible for deallocation of heap space allocated during + * AMD_S3_SAVE entry point. + * + * @param[in] StdHeader The standard header. + * @param[in,out] S3SaveParams Required input parameters for the AMD_INIT_RESUME + * entry point. + * + * @retval AGESA_STATUS + * + */ +AGESA_STATUS +AmdS3SaveDestructor ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT AMD_S3SAVE_PARAMS *S3SaveParams + ) +{ + AGESA_STATUS ReturnStatus; + AGESA_STATUS RetVal; + LOCATE_HEAP_PTR LocateHeap; + + ASSERT (S3SaveParams != NULL); + + ReturnStatus = AGESA_SUCCESS; + + // Deallocate heap space allocated during memory S3 save + LocateHeap.BufferHandle = AMD_MEM_S3_SAVE_HANDLE; + if (HeapLocateBuffer (&LocateHeap, StdHeader) == AGESA_SUCCESS) { + RetVal = HeapDeallocateBuffer (AMD_MEM_S3_SAVE_HANDLE, StdHeader); + } else { + RetVal = MemS3Deallocate (&S3SaveParams->StdHeader); + } + if (RetVal > ReturnStatus) { + ReturnStatus = RetVal; + } + + RetVal = HeapDeallocateBuffer (AMD_S3_NB_INFO_BUFFER_HANDLE, StdHeader); + if (RetVal > ReturnStatus) { + ReturnStatus = RetVal; + } + + RetVal = HeapDeallocateBuffer (AMD_S3_INFO_BUFFER_HANDLE, StdHeader); + if (RetVal > ReturnStatus) { + ReturnStatus = RetVal; + } + + return ReturnStatus; +} + +/*------------------------------------------------------------------------------------*/ +/** + * Initialize AmdS3Save stage platform profile and user option input. + * + * @param[in,out] PlatformConfig Platform profile/build option config structure + * @param[in,out] StdHeader AMD standard header config param + * + * @retval AGESA_SUCCESS Always Succeeds. + * + */ +AGESA_STATUS +AmdS3SavePlatformConfigInit ( + IN OUT PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + CommonPlatformConfigInit (PlatformConfig, StdHeader); + + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonInits.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonInits.c new file mode 100644 index 0000000..10dba85 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonInits.c @@ -0,0 +1,167 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Common initialization routines. + * + * Contains common initialization routines across AGESA entries of phases. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Common + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Filecode.h" +#include "heapManager.h" +#include "CommonInits.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_COMMON_COMMONINITS_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern BUILD_OPT_CFG UserOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*------------------------------------------------------------------------------------*/ + +/** + * Common routine to initialize PLATFORM_CONFIGURATION. + * + * @param[in,out] PlatformConfig Platform profile/build option config structure + * @param[in,out] StdHeader AMD standard header config param + * + * @retval AGESA_SUCCESS Always Succeeds. + * + */ +AGESA_STATUS +CommonPlatformConfigInit ( + IN OUT PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINTN i; + + PlatformConfig->PlatformProfile = UserOptions.CfgPerformanceProfile; + PlatformConfig->PlatformDeemphasisList = UserOptions.CfgPlatformDeemphasisList; + PlatformConfig->CoreLevelingMode = (UINT8) UserOptions.CfgCoreLevelingMode; + PlatformConfig->C1eMode = UserOptions.CfgPlatformC1eMode; + PlatformConfig->C1ePlatformData = UserOptions.CfgPlatformC1eOpData; + PlatformConfig->C1ePlatformData1 = UserOptions.CfgPlatformC1eOpData1; + PlatformConfig->C1ePlatformData2 = UserOptions.CfgPlatformC1eOpData2; + PlatformConfig->C1ePlatformData3 = UserOptions.CfgPlatformC1eOpData3; + PlatformConfig->CStateMode = UserOptions.CfgPlatformCStateMode; + PlatformConfig->CStatePlatformData = UserOptions.CfgPlatformCStateOpData; + PlatformConfig->CStateIoBaseAddress = UserOptions.CfgPlatformCStateIoBaseAddress; + PlatformConfig->CpbMode = UserOptions.CfgPlatformCpbMode; + PlatformConfig->UserOptionDmi = UserOptions.OptionDmi; + PlatformConfig->UserOptionPState = UserOptions.OptionAcpiPstates; + PlatformConfig->UserOptionCrat = UserOptions.OptionCrat; + PlatformConfig->UserOptionCdit = UserOptions.OptionCdit; + PlatformConfig->UserOptionSrat = UserOptions.OptionSrat; + PlatformConfig->UserOptionSlit = UserOptions.OptionSlit; + PlatformConfig->UserOptionWhea = UserOptions.OptionWhea; + PlatformConfig->LowPowerPstateForProcHot = UserOptions.CfgLowPowerPstateForProcHot; + PlatformConfig->PowerCeiling = UserOptions.CfgAmdPstateCapValue; + PlatformConfig->ForcePstateIndependent = UserOptions.CfgAcpiPstateIndependent; + PlatformConfig->PStatesInHpcMode = UserOptions.OptionPStatesInHpcMode; + PlatformConfig->NumberOfIoApics = UserOptions.CfgPlatNumIoApics; + for (i = 0; i < MaxVrmType; i++) { + PlatformConfig->VrmProperties[i] = UserOptions.CfgPlatVrmCfg[i]; + } + PlatformConfig->ProcessorScopeInSb = UserOptions.CfgProcessorScopeInSb; + PlatformConfig->ProcessorScopeName0 = UserOptions.CfgProcessorScopeName0; + PlatformConfig->ProcessorScopeName1 = UserOptions.CfgProcessorScopeName1; + PlatformConfig->GnbHdAudio = UserOptions.CfgGnbHdAudio; + PlatformConfig->AbmSupport = UserOptions.CfgAbmSupport; + PlatformConfig->DynamicRefreshRate = UserOptions.CfgDynamicRefreshRate; + PlatformConfig->LcdBackLightControl = UserOptions.CfgLcdBackLightControl; + if ((StdHeader->HeapStatus == HEAP_LOCAL_CACHE) || + (StdHeader->HeapStatus == HEAP_TEMP_MEM) || + (StdHeader->HeapStatus == HEAP_SYSTEM_MEM)) { + IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, PlatformConfig, StdHeader); + } + return AGESA_SUCCESS; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonInits.h b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonInits.h new file mode 100644 index 0000000..0a237d5 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonInits.h @@ -0,0 +1,92 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Common initialization routines. + * + * Contains common initialization routines across AGESA entries of phases. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Common + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _COMMON_INITS_H_ +#define _COMMON_INITS_H_ + +/** + * Common routine to initialize PLATFORM_CONFIGURATION. + * + * @param[in,out] PlatformConfig Platform profile/build option config structure + * @param[in,out] StdHeader AMD standard header config param + * + * @retval AGESA_SUCCESS Always Succeeds. + * + */ +AGESA_STATUS +CommonPlatformConfigInit ( + IN OUT PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +#endif // _COMMON_INITS_H_ + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonPage.h b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonPage.h new file mode 100644 index 0000000..bcf787f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonPage.h @@ -0,0 +1,143 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Create outline and references for Processor Common Component mainpage documentation. + * + * Design guides, maintenance guides, and general documentation, are + * collected using this file onto the documentation mainpage. + * This file contains doxygen comment blocks, only. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Documentation + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/** + * @page commonmain Processor Common Component Documentation + * + * Additional documentation for the Common component consists of + * + * - Maintenance Guides: + * - @subpage amdconfigparamname "Naming Guidelines for type AMD_CONFIG_PARAMS" + * - Design Guides: + * - add here >>> + * + */ + +/** + * @page amdconfigparamname Naming Guidelines for type AMD_CONFIG_PARAMS + * @par + * These are the guidelines for naming objects of type AMD_CONFIG_PARAMS and AMD_CONFIG_PARAMS * in AGESA code. + * <ul> + * + * <li> + * Formal parameter names of type AMD_CONFIG_PARAMS and AMD_CONFIG_PARAMS * will always be named + * StdHeader. This covers all function prototypes, function definitions, and method typedefs (a + * typedef of a function prototype) in AGESA code. Examples: + * @n @code + * VOID + * LibAmdPciFindNextCap ( + * IN OUT PCI_ADDR *Address, + * IN AMD_CONFIG_PARAMS *StdHeader + * ) + * + * typedef VOID F_DO_TABLE_ENTRY ( + * IN TABLE_ENTRY_DATA *CurrentEntry, + * IN PLATFORM_CONFIGURATION *PlatformConfig, + * IN AMD_CONFIG_PARAMS *StdHeader + * ); + * + * @endcode + * + * <li> + * Structure members of type AMD_CONFIG_PARAMS or AMD_CONFIG_PARAMS * will always be named StdHeader. Examples: + * @n @code + /// Example of struct member naming. + * typedef struct { + * IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard Header + * IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. + * } AMD_CPU_RECOVERY_PARAMS; + * + * @endcode + * + * <li> + * Routines which define local variables of type AMD_CONFIG_PARAMS or AMD_CONFIG_PARAMS * should + * name the local variable as closely as practical to StdHeader, but otherwise freedom is allowed. Example: + * @n @code + * AMD_CONFIG_PARAMS *NewStdHeader; + * [...] + * NewStdHeader = (AMD_CONFIG_PARAMS *)AllocHeapParams.BufferPtr; + * @endcode + * + * <li> + * Arguments to routines with AMD_CONFIG_PARAMS or AMD_CONFIG_PARAMS * formal parameters are not + * checked. Freedom is allowed in order to conform to these guidelines in a practical, readable + * way. This includes typecast arguments. Examples: + * @n @code + * Status = GetEventLog (&LogEvent, (AMD_CONFIG_PARAMS *)Event); + * + * MemS3ExitSelfRefRegDA (NBPtr, &MemPtr->StdHeader); + * @endcode + * + * </ul> + * + */ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonReturns.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonReturns.c new file mode 100644 index 0000000..973cfde --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonReturns.c @@ -0,0 +1,239 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Common Return routines. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Common + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + +#include "AGESA.h" +#include "Ids.h" +#include "Filecode.h" +#include "CommonReturns.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_COMMON_COMMONRETURNS_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +CommonFchInitStub ( + IN VOID *DataPtr + ); + +VOID +FchTaskDummy ( + IN VOID *DataPtr + ); + +/*----------------------------------------------------------------------------------------*/ +/** +* Return TRUE. +* +* @retval TRUE Default case, no special action +*/ +BOOLEAN +CommonReturnTrue ( VOID ) +{ + return TRUE; +} + + +/*----------------------------------------------------------------------------------------*/ +/** +* Return False. +* +* @retval FALSE Default case, no special action +*/ +BOOLEAN +CommonReturnFalse ( VOID ) +{ + return FALSE; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Return (UINT8)zero. + * + * + * @retval zero None, or only case zero. + */ +UINT8 +CommonReturnZero8 ( VOID ) +{ + return 0; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Return (UINT32)zero. + * + * + * @retval zero None, or only case zero. + */ +UINT32 +CommonReturnZero32 ( VOID ) +{ + return 0; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Return (UINT64)zero. + * + * + * @retval zero None, or only case zero. + */ +UINT64 +CommonReturnZero64 ( VOID ) +{ + return 0; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Return NULL + * + * @retval NULL pointer to nothing + */ +VOID * +CommonReturnNULL ( VOID ) +{ + return NULL; +} + +/*----------------------------------------------------------------------------------------*/ +/** +* Return AGESA_SUCCESS. +* +* @retval AGESA_SUCCESS Success. +*/ +AGESA_STATUS +CommonReturnAgesaSuccess ( VOID ) +{ + return AGESA_SUCCESS; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Do Nothing. + * + */ +VOID +CommonVoid ( VOID ) +{ +} + +/*----------------------------------------------------------------------------------------*/ +/** + * ASSERT if this routine is called. + * + */ +VOID +CommonAssert ( VOID ) +{ + ASSERT (FALSE); +} + + +/*----------------------------------------------------------------------------------------*/ +/** +* Return AGESA_SUCCESS. +* +* @retval AGESA_SUCCESS Success. +*/ +AGESA_STATUS +CommonFchInitStub ( + IN VOID *DataPtr + ) +{ + return AGESA_SUCCESS; +} + + +VOID +FchTaskDummy ( + IN VOID *DataPtr + ) +{ +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.c new file mode 100644 index 0000000..005dc2d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.c @@ -0,0 +1,340 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA Input Structure Creation + * + * Contains AGESA input structure creation support. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Common + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "GeneralServices.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_COMMON_CREATESTRUCT_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern CONST FUNCTION_PARAMS_INFO FuncParamsInfo[]; +extern CONST UINTN InitializerCount; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern BUILD_OPT_CFG UserOptions; + +/*---------------------------------------------------------------------------------------*/ +/** + * Allocate and initialize Config headers and Service Interface structures. + * + * This function will be called for each AGESA public APIs. + * This function will do the following: + * -# Locate the AGESA API structure parameters initializer function information. + * -# Find the size of the structure that gets passed to each public APIs as + * the entry parameter. Allocate heap space using the size for PreMemHeap, callout for + * memory allocation for PostMemDram, and just set the config and service interface + * pointers for ByHost. + * -# If the allocation is not ByHost, copy the AmdConfigParams into the newly created AmdConfigParams. + * For ByHost, we're using the caller's existing config params. + * -# Call the initializer function, and pass a reference to the Config params and to + * the Service Interface struct. On return the constructor will have filled the + * remaining structure with default values. + * -# Fill the remaining info in the newly created structure on heap in AMD_CONFIG_PARAMS + * area (i.e. Fill *newStructPtr with the pointer to the newly created structure) + * -# Set the appropriate AGESA function number in the StdHeader member of the input + * parameter structure. + * + * @param[in,out] InterfaceParams Pointer to structure containing the function call + * whose parameter structure is to be created, the + * allocation method, and a pointer to the newly + * created structure. + * + * @retval AGESA_SUCCESS The interface struct is allocated and initialized. + * @retval AGESA_UNSUPPORTED The Service is not supported. + * + */ +AGESA_STATUS +AmdCreateStruct ( + IN OUT AMD_INTERFACE_PARAMS *InterfaceParams + ) +{ + UINTN ServiceIndex; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + AMD_CONFIG_PARAMS *NewlyCreatedConfig; + VOID *NewlyCreatedServiceInterface; + AGESA_STATUS AgesaStatus; + AGESA_STATUS TempStatus; + AGESA_STATUS IgnoredSts; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + AgesaStatus = AGESA_SUCCESS; + + ASSERT (InterfaceParams != NULL); + + switch (InterfaceParams->AgesaFunctionName) { + case AMD_INIT_RESET: + if (!IsBsp (&InterfaceParams->StdHeader, &IgnoredSts)) { + // APs must transfer their system core number from the mailbox to + // a local register while it is still valid. + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &InterfaceParams->StdHeader); + FamilySpecificServices->TransferApCoreNumber (FamilySpecificServices, &InterfaceParams->StdHeader); + } + InterfaceParams->StdHeader.HeapStatus = HEAP_DO_NOT_EXIST_YET; + break; + case AMD_INIT_EARLY: + case AMD_INIT_RECOVERY: + case AMD_INIT_RESUME: + case AMD_INIT_POST: + InterfaceParams->StdHeader.HeapStatus = HEAP_LOCAL_CACHE; + break; + case AMD_INIT_ENV: + InterfaceParams->StdHeader.HeapStatus = HEAP_TEMP_MEM; + break; + case AMD_INIT_LATE: + case AMD_INIT_MID: + case AMD_S3_SAVE: + case AMD_LATE_RUN_AP_TASK: + InterfaceParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + break; + case AMD_S3LATE_RESTORE: + InterfaceParams->StdHeader.HeapStatus = HEAP_S3_RESUME; + break; + default: + ASSERT (FALSE); + InterfaceParams->StdHeader.HeapStatus = HEAP_LOCAL_CACHE; + break; + } + + InterfaceParams->StdHeader.HeapBasePtr = HeapGetBaseAddress (&InterfaceParams->StdHeader); + + if (InterfaceParams->AgesaFunctionName == AMD_INIT_RESET) { + AgesaStatus = HeapManagerInit (&InterfaceParams->StdHeader); + } + + // Step 1 + for (ServiceIndex = 0; ServiceIndex < InitializerCount; ServiceIndex++) { + if (FuncParamsInfo[ServiceIndex].AgesaFunctionName == InterfaceParams->AgesaFunctionName) { + break; + } + } + if (ServiceIndex >= InitializerCount) { + // A call was made to AGESA with an invalid function number. This wrapper error may be due to the build target + // not containing the desired entry point. + return AGESA_UNSUPPORTED; + } + + // Step 2 + LibAmdMemFill (&AllocHeapParams, 0, (UINTN) (sizeof (ALLOCATE_HEAP_PARAMS)), &InterfaceParams->StdHeader); + + if (InterfaceParams->AllocationMethod < ByHost) { + // Allocate one buffer to contain the config params and the service struct. + // The service struct begins immediately after the config params. + AllocHeapParams.RequestedBufferSize = FuncParamsInfo[ServiceIndex].CreateStructSize + sizeof (AMD_CONFIG_PARAMS); + AllocHeapParams.BufferHandle = FuncParamsInfo[ServiceIndex].BufferHandle; + AllocHeapParams.Persist = HEAP_SYSTEM_MEM; + TempStatus = HeapAllocateBuffer (&AllocHeapParams, &(InterfaceParams->StdHeader)); + AgesaStatus = ((AgesaStatus > TempStatus) ? AgesaStatus : TempStatus); + NewlyCreatedConfig = (AMD_CONFIG_PARAMS *)AllocHeapParams.BufferPtr; + NewlyCreatedConfig++; + NewlyCreatedServiceInterface = NewlyCreatedConfig; + NewlyCreatedConfig = (AMD_CONFIG_PARAMS *)AllocHeapParams.BufferPtr; + } else { + // The caller (example, agesa basic interface implementation) already has a buffer to use. + NewlyCreatedConfig = (AMD_CONFIG_PARAMS *)InterfaceParams; + NewlyCreatedServiceInterface = InterfaceParams->NewStructPtr; + ASSERT (InterfaceParams->NewStructSize >= FuncParamsInfo[ServiceIndex].CreateStructSize); + } + ASSERT (NewlyCreatedConfig != NULL); + ASSERT (NewlyCreatedServiceInterface != NULL); + + // Step 3 + if (InterfaceParams->AllocationMethod != ByHost) { + *NewlyCreatedConfig = InterfaceParams->StdHeader; + } + + // Step 4 + TempStatus = FuncParamsInfo[ServiceIndex].AgesaFunction (NewlyCreatedConfig, NewlyCreatedServiceInterface); + AgesaStatus = ((AgesaStatus > TempStatus) ? AgesaStatus : TempStatus); + + // Step 5 + if (InterfaceParams->AllocationMethod != ByHost) { + InterfaceParams->NewStructPtr = (VOID *) NewlyCreatedServiceInterface; + InterfaceParams->NewStructSize = FuncParamsInfo[ServiceIndex].CreateStructSize; + } + + // Step 6 + ((AMD_CONFIG_PARAMS *) InterfaceParams->NewStructPtr)->Func = InterfaceParams->AgesaFunctionName; + return AgesaStatus; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Clears storage space from allocation for a parameter block of an + * AGESA software call entry. + * + * @param[in,out] InterfaceParams Pointer to structure containing the function call + * whose parameter structure is to be deallocated. + * + * @retval AGESA_STATUS + * + *--------------------------------------------------------------------------------------- + **/ +AGESA_STATUS +AmdReleaseStruct ( + IN OUT AMD_INTERFACE_PARAMS *InterfaceParams + ) +{ + UINT8 i; + UINT8 *BufferPtr; + VOID *ServicePtr; + AGESA_STATUS AgesaStatus; + AGESA_STATUS TempStatus; + LOCATE_HEAP_PTR LocHeap; + + AgesaStatus = AGESA_SUCCESS; + + switch (InterfaceParams->AgesaFunctionName) { + case AMD_INIT_RESET: + case AMD_INIT_EARLY: + case AMD_INIT_RECOVERY: + case AMD_INIT_RESUME: + InterfaceParams->StdHeader.HeapStatus = HEAP_LOCAL_CACHE; + break; + case AMD_INIT_POST: + InterfaceParams->StdHeader.HeapStatus = HEAP_TEMP_MEM; + break; + case AMD_INIT_ENV: + case AMD_INIT_LATE: + case AMD_INIT_MID: + case AMD_S3_SAVE: + case AMD_LATE_RUN_AP_TASK: + InterfaceParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + break; + case AMD_S3LATE_RESTORE: + InterfaceParams->StdHeader.HeapStatus = HEAP_S3_RESUME; + break; + default: + ASSERT (FALSE); + InterfaceParams->StdHeader.HeapStatus = HEAP_LOCAL_CACHE; + break; + } + + InterfaceParams->StdHeader.HeapBasePtr = HeapGetBaseAddress (&InterfaceParams->StdHeader); + +// Step 1 + for (i = 0; i < InitializerCount; i++) { + if (FuncParamsInfo[i].AgesaFunctionName == InterfaceParams->AgesaFunctionName) { + break; + } + } + if (i >= InitializerCount) { + return AGESA_BOUNDS_CHK; + } + + // Step 2 + if (InterfaceParams->AllocationMethod < ByHost) { + LocHeap.BufferHandle = FuncParamsInfo[i].BufferHandle; + if (HeapLocateBuffer (&LocHeap, &(InterfaceParams->StdHeader)) == AGESA_SUCCESS) { + BufferPtr = (UINT8 *) LocHeap.BufferPtr; + ServicePtr = &BufferPtr[sizeof (AMD_CONFIG_PARAMS)]; + TempStatus = FuncParamsInfo[i].AgesaDestructor (&(InterfaceParams->StdHeader), ServicePtr); + AgesaStatus = ((AgesaStatus > TempStatus) ? AgesaStatus : TempStatus); + } + } + + // Step 3 + if (InterfaceParams->AllocationMethod < ByHost) { + TempStatus = HeapDeallocateBuffer (FuncParamsInfo[i].BufferHandle, &(InterfaceParams->StdHeader)); + AgesaStatus = ((AgesaStatus > TempStatus) ? AgesaStatus : TempStatus); + } else { + // Unless we define service specific destructors, nothing to do for ByHost. + return AGESA_SUCCESS; + } + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h new file mode 100644 index 0000000..ca1947d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h @@ -0,0 +1,222 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD AGESA Input Structure Creation + * + * Contains AGESA input creation structures. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Common + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CREATE_STRUCT_H_ +#define _CREATE_STRUCT_H_ + +/** + * A constructor method. + * + * Sets inputs to valid, basic level, defaults for the specific service instance. + * Constructors should avoid using the header, since these routines should not + * do operations which may fail or require status back to the user. The constructor + * should always SUCCEED. + * + * @param[in] StdHeader Opaque handle to standard config header + * @param[in] ServiceInterface Service Interface structure to initialize. + * + * @retval AGESA_SUCCESS Constructors are not allowed to fail +*/ +typedef AGESA_STATUS +F_AGESA_FUNCTION ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN VOID *ServiceInterface + ); + +/// Reference to a Method. +typedef F_AGESA_FUNCTION *PF_AGESA_FUNCTION; + +/** + * A Destructor method. + * + * Sets inputs to valid, basic level, defaults for the specific service instance. + * The constructor should always SUCCEED. + * + * @param[in] StdHeader Opaque handle to standard config header. + * @param[in] ServiceInterface Service Interface structure to initialize. + * + * @retval AGESA_SUCCESS Constructors are not allowed to fail +*/ +typedef AGESA_STATUS +F_AGESA_DESTRUCTOR ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN VOID *ServiceInterface + ); + +/// Reference to a Method. +typedef F_AGESA_DESTRUCTOR *PF_AGESA_DESTRUCTOR; + +/** + * Provide the information needed to invoke each service constructor. + */ +typedef struct { + IN AGESA_STRUCT_NAME AgesaFunctionName; ///< Identifies the service + IN UINT16 CreateStructSize; ///< The service's input struct size. + /// Do NOT include a config params header! + OUT PF_AGESA_FUNCTION AgesaFunction; ///< The constructor function + OUT PF_AGESA_DESTRUCTOR AgesaDestructor; ///< The destructor function. + IN AGESA_BUFFER_HANDLE BufferHandle; ///< The buffer handle id for the service. +} FUNCTION_PARAMS_INFO; + +/** + * All available services have their constructor info here. + */ +AGESA_STATUS +AmdInitResetConstructor ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_RESET_PARAMS *AmdResetParams + ); + +AGESA_STATUS +AmdInitRecoveryInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT AMD_RECOVERY_PARAMS *AmdRecoveryParamsPtr + ); + +AGESA_STATUS +AmdInitEarlyInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT AMD_EARLY_PARAMS *EarlyParams + ); + +AGESA_STATUS +AmdInitPostInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT AMD_POST_PARAMS *PostParamsPtr + ); + +AGESA_STATUS +AmdInitPostDestructor ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_POST_PARAMS *PostParamsPtr + ); + +AGESA_STATUS +AmdInitEnvInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT AMD_ENV_PARAMS *EnvParamsPtr + ); + +AGESA_STATUS +AmdInitMidInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT AMD_MID_PARAMS *MidParamsPtr + ); + +AGESA_STATUS +AmdInitLateInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT AMD_LATE_PARAMS *LateParamsPtr + ); + +AGESA_STATUS +AmdInitLateDestructor ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_LATE_PARAMS *LateParamsPtr + ); + +AGESA_STATUS +AmdInitResumeInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT AMD_RESUME_PARAMS *ResumeParams + ); + +AGESA_STATUS +AmdInitResumeDestructor ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT AMD_RESUME_PARAMS *ResumeParams + ); + +AGESA_STATUS +AmdS3SaveInitializer ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT AMD_S3SAVE_PARAMS *S3SaveParams + ); + +AGESA_STATUS +AmdS3SaveDestructor ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT AMD_S3SAVE_PARAMS *S3SaveParams + ); + +AGESA_STATUS +AmdS3LateRestoreInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT AMD_S3LATE_PARAMS *S3LateParams + ); + +AGESA_STATUS +AmdLateRunApTaskInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT AP_EXE_PARAMS *AmdApExeParams + ); +#endif // _CREATE_STRUCT_H_ + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c new file mode 100644 index 0000000..f57d730 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c @@ -0,0 +1,468 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * S3 save/restore script + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "Porting.h" +#include "AMD.h" +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "S3SaveState.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_COMMON_S3RESTORESTATE_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +extern S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration; +extern S3_DISPATCH_FUNCTION_ENTRY S3DispatchFunctionTable[]; +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +AGESA_STATUS +STATIC +S3RestoreStateFromTable ( + IN S3_SAVE_TABLE_HEADER *S3SaveTablePtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize S3 Script framework + * + * + * + * @param[in] StdHeader Pointer to standard header + */ +AGESA_STATUS +S3ScriptRestore ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return OptionS3ScriptConfiguration.Restore (StdHeader); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize S3 Script framework + * + * + * + * @param[in] StdHeader Pointer to standard header + */ +AGESA_STATUS +S3ScriptRestoreStateStub ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return AGESA_SUCCESS; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize S3 Script framework + * + * + * + * @param[in] StdHeader Pointer to standard header + */ +AGESA_STATUS +S3ScriptRestoreState ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + S3_SAVE_TABLE_HEADER *S3SaveTablePtr; + Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr); + if (Status != AGESA_SUCCESS) { + IDS_ERROR_TRAP; + return AGESA_FATAL; + } + S3SaveTablePtr->Locked = TRUE; + Status = S3RestoreStateFromTable (S3SaveTablePtr, StdHeader); + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize S3 Script framework + * + * + * + * @param[in] S3SaveTablePtr Pointer to S3 Save Table + * @param[in] StdHeader Pointer to standard header + */ +AGESA_STATUS +STATIC +S3RestoreStateFromTable ( + IN S3_SAVE_TABLE_HEADER *S3SaveTablePtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + VOID *S3SaveTableRecordPtr; + PCI_ADDR PciAddress; + UINTN Index; + S3SaveTableRecordPtr = (UINT8 *) S3SaveTablePtr + sizeof (S3_SAVE_TABLE_HEADER); + IDS_HDT_CONSOLE (S3_TRACE, "Start S3 restore\n", ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address); + while ((UINT8 *) S3SaveTableRecordPtr < ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset)) { + switch (*(UINT16 *) S3SaveTableRecordPtr) { + case SAVE_STATE_IO_WRITE_OPCODE: + S3_SCRIPT_DEBUG_CODE ( + IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address); + S3SaveDebugPrintHexArray (StdHeader, (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER), 1, ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width); + IDS_HDT_CONSOLE (S3_TRACE, "\n"); + ); + LibAmdIoWrite ( + ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width, + (UINT16) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address, + (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER), + StdHeader + ); + S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + + sizeof (S3_WRITE_OP_HEADER) + + LibAmdAccessWidth (((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width); + break; + case SAVE_STATE_IO_READ_WRITE_OPCODE: + S3_SCRIPT_DEBUG_CODE ( + IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Address); + S3SaveDebugPrintHexArray ( + StdHeader, + (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER), + 1, + ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width + ); + IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); + S3SaveDebugPrintHexArray ( + StdHeader, + (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width), + 1, + ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width + ); + IDS_HDT_CONSOLE (S3_TRACE, "\n"); + ); + LibAmdIoRMW ( + ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width, + (UINT16) ((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Address, + (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER), + (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width), + StdHeader + ); + S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + + sizeof (S3_READ_WRITE_OP_HEADER) + + 2 * LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width); + break; + case SAVE_STATE_MEM_WRITE_OPCODE: + S3_SCRIPT_DEBUG_CODE ( + IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address); + S3SaveDebugPrintHexArray (StdHeader, (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER), 1, ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width); + IDS_HDT_CONSOLE (S3_TRACE, "\n"); + ); + LibAmdMemWrite ( + ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width, + ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address, + (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER), + StdHeader + ); + S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + + sizeof (S3_WRITE_OP_HEADER) + + LibAmdAccessWidth (((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width); + break; + case SAVE_STATE_MEM_READ_WRITE_OPCODE: + S3_SCRIPT_DEBUG_CODE ( + IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Address); + S3SaveDebugPrintHexArray ( + StdHeader, + (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER), + 1, + ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width + ); + IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); + S3SaveDebugPrintHexArray ( + StdHeader, + (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width), + 1, + ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width + ); + IDS_HDT_CONSOLE (S3_TRACE, "\n"); + ); + LibAmdMemRMW ( + ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width, + ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address, + (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER), + (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Width), + StdHeader + ); + S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + + sizeof (S3_READ_WRITE_OP_HEADER) + + 2 * LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width); + break; + case SAVE_STATE_PCI_CONFIG_WRITE_OPCODE: + PciAddress.AddressValue = (UINT32) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address; + S3_SCRIPT_DEBUG_CODE ( + IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address); + S3SaveDebugPrintHexArray (StdHeader, (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER), 1, ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width); + IDS_HDT_CONSOLE (S3_TRACE, "\n"); + ); + LibAmdPciWrite ( + ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width, + PciAddress, + (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER), + StdHeader + ); + S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + + sizeof (S3_WRITE_OP_HEADER) + + LibAmdAccessWidth (((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width); + break; + case SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE: + PciAddress.AddressValue = (UINT32) ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address; + S3_SCRIPT_DEBUG_CODE ( + IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Address); + S3SaveDebugPrintHexArray ( + StdHeader, + (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER), + 1, + ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width + ); + IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); + S3SaveDebugPrintHexArray ( + StdHeader, + (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width), + 1, + ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width + ); + IDS_HDT_CONSOLE (S3_TRACE, "\n"); + ); + LibAmdPciRMW ( + ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width, + PciAddress, + (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER), + (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width), + StdHeader + ); + S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + + sizeof (S3_READ_WRITE_OP_HEADER) + + 2 * LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width); + break; + case SAVE_STATE_STALL_OPCODE: + break; + case SAVE_STATE_INFORMATION_OPCODE: + IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: Info: [%s]\n", (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_INFO_OP_HEADER)); + S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + + sizeof (S3_INFO_OP_HEADER) + + ((S3_INFO_OP_HEADER*) S3SaveTableRecordPtr)->Length; + break; + case SAVE_STATE_DISPATCH_OPCODE: + S3_SCRIPT_DEBUG_CODE ( + IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Function Id: 0x%02x, Context: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), ((S3_DISPATCH_OP_HEADER*) S3SaveTableRecordPtr)->FunctionId); + S3SaveDebugPrintHexArray ( + StdHeader, + (VOID*)((UINT8*) S3SaveTableRecordPtr + sizeof (S3_DISPATCH_OP_HEADER)), + ((S3_DISPATCH_OP_HEADER*) S3SaveTableRecordPtr)->Length, + AccessWidth8); + IDS_HDT_CONSOLE (S3_TRACE, "\n"); + ); + Index = 0; + while (S3DispatchFunctionTable[Index].FunctionId != 0) { + if (S3DispatchFunctionTable[Index].FunctionId == ((S3_DISPATCH_OP_HEADER*) S3SaveTableRecordPtr)->FunctionId) { + (S3DispatchFunctionTable[Index].Function) ( + StdHeader, + ((S3_DISPATCH_OP_HEADER*) S3SaveTableRecordPtr)->Length, + (VOID*)((UINT8*) S3SaveTableRecordPtr + sizeof (S3_DISPATCH_OP_HEADER)) + ); + break; + } + Index++; + } + ASSERT (S3DispatchFunctionTable[Index].FunctionId != 0); + S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + + sizeof (S3_DISPATCH_OP_HEADER) + + ((S3_DISPATCH_OP_HEADER*) S3SaveTableRecordPtr)->Length; + break; + + case SAVE_STATE_IO_POLL_OPCODE: + S3_SCRIPT_DEBUG_CODE ( + IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%04x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Address); + S3SaveDebugPrintHexArray ( + StdHeader, + (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER), + 1, + ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width + ); + IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); + S3SaveDebugPrintHexArray ( + StdHeader, + (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width), + 1, + ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width + ); + ) + LibAmdIoPoll ( + ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width, + (UINT16) ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Address, + (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER), + (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Width), + ((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Delay, + StdHeader + ); + S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + + sizeof (S3_POLL_OP_HEADER) + + 2 * LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width); + break; + case SAVE_STATE_MEM_POLL_OPCODE: + S3_SCRIPT_DEBUG_CODE ( + IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT32) ((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Address); + S3SaveDebugPrintHexArray ( + StdHeader, + (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER), + 1, + ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width + ); + IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); + S3SaveDebugPrintHexArray ( + StdHeader, + (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width), + 1, + ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width + ); + ) + LibAmdMemPoll ( + ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width, + ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Address, + (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER), + (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width), + ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Delay, + StdHeader + ); + S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + + sizeof (S3_POLL_OP_HEADER) + + 2 * LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width); + break; + case SAVE_STATE_PCI_CONFIG_POLL_OPCODE: + PciAddress.AddressValue = (UINT32) ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Address; + S3_SCRIPT_DEBUG_CODE ( + IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT32) ((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Address); + S3SaveDebugPrintHexArray ( + StdHeader, + (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER), + 1, + ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width + ); + IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); + S3SaveDebugPrintHexArray ( + StdHeader, + (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width), + 1, + ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width + ); + ) + LibAmdPciPoll ( + ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width, + PciAddress, + (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER), + (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width), + ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Delay, + StdHeader + ); + S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr + + sizeof (S3_POLL_OP_HEADER) + + 2 * LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width); + break; + default: + IDS_HDT_CONSOLE (S3_TRACE, " ERROR!!! Invalid S3 restore opcode\n"); + ASSERT (FALSE); + return AGESA_ERROR; + } + } + IDS_HDT_CONSOLE (S3_TRACE, " End S3 Restore \n"); + return AGESA_SUCCESS; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c new file mode 100644 index 0000000..e147875 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c @@ -0,0 +1,678 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * S3 save/restore script + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "Porting.h" +#include "AMD.h" +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "S3SaveState.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_COMMON_S3SAVESTATE_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +extern S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +S3SaveStateExtendTableLenth ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT S3_SAVE_TABLE_HEADER **S3SaveTable + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize S3 Script framework + * + * + * + * @param[in] StdHeader Pointer to standard header + */ +AGESA_STATUS +S3ScriptInit ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return OptionS3ScriptConfiguration.Init (StdHeader); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize S3 Script framework + * + * + * + * @param[in] StdHeader Pointer to standard header + */ +AGESA_STATUS +S3ScriptInitStateStub ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize S3 Script framework + * + * + * + * @param[in] StdHeader Pointer to standard header + */ +AGESA_STATUS +S3ScriptInitState ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + AllocHeapParams.RequestedBufferSize = S3_TABLE_LENGTH; + AllocHeapParams.BufferHandle = AMD_S3_SCRIPT_SAVE_TABLE_HANDLE; + AllocHeapParams.Persist = HEAP_SYSTEM_MEM; + Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader); + if (Status == AGESA_SUCCESS) { + ((S3_SAVE_TABLE_HEADER *) AllocHeapParams.BufferPtr)->TableLength = S3_TABLE_LENGTH; + ((S3_SAVE_TABLE_HEADER *) AllocHeapParams.BufferPtr)->SaveOffset = sizeof (S3_SAVE_TABLE_HEADER); + ((S3_SAVE_TABLE_HEADER *) AllocHeapParams.BufferPtr)->Locked = FALSE; + } + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize S3 Script framework + * + * + * + * @param[in] StdHeader Pointer to standard header + * @param[in,out] S3SaveTable S3 save table header + */ +AGESA_STATUS +S3SaveStateExtendTableLenth ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT S3_SAVE_TABLE_HEADER **S3SaveTable + ) +{ + AGESA_STATUS Status; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + VOID *TempBuffer; + UINT16 NewTableLength; + UINT16 CurrentTableLength; + //Allocate temporary buffer + NewTableLength = (*S3SaveTable)->TableLength + S3_TABLE_LENGTH_INCREMENT; + AllocHeapParams.RequestedBufferSize = NewTableLength; + AllocHeapParams.BufferHandle = AMD_S3_SCRIPT_TEMP_BUFFER_HANDLE; + AllocHeapParams.Persist = StdHeader->HeapStatus; + Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader); + if (Status != AGESA_SUCCESS) { + return Status; + } + //Save current table length + CurrentTableLength = (*S3SaveTable)->TableLength; + //Update table length + (*S3SaveTable)->TableLength = NewTableLength; + //Copy S3 save toable to temporary location + LibAmdMemCopy (AllocHeapParams.BufferPtr, *S3SaveTable, CurrentTableLength, StdHeader); + //Save pointer to temp buffer + TempBuffer = AllocHeapParams.BufferPtr; + // Free original S3 save buffer + HeapDeallocateBuffer (AMD_S3_SCRIPT_SAVE_TABLE_HANDLE, StdHeader); + + AllocHeapParams.RequestedBufferSize = NewTableLength; + AllocHeapParams.BufferHandle = AMD_S3_SCRIPT_SAVE_TABLE_HANDLE; + AllocHeapParams.Persist = StdHeader->HeapStatus; + Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader); + if (Status != AGESA_SUCCESS) { + return Status; + } + LibAmdMemCopy (AllocHeapParams.BufferPtr, TempBuffer, AllocHeapParams.RequestedBufferSize, StdHeader); + *S3SaveTable = (S3_SAVE_TABLE_HEADER*) AllocHeapParams.BufferPtr; + HeapDeallocateBuffer (AMD_S3_SCRIPT_TEMP_BUFFER_HANDLE, StdHeader); + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize S3 Script framework + * + * + * + * @param[in] StdHeader Pointer to standard header + * @param[out] S3SaveTable S3 save table header + */ +AGESA_STATUS +S3ScriptGetS3SaveTable ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT S3_SAVE_TABLE_HEADER **S3SaveTable + ) +{ + AGESA_STATUS Status; + LOCATE_HEAP_PTR LocHeapParams; + LocHeapParams.BufferHandle = AMD_S3_SCRIPT_SAVE_TABLE_HANDLE; + Status = HeapLocateBuffer (&LocHeapParams, StdHeader); + if (Status != AGESA_SUCCESS) { + *S3SaveTable = NULL; + return Status; + } + *S3SaveTable = (S3_SAVE_TABLE_HEADER *) LocHeapParams.BufferPtr; + return AGESA_SUCCESS; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Save S3 write opcode + * + * + * + * @param[in] StdHeader Pointer to standard header + * @param[in] OpCode Operation opcode + * @param[in] Width Width + * @param[in] Address Register address + * @param[in] Count Number of register writes + * @param[in] Buffer Pointer to write buffer + */ +AGESA_STATUS +S3SaveStateSaveWriteOp ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 OpCode, + IN ACCESS_WIDTH Width, + IN UINT64 Address, + IN UINT32 Count, + IN VOID *Buffer + ) +{ + S3_SAVE_TABLE_HEADER *S3SaveTablePtr; + S3_WRITE_OP_HEADER *SaveOffsetPtr; + UINT32 OpCodeLength; + UINT32 WidthLength; + AGESA_STATUS Status; + + Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr); + if (Status != AGESA_SUCCESS) { + return Status; + } + if (S3SaveTablePtr->Locked) { + return AGESA_UNSUPPORTED; + } + WidthLength = LibAmdAccessWidth (Width); + OpCodeLength = sizeof (S3_WRITE_OP_HEADER) + WidthLength * Count; + if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) { + Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr); + if (Status != AGESA_SUCCESS) { + return Status; + } + } + S3_SCRIPT_DEBUG_CODE ( + IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); + S3SaveDebugPrintHexArray (StdHeader, Buffer, Count, Width); + IDS_HDT_CONSOLE (S3_TRACE, "\n"); + ); + SaveOffsetPtr = (S3_WRITE_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset); + SaveOffsetPtr->OpCode = OpCode; + SaveOffsetPtr->Width = Width; + SaveOffsetPtr->Count = Count; + SaveOffsetPtr->Address = Address; + LibAmdMemCopy ( + (UINT8 *) SaveOffsetPtr + sizeof (S3_WRITE_OP_HEADER), + Buffer, + WidthLength * Count, + StdHeader + ); + S3SaveTablePtr->SaveOffset += OpCodeLength; + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Save S3 write opcode + * + * + * + * @param[in] StdHeader Pointer to standard header + * @param[in] OpCode Operation opcode + * @param[in] Width Width + * @param[in] Address Register address + * @param[in] Data Pointer to data + * @param[in] DataMask Pointer data mask + */ +AGESA_STATUS +S3SaveStateSaveReadWriteOp ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 OpCode, + IN ACCESS_WIDTH Width, + IN UINT64 Address, + IN VOID *Data, + IN VOID *DataMask + ) +{ + + S3_SAVE_TABLE_HEADER *S3SaveTablePtr; + S3_READ_WRITE_OP_HEADER *SaveOffsetPtr; + UINT32 OpCodeLength; + UINT32 WidthLength; + AGESA_STATUS Status; + + Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr); + if (Status != AGESA_SUCCESS) { + return Status; + } + if (S3SaveTablePtr->Locked) { + return AGESA_UNSUPPORTED; + } + WidthLength = LibAmdAccessWidth (Width); + OpCodeLength = sizeof (S3_READ_WRITE_OP_HEADER) + WidthLength * 2; + if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) { + Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr); + if (Status != AGESA_SUCCESS) { + return Status; + } + } + S3_SCRIPT_DEBUG_CODE ( + IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); + S3SaveDebugPrintHexArray (StdHeader, Data, 1, Width); + IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); + S3SaveDebugPrintHexArray (StdHeader, DataMask, 1, Width); + IDS_HDT_CONSOLE (S3_TRACE, "\n"); + ); + SaveOffsetPtr = (S3_READ_WRITE_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset); + SaveOffsetPtr->OpCode = OpCode; + SaveOffsetPtr->Width = Width; + SaveOffsetPtr->Address = Address; + + LibAmdMemCopy ( + (UINT8 *) SaveOffsetPtr + sizeof (S3_READ_WRITE_OP_HEADER), + Data, + WidthLength, + StdHeader + ); + LibAmdMemCopy ( + (UINT8 *) SaveOffsetPtr + sizeof (S3_READ_WRITE_OP_HEADER) + WidthLength, + DataMask, + WidthLength, + StdHeader + ); + S3SaveTablePtr->SaveOffset += OpCodeLength; + return AGESA_SUCCESS; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Save S3 poll opcode + * + * + * + * @param[in] StdHeader Pointer to standard header + * @param[in] OpCode Operation opcode + * @param[in] Width Width + * @param[in] Address Register address + * @param[in] Data Pointer to data + * @param[in] DataMask Pointer data mask + * @param[in] Delay Time delay for poll + */ +AGESA_STATUS +S3SaveStateSavePollOp ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 OpCode, + IN ACCESS_WIDTH Width, + IN UINT64 Address, + IN VOID *Data, + IN VOID *DataMask, + IN UINT64 Delay + ) +{ + + S3_SAVE_TABLE_HEADER *S3SaveTablePtr; + S3_POLL_OP_HEADER *SaveOffsetPtr; + UINT32 OpCodeLength; + UINT32 WidthLength; + AGESA_STATUS Status; + + Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr); + if (Status != AGESA_SUCCESS) { + return Status; + } + if (S3SaveTablePtr->Locked) { + return AGESA_UNSUPPORTED; + } + WidthLength = LibAmdAccessWidth (Width); + OpCodeLength = sizeof (S3_POLL_OP_HEADER) + WidthLength * 2; + if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) { + Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr); + if (Status != AGESA_SUCCESS) { + return Status; + } + } + S3_SCRIPT_DEBUG_CODE ( + IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address); + S3SaveDebugPrintHexArray (StdHeader, Data, 1, Width); + IDS_HDT_CONSOLE (S3_TRACE, " Mask: "); + S3SaveDebugPrintHexArray (StdHeader, DataMask, 1, Width); + IDS_HDT_CONSOLE (S3_TRACE, "\n"); + ); + SaveOffsetPtr = (S3_POLL_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset); + SaveOffsetPtr->OpCode = OpCode; + SaveOffsetPtr->Width = Width; + SaveOffsetPtr->Delay = Delay; + SaveOffsetPtr->Address = Address; + + LibAmdMemCopy ( + (UINT8 *) SaveOffsetPtr + sizeof (S3_POLL_OP_HEADER), + Data, + WidthLength, + StdHeader + ); + LibAmdMemCopy ( + (UINT8 *) SaveOffsetPtr + sizeof (S3_POLL_OP_HEADER) + WidthLength, + DataMask, + WidthLength, + StdHeader + ); + S3SaveTablePtr->SaveOffset += OpCodeLength; + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Save S3 info opcode + * + * + * + * @param[in] StdHeader Pointer to standard header + * @param[in] OpCode Operation opcode + * @param[in] InformationLength Info length + * @param[in] Information Pointer to information + */ +AGESA_STATUS +S3SaveStateSaveInfoOp ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 OpCode, + IN UINT32 InformationLength, + IN VOID *Information + ) +{ + + S3_SAVE_TABLE_HEADER *S3SaveTablePtr; + S3_INFO_OP_HEADER *SaveOffsetPtr; + UINT32 OpCodeLength; + + AGESA_STATUS Status; + + Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr); + if (Status != AGESA_SUCCESS) { + return Status; + } + if (S3SaveTablePtr->Locked) { + return AGESA_UNSUPPORTED; + } + OpCodeLength = sizeof (S3_INFO_OP_HEADER) + InformationLength; + if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) { + Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr); + if (Status != AGESA_SUCCESS) { + return Status; + } + } + SaveOffsetPtr = (S3_INFO_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset); + SaveOffsetPtr->OpCode = OpCode; + SaveOffsetPtr->Length = InformationLength; + S3_SCRIPT_DEBUG_CODE ( + IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: Info: %s \n", Information); + ); + LibAmdMemCopy ( + (UINT8 *) SaveOffsetPtr + sizeof (S3_INFO_OP_HEADER), + Information, + InformationLength, + StdHeader + ); + S3SaveTablePtr->SaveOffset += OpCodeLength; + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Save S3 dispatch opcode + * + * + * + * @param[in] StdHeader Pointer to standard header + * @param[in] OpCode Operation opcode + * @param[in] FunctionId Function ID + * @param[in] ContextLength Context length + * @param[in] Context Pointer to Context + */ +AGESA_STATUS +S3SaveStateSaveDispatchOp ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 OpCode, + IN UINT16 FunctionId, + IN UINT16 ContextLength, + IN VOID *Context + ) +{ + + S3_SAVE_TABLE_HEADER *S3SaveTablePtr; + S3_DISPATCH_OP_HEADER *SaveOffsetPtr; + UINT32 OpCodeLength; + AGESA_STATUS Status; + + Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr); + if (Status != AGESA_SUCCESS) { + return Status; + } + if (S3SaveTablePtr->Locked) { + return AGESA_UNSUPPORTED; + } + OpCodeLength = sizeof (S3_DISPATCH_OP_HEADER) + ContextLength; + if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) { + Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr); + if (Status != AGESA_SUCCESS) { + return Status; + } + } + S3_SCRIPT_DEBUG_CODE ( + IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Function Id: 0x%02x, Context: ", S3SaveDebugOpcodeString (StdHeader, OpCode), FunctionId); + S3SaveDebugPrintHexArray (StdHeader, Context, ContextLength, AccessWidth8); + IDS_HDT_CONSOLE (S3_TRACE, "\n"); + ); + SaveOffsetPtr = (S3_DISPATCH_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset); + SaveOffsetPtr->OpCode = OpCode; + SaveOffsetPtr->Length = ContextLength; + SaveOffsetPtr->FunctionId = FunctionId; + LibAmdMemCopy ( + (UINT8 *) SaveOffsetPtr + sizeof (S3_DISPATCH_OP_HEADER), + Context, + ContextLength, + StdHeader + ); + + S3SaveTablePtr->SaveOffset += OpCodeLength; + return AGESA_SUCCESS; +} + + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Save S3 debug support + * + * + * + * @param[in] StdHeader Pointer to standard header + * @param[in] Op Opcode + */ +CHAR8* +S3SaveDebugOpcodeString ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 Op + ) +{ + switch (Op) { + case SAVE_STATE_IO_WRITE_OPCODE: + return (CHAR8 *)"IO WR"; + case SAVE_STATE_IO_READ_WRITE_OPCODE: + return (CHAR8 *)"IO RD/WR"; + case SAVE_STATE_IO_POLL_OPCODE: + return (CHAR8 *)"IO POLL"; + case SAVE_STATE_MEM_WRITE_OPCODE: + return (CHAR8 *)"MEM WR"; + case SAVE_STATE_MEM_READ_WRITE_OPCODE: + return (CHAR8 *)"MEM RD/WR"; + case SAVE_STATE_MEM_POLL_OPCODE: + return (CHAR8 *)"MEM POLL"; + case SAVE_STATE_PCI_CONFIG_WRITE_OPCODE: + return (CHAR8 *)"PCI WR"; + case SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE: + return (CHAR8 *)"PCI RD/WR"; + case SAVE_STATE_PCI_CONFIG_POLL_OPCODE: + return (CHAR8 *)"PCI POLL"; + case SAVE_STATE_STALL_OPCODE: + return (CHAR8 *)"STALL"; + case SAVE_STATE_DISPATCH_OPCODE: + return (CHAR8 *)"DISPATCH"; + default: + IDS_ERROR_TRAP; + } + return (CHAR8 *)"!!! Unrecognize opcode !!!"; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Save S3 debug support + * + * + * + * @param[in] StdHeader Pointer to standard header + * @param[in] Array Array + * @param[in] Count Count of element in array + * @param[in] Width Array Element width + */ +VOID +S3SaveDebugPrintHexArray ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN VOID *Array, + IN UINT32 Count, + IN ACCESS_WIDTH Width + ) +{ + UINTN Index; + + for (Index = 0; Index < Count; Index++) { + switch (Width) { + case AccessWidth8: + case AccessS3SaveWidth8: + IDS_HDT_CONSOLE (S3_TRACE, "0x%02x", *((UINT8*)Array + Index)); + break; + case AccessWidth16: + case AccessS3SaveWidth16: + IDS_HDT_CONSOLE (S3_TRACE, "0x%04x", *((UINT16*)Array + Index)); + break; + case AccessWidth32: + case AccessS3SaveWidth32: + IDS_HDT_CONSOLE (S3_TRACE, "0x%08x", *((UINT32*)Array + Index)); + break; + case AccessWidth64: + case AccessS3SaveWidth64: + //IDS_HDT_CONSOLE (S3_TRACE, "0x%08x%08x", ((UINT32*) ((UINT64*)Array + Index)[1], ((UINT32*) ((UINT64*)Array + Index))[0])); + break; + default: + IDS_ERROR_TRAP; + } + if (Index < (Count - 1)) { + IDS_HDT_CONSOLE (S3_TRACE, ", "); + } + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.h b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.h new file mode 100644 index 0000000..7eb76dd --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.h @@ -0,0 +1,389 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Various PCI service routines. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _S3SAVESTATE_H_ +#define _S3SAVESTATE_H_ + +#pragma pack (push, 1) + +#ifndef S3_SCRIPT_DEBUG_CODE + #define S3_SCRIPT_DEBUG_CODE(Code) Code +#endif + +/// Dispatch function ID repository +typedef enum { + NbSmuIndirectWriteS3Script_ID = 1, ///< GNB SMU service request function ID. + NbSmuServiceRequestS3Script_ID, ///< GNB PCIe late restore function ID. + PcieLateRestoreS3Script_ID, ///< GNB SMU indirect write. + GnbSmuServiceRequestV4S3Script_ID, ///< SMU service request + GnbLibStallS3Script_ID, ///< Stall request + PcieLateRestoreTNS3Script_ID, ///< GNB PCIe late restore TN + PcieLateRestoreKMS3Script_ID, ///< GNB PCIe late restore KM + PcieLateRestoreTHS3Script_ID, ///< GNB PCIe late restore KM + GfxRequestSclkTNS3Script_ID ///< SCLk setting +} S3_DISPATCH_FUNCTION_ID; + +#define SAVE_STATE_IO_WRITE_OPCODE 0x00 +#define SAVE_STATE_IO_READ_WRITE_OPCODE 0x01 +#define SAVE_STATE_MEM_WRITE_OPCODE 0x02 +#define SAVE_STATE_MEM_READ_WRITE_OPCODE 0x03 +#define SAVE_STATE_PCI_CONFIG_WRITE_OPCODE 0x04 +#define SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE 0x05 +#define SAVE_STATE_STALL_OPCODE 0x07 +#define SAVE_STATE_INFORMATION_OPCODE 0x0A +#define SAVE_STATE_IO_POLL_OPCODE 0x0D +#define SAVE_STATE_MEM_POLL_OPCODE 0x0E +#define SAVE_STATE_PCI_CONFIG_POLL_OPCODE 0x0F +#define SAVE_STATE_DISPATCH_OPCODE 0x20 +#define SAVE_STATE_BREAKPOINT_OPCODE 0x21 + + +#define S3_TABLE_LENGTH 8 * 1024 +#define S3_TABLE_LENGTH_INCREMENT 1 * 1024 + +/// S3 Save Table +typedef struct { + UINT16 TableLength; ///< Table Length + UINT32 SaveOffset; ///< Save Location + BOOLEAN Locked; ///< Locked +} S3_SAVE_TABLE_HEADER; + +/// S3 write operation header +typedef struct { + UINT16 OpCode; ///< Opcode + ACCESS_WIDTH Width; ///< Data width (byte, word, dword) + UINT64 Address; ///< Register address + UINT32 Count; ///< Write count +} S3_WRITE_OP_HEADER; + +/// S3 Read and Write Operation header +typedef struct { + UINT16 OpCode; ///< Opcode + ACCESS_WIDTH Width; ///< Data width (byte, word, dword) + UINT64 Address; ///< Register Address +} S3_READ_WRITE_OP_HEADER; + +/// S3 Poll operation header +typedef struct { + UINT16 OpCode; ///< Opcode + ACCESS_WIDTH Width; ///< Data width (byte, word, dword) + UINT64 Address; ///< Register address + UINT64 Delay; ///< Time delay +} S3_POLL_OP_HEADER; + +/// Information operation header +typedef struct { + UINT16 OpCode; ///< Opcode + UINT32 Length; ///< Length of info +} S3_INFO_OP_HEADER; + +/// Dispatch operation header +typedef struct { + UINT16 OpCode; ///< Opcode + UINT16 FunctionId; ///< Function ID + UINT16 Length; ///< Length in bytes of the context +} S3_DISPATCH_OP_HEADER; + + +typedef VOID S3_DISPATCH_FUNCTION ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID *Context + ); + +/// Dispatch function table entry +typedef struct { + UINT16 FunctionId; ///<Function ID + S3_DISPATCH_FUNCTION *Function; ///<Function pointer +} S3_DISPATCH_FUNCTION_ENTRY; + +typedef AGESA_STATUS (*S3_SCRIPT_INIT) ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef AGESA_STATUS (*S3_SCRIPT_RESTORE) ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// S3 Script Configuration +typedef struct { + S3_SCRIPT_INIT Init; ///< Script initialization + S3_SCRIPT_RESTORE Restore; ///< Script restore +} S3_SCRIPT_CONFIGURATION; + +AGESA_STATUS +S3ScriptInit ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +S3ScriptInitState ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +S3ScriptInitStateStub ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +S3ScriptRestore ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +S3ScriptRestoreState ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +S3ScriptRestoreStateStub ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +S3ScriptGetS3SaveTable ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT S3_SAVE_TABLE_HEADER **S3SaveTable + ); + +VOID +S3SaveDebugPrintHexArray ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN VOID *Array, + IN UINT32 Count, + IN ACCESS_WIDTH Width + ); + +CHAR8* +S3SaveDebugOpcodeString ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 Op + ); + +AGESA_STATUS +S3SaveStateSaveWriteOp ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 OpCode, + IN ACCESS_WIDTH Width, + IN UINT64 Address, + IN UINT32 Count, + IN VOID *Buffer + ); + +AGESA_STATUS +S3SaveStateSaveReadWriteOp ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 OpCode, + IN ACCESS_WIDTH Width, + IN UINT64 Address, + IN VOID *Data, + IN VOID *DataMask + ); + +AGESA_STATUS +S3SaveStateSavePollOp ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 OpCode, + IN ACCESS_WIDTH Width, + IN UINT64 Address, + IN VOID *Data, + IN VOID *DataMask, + IN UINT64 Delay + ); + +AGESA_STATUS +S3SaveStateSaveInfoOp ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 OpCode, + IN UINT32 InformationLength, + IN VOID *Information + ); + +AGESA_STATUS +S3SaveStateSaveDispatchOp ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 OpCode, + IN UINT16 FunctionId, + IN UINT16 ContextLength, + IN VOID *Context + ); + +//PCI write +#define S3_SAVE_PCI_WRITE(StdHeader, Address, Width, DataPtr) \ + S3SaveStateSaveWriteOp ( \ + StdHeader, \ + SAVE_STATE_PCI_CONFIG_WRITE_OPCODE, \ + Width, \ + Address.AddressValue, \ + 1, \ + DataPtr \ + ) + +//PCI read modify write +#define S3_SAVE_PCI_RMW (StdHeader, Address, Width, DataPtr, DataMaskPtr) \ + S3SaveStateSaveWriteOp ( \ + StdHeader, \ + SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE, \ + Width, \ + Address.AddressValue, \ + DataPtr, \ + DataMask \ + ) + +//PCI read modify write +#define S3_SAVE_PCI_POLL(StdHeader, Address, Width, DataPtr, DataMaskPtr, Delay) \ + S3SaveStateSavePollOp ( \ + StdHeader, \ + SAVE_STATE_PCI_CONFIG_POLL_OPCODE, \ + Width, \ + Address.AddressValue, \ + DataPtr, \ + DataMask, \ + Delay \ + ) + +//Memory/MMIO write +#define S3_SAVE_MEM_WRITE(StdHeader, Address, Width, DataPtr) \ + S3SaveStateSaveWriteOp ( \ + StdHeader, \ + SAVE_STATE_MEM_WRITE_OPCODE, \ + Width, \ + Address, \ + 1, \ + DataPtr \ + ) + +//Memory/MMIO read modify write +#define S3_SAVE_MEM_RMW(StdHeader, Address, Width, DataPtr, DataMaskPtr) \ + S3SaveStateSaveWriteOp ( \ + StdHeader, \ + SAVE_STATE_MEM_READ_WRITE_OPCODE, \ + Width, \ + Address, \ + DataPtr, \ + DataMask \ + ) + +//Memory/MMIO read modify write +#define S3_SAVE_MEM_POLL(StdHeader, Address, Width, DataPtr, DataMaskPtr, Delay) \ + S3SaveStateSavePollOp ( \ + StdHeader, \ + SAVE_STATE_MEM_POLL_OPCODE, \ + Width, \ + Address, \ + DataPtr, \ + DataMask, \ + Delay \ + ) + +// I/O write +#define S3_SAVE_IO_WRITE(StdHeader, Address, Width, DataPtr) \ + S3SaveStateSaveWriteOp ( \ + StdHeader, \ + SAVE_STATE_IO_WRITE_OPCODE, \ + Width, \ + Address, \ + 1, \ + DataPtr \ + ) + +// Save information +#define S3_SAVE_INFORMATION(StdHeader, InformationLength, Information) \ + S3SaveStateSaveInfoOp ( \ + StdHeader, \ + SAVE_STATE_INFORMATION_OPCODE, \ + InformationLength, \ + Information \ + ) + +// Save information string S3_SAVE_INFORMATION_STRING (StdHeader, "Message") +#define S3_SAVE_INFORMATION_STRING(StdHeader, Information) \ + S3SaveStateSaveInfoOp ( \ + StdHeader, \ + SAVE_STATE_INFORMATION_OPCODE, \ + sizeof (Information), \ + Information \ + ) + +// Save dispatch function +#define S3_SAVE_DISPATCH(StdHeader, FunctionId, ContextLength, Context) \ + S3SaveStateSaveDispatchOp ( \ + StdHeader, \ + SAVE_STATE_DISPATCH_OPCODE, \ + FunctionId, \ + ContextLength, \ + Context \ + ) + +#pragma pack (pop) +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaEnv.c new file mode 100644 index 0000000..cf5bfc6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaEnv.c @@ -0,0 +1,108 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH HD Audio Controller + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE (0xB002) +// +// Declaration of local functions +// + +/** + * + * emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +Fchdef178 ( + IN VOID *FchDataPtr + ) +{ + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + if ( LocalCfgPtr->Azalia.AzaliaEnable == hdaconf1 ) { + RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xEB , AccessWidth8, (UINT32)~BIT0, 0); + } else { + RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xEB , AccessWidth8, (UINT32)~BIT0, BIT0); + RwPci ((((0x14<<3)+2) << 16) + FCH_AZ_REG4C, AccessWidth8, (UINT32)~BIT0, BIT0, StdHeader); + + if ( LocalCfgPtr->Azalia.AzaliaMsiEnable) { + RwPci ((((0x14<<3)+2) << 16) + FCH_AZ_REG44, AccessWidth32, (UINT32)~BIT8, BIT8, StdHeader); + RwPci ((((0x14<<3)+2) << 16) + FCH_AZ_REG60, AccessWidth32, (UINT32)~BIT16, BIT16, StdHeader); + } + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaLate.c new file mode 100644 index 0000000..37acfc6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaLate.c @@ -0,0 +1,86 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH HD Audio Controller + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE (0xB004) + +/** + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +Fchdef180 ( + IN VOID *FchDataPtr + ) +{ +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaMid.c new file mode 100644 index 0000000..65c5e59 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaMid.c @@ -0,0 +1,83 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH HD Audio Controller + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE (0xB003) +// +// Declaration of local functions +// + + + + + + + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaReset.c new file mode 100644 index 0000000..d10857e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Azalia/AzaliaReset.c @@ -0,0 +1,88 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH HD Audio Controller + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE (0xB001) + +/** + * + * + * + * + * @param[in] FchDataPtr + * + */ +VOID +Fchdef174 ( + IN VOID *FchDataPtr + ) +{ +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/AcpiLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/AcpiLib.c new file mode 100644 index 0000000..bd94fae --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/AcpiLib.c @@ -0,0 +1,270 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH ACPI lib + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_COMMON_ACPILIB_FILECODE +// +// +// Routine Description: +// +// Locate ACPI table +// +// Arguments: +// +// Signature - table signature +// +//Returns: +// +// pointer to ACPI table +// +// +VOID* +AcpiLocateTable ( + IN UINT32 Signature + ) +{ + UINT32 Index; + UINT32 *RsdPtr; + UINT32 *Rsdt; + UINTN TableOffset; + DESCRIPTION_HEADER *CurrentTable; + + RsdPtr = (UINT32*) (UINTN) FCHOEM_ACPI_TABLE_RANGE_LOW; + Rsdt = NULL; + do { + if ( *RsdPtr == Int32FromChar('R','S','D',' ') && *(RsdPtr + 1) == Int32FromChar('P','T','R',' ') ) { /* ' DSR' & ' RTP' */ + Rsdt = (UINT32*) (UINTN) ((RSDP_HEADER*)RsdPtr)->RsdtAddress; + break; + } + RsdPtr += 4; + } while ( RsdPtr <= (UINT32*) (UINTN) FCHOEM_ACPI_TABLE_RANGE_HIGH ); + + if ( Rsdt != NULL && AcpiGetTableCheckSum (Rsdt) == 0 ) { + for ( Index = 0; Index < (((DESCRIPTION_HEADER*)Rsdt)->Length - sizeof (DESCRIPTION_HEADER)) / 4; Index++ ) { + TableOffset = *(UINTN*) ((UINT8*)Rsdt + sizeof (DESCRIPTION_HEADER) + Index * 4); + CurrentTable = (DESCRIPTION_HEADER*)TableOffset; + if ( CurrentTable->Signature == Signature ) { + return CurrentTable; + } + } + } + return NULL; +} + +// +// +// Routine Description: +// +// Update table CheckSum +// +// Arguments: +// +// TablePtr - table pointer +// +// Returns: +// +// none +// +// +VOID +AcpiSetTableCheckSum ( + IN VOID *TablePtr + ) +{ + UINT8 CheckSum; + + CheckSum = 0; + ((DESCRIPTION_HEADER*)TablePtr)->CheckSum = 0; + CheckSum = AcpiGetTableCheckSum (TablePtr); + ((DESCRIPTION_HEADER*)TablePtr)->CheckSum = (UINT8) (FCHOEM_ACPI_BYTE_CHECHSUM - CheckSum); +} + +// +// +// Routine Description: +// +// Get table CheckSum - Get ACPI table checksum +// +// Arguments: +// +// TablePtr - table pointer +// +// Returns: +// +// none +// +// +UINT8 +AcpiGetTableCheckSum ( + IN VOID *TablePtr + ) +{ + return GetByteSum (TablePtr, ((DESCRIPTION_HEADER*)TablePtr)->Length); +} + + +// +// +// Routine Description: +// +// GetByteSum - Get BYTE checksum value +// +// Arguments: +// +// DataPtr - table pointer +// Length - table length +// +// Returns: +// +// CheckSum - CheckSum value +// +// +UINT8 +GetByteSum ( + IN VOID *DataPtr, + IN UINT32 Length + ) +{ + UINT32 Index; + UINT8 CheckSum; + + CheckSum = 0; + for ( Index = 0; Index < Length; Index++ ) { + CheckSum = CheckSum + (*((UINT8*)DataPtr + Index)); + } + return CheckSum; +} + +// +// +// Routine Description: +// +// GetFchAcpiMmioBase - Get FCH HwAcpi MMIO Base Address +// +// Arguments: +// +// AcpiMmioBase - HwAcpi MMIO Base Address +// StdHeader - Amd Stand Header +// +// Returns: +// +// AcpiMmioBase - HwAcpi MMIO Base Address +// +// +VOID +GetFchAcpiMmioBase ( + OUT UINT32 *AcpiMmioBase, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 AcpiMmioBaseAddressDword; + + ReadPmio (FCH_PMIOA_REG24 + 2, AccessWidth16, &AcpiMmioBaseAddressDword, StdHeader); + *AcpiMmioBase = AcpiMmioBaseAddressDword << 16; +} + +// +// +// Routine Description: +// +// GetFchAcpiPmBase - Get FCH HwAcpi PM Base Address +// +// Arguments: +// +// AcpiPmBase - HwAcpi PM Base Address +// StdHeader - Amd Stand Header +// +// Returns: +// +// AcpiPmBase - HwAcpi PM Base Address +// +// +VOID +GetFchAcpiPmBase ( + OUT UINT16 *AcpiPmBase, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + ReadPmio (FCH_PMIOA_REG60, AccessWidth16, AcpiPmBase, StdHeader); +} + + +UINT8 +ReadFchSleepType ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT16 Value16; + + ReadPmio (FCH_PMIOA_REG62, AccessWidth16, &Value16, StdHeader); + LibAmdIoRead (AccessWidth16, Value16, &Value16, StdHeader); + return (UINT8) ((Value16 >> 10) & 7); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/AcpiLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/AcpiLib.h new file mode 100644 index 0000000..4446189 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/AcpiLib.h @@ -0,0 +1,114 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH ACPI lib + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +/// +/// RSDP - ACPI 2.0 table RSDP +/// +typedef struct _RSDP_HEADER { + UINT64 Signature; ///< RSDP signature "RSD PTR" + UINT8 CheckSum; ///< checksum of the first 20 bytes + UINT8 OEMID[6]; ///< OEM ID + UINT8 Revision; ///< 0 for APCI 1.0, 2 for ACPI 2.0 + UINT32 RsdtAddress; ///< physical address of RSDT + UINT32 Length; ///< total length of RSDP (including extended part) + UINT64 XsdtAddress; ///< physical address of XSDT + UINT8 ExtendedCheckSum; ///< chechsum of whole table + UINT8 Reserved[3]; ///< Reserved +} RSDP_HEADER; + +/// +/// DESCRIPTION_HEADER - ACPI common table header +/// +typedef struct _DESCRIPTION_HEADER { + UINT32 Signature; ///< ACPI signature (4 ASCII characters) + UINT32 Length; ///< Length of table, in bytes, including header + UINT8 Revision; ///< ACPI Specification minor version # + UINT8 CheckSum; ///< To make sum of entire table == 0 + UINT8 OemId[6]; ///< OEM identification + UINT8 OemTableId[8]; ///< OEM table identification + UINT32 OemRevision; ///< OEM revision number + UINT32 CreatorId; ///< ASL compiler vendor ID + UINT32 CreatorRevision; ///< ASL compiler revision number +} DESCRIPTION_HEADER; + +/// +/// _AcpiRegWrite - ACPI MMIO register R/W structure +/// +typedef struct _ACPI_REG_WRITE { + UINT8 MmioBase; /// MmioBase: Index of Fch block (For instance GPIO_BASE:0x01 SMI_BASE:0x02) + UINT8 MmioReg; /// MmioReg : Register index + UINT8 DataAndMask; /// DataANDMask : AND Register Data + UINT8 DataOrMask; /// DataOrMask : Or Register Data +} ACPI_REG_WRITE; + +VOID* AcpiLocateTable (IN UINT32 Signature); +VOID AcpiSetTableCheckSum (IN VOID *TablePtr); +UINT8 AcpiGetTableCheckSum (IN VOID *TablePtr); +UINT8 GetByteSum (IN VOID *DataPtr, IN UINT32 Length); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchBiosRamUsage.h b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchBiosRamUsage.h new file mode 100644 index 0000000..c614936 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchBiosRamUsage.h @@ -0,0 +1,94 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH BIOS Ram usage + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#ifndef _FCH_BIOS_RAM_USAGE_H_ +#define _FCH_BIOS_RAM_USAGE_H_ + +#define RESTORE_MEMORY_CONTROLLER_START 0 +#define XHCI_REGISTER_BAR00 0xD0 +#define XHCI_REGISTER_BAR01 0xD1 +#define XHCI_REGISTER_BAR02 0xD2 +#define XHCI_REGISTER_BAR03 0xD3 +#define XHCI_REGISTER_04H 0xD4 +#define XHCI_REGISTER_0CH 0xD5 +#define XHCI_REGISTER_3CH 0xD6 +#define XHCI1_REGISTER_BAR00 0xE0 +#define XHCI1_REGISTER_BAR01 0xE1 +#define XHCI1_REGISTER_BAR02 0xE2 +#define XHCI1_REGISTER_BAR03 0xE3 +#define XHCI1_REGISTER_04H 0xE4 +#define XHCI1_REGISTER_0CH 0xE5 +#define XHCI1_REGISTER_3CH 0xE6 +#define RTC_WORKAROUND_DATA_START 0xF0 +#define BOOT_TIME_FLAG_SEC 0xF8 +#define BOOT_TIME_FLAG_INT19 0xFC + +#endif + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommon.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommon.c new file mode 100644 index 0000000..732e713 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommon.c @@ -0,0 +1,74 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH common + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "heapManager.h" +#define FILECODE PROC_FCH_COMMON_FCHCOMMON_FILECODE + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonCfg.h new file mode 100644 index 0000000..34805bb --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonCfg.h @@ -0,0 +1,1187 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH Function Support Definition + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#ifndef _FCH_COMMON_CFG_H_ +#define _FCH_COMMON_CFG_H_ + +#pragma pack (push, 1) + +//----------------------------------------------------------------------------- +// FCH DEFINITIONS AND MACROS +//----------------------------------------------------------------------------- + +// +// FCH Component Data Structure Definitions +// + +/// PCI_ADDRESS - PCI access structure +#define PCI_ADDRESS(bus, dev, func, reg) \ + (UINT32) ( (((UINT32)bus) << 24) + (((UINT32)dev) << 19) + (((UINT32)func) << 16) + ((UINT32)reg) ) + +/// +/// - Byte Register R/W structure +/// +typedef struct _REG8_MASK { + UINT8 RegIndex; /// RegIndex - Reserved + UINT8 AndMask; /// AndMask - Reserved + UINT8 OrMask; /// OrMask - Reserved +} REG8_MASK; + + +/// +/// PCIE Reset Block +/// +typedef enum { + NbBlock, ///< Reset for NB PCIE + FchBlock ///< Reset for FCH GPP +} RESET_BLOCK; + +/// +/// PCIE Reset Operation +/// +typedef enum { + DeassertReset, ///< DeassertRese - Deassert reset + AssertReset ///< AssertReset - Assert reset +} RESET_OP; + + +/// +/// SD structure +/// +typedef struct { + SD_MODE SdConfig; ///< SD Mode configuration + /// @li <b>00</b> - Disabled + /// @li <b>00</b> - AMDA, set 24,18,16, default + /// @li <b>01</b> - DMA clear 24, 16, set 18 + /// @li <b>10</b> - PIO clear 24,18,16 + /// + UINT8 SdSpeed; ///< SD Speed + /// @li <b>0</b> - Low speed clear 17 + /// @li <b>1</b> - High speed, set 17, default + /// + UINT8 SdBitWidth; ///< SD Bit Width + /// @li <b>0</b> - 32BIT clear 23 + /// @li <b>1</b> - 64BIT, set 23,default + /// + UINT32 SdSsid; ///< SD Subsystem ID + SD_CLOCK_CONTROL SdClockControl; ///< SD Clock Control + BOOLEAN SdClcokMultiplier; ///< SD Clock Multiplier enable/disable + UINT8 SdReTuningMode; ///< SD Re-tuning modes select + /// @li <b>0</b> - mode 1 + /// @li <b>1</b> - mode 2 + /// @li <b>2</b> - mode 3 + UINT8 SdHostControllerVersion; ///< SD controller Version + /// @li <b>1</b> - SD 2.0 + /// @li <b>2</b> - SD 3.0 +} FCH_SD; + +/// +/// CODEC_ENTRY - Fch HD Audio OEM Codec structure +/// +typedef struct _CODEC_ENTRY { + UINT8 Nid; /// Nid - Reserved + UINT32 Byte40; /// Byte40 - Reserved +} CODEC_ENTRY; + +/// +/// CODEC_TBL_LIST - Fch HD Audio Codec table list +/// +typedef struct _CODEC_TBL_LIST { + UINT32 CodecId; /// CodecID - Codec ID + CODEC_ENTRY* CodecTablePtr; /// CodecTablePtr - Codec table pointer +} CODEC_TBL_LIST; + +/// +/// AZALIA_PIN - HID Azalia or GPIO define structure. +/// +typedef struct _AZALIA_PIN { + UINT8 AzaliaSdin0; ///< AzaliaSdin0 + /// @par + /// @li <b>00</b> - GPIO PIN + /// @li <b>10</b> - As a Azalia SDIN pin + + UINT8 AzaliaSdin1; ///< AzaliaSdin1 + /// @par + /// SDIN1 is define at BIT2 & BIT3 + /// @li <b>00</b> - GPIO PIN + /// @li <b>10</b> - As a Azalia SDIN pin + + UINT8 AzaliaSdin2; ///< AzaliaSdin2 + /// @par + /// SDIN2 is define at BIT4 & BIT5 + /// @li <b>00</b> - GPIO PIN + /// @li <b>10</b> - As a Azalia SDIN pin + + UINT8 AzaliaSdin3; ///< AzaliaSdin3 + /// @par + /// SDIN3 is define at BIT6 & BIT7 + /// @li <b>00</b> - GPIO PIN + /// @li <b>10</b> - As a Azalia SDIN pin +} AZALIA_PIN; + +/// +/// Azalia structure +/// +typedef struct { + HDA_CONFIG AzaliaEnable; ///< AzaliaEnable - Azalia function configuration + BOOLEAN AzaliaMsiEnable; ///< AzaliaMsiEnable - Azalia MSI capability + UINT32 AzaliaSsid; ///< AzaliaSsid - Azalia Subsystem ID + UINT8 AzaliaPinCfg; ///< AzaliaPinCfg - Azalia Controller SDIN pin Configuration + /// @par + /// @li <b>0</b> - disable + /// @li <b>1</b> - enable + + UINT8 AzaliaFrontPanel; ///< AzaliaFrontPanel - Azalia Controller Front Panel Configuration + /// @par + /// Support Front Panel configuration + /// @li <b>0</b> - Auto + /// @li <b>1</b> - disable + /// @li <b>2</b> - enable + + UINT8 FrontPanelDetected; ///< FrontPanelDetected - Force Azalia Controller Front Panel Configuration + /// @par + /// Force Front Panel configuration + /// @li <b>0</b> - Not Detected + /// @li <b>1</b> - Detected + + UINT8 AzaliaSnoop; ///< AzaliaSnoop - Azalia Controller Snoop feature Configuration + /// @par + /// Azalia Controller Snoop feature Configuration + /// @li <b>0</b> - disable + /// @li <b>1</b> - enable + + UINT8 AzaliaDummy; /// AzaliaDummy - Reserved */ + + AZALIA_PIN AzaliaConfig; /// AzaliaConfig - Azaliz Pin Configuration + +/// +/// AZOEMTBL - Azalia Controller OEM Codec Table Pointer +/// + CODEC_TBL_LIST *AzaliaOemCodecTablePtr; /// AzaliaOemCodecTablePtr - Oem Azalia Codec Table Pointer + +/// +/// AZOEMFPTBL - Azalia Controller Front Panel OEM Table Pointer +/// + VOID *AzaliaOemFpCodecTablePtr; /// AzaliaOemFpCodecTablePtr - Oem Front Panel Codec Table Pointer +} FCH_AZALIA; + +/// +/// SPI structure +/// +typedef struct { + BOOLEAN LpcMsiEnable; ///< LPC MSI capability + UINT32 LpcSsid; ///< LPC Subsystem ID + UINT32 RomBaseAddress; ///< SpiRomBaseAddress + /// @par + /// SPI ROM BASE Address + /// + UINT8 SpiSpeed; ///< SpiSpeed - Spi Frequency + /// @par + /// SPI Speed [1.0] - the clock speed for non-fast read command + /// @li <b>00</b> - 66Mhz + /// @li <b>01</b> - 33Mhz + /// @li <b>10</b> - 22Mhz + /// @li <b>11</b> - 16.5Mhz + /// + UINT8 SpiFastSpeed; ///< FastSpeed - Spi Fast Speed feature + /// @par + /// TBD + /// + UINT8 WriteSpeed; ///< WriteSpeed - Spi Write Speed + /// @par + /// TBD + /// + UINT8 SpiMode; ///< SpiMode - Spi Mode Setting + /// @par + /// @li <b>101</b> - Qual-io 1-4-4 + /// @li <b>100</b> - Dual-io 1-2-2 + /// @li <b>011</b> - Qual-io 1-1-4 + /// @li <b>010</b> - Dual-io 1-1-2 + /// @li <b>111</b> - FastRead + /// @li <b>110</b> - Normal + /// + UINT8 AutoMode; ///< AutoMode - Spi Auto Mode + /// @par + /// SPI Auto Mode + /// @li <b>0</b> - Disabled + /// @li <b>1</b> - Enabled + /// + UINT8 SpiBurstWrite; ///< SpiBurstWrite - Spi Burst Write Mode + /// @par + /// SPI Burst Write + /// @li <b>0</b> - Disabled + /// @li <b>1</b> - Enabled +} FCH_SPI; + + +/// +/// IDE structure +/// +typedef struct { + BOOLEAN IdeEnable; ///< IDE function switch + BOOLEAN IdeMsiEnable; ///< IDE MSI capability + UINT32 IdeSsid; ///< IDE controller Subsystem ID +} FCH_IDE; + +/// +/// IR Structure +/// +typedef struct { + IR_CONFIG IrConfig; ///< IrConfig + UINT8 IrPinControl; ///< IrPinControl +} FCH_IR; + + +/// +/// PCI Bridge Structure +/// +typedef struct { + BOOLEAN PcibMsiEnable; ///< PCI-PCI Bridge MSI capability + UINT32 PcibSsid; ///< PCI-PCI Bridge Subsystem ID + UINT8 PciClks; ///< 33MHz PCICLK0/1/2/3 Enable, bits [0:3] used + /// @li <b>0</b> - disable + /// @li <b>1</b> - enable + /// + UINT16 PcibClkStopOverride; ///< PCIB_CLK_Stop Override + BOOLEAN PcibClockRun; ///< Enable the auto clkrun functionality + /// @li <b>0</b> - disable + /// @li <b>1</b> - enable + /// +} FCH_PCIB; + + +/// +/// - SATA Phy setting structure +/// +typedef struct _SATA_PHY_SETTING { + UINT16 PhyCoreControlWord; /// PhyCoreControlWord - Reserved + UINT32 PhyFineTuneDword; /// PhyFineTuneDword - Reserved +} SATA_PHY_SETTING; + +/// +/// SATA main setting structure +/// +typedef struct _SATA_ST { + UINT8 SataModeReg; ///< SataModeReg - Sata Controller Mode + BOOLEAN SataEnable; ///< SataEnable - Sata Controller Function + /// @par + /// Sata Controller + /// @li <b>0</b> - disable + /// @li <b>1</b> - enable + /// + UINT8 Sata6AhciCap; ///< Sata6AhciCap - Reserved */ + BOOLEAN SataSetMaxGen2; ///< SataSetMaxGen2 - Set Sata Max Gen2 mode + /// @par + /// Sata Controller Set to Max Gen2 mode + /// @li <b>0</b> - disable + /// @li <b>1</b> - enable + /// + BOOLEAN IdeEnable; ///< IdeEnable - Ide Controller Mode + /// @par + /// Sata IDE Controller set to Combined Mode + /// @li <b>0</b> - disable + /// @li <b>1</b> - enable + /// + UINT8 SataClkMode; /// SataClkMode - Reserved +} SATA_ST; + +/// +/// SATA_PORT_ST - SATA PORT structure +/// +typedef struct _SATA_PORT_ST { + UINT8 SataPortReg; ///< SATA Port bit map - bits[0:7] for ports 0 ~ 7 + /// @li <b>0</b> - disable + /// @li <b>1</b> - enable + /// + BOOLEAN Port0; ///< PORT0 - 0:disable, 1:enable + BOOLEAN Port1; ///< PORT1 - 0:disable, 1:enable + BOOLEAN Port2; ///< PORT2 - 0:disable, 1:enable + BOOLEAN Port3; ///< PORT3 - 0:disable, 1:enable + BOOLEAN Port4; ///< PORT4 - 0:disable, 1:enable + BOOLEAN Port5; ///< PORT5 - 0:disable, 1:enable + BOOLEAN Port6; ///< PORT6 - 0:disable, 1:enable + BOOLEAN Port7; ///< PORT7 - 0:disable, 1:enable +} SATA_PORT_ST; + +/// +///< _SATA_PORT_MD - Force Each PORT to GEN1/GEN2 mode +/// +typedef struct _SATA_PORT_MD { + UINT16 SataPortMode; ///< SATA Port GEN1/GEN2 mode bit map - bits [0:15] for ports 0 ~ 7 + UINT8 Port0; ///< PORT0 - set BIT0 to GEN1, BIT1 - PORT0 set to GEN2 + UINT8 Port1; ///< PORT1 - set BIT2 to GEN1, BIT3 - PORT1 set to GEN2 + UINT8 Port2; ///< PORT2 - set BIT4 to GEN1, BIT5 - PORT2 set to GEN2 + UINT8 Port3; ///< PORT3 - set BIT6 to GEN1, BIT7 - PORT3 set to GEN2 + UINT8 Port4; ///< PORT4 - set BIT8 to GEN1, BIT9 - PORT4 set to GEN2 + UINT8 Port5; ///< PORT5 - set BIT10 to GEN1, BIT11 - PORT5 set to GEN2 + UINT8 Port6; ///< PORT6 - set BIT12 to GEN1, BIT13 - PORT6 set to GEN2 + UINT8 Port7; ///< PORT7 - set BIT14 to GEN1, BIT15 - PORT7 set to GEN2 +} SATA_PORT_MD; +/// +/// SATA structure +/// +typedef struct { + BOOLEAN SataMsiEnable; ///< SATA MSI capability + UINT32 SataIdeSsid; ///< SATA IDE mode SSID + UINT32 SataRaidSsid; ///< SATA RAID mode SSID + UINT32 SataRaid5Ssid; ///< SATA RAID 5 mode SSID + UINT32 SataAhciSsid; ///< SATA AHCI mode SSID + + SATA_ST SataMode; /// SataMode - Reserved + SATA_CLASS SataClass; ///< SataClass - SATA Controller mode [2:0] + UINT8 SataIdeMode; ///< SataIdeMode - Sata IDE Controller mode + /// @par + /// @li <b>0</b> - Legacy IDE mode + /// @li <b>1</b> - Native IDE mode + /// + UINT8 SataDisUnusedIdePChannel; ///< SataDisUnusedIdePChannel-Disable Unused IDE Primary Channel + /// @par + /// @li <b>0</b> - Channel Enable + /// @li <b>1</b> - Channel Disable + /// + UINT8 SataDisUnusedIdeSChannel; ///< SataDisUnusedIdeSChannel - Disable Unused IDE Secondary Channel + /// @par + /// @li <b>0</b> - Channel Enable + /// @li <b>1</b> - Channel Disable + /// + UINT8 IdeDisUnusedIdePChannel; ///< IdeDisUnusedIdePChannel-Disable Unused IDE Primary Channel + /// @par + /// @li <b>0</b> - Channel Enable + /// @li <b>1</b> - Channel Disable + /// + UINT8 IdeDisUnusedIdeSChannel; ///< IdeDisUnusedIdeSChannel-Disable Unused IDE Secondary Channel + /// @par + /// @li <b>0</b> - Channel Enable + /// @li <b>1</b> - Channel Disable + /// + UINT8 SataOptionReserved; /// SataOptionReserved - Reserved + + SATA_PORT_ST SataEspPort; ///< SataEspPort - SATA port is external accessible on a signal only connector (eSATA:) + + SATA_PORT_ST SataPortPower; ///< SataPortPower - Port Power configuration + + SATA_PORT_MD SataPortMd; ///< SataPortMd - Port Mode + + UINT8 SataAggrLinkPmCap; /// SataAggrLinkPmCap - 0:OFF 1:ON + UINT8 SataPortMultCap; /// SataPortMultCap - 0:OFF 1:ON + UINT8 SataClkAutoOff; /// SataClkAutoOff - AutoClockOff 0:Disabled, 1:Enabled + UINT8 SataPscCap; /// SataPscCap 1:Enable PSC, 0:Disable PSC capability + UINT8 BiosOsHandOff; /// BiosOsHandOff - Reserved + UINT8 SataFisBasedSwitching; /// SataFisBasedSwitching - Reserved + UINT8 SataCccSupport; /// SataCccSupport - Reserved + UINT8 SataSscCap; /// SataSscCap - 1:Enable, 0:Disable SSC capability + UINT8 SataMsiCapability; /// SataMsiCapability 0:Hidden 1:Visible + UINT8 SataForceRaid; /// SataForceRaid 0:No function 1:Force RAID + UINT8 SataInternal100Spread; /// SataInternal100Spread - Reserved + UINT8 SataDebugDummy; /// SataDebugDummy - Reserved + UINT8 SataTargetSupport8Device; /// SataTargetSupport8Device - Reserved + UINT8 SataDisableGenericMode; /// SataDisableGenericMode - Reserved + BOOLEAN SataAhciEnclosureManagement; /// SataAhciEnclosureManagement - Reserved + UINT8 SataSgpio0; /// SataSgpio0 - Reserved + UINT8 SataSgpio1; /// SataSgpio1 - Reserved + UINT8 SataPhyPllShutDown; /// SataPhyPllShutDown - Reserved + BOOLEAN SataHotRemovalEnh; /// SataHotRemovalEnh - Reserved + + SATA_PORT_ST SataHotRemovalEnhPort; ///< SataHotRemovalEnhPort - Hot Remove + + BOOLEAN SataOobDetectionEnh; /// SataOobDetectionEnh - TRUE + BOOLEAN SataPowerSavingEnh; /// SataPowerSavingEnh - TRUE + UINT8 SataMemoryPowerSaving; /// SataMemoryPowerSaving - 0-3 Default [3] + UINT32 TempMmio; /// TempMmio - Reserved +} FCH_SATA; + + +// +// IMC Message Register Software Interface +// +#define CPU_MISC_BUS_DEV_FUN ((0x18 << 3) + 3) + +#define MSG_SYS_TO_IMC 0x80 +#define Fun_80 0x80 +#define Fun_81 0x81 +#define Fun_82 0x82 +#define Fun_83 0x83 +#define Fun_84 0x84 +#define Fun_85 0x85 +#define Fun_86 0x86 +#define Fun_87 0x87 +#define Fun_88 0x88 +#define Fun_89 0x89 +#define Fun_90 0x90 +#define MSG_IMC_TO_SYS 0x81 +#define MSG_REG0 0x82 +#define MSG_REG1 0x83 +#define MSG_REG2 0x84 +#define MSG_REG3 0x85 +#define MSG_REG4 0x86 +#define MSG_REG5 0x87 +#define MSG_REG6 0x88 +#define MSG_REG7 0x89 +#define MSG_REG8 0x8A +#define MSG_REG9 0x8B +#define MSG_REGA 0x8C +#define MSG_REGB 0x8D +#define MSG_REGC 0x8E +#define MSG_REGD 0x8F + +#define DISABLED 0 +#define ENABLED 1 + + + +/// +/// EC structure +/// +typedef struct _FCH_EC { + UINT8 MsgFun81Zone0MsgReg0; ///<Thermal zone + UINT8 MsgFun81Zone0MsgReg1; ///<Thermal zone + UINT8 MsgFun81Zone0MsgReg2; ///<Thermal zone control byte 1 + UINT8 MsgFun81Zone0MsgReg3; ///<Thermal zone control byte 2 + UINT8 MsgFun81Zone0MsgReg4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius. + UINT8 MsgFun81Zone0MsgReg5; ///<Hysteresis information + UINT8 MsgFun81Zone0MsgReg6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 + UINT8 MsgFun81Zone0MsgReg7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located. + UINT8 MsgFun81Zone0MsgReg8; ///<Fan PWM stepping rate in unit of PWM level percentage + UINT8 MsgFun81Zone0MsgReg9; ///<Fan PWM ramping rate in 5ms unit +// +// EC LDN9 function 81 zone 1 +// + UINT8 MsgFun81Zone1MsgReg0; ///<Thermal zone + UINT8 MsgFun81Zone1MsgReg1; ///<Thermal zone + UINT8 MsgFun81Zone1MsgReg2; ///<Thermal zone control byte 1 + UINT8 MsgFun81Zone1MsgReg3; ///<Thermal zone control byte 2 + UINT8 MsgFun81Zone1MsgReg4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius. + UINT8 MsgFun81Zone1MsgReg5; ///<Hysteresis information + UINT8 MsgFun81Zone1MsgReg6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 + UINT8 MsgFun81Zone1MsgReg7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located. + UINT8 MsgFun81Zone1MsgReg8; ///<Fan PWM stepping rate in unit of PWM level percentage + UINT8 MsgFun81Zone1MsgReg9; ///<Fan PWM ramping rate in 5ms unit +// +//EC LDN9 function 81 zone 2 +// + UINT8 MsgFun81Zone2MsgReg0; ///<Thermal zone + UINT8 MsgFun81Zone2MsgReg1; ///<Thermal zone + UINT8 MsgFun81Zone2MsgReg2; ///<Thermal zone control byte 1 + UINT8 MsgFun81Zone2MsgReg3; ///<Thermal zone control byte 2 + UINT8 MsgFun81Zone2MsgReg4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius. + UINT8 MsgFun81Zone2MsgReg5; ///<Hysteresis information + UINT8 MsgFun81Zone2MsgReg6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 + UINT8 MsgFun81Zone2MsgReg7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located. + UINT8 MsgFun81Zone2MsgReg8; ///<Fan PWM stepping rate in unit of PWM level percentage + UINT8 MsgFun81Zone2MsgReg9; ///<Fan PWM ramping rate in 5ms unit +// +//EC LDN9 function 81 zone 3 +// + UINT8 MsgFun81Zone3MsgReg0; ///<Thermal zone + UINT8 MsgFun81Zone3MsgReg1; ///<Thermal zone + UINT8 MsgFun81Zone3MsgReg2; ///<Thermal zone control byte 1 + UINT8 MsgFun81Zone3MsgReg3; ///<Thermal zone control byte 2 + UINT8 MsgFun81Zone3MsgReg4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius. + UINT8 MsgFun81Zone3MsgReg5; ///<Hysteresis information + UINT8 MsgFun81Zone3MsgReg6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 + UINT8 MsgFun81Zone3MsgReg7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located. + UINT8 MsgFun81Zone3MsgReg8; ///<Fan PWM stepping rate in unit of PWM level percentage + UINT8 MsgFun81Zone3MsgReg9; ///<Fan PWM ramping rate in 5ms unit +// +//EC LDN9 function 83 zone 0 +// + UINT8 MsgFun83Zone0MsgReg0; ///<Thermal zone + UINT8 MsgFun83Zone0MsgReg1; ///<Thermal zone + UINT8 MsgFun83Zone0MsgReg2; ///<_AC0 + UINT8 MsgFun83Zone0MsgReg3; ///<_AC1 + UINT8 MsgFun83Zone0MsgReg4; ///<_AC2 + UINT8 MsgFun83Zone0MsgReg5; ///<_AC3 + UINT8 MsgFun83Zone0MsgReg6; ///<_AC4 + UINT8 MsgFun83Zone0MsgReg7; ///<_AC5 + UINT8 MsgFun83Zone0MsgReg8; ///<_AC6 + UINT8 MsgFun83Zone0MsgReg9; ///<_AC7 + UINT8 MsgFun83Zone0MsgRegA; ///<_CRT + UINT8 MsgFun83Zone0MsgRegB; ///<_PSV +// +//EC LDN9 function 83 zone 1 +// + UINT8 MsgFun83Zone1MsgReg0; ///<Thermal zone + UINT8 MsgFun83Zone1MsgReg1; ///<Thermal zone + UINT8 MsgFun83Zone1MsgReg2; ///<_AC0 + UINT8 MsgFun83Zone1MsgReg3; ///<_AC1 + UINT8 MsgFun83Zone1MsgReg4; ///<_AC2 + UINT8 MsgFun83Zone1MsgReg5; ///<_AC3 + UINT8 MsgFun83Zone1MsgReg6; ///<_AC4 + UINT8 MsgFun83Zone1MsgReg7; ///<_AC5 + UINT8 MsgFun83Zone1MsgReg8; ///<_AC6 + UINT8 MsgFun83Zone1MsgReg9; ///<_AC7 + UINT8 MsgFun83Zone1MsgRegA; ///<_CRT + UINT8 MsgFun83Zone1MsgRegB; ///<_PSV +// +//EC LDN9 function 83 zone 2 +// + UINT8 MsgFun83Zone2MsgReg0; ///<Thermal zone + UINT8 MsgFun83Zone2MsgReg1; ///<Thermal zone + UINT8 MsgFun83Zone2MsgReg2; ///<_AC0 + UINT8 MsgFun83Zone2MsgReg3; ///<_AC1 + UINT8 MsgFun83Zone2MsgReg4; ///<_AC2 + UINT8 MsgFun83Zone2MsgReg5; ///<_AC3 + UINT8 MsgFun83Zone2MsgReg6; ///<_AC4 + UINT8 MsgFun83Zone2MsgReg7; ///<_AC5 + UINT8 MsgFun83Zone2MsgReg8; ///<_AC6 + UINT8 MsgFun83Zone2MsgReg9; ///<_AC7 + UINT8 MsgFun83Zone2MsgRegA; ///<_CRT + UINT8 MsgFun83Zone2MsgRegB; ///<_PSV +// +//EC LDN9 function 83 zone 3 +// + UINT8 MsgFun83Zone3MsgReg0; ///<Thermal zone + UINT8 MsgFun83Zone3MsgReg1; ///<Thermal zone + UINT8 MsgFun83Zone3MsgReg2; ///<_AC0 + UINT8 MsgFun83Zone3MsgReg3; ///<_AC1 + UINT8 MsgFun83Zone3MsgReg4; ///<_AC2 + UINT8 MsgFun83Zone3MsgReg5; ///<_AC3 + UINT8 MsgFun83Zone3MsgReg6; ///<_AC4 + UINT8 MsgFun83Zone3MsgReg7; ///<_AC5 + UINT8 MsgFun83Zone3MsgReg8; ///<_AC6 + UINT8 MsgFun83Zone3MsgReg9; ///<_AC7 + UINT8 MsgFun83Zone3MsgRegA; ///<_CRT + UINT8 MsgFun83Zone3MsgRegB; ///<_PSV +// +//EC LDN9 function 85 zone 0 +// + UINT8 MsgFun85Zone0MsgReg0; ///<Thermal zone + UINT8 MsgFun85Zone0MsgReg1; ///<Thermal zone + UINT8 MsgFun85Zone0MsgReg2; ///<AL0 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone0MsgReg3; ///<AL1 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone0MsgReg4; ///<AL2 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone0MsgReg5; ///<AL3 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone0MsgReg6; ///<AL4 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone0MsgReg7; ///<AL5 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone0MsgReg8; ///<AL6 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone0MsgReg9; ///<AL7 PWM level in percentage (0 - 100%) +// +//EC LDN9 function 85 zone 1 +// + UINT8 MsgFun85Zone1MsgReg0; ///<Thermal zone + UINT8 MsgFun85Zone1MsgReg1; ///<Thermal zone + UINT8 MsgFun85Zone1MsgReg2; ///<AL0 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone1MsgReg3; ///<AL1 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone1MsgReg4; ///<AL2 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone1MsgReg5; ///<AL3 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone1MsgReg6; ///<AL4 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone1MsgReg7; ///<AL5 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone1MsgReg8; ///<AL6 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone1MsgReg9; ///<AL7 PWM level in percentage (0 - 100%) +// +//EC LDN9 function 85 zone 2 +// + UINT8 MsgFun85Zone2MsgReg0; ///<Thermal zone + UINT8 MsgFun85Zone2MsgReg1; ///<Thermal zone + UINT8 MsgFun85Zone2MsgReg2; ///<AL0 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone2MsgReg3; ///<AL1 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone2MsgReg4; ///<AL2 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone2MsgReg5; ///<AL3 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone2MsgReg6; ///<AL4 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone2MsgReg7; ///<AL5 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone2MsgReg8; ///<AL6 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone2MsgReg9; ///<AL7 PWM level in percentage (0 - 100%) +// +//EC LDN9 function 85 zone 3 +// + UINT8 MsgFun85Zone3MsgReg0; ///<Thermal zone + UINT8 MsgFun85Zone3MsgReg1; ///<Thermal zone + UINT8 MsgFun85Zone3MsgReg2; ///<AL0 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone3MsgReg3; ///<AL1 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone3MsgReg4; ///<AL2 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone3MsgReg5; ///<AL3 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone3MsgReg6; ///<AL4 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone3MsgReg7; ///<AL5 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone3MsgReg8; ///<AL6 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone3MsgReg9; ///<AL7 PWM level in percentage (0 - 100%) +// +//EC LDN9 function 89 TEMPIN channel 0 +// + UINT8 MsgFun89Zone0MsgReg0; ///<Thermal zone + UINT8 MsgFun89Zone0MsgReg1; ///<Thermal zone + UINT8 MsgFun89Zone0MsgReg2; ///<At DWORD bit 0-7 + UINT8 MsgFun89Zone0MsgReg3; ///<At DWORD bit 15-8 + UINT8 MsgFun89Zone0MsgReg4; ///<At DWORD bit 23-16 + UINT8 MsgFun89Zone0MsgReg5; ///<At DWORD bit 31-24 + UINT8 MsgFun89Zone0MsgReg6; ///<Ct DWORD bit 0-7 + UINT8 MsgFun89Zone0MsgReg7; ///<Ct DWORD bit 15-8 + UINT8 MsgFun89Zone0MsgReg8; ///<Ct DWORD bit 23-16 + UINT8 MsgFun89Zone0MsgReg9; ///<Ct DWORD bit 31-24 + UINT8 MsgFun89Zone0MsgRegA; ///<Mode bit 0-7 +// +//EC LDN9 function 89 TEMPIN channel 1 +// + UINT8 MsgFun89Zone1MsgReg0; ///<Thermal zone + UINT8 MsgFun89Zone1MsgReg1; ///<Thermal zone + UINT8 MsgFun89Zone1MsgReg2; ///<At DWORD bit 0-7 + UINT8 MsgFun89Zone1MsgReg3; ///<At DWORD bit 15-8 + UINT8 MsgFun89Zone1MsgReg4; ///<At DWORD bit 23-16 + UINT8 MsgFun89Zone1MsgReg5; ///<At DWORD bit 31-24 + UINT8 MsgFun89Zone1MsgReg6; ///<Ct DWORD bit 0-7 + UINT8 MsgFun89Zone1MsgReg7; ///<Ct DWORD bit 15-8 + UINT8 MsgFun89Zone1MsgReg8; ///<Ct DWORD bit 23-16 + UINT8 MsgFun89Zone1MsgReg9; ///<Ct DWORD bit 31-24 + UINT8 MsgFun89Zone1MsgRegA; ///<Mode bit 0-7 +// +//EC LDN9 function 89 TEMPIN channel 2 +// + UINT8 MsgFun89Zone2MsgReg0; ///<Thermal zone + UINT8 MsgFun89Zone2MsgReg1; ///<Thermal zone + UINT8 MsgFun89Zone2MsgReg2; ///<At DWORD bit 0-7 + UINT8 MsgFun89Zone2MsgReg3; ///<At DWORD bit 15-8 + UINT8 MsgFun89Zone2MsgReg4; ///<At DWORD bit 23-16 + UINT8 MsgFun89Zone2MsgReg5; ///<At DWORD bit 31-24 + UINT8 MsgFun89Zone2MsgReg6; ///<Ct DWORD bit 0-7 + UINT8 MsgFun89Zone2MsgReg7; ///<Ct DWORD bit 15-8 + UINT8 MsgFun89Zone2MsgReg8; ///<Ct DWORD bit 23-16 + UINT8 MsgFun89Zone2MsgReg9; ///<Ct DWORD bit 31-24 + UINT8 MsgFun89Zone2MsgRegA; ///<Mode bit 0-7 +// +//EC LDN9 function 89 TEMPIN channel 3 +// + UINT8 MsgFun89Zone3MsgReg0; ///<Thermal zone + UINT8 MsgFun89Zone3MsgReg1; ///<Thermal zone + UINT8 MsgFun89Zone3MsgReg2; ///<At DWORD bit 0-7 + UINT8 MsgFun89Zone3MsgReg3; ///<At DWORD bit 15-8 + UINT8 MsgFun89Zone3MsgReg4; ///<At DWORD bit 23-16 + UINT8 MsgFun89Zone3MsgReg5; ///<At DWORD bit 31-24 + UINT8 MsgFun89Zone3MsgReg6; ///<Ct DWORD bit 0-7 + UINT8 MsgFun89Zone3MsgReg7; ///<Ct DWORD bit 15-8 + UINT8 MsgFun89Zone3MsgReg8; ///<Ct DWORD bit 23-16 + UINT8 MsgFun89Zone3MsgReg9; ///<Ct DWORD bit 31-24 + UINT8 MsgFun89Zone3MsgRegA; ///<Mode bit 0-7 +// +// FLAG for Fun83/85/89 support +// + UINT16 IMCFUNSupportBitMap; ///< Bit0=81FunZone0 support(1=On;0=Off); bit1-3=81FunZone1-Zone3;Bit4-7=83FunZone0-Zone3;Bit8-11=85FunZone0-Zone3;Bit11-15=89FunZone0-Zone3; +} FCH_EC; + +/// +/// IMC structure +/// +typedef struct _FCH_IMC { + UINT8 ImcEnable; ///< ImcEnable - IMC Enable + UINT8 ImcEnabled; ///< ImcEnabled - IMC Enable + UINT8 ImcSureBootTimer; ///< ImcSureBootTimer - IMc SureBootTimer function + FCH_EC EcStruct; ///< EC structure + UINT8 ImcEnableOverWrite; ///< OverWrite IMC with the EC structure + /// @li <b>0</b> - disable + /// @li <b>1</b> - enable + /// +} FCH_IMC; + + +/// +/// Hpet structure +/// +typedef struct { + BOOLEAN HpetEnable; ///< HPET function switch + + BOOLEAN HpetMsiDis; ///< HpetMsiDis - South Bridge HPET MSI Configuration + /// @par + /// @li <b>1</b> - disable + /// @li <b>0</b> - enable + + UINT32 HpetBase; ///< HpetBase + /// @par + /// HPET Base address +} FCH_HPET; + + +/// +/// GCPU related parameters +/// +typedef struct { + UINT8 AcDcMsg; ///< Send a message to CPU to indicate the power mode (AC vs battery) + /// @li <b>1</b> - disable + /// @li <b>0</b> - enable + + UINT8 TimerTickTrack; ///< Send a message to CPU to indicate the latest periodic timer interval + /// @li <b>1</b> - disable + /// @li <b>0</b> - enable + + UINT8 ClockInterruptTag; ///< Mark the periodic timer interrupt + /// @li <b>1</b> - disable + /// @li <b>0</b> - enable + + UINT8 OhciTrafficHanding; ///< Cause CPU to break out from C state when USB OHCI has pending traffic + /// @li <b>1</b> - disable + /// @li <b>0</b> - enable + + UINT8 EhciTrafficHanding; ///< Cause CPU to break out from C state when USB EHCI has pending traffic + /// @li <b>1</b> - disable + /// @li <b>0</b> - enable + + UINT8 GcpuMsgCMultiCore; ///< Track of CPU C state by monitoring each core's C state message + /// @li <b>1</b> - disable + /// @li <b>0</b> - enable + + UINT8 GcpuMsgCStage; ///< Enable the FCH C state coordination logic + /// @li <b>1</b> - disable + /// @li <b>0</b> - enable +} FCH_GCPU; + + +/// +/// Timer +/// +typedef struct { + BOOLEAN Enable; ///< Whether to register timer SMI in POST + BOOLEAN StartNow; ///< Whether to start the SMI immediately during registration + UINT16 CycleDuration; ///< [14:0] - Actual cycle duration = CycleDuration + 1 +} TIMER_SMI; + + +/// +/// MISC structure +/// +typedef struct { + BOOLEAN NativePcieSupport; /// PCIe NativePcieSupport - Debug function. 1:Enabled, 0:Disabled + BOOLEAN S3Resume; /// S3Resume - Flag of ACPI S3 Resume. + BOOLEAN RebootRequired; /// RebootRequired - Flag of Reboot system is required. + UINT8 FchVariant; /// FchVariant - FCH Variant value. + UINT8 Cg2Pll; ///< CG2 PLL - 0:disable, 1:enable + TIMER_SMI LongTimer; ///< Long Timer SMI + TIMER_SMI ShortTimer; ///< Short Timer SMI +} FCH_MISC; + + +/// +/// SMBus structure +/// +typedef struct { + UINT32 SmbusSsid; ///< SMBUS controller Subsystem ID +} FCH_SMBUS; + + +/// +/// Acpi structure +/// +typedef struct { + UINT16 Smbus0BaseAddress; ///< Smbus0BaseAddress + /// @par + /// Smbus BASE Address + /// + UINT16 Smbus1BaseAddress; ///< Smbus1BaseAddress + /// @par + /// Smbus1 (ASF) BASE Address + /// + UINT16 SioPmeBaseAddress; ///< SioPmeBaseAddress + /// @par + /// SIO PME BASE Address + /// + UINT32 WatchDogTimerBase; ///< WatchDogTimerBase + /// @par + /// Watch Dog Timer Address + /// + UINT16 AcpiPm1EvtBlkAddr; ///< AcpiPm1EvtBlkAddr + /// @par + /// ACPI PM1 event block Address + /// + UINT16 AcpiPm1CntBlkAddr; ///< AcpiPm1CntBlkAddr + /// @par + /// ACPI PM1 Control block Address + /// + UINT16 AcpiPmTmrBlkAddr; ///< AcpiPmTmrBlkAddr + /// @par + /// ACPI PM timer block Address + /// + UINT16 CpuControlBlkAddr; ///< CpuControlBlkAddr + /// @par + /// ACPI CPU control block Address + /// + UINT16 AcpiGpe0BlkAddr; ///< AcpiGpe0BlkAddr + /// @par + /// ACPI GPE0 block Address + /// + UINT16 SmiCmdPortAddr; ///< SmiCmdPortAddr + /// @par + /// SMI command port Address + /// + UINT16 AcpiPmaCntBlkAddr; ///< AcpiPmaCntBlkAddr + /// @par + /// ACPI PMA Control block Address + /// + BOOLEAN AnyHt200MhzLink; ///< AnyHt200MhzLink + /// @par + /// HT Link Speed on 200MHz option for each CPU specific LDTSTP# (Force enable) + /// + BOOLEAN SpreadSpectrum; ///< SpreadSpectrum + /// @par + /// Spread Spectrum function + /// @li <b>0</b> - disable + /// @li <b>1</b> - enable + /// + POWER_FAIL PwrFailShadow; ///< PwrFailShadow = PM_Reg: 5Bh [3:0] + /// @par + /// @li <b>00</b> - Always off + /// @li <b>01</b> - Always on + /// @li <b>11</b> - Use previous + /// + UINT8 StressResetMode; ///< StressResetMode 01-10 + /// @li <b>00</b> - Disabed + /// @li <b>01</b> - Io Write 0x64 with 0xfe + /// @li <b>10</b> - Io Write 0xcf9 with 0x06 + /// @li <b>11</b> - Io Write 0xcf9 with 0x0e + /// + BOOLEAN MtC1eEnable; /// MtC1eEnable - Enable MtC1e + VOID* OemProgrammingTablePtr; /// Pointer of ACPI OEM table +} FCH_ACPI; + + +/// +/// HWM temp parameter structure +/// +typedef struct _FCH_HWM_TEMP_PAR { + UINT16 At; ///< At + UINT16 Ct; ///< Ct + UINT8 Mode; ///< Mode BIT0:HiRatio BIT1:HiCurrent +} FCH_HWM_TEMP_PAR; + +/// +/// HWM Current structure +/// +typedef struct _FCH_HWM_CUR { + UINT16 FanSpeed[5]; ///< FanSpeed - fan Speed + UINT16 Temperature[5]; ///< Temperature - temperature + UINT16 Voltage[8]; ///< Voltage - voltage +} FCH_HWM_CUR; + +/// +/// HWM fan control structure +/// +typedef struct _FCH_HWM_FAN_CTR { + UINT8 InputControlReg00; /// Fan Input Control register, PM2 offset [0:4]0 + UINT8 ControlReg01; /// Fan control register, PM2 offset [0:4]1 + UINT8 FreqReg02; /// Fan frequency register, PM2 offset [0:4]2 + UINT8 LowDutyReg03; /// Low Duty register, PM2 offset [0:4]3 + UINT8 MedDutyReg04; /// Med Duty register, PM2 offset [0:4]4 + UINT8 MultiplierReg05; /// Multiplier register, PM2 offset [0:4]5 + UINT16 LowTempReg06; /// Low Temp register, PM2 offset [0:4]6 + UINT16 MedTempReg08; /// Med Temp register, PM2 offset [0:4]8 + UINT16 HighTempReg0A; /// High Temp register, PM2 offset [0:4]A + UINT8 LinearRangeReg0C; /// Linear Range register, PM2 offset [0:4]C + UINT8 LinearHoldCountReg0D; /// Linear Hold Count register, PM2 offset [0:4]D +} FCH_HWM_FAN_CTR; + +/// +/// Hwm structure +/// +typedef struct _FCH_HWM { + UINT8 HwMonitorEnable; ///< HwMonitorEnable + UINT32 HwmControl; ///< hwmControl + /// @par + /// HWM control configuration + /// @li <b>0</b> - HWM is Enabled + /// @li <b>1</b> - IMC is Enabled + /// + UINT8 FanSampleFreqDiv; ///< Sampling rate of Fan Speed + /// @li <b>00</b> - Base(22.5KHz) + /// @li <b>01</b> - Base(22.5KHz)/2 + /// @li <b>10</b> - Base(22.5KHz)/4 + /// @li <b>11</b> - Base(22.5KHz)/8 + /// + UINT8 HwmFchtsiAutoPoll; ///< TSI Auto Polling + /// @li <b>0</b> - disable + /// @li <b>1</b> - enable + /// + UINT8 HwmFchtsiAutoPollStarted; ///< HwmSbtsiAutoPollStarted + UINT8 FanLinearEnhanceEn; ///< FanLinearEnhanceEn + UINT8 FanLinearHoldFix; ///< FanLinearHoldFix + UINT8 FanLinearRangeOutLimit; ///< FanLinearRangeOutLimit + UINT16 HwmCalibrationFactor; /// Calibration Factor + FCH_HWM_CUR HwmCurrent; /// HWM Current structure + FCH_HWM_CUR HwmCurrentRaw; /// HWM Current Raw structure + FCH_HWM_TEMP_PAR HwmTempPar[5]; /// HWM Temp parameter structure + FCH_HWM_FAN_CTR HwmFanControl[5]; /// HWM Fan Control structure + FCH_HWM_FAN_CTR HwmFanControlCooked[5]; /// HWM Fan Control structure +} FCH_HWM; + + +/// +/// Gec structure +/// +typedef struct { + BOOLEAN GecEnable; ///< GecEnable - GEC function switch + UINT8 GecPhyStatus; /// GEC PHY Status + UINT8 GecPowerPolicy; /// GEC Power Policy + /// @li <b>00</b> - GEC is powered down in S3 and S5 + /// @li <b>01</b> - GEC is powered down only in S5 + /// @li <b>10</b> - GEC is powered down only in S3 + /// @li <b>11</b> - GEC is never powered down + /// + UINT8 GecDebugBus; /// GEC Debug Bus + /// @li <b>0</b> - disable + /// @li <b>1</b> - enable + /// + UINT32 GecShadowRomBase; ///< GecShadowRomBase + /// @par + /// GEC (NIC) SHADOWROM BASE Address + /// + VOID *PtrDynamicGecRomAddress; /// Pointer of Dynamic GEC ROM Address +} FCH_GEC; + + +/// +/// _ABTblEntry - AB link register table R/W structure +/// +typedef struct _AB_TBL_ENTRY { + UINT8 RegType; /// RegType : AB Register Type (ABCFG, AXCFG and so on) + UINT32 RegIndex; /// RegIndex : AB Register Index + UINT32 RegMask; /// RegMask : AB Register Mask + UINT32 RegData; /// RegData : AB Register Data +} AB_TBL_ENTRY; + +/// +/// AB structure +/// +typedef struct { + BOOLEAN AbMsiEnable; ///< ABlink MSI capability + UINT8 ALinkClkGateOff; /// Alink Clock Gate-Off function - 0:disable, 1:enable *KR + UINT8 BLinkClkGateOff; /// Blink Clock Gate-Off function - 0:disable, 1:enable *KR + UINT8 AbClockGating; /// AB Clock Gating - 0:disable, 1:enable *KR + UINT8 GppClockGating; /// GPP Clock Gating - 0:disable, 1:enable + UINT8 UmiL1TimerOverride; /// UMI L1 inactivity timer overwrite value + UINT8 UmiLinkWidth; /// UMI Link Width + UINT8 UmiDynamicSpeedChange; /// UMI Dynamic Speed Change - 0:disable, 1:enable + UINT8 PcieRefClockOverClocking; /// PCIe Ref Clock OverClocking value + UINT8 UmiGppTxDriverStrength; /// UMI GPP TX Driver Strength + BOOLEAN NbSbGen2; /// UMI link Gen2 - 0:Gen1, 1:Gen2 + UINT8 PcieOrderRule; /// PCIe Order Rule - 0:disable, 1:enable *KR AB Posted Pass Non-Posted + UINT8 SlowSpeedAbLinkClock; /// Slow Speed AB Link Clock - 0:disable, 1:enable *KR + UINT8 ResetCpuOnSyncFlood; /// Reset Cpu On Sync Flood - 0:disable, 1:enable *KR + BOOLEAN AbDmaMemoryWrtie3264B; /// AB DMA Memory Write 32/64 BYTE Support *KR only + BOOLEAN AbMemoryPowerSaving; /// AB Memory Power Saving *KR only + BOOLEAN SbgDmaMemoryWrtie3264ByteCount; /// SBG DMA Memory Write 32/64 BYTE Count Support *KR only + BOOLEAN SbgMemoryPowerSaving; /// SBG Memory Power Saving *KR only +} FCH_AB; + + +/** + * PCIE_CAP_ID - PCIe Cap ID + * + */ +#define PCIE_CAP_ID 0x10 + +/// +/// FCH_GPP_PORT_CONFIG - Fch GPP port config structure +/// +typedef struct { + BOOLEAN PortPresent; ///< Port connection + /// @par + /// @li <b>0</b> - Port doesn't have slot. No need to train the link + /// @li <b>1</b> - Port connection defined and needs to be trained + /// + BOOLEAN PortDetected; ///< Link training status + /// @par + /// @li <b>0</b> - EP not detected + /// @li <b>1</b> - EP detected + /// + BOOLEAN PortIsGen2; ///< Port link speed configuration + /// @par + /// @li <b>00</b> - Auto + /// @li <b>01</b> - Forced GEN1 + /// @li <b>10</b> - Forced GEN2 + /// @li <b>11</b> - Reserved + /// + BOOLEAN PortHotPlug; ///< Support hot plug? + /// @par + /// @li <b>0</b> - No support + /// @li <b>1</b> - support + /// + UINT8 PortMisc; /// PortMisc - Reserved +} FCH_GPP_PORT_CONFIG; + +/// +/// GPP structure +/// +typedef struct { + FCH_GPP_PORT_CONFIG PortCfg[4]; /// GPP port configuration structure + GPP_LINKMODE GppLinkConfig; ///< GppLinkConfig - PCIE_GPP_Enable[3:0] + /// @li <b>0000</b> - Port ABCD -> 4:0:0:0 + /// @li <b>0010</b> - Port ABCD -> 2:2:0:0 + /// @li <b>0011</b> - Port ABCD -> 2:1:1:0 + /// @li <b>0100</b> - Port ABCD -> 1:1:1:1 + /// + BOOLEAN GppFunctionEnable; ///< GPP Function - 0:disable, 1:enable + BOOLEAN GppToggleReset; ///< Toggle GPP core reset + UINT8 GppHotPlugGeventNum; ///< Hotplug GEVENT # - valid value 0-31 + UINT8 GppFoundGfxDev; ///< Gpp Found Gfx Device + /// @li <b>0</b> - Not found + /// @li <b>1</b> - Found + /// + BOOLEAN GppGen2; ///< GPP Gen2 - 0:disable, 1:enable + UINT8 GppGen2Strap; ///< GPP Gen2 Strap - 0:disable, 1:enable, FCH itself uses this + BOOLEAN GppMemWrImprove; ///< GPP Memory Write Improve - 0:disable, 1:enable + BOOLEAN GppUnhidePorts; ///< GPP Unhide Ports - 0:disable, 1:enable + UINT8 GppPortAspm; ///< GppPortAspm - ASPM state for all GPP ports + /// @li <b>01</b> - Disabled + /// @li <b>01</b> - L0s + /// @li <b>10</b> - L1 + /// @li <b>11</b> - L0s + L1 + /// + BOOLEAN GppLaneReversal; ///< GPP Lane Reversal - 0:disable, 1:enable + BOOLEAN GppPhyPllPowerDown; ///< GPP PHY PLL Power Down - 0:disable, 1:enable + BOOLEAN GppDynamicPowerSaving; ///< GPP Dynamic Power Saving - 0:disable, 1:enable + BOOLEAN PcieAer; ///< PcieAer - Advanced Error Report: 0/1-disable/enable + BOOLEAN PcieRas; ///< PCIe RAS - 0:disable, 1:enable + BOOLEAN PcieCompliance; ///< PCIe Compliance - 0:disable, 1:enable + BOOLEAN PcieSoftwareDownGrade; ///< PCIe Software Down Grade + BOOLEAN UmiPhyPllPowerDown; ///< UMI PHY PLL Power Down - 0:disable, 1:enable + BOOLEAN SerialDebugBusEnable; ///< Serial Debug Bus Enable + UINT8 GppHardwareDownGrade; ///< GppHardwareDownGrade - Gpp HW Down Grade function 0:Disable, 1-4: portA-D + UINT8 GppL1ImmediateAck; ///< GppL1ImmediateAck - Gpp L1 Immediate ACK 0: enable, 1: disable + BOOLEAN NewGppAlgorithm; ///< NewGppAlgorithm - New GPP procedure + UINT8 HotPlugPortsStatus; ///< HotPlugPortsStatus - Save Hot-Plug Ports Status + UINT8 FailPortsStatus; ///< FailPortsStatus - Save Failure Ports Status + UINT8 GppPortMinPollingTime; ///< GppPortMinPollingTime - Min. Polling time for Gpp Port Training +} FCH_GPP; + + +/// +/// FCH USB sturcture +/// +typedef struct { + BOOLEAN Ohci1Enable; ///< OHCI1 controller enable + BOOLEAN Ohci2Enable; ///< OHCI2 controller enable + BOOLEAN Ohci3Enable; ///< OHCI3 controller enable + BOOLEAN Ohci4Enable; ///< OHCI4 controller enable + BOOLEAN Ehci1Enable; ///< EHCI1 controller enable + BOOLEAN Ehci2Enable; ///< EHCI2 controller enable + BOOLEAN Ehci3Enable; ///< EHCI3 controller enable + BOOLEAN Xhci0Enable; ///< XHCI0 controller enable + BOOLEAN Xhci1Enable; ///< XHCI1 controller enable + BOOLEAN UsbMsiEnable; ///< USB MSI capability + UINT32 OhciSsid; ///< OHCI SSID + UINT32 Ohci4Ssid; ///< OHCI 4 SSID + UINT32 EhciSsid; ///< EHCI SSID + UINT32 XhciSsid; ///< XHCI SSID + BOOLEAN UsbPhyPowerDown; ///< USB PHY Power Down - 0:disable, 1:enable + UINT32 UserDefineXhciRomAddr; ///< XHCI ROM address define by platform BIOS +} FCH_USB; + + +/// Private: FCH_DATA_BLOCK_RESET +typedef struct _FCH_RESET_DATA_BLOCK { + AMD_CONFIG_PARAMS *StdHeader; ///< Header structure + FCH_RESET_INTERFACE FchReset; ///< Reset interface + + UINT8 FastSpeed; ///< SPI Fast Speed - 0:disable, 1:enable + UINT8 WriteSpeed; ///< SPI Write Speed + UINT8 Mode; ///< SPI Mode + /// @li <b>101</b> - Qual-io 1-4-4 + /// @li <b>100</b> - Dual-io 1-2-2 + /// @li <b>011</b> - Qual-io 1-1-4 + /// @li <b>010</b> - Dual-io 1-1-2 + /// @li <b>111</b> - FastRead + /// @li <b>110</b> - Normal + /// + UINT8 AutoMode; ///< SPI Auto Mode - 0:disable, 1:enable + UINT8 BurstWrite; ///< SPI Burst Write - 0:disable, 1:enable + BOOLEAN Sata6AhciCap; ///< SATA 6 AHCI Capability - TRUE:enable, FALSE:disable + UINT8 Cg2Pll; ///< CG2 PLL - 0:disable, 1:enable + BOOLEAN EcKbd; ///< EC KBD - 0:disable, 1:enable + BOOLEAN LegacyFree; ///< Legacy Free - 0:disable, 1:enable + BOOLEAN SataSetMaxGen2; ///< SATA enable maximum GEN2 + UINT8 SataClkMode; ///< SATA reference clock selector and divider + UINT8 SataModeReg; ///< Output: SATAConfig PMIO:0xDA + BOOLEAN SataInternal100Spread; ///< SATA internal 100MHz spread ON/OFF + UINT8 SpiSpeed; ///< SPI NormSpeed: 00-66MHz, 01-33MHz, 10-22MHz, 11-16.5MHz + BOOLEAN EcChannel0; ///< Enable EC channel 0 + FCH_GPP Gpp; ///< GPP subsystem + VOID* OemResetProgrammingTablePtr; /// Pointer of ACPI OEM table +} FCH_RESET_DATA_BLOCK; + + +/// Private: FCH_DATA_BLOCK +typedef struct _FCH_DATA_BLOCK { + AMD_CONFIG_PARAMS *StdHeader; ///< Header structure + + FCH_ACPI HwAcpi; ///< ACPI structure + FCH_AB Ab; ///< AB structure + FCH_GPP Gpp; ///< GPP structure + FCH_USB Usb; ///< USB structure + FCH_SATA Sata; ///< SATA structure + FCH_SMBUS Smbus; ///< SMBus structure + FCH_IDE Ide; ///< IDE structure + FCH_AZALIA Azalia; ///< Azalia structure + FCH_SPI Spi; ///< SPI structure + FCH_PCIB Pcib; ///< PCIB structure + FCH_GEC Gec; ///< GEC structure + FCH_SD Sd; ///< SD structure + FCH_HWM Hwm; ///< Hardware Moniter structure + FCH_IR Ir; ///< IR structure + FCH_HPET Hpet; ///< HPET structure + FCH_GCPU Gcpu; ///< GCPU structure + FCH_IMC Imc; ///< IMC structure + FCH_MISC Misc; ///< MISC structure +} FCH_DATA_BLOCK; + +#pragma pack (pop) + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonSmm.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonSmm.c new file mode 100644 index 0000000..777e9ce --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchCommonSmm.c @@ -0,0 +1,98 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH common SMM + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_COMMON_FCHCOMMONSMM_FILECODE + +/*----------------------------------------------------------------------------------------*/ +/** + * FchSmmAcpiOn - Config Fch during ACPI_ON + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchSmmAcpiOn ( + IN FCH_DATA_BLOCK *FchDataPtr + ) +{ + // + // Commented the following code since we need to leave the IRQ1/12 filtering enabled always as per latest + // recommendation. This is required to fix the keyboard stuck issue when playing games under Windows + // + + // + // Disable Power Button SMI + // + RwMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGAC, AccessWidth8, ~(BIT6), 0); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchDef.h b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchDef.h new file mode 100644 index 0000000..af1d1ba --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchDef.h @@ -0,0 +1,484 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH routine definition + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#ifndef _FCH_DEF_H_ +#define _FCH_DEF_H_ + + +UINT32 ReadAlink (IN UINT32 Index, IN AMD_CONFIG_PARAMS *StdHeader); +VOID WriteAlink (IN UINT32 Index, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader); +VOID RwAlink (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); +VOID ReadMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr); +VOID WriteMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr); +VOID RwMem (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data); +VOID ReadPci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID WritePci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID RwPci (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader); +VOID ProgramPciByteTable (IN REG8_MASK* pPciByteTable, IN UINT16 dwTableSize, IN AMD_CONFIG_PARAMS *StdHeader); +VOID ProgramFchAcpiMmioTbl (IN ACPI_REG_WRITE *pAcpiTbl, IN AMD_CONFIG_PARAMS *StdHeader); +VOID ProgramFchSciMapTbl (IN SCI_MAP_CONTROL *pSciMapTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock); +VOID ProgramFchGpioTbl (IN GPIO_CONTROL *pGpioTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock); +VOID ProgramFchSataPhyTbl (IN SATA_PHY_CONTROL *pSataPhyTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock); +VOID GetChipSysMode (IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +BOOLEAN IsImcEnabled (IN AMD_CONFIG_PARAMS *StdHeader); +VOID ReadPmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID WritePmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID RwPmio (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); +VOID ReadPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID WritePmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID RwPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); +VOID ReadBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID WriteBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID GetFchAcpiMmioBase (OUT UINT32 *AcpiMmioBase, IN AMD_CONFIG_PARAMS *StdHeader); +VOID GetFchAcpiPmBase (OUT UINT16 *AcpiPmBase, IN AMD_CONFIG_PARAMS *StdHeader); +UINT8 ReadFchSleepType (IN AMD_CONFIG_PARAMS *StdHeader); + +/// +/// Fch Ab Routines +/// +/// Pei Phase +/// +VOID FchInitResetAb (IN VOID* FchDataPtr); +VOID FchProgramAbPowerOnReset (IN VOID* FchDataPtr); +/// +/// Dxe Phase +/// +VOID FchInitEnvAb (IN VOID* FchDataPtr); +VOID FchInitEnvAbSpecial (IN VOID* FchDataPtr); +VOID FchInitMidAb (IN VOID* FchDataPtr); +VOID FchInitLateAb (IN VOID* FchDataPtr); +/// +/// Other Public Routines +/// +VOID FchInitEnvAbLinkInit (IN VOID* FchDataPtr); +BOOLEAN IsUmiOneLaneGen1Mode (IN AMD_CONFIG_PARAMS *StdHeader); +VOID FchAbLateProgram (IN VOID* FchDataPtr); + +/// +/// Fch Pcie Routines +/// +/// Pei Phase +/// +VOID FchInitResetPcie (IN VOID* FchDataPtr); +/// +/// Dxe Phase +/// +VOID FchInitEnvPcie (IN VOID* FchDataPtr); +VOID FchInitMidPcie (IN VOID* FchDataPtr); +VOID FchInitLatePcie (IN VOID* FchDataPtr); +VOID ProgramPcieNativeMode (IN VOID* FchDataPtr); + +/// +/// Fch Gpp Routines +/// +/// Pei Phase +/// +VOID FchInitResetGpp (IN VOID* FchDataPtr); +VOID ProgramFchGppInitReset (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader); +VOID FchResetPcie (IN RESET_BLOCK ResetBlock, IN RESET_OP ResetOp, IN AMD_CONFIG_PARAMS *StdHeader); + +/// +/// Dxe Phase +/// +VOID FchInitEnvGpp (IN VOID* FchDataPtr); +VOID FchInitMidGpp (IN VOID* FchDataPtr); +VOID FchInitLateGpp (IN VOID* FchDataPtr); + +/// +/// Common Gpp Routines +/// +VOID ProgramGppTogglePcieReset (IN BOOLEAN DoToggling, IN AMD_CONFIG_PARAMS *StdHeader); +VOID FchGppForceGen1 (IN FCH_GPP *FchGpp, IN CONST UINT8 ActivePorts, IN AMD_CONFIG_PARAMS *StdHeader); +VOID FchGppForceGen2 (IN FCH_GPP *FchGpp, IN CONST UINT8 ActivePorts, IN AMD_CONFIG_PARAMS *StdHeader); +VOID FchGppDynamicPowerSaving (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader); +UINT8 GppPortPollingLtssm (IN FCH_GPP *FchGpp, IN UINT8 ActivePorts, IN BOOLEAN IsGen2, IN AMD_CONFIG_PARAMS *StdHeader); +VOID GppGen2Workaround (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader); +UINT8 FchFindPciCap (IN UINT32 PciAddress, IN UINT8 TargetCapId, IN AMD_CONFIG_PARAMS *StdHeader); +VOID FchGppPortInit (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader); +VOID FchGppPortInitPhaseII (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader); +VOID FchGppPortInitS3Phase (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader); +UINT32 GppGetFchTempBus (IN AMD_CONFIG_PARAMS *StdHeader); + +/// +/// +/// Pei Phase +/// +VOID Fchdef174 (IN VOID *FchDataPtr); +/// +/// Dxe Phase +/// +VOID Fchdef178 (IN VOID *FchDataPtr); +VOID Fchdef179 (IN VOID *FchDataPtr); +VOID Fchdef180 (IN VOID *FchDataPtr); + + +/// +/// Fch GEC Routines +/// +/// Pei Phase +/// +VOID FchInitResetGec (IN VOID* FchDataPtr); +/// +/// Dxe Phase +/// +VOID FchInitEnvGec (IN VOID* FchDataPtr); +VOID FchInitMidGec (IN VOID* FchDataPtr); +VOID FchInitLateGec (IN VOID* FchDataPtr); +/// +/// Other Public Routines +/// +VOID FchInitGecController (IN VOID* FchDataPtr); +VOID FchSwInitGecBootRom (IN VOID* FchDataPtr); + +/// +/// Fch HwAcpi Routines +/// +/// Pei Phase +/// +VOID FchInitResetHwAcpiP (IN VOID *FchDataPtr); +VOID FchInitResetHwAcpi (IN VOID *FchDataPtr); +VOID ProgramFchHwAcpiResetP (IN VOID *FchDataPtr); +/// +/// Dxe Phase +/// +VOID FchInitEnvHwAcpiP (IN VOID *FchDataPtr); +VOID FchInitEnvHwAcpi (IN VOID *FchDataPtr); +VOID ProgramEnvPFchAcpiMmio (IN VOID *FchDataPtr); +VOID ProgramFchEnvHwAcpiPciReg (IN VOID *FchDataPtr); +VOID ProgramSpecificFchInitEnvAcpiMmio (IN VOID *FchDataPtr); +VOID ProgramFchEnvSpreadSpectrum (IN VOID *FchDataPtr); +VOID FchInitMidHwAcpi (IN VOID *FchDataPtr); +VOID FchInitLateHwAcpi (IN VOID *FchDataPtr); + +/// +/// Other Public Routines +/// +VOID HpetInit (IN VOID *FchDataPtr); +VOID C3PopupSetting (IN VOID *FchDataPtr); +VOID MtC1eEnable (IN VOID *FchDataPtr); +VOID GcpuRelatedSetting (IN VOID *FchDataPtr); +VOID StressResetModeLate (IN VOID *FchDataPtr); + +/// +/// Fch Hwm Routines +/// +/// Pei Phase +/// +VOID FchInitResetHwm (IN VOID* FchDataPtr); +/// +/// Dxe Phase +/// +VOID FchInitEnvHwm (IN VOID* FchDataPtr); +VOID FchInitMidHwm (IN VOID* FchDataPtr); +VOID FchInitLateHwm (IN VOID* FchDataPtr); +/// +/// Other Public Routines +/// +VOID HwmInitRegister (IN VOID* FchDataPtr); +VOID HwmProcessParameter (IN VOID* FchDataPtr); +VOID HwmSetRegister (IN VOID* FchDataPtr); +VOID HwmGetCalibrationFactor (IN VOID* FchDataPtr); +VOID HwmFchtsiAutoPolling (IN VOID* FchDataPtr); +VOID HwmGetRawData (IN VOID* FchDataPtr); +VOID HwmCaculate (IN VOID* FchDataPtr); +VOID HwmFchtsiAutoPollingOff (IN VOID* FchDataPtr); +VOID FchECfancontrolservice (IN VOID* FchDataPtr); + + +/// +/// Fch Ide Routines +/// +VOID FchInitEnvIde (IN VOID* FchDataPtr); +VOID FchInitMidIde (IN VOID* FchDataPtr); +VOID FchInitLateIde (IN VOID* FchDataPtr); + + +/// +/// Fch Imc Routines +/// +/// Pei Phase +/// +VOID FchInitResetImc (IN VOID *FchDataPtr); +VOID FchInitResetEc (IN VOID *FchDataPtr); +/// +/// Dxe Phase +/// +VOID FchInitEnvImc (IN VOID *FchDataPtr); +VOID FchInitMidImc (IN VOID *FchDataPtr); +VOID FchInitLateImc (IN VOID *FchDataPtr); +VOID FchInitEnvEc (IN VOID *FchDataPtr); +VOID FchInitMidEc (IN VOID *FchDataPtr); +VOID FchInitLateEc (IN VOID *FchDataPtr); +/// +/// Other Public Routines +/// +VOID EnterEcConfig (IN AMD_CONFIG_PARAMS *StdHeader); +VOID ExitEcConfig (IN AMD_CONFIG_PARAMS *StdHeader); +VOID ReadEc8 (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID WriteEc8 (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID RwEc8 (IN UINT8 Address, IN UINT8 AndMask, IN UINT8 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); +VOID WriteECmsg (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID ReadECmsg (IN UINT8 Address, IN UINT8 OpFlag, OUT VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID WaitForEcLDN9MailboxCmdAck (IN AMD_CONFIG_PARAMS *StdHeader); + +VOID ImcSleep (IN VOID *FchDataPtr); +VOID ImcEnableSurebootTimer (IN VOID *FchDataPtr); +VOID ImcDisarmSurebootTimer (IN VOID *FchDataPtr); +VOID ImcDisableSurebootTimer (IN VOID *FchDataPtr); +VOID ImcWakeup (IN VOID *FchDataPtr); +VOID ImcIdle (IN VOID *FchDataPtr); +BOOLEAN ValidateImcFirmware (IN VOID *FchDataPtr); +VOID SoftwareToggleImcStrapping (IN VOID *FchDataPtr); + + +/// +/// Fch Ir Routines +/// +/// Dxe Phase +/// +VOID FchInitEnvIr (IN VOID* FchDataPtr); +VOID FchInitMidIr (IN VOID* FchDataPtr); +VOID FchInitLateIr (IN VOID* FchDataPtr); + +/// +/// Fch Pcib Routines +/// +/// Pei Phase +/// +VOID FchInitResetPcib (IN VOID* FchDataPtr); +VOID FchInitResetPcibPort80Enable (IN VOID* FchDataPtr); + +/// +/// Dxe Phase +/// +VOID FchInitEnvPcib (IN VOID* FchDataPtr); +VOID FchInitMidPcib (IN VOID* FchDataPtr); +VOID FchInitLatePcib (IN VOID* FchDataPtr); + + +/// +/// Fch SATA Routines +/// +/// Pei Phase +/// +VOID FchInitResetSata (IN VOID *FchDataPtr); +VOID FchInitResetSataProgram (IN VOID *FchDataPtr); +/// +/// Dxe Phase +/// +VOID FchInitMidSata (IN VOID *FchDataPtr); +VOID FchInitEnvSata (IN VOID *FchDataPtr); +VOID FchInitEnvProgramSataPciRegs (IN VOID *FchDataPtr); +VOID FchInitMidProgramSataRegs (IN VOID *FchDataPtr); +VOID FchInitLateProgramSataRegs (IN VOID *FchDataPtr); + +VOID FchInitLateSata (IN VOID *FchDataPtr); +VOID FchInitEnvSataIde (IN VOID *FchDataPtr); +VOID FchInitMidSataIde (IN VOID *FchDataPtr); +VOID FchInitLateSataIde (IN VOID *FchDataPtr); +VOID FchInitEnvSataAhci (IN VOID *FchDataPtr); +VOID FchInitMidSataAhci (IN VOID *FchDataPtr); +VOID FchInitLateSataAhci (IN VOID *FchDataPtr); +VOID FchInitEnvSataRaid (IN VOID *FchDataPtr); +VOID FchInitMidSataRaid (IN VOID *FchDataPtr); +VOID FchInitLateSataRaid (IN VOID *FchDataPtr); +VOID FchInitEnvSataIde2Ahci (IN VOID *FchDataPtr); +VOID FchInitMidSataIde2Ahci (IN VOID *FchDataPtr); +VOID FchInitLateSataIde2Ahci (IN VOID *FchDataPtr); + +VOID SataAhciSetDeviceNumMsi (IN VOID *FchDataPtr); +VOID SataRaidSetDeviceNumMsi (IN VOID *FchDataPtr); +VOID SataIde2AhciSetDeviceNumMsi (IN VOID *FchDataPtr); +VOID SataSetIrqIntResource (IN VOID *FchDataPtr, IN AMD_CONFIG_PARAMS *StdHeader); +VOID SataBar5setting (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr); +VOID SataEnableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader); +VOID SataDisableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader); +VOID SataSetDeviceNumMsi (IN VOID *FchDataPtr); +VOID FchSataSetDeviceNumMsi (IN VOID *FchDataPtr); +VOID ShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5); +VOID FchShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5); +VOID SataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr); +VOID FchSataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr); +VOID FchSataGpioInitial (IN VOID *FchDataPtr); +VOID SataBar5RegSet (IN VOID *FchDataPtr); +VOID SataSetPortGenMode (IN VOID *FchDataPtr); +VOID FchSataSetPortGenMode (IN VOID *FchDataPtr); +VOID FchProgramSataPhy (IN AMD_CONFIG_PARAMS *StdHeader); +VOID FchSataDriveFpga (IN VOID *FchDataPtr); +VOID FchInitEnvSataRaidProgram (IN VOID *FchDataPtr); + +/// +/// FCH USB Controller Public Function +/// +/// Pei Phase +/// +VOID FchInitResetUsb (IN VOID *FchDataPtr); +VOID FchInitResetOhci (IN VOID *FchDataPtr); +VOID FchInitResetEhci (IN VOID *FchDataPtr); +VOID FchInitResetXhci (IN VOID *FchDataPtr); +VOID FchInitResetXhciProgram (IN VOID *FchDataPtr); +/// +/// Dxe Phase +/// +VOID FchInitEnvUsb (IN VOID *FchDataPtr); +VOID FchInitMidUsb (IN VOID *FchDataPtr); +VOID FchInitLateUsb (IN VOID *FchDataPtr); +VOID FchInitEnvUsbOhci (IN VOID *FchDataPtr); +VOID FchInitMidUsbOhci (IN VOID *FchDataPtr); +VOID FchInitLateUsbOhci (IN VOID *FchDataPtr); +VOID FchInitEnvUsbEhci (IN VOID *FchDataPtr); +VOID FchInitMidUsbEhci (IN VOID *FchDataPtr); +VOID FchInitLateUsbEhci (IN VOID *FchDataPtr); +VOID FchInitEnvUsbXhci (IN VOID *FchDataPtr); +VOID FchInitMidUsbXhci (IN VOID *FchDataPtr); +VOID FchInitLateUsbXhci (IN VOID *FchDataPtr); +VOID FchInitMidUsbOhci1 (IN VOID *FchDataPtr); +VOID FchInitMidUsbOhci2 (IN VOID *FchDataPtr); +VOID FchInitMidUsbOhci3 (IN VOID *FchDataPtr); +VOID FchInitMidUsbOhci4 (IN VOID *FchDataPtr); +VOID FchInitMidUsbEhci1 (IN FCH_DATA_BLOCK *FchDataPtr); +VOID FchInitMidUsbEhci2 (IN FCH_DATA_BLOCK *FchDataPtr); +VOID FchInitMidUsbEhci3 (IN FCH_DATA_BLOCK *FchDataPtr); +/// +/// Other Public Routines +/// +VOID FchSetUsbEnableReg (IN FCH_DATA_BLOCK *FchDataPtr); +VOID FchOhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr); +VOID FchEhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr); +VOID FchXhciInitBeforePciInit (IN FCH_DATA_BLOCK* FchDataPtr); +VOID FchXhciInitIndirectReg (IN AMD_CONFIG_PARAMS *StdHeader); +VOID FchInitLateUsbXhciProgram (IN VOID *FchDataPtr); +VOID FchXhciPowerSavingProgram (IN FCH_DATA_BLOCK* FchDataPtr); + + + +/// +/// Fch Sd Routines +/// +VOID FchInitEnvSd (IN VOID *FchDataPtr); +VOID FchInitMidSd (IN VOID *FchDataPtr); +VOID FchInitLateSd (IN VOID *FchDataPtr); + +/// +/// Other Public Routines +/// + +VOID FchInitEnvSdProgram (IN VOID *FchDataPtr); + +/// +/// Fch Spi Routines +/// +/// Pei Phase +/// +VOID FchInitResetSpi (IN VOID *FchDataPtr); +VOID FchInitResetLpc (IN VOID *FchDataPtr); +VOID FchInitResetLpcProgram (IN VOID *FchDataPtr); +/// +/// Dxe Phase +/// +VOID FchInitEnvSpi (IN VOID *FchDataPtr); +VOID FchInitMidSpi (IN VOID *FchDataPtr); +VOID FchInitLateSpi (IN VOID *FchDataPtr); +VOID FchInitEnvLpc (IN VOID *FchDataPtr); +VOID FchInitMidLpc (IN VOID *FchDataPtr); +VOID FchInitLateLpc (IN VOID *FchDataPtr); +VOID FchInitEnvLpcProgram (IN VOID *FchDataPtr); +/// +/// Other Public Routines +/// +VOID FchSpiUnlock (IN VOID *FchDataPtr); +VOID FchSpiLock (IN VOID *FchDataPtr); + +/*--------------------------- Documentation Pages ---------------------------*/ +VOID FchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader); +VOID CimFchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader); +VOID FchPciReset (IN AMD_CONFIG_PARAMS *StdHeader); +VOID OutPort80 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader); +VOID OutPort1080 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader); +VOID GetEfuseStatus (IN VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID TurnOffCG2 (OUT VOID); +VOID BackUpCG2 (OUT VOID); +VOID FchCopyMem (IN VOID* pDest, IN VOID* pSource, IN UINTN Length); +VOID* GetRomSigPtr (IN UINTN* RomSigPtr, IN AMD_CONFIG_PARAMS *StdHeader); +VOID RwXhciIndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); +VOID RwXhci0IndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); +VOID RwXhci1IndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); +VOID AcLossControl (IN UINT8 AcLossControlValue); +VOID FchVgaInit (OUT VOID); +VOID RecordFchConfigPtr (IN UINT32 FchConfigPtr); +VOID ValidateFchVariant (IN VOID *FchDataPtr); +VOID RecordSmiStatus (IN AMD_CONFIG_PARAMS *StdHeader); +BOOLEAN IsGCPU (IN VOID *FchDataPtr); +BOOLEAN IsExternalClockMode (IN VOID *FchDataPtr); +BOOLEAN IsLpcRom (OUT VOID); +VOID SbSleepTrapControl (IN BOOLEAN SleepTrap); + +#endif + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchLib.c new file mode 100644 index 0000000..dba0696 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchLib.c @@ -0,0 +1,629 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH IO access common routine + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_COMMON_FCHLIB_FILECODE + +/**< FchStall - Reserved */ +VOID +FchStall ( + IN UINT32 uSec, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT16 timerAddr; + UINT32 startTime; + UINT32 elapsedTime; + + LibAmdMemRead (AccessWidth16, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64), &timerAddr, StdHeader); + if ( timerAddr == 0 ) { + uSec = uSec / 2; + while ( uSec != 0 ) { + LibAmdIoRead (AccessWidth8, FCHOEM_IO_DELAY_PORT, (UINT8 *) (&startTime), StdHeader); + uSec--; + } + } else { + LibAmdIoRead (AccessWidth32, timerAddr, &startTime, StdHeader); + for ( ;; ) { + LibAmdIoRead (AccessWidth32, timerAddr, &elapsedTime, StdHeader); + if ( elapsedTime < startTime ) { + elapsedTime = elapsedTime + FCH_MAX_TIMER - startTime; + } else { + elapsedTime = elapsedTime - startTime; + } + if ( (elapsedTime * FCHOEM_ELAPSED_TIME_UNIT / FCHOEM_ELAPSED_TIME_DIVIDER) > uSec ) { + break; + } + } + } +} + +/**< cimFchStall - Reserved */ +VOID +CimFchStall ( + IN UINT32 uSec, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT16 timerAddr; + UINT32 startTime; + UINT32 elapsedTime; + + LibAmdMemRead (AccessWidth16, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64), &timerAddr, StdHeader); + if ( timerAddr == 0 ) { + uSec = uSec / 2; + while ( uSec != 0 ) { + LibAmdIoRead (AccessWidth8, FCHOEM_IO_DELAY_PORT, (UINT8*)&elapsedTime, StdHeader); + uSec--; + } + } else { + LibAmdIoRead (AccessWidth32, timerAddr, &startTime, StdHeader); + for ( ;; ) { + LibAmdIoRead (AccessWidth32, timerAddr, &elapsedTime, StdHeader); + if ( elapsedTime < startTime ) { + elapsedTime = elapsedTime + FCH_MAX_TIMER - startTime; + } else { + elapsedTime = elapsedTime - startTime; + } + if ( (elapsedTime * FCHOEM_ELAPSED_TIME_UNIT / FCHOEM_ELAPSED_TIME_DIVIDER) > uSec ) { + break; + } + } + } +} + +/**< FchReset - Reserved */ +VOID +FchPciReset ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 PciRstValue; + + PciRstValue = 0x06; + LibAmdIoWrite (AccessWidth8, FCH_PCIRST_BASE_IO, &PciRstValue, StdHeader); +} + +/**< outPort80 - Reserved */ +VOID +OutPort80 ( + IN UINT32 pcode, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + LibAmdIoWrite (AccessWidth8, FCHOEM_OUTPUT_DEBUG_PORT, &pcode, StdHeader); + return; +} + +/**< outPort1080 - Reserved */ +VOID +OutPort1080 ( + IN UINT32 pcode, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + LibAmdIoWrite (AccessWidth32, 0x1080, &pcode, StdHeader); + return; +} + +/**< FchCopyMem - Reserved */ +VOID +FchCopyMem ( + IN VOID* pDest, + IN VOID* pSource, + IN UINTN Length + ) +{ + UINTN i; + UINT8 *Ptr; + UINT8 *Source; + Ptr = (UINT8*)pDest; + Source = (UINT8*)pSource; + for (i = 0; i < Length; i++) { + *Ptr = *Source; + Source++; + Ptr++; + } +} + +/** GetRomSigPtr - Reserved **/ +VOID* +GetRomSigPtr ( + IN UINTN *RomSigPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 RomPtr; + UINT32 RomSig; + UINT16 MswAddr; + + *RomSigPtr = 0; + MswAddr = 0xFFF0; + do { + RomPtr = (MswAddr << 16) + FCH_ROMSIG_BASE_IO; + LibAmdMemRead (AccessWidth32, (UINT64) RomPtr, &RomSig, StdHeader); + if (RomSig == FCH_ROMSIG_SIGNATURE) { + *RomSigPtr = RomPtr; + break; + } + MswAddr <<= 1; + } while (MswAddr != 0xFE00); + return RomSigPtr; +} + +/** RwXhciIndReg - Reserved **/ +VOID +RwXhciIndReg ( + IN UINT32 Index, + IN UINT32 AndMask, + IN UINT32 OrMask, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 RevReg; + PCI_ADDR PciAddress; + + PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x48; + LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader); + PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x4C; + RevReg = ~AndMask; + LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader); + + PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x48; + LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader); + PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x4C; + RevReg = ~AndMask; + LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader); +} + +/** RwXhci0IndReg - Reserved **/ +VOID +RwXhci0IndReg ( + IN UINT32 Index, + IN UINT32 AndMask, + IN UINT32 OrMask, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 RevReg; + PCI_ADDR PciAddress; + + PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x48; + LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader); + PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x4C; + RevReg = ~AndMask; + LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader); +} + +/** RwXhci1IndReg - Reserved **/ +VOID +RwXhci1IndReg ( + IN UINT32 Index, + IN UINT32 AndMask, + IN UINT32 OrMask, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 RevReg; + PCI_ADDR PciAddress; + + PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x48; + LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader); + PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x4C; + RevReg = ~AndMask; + LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader); +} + +/** AcLossControl - Reserved **/ +VOID +AcLossControl ( + IN UINT8 AcLossControlValue + ) +{ + AcLossControlValue &= 0x03; + AcLossControlValue |= BIT2; + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5B, AccessWidth8, 0xF0, AcLossControlValue); +} + +/** RecordFchConfigPtr - Reserved **/ +VOID +RecordFchConfigPtr ( + IN UINT32 FchConfigPtr + ) +{ + RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x08, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 0) & 0xFF) ); + RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x09, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 8) & 0xFF) ); + RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0A, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 16) & 0xFF) ); + RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0B, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 24) & 0xFF) ); +} + +/** ReadAlink - Reserved **/ +UINT32 +ReadAlink ( + IN UINT32 Index, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Data; + LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader); + LibAmdIoRead (AccessWidth32, ALINK_ACCESS_DATA, &Data, StdHeader); + //Clear Index + Index = 0; + LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader); + return Data; +} + +/** WriteAlink - Reserved **/ +VOID +WriteAlink ( + IN UINT32 Index, + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader); + LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_DATA, &Data, StdHeader); + //Clear Index + Index = 0; + LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader); +} + +/** RwAlink - Reserved **/ +VOID +RwAlink ( + IN UINT32 Index, + IN UINT32 AndMask, + IN UINT32 OrMask, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 AccessType; + + AccessType = Index & 0xE0000000; + if (AccessType == (AXINDC << 29)) { + WriteAlink ((FCH_AX_INDXC_REG30 | AccessType), Index & 0x1FFFFFFF, StdHeader); + Index = FCH_AX_DATAC_REG34 | AccessType; + } else if (AccessType == (AXINDP << 29)) { + WriteAlink ((FCH_AX_INDXP_REG38 | AccessType), Index & 0x1FFFFFFF, StdHeader); + Index = FCH_AX_DATAP_REG3C | AccessType; + } + WriteAlink (Index, (ReadAlink (Index, StdHeader) & AndMask) | OrMask, StdHeader); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Read PMIO + * + * + * + * @param[in] Address - PMIO Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Read Data Buffer + * @param[in] StdHeader + * + */ +VOID +ReadPmio ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + + OpFlag = OpFlag & 0x7f; + OpFlag = 1 << (OpFlag - 1); + for (i = 0; i < OpFlag; i++) { + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD6, &Address, StdHeader); + Address++; + LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD7, (UINT8 *)Value + i, StdHeader); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Write PMIO + * + * + * + * @param[in] Address - PMIO Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Write Data Buffer + * @param[in] StdHeader + * + */ +VOID +WritePmio ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + + OpFlag = OpFlag & 0x7f; + OpFlag = 1 << (OpFlag - 1); + for (i = 0; i < OpFlag; i++) { + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD6, &Address, StdHeader); + Address++; + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD7, (UINT8 *)Value + i, StdHeader); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * RwPmio - Read/Write PMIO + * + * + * + * @param[in] Address - PMIO Offset value + * @param[in] OpFlag - Access sizes + * @param[in] AndMask - Data And Mask 32 bits + * @param[in] OrMask - Data OR Mask 32 bits + * @param[in] StdHeader + * + */ +VOID +RwPmio ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN UINT32 AndMask, + IN UINT32 OrMask, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Result; + + ReadPmio (Address, OpFlag, &Result, StdHeader); + Result = (Result & AndMask) | OrMask; + WritePmio (Address, OpFlag, &Result, StdHeader); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Read PMIO2 + * + * + * + * @param[in] Address - PMIO2 Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Read Data Buffer + * @param[in] StdHeader + * + */ +VOID +ReadPmio2 ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + + OpFlag = OpFlag & 0x7f; + OpFlag = 1 << (OpFlag - 1); + for ( i = 0; i < OpFlag; i++ ) { + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD0, &Address, StdHeader); + Address++; + LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD1, (UINT8 *) Value + i, StdHeader); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Write PMIO 2 + * + * + * + * @param[in] Address - PMIO2 Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Write Data Buffer + * @param[in] StdHeader + * + */ +VOID +WritePmio2 ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + + OpFlag = OpFlag & 0x7f; + OpFlag = 1 << (OpFlag - 1); + + for ( i = 0; i < OpFlag; i++ ) { + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD0, &Address, StdHeader); + Address++; + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD1, (UINT8 *) Value + i, StdHeader); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * RwPmio2 - Read/Write PMIO2 + * + * + * + * @param[in] Address - PMIO2 Offset value + * @param[in] OpFlag - Access sizes + * @param[in] AndMask - Data And Mask 32 bits + * @param[in] OrMask - Data OR Mask 32 bits + * @param[in] StdHeader + * + */ +VOID +RwPmio2 ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN UINT32 AndMask, + IN UINT32 OrMask, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Result; + + ReadPmio2 (Address, OpFlag, &Result, StdHeader); + Result = (Result & AndMask) | OrMask; + WritePmio2 (Address, OpFlag, &Result, StdHeader); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Read BIOSRAM + * + * + * + * @param[in] Address - BIOSRAM Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Read Data Buffer + * @param[in] StdHeader + * + */ +VOID +ReadBiosram ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + + OpFlag = OpFlag & 0x7f; + OpFlag = 1 << (OpFlag - 1); + for (i = 0; i < OpFlag; i++) { + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD4, &Address, StdHeader); + Address++; + LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD5, (UINT8 *)Value + i, StdHeader); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Write BIOSRAM + * + * + * + * @param[in] Address - BIOSRAM Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Write Data Buffer + * @param[in] StdHeader + * + */ +VOID +WriteBiosram ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + + OpFlag = OpFlag & 0x7f; + OpFlag = 1 << (OpFlag - 1); + for (i = 0; i < OpFlag; i++) { + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD4, &Address, StdHeader); + Address++; + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD5, (UINT8 *)Value + i, StdHeader); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Record SMI Status + * + * + * @param[in] StdHeader + * + */ +VOID +RecordSmiStatus ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINTN Index; + UINT8 SwSmiValue; + + ACPIMMIO8 (0xfed80320) |= 0x01; + for ( Index = 0; Index < 20; Index++ ) { + ACPIMMIO8 (0xfed10020 + Index) = ACPIMMIO8 (0xfed80280 + Index); + } + LibAmdIoRead (AccessWidth8, 0xB0, &SwSmiValue, StdHeader); + ACPIMMIO8 (0xfed10040) = SwSmiValue; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchPeLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchPeLib.c new file mode 100644 index 0000000..7cd64b7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchPeLib.c @@ -0,0 +1,351 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH IO access common routine + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ + +#include "FchPlatform.h" +#define FILECODE PROC_FCH_COMMON_FCHPELIB_FILECODE + +/*----------------------------------------------------------------------------------------*/ +/** + * ProgramPciByteTable - Program PCI register by table (8 bits data) + * + * + * + * @param[in] pPciByteTable - Table data pointer + * @param[in] dwTableSize - Table length + * @param[in] StdHeader + * + */ +VOID +ProgramPciByteTable ( + IN REG8_MASK *pPciByteTable, + IN UINT16 dwTableSize, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + UINT8 dbBusNo; + UINT8 dbDevFnNo; + UINT8 Or8; + UINT8 Mask8; + PCI_ADDR PciAddress; + + dbBusNo = pPciByteTable->RegIndex; + dbDevFnNo = pPciByteTable->AndMask; + pPciByteTable++; + + for ( i = 1; i < dwTableSize; i++ ) { + if ( (pPciByteTable->RegIndex == 0xFF) && (pPciByteTable->AndMask == 0xFF) && (pPciByteTable->OrMask == 0xFF) ) { + pPciByteTable++; + dbBusNo = pPciByteTable->RegIndex; + dbDevFnNo = pPciByteTable->AndMask; + pPciByteTable++; + i++; + } else { + PciAddress.AddressValue = (dbBusNo << 20) + (dbDevFnNo << 12) + pPciByteTable->RegIndex; + Or8 = pPciByteTable->OrMask; + Mask8 = ~pPciByteTable->AndMask; + LibAmdPciRMW (AccessWidth8, PciAddress, &Or8, &Mask8, StdHeader); + pPciByteTable++; + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * ProgramFchAcpiMmioTbl - Program FCH ACPI MMIO register by table (8 bits data) + * + * + * + * @param[in] pAcpiTbl - Table data pointer + * @param[in] StdHeader + * + */ +VOID +ProgramFchAcpiMmioTbl ( + IN ACPI_REG_WRITE *pAcpiTbl, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + UINT8 Or8; + UINT8 Mask8; + UINT32 ddtempVar; + + if (pAcpiTbl != NULL) { + if ((pAcpiTbl->MmioReg == 0) && (pAcpiTbl->MmioBase == 0) && (pAcpiTbl->DataAndMask == 0xB0) && (pAcpiTbl->DataOrMask == 0xAC)) { + // Signature Checking + pAcpiTbl++; + for ( i = 1; pAcpiTbl->MmioBase < 0x1D; i++ ) { + ddtempVar = ACPI_MMIO_BASE | (pAcpiTbl->MmioBase) << 8 | pAcpiTbl->MmioReg; + Or8 = pAcpiTbl->DataOrMask; + Mask8 = ~pAcpiTbl->DataAndMask; + LibAmdMemRMW (AccessWidth8, (UINT64) ddtempVar, &Or8, &Mask8, StdHeader); + pAcpiTbl++; + } + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * ProgramFchSciMapTbl - Program FCH SCI Map table (8 bits data) + * + * + * + * @param[in] pSciMapTbl - Table data pointer + * @param[in] FchResetDataBlock + * + */ +VOID +ProgramFchSciMapTbl ( + IN SCI_MAP_CONTROL *pSciMapTbl, + IN FCH_RESET_DATA_BLOCK *FchResetDataBlock + ) +{ + AMD_CONFIG_PARAMS *StdHeader; + + UINT32 ddtempVar; + StdHeader = FchResetDataBlock->StdHeader; + + if (pSciMapTbl != NULL) { + while (pSciMapTbl->InputPin != 0xFF) { + if ((pSciMapTbl->InputPin >= 0x40) && (pSciMapTbl->InputPin < 0x80) && (pSciMapTbl->GpeMap < 0x20)) { + ddtempVar = ACPI_MMIO_BASE | SMI_BASE | pSciMapTbl->InputPin; + if (((pSciMapTbl->InputPin == 0x78 ) && (FchResetDataBlock->FchReset.Xhci0Enable == 0)) || \ + ((pSciMapTbl->InputPin == 0x79 ) && (FchResetDataBlock->FchReset.Xhci1Enable == 0))) { + } else { + LibAmdMemWrite (AccessWidth8, (UINT64) ddtempVar, &pSciMapTbl->GpeMap, StdHeader); + } + } else { + //Assert Warning "SCI map is invalid" + } + pSciMapTbl++; + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * ProgramFchGpioTbl - Program FCH Gpio table (8 bits data) + * + * + * + * @param[in] pGpioTbl - Table data pointer + * @param[in] FchResetDataBlock + * + */ +VOID +ProgramFchGpioTbl ( + IN GPIO_CONTROL *pGpioTbl, + IN FCH_RESET_DATA_BLOCK *FchResetDataBlock + ) +{ + AMD_CONFIG_PARAMS *StdHeader; + + UINT32 ddtempVar; + StdHeader = FchResetDataBlock->StdHeader; + + if (pGpioTbl != NULL) { + while (pGpioTbl->GpioPin != 0xFF) { + ddtempVar = ACPI_MMIO_BASE | IOMUX_BASE | pGpioTbl->GpioPin; + LibAmdMemWrite (AccessWidth8, (UINT64) ddtempVar, &pGpioTbl->PinFunction, StdHeader); + ddtempVar = ACPI_MMIO_BASE | GPIO_BASE | pGpioTbl->GpioPin; + LibAmdMemWrite (AccessWidth8, (UINT64) ddtempVar, &pGpioTbl->CfgByte, StdHeader); + pGpioTbl++; + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * ProgramSataPhyTbl - Program FCH Sata Phy table (8 bits data) + * + * + * + * @param[in] pSataPhyTbl - Table data pointer + * @param[in] FchResetDataBlock + * + */ +VOID +ProgramFchSataPhyTbl ( + IN SATA_PHY_CONTROL *pSataPhyTbl, + IN FCH_RESET_DATA_BLOCK *FchResetDataBlock + ) +{ + AMD_CONFIG_PARAMS *StdHeader; + + //UINT32 ddtempVar; + StdHeader = FchResetDataBlock->StdHeader; + + if (pSataPhyTbl != NULL) { + while (pSataPhyTbl->PhyData != 0xFFFFFFFF) { + //to be implemented + pSataPhyTbl++; + } + } +} + +/** + * GetChipSysMode - Get Chip status + * + * + * @param[in] Value - Return Chip strap status + * StrapStatus [15.0] - Hudson-2 chip Strap Status + * @li <b>0001</b> - Not USED FWH + * @li <b>0002</b> - Not USED LPC ROM + * @li <b>0004</b> - EC enabled + * @li <b>0008</b> - Reserved + * @li <b>0010</b> - Internal Clock mode + * @param[in] StdHeader + * + */ +VOID +GetChipSysMode ( + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + LibAmdMemRead (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80), Value, StdHeader); +} + +/** + * IsImcEnabled - Is IMC Enabled + * @retval TRUE for IMC Enabled; FALSE for IMC Disabled + */ +BOOLEAN +IsImcEnabled ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 dbSysConfig; + GetChipSysMode (&dbSysConfig, StdHeader); + if (dbSysConfig & ChipSysEcEnable) { + return TRUE; + } else { + return FALSE; + } +} + + +/** + * GetEfuseStatue - Get Efuse status + * + * + * @param[in] Value - Return Chip strap status + * @param[in] StdHeader + * + */ +VOID +GetEfuseStatus ( + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 Or8; + UINT8 Mask8; + + Or8 = BIT5; + Mask8 = BIT5; + LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8), &Or8, &Mask8, StdHeader); + LibAmdMemWrite (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + 0xD8 ), Value, StdHeader); + LibAmdMemRead (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + 0xD8 + 1), Value, StdHeader); + Or8 = 0; + Mask8 = BIT5; + LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8), &Or8, &Mask8, StdHeader); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * SbSleepTrapControl - SB Sleep Trap Control + * + * + * + * @param[in] SleepTrap - Whether sleep trap is enabled + * + */ +VOID +SbSleepTrapControl ( + IN BOOLEAN SleepTrap + ) +{ + if (SleepTrap) { + ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) &= ~(BIT2 + BIT3); + ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) |= BIT2; + + ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xBE ) &= ~ (BIT5); + ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) &= ~ (BIT0 + BIT1); + ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) |= BIT1; + } else { + ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xBE ) |= BIT5; + ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) &= ~ (BIT0 + BIT1); + ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) |= BIT0; + + ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) &= ~(BIT2 + BIT3); + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/MemLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/MemLib.c new file mode 100644 index 0000000..d80f74e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/MemLib.c @@ -0,0 +1,171 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH memory access lib + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Ids.h" +#define FILECODE PROC_FCH_COMMON_MEMLIB_FILECODE + + +/** + * ReadMem - Read FCH BAR Memory + * + * @param[in] Address - Memory BAR address + * @param[in] OpFlag - Access width + * @param[in] *ValuePtr - In/Out value pointer + * + */ +VOID +ReadMem ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN VOID *ValuePtr + ) +{ + OpFlag = OpFlag & 0x7f; + + switch ( OpFlag ) { + case AccessWidth8: + *((UINT8*)ValuePtr) = *((UINT8*) ((UINTN)Address)); + break; + + case AccessWidth16: + *((UINT16*)ValuePtr) = *((UINT16*) ((UINTN)Address)); + break; + + case AccessWidth32: + *((UINT32*)ValuePtr) = *((UINT32*) ((UINTN)Address)); + break; + + default: + ASSERT (FALSE); + break; + } +} + +/** + * WriteMem - Write FCH BAR Memory + * + * @param[in] Address - Memory BAR address + * @param[in] OpFlag - Access width + * @param[in] *ValuePtr - In/Out Value pointer + * + */ +VOID +WriteMem ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN VOID *ValuePtr + ) +{ + OpFlag = OpFlag & 0x7f; + + switch ( OpFlag ) { + case AccessWidth8 : + *((UINT8*) ((UINTN)Address)) = *((UINT8*)ValuePtr); + break; + + case AccessWidth16: + *((UINT16*) ((UINTN)Address)) = *((UINT16*)ValuePtr); + break; + + case AccessWidth32: + *((UINT32*) ((UINTN)Address)) = *((UINT32*)ValuePtr); + break; + + default: + ASSERT (FALSE); + break; + } +} + +/** + * RwMem - Read & Write FCH BAR Memory + * + * @param[in] Address - Memory BAR address + * @param[in] OpFlag - Access width + * @param[in] Mask - Mask Value of data + * @param[in] Data - Write data + * + */ +VOID +RwMem ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN UINT32 Mask, + IN UINT32 Data + ) +{ + UINT32 Result; + + ReadMem (Address, OpFlag, &Result); + Result = (Result & Mask) | Data; + WriteMem (Address, OpFlag, &Result); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/PciLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/PciLib.c new file mode 100644 index 0000000..f63710e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/PciLib.c @@ -0,0 +1,121 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH PCI access lib + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_COMMON_PCILIB_FILECODE + +VOID +ReadPci ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN VOID* Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + + PciAddress.AddressValue = ((Address >> 4) & ~0xFFF) + (Address & 0xFFF); + LibAmdPciRead ((ACCESS_WIDTH) OpFlag, PciAddress, Value, StdHeader); +} + + +VOID +WritePci ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + + PciAddress.AddressValue = ((Address >> 4) & ~0xFFF) + (Address & 0xFFF); + LibAmdPciWrite ((ACCESS_WIDTH) OpFlag, PciAddress, Value, StdHeader); +} + + +VOID +RwPci ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN UINT32 Mask, + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + UINT32 rMask; + + PciAddress.AddressValue = ((Address >> 4) & ~0xFFF) + (Address & 0xFFF); + rMask = ~Mask; + LibAmdPciRMW ((ACCESS_WIDTH) OpFlag, PciAddress, &Data, &rMask, StdHeader); +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Fch.h b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Fch.h new file mode 100644 index 0000000..963d96d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Fch.h @@ -0,0 +1,1653 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH registers definition + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 64988 $ @e $Date: 2012-02-06 03:07:17 -0600 (Mon, 06 Feb 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#define FCH_REVISION "0.0.5.0" +#define FCH_ID "FCH_A05" +#define FCH_VERSION 0x0000 + +/** + * @page fchinitguide FCH implement phase in AGESA + * + * FCH provides below access to supported FCH service functions + * and data. + * - @subpage fchreset "FCH_INIT_RESET" + * - @subpage fchenv "FCH_INIT_ENV" + * - @subpage fchmid "FCH_INIT_MID" + * - @subpage fchlate "FCH_INIT_LATE" + * - @subpage fchs3early "FCH_INIT_S3_EARLY_RESTORE" + * - @subpage fchs3late "FCH_INIT_S3_LATE_RESTORE" + * - @subpage fchsmm "FCH_SMM_SERVICE" + * - @subpage fchsmmacpion "FCH_SMM_ACPION" + */ + +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page fchreset FCH_INIT_RESET + * @section FCH_INIT_RESET Interface Call + * @par + * Initialize structure referenced by FCH_RESET_DATA_BLOCK to default recommended value. + * @subsection FCH_INIT_RESET_CallIn Call Prototype + * @par + * AGESA_STATUS FchInitReset (IN AMD_RESET_PARAMS *ResetParams); + * @subsection FCH_INIT_RESET_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection FCH_INIT_RESET_Config Prepare for Configuration Data. + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSmbus0BaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSmbus1BaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSioPmeBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgWatchDogTimerBase </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgGecShadowRomBase </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSpiRomBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPm1EvtBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPm1CntBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPmTmrBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgCpuControlBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiGpe0BlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSmiCmdPortAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPmaCntBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_RESET_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_RESET_INTERFACE::IdeEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * </TABLE> + * + */ + +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page fchenv FCH_INIT_ENV + * @section FCH_INIT_ENV Interface Call + * @par + * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value. + * @subsection FCH_INIT_ENV_CallIn Call Prototype + * @par + * AGESA_STATUS FchInitEnv (IN AMD_ENV_PARAMS *EnvParams); + * @subsection FCH_INIT_ENV_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection FCH_INIT_ENV_Config Prepare for Configuration Data. + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SdConfig </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::IrConfig </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataIdeMode </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci1Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci2Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci3Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci4Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::XhciSwitch </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * </TABLE> + * + */ + +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page fchmid FCH_INIT_MID + * @section FCH_INIT_MID Interface Call + * @par + * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value. + * @subsection FCH_INIT_MID_CallIn Call Prototype + * @par + * AGESA_STATUS FchInitMid (IN AMD_MID_PARAMS *MidParams); + * @subsection FCH_INIT_MID_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection FCH_INIT_MID_Config Prepare for Configuration Data. + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::IdeEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::XhciSwitch </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * + */ + +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @section FCH_INIT_LATE Interface Call + * @par + * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value. + * @subsection FCH_INIT_LATE_CallIn Call Prototype + * @par + * AGESA_STATUS FchInitLate (IN AMD_S3SAVE_PARAMS *LateParams); + * @subsection FCH_INIT_LATE_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection FCH_INIT_LATE_Config Prepare for Configuration Data. + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::XhciSwitch </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSpiRomBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * </TABLE> + * + */ + +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page fchs3early FCH_INIT_S3_EARLY_RESTORE + * @section FCH_INIT_S3_EARLY_RESTORE Interface Call + * @par + * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value. + * @subsection FCH_INIT_S3_EARLY_RESTORE_CallIn Call Prototype + * @par + * VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); + * @subsection FCH_INIT_S3_EARLY_RESTORE_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection FCH_INIT_S3_EARLY_RESTORE_Config Prepare for Configuration Data. + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SdConfig </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::IrConfig </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataIdeMode </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci1Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci2Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci3Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci4Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::XhciSwitch </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * </TABLE> + * + */ + +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page fchs3late FCH_INIT_S3_LATE_RESTORE + * @section FCH_INIT_S3_LATE_RESTORE Interface Call + * @par + * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value. + * @subsection FCH_INIT_S3_LATE_RESTORE_CallIn Call Prototype + * @par + * VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); + * @subsection FCH_INIT_S3_LATE_RESTORE_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection FCH_INIT_S3_LATE_RESTORE_Config Prepare for Configuration Data. + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::IdeEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::XhciSwitch </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSpiRomBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * </TABLE> + * + */ + +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page fchsmm FCH_SMM_SERVICE + * @section FCH_SMM_SERVICE Interface Call + * Initialize structure referenced by FCHCFG to default recommended value. + * @subsection FCH_SMM_SERVICE_CallIn Call Prototype + * @par + * FchSmmService ((FCHCFG*)pConfig) (Followed PH Interface) + * @subsection FCH_SMM_SERVICE_CallID Service ID + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> FCH_SMM_SERVICE --> 0x00010060 </TD></TR> + * </TABLE> + * @subsection FCH_SMM_SERVICE_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection FCH_SMM_SERVICE_Config Prepare for Configuration Data. + * @par + * Not necessary on current implementation + * + */ +#define FCH_SMM_SERVICE 0x00010060ul +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page fchsmmacpion FCH_SMM_ACPION + * @section FCH_SMM_ACPION Interface Call + * Initialize structure referenced by FCHCFG to default recommended value. + * @subsection FCH_SMM_ACPION_CallIn Call Prototype + * @par + * FchSmmAcpiOn ((FCHCFG*)pConfig) (Followed PH Interface) + * @subsection FCH_SMM_ACPION_CallID Service ID + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> FCH_SMM_ACPION --> 0x00010061 </TD></TR> + * </TABLE> + * @subsection FCH_SMM_ACPION_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection FCH_SMM_ACPION_Config Prepare for Configuration Data. + * @par + * Not necessary on current implementation + * + */ +#define FCH_SMM_ACPION 0x00010061ul + +#ifndef OEM_CALLBACK_BASE + #define OEM_CALLBACK_BASE 0x00010100ul +#endif + +//0x00 - 0x0F callback functions are reserved for bootblock +#define SATA_PHY_PROGRAMMING OEM_CALLBACK_BASE + 0x10 +#define PULL_UP_PULL_DOWN_SETTINGS OEM_CALLBACK_BASE + 0x20 +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page CB_SBGPP_RESET_ASSERT_Page CB_SBGPP_RESET_ASSERT + * @section CB_SBGPP_RESET_ASSERT Interface Call + * Initialize structure referenced by FCHCFG to default recommended value. + * @subsection CB_SBGPP_RESET_ASSERT_CallID Service ID + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> CB_SBGPP_RESET_ASSERT --> 0x00010130 </TD></TR> + * </TABLE> + * @subsection CB_SBGPP_RESET_ASSERT_Config Prepare for Configuration Data. + * @par + * Not necessary on current implementation + * + */ +#define CB_SBGPP_RESET_ASSERT OEM_CALLBACK_BASE + 0x30 +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page CB_SBGPP_RESET_DEASSERT_Page CB_SBGPP_RESET_DEASSERT + * @section CB_SBGPP_RESET_DEASSERT Interface Call + * Initialize structure referenced by FCHCFG to default recommended value. + * @subsection CB_SBGPP_RESET_DEASSERT _CallID Service ID + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> CB_SBGPP_RESET_DEASSERT --> 0x00010131 </TD></TR> + * </TABLE> + * @subsection CB_SBGPP_RESET_DEASSERT _Config Prepare for Configuration Data. + * @par + * Not necessary on current implementation + * + */ +#define CB_SBGPP_RESET_DEASSERT OEM_CALLBACK_BASE + 0x31 + +#define CFG_ADDR_PORT 0xCF8 +#define CFG_DATA_PORT 0xCFC + +#define ALINK_ACCESS_INDEX 0x0CD8 +#define ALINK_ACCESS_DATA ALINK_ACCESS_INDEX + 4 + +/*------------------------------------------------------------------ +; I/O Base Address - Should be set by host BIOS +;------------------------------------------------------------------ */ +#define DELAY_PORT 0x0E0 + +#define FCH_8259_CONTROL_REG_MASTER 0x20 +#define FCH_8259_MASK_REG_MASTER 0x21 + +/*------------------------------------------------------------------ +; DEBUG_PORT = 8-bit I/O Port Address for POST Code Display +;------------------------------------------------------------------ */ +// ASIC VendorID and DeviceIDs +#define ATI_VID 0x1002 +#define AMD_FCH_VID 0x1022 +#define FCH_DEVICE_ID 0x780B +#define FCH_SATA_VID AMD_FCH_VID // Dev 17 Func 0 +#define FCH_SATA_DID 0x7800 +#define FCH_SATA_AHCI_DID 0x7801 +#define FCH_SATA_RAID_DID 0x7802 +#define FCH_SATA_RAID5_DID 0x7803 +#define FCH_SATA_AMDAHCI_DID 0x7804 +#define FCH_USB_OHCI_VID AMD_FCH_VID // Dev 18 Func 0, Dev 19 Func 0 +#define FCH_USB_OHCI_DID 0x7807 +#define FCH_USB_EHCI_VID AMD_FCH_VID // Dev 18 Func 2, Dev 19 Func 2 +#define FCH_USB_EHCI_DID 0x7808 +#define FCH_USB_XHCI_VID AMD_FCH_VID // Dev 10 Func 0, Dev 10 Func 1 +#define FCH_USB_XHCI_DID 0x7812 +#define FCH_SMBUS_VID AMD_FCH_VID // Dev 20 Func 0 +#define FCH_SMBUS_DID 0x780B +#define FCH_IDE_VID AMD_FCH_VID // Dev 20 Func 1 +#define FCH_IDE_DID 0x780C +#define FCH_LPC_VID AMD_FCH_VID // Dev 20 Func 3 +#define FCH_LPC_DID 0x780E +#define FCH_PCIB_VID AMD_FCH_VID // Dev 20 Func 4 +#define FCH_PCIB_DID 0x780F +#define FCH_USB_OHCIF_VID AMD_FCH_VID // dev 20 Func 5 +#define FCH_USB_OHCIF_DID 0x7809 +#define FCH_NIC_VID 0x14E4 // Dev 20 Func 6 +#define FCH_NIC_DID 0x1699 +#define FCH_SD_VID AMD_FCH_VID // Dev 20 Func 7 +#define FCH_SD_DID 0x7806 + +//FCH Variant +#define FCH_Variant_EFUSE_LOCATION 0x1E // EFUSE bit 240-247 + +#define FCH_M2 0x01 +#define FCH_M3 0x03 +#define FCH_M3T 0x07 +#define FCH_D2 0x0F +#define FCH_D3 0x1F +#define FCH_D4 0x3F + + +//Misc +#define R_FCH_ACPI_PM1_STATUS 0x00 +#define R_FCH_ACPI_PM1_ENABLE 0x02 +#define R_FCH_ACPI_PM_CONTROL 0x04 +#define R_FCH_ACPI_EVENT_STATUS 0x20 +#define R_FCH_ACPI_EVENT_ENABLE 0x24 +#define R_FCH_PM_ACPI_PMA_CNT_BLK_LO 0x2C + +// ACPI Sleep Type +#define ACPI_SLPTYP_S0 0 +#define ACPI_SLPTYP_S1 1 +#define ACPI_SLPTYP_S3 3 +#define ACPI_SLPTYP_S4 4 +#define ACPI_SLPTYP_S5 5 + +//#define SATA_BUS_DEV_FUN_FPGA 0x228 +#define SATA_BUS_DEV_FUN ((0x11 << 3) + 0) +#define FCH_SATA1_BUS 0 +#define FCH_SATA1_DEV 17 +#define FCH_SATA1_FUNC 0 + +#define FC_BUS_DEV_FUN ((0x11 << 3) + 1) +#define FCH_XHCI_BUS 0 +#define FCH_XHCI_DEV 16 +#define FCH_XHCI_FUNC 0 +#define USB_XHCI_BUS_DEV_FUN ((FCH_XHCI_DEV << 3) + FCH_XHCI_FUNC) +#define FCH_XHCI1_BUS 0 +#define FCH_XHCI1_DEV 16 +#define FCH_XHCI1_FUNC 1 +#define USB_XHCI1_BUS_DEV_FUN ((FCH_XHCI1_DEV << 3) + FCH_XHCI1_FUNC) +#define USB1_OHCI_BUS_DEV_FUN ((0x12 << 3) + 0) // PORT 0-4 +#define FCH_OHCI1_BUS 0 +#define FCH_OHCI1_DEV 18 +#define FCH_OHCI1_FUNC 0 +#define USB2_OHCI_BUS_DEV_FUN ((0x13 << 3) + 0) // PORT 5-9 +#define FCH_OHCI2_BUS 0 +#define FCH_OHCI2_DEV 19 +#define FCH_OHCI2_FUNC 0 +#define USB3_OHCI_BUS_DEV_FUN ((0x16 << 3) + 0) // PORT 10-13 +#define FCH_OHCI3_BUS 0 +#define FCH_OHCI3_DEV 22 +#define FCH_OHCI3_FUNC 0 +#define USB1_EHCI_BUS_DEV_FUN ((0x12 << 3) + 2) // PORT 0-4 +#define FCH_EHCI1_BUS 0 +#define FCH_EHCI1_DEV 18 +#define FCH_EHCI1_FUNC 2 +#define USB2_EHCI_BUS_DEV_FUN ((0x13 << 3) + 2) // PORT 5-9 +#define FCH_EHCI2_BUS 0 +#define FCH_EHCI2_DEV 19 +#define FCH_EHCI2_FUNC 2 +#define USB3_EHCI_BUS_DEV_FUN ((0x16 << 3) + 2) // PORT 10-13 +#define FCH_EHCI3_BUS 0 +#define FCH_EHCI3_DEV 22 +#define FCH_EHCI3_FUNC 2 +#define SMBUS_BUS_DEV_FUN ((0x14 << 3) + 0) +#define FCH_ISA_BUS 0 +#define FCH_ISA_DEV 20 +#define FCH_ISA_FUNC 0 +#define IDE_BUS_DEV_FUN ((0x14 << 3) + 1) +#define FCH_IDE_BUS 0 +#define FCH_IDE_DEV 20 +#define FCH_IDE_FUNC 1 +#define LPC_BUS_DEV_FUN ((0x14 << 3) + 3) +#define FCH_LPC_BUS 0 +#define FCH_LPC_DEV 20 +#define FCH_LPC_FUNC 3 +#define PCIB_BUS_DEV_FUN ((0x14 << 3) + 4) // P2P in SB700 +#define FCH_PCI_BUS 0 +#define FCH_PCI_DEV 20 +#define FCH_PCI_FUNC 4 +#define USB4_OHCI_BUS_DEV_FUN ((0x14 << 3) + 5) // PORT FL0 - FL1 +#define FCH_OHCI4_BUS 0 +#define FCH_OHCI4_DEV 20 +#define FCH_OHCI4_FUNC 5 +//Gigabyte Ethernet Controller +#define GEC_BUS_DEV_FUN ((0x14 << 3) + 6) +#define FCH_GBEC_BUS 0 +#define FCH_GBEC_DEV 20 +#define FCH_GBEC_FUNC 6 + +#define SD_BUS_DEV_FUN ((0x14 << 3) + 7) // SD Controller +#define SD_PCI_BUS 0 +#define SD_PCI_DEV 20 +#define SD_PCI_FUNC 7 +#define SD_PCI_REG10 0x10 +#define SD_PCI_REG2C 0x2C +#define SD_PCI_REGA4 0xA4 +#define SD_PCI_REGA8 0xA8 +#define SD_PCI_REGAC 0xAC +#define SD_PCI_REGB0 0xB0 + + +#define FCH_GPP_BUS 0 +#define FCH_GPP_DEV 21 +#define FCH_GPP_FUNC 0 +#define GPP0_BUS_DEV_FUN ((0x15 << 3) + 0) // GPP P2P bridge PORT0 +#define GPP1_BUS_DEV_FUN ((0x15 << 3) + 1) // GPP P2P bridge PORT1 +#define GPP2_BUS_DEV_FUN ((0x15 << 3) + 2) // GPP P2P bridge PORT2 +#define GPP3_BUS_DEV_FUN ((0x15 << 3) + 3) // GPP P2P bridge PORT3 + +#define ACPI_MMIO_BASE 0xFED80000ul +#define FCH_CFG_BASE 0x000 // DWORD +#define GPIO_BASE 0x100 // BYTE +#define SMI_BASE 0x200 // DWORD +#define PMIO_BASE 0x300 // DWORD +#define PMIO2_BASE 0x400 // BYTE +#define BIOS_RAM_BASE 0x500 // BYTE +#define CMOS_RAM_BASE 0x600 // BYTE +#define CMOS_BASE 0x700 // BYTE +#define ASF_BASE 0x900 // DWORD +#define SMBUS_BASE 0xA00 // DWORD +#define WATCHDOG_BASE 0xB00 // +#define HPET_BASE 0xC00 // DWORD +#define IOMUX_BASE 0xD00 // BYTE +#define MISC_BASE 0xE00 +#define SERIAL_DEBUG_BASE 0x1000 +#define GFX_DAC_BASE 0x1400 +#define CEC_BASE 0x1800 +#define XHCI_BASE 0x1C00 + + +// RegSpace field (AB_INDEX[31:29] +#define AXINDC 0 // AXINDC +#define AXINDP 2 // AXINDP +#define ABCFG 6 // ABCFG +#define AXCFG 4 // AXCFG +#define RCINDXC 1 // PCIEIND +#define RCINDXP 3 // PCIEIND_P + +#define GPP_DEV_NUM 21 // +#define MAX_GPP_PORTS 4 + +#define PCIE_FORCE_GEN1_EFUSE_LOCATION 0x14 // EFUSE bit 160 +// +// ABCFG Registers +// +#define FCH_ABCFG_REG00 0x00 // VENDOR ID +#define FCH_ABCFG_REG08 0x08 // REVISION ID +#define FCH_ABCFG_REG40 0x40 // BL_EVENTCNT0LO +#define FCH_ABCFG_REG44 0x44 // BL_EVENTCNT1LO +#define FCH_ABCFG_REG48 0x48 // BL_EVENTCNTSEL +#define FCH_ABCFG_REG4A 0x4A // BL_EVENTCNT0HI +#define FCH_ABCFG_REG4B 0x4B // BL_EVENTCNT1HI +#define FCH_ABCFG_REG4C 0x4C // BL_EVENTCNTCTL +#define FCH_ABCFG_REG50 0x50 // MISCCTL_50 +#define FCH_ABCFG_REG54 0x54 // MISCCTL_54 +#define FCH_ABCFG_REG58 0x58 // BL RAB CONTROL + +#define FCH_ABCFG_REG60 0x60 // LINKWIDTH_CTL +#define FCH_ABCFG_REG64 0x64 // LINKWIDTH_UP_INTERVAL +#define FCH_ABCFG_REG68 0x68 // LINKWIDTH_DN_INVERVAL +#define FCH_ABCFG_REG6C 0x6C // LINKWIDTH_UPSTREAM_DWORDS +#define FCH_ABCFG_REG70 0x70 // LINKWIDTH_DOWNSTREAM_DWORDS +#define FCH_ABCFG_REG74 0x74 // LINKWIDTH_THRESHOLD_INCREASE +#define FCH_ABCFG_REG78 0x78 // LINKWIDTH_THRESHOLD_DECREASE + +#define FCH_ABCFG_REG80 0x80 // BL DMA PREFETCH CONTROL +#define FCH_ABCFG_REG88 0x88 // +#define FCH_ABCFG_REG90 0x90 // BIF CONTROL 0 +#define FCH_ABCFG_REG94 0x94 // MSI CONTROL +#define FCH_ABCFG_REG98 0x98 // BIF CONTROL 1 +#define FCH_ABCFG_REG9C 0x9C // MISCCTL_9C +#define FCH_ABCFG_REGA0 0xA0 // BIF PHY CONTROL ENABLE +#define FCH_ABCFG_REGA4 0xA4 // BIF PHY CONTROL A4 +#define FCH_ABCFG_REGA8 0xA8 // BIF PHY CONTROL A8 +#define FCH_ABCFG_REGB4 0xB4 // +#define FCH_ABCFG_REGC0 0xC0 // PCIE_GPP_ENABLE +#define FCH_ABCFG_REGF0 0xF0 // GPP_UPSTREAM_CONTROL +#define FCH_ABCFG_REGF4 0xF4 // GPP_SYSTEM_ERROR_CONTROL +#define FCH_ABCFG_REG208 0x208 // KR New +#define FCH_ABCFG_REG300 0x300 // MCTP_VDM_RX_SMI_CONTROL +#define FCH_ABCFG_REG31C 0x31C // BIF_GPP_STRAP_LINK_CONTROL_0 +#define FCH_ABCFG_REG330 0x330 // BIF_GPP_STRAP_BIF_0 +#define FCH_ABCFG_REG340 0x340 // BIF_GPP_STRAP_BIF_LANE_A +#define FCH_ABCFG_REG344 0x344 // BIF_GPP_STRAP_BIF_LANE_B +#define FCH_ABCFG_REG348 0x348 // BIF_GPP_STRAP_BIF_LANE_C +#define FCH_ABCFG_REG34C 0x34C // BIF_GPP_STRAP_BIF_LANE_D +#define FCH_ABCFG_REG404 0x404 // GPP0_SHADOW_COMMAND +#define FCH_ABCFG_REG418 0x418 // GPP0_SHADOW_BUS_NUMBER +#define FCH_ABCFG_REG41C 0x41C // GPP0_SHADOW_IO_LIMIT_BASE +#define FCH_ABCFG_REG420 0x420 // GPP0_SHADOW_MEM_LIMIT_BASE +#define FCH_ABCFG_REG424 0x424 // GPP0_SHADOW_PREF_MEM_LIMIT_BASE +#define FCH_ABCFG_REG428 0x428 // GPP0_SHADOW_PREF_MEM_BASE_UPPER +#define FCH_ABCFG_REG42C 0x42C // GPP0_SHADOW_PREF_MEM_LIMIT_UPPER +#define FCH_ABCFG_REG430 0x430 // GPP0_SHADOW_IO_LIMIT_BASE_UPPER +#define FCH_ABCFG_REG43C 0x43C // GPP0_SHADOW_BRIDGE_CONTROL +#define FCH_ABCFG_REG444 0x444 // GPP1_SHADOW_COMMAND +#define FCH_ABCFG_REG458 0x458 // GPP1_SHADOW_BUS_NUMBER +#define FCH_ABCFG_REG45C 0x45C // GPP1_SHADOW_IO_LIMIT_BASE +#define FCH_ABCFG_REG460 0x460 // GPP1_SHADOW_MEM_LIMIT_BASE +#define FCH_ABCFG_REG464 0x464 // GPP1_SHADOW_PREF_MEM_LIMIT_BASE +#define FCH_ABCFG_REG468 0x468 // GPP1_SHADOW_PREF_MEM_BASE_UPPER +#define FCH_ABCFG_REG46C 0x46C // GPP1_SHADOW_PREF_MEM_LIMIT_UPPER +#define FCH_ABCFG_REG470 0x470 // GPP1_SHADOW_IO_LIMIT_BASE_UPPER +#define FCH_ABCFG_REG47C 0x47C // GPP1_SHADOW_BRIDGE_CONTROL +#define FCH_ABCFG_REG484 0x484 // GPP2_SHADOW_COMMAND +#define FCH_ABCFG_REG498 0x498 // GPP2_SHADOW_BUS_NUMBER +#define FCH_ABCFG_REG49C 0x49C // GPP2_SHADOW_IO_LIMIT_BASE +#define FCH_ABCFG_REG4A0 0x4A0 // GPP2_SHADOW_MEM_LIMIT_BASE +#define FCH_ABCFG_REG4A4 0x4A4 // GPP2_SHADOW_PREF_MEM_LIMIT_BASE +#define FCH_ABCFG_REG4A8 0x4A8 // GPP2_SHADOW_PREF_MEM_BASE_UPPER +#define FCH_ABCFG_REG4AC 0x4AC // GPP2_SHADOW_PREF_MEM_LIMIT_UPPER +#define FCH_ABCFG_REG4B0 0x4B0 // GPP2_SHADOW_IO_LIMIT_BASE_UPPER +#define FCH_ABCFG_REG4BC 0x4BC // GPP2_SHADOW_BRIDGE_CONTROL +#define FCH_ABCFG_REG4C4 0x4C4 // GPP3_SHADOW_COMMAND +#define FCH_ABCFG_REG4D8 0x4D8 // GPP3_SHADOW_BUS_NUMBER +#define FCH_ABCFG_REG4DC 0x4DC // GPP3_SHADOW_IO_LIMIT_BASE +#define FCH_ABCFG_REG4E0 0x4E0 // GPP3_SHADOW_MEM_LIMIT_BASE +#define FCH_ABCFG_REG4E4 0x4E4 // GPP3_SHADOW_PREF_MEM_LIMIT_BASE +#define FCH_ABCFG_REG4E8 0x4E8 // GPP3_SHADOW_PREF_MEM_BASE_UPPER +#define FCH_ABCFG_REG4EC 0x4EC // GPP3_SHADOW_PREF_MEM_LIMIT_UPPER +#define FCH_ABCFG_REG4F0 0x4F0 // GPP3_SHADOW_IO_LIMIT_BASE_UPPER +#define FCH_ABCFG_REG4FC 0x4FC // GPP3_SHADOW_BRIDGE_CONTROL +#define FCH_ABCFG_REG10040 0x10040ul // AL_EVENTCNT0LO +#define FCH_ABCFG_REG10044 0x10044ul // AL_EVENTCNT1LO +#define FCH_ABCFG_REG1004A 0x1004Aul // AL_EVENTCNT0HI +#define FCH_ABCFG_REG1004B 0x1004Bul // AL_EVENTCNT1HI +#define FCH_ABCFG_REG10050 0x10050ul // MISCCTL_10050 +#define FCH_ABCFG_REG10054 0x10054ul // AL_ARB_CTL +#define FCH_ABCFG_REG10056 0x10056ul // AL_CLK_CTL +#define FCH_ABCFG_REG10058 0x10058ul // AL RAB CONTROL +#define FCH_ABCFG_REG1005C 0x1005Cul // AL MLT CONTROL +#define FCH_ABCFG_REG10060 0x10060ul // AL DMA PREFETCH ENABLE +#define FCH_ABCFG_REG10064 0x10064ul // AL DMA PREFETCH FLUSH CONTROL +#define FCH_ABCFG_REG10068 0x10068ul // AL PREFETCH LIMIT +#define FCH_ABCFG_REG1006C 0x1006Cul // AL DMA PREFETCH CONTROL +#define FCH_ABCFG_REG10070 0x10070ul // MISCCTL_10070 +#define FCH_ABCFG_REG10080 0x10080ul // CLKMUXSTATUS +#define FCH_ABCFG_REG10090 0x10090ul // BIF CONTROL 0 +#define FCH_ABCFG_REG1009C 0x1009Cul // MISCCTL_1009C + +// +// RCINDX_P Registers +// +#define FCH_RCINDXP_REG01 0x01 | RCINDXP << 29 // PCIEP_SCRATCH +#define FCH_RCINDXP_REG02 0x02 | RCINDXP << 29 // +#define FCH_RCINDXP_REG10 0x10 | RCINDXP << 29 // +#define FCH_RCINDXP_REG20 0x20 | RCINDXP << 29 // PCIE_TX_CNTL +#define FCH_RCINDXP_REG21 0x21 | RCINDXP << 29 // PCIE_TX_REQUESTER_ID +#define FCH_RCINDXP_REG50 0x50 | RCINDXP << 29 // PCIE_P_PORT_LANE_STATUS +#define FCH_RCINDXP_REG6A 0x6A | RCINDXP << 29 // +#define FCH_RCINDXP_REG70 0x70 | RCINDXP << 29 // PCIE_RX_CNTL +#define FCH_RCINDXP_REGA0 0xA0 | RCINDXP << 29 // PCIE_LC_CNTL +#define FCH_RCINDXP_REGA1 0xA1 | RCINDXP << 29 // PCIE_LC_TRAINING_CNTL +#define FCH_RCINDXP_REGA2 0xA2 | RCINDXP << 29 // +#define FCH_RCINDXP_REGA4 0xA4 | RCINDXP << 29 // +#define FCH_RCINDXP_REGA5 0xA5 | RCINDXP << 29 // PCIE_LC_STATE0 +#define FCH_RCINDXP_REGC0 0xC0 | RCINDXP << 29 // + +// +// RCINDX_C Registers +// +#define FCH_RCINDXC_REG02 0x02 | RCINDXC << 29 // PCIE_HW_DEBUG +#define FCH_RCINDXC_REG10 0x10 | RCINDXC << 29 // PCIE_CNTL +#define FCH_RCINDXC_REG40 0x40 | RCINDXC << 29 // PCIE_P_CNTL +#define FCH_RCINDXC_REG65 0x65 | RCINDXC << 29 // PCIE_P_PAD_FORCE_DIS +#define FCH_RCINDXC_REGC0 0xC0 | RCINDXC << 29 // PCIE_STRAP_MISC +#define FCH_RCINDXC_REGC1 0xC1 | RCINDXC << 29 // PCIE_STRAP_MISC2 + + +// +// AXINDC Registers +// +#define FCH_AX_INDXC_REG02 0x02 // PCIEP_HW_DEBUG +#define FCH_AX_INDXC_REG10 0x10 +#define FCH_AX_INDXC_REG30 0x30 +#define FCH_AX_DATAC_REG34 0x34 +#define FCH_AX_INDXP_REG38 0x38 +#define FCH_AX_DATAP_REG3C 0x3C +#define FCH_AX_INDXC_REG40 0x40 | AXINDC << 29 +#define FCH_AX_INDXC_REGA4 0xA4 | AXINDC << 29 + +#define FCH_AX_INDXP_REG02 0x02 | AXINDP << 29 +#define FCH_AX_INDXP_REGA0 0xA0 | AXINDP << 29 +#define FCH_AX_INDXP_REGA4 0xA4 | AXINDP << 29 +#define FCH_AX_INDXP_REGB1 0xB1 | AXINDP << 29 + +#define FCH_AX_CFG_REG68 0x68 | AXCFG << 29 +#define FCH_AX_CFG_REG88 0x88 | AXCFG << 29 + +#define FCH_AB_REG04 0x04 +#define FCH_AB_REG40 0x40 + +//Sata Port Configuration +#define SIX_PORTS 0 +#define FOUR_PORTS 1 + +#define SATA_EFUSE_LOCATION 0x10 // EFUSE bit 133 +#define SATA_FIS_BASE_EFUSE_LOC 0x15 // EFUSE bit 169 +#define SATA_EFUSE_BIT 0x20 // + +#define FCH_SATA_BAR5_REG100 0x0100 // Serial ATA SControl - RW - 32 bits - [Offset: 100h (channel 1) / 180 +#define FCH_SATA_BAR5_REG104 0x0104 // Serial ATA Sstatus - RW - 32 bits - [Offset: 104h (channel 1) / 184h (cannel +#define FCH_SATA_BAR5_REG108 0x0108 // Serial ATA Serror - RW - 32 bits - [Offset: 108h (channel 1) / 188h (cannel +#define FCH_SATA_BAR5_REG10C 0x010C // Serial ATA Sdevice - RW - 32 bits - [Offset: 10Ch (channel 1) / 18Ch (cannel +#define FCH_SATA_BAR5_REG120 0x0120 // +#define FCH_SATA_BAR5_REG128 0x0128 // Port Serial ATA Status +#define FCH_SATA_BAR5_REG12C 0x012C // Port Serial ATA Control +#define FCH_SATA_BAR5_REG130 0x0130 +#define FCH_SATA_BAR5_REG1B0 0x01B0 +#define FCH_SATA_BAR5_REG230 0x0230 +#define FCH_SATA_BAR5_REG2B0 0x02B0 +#define FCH_SATA_BAR5_REG330 0x0330 +#define FCH_SATA_BAR5_REG3B0 0x03B0 + + +// USB ports +#define NUM_USB1_PORTS 5 +#define NUM_USB2_PORTS 5 +#define NUM_USB3_PORTS 4 +#define NUM_USB4_PORTS 2 +#define NUM_XHC0_PORTS 2 +#define NUM_XHC1_PORTS 2 + + +// Chip type definition +#define CHIPTYPE_HUDSON2 (1 << 0) +#define CHIPTYPE_YUBA (1 << 1) + + +// +// USB XHCI Device 0x7812 +// Device 16 (0x10) Func 0/1 +// +#define XHCI_EFUSE_LOCATION 0x18 // EFUSE bit 192, 193 +#define FCH_XHCI_REG48 0x48 // Port Force Reset - RW (800) +#define FCH_XHCI_REG4C 0x4C // MSI - RW (800) +// +// USB OHCI Device 0x7807 +// Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 0 +// Device 20 (0x14) Func 5 (FL) 0x7809 +// +#define FCH_OHCI_REG00 0x00 // Device/Vendor ID - R (0x43971002ul) +#define FCH_OHCI_REG04 0x04 // Command - RW +#define FCH_OHCI_REG06 0x06 // Status - R +#define FCH_OHCI_REG08 0x08 // Revision ID/Class Code - R +#define FCH_OHCI_REG0C 0x0C // Miscellaneous - RW +#define FCH_OHCI_REG10 0x10 // Bar_OCI - RW +#define FCH_OHCI_REG2C 0x2C // Subsystem Vendor ID/ Subsystem ID - RW +#define FCH_OHCI_REG34 0x34 // Capability Pointer - R +#define FCH_OHCI_REG3C 0x3C // Interrupt Line - RW +#define FCH_OHCI_REG3D 0x3D // Interrupt Line - RW +#define FCH_OHCI_REG40 0x40 // Config Timers - RW +#define FCH_OHCI_REG42 0x42 // Port Disable Control - RW (800) +#define FCH_OHCI_REG46 0x46 // USB PHY Battery Charger - RW (800) +#define FCH_OHCI_REG48 0x48 // Port Force Reset - RW (800) +#define FCH_OHCI_REG4C 0x4C // MSI - RW (800) +#define FCH_OHCI_REG51 0x51 +#define FCH_OHCI_REG58 0x58 // Over Current Control - RW +#define FCH_OHCI_REG5C 0x5C // Over Current Control - RW +#define FCH_OHCI_REG60 0x60 // Serial Bus Release Number - RW +#define FCH_OHCI_REG74 0x74 // Target Timeout Control - RW +#define FCH_OHCI_REG80 0x80 // +#define FCH_OHCI_REGD0 0x0D0 // MSI Control - RW +#define FCH_OHCI_REGD4 0x0D4 // MSI Address - RW +#define FCH_OHCI_REGD8 0x0D8 // MSI Data - RW + +#define FCH_OHCI_BAR_REG00 0x00 // cRevision - R +#define FCH_OHCI_BAR_REG04 0x04 // cControl +#define FCH_OHCI_BAR_REG08 0x08 // cCommandStatus +#define FCH_OHCI_BAR_REG0C 0x0C // cInterruptStatus RW +#define FCH_OHCI_BAR_REG10 0x10 // cInterruptEnable +#define FCH_OHCI_BAR_REG14 0x14 // cInterruptDisable +#define FCH_OHCI_BAR_REG18 0x18 // HcCCA +#define FCH_OHCI_BAR_REG1C 0x1C // cPeriodCurrentED +#define FCH_OHCI_BAR_REG20 0x20 // HcControleadED +#define FCH_OHCI_BAR_REG24 0x24 // cControlCurrentED RW +#define FCH_OHCI_BAR_REG28 0x28 // HcBulkeadED +#define FCH_OHCI_BAR_REG2C 0x2C // cBulkCurrentED- RW +#define FCH_OHCI_BAR_REG30 0x30 // HcDoneead +#define FCH_OHCI_BAR_REG34 0x34 // cFmInterval +#define FCH_OHCI_BAR_REG38 0x38 // cFmRemaining +#define FCH_OHCI_BAR_REG3C 0x3C // cFmNumber +#define FCH_OHCI_BAR_REG40 0x40 // cPeriodicStart +#define FCH_OHCI_BAR_REG44 0x44 // HcLSThresold +#define FCH_OHCI_BAR_REG48 0x48 // HcRDescriptorA +#define FCH_OHCI_BAR_REG4C 0x4C // HcRDescriptorB +#define FCH_OHCI_BAR_REG50 0x50 // HcRStatus +#define FCH_OHCI_BAR_REG54 0x54 // HcRhPortStatus (800) +#define FCH_OHCI_BAR_REG58 0x58 // HcRhPortStatus NPD (800) + +// +// USB EHCI Device 0x7808 +// Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 2 +// +#define FCH_EHCI_REG00 0x00 // DEVICE/VENDOR ID - R +#define FCH_EHCI_REG04 0x04 // Command - RW +#define FCH_EHCI_REG06 0x06 // Status - R +#define FCH_EHCI_REG08 0x08 // Revision ID/Class Code - R +#define FCH_EHCI_REG0C 0x0C // Miscellaneous - RW +#define FCH_EHCI_REG10 0x10 // BAR - RW +#define FCH_EHCI_REG2C 0x2C // Subsystem ID/Subsystem Vendor ID - RW +#define FCH_EHCI_REG34 0x34 // Capability Pointer - R +#define FCH_EHCI_REG3C 0x3C // Interrupt Line - RW +#define FCH_EHCI_REG3D 0x3D // Interrupt Line - RW +#define FCH_EHCI_REG40 0x40 // Config Timers - RW +#define FCH_EHCI_REG4C 0x4C // MSI - RW +#define FCH_EHCI_REG60 0x60 // SBRN - R +#define FCH_EHCI_REG61 0x61 // FLADJ - RW +#define FCH_EHCI_REGC0 0x0C0 // PME control - RW (800) +#define FCH_EHCI_REGC4 0x0C4 // PME Data /Status - RW (800) +#define FCH_EHCI_REGD0 0x0D0 // MSI Control - RW +#define FCH_EHCI_REGD4 0x0D4 // MSI Address - RW +#define FCH_EHCI_REGD8 0x0D8 // MSI Data - RW +#define FCH_EHCI_REGF0 0x0F0 // Function Level Reset Capability - R (800) +#define FCH_EHCI_REGF4 0x0F4 // Function Level Reset Capability - R (800) + +#define FCH_EHCI_BAR_REG00 0x00 // CAPLENGT - R +#define FCH_EHCI_BAR_REG02 0x002 // CIVERSION- R +#define FCH_EHCI_BAR_REG04 0x004 // CSPARAMS - R +#define FCH_EHCI_BAR_REG08 0x008 // CCPARAMS - R +#define FCH_EHCI_BAR_REG0C 0x00C // CSP-PORTROUTE - R + +#define FCH_EHCI_BAR_REG20 0x020 // USBCMD - RW - 32 bits +#define FCH_EHCI_BAR_REG24 0x024 // USBSTS - RW - 32 bits +#define FCH_EHCI_BAR_REG28 0x028 // USBINTR -RW - 32 bits +#define FCH_EHCI_BAR_REG2C 0x02C // FRINDEX -RW - 32 bits +#define FCH_EHCI_BAR_REG30 0x030 // CTRLDSSEGMENT -RW - 32 bits +#define FCH_EHCI_BAR_REG34 0x034 // PERIODICLISTBASE -RW - 32 bits +#define FCH_EHCI_BAR_REG38 0x038 // ASYNCLISTADDR -RW - 32 bits +#define FCH_EHCI_BAR_REG60 0x060 // CONFIGFLAG -RW - 32 bits +#define FCH_EHCI_BAR_REG64 0x064 // PORTSC (1-N_PORTS) -RW - 32 bits +#define FCH_EHCI_BAR_REGA4 0x0A4 // Packet Buffer Threshold Values - RW - 32 bits +#define FCH_EHCI_BAR_REGA8 0x0A8 // USB PHY Status 0 - R +#define FCH_EHCI_BAR_REGAC 0x0AC // USB PHY Status 1 - R +#define FCH_EHCI_BAR_REGB4 0x0B4 // UTMI Control - RW (800) +#define FCH_EHCI_BAR_REGB8 0x0B8 // Loopback Test +#define FCH_EHCI_BAR_REGBC 0x0BC // EHCI MISC Control +#define FCH_EHCI_BAR_REGC4 0x0C4 // USB Common PHY Control +#define FCH_EHCI_BAR_REGC8 0x0C8 // EHCI Debug Purpose +#define FCH_EHCI_BAR_REGCC 0x0CC // Ehci Spare 1 (800) ** +#define FCH_EHCI_BAR_REG100 0x100 // USB debug port + +// +// USB EHCI Device 0x7812 +// Device 16 (0x10) Func 0/1 +// +#define FCH_XHCI_REG00 0x00 // DEVICE/VENDOR ID - R +#define FCH_XHCI_REG04 0x04 // Command - RW +#define FCH_XHCI_REG10 0x10 // Bar0 +#define FCH_XHCI_REG2C 0x2C // Sub System ID +#define FCH_XHCI_REG40 0x40 // Index0 +#define FCH_XHCI_REG44 0x44 // Data0 +#define FCH_XHCI_REG48 0x48 // Index1 +#define FCH_XHCI_REG4C 0x4C // Data0 +#define FCH_XHCI_REG54 0x54 // PME Control/Status + +// +// FCH CFG device 0x780B +// Device 20 (0x14) Func 0 +// +#define FCH_CFG_REG00 0x000 // VendorID - R +#define FCH_CFG_REG02 0x002 // DeviceID - R +#define FCH_CFG_REG04 0x004 // Command- RW +#define FCH_CFG_REG05 0x005 // Command- RW +#define FCH_CFG_REG06 0x006 // STATUS- RW +#define FCH_CFG_REG08 0x008 // Revision ID/Class Code- R +#define FCH_CFG_REG0A 0x00A // +#define FCH_CFG_REG0B 0x00B // +#define FCH_CFG_REG0C 0x00C // Cache Line Size- R +#define FCH_CFG_REG0D 0x00D // Latency Timer- R +#define FCH_CFG_REG0E 0x00E // Header Type- R +#define FCH_CFG_REG0F 0x00F // BIST- R +#define FCH_CFG_REG10 0x010 // Base Address 0- R +#define FCH_CFG_REG11 0x011 //; +#define FCH_CFG_REG12 0x012 //; +#define FCH_CFG_REG13 0x013 //; +#define FCH_CFG_REG14 0x014 // Base Address 1- R +#define FCH_CFG_REG18 0x018 // Base Address 2- R +#define FCH_CFG_REG1C 0x01C // Base Address 3- R +#define FCH_CFG_REG20 0x020 // Base Address 4- R +#define FCH_CFG_REG24 0x024 // Base Address 5- R +#define FCH_CFG_REG28 0x028 // Cardbus CIS Pointer- R +#define FCH_CFG_REG2C 0x02C // Subsystem Vendor ID- W +#define FCH_CFG_REG2E 0x02E // Subsystem ID- W +#define FCH_CFG_REG30 0x030 // Expansion ROM Base Address - R +#define FCH_CFG_REG34 0x034 // Capability Pointer - R (800) default changed as 0x00 +#define FCH_CFG_REG3C 0x03C // Interrupt Line - R +#define FCH_CFG_REG3D 0x03D // Interrupt Pin - R +#define FCH_CFG_REG3E 0x03E // Min_Gnt - R +#define FCH_CFG_REG3F 0x03F // Max_Lat - R +#define FCH_CFG_REG90 0x090 // Smbus Base Address - R +#define FCH_CFG_REG9C 0x09C // SBResourceMMIO_BASE + +// +// FCH SATA IDE device +// Device 20 (0x14) Func 1 +// + +#define FCH_IDE_REG00 0x00 // Vendor ID +#define FCH_IDE_REG02 0x02 // Device ID +#define FCH_IDE_REG04 0x04 // Command +#define FCH_IDE_REG06 0x06 // Status +#define FCH_IDE_REG08 0x08 // Revision ID/Class Code +#define FCH_IDE_REG09 0x09 // Class Code +#define FCH_IDE_REG2C 0x2C // Subsystem ID and Subsystem Vendor ID +#define FCH_IDE_REG40 0x40 // Configuration - RW - 32 bits +#define FCH_IDE_REG34 0x34 +// +// Device 20 (0x14) Func 2 +// + +#define FCH_AZ_REG00 0x00 // Vendor ID - R +#define FCH_AZ_REG02 0x02 // Device ID - R/W +#define FCH_AZ_REG04 0x04 // PCI Command +#define FCH_AZ_REG06 0x06 // PCI Status - R/W +#define FCH_AZ_REG08 0x08 // Revision ID +#define FCH_AZ_REG09 0x09 // Programming Interface +#define FCH_AZ_REG0A 0x0A // Sub Class Code +#define FCH_AZ_REG0B 0x0B // Base Class Code +#define FCH_AZ_REG0C 0x0C // Cache Line Size - R/W +#define FCH_AZ_REG0D 0x0D // Latency Timer +#define FCH_AZ_REG0E 0x0E // Header Type +#define FCH_AZ_REG0F 0x0F // BIST +#define FCH_AZ_REG10 0x10 // Lower Base Address Register +#define FCH_AZ_REG14 0x14 // Upper Base Address Register +#define FCH_AZ_REG2C 0x2C // Subsystem Vendor ID +#define FCH_AZ_REG2D 0x2D // Subsystem ID +#define FCH_AZ_REG34 0x34 // Capabilities Pointer +#define FCH_AZ_REG3C 0x3C // Interrupt Line +#define FCH_AZ_REG3D 0x3D // Interrupt Pin +#define FCH_AZ_REG3E 0x3E // Minimum Grant +#define FCH_AZ_REG3F 0x3F // Maximum Latency +#define FCH_AZ_REG40 0x40 // Misc Control 1 +#define FCH_AZ_REG42 0x42 // Misc Control 2 Register +#define FCH_AZ_REG43 0x43 // Misc Control 3 Register +#define FCH_AZ_REG44 0x44 // Interrupt Pin Control Register +#define FCH_AZ_REG46 0x46 // Debug Control Register +#define FCH_AZ_REG4C 0x4C +#define FCH_AZ_REG50 0x50 // Power Management Capability ID +#define FCH_AZ_REG52 0x52 // Power Management Capabilities +#define FCH_AZ_REG54 0x54 // Power Management Control/Status +#define FCH_AZ_REG60 0x60 // MSI Capability ID +#define FCH_AZ_REG62 0x62 // MSI Message Control +#define FCH_AZ_REG64 0x64 // MSI Message Lower Address +#define FCH_AZ_REG68 0x68 // MSI Message Upper Address +#define FCH_AZ_REG6C 0x6C // MSI Message Data + +#define FCH_AZ_BAR_REG00 0x00 // Global Capabilities - R +#define FCH_AZ_BAR_REG02 0x02 // Minor Version - R +#define FCH_AZ_BAR_REG03 0x03 // Major Version - R +#define FCH_AZ_BAR_REG04 0x04 // Output Payload Capability - R +#define FCH_AZ_BAR_REG06 0x06 // Input Payload Capability - R +#define FCH_AZ_BAR_REG08 0x08 // Global Control - R/W +#define FCH_AZ_BAR_REG0C 0x0C // Wake Enable - R/W +#define FCH_AZ_BAR_REG0E 0x0E // State Change Status - R/W +#define FCH_AZ_BAR_REG10 0x10 // Global Status - R/W +#define FCH_AZ_BAR_REG18 0x18 // Output Stream Payload Capability - R +#define FCH_AZ_BAR_REG1A 0x1A // Input Stream Payload Capability - R +#define FCH_AZ_BAR_REG20 0x20 // Interrupt Control - R/W +#define FCH_AZ_BAR_REG24 0x24 // Interrupt Status - R/W +#define FCH_AZ_BAR_REG30 0x30 // Wall Clock Counter - R +#define FCH_AZ_BAR_REG38 0x38 // Stream Synchronization - R/W +#define FCH_AZ_BAR_REG40 0x40 // CORB Lower Base Address - R/W +#define FCH_AZ_BAR_REG44 0x44 // CORB Upper Base Address - RW +#define FCH_AZ_BAR_REG48 0x48 // CORB Write Pointer - R/W +#define FCH_AZ_BAR_REG4A 0x4A // CORB Read Pointer - R/W +#define FCH_AZ_BAR_REG4C 0x4C // CORB Control - R/W +#define FCH_AZ_BAR_REG4D 0x4D // CORB Status - R/W +#define FCH_AZ_BAR_REG4E 0x4E // CORB Size - R/W +#define FCH_AZ_BAR_REG50 0x50 // RIRB Lower Base Address - RW +#define FCH_AZ_BAR_REG54 0x54 // RIRB Upper Address - RW +#define FCH_AZ_BAR_REG58 0x58 // RIRB Write Pointer - RW +#define FCH_AZ_BAR_REG5A 0x5A // RIRB Response Interrupt Count - R/W +#define FCH_AZ_BAR_REG5C 0x5C // RIRB Control - R/W +#define FCH_AZ_BAR_REG5D 0x5D // RIRB Status - R/W +#define FCH_AZ_BAR_REG5E 0x5E // RIRB Size - R/W +#define FCH_AZ_BAR_REG60 0x60 // Immediate Command Output Interface - R/W +#define FCH_AZ_BAR_REG64 0x64 // Immediate Command Input Interface - R/W +#define FCH_AZ_BAR_REG68 0x68 // Immediate Command Input Interface - R/W +#define FCH_AZ_BAR_REG70 0x70 // DMA Position Lower Base Address - R/W +#define FCH_AZ_BAR_REG74 0x74 // DMA Position Upper Base Address - R/W +#define FCH_AZ_BAR_REG2030 0x2030 // Wall Clock Counter Alias - R + +// +// FCH LPC Device 0x780E +// Device 20 (0x14) Func 3 +// +#define FCH_LPC_REG00 0x00 // VID- R +#define FCH_LPC_REG02 0x02 // DID- R +#define FCH_LPC_REG04 0x04 // CMD- RW +#define FCH_LPC_REG06 0x06 // STATUS- RW +#define FCH_LPC_REG08 0x08 // Revision ID/Class Code - R +#define FCH_LPC_REG0C 0x0C // Cache Line Size - R +#define FCH_LPC_REG0D 0x0D // Latency Timer - R +#define FCH_LPC_REG0E 0x0E // Header Type - R +#define FCH_LPC_REG0F 0x0F // BIST- R +#define FCH_LPC_REG10 0x10 // Base Address Reg 0- RW* +#define FCH_LPC_REG2C 0x2C // Subsystem ID & Subsystem Vendor ID - Wo/Ro +#define FCH_LPC_REG34 0x34 // Capabilities Pointer - Ro +#define FCH_LPC_REG40 0x40 // PCI Control - RW +#define FCH_LPC_REG44 0x44 // IO Port Decode Enable Register 1- RW +#define FCH_LPC_REG45 0x45 // IO Port Decode Enable Register 2- RW +#define FCH_LPC_REG46 0x46 // IO Port Decode Enable Register 3- RW +#define FCH_LPC_REG47 0x47 // IO Port Decode Enable Register 4- RW +#define FCH_LPC_REG48 0x48 // IO/Mem Port Decode Enable Register 5- RW +#define FCH_LPC_REG49 0x49 // LPC Sync Timeout Count - RW +#define FCH_LPC_REG4A 0x4A // IO/Mem Port Decode Enable Register 6- RW +#define FCH_LPC_REG4C 0x4C // Memory Range Register - RW +#define FCH_LPC_REG50 0x50 // Rom Protect 0 - RW +#define FCH_LPC_REG54 0x54 // Rom Protect 1 - RW +#define FCH_LPC_REG58 0x58 // Rom Protect 2 - RW +#define FCH_LPC_REG5C 0x5C // Rom Protect 3 - RW +#define FCH_LPC_REG60 0x60 // PCI Memory Start Address of LPC Target Cycles - +#define FCH_LPC_REG62 0x62 // PCI Memory End Address of LPC Target Cycles - +#define FCH_LPC_REG64 0x64 // PCI IO base Address of Wide Generic Port - RW +#define FCH_LPC_REG65 0x65 +#define FCH_LPC_REG66 0x66 +#define FCH_LPC_REG67 0x67 +#define FCH_LPC_REG68 0x68 // LPC ROM Address Range 1 (Start Address) - RW +#define FCH_LPC_REG69 0x69 +#define FCH_LPC_REG6A 0x6A // LPC ROM Address Range 1 (End Address) - RW +#define FCH_LPC_REG6B 0x6B +#define FCH_LPC_REG6C 0x6C // LPC ROM Address Range 2 (Start Address)- RW +#define FCH_LPC_REG6D 0x6D +#define FCH_LPC_REG6E 0x6E // LPC ROM Address Range 2 (End Address) - RW +#define FCH_LPC_REG6F 0x6F +#define FCH_LPC_REG71 0x71 +#define FCH_LPC_REG72 0x72 +#define FCH_LPC_REG73 0x73 +#define FCH_LPC_REG74 0x74 // Alternative Wide IO Range Enable- W/R +#define FCH_LPC_REG7C 0x7C // TPM (trusted plant form module) reg- W/R +#define FCH_LPC_REG9C 0x9C +#define FCH_LPC_REG80 0x80 // MSI Capability Register- R +#define FCH_LPC_REGA0 0x0A0 // SPI base address +#define FCH_LPC_REGA1 0x0A1 // SPI base address +#define FCH_LPC_REGA2 0x0A2 // SPI base address +#define FCH_LPC_REGA3 0x0A3 // SPI base address +#define FCH_LPC_REGA4 0x0A4 +#define FCH_LPC_REGBA 0x0BA // EcControl +#define FCH_LPC_REGBB 0x0BB // HostControl +#define FCH_LPC_REGCC 0x0CC // AutoRomCfg +#define FCH_LPC_REGD0 0x0D0 + +// +// FCH PCIB 0x780F +// Device 20 (0x14) Func 4 +// +#define FCH_PCIB_REG04 0x04 // Command +#define FCH_PCIB_REG0D 0x0D // Primary Master Latency Timer +#define FCH_PCIB_REG1B 0x1B // Secondary Latency Timer +#define FCH_PCIB_REG1C 0x1C // IO Base +#define FCH_PCIB_REG1D 0x1D // IO Limit +#define FCH_PCIB_REG40 0x40 // CPCTRL +#define FCH_PCIB_REG42 0x42 // CLKCTRL +#define FCH_PCIB_REG48 0x48 // +#define FCH_PCIB_REG4A 0x4A // PCICLK Enable Bits +#define FCH_PCIB_REG4B 0x4B // Misc Control +#define FCH_PCIB_REG4C 0x4C // AutoClockRun Control +#define FCH_PCIB_REG50 0x50 // Dual Address Cycle Enable and PCIB_CLK_Stop Override +#define FCH_PCIB_REG65 0x65 // Misc Control +#define FCH_PCIB_REG66 0x66 // Misc Control +// +// FCH GEC 0x14E4 0x1699 +// Device 20 (0x14) Func 6 +// +#define FCH_GEC_REG10 0x10 // GEC BAR +// +// FCH MMIO Base (SMI) +// offset : 0x200 +// +#define FCH_SMI_REG00 0x00 // EventStatus +#define FCH_SMI_REG04 0x04 // EventEnable +#define FCH_SMI_REG08 0x08 // SciTrig +#define FCH_SMI_REG0C 0x0C // SciLevl +#define FCH_SMI_REG10 0x10 // SmiSciStatus +#define FCH_SMI_REG14 0x14 // SmiSciEn +#define FCH_SMI_REG18 0x18 // ForceSciEn +#define FCH_SMI_REG1C 0x1C // SciRwData +#define FCH_SMI_REG3C 0x3C // DataErrorStatus +#define FCH_SMI_REG20 0x20 // SciS0En + +// Empty from 0x72-0x7F +//#Define FCH_SMI_REG7C 0x7F // SciMap63 *** + +#define FCH_SMI_REG80 0x80 // SmiStatus0 +#define FCH_SMI_REG84 0x84 // SmiStatus1 +#define FCH_SMI_REG88 0x88 // SmiStatus2 +#define FCH_SMI_REG8C 0x8C // SmiStatus3 +#define FCH_SMI_REG90 0x90 // SmiStatus4 +#define FCH_SMI_REG94 0x94 // SmiPointer +#define FCH_SMI_REG96 0x96 // SmiTimer +#define FCH_SMI_REG98 0x98 // SmiTrig +#define FCH_SMI_REG9C 0x9C // SmiTrig +#define FCH_SMI_REGA0 0xA0 +#define FCH_SMI_REGA1 0xA1 +#define FCH_SMI_REGA2 0xA2 +#define FCH_SMI_REGA3 0xA3 +#define FCH_SMI_REGA4 0xA4 +#define FCH_SMI_REGA5 0xA5 +#define FCH_SMI_REGA6 0xA6 +#define FCH_SMI_REGA7 0xA7 +#define FCH_SMI_REGA8 0xA8 +#define FCH_SMI_REGA9 0xA9 +#define FCH_SMI_REGAA 0xAA +#define FCH_SMI_REGAB 0xAB +#define FCH_SMI_REGAC 0xAC +#define FCH_SMI_REGAD 0xAD +#define FCH_SMI_REGAE 0xAE +#define FCH_SMI_REGAF 0xAF +#define FCH_SMI_REGB0 0xB0 +#define FCH_SMI_REGB1 0xB1 +#define FCH_SMI_REGB2 0xB2 +#define FCH_SMI_REGB3 0xB3 +#define FCH_SMI_REGB4 0xB4 +#define FCH_SMI_REGB5 0xB5 +#define FCH_SMI_REGB6 0xB6 +#define FCH_SMI_REGB7 0xB7 +#define FCH_SMI_REGB8 0xB8 +#define FCH_SMI_REGB9 0xB9 +#define FCH_SMI_REGBA 0xBA +#define FCH_SMI_REGBB 0xBB +#define FCH_SMI_REGBC 0xBC +#define FCH_SMI_REGBD 0xBD +#define FCH_SMI_REGBE 0xBE +#define FCH_SMI_REGBF 0xBF +#define FCH_SMI_REGC0 0xC0 +#define FCH_SMI_REGC1 0xC1 +#define FCH_SMI_REGC2 0xC2 +#define FCH_SMI_REGC3 0xC3 +#define FCH_SMI_REGC4 0xC4 +#define FCH_SMI_REGC5 0xC5 +#define FCH_SMI_REGC6 0xC6 +#define FCH_SMI_REGC7 0xC7 +#define FCH_SMI_REGC8 0xC8 +#define FCH_SMI_REGCA 0xCA // IoTrapping1 +#define FCH_SMI_REGCC 0xCC // IoTrapping2 +#define FCH_SMI_REGCE 0xCE // IoTrapping3 +#define FCH_SMI_REGD0 0xD0 // MemTrapping0 +#define FCH_SMI_REGD4 0xD4 // MemRdOvrData0 +#define FCH_SMI_REGD8 0xD8 // MemTrapping1 +#define FCH_SMI_REGDC 0xDC // MemRdOvrData1 +#define FCH_SMI_REGE0 0xE0 // MemTrapping2 +#define FCH_SMI_REGE4 0xE4 // MemRdOvrData2 +#define FCH_SMI_REGE8 0xE8 // MemTrapping3 +#define FCH_SMI_REGEC 0xEC // MemRdOvrData3 +#define FCH_SMI_REGF0 0xF0 // CfgTrapping0 +#define FCH_SMI_REGF4 0xF4 // CfgTrapping1 +#define FCH_SMI_REGF8 0xF8 // CfgTrapping2 +#define FCH_SMI_REGFC 0xFC // CfgTrapping3 + +// +// FCH MMIO Base (PMIO) +// offset : 0x300 +// +#define FCH_PMIOA_REG00 0x00 // ISA Decode +#define FCH_PMIOA_REG04 0x04 // ISA Control +#define FCH_PMIOA_REG08 0x08 // PCI Control +#define FCH_PMIOA_REG0C 0x0C // StpClkSmaf +#define FCH_PMIOA_REG10 0x10 // RetryDetect +#define FCH_PMIOA_REG14 0x14 // StuckDetect +#define FCH_PMIOA_REG20 0x20 // BiosRamEn +#define FCH_PMIOA_REG24 0x24 // AcpiMmioEn +#define FCH_PMIOA_REG2C 0x2C // Smbus0En +#define FCH_PMIOA_REG2E 0x2E // Smbus0Sel +#define FCH_PMIOA_REG34 0x34 // IoApicEn +#define FCH_PMIOA_REG3C 0x3C // SmartVoltEn +#define FCH_PMIOA_REG40 0x40 // SmartVolt2En +#define FCH_PMIOA_REG44 0x44 // BootTimerEn +#define FCH_PMIOA_REG48 0x48 // WatchDogTimerEn +#define FCH_PMIOA_REG4C 0x4C // WatchDogTimerConfig +#define FCH_PMIOA_REG50 0x50 // HPETEn +#define FCH_PMIOA_REG54 0x54 // SerialIrqConfig +#define FCH_PMIOA_REG56 0x56 // RtcControl +#define FCH_PMIOA_REG58 0x58 // VRT_T1 +#define FCH_PMIOA_REG59 0x59 // VRT_T2 +#define FCH_PMIOA_REG5A 0x5A // IntruderControl +#define FCH_PMIOA_REG5B 0x5B // RtcShadow +#define FCH_PMIOA_REG5C 0x5C +#define FCH_PMIOA_REG5E 0x5E // RtcExtIndex +#define FCH_PMIOA_REG5F 0x5F // RtcExtData +#define FCH_PMIOA_REG60 0x60 // AcpiPm1EvtBlk +#define FCH_PMIOA_REG62 0x62 // AcpiPm1CntBlk +#define FCH_PMIOA_REG64 0x64 // AcpiPmTmrBlk +#define FCH_PMIOA_REG66 0x66 // P_CNTBlk +#define FCH_PMIOA_REG68 0x68 // AcpiGpe0Blk +#define FCH_PMIOA_REG6A 0x6A // AcpiSmiCmd +#define FCH_PMIOA_REG6C 0x6C // AcpiPm2CntBlk +#define FCH_PMIOA_REG6E 0x6E // AcpiPmaCntBlk +#define FCH_PMIOA_REG74 0x74 // AcpiConfig +#define FCH_PMIOA_REG78 0x78 // WakeIoAddr +#define FCH_PMIOA_REG7A 0x7A // HaltCountEn +#define FCH_PMIOA_REG7C 0x7C // C1eWrPortAdr +#define FCH_PMIOA_REG7E 0x7E // CStateEn +#define FCH_PMIOA_REG7F 0x7F // CStateEn +#define FCH_PMIOA_REG80 0x80 // BreakEvent +#define FCH_PMIOA_REG88 0x88 // CStateControl +#define FCH_PMIOA_REG89 0x89 // +#define FCH_PMIOA_REG8C 0x8C // StpClkHoldTime +#define FCH_PMIOA_REG8E 0x8E // PopUpEndTime +#define FCH_PMIOA_REG90 0x90 // C4Control +#define FCH_PMIOA_REG94 0x94 // CStateTiming0 +#define FCH_PMIOA_REG96 0x96 // +#define FCH_PMIOA_REG97 0x97 // +#define FCH_PMIOA_REG98 0x98 // CStateTiming1 +#define FCH_PMIOA_REG99 0x99 // +#define FCH_PMIOA_REG9B 0x9B // +#define FCH_PMIOA_REG9C 0x9C // C2Count +#define FCH_PMIOA_REG9D 0x9D // C3Count +#define FCH_PMIOA_REGA0 0xA0 // MessageCState +#define FCH_PMIOA_REGA4 0xA4 // +#define FCH_PMIOA_REGA8 0xA8 // TrafficMonitorIdleTime +#define FCH_PMIOA_REGAA 0xAA // TrafficMonitorIntTime +#define FCH_PMIOA_REGAC 0xAC // TrafficMonitorTrafficCount +#define FCH_PMIOA_REGAE 0xAE // TrafficMonitorIntrCount +#define FCH_PMIOA_REGB0 0xB0 // TrafficMonitorTimeTick +#define FCH_PMIOA_REGB4 0xB4 // FidVidControl +#define FCH_PMIOA_REGB7 0xB7 // Tpreset1b +#define FCH_PMIOA_REGB8 0xB8 // TPRESET2 +#define FCH_PMIOA_REGBA 0xBA // S_StateControl +#define FCH_PMIOA_REGBB 0xBB // +#define FCH_PMIOA_REGBC 0xBC // ThrottlingControl +#define FCH_PMIOA_REGBE 0xBE // ResetControl +#define FCH_PMIOA_REGBF 0xBF // ResetControl +#define FCH_PMIOA_REGC0 0xC0 // S5Status +#define FCH_PMIOA_REGC2 0xC2 // ResetStatus +#define FCH_PMIOA_REGC4 0xC4 // ResetCommand +#define FCH_PMIOA_REGC5 0xC5 // CF9Shadow +#define FCH_PMIOA_REGC6 0xC6 // HTControl +#define FCH_PMIOA_REGC8 0xC8 // Misc +#define FCH_PMIOA_REGCC 0xCC // IoDrvSth +#define FCH_PMIOA_REGD0 0xD0 // CLKRunEn +#define FCH_PMIOA_REGD2 0xD2 // PmioDebug +#define FCH_PMIOA_REGD6 0xD6 // IMCGating +#define FCH_PMIOA_REGE0 0xE0 // ABRegBar +#define FCH_PMIOA_REGE7 0xE7 +#define FCH_PMIOA_REGEA 0xEA // PcibConfig +#define FCH_PMIOA_REGEC 0xEC // LpcGating +#define FCH_PMIOA_REGED 0xED // UsbGating +#define FCH_PMIOA_REGEE 0xEE // UsbCntrl +#define FCH_PMIOA_REGEF 0xEF // UsbEnable +#define FCH_PMIOA_REGF0 0xF0 // UsbControl +#define FCH_PMIOA_REGF3 0xF3 // UsbDebug +#define FCH_PMIOA_REGF6 0xF6 // GecEn +#define FCH_PMIOA_REGF8 0xF8 // GecConfig +#define FCH_PMIOA_REGFC 0xFC // TraceMemoryEn + +// +// FCH MMIO Base (PMIO2) +// offset : 0x400 +// + + +#define FCH_PMIO2_REG63 0x63 // SampleFreqDiv +#define FCH_PMIO2_REG69 0x69 // Fan0 Speed +#define FCH_PMIO2_REG95 0x95 // Temperature +#define FCH_PMIO2_REGB8 0xB8 // Voltage +#define FCH_PMIO2_REGEA 0xEA // Hwm_Calibration + +#define FCH_PMIO2_REG92 0x92 // + +#define FCH_PMIO2_REG 0xFC // TraceMemoryEn + + +// +// FCH MMIO Base (GPIO/IoMux) +// offset : 0x100/0xD00 +// +/* +GPIO from 0 ~ 67, (GEVENT 0-23) 128 ~ 150, 160 ~ 226. +*/ +#define FCH_GPIO_REG60 0x3C +#define FCH_GPIO_REG61 0x3D +#define FCH_GPIO_REG62 0x3E +#define FCH_GPIO_REG63 0x3F +#define FCH_GPIO_REG64 0x40 +#define FCH_GPIO_REG65 0x41 +#define FCH_GPIO_REG66 0x42 +#define FCH_GPIO_REG67 0x43 +#define FCH_GPIO_REG68 0x44 +#define FCH_GPIO_REG69 0x45 +#define FCH_GPIO_REG70 0x46 +#define FCH_GPIO_REG71 0x47 +#define FCH_GPIO_REG72 0x48 +#define FCH_GPIO_REG73 0x49 +#define FCH_GPIO_REG74 0x4A +#define FCH_GPIO_REG75 0x4B +#define FCH_GPIO_REG76 0x4C +#define FCH_GPIO_REG77 0x4D +#define FCH_GPIO_REG78 0x4E +#define FCH_GPIO_REG79 0x4F +#define FCH_GPIO_REG80 0x50 + +#define FCH_GEVENT_REG00 0x60 +#define FCH_GEVENT_REG01 0x61 +#define FCH_GEVENT_REG02 0x62 +#define FCH_GEVENT_REG03 0x63 +#define FCH_GEVENT_REG04 0x64 +#define FCH_GEVENT_REG05 0x65 +#define FCH_GEVENT_REG06 0x66 +#define FCH_GEVENT_REG07 0x67 +#define FCH_GEVENT_REG08 0x68 +#define FCH_GEVENT_REG09 0x69 +#define FCH_GEVENT_REG10 0x6A +#define FCH_GEVENT_REG11 0x6B +#define FCH_GEVENT_REG12 0x6C +#define FCH_GEVENT_REG13 0x6D +#define FCH_GEVENT_REG14 0x6E +#define FCH_GEVENT_REG15 0x6F +#define FCH_GEVENT_REG16 0x70 +#define FCH_GEVENT_REG17 0x71 +#define FCH_GEVENT_REG18 0x72 +#define FCH_GEVENT_REG19 0x73 +#define FCH_GEVENT_REG20 0x74 +#define FCH_GEVENT_REG21 0x75 +#define FCH_GEVENT_REG22 0x76 +#define FCH_GEVENT_REG23 0x77 +// S5-DOMAIN GPIO +#define FCH_GPIO_REG166 0xA6 +#define FCH_GPIO_REG167 0xA7 +#define FCH_GPIO_REG168 0xA8 +#define FCH_GPIO_REG169 0xA9 +#define FCH_GPIO_REG170 0xAA + +// +// FCH MMIO Base (SMBUS) +// offset : 0xA00 +// +#define FCH_SMBUS_REG12 0x12 // I2CbusConfig + +// +// FCH MMIO Base (MISC) +// offset : 0xE00 +// +#define FCH_MISC_REG00 0x00 // ClkCntrl0 +/* +FCH_MISC_REG00 EQU 000h + ClkCntrl0 EQU 0FFFFFFFFh +*/ +#define FCH_MISC_REG04 0x04 // ClkCntrl1 +/* +FCH_MISC_REG04 EQU 004h + ClkCntrl1 EQU 0FFFFFFFFh +*/ +#define FCH_MISC_REG08 0x08 // ClkCntrl2 +/* +FCH_MISC_REG08 EQU 008h + ClkCntrl2 EQU 0FFFFFFFFh +*/ +#define FCH_MISC_REG0C 0x0C // ClkCntrl3 +/* +FCH_MISC_REG0C EQU 00Ch + ClkCntrl3 EQU 0FFFFFFFFh +*/ +#define FCH_MISC_REG10 0x10 // ClkCntrl4 +/* +FCH_MISC_REG10 EQU 010h + ClkCntrl4 EQU 0FFFFFFFFh +*/ +#define FCH_MISC_REG14 0x14 // ClkCntrl5 +/* +FCH_MISC_REG14 EQU 014h + ClkCntrl5 EQU 0FFFFFFFFh +*/ +#define FCH_MISC_REG18 0x18 // ClkCntrl6 +/* +FCH_MISC_REG18 EQU 018h + ClkCntrl6 EQU 0FFFFFFFFh +*/ +#define FCH_MISC_REG1C 0x1C +#define FCH_MISC_REG30 0x30 // OscFreqCounter +/* +FCH_MISC_REG30 EQU 030h + OscCounter EQU 0FFFFFFFFh ; The 32bit register shows the number of OSC clock per second. +*/ +#define FCH_MISC_REG34 0x34 // HpetClkPeriod +/* +FCH_MISC_REG34 EQU 034h + HpetClkPeriod EQU 0FFFFFFFFh ; default - 0x429B17Eh (14.31818M). +*/ +#define FCH_MISC_REG28 0x28 // ClkDrvSth2 +#define FCH_MISC_REG40 0x40 // MiscCntrl for clock only +#define FCH_MISC_REG41 0x41 // MiscCntr2 +#define FCH_MISC_REG42 0x42 // MiscCntr3 +#define FCH_MISC_REG44 0x44 // ValueOnPort80 +#define FCH_MISC_REG50 0x50 // +/* +FCH_MISC_REG40 EQU 040h +*/ + +#define FCH_MISC_REG80 0x80 /**< FCH_MISC_REG80 + * @par + * StrapStatus [15.0] - FCH chip Strap Status + * @li <b>0001</b> - Not USED FWH + * @li <b>0002</b> - Not USED LPC ROM + * @li <b>0004</b> - EC enabled + * @li <b>0008</b> - Reserved + * @li <b>0010</b> - Internal Clock mode + */ +#define FCH_MISC_REGB6 0xB6 // + +#define ChipSysNotUseFWHRom 0x0001 // EcPwm3 pad +#define ChipSysNotUseLpcRom 0x0002 // Inverted version from EcPwm2 pad (default - 1) + // Note: Both EcPwm3 and EcPwm2 straps pins are used to select boot ROM type. +#define ChipSysEcEnable 0x0004 // Enable Embedded Controller (EC) +#define ChipSysBootFailTmrEn 0x0008 // Enable Watchdog function +#define ChipSysIntClkGen 0x0010 // Select 25Mhz crystal clock or 100Mhz PCI-E clock ** + +#define FCH_MISC_REG84 0x84 // StrapOverride +/* +FCH_MISC_REG84 EQU 084h + Override FWHDisableStrap EQU BIT0 ; Override FWHDiableStrap value from external pin. + Override UseLpcRomStrap EQU BIT1 ; Override UseLpcRomStrap value from external pin. + Override EcEnableStrap EQU BIT2 ; Override EcEnableStrap value from external pin. + Override BootFailTmrEnStrap EQU BIT3 ; Override BootFailTmrEnStrap value from external pin. + Override DefaultModeStrap EQU BIT5 ; Override DefaultModeStrap value from external pin. + Override I2CRomStrap EQU BIT7 ; Override I2CRomStrap value from external pin. + Override ILAAutorunEnBStrap EQU BIT8 ; Override ILAAutorunEnBStrap value from external pin. + Override FcPllBypStrap EQU BIT9 ; Override FcPllBypStrap value from external pin. + Override PciPllBypStrap EQU BIT10 ; Override PciPllBypStrap value from external pin. + Override ShortResetStrap EQU BIT11 ; Override ShortResetStrap value from external pin. + Override FastBif2ClkStrap EQU BIT13 ; Override FastBif2ClkStrap value from external pin + PciRomBootStrap EQU BIT15 ; Override PCI Rom Boot Strap value from external pin + BlinkSlowModestrap EQU BIT16 ; Override Blink Slow mode (100Mhz) from external pin + ClkGenStrap EQU BIT17 ; Override CLKGEN from external pin. + BIF_GEN2_COMPL_Strap EQU BIT18 ; Override BIF_ GEN2_COMPLIANCE strap from external pin. + StrapOverrideEn EQU BIT31 ; Enable override strapping feature. +*/ +#define FCH_MISC_REGC0 0xC0 // CPU_Pstate0 +/* +FCH_MISC_REGC0 EQU 0C0h + Core0_PState EQU BIT0+BIT1+BIT2 ; 000: P0 001: P1 010: P2 011: P3 100: P4 101: P5 110: P6 111: P7 + Core1_PState EQU BIT4+BIT5+BIT6 + Core2_PState EQU BIT8+BIT9+BIT10 + Core3_PState EQU BIT12+BIT13+BIT14 + Core4_PState EQU BIT16++BIT17+BIT18 + Core5_PState EQU BIT20+BIT21+BIT22 + Core6_PState EQU BIT24+BIT25+BIT26 + Core7_PState EQU BIT28+BIT29+BIT30 +*/ +#define FCH_MISC_REGC4 0xC4 // CPU_Pstate1 +/* +FCH_MISC_REGC4 EQU 0C4h + Core8_PState EQU BIT0+BIT1+BIT2 ; 000: P0 001: P1 010: P2 011: P3 100: P4 101: P5 110: P6 111: P7 + Core9_PState EQU BIT4+BIT5+BIT6 + Core10_PState EQU BIT8+BIT9+BIT10 + Core11_PState EQU BIT12+BIT13+BIT14 + Core12_PState EQU BIT16++BIT17+BIT18 + Core13_PState EQU BIT20+BIT21+BIT22 + Core14_PState EQU BIT24+BIT25+BIT26 + Core15_PState EQU BIT28+BIT29+BIT30 +*/ +#define FCH_MISC_REGD0 0xD0 // CPU_Cstate0 +/* +FCH_MISC_REGD0 EQU 0D0h + Core0_CState EQU BIT0+BIT1+BIT2 ; 000: C0 001: C1 010: C2 011: C3 100: C4 101: C5 110: C6 111: C7 + Core1_CState EQU BIT4+BIT5+BIT6 + Core2_CState EQU BIT8+BIT9+BIT10 + Core3_CState EQU BIT12+BIT13+BIT14 + Core4_CState EQU BIT16++BIT17+BIT18 + Core5_CState EQU BIT20+BIT21+BIT22 + Core6_CState EQU BIT24+BIT25+BIT26 + Core7_CState EQU BIT28+BIT29+BIT30 +*/ +#define FCH_MISC_REGD4 0xD4 // CPU_Cstate1 +/* +FCH_MISC_REGD4 EQU 0D4h + Core8_CState EQU BIT0+BIT1+BIT2 ; 000: C0 001: C1 010: C2 011: C3 100: C4 101: C5 110: C6 111: C7 + Core9_CState EQU BIT4+BIT5+BIT6 + Core10_CState EQU BIT8+BIT9+BIT10 + Core11_CState EQU BIT12+BIT13+BIT14 + Core12_CState EQU BIT16++BIT17+BIT18 + Core13_CState EQU BIT20+BIT21+BIT22 + Core14_CState EQU BIT24+BIT25+BIT26 + Core15_CState EQU BIT28+BIT29+BIT30 +*/ +#define FCH_MISC_REGF0 0xF0 // SataPortSts +/* +FCH_MISC_REGF0 EQU 0F0h + Port0Sts EQU BIT0 ; The selected status of Port 0. + Port1Sts EQU BIT1 ; The selected status of Port 1 + Port2Sts EQU BIT2 ; The selected status of Port 2. + Port3Sts EQU BIT3 ; The selected status of Port 3 + Port4Sts EQU BIT4 ; The selected status of Port 4. + Port5Sts EQU BIT5 ; The selected status of Port 5 + SataPortSel EQU BIT24+BIT25 ; 00 - Select "led" for Port 0 to 5 + ; 01 - Select "delete" for Port 0 to 5 + ; 10 - Select "err" for Port 0 to 5 + ; 11 - Select "led" for Port 0 to 5 +*/ + +// +// FCH MMIO Base (SERIAL_DEBUG_BASE) +// offset : 0x1000 +// +#define FCH_SDB_REG00 0x00 // +#define FCH_SDB_REG74 0x74 + + + + +#define FCH_IOMAP_REG70 0x070 // Nmi_Enable +#define FCH_IOMAP_REG71 0x071 // RtcDataPort +#define FCH_IOMAP_REG72 0x072 // AlternatRtcAddrPort +#define FCH_IOMAP_REG73 0x073 // AlternatRtcDataPort +#define FCH_IOMAP_REGC0 0x0C0 // Dma2_C4Addr +#define FCH_IOMAP_REGC2 0x0C2 // Dma2_C4Cnt +#define FCH_IOMAP_REGC4 0x0C4 // Dma2_C5Addr +#define FCH_IOMAP_REGC6 0x0C6 // Dma2_C5Cnt +#define FCH_IOMAP_REGC8 0x0C8 // Dma2_C6Addr +#define FCH_IOMAP_REGCA 0x0CA // Dma2_C6Cnt +#define FCH_IOMAP_REGCC 0x0CC // Dma2_C7Addr +#define FCH_IOMAP_REGCE 0x0CE // Dma2_C7Cnt +#define FCH_IOMAP_REGD0 0x0D0 // Dma_Status +#define FCH_IOMAP_REGD2 0x0D2 // Dma_WriteRest +#define FCH_IOMAP_REGD4 0x0D4 // Dma_WriteMask +#define FCH_IOMAP_REGD6 0x0D6 // Dma_WriteMode +#define FCH_IOMAP_REGD8 0x0D8 // Dma_Clear +#define FCH_IOMAP_REGDA 0x0DA // Dma_Clear +#define FCH_IOMAP_REGDC 0x0DC // Dma_ClrMask +#define FCH_IOMAP_REGDE 0x0DE // Dma_ClrMask +#define FCH_IOMAP_REGF0 0x0F0 // NCP_Error +#define FCH_IOMAP_REG40B 0x040B // DMA1_Extend +#define FCH_IOMAP_REG4D0 0x04D0 // IntrEdgeControl +#define FCH_IOMAP_REG4D6 0x04D6 // DMA2_Extend +#define FCH_IOMAP_REGC00 0x0C00 // Pci_Intr_Index +#define FCH_IOMAP_REGC01 0x0C01 // Pci_Intr_Data +#define FCH_IOMAP_REGC14 0x0C14 // Pci_Error +#define FCH_IOMAP_REGC50 0x0C50 // CMIndex +#define FCH_IOMAP_REGC51 0x0C51 // CMData +#define FCH_IOMAP_REGC52 0x0C52 // GpmPort +#define FCH_IOMAP_REGC6F 0x0C6F // Isa_Misc +#define FCH_IOMAP_REGCD0 0x0CD0 // PMio2_Index +#define FCH_IOMAP_REGCD1 0x0CD1 // PMio2_Data +#define FCH_IOMAP_REGCD4 0x0CD4 // BIOSRAM_Index +#define FCH_IOMAP_REGCD5 0x0CD5 // BIOSRAM_Data +#define FCH_IOMAP_REGCD6 0x0CD6 // PM_Index +#define FCH_IOMAP_REGCD7 0x0CD7 // PM_Data +#define FCH_IOMAP_REGCF9 0x0CF9 // CF9Rst reg + +#define FCH_IRQ_INTA 0x00 // INTA# +#define FCH_IRQ_INTB 0x01 // INTB# +#define FCH_IRQ_INTC 0x02 // INTC# +#define FCH_IRQ_INTD 0x03 // INTD# +#define FCH_IRQ_INTE 0x04 // INTE# +#define FCH_IRQ_INTF 0x05 // INTF# +#define FCH_IRQ_INTG 0x06 // INTG# +#define FCH_IRQ_INTH 0x07 // INTH# +#define FCH_IRQ_SCI 0x10 // SCI +#define FCH_IRQ_SMBUS0 0x11 // SMBUS0 +#define FCH_IRQ_ASF 0x12 // ASF +#define FCH_IRQ_HDAUDIO 0x13 // HD Audio +#define FCH_IRQ_FC 0x14 // FC +#define FCH_IRQ_GEC 0x15 // GEC +#define FCH_IRQ_SD 0x17 // SD +#define FCH_IRQ_IMCINT0 0x20 // IMC INT0 +#define FCH_IRQ_IMCINT1 0x21 // IMC INT1 +#define FCH_IRQ_IMCINT2 0x22 // IMC INT2 +#define FCH_IRQ_IMCINT3 0x23 // IMC INT3 +#define FCH_IRQ_IMCINT4 0x24 // IMC INT4 +#define FCH_IRQ_IMCINT5 0x25 // IMC INT5 +#define FCH_IRQ_USB18INTA 0x30 // Dev 18 (USB) INTA# +#define FCH_IRQ_USB18INTB 0x31 // Dev 18 (USB) INTB# +#define FCH_IRQ_USB19INTA 0x32 // Dev 19 (USB) INTA# +#define FCH_IRQ_USB19INTB 0x33 // Dev 19 (USB) INTB# +#define FCH_IRQ_USB22INTA 0x34 // Dev 22 (USB) INTA# +#define FCH_IRQ_USB22INTB 0x35 // Dev 22 (USB) INTB# +#define FCH_IRQ_USB20INTC 0x36 // Dev 20 (USB) INTC# +#define FCH_IRQ_IDE 0x40 // IDE pci interrupt +#define FCH_IRQ_SATA 0x41 // SATA pci interrupt +#define FCH_IRQ_GPPINT0 0x50 // Gpp Int0 +#define FCH_IRQ_GPPINT1 0x51 // Gpp Int1 +#define FCH_IRQ_GPPINT2 0x52 // Gpp Int2 +#define FCH_IRQ_GPPINT3 0x53 // Gpp Int3 +#define FCH_IRQ_IOAPIC 0x80 // Select IRQ routing to IoApic mode +#define FCH_IRQ_PIC 0x00 // Select IRQ routing to PIC mode + +#define FCH_SPI_MMIO_REG00 0x00 //SPI_ +#define FCH_SPI_MMIO_REG0C 0x0C //SPI_Cntrl1 Register +#define FCH_SPI_MMIO_REG1C 0x1C // + +#define FCH_SPI_MODE_FAST 0x7 // +#define FCH_SPI_MODE_NORMAL 0x6 // +#define FCH_SPI_MODE_QUAL_144 0x5 // +#define FCH_SPI_MODE_QUAL_122 0x4 // +#define FCH_SPI_MODE_QUAL_114 0x3 // +#define FCH_SPI_MODE_QUAL_112 0x2 // + +#define AMD_NB_REG78 0x78 +#define AMD_NB_SCRATCH AMD_NB_REG78 +#define MailBoxPort 0x3E + +#define MAX_LT_POLLINGS 0x4000 +#define SMI_TIMER_ENABLE BIT15 + + +#define ACPIMMIO32(x) (*(volatile UINT32*)(UINTN)(x)) +#define ACPIMMIO16(x) (*(volatile UINT16*)(UINTN)(x)) +#define ACPIMMIO8(x) (*(volatile UINT8*)(UINTN)(x)) + +#define XHCI_ACPI_MMIO_AMD_REG00 0x00 +#define U3PLL_LOCK BIT7 +#define U3PLL_RESET BIT8 +#define U3PHY_RESET BIT9 +#define U3CORE_RESET BIT10 +#define XHC0_FUNC_RESET BIT11 +#define XHC1_FUNC_RESET BIT12 + +#define XHCI_ACPI_MMIO_AMD_REG04 0x04 +#define XHCI_ACPI_MMIO_AMD_REG08 0x08 +#define XHCI_ACPI_MMIO_AMD_REG20 0x20 +#define XHCI_ACPI_MMIO_AMD_REG90 0x90 // adaptation timer settings +#define XHCI_ACPI_MMIO_AMD_REG98 0x98 +#define XHCI_ACPI_MMIO_AMD_REGA0 0xA0 // BAR 0 +#define XHCI_ACPI_MMIO_AMD_REGA4 0xA4 // BAR 1 +#define XHCI_ACPI_MMIO_AMD_REGA8 0xA8 // BAR 2 +#define XHCI_ACPI_MMIO_AMD_REGB0 0xB0 // SPI_Valid_Base. +#define XHCI_ACPI_MMIO_AMD_REGC0 0xC0 // Firmware starting offset for coping +#define XHCI_ACPI_MMIO_AMD_REGB4 0xB4 +#define XHCI_ACPI_MMIO_AMD_REGD0 0xD0 + +#define FCH_XHCI_REG48 0x48 // XHCI IND_REG Index registers +#define FCH_XHCI_REG4C 0x4C // XHCI IND_REG Data registers + +#define FCH_XHCI_IND60_BASE 0x40000000ul // + +#define FCH_XHCI_IND60_REG00 FCH_XHCI_IND60_BASE + 0x00 // +#define FCH_XHCI_IND60_REG04 FCH_XHCI_IND60_BASE + 0x04 // +#define FCH_XHCI_IND60_REG08 FCH_XHCI_IND60_BASE + 0x08 // +#define FCH_XHCI_IND60_REG0C FCH_XHCI_IND60_BASE + 0x0C // +#define FCH_XHCI_IND60_REG18 FCH_XHCI_IND60_BASE + 0x18 // + + +#define FCH_XHCI_IND_REG00 0x00 // +#define FCH_XHCI_IND_REG04 0x04 // +#define FCH_XHCI_IND_REG88 0x88 // +#define FCH_XHCI_IND_REG94 0x94 // adaptation mode settings +#define FCH_XHCI_IND_REG98 0x98 // CR phase and frequency filter settings +#define FCH_XHCI_IND_REGC8 0xC8 // +#define FCH_XHCI_IND_REGD4 0xD4 // adaptation mode settings +#define FCH_XHCI_IND_REGD8 0xD8 // CR phase and frequency filter settings + +#define SPI_HEAD_LENGTH 0x0E +#define SPI_BAR0_VLD 0x01 +#define SPI_BASE0 (0x00 << 7) +#define SPI_BAR1_VLD (0x01 << 8) +#define SPI_BASE1 (SPI_HEAD_LENGTH << 10) +#define SPI_BAR2_VLD (0x01 << 16) +#define SPI_BASE2(x) ((SPI_HEAD_LENGTH + ACPIMMIO16(x)) << 18) + +#define FW_TO_SIGADDR_OFFSET 0x0C +#define BCD_ADDR_OFFSET 0x02 +#define BCD_SIZE_OFFSET 0x04 +#define FW_ADDR_OFFSET 0x06 +#define FW_SIZE_OFFSET 0x08 +#define ACD_ADDR_OFFSET 0x0A +#define ACD_SIZE_OFFSET 0x0C + +#define PKT_DATA_REG ACPI_MMIO_BASE + GFX_DAC_BASE + 0x00 +#define PKT_LEN_REG ACPI_MMIO_BASE + GFX_DAC_BASE + 0x14 +#define PKT_CTRL_REG ACPI_MMIO_BASE + GFX_DAC_BASE + 0x15 +#define EFUS_DAC_ADJUSTMENT_CONTROL 0x850A8ul +#define BGADJ 0x1F +#define DACADJ 0x1B +#define EFUS_DAC_ADJUSTMENT_CONTROL_DATA (BGADJ + (DACADJ << 8) + BIT16 ) + +#ifndef FCH_DEADLOOP + #define FCH_DEADLOOP() { volatile UINTN __i; __i = 1; while (__i); } +#endif + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/FchPage.h b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/FchPage.h new file mode 100644 index 0000000..9d53621 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/FchPage.h @@ -0,0 +1,87 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Create outline and references for FCH Component mainpage documentation. + * + * Design guides, maintenance guides, and general documentation, are + * collected using this file onto the documentation mainpage. + * This file contains doxygen comment blocks, only. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Documentation + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/** + * @page fchmain FCH Component Documentation + * + * Additional documentation for the FCH component consists of + * + * - Maintenance Guides: + * - @subpage fchinitguide "FCH Implementation Guide" + * - @subpage fchauxguide "FCH UEFI Auxiliary driver" + * - @subpage fchhwmguide "FCH Hardware Monitor driver" + * - add here >>> + * - Design Guides: + * - add here >>> + * + */ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h new file mode 100644 index 0000000..8e5072c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h @@ -0,0 +1,145 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH platform definition + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#ifndef _FCH_PLATFORM_H_ +#define _FCH_PLATFORM_H_ + +#define MAX_SATA_PORTS 8 + +#include "AGESA.h" + +#ifndef FCHOEM_ACPI_RESTORE_SWSMI + #define FCHOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3 + #define FCHOEM_AFTER_PCI_RESTORE_SWSMI 0xD4 + #define FCHOEM_ENABLE_ACPI_SWSMI 0xA0 + #define FCHOEM_DISABLE_ACPI_SWSMI 0xA1 + #define FCHOEM_START_TIMER_SMI 0xBC + #define FCHOEM_STOP_TIMER_SMI 0xBD +#endif + +#ifndef FCHOEM_SPI_UNLOCK_SWSMI + #define FCHOEM_SPI_UNLOCK_SWSMI 0xAA +#endif +#ifndef FCHOEM_SPI_LOCK_SWSMI + #define FCHOEM_SPI_LOCK_SWSMI 0xAB +#endif + +#ifndef FCHOEM_ACPI_TABLE_RANGE_LOW + #define FCHOEM_ACPI_TABLE_RANGE_LOW 0xE0000ul +#endif + +#ifndef FCHOEM_ACPI_TABLE_RANGE_HIGH + #define FCHOEM_ACPI_TABLE_RANGE_HIGH 0xFFFF0ul +#endif + +#ifndef FCHOEM_ACPI_BYTE_CHECHSUM + #define FCHOEM_ACPI_BYTE_CHECHSUM 0x100 +#endif + +#ifndef FCHOEM_IO_DELAY_PORT + #define FCHOEM_IO_DELAY_PORT 0x80 +#endif + +#ifndef FCHOEM_OUTPUT_DEBUG_PORT + #define FCHOEM_OUTPUT_DEBUG_PORT 0x80 +#endif + +#define FCH_PCIRST_BASE_IO 0xCF9 +#define FCH_PCI_RESET_COMMAND06 0x06 +#define FCH_PCI_RESET_COMMAND0E 0x0E +#define FCH_KBDRST_BASE_IO 0x64 +#define FCH_KBC_RESET_COMMAND 0xFE +#define FCH_ROMSIG_BASE_IO 0x20000l +#define FCH_ROMSIG_SIGNATURE 0x55AA55AAul +#define FCH_MAX_TIMER 0xFFFFFFFFul +#define FCH_GEC_INTERNAL_REG 0x6804 +#define FCH_HPET_REG_MASK 0xFFFFF800ul +#define FCH_FAKE_USB_BAR_ADDRESS 0x58830000ul + + +#ifndef FCHOEM_ELAPSED_TIME_UNIT + #define FCHOEM_ELAPSED_TIME_UNIT 28 +#endif + +#ifndef FCHOEM_ELAPSED_TIME_DIVIDER + #define FCHOEM_ELAPSED_TIME_DIVIDER 100 +#endif + +#include "Fch.h" +#include "amdlib.h" +#include "FchCommonCfg.h" +#include "AcpiLib.h" +#include "FchDef.h" +#include "FchBiosRamUsage.h" +#include "AmdFch.h" + +extern BUILD_OPT_CFG UserOptions; + +#endif // _FCH_PLATFORM_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/Family/Hudson2/Hudson2GecEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/Family/Hudson2/Hudson2GecEnvService.c new file mode 100644 index 0000000..01aeae9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/Family/Hudson2/Hudson2GecEnvService.c @@ -0,0 +1,130 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH GEC controller + * + * Init GEC features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ + +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_GEC_FAMILY_HUDSON2_HUDSON2GECENVSERVICE_FILECODE + +/** + * FchInitGecController - Config GEC controller + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitGecController ( + IN VOID *FchDataPtr + ) +{ + UINT8 FchSBGecDebugBus; + UINT8 FchSBGecPwr; + FCH_DATA_BLOCK *LocalCfgPtr; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + + FchSBGecDebugBus = (UINT8) LocalCfgPtr->Gec.GecDebugBus; + FchSBGecPwr = (UINT8) LocalCfgPtr->Gec.GecPowerPolicy; + + if ( LocalCfgPtr->Misc.Cg2Pll == 1 ) { + LocalCfgPtr->Gec.GecEnable = FALSE; + } + + if ( LocalCfgPtr->Gec.GecEnable == TRUE) { + // + // GEC Enabled + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xF6 , AccessWidth8, (UINT32)~BIT0, 0x00); + + RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GEVENT_REG11, AccessWidth8, 0, 0x00); + RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GEVENT_REG21, AccessWidth8, 0, 0x01); + RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG166, AccessWidth8, 0, 0x01); + RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0xB5 , AccessWidth8, 0, 0x01); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF8, AccessWidth8, (UINT32)~(BIT5 + BIT6), (UINT8) ((FchSBGecPwr) << 5)); + + if (FchSBGecDebugBus == 1) { + // + // GEC Debug Bus Enabled + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF6, AccessWidth8, (UINT32)~BIT3, BIT3); + } else { + // + // GEC Debug Bus Disabled + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF6, AccessWidth8, (UINT32)~BIT3, 0x00); + } + } else { + // + // GEC Disabled + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF6, AccessWidth8, (UINT32)~BIT0, BIT0); + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/Family/Hudson2/Hudson2GecService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/Family/Hudson2/Hudson2GecService.c new file mode 100644 index 0000000..ccbeec2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/Family/Hudson2/Hudson2GecService.c @@ -0,0 +1,105 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH GEC controller + * + * Init GEC features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ + +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_GEC_FAMILY_HUDSON2_HUDSON2GECSERVICE_FILECODE + +/** + * FchSwInitGecBootRom - Config GEC Boot ROM by Platform define + * ROM address + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchSwInitGecBootRom ( + IN VOID *FchDataPtr + ) +{ + VOID* GecRomAddress; + VOID* GecShadowRomAddress; + UINT32 Temp; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + if ( !LocalCfgPtr->Gec.PtrDynamicGecRomAddress == 0 ) { + GecRomAddress = LocalCfgPtr->Gec.PtrDynamicGecRomAddress; + GecShadowRomAddress = (VOID*) (UINTN) LocalCfgPtr->Gec.GecShadowRomBase; + FchCopyMem (GecShadowRomAddress, GecRomAddress, 0x100); + ReadPci ((GEC_BUS_DEV_FUN << 16) + FCH_GEC_REG10, AccessWidth32, &Temp, StdHeader); + Temp = Temp & 0xFFFFFFF0; + RwMem (Temp + FCH_GEC_INTERNAL_REG, AccessWidth32, 0, BIT0 + BIT29); + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecEnv.c new file mode 100644 index 0000000..5a6c27f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecEnv.c @@ -0,0 +1,92 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH GEC controller + * + * Init GEC features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ + +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_GEC_GECENV_FILECODE + + +/** + * FchInitEnvGec - Config GEC controller before PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvGec ( + IN VOID *FchDataPtr + ) +{ + FchInitGecController (FchDataPtr); +} + + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecLate.c new file mode 100644 index 0000000..1178ebf --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecLate.c @@ -0,0 +1,88 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH GEC controller + * + * Init GEC features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ + +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_GEC_GECLATE_FILECODE + +/** + * FchInitLateGec - Prepare GEC controller to boot to OS. + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitLateGec ( + IN VOID *FchDataPtr + ) +{ +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecMid.c new file mode 100644 index 0000000..11cba8e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecMid.c @@ -0,0 +1,90 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH GEC controller + * + * Init GEC features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ + +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_GEC_GECMID_FILECODE + + + +/** + * FchInitMidGec - Config GEC controller after PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidGec ( + IN VOID *FchDataPtr + ) +{ + FchSwInitGecBootRom (FchDataPtr); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecReset.c new file mode 100644 index 0000000..a3ce629 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Gec/GecReset.c @@ -0,0 +1,94 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH GEC controller + * + * Init Gec Controller features (PEI phase). + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_GEC_GECRESET_FILECODE + +/** + * FchInitResetGec - Config Gec controller during Power-On + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitResetGec ( + IN VOID *FchDataPtr + ) +{ + // + // Init Gec SHADOW Rom Base Address + // + RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG9C, AccessWidth32, 0, \ + UserOptions.FchBldCfg->CfgGecShadowRomBase + 1, ((FCH_RESET_DATA_BLOCK *) FchDataPtr)->StdHeader); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c new file mode 100644 index 0000000..4d8a917 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c @@ -0,0 +1,586 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch HwAcpi controller + * + * Init HwAcpi Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "amdlib.h" +#include "cpuServices.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPIENVSERVICE_FILECODE + +#define AMD_CPUID_APICID_LPC_BID 0x00000001ul // Local APIC ID, Logical Processor Count, Brand ID + +/** + * FchInitEnvHwAcpiMmioTable - Fch ACPI MMIO initial + * during POST. + * + */ +ACPI_REG_WRITE FchHudson2InitEnvHwAcpiMmioTable[] = +{ + {00, 00, 0xB0, 0xAC}, /// Signature + + // + // HPET workaround + // + {PMIO_BASE >> 8, FCH_PMIOA_REG54 + 3, 0xFC, BIT0 + BIT1}, + {PMIO_BASE >> 8, FCH_PMIOA_REG54 + 2, 0x7F, BIT7}, + {PMIO_BASE >> 8, FCH_PMIOA_REG54 + 2, 0x7F, 0x00}, + // + // Enable Hudson-2 A12 ACPI bits at PMIO 0xC0 [30, 10:3] + // ClrAllStsInThermalEvent 3 Set to 1 to allow ASF remote power down/power cycle, Thermal event, Fan slow event to clear all the Gevent status and enabled bits. The bit should be set to 1 all the time. + // UsbGoodClkDlyEn 4 Set to 1 to delay de-assertion of Usb clk by 6 Osc clk. The bit should be set to 1 all the time. + // ForceNBCPUPwr 5 Set to 1 to force CPU pwrGood to be toggled along with NB pwrGood. + // MergeUsbPerReq 6 Set to 1 to merge usb perdical traffic into usb request as one of break event. + // IMCWatchDogRstEn 7 Set to 1 to allow IMC watchdog timer to reset entire acpi block. The bit should be set to 1 when IMC is enabled. + // GeventStsFixEn 8 1: Gevent status is not reset by its enable bit. 0: Gevent status is reset by its enable bit. + // PmeTimerFixEn 9 Set to 1 to reset Pme Timer when going to sleep state. + // UserRst2EcEn 10 Set to 1 to route user reset event to Ec. The bit should be set to 1 when IMC is enabled. + // Smbus0ClkSEn 30 Set to 1 to enable SMBus0 controller clock stretch support. + // + {PMIO_BASE >> 8, FCH_PMIOA_REGC4, (UINT8)~BIT2, BIT2}, + {PMIO_BASE >> 8, FCH_PMIOA_REGC0, 0, 0xF9}, + {PMIO_BASE >> 8, FCH_PMIOA_REGC0 + 1, 0x04, 0x07}, + // + // RtcSts 19-17 RTC_STS set only in Sleep State. + // GppPme 20 Set to 1 to enable PME request from SB GPP. + // Pcireset 22 Set to 1 to allow SW to reset PCIe. + // + {PMIO_BASE >> 8, 0xC2 , 0x20, 0x58}, + {PMIO_BASE >> 8, 0xC2 + 1, 0, 0x40}, + {PMIO_BASE >> 8, 0xC2 , (UINT8)~(BIT4), BIT4}, + + {PMIO_BASE >> 8, FCH_PMIOA_REGCC, 0xF8, 0x01}, + {PMIO_BASE >> 8, FCH_PMIOA_REG74, 0x00, BIT0 + BIT1 + BIT2 + BIT4}, + {PMIO_BASE >> 8, FCH_PMIOA_REG74 + 3, (UINT8)~BIT5, 0}, + {PMIO_BASE >> 8, 0xDE + 1, (UINT8)~(BIT0 + BIT1), BIT0 + BIT1}, + {PMIO_BASE >> 8, 0xDE , (UINT8)~BIT4, BIT4}, + {PMIO_BASE >> 8, FCH_PMIOA_REGBA, (UINT8)~BIT3, BIT3}, + {PMIO_BASE >> 8, FCH_PMIOA_REGBA + 1, (UINT8)~BIT6, BIT6}, + {PMIO_BASE >> 8, FCH_PMIOA_REGBC, (UINT8)~BIT1, BIT1}, + {PMIO_BASE >> 8, FCH_PMIOA_REGED, (UINT8)~(BIT0 + BIT1), 0}, + {PMIO_BASE >> 8, 0xDC , 0x7C, BIT0}, /// Hiding Flash Controller PM_IO 0xDC[7] = 0x0 & PM_IO 0xDC [1:0]=0x01 + {PMIO_BASE >> 8, FCH_PMIOA_REGBF, (UINT8)~BIT0, 0}, + {PMIO_BASE >> 8, FCH_PMIOA_REGBE, (UINT8)~BIT0, BIT0}, + + {SMI_BASE >> 8, 0x41 , 0, 1}, + {SMI_BASE >> 8, 0x43 , 0, 3}, + {SMI_BASE >> 8, 0x44 , 0, 4}, + {SMI_BASE >> 8, 0x45 , 0, 5}, + {SMI_BASE >> 8, 0x46 , 0, 6}, + {SMI_BASE >> 8, 0x57 , 0, 23}, + {SMI_BASE >> 8, 0x78 , 0, 11}, + {SMI_BASE >> 8, 0x79 , 0, 11}, + {SMI_BASE >> 8, 0x58 , 0, 11}, + {SMI_BASE >> 8, 0x59 , 0, 11}, + {SMI_BASE >> 8, 0x5A , 0, 11}, + {SMI_BASE >> 8, 0x5B , 0, 11}, + {SMI_BASE >> 8, 0x68 , 0, 12}, + {SMI_BASE >> 8, 0x6C , 0, 13}, + {SMI_BASE >> 8, 0x5C , 0, 15}, + {SMI_BASE >> 8, 0x5D , 0, 16}, + {SMI_BASE >> 8, 0x5E , 0, 17}, + {SMI_BASE >> 8, 0x5F , 0, 18}, + {SMI_BASE >> 8, 0x67 , 0, 19}, + {SMI_BASE >> 8, 0x6A , 0, 28}, + {SMI_BASE >> 8, 0x48 , 0, 24}, + {SMI_BASE >> 8, 0x64 , 0, 27}, + {SMI_BASE >> 8, 0x65 , 0, 30}, + {SMI_BASE >> 8, 0x66 , 0, 31}, + {SMI_BASE >> 8, FCH_SMI_REG08, 0xE7, 0}, + {SMI_BASE >> 8, FCH_SMI_REG0C + 2, (UINT8)~BIT3, BIT3}, + {SMI_BASE >> 8, 0x70 , 0, 9}, + {SMI_BASE >> 8, FCH_SMI_REG3C, 0, BIT6}, + {SMI_BASE >> 8, 0x84 + 2, 0, BIT7}, + + // + // CG PLL CMOX Clock Driver Setting for power saving + // + {MISC_BASE >> 8, FCH_MISC_REG18 + 0x06, 0, 0xE0}, + {MISC_BASE >> 8, FCH_MISC_REG18 + 0x07, 0, 0x1F}, + + {MISC_BASE >> 8, 0x50 + 3, (UINT8)~BIT5, BIT5}, + {MISC_BASE >> 8, 0x50 + 2, (UINT8)~BIT3, BIT3}, + //{SERIAL_DEBUG_BASE >> 8, FCH_SDB_REG74, 0, 0}, + {0xFF, 0xFF, 0xFF, 0xFF}, +}; + +/** + * FchHudson2InitEnvHwAcpiPciTable - PCI device registers initial + * during early POST. + * + */ +REG8_MASK FchHudson2InitEnvHwAcpiPciTable[] = +{ + // + // SMBUS Device (Bus 0, Dev 20, Func 0) + // + {0x00, SMBUS_BUS_DEV_FUN, 0}, + {FCH_CFG_REG10, 0X00, (FCH_VERSION & 0xFF)}, ///Program the version information + {FCH_CFG_REG11, 0X00, (FCH_VERSION >> 8)}, + {0xFF, 0xFF, 0xFF}, +}; + + +/** + * ProgramPFchAcpiMmio - Config HwAcpi MMIO registers + * Acpi S3 resume won't execute this procedure (POST only) + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +ProgramEnvPFchAcpiMmio ( + IN VOID *FchDataPtr + ) +{ + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE*) (&FchHudson2InitEnvHwAcpiMmioTable[0]), StdHeader); +} + +/** + * ProgramFchEnvHwAcpiPciReg - Config HwAcpi PCI controller + * before PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +ProgramFchEnvHwAcpiPciReg ( + IN VOID *FchDataPtr + ) +{ + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + // + // FCH CFG programming + // + // Make BAR registers of smbus visible. + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8 + 1, AccessWidth8, (UINT8)~BIT6, 0); + + // + //Early post initialization of pci config space + // + ProgramPciByteTable ((REG8_MASK*) (&FchHudson2InitEnvHwAcpiPciTable[0]), sizeof (FchHudson2InitEnvHwAcpiPciTable) / sizeof (REG8_MASK), StdHeader); + + if ( LocalCfgPtr->Smbus.SmbusSsid != 0 ) { + RwPci ((SMBUS_BUS_DEV_FUN << 16) + FCH_CFG_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Smbus.SmbusSsid, StdHeader); + } + + // + //Make BAR registers of smbus invisible. + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8 + 1, AccessWidth8, (UINT8)~BIT6, BIT6); +} + +/** + * FchVgaInit - Config VGA CODEC + * + * @param[in] VOID empty + * + */ +VOID +FchVgaInit ( + OUT VOID + ) +{ + // + // Cobia_Nutmeg_DP-VGA Electrical SI validation_Lower RGB Luminance level BGADJ=0x1F & DACADJ=0x1B + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC4, AccessWidth8, 0xff, BIT5 ); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xD8 , AccessWidth8, 0x00, 0x17 ); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xD9 , AccessWidth8, 0x00, ((BGADJ << 2) + (((DACADJ & 0xf0) >> 4) & 0x3))); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xD8 , AccessWidth8, 0x00, 0x16 ); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xD9 , AccessWidth8, 0x0f, ((DACADJ & 0x0f) << 4)); + + *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x00))) = (0x08 << 4) + (UINT8) ((EFUS_DAC_ADJUSTMENT_CONTROL >> 16) & 0xff); + *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x01))) = (UINT8) ((EFUS_DAC_ADJUSTMENT_CONTROL >> 8) & 0xff); + *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x02))) = (UINT8) ((EFUS_DAC_ADJUSTMENT_CONTROL >> 0) & 0xff); + *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x03))) = (UINT8) (0x03); + *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x04))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 0) & 0xff); + *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x05))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 8) & 0xff); + *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x06))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 16) & 0xff); + *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x07))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 24) & 0xff); + *((UINT8*) ((UINTN)(PKT_LEN_REG))) = 0x08; + *((UINT8*) ((UINTN)(PKT_CTRL_REG))) = 0x01; +} + +/** + * ProgramSpecificFchInitEnvAcpiMmio - Config HwAcpi MMIO before + * PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +ProgramSpecificFchInitEnvAcpiMmio ( + IN VOID *FchDataPtr + ) +{ + CPUID_DATA CpuId; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + // + // Set ASF SMBUS master function enabled here (temporary) + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0x28 , AccessWidth16, (UINT32)~(BIT0 + BIT2), BIT0 + BIT2); + +#ifdef ACPI_SLEEP_TRAP + // + // Set SLP_TYPE as SMI event + // + RwMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0, AccessWidth8, (UINT32)~(BIT2 + BIT3), BIT2); + + // + // Disabled SLP function for S1/S3/S4/S5 + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBE, AccessWidth8, (UINT32)~BIT5, 0x00); + + // + // Set S state transition disabled (BIT0) force ACPI to send SMI message when writing to SLP_TYP Acpi register. (BIT1) + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG08 + 3, AccessWidth8, (UINT32)~(BIT0 + BIT1), BIT1); + + // + // Enabled Global Smi ( BIT7 clear as 0 to enable ) + // + RwMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG98 + 3 , AccessWidth8, (UINT32)~BIT7, 0x00); +#endif + + // + // Set Stutter timer settings + // + LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuId, StdHeader); + + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80 + 1, AccessWidth8, (UINT32)~(BIT3 + BIT4), BIT3 + BIT4); + + // + // Set LDTSTP# duration to 10us for Specific CPU, or when HT link is 200MHz + // + if ((LocalCfgPtr->HwAcpi.AnyHt200MhzLink) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100080) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100090) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x1000A0)) { + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG94, AccessWidth8, 0, 0x0A); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80 + 3, AccessWidth8, 0xFE, 0x28); + } else { + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG94, AccessWidth8, 0, 0x01); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80 + 3, AccessWidth8, 0xFE, 0x20); + } + + // + // SSC will provide better jitter margin + // + RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x13, AccessWidth8, 0xFC, 0x01); + // + // Ac Loss Control + // + AcLossControl ((UINT8) LocalCfgPtr->HwAcpi.PwrFailShadow); + // + //FCH VGA Init + // + FchVgaInit (); + + // + // 2.16 Enable DMAACTIVE + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7F, AccessWidth8, 0xFE, 0x01); + + // + // Set ACPIMMIO by OEM Input table + // + ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE *) (LocalCfgPtr->HwAcpi.OemProgrammingTablePtr), StdHeader); +} + +/** + * ValidateFchVariant - Validate FCH Variant + * + * + * + * @param[in] FchDataPtr + * + */ +VOID +ValidateFchVariant ( + IN VOID *FchDataPtr + ) +{ + UINT8 XhciEfuse; + UINT8 PcieEfuse; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + switch ( LocalCfgPtr->Misc.FchVariant ) { + case FCH_M3T: + //Disable Devices for M3T + LocalCfgPtr->Gec.GecEnable = 1; + LocalCfgPtr->Hwm.HwMonitorEnable = 0; + LocalCfgPtr->Sd.SdConfig = 0; + LocalCfgPtr->Ir.IrConfig = 0; + break; + + default: + break; + } + + // add Efuse checking for Xhci enable/disable + XhciEfuse = XHCI_EFUSE_LOCATION; + GetEfuseStatus (&XhciEfuse, StdHeader); + if ((XhciEfuse & (BIT0 + BIT1)) == (BIT0 + BIT1)) { + LocalCfgPtr->Usb.Xhci0Enable = 0; + LocalCfgPtr->Usb.Xhci1Enable = 0; + } + + // add Efuse checking for PCIE Gen2 enable + PcieEfuse = PCIE_FORCE_GEN1_EFUSE_LOCATION; + GetEfuseStatus (&PcieEfuse, StdHeader); + if ( PcieEfuse & BIT0 ) { + LocalCfgPtr->Gpp.GppGen2 = 0; + } +} + +/** + * IsExternalClockMode - Is External Clock Mode? + * + * + * @retval TRUE or FALSE + * + */ +BOOLEAN +IsExternalClockMode ( + IN VOID *FchDataPtr + ) +{ + UINT8 MISC80; + ReadMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80, AccessWidth8, &MISC80); + return ( (BOOLEAN) ((MISC80 & BIT4) == 0) ); +} + + +/** + * ProgramFchEnvSpreadSpectrum - Config SpreadSpectrum before + * PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +ProgramFchEnvSpreadSpectrum ( + IN VOID *FchDataPtr + ) +{ + UINT8 PortStatus; + UINT8 FchSpreadSpectrum; + + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + FchSpreadSpectrum = LocalCfgPtr->HwAcpi.SpreadSpectrum; + + if ((FchSpreadSpectrum > 0) && !(IsExternalClockMode (FchDataPtr))) { + RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x40, AccessWidth32, (UINT32) (~(0x1 << 25)), (0x1 << 25)); + RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth32, (UINT32) (~(0x1 << 0)), (0x0 << 0)); + RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x18, AccessWidth32, (UINT32) (~(0x7FF << 5)), (0x318 << 5)); + RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x18, AccessWidth32, (UINT32) (~(0xF << 16)), (0x0 << 16)); + RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccessWidth32, (UINT32) (~(0xFFFF << 8)), (0x6F83 << 8)); + RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccessWidth32, (UINT32) (~(0xFF << 0)), (0x90 << 0)); + RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x1C, AccessWidth32, (UINT32) (~(0x3F << 0)), (0x0 << 0)); + RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth32, (UINT32) (~(0xF << 28)), (0x7 << 28)); + RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth32, (UINT32) (~(0x1 << 7)), (0x0 << 8)); + RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth32, (UINT32) (~(0x1 << 8)), (0x1 << 8)); + RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccessWidth32, (UINT32) (~(0x3 << 24)), (0x1 << 24)); + + RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG08, AccessWidth8, 0xFE, 0x01); + } else { + RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG08, AccessWidth8, 0xFE, 0x00); + } + + // + // PLL 100Mhz Reference Clock Buffer setting for internal clock generator mode (BIT5) + // OSC Clock setting for internal clock generator mode (BIT6) + // + GetChipSysMode (&PortStatus, StdHeader); + if ( ((PortStatus & ChipSysIntClkGen) == ChipSysIntClkGen) ) { + RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x04 + 1, AccessWidth8, (UINT32)~(BIT5 + BIT6), BIT5 + BIT6); + } +} + +/** + * TurnOffCG2 + * + * + * @retval VOID + * + */ +VOID +TurnOffCG2 ( + OUT VOID + ) +{ + RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x40, AccessWidth8, (UINT32)~BIT6, 0); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xDA , AccessWidth8, 0x0F, 0xA0); + RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0x41, AccessWidth8, (UINT32)~(BIT1 + BIT0), (BIT1 + BIT0)); + RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x41, AccessWidth8, (UINT32)~( BIT4), (BIT4)); + RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x41, AccessWidth8, (UINT32)~(BIT6), (BIT6)); + RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth8, (UINT32)~BIT6, BIT6); + RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x1C, AccessWidth8, (UINT32)~BIT6, BIT6); +} + +/** + * BackUpCG2 + * + * + * @retval VOID + * + */ +VOID +BackUpCG2 ( + OUT VOID + ) +{ + UINT8 Byte; + ReadMem (ACPI_MMIO_BASE + MISC_BASE + 0x1C, AccessWidth8, &Byte); + if (Byte & BIT6) { + RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x41, AccessWidth8, (UINT32)~(BIT6), (0)); + } +} + +/** + * HpetInit - Program Fch HPET function + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +HpetInit ( + IN VOID *FchDataPtr + ) +{ + DESCRIPTION_HEADER *HpetTable; + UINT8 FchHpetTimer; + UINT8 FchHpetMsiDis; + FCH_DATA_BLOCK *LocalCfgPtr; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + FchHpetTimer = (UINT8) LocalCfgPtr->Hpet.HpetEnable; + FchHpetMsiDis = (UINT8) LocalCfgPtr->Hpet.HpetMsiDis; + + HpetTable = NULL; + if ( FchHpetTimer == TRUE ) { + // + //Program the HPET BAR address + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG50, AccessWidth32, FCH_HPET_REG_MASK, LocalCfgPtr->Hpet.HpetBase); + + // + //Enabling decoding of HPET MMIO + //Enable HPET MSI support + //Enable High Precision Event Timer (also called Multimedia Timer) interrupt + // + if ( FchHpetMsiDis == FALSE ) { + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG50, AccessWidth32, FCH_HPET_REG_MASK, BIT0 + BIT1 + BIT2 + BIT3 + BIT4); +#ifdef FCH_TIMER_TICK_INTERVAL_WA + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG50, AccessWidth32, FCH_HPET_REG_MASK, BIT0 + BIT1); +#endif + } else { + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG50, AccessWidth32, FCH_HPET_REG_MASK, BIT0 + BIT1); + } + + } else { + if ( ! (LocalCfgPtr->Misc.S3Resume) ) { + HpetTable = (DESCRIPTION_HEADER*) AcpiLocateTable (Int32FromChar('H','P','E','T')); /* 'TEPH' */ + } + if ( HpetTable != NULL ) { + HpetTable->Signature = Int32FromChar('T','E','P','H'); /* 'HPET' */ + } + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c new file mode 100644 index 0000000..ee19fb9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c @@ -0,0 +1,315 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch HwAcpi controller + * + * Init HwAcpi Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuServices.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPILATESERVICE_FILECODE + +#define AMD_CPUID_APICID_LPC_BID 0x00000001ul // Local APIC ID, Logical Processor Count, Brand ID + +/** + * C3PopupSetting - Program Fch C state function + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +C3PopupSetting ( + IN VOID *FchDataPtr + ) +{ +#define NON_SUPPORT_PREVIOUS_C3 TRUE +#ifndef NON_SUPPORT_PREVIOUS_C3 + UINT32 Value; + BOOLEAN ProcessorPresent; + + // + // C-State and VID/FID Change + // + ProcessorPresent = GetActiveCoresInGivenSocket (0, &Value, ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader); + + if (ProcessorPresent && (Value > 1)) { + // + //PM 0x80[2]=1, For system with dual core CPU, set this bit to 1 to automatically clear BM_STS when the C3 state is being initiated. + //PM 0x80[1]=1, For system with dual core CPU, set this bit to 1 and BM_STS will cause C3 to wakeup regardless of BM_RLD + //PM 0x7E[6]=1, Enable pop-up for C3. For internal bus mastering or BmReq# from the NB, the FCH will de-assert + //LDTSTP# (pop-up) to allow DMA traffic, then assert LDTSTP# again after some idle time. + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth8, (UINT32)~(BIT1 + BIT2), (BIT1 + BIT2)); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7E, AccessWidth8, (UINT32)~BIT6, BIT6); + } + + // + //PM 0x80 [8] = 0 for system with NB + //Note: North bridge has AllowLdtStop built for both display and PCIE traffic to wake up the HT link. + //BmReq# needs to be ignored otherwise may cause LDTSTP# not to toggle. + //PM_IO 0x80[3]=1, Ignore BM_STS_SET message from NB + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, (UINT32)~(BIT9 + BIT8 + BIT7 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), 0x21F); + + // + //LdtStartTime = 10h for minimum LDTSTP# de-assertion duration of 16us in StutterMode. This is to guarantee that + //the HT link has been safely reconnected before it can be disconnected again. If C3 pop-up is enabled, the 16us also + //serves as the minimum idle time before LDTSTP# can be asserted again. This allows DMA to finish before the HT + //link is disconnected. + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG94 + 2, AccessWidth8, 0, 0x10); + + // + //This setting provides 16us delay before the assertion of LDTSTOP# when C3 is entered. The + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG98 + 1, AccessWidth8, 0, 0x10); + + // + // ASIC info + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7C, AccessWidth8, 0, 0x85); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7C + 1, AccessWidth8, 0, 0x01); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7E + 1, AccessWidth8, (UINT32)~(BIT7 + BIT5), BIT7 + BIT5); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG88 + 1, AccessWidth8, (UINT32)~BIT4, BIT4); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG98 + 3, AccessWidth8, 0, 0x10); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGB4 + 1, AccessWidth8, 0, 0x0B); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG88, AccessWidth8, (UINT32)~(BIT4 + BIT5), BIT4 + BIT5); +#else + // C-State and VID/FID Change + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG88, AccessWidth8, (UINT32)~(BIT5), BIT5); + + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, (UINT32)~(BIT2), BIT2); + + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, (UINT32)~(BIT1), BIT1); + + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7E, AccessWidth8, (UINT32)~(BIT6), BIT6); + + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG94, AccessWidth8, 0, 0x01); + + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG89, AccessWidth8, (UINT32)~BIT4, BIT4); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG88, AccessWidth8, (UINT32)~BIT4, BIT4); + + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG9B, AccessWidth8, (UINT32)~(BIT6 + BIT5 + BIT4), BIT4); + + RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0x9B , AccessWidth8, (UINT32)~(BIT1 + BIT0), 0); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG96, AccessWidth8, 0, 0x10); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG99, AccessWidth8, 0, 0x10); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG8E, AccessWidth8, 0, 0x80); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG97, AccessWidth8, (UINT32)~(BIT1 + BIT0), 0); + + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, (UINT32)~(BIT4), BIT4); + + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, (UINT32)~(BIT9), BIT9); + + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, (UINT32)~(BIT7), 0); +#endif + +} + +/** + * GcpuRelatedSetting - Program Gcpu C related function + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +GcpuRelatedSetting ( + IN VOID *FchDataPtr + ) +{ + UINT8 FchAcDcMsg; + UINT8 FchTimerTickTrack; + UINT8 FchClockInterruptTag; + UINT8 FchOhciTrafficHanding; + UINT8 FchEhciTrafficHanding; + UINT8 FchGcpuMsgCMultiCore; + UINT8 FchGcpuMsgCStage; + UINT32 Value; + FCH_DATA_BLOCK *LocalCfgPtr; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + + FchAcDcMsg = (UINT8) LocalCfgPtr->Gcpu.AcDcMsg; + FchTimerTickTrack = (UINT8) LocalCfgPtr->Gcpu.TimerTickTrack; + FchClockInterruptTag = (UINT8) LocalCfgPtr->Gcpu.ClockInterruptTag; + FchOhciTrafficHanding = (UINT8) LocalCfgPtr->Gcpu.OhciTrafficHanding; + FchEhciTrafficHanding = (UINT8) LocalCfgPtr->Gcpu.EhciTrafficHanding; + FchGcpuMsgCMultiCore = (UINT8) LocalCfgPtr->Gcpu.GcpuMsgCMultiCore; + FchGcpuMsgCStage = (UINT8) LocalCfgPtr->Gcpu.GcpuMsgCStage; + + ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGA0, AccessWidth32, &Value); + Value = Value & 0xC07F00A0; + + if ( FchAcDcMsg ) { + Value = Value | BIT0; + } + + if ( FchTimerTickTrack ) { + Value = Value | BIT1; + } + + if ( FchClockInterruptTag ) { + Value = Value | BIT10; + } + + if ( FchOhciTrafficHanding ) { + Value = Value | BIT13; + } + + if ( FchEhciTrafficHanding ) { + Value = Value | BIT15; + } + + if ( FchGcpuMsgCMultiCore ) { + Value = Value | BIT23; + } + + if ( FchGcpuMsgCMultiCore ) { + Value = (Value | (BIT6 + BIT4 + BIT3 + BIT2)); + } + + WriteMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGA0, AccessWidth32, &Value); +} + +/** + * MtC1eEnable - Program Mt C1E Enable Function + * + * + * + * @param[in] FchDataPtr + * + */ +VOID +MtC1eEnable ( + IN VOID *FchDataPtr + ) +{ + FCH_DATA_BLOCK *LocalCfgPtr; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + + if ( LocalCfgPtr->HwAcpi.MtC1eEnable ) { + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7A, AccessWidth16, (UINT32)~BIT15, BIT15); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7A, AccessWidth16, (UINT32)~(BIT3 + BIT2 + BIT1 + BIT0), 0x01); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, (UINT32)~(BIT13 + BIT7), BIT13 + BIT7); + } +} + +/** + * StressResetModeLate - Stress Reset Mode + * + * + * + * @param[in] FchDataPtr + * + */ +VOID +StressResetModeLate ( + IN VOID *FchDataPtr + ) +{ + UINT8 ResetValue; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + switch ( LocalCfgPtr->HwAcpi.StressResetMode ) { + case 0: + return; + case 1: + ResetValue = FCH_KBC_RESET_COMMAND; + LibAmdIoWrite (AccessWidth8, FCH_KBDRST_BASE_IO, &ResetValue, StdHeader); + break; + case 2: + ResetValue = FCH_PCI_RESET_COMMAND06; + LibAmdIoWrite (AccessWidth8, FCH_PCIRST_BASE_IO, &ResetValue, StdHeader); + break; + case 3: + ResetValue = FCH_PCI_RESET_COMMAND0E; + LibAmdIoWrite (AccessWidth8, FCH_PCIRST_BASE_IO, &ResetValue, StdHeader); + break; + case 4: + LocalCfgPtr->HwAcpi.StressResetMode = 3; + return; + default: + ASSERT (FALSE); + return; + } + while (LocalCfgPtr->HwAcpi.StressResetMode) { + } +} + + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiMidService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiMidService.c new file mode 100644 index 0000000..319c92e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiMidService.c @@ -0,0 +1,75 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch HwAcpi controller + * + * Init HwAcpi Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "amdlib.h" +#include "cpuServices.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPIMIDSERVICE_FILECODE diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c new file mode 100644 index 0000000..383ab8d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c @@ -0,0 +1,168 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch HwAcpi controller + * + * Init Spread Spectrum features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "amdlib.h" +#include "cpuServices.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2SSSERVICE_FILECODE + +/** + * FchInitResetAcpiMmioTable - Fch ACPI MMIO initial + * during the power on stage. + * + * + * + * + */ +ACPI_REG_WRITE FchInitResetAcpiMmioTable[] = +{ + {00, 00, 0xB0, 0xAC}, /// Signature + {MISC_BASE >> 8, FCH_MISC_REG41, 0x1F, 0x40}, //keep Auxiliary_14Mclk_Sel [12] + // + // USB 3.0 Reference Clock MISC_REG 0x40 [4] = 0 Enable spread-spectrum reference clock. + // + {MISC_BASE >> 8, FCH_MISC_REG40, 0xEF, 0x00}, + + {PMIO_BASE >> 8, 0x5D , 0x00, BIT0}, + {PMIO_BASE >> 8, FCH_PMIOA_REGD2, 0xCF, BIT4 + BIT5}, + {SMBUS_BASE >> 8, FCH_SMBUS_REG12, 0x00, BIT0}, + {PMIO_BASE >> 8, 0x28 , 0xFF, BIT0 + BIT2}, + {PMIO_BASE >> 8, FCH_PMIOA_REG44 + 3, 0x67, 0}, /// Stop Boot timer + {PMIO_BASE >> 8, FCH_PMIOA_REG48, 0xFF, BIT0}, + {PMIO_BASE >> 8, FCH_PMIOA_REG00, 0xFF, 0x0E}, + {PMIO_BASE >> 8, 0x00 + 2, 0xFF, 0x40}, + {PMIO_BASE >> 8, 0x00 + 3, 0xFF, 0x08}, + {PMIO_BASE >> 8, FCH_PMIOA_REG34, 0xEF, BIT0 + BIT1}, + {PMIO_BASE >> 8, FCH_PMIOA_REGEC, 0xFD, BIT1}, + {PMIO_BASE >> 8, FCH_PMIOA_REG08, 0xFE, BIT2 + BIT4}, + {PMIO_BASE >> 8, 0x04 + 1, 0xFF, BIT0}, + {PMIO_BASE >> 8, FCH_PMIOA_REG54, 0x00, BIT4 + BIT6 + BIT7}, + {PMIO_BASE >> 8, 0x04 + 3, 0xFD, BIT1}, + {PMIO_BASE >> 8, FCH_PMIOA_REG74, 0xF6, BIT0 + BIT3}, + {PMIO_BASE >> 8, FCH_PMIOA_REGF0, (UINT8)~BIT2, 0x00}, + + // + // GEC I/O Termination Setting + // PM_Reg 0xF6 = Power-on default setting + // PM_Reg 0xF7 = Power-on default setting + // PM_Reg 0xF8 = 0x6C + // PM_Reg 0xF9 = 0x21 + // PM_Reg 0xFA = 0x00 Hudson-2 A12 GEC I/O Pad settings for 3.3V CMOS + // + {PMIO_BASE >> 8, FCH_PMIOA_REGF8, 0x00, 0x6C}, + {PMIO_BASE >> 8, FCH_PMIOA_REGF8 + 1, 0x00, 0x07}, + {PMIO_BASE >> 8, FCH_PMIOA_REGF8 + 2, 0x00, 0x00}, + // + // GEC -end + // + + {PMIO_BASE >> 8, FCH_PMIOA_REGC4, 0xee, 0x04}, /// Release NB_PCIE_RST + {PMIO_BASE >> 8, FCH_PMIOA_REGC0 + 2, 0xBF, 0x40}, + {PMIO_BASE >> 8, FCH_PMIOA_REGBE, 0xDF, BIT5}, + + // + // Enabling ClkRun Function + // + {PMIO_BASE >> 8, FCH_PMIOA_REGBB, 0xFF, BIT2}, + {PMIO_BASE >> 8, FCH_PMIOA_REGD0, (UINT8)~BIT2, 0}, + + {0xFF, 0xFF, 0xFF, 0xFF}, +}; + +/** + * ProgramFchHwAcpiResetP - Config SpreadSpectrum before PCI + * emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +ProgramFchHwAcpiResetP ( + IN VOID *FchDataPtr + ) +{ + FCH_RESET_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr; + StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader; + + RwPmio (0xD3, AccessWidth8, (UINT32)~BIT4, 0, StdHeader); + RwPmio (0xD3, AccessWidth8, (UINT32)~BIT4, BIT4, StdHeader); + + if ( LocalCfgPtr->Cg2Pll == 1 ) { + TurnOffCG2 (); + LocalCfgPtr->SataClkMode = 0x0a; + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiEnv.c new file mode 100644 index 0000000..38a54a6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiEnv.c @@ -0,0 +1,135 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch HwAcpi controller + * + * Init HwAcpi Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "amdlib.h" +#include "cpuServices.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_HWACPI_HWACPIENV_FILECODE + + + + + + + +/** + * FchInitEnvHwAcpiP - Config HwAcpi controller preliminary + * (Special) + * Acpi S3 resume won't execute this procedure (POST only) + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvHwAcpiP ( + IN VOID *FchDataPtr + ) +{ + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + RecordFchConfigPtr ( (UINT32) ((UINTN) (LocalCfgPtr))); + + ValidateFchVariant (LocalCfgPtr); + + ProgramEnvPFchAcpiMmio (FchDataPtr); + + ProgramFchEnvSpreadSpectrum (FchDataPtr); +} + +/** + * FchInitEnvHwAcpi - Config HwAcpi controller before PCI + * emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvHwAcpi ( + IN VOID *FchDataPtr + ) +{ + FCH_DATA_BLOCK *LocalCfgPtr; + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + + ProgramFchEnvHwAcpiPciReg (FchDataPtr); + // + // FCH Specific Function programming + // + ProgramSpecificFchInitEnvAcpiMmio (FchDataPtr); + HpetInit (LocalCfgPtr); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiLate.c new file mode 100644 index 0000000..e3f5beb --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiLate.c @@ -0,0 +1,205 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch HwAcpi controller + * + * Init HwAcpi Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "amdlib.h" +#include "cpuServices.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_HWACPI_HWACPILATE_FILECODE + +#define AMD_CPUID_APICID_LPC_BID 0x00000001ul // Local APIC ID, Logical Processor Count, Brand ID + + + + + + + +/// +/// PCI_IRQ_REG_BLOCK- FCH PCI IRQ registers block +/// +typedef struct _PCI_IRQ_REG_BLOCK { + UINT8 PciIrqIndex; // PciIrqIndex - selects which PCI interrupt to map + UINT8 PciIrqData; // PciIrqData - Interrupt # +} PCI_IRQ_REG_BLOCK; + +STATIC PCI_IRQ_REG_BLOCK FchInternalDeviceIrqForApicMode[] = { + { (FCH_IRQ_INTA | FCH_IRQ_IOAPIC), 0x10}, + { (FCH_IRQ_INTB | FCH_IRQ_IOAPIC), 0x11}, + { (FCH_IRQ_INTC | FCH_IRQ_IOAPIC), 0x12}, + { (FCH_IRQ_INTD | FCH_IRQ_IOAPIC), 0x13}, + { (FCH_IRQ_INTE | FCH_IRQ_IOAPIC), 0x14}, + { (FCH_IRQ_INTF | FCH_IRQ_IOAPIC), 0x15}, + { (FCH_IRQ_INTG | FCH_IRQ_IOAPIC), 0x16}, + { (FCH_IRQ_INTH | FCH_IRQ_IOAPIC), 0x17}, + { (FCH_IRQ_HDAUDIO | FCH_IRQ_IOAPIC), 0x10}, + { (FCH_IRQ_GEC | FCH_IRQ_IOAPIC), 0x10}, + { (FCH_IRQ_SD | FCH_IRQ_IOAPIC), 0x10}, + { (FCH_IRQ_GPPINT0 | FCH_IRQ_IOAPIC), 0x10}, + { (FCH_IRQ_IDE | FCH_IRQ_IOAPIC), 0x11}, + { (FCH_IRQ_USB18INTB | FCH_IRQ_IOAPIC), 0x11}, + { (FCH_IRQ_USB19INTB | FCH_IRQ_IOAPIC), 0x11}, + { (FCH_IRQ_USB22INTB | FCH_IRQ_IOAPIC), 0x11}, + { (FCH_IRQ_GPPINT1 + FCH_IRQ_IOAPIC), 0x11}, + { (FCH_IRQ_USB18INTA | FCH_IRQ_IOAPIC), 0x12}, + { (FCH_IRQ_USB19INTA | FCH_IRQ_IOAPIC), 0x12}, + { (FCH_IRQ_USB22INTA | FCH_IRQ_IOAPIC), 0x12}, + { (FCH_IRQ_USB20INTC | FCH_IRQ_IOAPIC), 0x12}, + { (FCH_IRQ_GPPINT2 | FCH_IRQ_IOAPIC), 0x12}, + { (FCH_IRQ_SATA | FCH_IRQ_IOAPIC), 0x13}, + { (FCH_IRQ_GPPINT3 | FCH_IRQ_IOAPIC), 0x13}, + }; + +#define NUM_OF_DEVICE_FOR_APICIRQ sizeof (FchInternalDeviceIrqForApicMode) / sizeof (PCI_IRQ_REG_BLOCK) + +/** + * FchInitLateHwAcpi - Prepare HwAcpi controller to boot to OS. + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitLateHwAcpi ( + IN VOID *FchDataPtr + ) +{ + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + UINT8 i; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + if ( IsGCPU (LocalCfgPtr) ) { + GcpuRelatedSetting (LocalCfgPtr); + } else { + //TNBU C3PopupSetting (LocalCfgPtr); + } + + // Mt C1E Enable + MtC1eEnable (LocalCfgPtr); + + if (LocalCfgPtr->Gpp.SerialDebugBusEnable == TRUE ) { + RwMem (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + FCH_SDB_REG00, AccessWidth8, 0xFF, 0x05); + } + + StressResetModeLate (LocalCfgPtr); + SbSleepTrapControl (FALSE); /* TODO: Checkout if we need to disable sleep trap in Non-SMI mode. */ + for (i = 0; i < NUM_OF_DEVICE_FOR_APICIRQ; i++) { + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &FchInternalDeviceIrqForApicMode[i].PciIrqIndex, StdHeader); + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &FchInternalDeviceIrqForApicMode[i].PciIrqData, StdHeader); + } +} + +/** + * IsGCPU - Is Gcpu Cpu? + * + * + * @retval TRUE or FALSE + * + */ +BOOLEAN +IsGCPU ( + IN VOID *FchDataPtr + ) +{ + UINT8 ExtendedFamily; + UINT8 ExtendedModel; + UINT8 BaseFamily; + UINT8 BaseModel; + UINT8 Stepping; + UINT8 Family; + UINT8 Model; + CPUID_DATA CpuId; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuId, StdHeader); + + ExtendedFamily = (UINT8) ((CpuId.EAX_Reg >> 20) & 0xff); + ExtendedModel = (UINT8) ((CpuId.EAX_Reg >> 16) & 0xf); + BaseFamily = (UINT8) ((CpuId.EAX_Reg >> 8) & 0xf); + BaseModel = (UINT8) ((CpuId.EAX_Reg >> 4) & 0xf); + Stepping = (UINT8) ((CpuId.EAX_Reg >> 0) & 0xf); + Family = BaseFamily + ExtendedFamily; + Model = (ExtendedModel << 4) + BaseModel; + + if ( (Family == 0x12) || \ + (Family == 0x14) || \ + (Family == 0x16) ) { + return TRUE; + } else { + return FALSE; + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiMid.c new file mode 100644 index 0000000..6f39196 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiMid.c @@ -0,0 +1,91 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch HwAcpi controller + * + * Init HwAcpi Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "amdlib.h" +#include "cpuServices.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_HWACPI_HWACPIMID_FILECODE + +/** + * FchInitMidHwAcpi - Config HwAcpi controller after PCI + * emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidHwAcpi ( + IN VOID *FchDataPtr + ) +{ +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiReset.c new file mode 100644 index 0000000..5387f8c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiReset.c @@ -0,0 +1,229 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch HwAcpi controller + * + * Init HwAcpi Controller features (PEI phase). + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_HWACPI_HWACPIRESET_FILECODE + +extern ACPI_REG_WRITE FchInitResetAcpiMmioTable[]; + + +/** + * FchInitResetHwAcpiP - Config HwAcpi controller ( Preliminary + * ) during Power-On + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitResetHwAcpiP ( + IN VOID *FchDataPtr + ) +{ + FCH_RESET_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr; + + StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader; + + // + // Enabled (Mmio_mem_enable) + // + RwPmio (FCH_PMIOA_REG24, AccessWidth8, 0xFF, BIT0, StdHeader); + + ProgramFchHwAcpiResetP (FchDataPtr); + + // + // enable CF9 + // + RwPmio (0xD2, AccessWidth8, (UINT32)~BIT6, 0, StdHeader); +} + +/** + * FchInitResetHwAcpi - Config HwAcpi controller during Power-On + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitResetHwAcpi ( + IN VOID *FchDataPtr + ) +{ + UINT16 SmbusBase; + UINT8 Value; + UINT16 AsfPort; + FCH_RESET_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + // + // Set Build option into SB + // + WritePci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG64, AccessWidth16, &(UserOptions.FchBldCfg->CfgSioPmeBaseAddress), StdHeader); + + // + // Enabled SMBUS0/SMBUS1 (ASF) Base Address + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2C, AccessWidth16, 06, (UserOptions.FchBldCfg->CfgSmbus0BaseAddress) + BIT0); ///protect BIT[2:1] + RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0x28 , AccessWidth16, 06, (UserOptions.FchBldCfg->CfgSmbus1BaseAddress) + BIT0); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr)); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG62, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr)); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr)); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG66, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgCpuControlBlkAddr)); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG68, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr)); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6A, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgSmiCmdPortAddr)); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6C, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr)); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6E, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgSmiCmdPortAddr) + 8); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG48, AccessWidth32, 00, (UserOptions.FchBldCfg->CfgWatchDogTimerBase)); + + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2E, AccessWidth8, (UINT32)~(BIT1 + BIT2), 0); ///clear BIT[2:1] + SmbusBase = (UINT16) (UserOptions.FchBldCfg->CfgSmbus0BaseAddress); + Value = 0x00; + LibAmdIoWrite (AccessWidth8, SmbusBase + 0x14, &Value, StdHeader); + + ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE*) (&FchInitResetAcpiMmioTable[0]), StdHeader); + + if (UserOptions.FchBldCfg->CfgFchSciMapControl != NULL) { + ProgramFchSciMapTbl ((UserOptions.FchBldCfg->CfgFchSciMapControl), LocalCfgPtr); + } + + if (UserOptions.FchBldCfg->CfgFchGpioControl != NULL) { + ProgramFchGpioTbl ((UserOptions.FchBldCfg->CfgFchGpioControl), LocalCfgPtr); + } + + if (UserOptions.FchBldCfg->CfgFchSataPhyControl != NULL) { + ProgramFchSataPhyTbl ((UserOptions.FchBldCfg->CfgFchSataPhyControl), LocalCfgPtr); + } + + // + // Prevent RTC error + // + Value = 0x0A; + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG70, &Value, StdHeader); + LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); + Value &= 0xEF; + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); + + Value = 0x08; + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader); + LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader); + if ( !LocalCfgPtr->EcKbd ) { + // + // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input + // + Value = Value | 0x0A; + } + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader); + + Value = 0x09; + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader); + LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader); + if ( !LocalCfgPtr->EcKbd ) { + // + // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input + // + Value = Value & 0xF9; + } + + if ( LocalCfgPtr->LegacyFree ) { + // + // Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation. + // + Value = Value & 0x9F; + } + // + // Enabled IRQ input + // + Value = Value | BIT4; + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader); + + AsfPort = ((UINT16) UserOptions.FchBldCfg->CfgSmbus1BaseAddress & 0xFFF0); + if ( AsfPort != 0 ) { + UINT8 dbValue; + dbValue = 0x70; + LibAmdIoWrite (AccessWidth8, AsfPort + 0x0E, &dbValue, StdHeader); + } + // + // Set ACPIMMIO by OEM Input table + // + if ( LocalCfgPtr->OemResetProgrammingTablePtr != NULL ) { + ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE *) (LocalCfgPtr->OemResetProgrammingTablePtr), StdHeader); + } +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmEnvService.c new file mode 100644 index 0000000..64315c8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmEnvService.c @@ -0,0 +1,294 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH Hwm controller + * + * Init Hwm Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMENVSERVICE_FILECODE + +FCH_HWM_TEMP_PAR TempParDefault[] = { + { 5220, 27365 , 0 }, + { 5225, 27435 , 0 }, + { 5220, 27516 , BIT0 }, ///High Ratio + { 5212, 27580 , BIT1 }, ///High Current + { 5123, 27866 , 0 } +}; + +/** + * HwmInitRegister - Init Hardware Monitor Register. + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +HwmInitRegister ( + IN VOID *FchDataPtr + ) +{ + RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xB2, AccessWidth8, 0, 0x55); + RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xB3, AccessWidth8, 0, 0x55); + RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x91, AccessWidth8, 0, 0x55); + RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x92, AccessWidth8, 0, 0x55); + + RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x00, AccessWidth8, 0, 0x06); + RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x10, AccessWidth8, 0, 0x06); + RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x20, AccessWidth8, 0, 0x06); + RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x30, AccessWidth8, 0, 0x06); + RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x40, AccessWidth8, 0, 0x06); + + RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x66, AccessWidth8, 0, 0x01); + RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x6B, AccessWidth8, 0, 0x01); + RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x70, AccessWidth8, 0, 0x01); + RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x75, AccessWidth8, 0, 0x01); + RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x7A, AccessWidth8, 0, 0x01); + + RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xE6, AccessWidth8, 0xff, 0x02); + RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xF8, AccessWidth8, 0, 0x05); + RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xF9, AccessWidth8, 0, 0x06); + RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xFF, AccessWidth8, 0, 0x42); + RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xE9, AccessWidth8, 0, 0xFF); + RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xEB, AccessWidth8, 0, 0x1F); + //RPR 2.12 HWM Sensor Clk + RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xEF, AccessWidth8, 0, 0x0A); + RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xFB, AccessWidth8, 0, 0x00); + //2.9 Enhancement of FanOut0 Control + RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x50 , AccessWidth32, (UINT32)~ (BIT11 + BIT20), (BIT11 + BIT20)); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xB6 , AccessWidth8, 0x0F, 0x10); +} + +/** + * HwmProcessParameter - Hardware Monitor process Parameter + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +HwmProcessParameter ( + IN VOID *FchDataPtr + ) +{ + UINT8 Index; + UINT8 TempChannel; + UINT8 ValueByte; + UINT16 ValueWord; + FCH_DATA_BLOCK *LocalCfgPtr; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + LibAmdMemCopy ((VOID *) (LocalCfgPtr->Hwm.HwmFanControlCooked), (VOID *) (LocalCfgPtr->Hwm.HwmFanControl), (sizeof (FCH_HWM_FAN_CTR) * 5), LocalCfgPtr->StdHeader); + + HwmGetCalibrationFactor (LocalCfgPtr); + // + //temperatue parameter + // + for ( Index = 0; Index < 5 ; Index++ ) { + if ( LocalCfgPtr->Hwm.HwmTempPar[Index].At == 0 ) { + LocalCfgPtr->Hwm.HwmTempPar[Index] = TempParDefault[Index]; + } + } + + for ( Index = 0; Index < 5 ; Index++ ) { + if ( LocalCfgPtr->Hwm.HwmFanControl[Index].LowDutyReg03 == 100 ) { + LocalCfgPtr->Hwm.HwmFanControlCooked[Index].LowDutyReg03 = 255; + } else { + LocalCfgPtr->Hwm.HwmFanControlCooked[Index].LowDutyReg03 = (LocalCfgPtr->Hwm.HwmFanControl[Index].LowDutyReg03 << 8) / 100; + } + + if ( LocalCfgPtr->Hwm.HwmFanControl[Index].MedDutyReg04 == 100 ) { + LocalCfgPtr->Hwm.HwmFanControlCooked[Index].MedDutyReg04 = 255; + } else { + LocalCfgPtr->Hwm.HwmFanControlCooked[Index].MedDutyReg04 = (LocalCfgPtr->Hwm.HwmFanControl[Index].MedDutyReg04 << 8) / 100; + } + + ValueByte = (UINT8) ((256 - LocalCfgPtr->Hwm.HwmFanControl[Index].LowDutyReg03) / (LocalCfgPtr->Hwm.HwmFanControl[Index].HighTempReg0A - LocalCfgPtr->Hwm.HwmFanControl[Index].MedTempReg08)); + ValueWord = LocalCfgPtr->Hwm.HwmFanControl[Index].LowTempReg06; + + if (LocalCfgPtr->Hwm.HwmFanControl[Index].InputControlReg00 > 4) { + TempChannel = 0; + } else { + TempChannel = LocalCfgPtr->Hwm.HwmFanControl[Index].InputControlReg00; + } + + if ((LocalCfgPtr->Hwm.HwmFchtsiAutoPoll == 1) && (Index == 0)) { + ValueWord = ValueWord << 8; + } else { + ValueByte = (UINT8) (ValueByte * 10000 / LocalCfgPtr->Hwm.HwmTempPar[TempChannel].At); + ValueWord = ((ValueWord * 100 + LocalCfgPtr->Hwm.HwmTempPar[TempChannel].Ct ) * 100 * LocalCfgPtr->Hwm.HwmCalibrationFactor / LocalCfgPtr->Hwm.HwmTempPar[TempChannel].At) >> 3; + } + LocalCfgPtr->Hwm.HwmFanControlCooked[Index].LowTempReg06 = ValueWord; + LocalCfgPtr->Hwm.HwmFanControlCooked[Index].MultiplierReg05 = ValueByte & 0x3f; + + ValueWord = LocalCfgPtr->Hwm.HwmFanControl[Index].MedTempReg08; + if ((LocalCfgPtr->Hwm.HwmFchtsiAutoPoll == 1) && (Index == 0)) { + ValueWord = ValueWord << 8; + } else { + ValueWord = ((ValueWord * 100 + LocalCfgPtr->Hwm.HwmTempPar[TempChannel].Ct ) * 100 * LocalCfgPtr->Hwm.HwmCalibrationFactor / LocalCfgPtr->Hwm.HwmTempPar[TempChannel].At) >> 3; + } + LocalCfgPtr->Hwm.HwmFanControlCooked[Index].MedTempReg08 = ValueWord; + + ValueWord = LocalCfgPtr->Hwm.HwmFanControl[Index].HighTempReg0A; + if ((LocalCfgPtr->Hwm.HwmFchtsiAutoPoll == 1) && (Index == 0)) { + ValueWord = ValueWord << 8; + } else { + ValueWord = ((ValueWord * 100 + LocalCfgPtr->Hwm.HwmTempPar[TempChannel].Ct ) * 100 * LocalCfgPtr->Hwm.HwmCalibrationFactor / LocalCfgPtr->Hwm.HwmTempPar[TempChannel].At) >> 3; + } + LocalCfgPtr->Hwm.HwmFanControlCooked[Index].HighTempReg0A = ValueWord; + } +} + +/** + * hwmSetRegister - Hardware Monitor Set Parameter + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +HwmSetRegister ( + IN VOID *FchDataPtr + ) +{ + UINT8 *DbValuePtr; + UINT8 Index; + UINT8 RegisterN; + UINT8 RegisterPM2RegF8; + UINT8 RegisterPM2RegF9; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + // + //Configure Fans + // + for ( Index = 0; Index < 5 ; Index++ ) { + DbValuePtr = &(LocalCfgPtr->Hwm.HwmFanControlCooked[Index].InputControlReg00); + for ( RegisterN = 0; RegisterN < 0x0E ; RegisterN++ ) { + WritePmio2 (Index * 0x10 + RegisterN, AccessWidth8, DbValuePtr, StdHeader); + DbValuePtr ++; + } + } + + // + //Configure Sample Frequency Divider + // + WritePmio2 (0x63 , AccessWidth8, &(LocalCfgPtr->Hwm.FanSampleFreqDiv), StdHeader); + + // + //Configure Mode + // + ReadPmio2 (0xF8, AccessWidth8, &RegisterPM2RegF8, StdHeader); + ReadPmio2 (0xF9, AccessWidth8, &RegisterPM2RegF9, StdHeader); + for ( Index = 0; Index < 5 ; Index++ ) { + if (LocalCfgPtr->Hwm.HwmTempPar[Index].Mode == BIT0) { + RegisterPM2RegF8 |= 1 << (Index + 3); + } else if (LocalCfgPtr->Hwm.HwmTempPar[Index].Mode == BIT1) { + RegisterPM2RegF9 |= 1 << (Index + 3); + } + } + WritePmio2 (0xF8, AccessWidth8, &RegisterPM2RegF8, StdHeader); + WritePmio2 (0xF9, AccessWidth8, &RegisterPM2RegF9, StdHeader); +} + +/** + * hwmGetCalibrationFactor - Hardware Monitor Get Calibration + * Factor + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +HwmGetCalibrationFactor ( + IN VOID *FchDataPtr + ) +{ + UINT8 ValueByte; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + // + //temperatue parameter + // + ReadPmio2 (FCH_PMIO2_REGEA, AccessWidth8, &ValueByte, StdHeader); + if ( ValueByte & BIT7 ) { + if ( ValueByte & BIT6 ) { + LocalCfgPtr->Hwm.HwmCalibrationFactor = 0x100 + ValueByte; + } else { + LocalCfgPtr->Hwm.HwmCalibrationFactor = 0x200 + (ValueByte & 0x3f ); + } + } else { + LocalCfgPtr->Hwm.HwmCalibrationFactor = 0x200; + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c new file mode 100644 index 0000000..7c1839b --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c @@ -0,0 +1,216 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH Hwm controller + * + * Init Hwm Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 64785 $ @e $Date: 2012-01-30 21:46:59 -0600 (Mon, 30 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMLATESERVICE_FILECODE + +/** + * Table for Function Number + * + * + * + * + */ +STATIC UINT8 FunctionNumber[] = +{ + Fun_81, + Fun_83, + Fun_85, + Fun_89, +}; + +/** + * Table for Max Thermal Zone + * + * + * + * + */ +UINT8 MaxZone[] = +{ + 4, + 4, + 4, + 4, +}; + + +/** + * Table for Max Register + * + * + * + * + */ +UINT8 MaxRegister[] = +{ + MSG_REG9, + MSG_REGB, + MSG_REG9, + MSG_REGA, +}; + +/*------------------------------------------------------------------------------- +;Procedure: IsZoneFuncEnable +; +;Description: This routine will check every zone support function with BitMap from user define +; +; +;Exit: None +; +;Modified: None +; +;----------------------------------------------------------------------------- +*/ +STATIC BOOLEAN +IsZoneFuncEnable ( + IN UINT16 Flag, + IN UINT8 func, + IN UINT8 Zone + ) +{ + return (BOOLEAN) (((Flag >> (func *4)) & 0xF) & ((UINT8 )1 << Zone)); +} + +/*------------------------------------------------------------------------------- +;Procedure: FchECfancontrolservice +; +;Description: This routine service EC fan policy +; +; +;Exit: None +; +;Modified: None +; +;----------------------------------------------------------------------------- +*/ +VOID +FchECfancontrolservice ( + IN VOID *FchDataPtr + ) +{ + UINT8 ZoneNum; + UINT8 FunNum; + UINT8 RegNum; + UINT8 *CurPoint; + UINT8 FunIndex; + BOOLEAN IsSendEcMsg; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + if (!IsImcEnabled (StdHeader)) { + return; //IMC is not enabled + } + + CurPoint = &LocalCfgPtr->Imc.EcStruct.MsgFun81Zone0MsgReg0 + MaxZone[0] * (MaxRegister[0] - MSG_REG0 + 1); + + for ( FunIndex = 1; FunIndex <= 3; FunIndex++ ) { + FunNum = FunctionNumber[FunIndex]; + for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) { + IsSendEcMsg = IsZoneFuncEnable (LocalCfgPtr->Imc.EcStruct.IMCFUNSupportBitMap, FunIndex, ZoneNum); + if (IsSendEcMsg) { + for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) { + WriteECmsg (RegNum, AccessWidth8, CurPoint, StdHeader); + CurPoint += 1; + } + WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &FunNum, StdHeader); // function number + WaitForEcLDN9MailboxCmdAck (StdHeader); + } else { + CurPoint += (MaxRegister[FunIndex] - MSG_REG0 + 1); + } + } + } + + CurPoint = &LocalCfgPtr->Imc.EcStruct.MsgFun81Zone0MsgReg0; + for ( FunIndex = 0; FunIndex <= 0; FunIndex++ ) { + FunNum = FunctionNumber[FunIndex]; + for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) { + IsSendEcMsg = IsZoneFuncEnable (LocalCfgPtr->Imc.EcStruct.IMCFUNSupportBitMap, FunIndex, ZoneNum); + if (IsSendEcMsg) { + for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) { + if (RegNum == MSG_REG2) { + *CurPoint &= 0xFE; + } + WriteECmsg (RegNum, AccessWidth8, CurPoint, StdHeader); + CurPoint += 1; + } + WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &FunNum, StdHeader); // function number + WaitForEcLDN9MailboxCmdAck (StdHeader); + } else { + CurPoint += (MaxRegister[FunIndex] - MSG_REG0 + 1); + } + } + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmMidService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmMidService.c new file mode 100644 index 0000000..71f883a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmMidService.c @@ -0,0 +1,275 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH Hwm controller + * + * Init Hwm Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMMIDSERVICE_FILECODE + +/** + * hwmFchtsiAutoPolling - Hardware Monitor Auto Poll SB-TSI. + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +HwmFchtsiAutoPolling ( + IN VOID *FchDataPtr + ) +{ + UINT8 ValueByte; + UINT16 SmbusBase; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + SmbusBase = (UINT16) (LocalCfgPtr->HwAcpi.Smbus0BaseAddress); + + if (LocalCfgPtr->Hwm.HwmFchtsiAutoPoll == 1) { + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2E, AccessWidth8, (UINT32)~(BIT1 + BIT2), BIT2); + ValueByte = 0xff; + LibAmdIoWrite (AccessWidth8, SmbusBase, &ValueByte, StdHeader); + ValueByte = 0x08; + LibAmdIoWrite (AccessWidth8, SmbusBase + 2, &ValueByte, StdHeader); + ValueByte = 0x09; + LibAmdIoWrite (AccessWidth8, SmbusBase + 3, &ValueByte, StdHeader); + ValueByte = 0x98; + LibAmdIoWrite (AccessWidth8, SmbusBase + 4, &ValueByte, StdHeader); + ValueByte = 0x20; + LibAmdIoWrite (AccessWidth8, SmbusBase + 5, &ValueByte, StdHeader); + ValueByte = 0x48; + LibAmdIoWrite (AccessWidth8, SmbusBase + 2, &ValueByte, StdHeader); + + LibAmdIoRead (AccessWidth8, SmbusBase + 0, &ValueByte, StdHeader); + while ( ValueByte & BIT0 ) { + LibAmdIoRead (AccessWidth8, SmbusBase + 0, &ValueByte, StdHeader); + } + + ValueByte = 0x08; + LibAmdIoWrite (AccessWidth8, SmbusBase + 2, &ValueByte, StdHeader); + ValueByte = 0x10; + LibAmdIoWrite (AccessWidth8, SmbusBase + 3, &ValueByte, StdHeader); + ValueByte = 0x99; + LibAmdIoWrite (AccessWidth8, SmbusBase + 4, &ValueByte, StdHeader); + + ValueByte = 0x80; + LibAmdIoWrite (AccessWidth8, SmbusBase + 0x14, &ValueByte, StdHeader); + ValueByte = 0x01; + LibAmdIoWrite (AccessWidth8, SmbusBase + 0x17, &ValueByte, StdHeader); + ValueByte = 0x81; + LibAmdIoWrite (AccessWidth8, SmbusBase + 0x14, &ValueByte, StdHeader); + + // + //map SB-TSI to tempin0 + // + RwMem (ACPI_MMIO_BASE + PMIO2_BASE + FCH_PMIO2_REG92, AccessWidth8, (UINT32)~BIT3, BIT3); + } else { + HwmFchtsiAutoPollingOff (LocalCfgPtr); + } +} + +/** + * HwmFchtsiAutoPollingOff - Hardware Monitor Auto Poll SB-TSI + * Off. + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +HwmFchtsiAutoPollingOff ( + IN VOID *FchDataPtr + ) +{ + UINT8 ValueByte; + UINT16 SmbusBase; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + if ( LocalCfgPtr->Hwm.HwMonitorEnable ) { + SmbusBase = (UINT16) (LocalCfgPtr->HwAcpi.Smbus0BaseAddress); + ValueByte = 0x00; + LibAmdIoWrite (AccessWidth8, SmbusBase + 0x14, &ValueByte, StdHeader); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2E, AccessWidth8, (UINT32)~(BIT1 + BIT2), 0); + RwMem (ACPI_MMIO_BASE + PMIO2_BASE + FCH_PMIO2_REG92, AccessWidth8, (UINT32)~BIT3, 0x00); + } +} + +/** + * HwmGetRawData - Hardware Monitor Get Raw Data. + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +HwmGetRawData ( + IN VOID *FchDataPtr + ) +{ + UINT8 Index; + UINT16 ValueWord; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + // + //fan speed + // + for ( Index = 0; Index < 5 ; Index++ ) { + ReadPmio2 (FCH_PMIO2_REG69 + Index * 5, AccessWidth16, &ValueWord, StdHeader); + if ( (ValueWord & 0xFFC0) != 0xFFC0 ) { + LocalCfgPtr->Hwm.HwmCurrentRaw.FanSpeed[Index] = ValueWord; + } + } + // + //temperatue + // + for ( Index = 0; Index < 5 ; Index++ ) { + ReadPmio2 (FCH_PMIO2_REG95 + Index * 4, AccessWidth16, &ValueWord, StdHeader); + if ( ( Index == 1 ) || (ValueWord > 0x4000) ) { + LocalCfgPtr->Hwm.HwmCurrentRaw.Temperature[Index] = ValueWord; + } + } + // + //voltage + // + for ( Index = 0; Index < 8 ; Index++ ) { + ReadPmio2 (FCH_PMIO2_REGB8 + Index * 4, AccessWidth16, &ValueWord, StdHeader); + if ( (ValueWord & 0xFFC0) != 0xFFC0 ) { + LocalCfgPtr->Hwm.HwmCurrentRaw.Voltage[Index] = ValueWord; + } + } +} + +/** + * HwmCaculate - Hardware Monitor Caculate Raw Data to Display Data. + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +HwmCaculate ( + IN VOID *FchDataPtr + ) +{ + UINT8 Index; + UINT16 ValueWord; + FCH_DATA_BLOCK *LocalCfgPtr; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + + // + //fan speed + // + for ( Index = 0; Index < 5 ; Index++ ) { + ValueWord = LocalCfgPtr->Hwm.HwmCurrentRaw.FanSpeed[Index]; + if ((ValueWord == 0xffff) || (ValueWord == 0x0000)) { + LocalCfgPtr->Hwm.HwmCurrent.FanSpeed[Index] = 0; + } else { + LocalCfgPtr->Hwm.HwmCurrent.FanSpeed[Index] = ( 22720 >> LocalCfgPtr->Hwm.FanSampleFreqDiv ) * 60 / ValueWord / 2; + } + } + // + //temperatue + // + for ( Index = 0; Index < 5 ; Index++ ) { + ValueWord = LocalCfgPtr->Hwm.HwmCurrentRaw.Temperature[Index]; + if ((LocalCfgPtr->Hwm.HwmFchtsiAutoPoll == 1) && (Index == 1)) { + ValueWord = ((ValueWord & 0xff00) >> 8) * 10 + (((ValueWord & 0x00ff) * 10 ) >> 8); + } else { + ValueWord = ((ValueWord << 3) * LocalCfgPtr->Hwm.HwmTempPar[Index].At / LocalCfgPtr->Hwm.HwmCalibrationFactor / 100 - LocalCfgPtr->Hwm.HwmTempPar[Index].Ct) / 100 ; + } + if ( LocalCfgPtr->Hwm.HwmCurrent.Temperature[Index] == 0 ) { + ValueWord = 0; + } + if ( ValueWord < 10000 ) { + LocalCfgPtr->Hwm.HwmCurrent.Temperature[Index] = ValueWord; + } else { + LocalCfgPtr->Hwm.HwmCurrent.Temperature[Index] = 0; + } + } + // + //voltage + // + for ( Index = 0; Index < 8 ; Index++ ) { + ValueWord = LocalCfgPtr->Hwm.HwmCurrentRaw.Voltage[Index]; + LocalCfgPtr->Hwm.HwmCurrent.Voltage[Index] = (ValueWord >> 6) * 512 / LocalCfgPtr->Hwm.HwmCalibrationFactor; + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmEnv.c new file mode 100644 index 0000000..c670448 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmEnv.c @@ -0,0 +1,89 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH Hwm controller + * + * Init Hwm Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_HWM_HWMENV_FILECODE + +/** + * FchInitEnvHwm - Config Hwm controller before PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvHwm ( + IN VOID *FchDataPtr + ) +{ +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmLate.c new file mode 100644 index 0000000..c63efc4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmLate.c @@ -0,0 +1,98 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH Hwm controller + * + * Init Hwm Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_HWM_HWMLATE_FILECODE + + + +/** + * FchInitLateHwm - Prepare Hwm controller to boot to OS. + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitLateHwm ( + IN VOID *FchDataPtr + ) +{ + FCH_DATA_BLOCK *LocalCfgPtr; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + + ImcWakeup (LocalCfgPtr); + if (( LocalCfgPtr->Hwm.HwmFchtsiAutoPoll == FALSE ) && ( LocalCfgPtr->Hwm.HwMonitorEnable )) { + FchECfancontrolservice (LocalCfgPtr); + } +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmMid.c new file mode 100644 index 0000000..59f25ac --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmMid.c @@ -0,0 +1,88 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH Hwm controller + * + * Init Hwm Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_HWM_HWMMID_FILECODE + +/** + * FchInitMidHwm - Config Hwm controller after PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidHwm ( + IN VOID *FchDataPtr + ) +{ +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmReset.c new file mode 100644 index 0000000..71f5ea3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Hwm/HwmReset.c @@ -0,0 +1,89 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH Hwm controller + * + * Init Hwm Controller features (PEI phase). + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_HWM_HWMRESET_FILECODE + +/** + * FchInitResetHwm - Config Hwm controller during Power-On + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitResetHwm ( + IN VOID *FchDataPtr + ) +{ +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeEnv.c new file mode 100644 index 0000000..6d0f3a4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeEnv.c @@ -0,0 +1,147 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch IDE controller + * + * Init IDE Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_IDE_IDEENV_FILECODE + +/** + * FchInitEnvIde - Config Ide controller before PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvIde ( + IN VOID *FchDataPtr + ) +{ + UINT8 Channel; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG40), AccessWidth8, 0xff, BIT0, StdHeader); + + // + // Enabling IDE Explicit Pre-Fetch IDE PCI Config 0x62[8]=0 + // + RwPci (((IDE_BUS_DEV_FUN << 16) + 0x62 + 1), AccessWidth8, (UINT32)~BIT0, BIT5, StdHeader); + + // + // Disable SATA MSI + // + RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG34), AccessWidth8, 0x00, 0x00, StdHeader); + RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG06), AccessWidth8, 0xEF, 0x00, StdHeader); + + // + // Set Ide Channel enable/disable by parameter + // + ReadPci (((IDE_BUS_DEV_FUN << 16) + 0x040 + 11), AccessWidth8, &Channel, StdHeader); + Channel &= 0xCF; + if ( LocalCfgPtr->Sata.IdeDisUnusedIdePChannel ) { + Channel |= 0x10; + } + if ( LocalCfgPtr->Sata.IdeDisUnusedIdeSChannel ) { + Channel |= 0x20; + } + WritePci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG40 + 11), AccessWidth8, &Channel, StdHeader); + + // + // IDE Controller Class ID & SSID + // ** Get Sata Configuration ** for sync Sata & Ide with only one Legacy Ide device + // + if ( (LocalCfgPtr->Sata.SataIdeMode == 1) && (LocalCfgPtr->Sata.SataClass != SataLegacyIde) ) { + // + // Write the class code to IDE PCI register 08h-0Bh + // + RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG08), AccessWidth32, 0, 0x01018F40, StdHeader); + } + if ( LocalCfgPtr->Sata.SataClass == SataLegacyIde ) { + // + //Set SATA controller to native mode + // + RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG09), AccessWidth8, 0x00, 0x08F, StdHeader); + } + if (LocalCfgPtr->Ide.IdeSsid != 0 ) { + RwPci ((IDE_BUS_DEV_FUN << 16) + 0x2C , AccessWidth32, 0x00, LocalCfgPtr->Ide.IdeSsid, StdHeader); + } + + // + // Disable write access to PCI header + // + RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG40), AccessWidth8, (UINT32)~BIT0, 0, StdHeader); +} + + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeLate.c new file mode 100644 index 0000000..a60abaa --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeLate.c @@ -0,0 +1,86 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch IDE controller + * + * Init IDE Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_IDE_IDELATE_FILECODE +/** + * FchInitLateIde - Prepare IDE controller to boot to OS. + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitLateIde ( + IN VOID *FchDataPtr + ) +{ +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeMid.c new file mode 100644 index 0000000..4b9085c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ide/IdeMid.c @@ -0,0 +1,88 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch IDE controller + * + * Init IDE Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_IDE_IDEMID_FILECODE + +/** + * FchInitMidIde - Config IDE controller after PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidIde ( + IN VOID *FchDataPtr + ) +{ +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/Family/Hudson2/Hudson2ImcService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/Family/Hudson2/Hudson2ImcService.c new file mode 100644 index 0000000..4920372 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/Family/Hudson2/Hudson2ImcService.c @@ -0,0 +1,153 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Imc controller + * + * Init Imc Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_IMC_FAMILY_HUDSON2_HUDSON2IMCSERVICE_FILECODE + +// +// Declaration of local functions +// + + +/** + * SoftwareToggleImcStrapping - Software Toggle IMC Firmware Strapping. + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +SoftwareToggleImcStrapping ( + IN VOID *FchDataPtr + ) +{ + UINT8 ValueByte; + UINT8 PortStatusByte; + UINT32 AbValue; + UINT32 ABStrapOverrideReg; + AMD_CONFIG_PARAMS *StdHeader; + + StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader; + GetChipSysMode (&PortStatusByte, StdHeader); + + ReadPmio (FCH_PMIOA_REGBF, AccessWidth8, &ValueByte, StdHeader); + + // + //if ( (ValueByte & (BIT6 + BIT7)) != 0xC0 ) { // PwrGoodOut =1, PwrGoodEnB=1 + //The strapStatus register is not mapped into StrapOveride not in the same bit position. The following is difference. + // + //StrapStatus StrapOverride + // bit4 bit17 + // bit6 bit12 + // bit12 bit15 + // bit15 bit16 + // bit16 bit18 + // + ReadMem ((ACPI_MMIO_BASE + MISC_BASE + 0x80 ), AccessWidth32, &AbValue); + ABStrapOverrideReg = AbValue; + + if (AbValue & BIT4) { + ABStrapOverrideReg = (ABStrapOverrideReg & ~BIT4) | BIT17; + } + + if (AbValue & BIT6) { + ABStrapOverrideReg = (ABStrapOverrideReg & ~BIT6) | BIT12; + } + + if (AbValue & BIT12) { + ABStrapOverrideReg = (ABStrapOverrideReg & ~BIT12) | BIT15; + } + + if (AbValue & BIT15) { + ABStrapOverrideReg = (ABStrapOverrideReg & ~BIT15) | BIT16; + } + + if (AbValue & BIT16) { + ABStrapOverrideReg = (ABStrapOverrideReg & ~BIT16) | BIT18; + } + + ABStrapOverrideReg |= BIT31; /// Overwrite enable + + if ((PortStatusByte & ChipSysEcEnable) == 0) { + ABStrapOverrideReg |= BIT2; /// bit2- EcEnableStrap + } else { + ABStrapOverrideReg &= ~BIT2; /// bit2=0 EcEnableStrap + } + + WriteMem ((ACPI_MMIO_BASE + MISC_BASE + 0x84 ), AccessWidth32, &ABStrapOverrideReg); + ValueByte |= (BIT6 + BIT7); /// PwrGoodOut =1, PwrGoodEnB=1 + WritePmio (FCH_PMIOA_REGBF, AccessWidth8, &ValueByte, StdHeader); + + ValueByte = 06; + LibAmdIoWrite (AccessWidth8, 0xcf9, &ValueByte, StdHeader); + FchStall (0xffffffff, StdHeader); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcEnv.c new file mode 100644 index 0000000..ee5d1cb --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcEnv.c @@ -0,0 +1,212 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH Embedded Controller + * + * Init Ec Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_IMC_FCHECENV_FILECODE + + +/** + * FchInitEnvEc - Config Ec controller before PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvEc ( + IN VOID *FchDataPtr + ) +{ +} + +/*----------------------------------------------------------------------------------------*/ +/** + * EnterEcConfig - Force EC into Config mode + * + * + * + * + */ +VOID +EnterEcConfig ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT16 EcIndexPortDword; + UINT8 FchEcData8; + + ReadPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA4, AccessWidth16, &EcIndexPortDword, StdHeader); + EcIndexPortDword &= ~(BIT0); + FchEcData8 = 0x5A; + LibAmdIoWrite (AccessWidth8, EcIndexPortDword, &FchEcData8, StdHeader); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * ExitEcConfig - Force EC exit Config mode + * + * + * + * + */ +VOID +ExitEcConfig ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT16 EcIndexPortDword; + UINT8 FchEcData8; + + ReadPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA4, AccessWidth16, &EcIndexPortDword, StdHeader); + EcIndexPortDword &= ~(BIT0); + FchEcData8 = 0xA5; + LibAmdIoWrite (AccessWidth8, EcIndexPortDword, &FchEcData8, StdHeader); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * ReadEc8 - Read EC register data + * + * + * + * @param[in] Address - EC Register Offset Value + * @param[in] Value - Read Data Buffer + * @param[in] StdHeader + * + */ +VOID +ReadEc8 ( + IN UINT8 Address, + IN UINT8 *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT16 EcIndexPortDword; + + ReadPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA4, AccessWidth16, &EcIndexPortDword, StdHeader); + EcIndexPortDword &= ~(BIT0); + LibAmdIoWrite (AccessWidth8, EcIndexPortDword, &Address, StdHeader); + LibAmdIoRead (AccessWidth8, EcIndexPortDword + 1, Value, StdHeader); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * RwEc8 - Read/Write EC register + * + * + * + * @param[in] Address - EC Register Offset Value + * @param[in] AndMask - Data And Mask 8 bits + * @param[in] OrMask - Data OR Mask 8 bits + * @param[in] StdHeader + * + */ +VOID +RwEc8 ( + IN UINT8 Address, + IN UINT8 AndMask, + IN UINT8 OrMask, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 Result; + + ReadEc8 (Address, &Result, StdHeader); + Result = (Result & AndMask) | OrMask; + WriteEc8 (Address, &Result, StdHeader); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * WriteEc8 - Write date into EC register + * + * + * + * @param[in] Address - EC Register Offset Value + * @param[in] Value - Write Data Buffer + * @param[in] StdHeader + * + */ +VOID +WriteEc8 ( + IN UINT8 Address, + IN UINT8 *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT16 EcIndexPortDword; + + ReadPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA4, AccessWidth16, &EcIndexPortDword, StdHeader); + EcIndexPortDword &= ~(BIT0); + LibAmdIoWrite (AccessWidth8, EcIndexPortDword, &Address, StdHeader); + LibAmdIoWrite (AccessWidth8, EcIndexPortDword + 1, Value, StdHeader); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcLate.c new file mode 100644 index 0000000..2ecf1cb --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcLate.c @@ -0,0 +1,88 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH Embedded Controller + * + * Init Ec Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_IMC_FCHECLATE_FILECODE + +/** + * FchInitLateEc - Prepare Ec controller to boot to OS. + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitLateEc ( + IN VOID *FchDataPtr + ) +{ +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcMid.c new file mode 100644 index 0000000..ce865f1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcMid.c @@ -0,0 +1,88 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH Embedded Controller + * + * Init Ec Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_IMC_FCHECMID_FILECODE + +/** + * FchInitMidIde - Config Ec controller after PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidEc ( + IN VOID *FchDataPtr + ) +{ +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcReset.c new file mode 100644 index 0000000..db43b3d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/FchEcReset.c @@ -0,0 +1,143 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Ec controller + * + * Init Ec Controller features (PEI phase). + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_IMC_FCHECRESET_FILECODE + +/** + * FchInitResetEc - Config Ec controller during Power-On + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitResetEc ( + IN VOID *FchDataPtr + ) +{ + FCH_RESET_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + // + //Enable config mode + // + EnterEcConfig (StdHeader); + + // + //Do settings for mailbox - logical device 0x09 + // + RwEc8 (0x07, 0x00, 0x09, StdHeader); ///switch to device 9 (Mailbox) + RwEc8 (0x60, 0x00, (MailBoxPort >> 8), StdHeader); ///set MSB of Mailbox port + RwEc8 (0x61, 0x00, (MailBoxPort & 0xFF), StdHeader); ///set LSB of Mailbox port + RwEc8 (0x30, 0x00, 0x01, StdHeader); ///;Enable Mailbox Registers Interface, bit0=1 + + if ( LocalCfgPtr->EcKbd == ENABLED) { + // + //Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD6, AccessWidth8, (UINT32)~BIT8, BIT0 + BIT1 + BIT2 + BIT3); + + // + //Disable LPC Decoding of port 60/64 + // + RwPci (((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG47), AccessWidth8, (UINT32)~BIT5, 0, StdHeader); + + // + //Enable logical device 0x07 (Keyboard controller) + // + RwEc8 (0x07, 0x00, 0x07, StdHeader); + RwEc8 (0x30, 0x00, 0x01, StdHeader); + } + + if (IsImcEnabled (StdHeader) && ( LocalCfgPtr->EcChannel0 == ENABLED)) { + // + //Logical device 0x03 + // + RwEc8 (0x07, 0x00, 0x03, StdHeader); + RwEc8 (0x60, 0x00, 0x00, StdHeader); + RwEc8 (0x61, 0x00, 0x62, StdHeader); + RwEc8 (0x30, 0x00, 0x01, StdHeader); ///;Enable Device 3 + } + + // + //Enable EC (IMC) to generate SMI to BIOS + // + RwMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB3, AccessWidth8, (UINT32)~BIT6, BIT6); + ExitEcConfig (StdHeader); +} + + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcEnv.c new file mode 100644 index 0000000..4bc73bb --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcEnv.c @@ -0,0 +1,179 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Imc controller + * + * Init Imc Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_IMC_IMCENV_FILECODE + + + +// +// Declaration of local functions +// + + +/** + * FchInitEnvImc - Config Imc controller before PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvImc ( + IN VOID *FchDataPtr + ) +{ + UINT8 PortStatusByte; + FCH_DATA_BLOCK *LocalCfgPtr; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + + GetChipSysMode (&PortStatusByte, LocalCfgPtr->StdHeader); + + // + // Software IMC enable + // + if (((LocalCfgPtr->Imc.ImcEnableOverWrite == 1) && ((PortStatusByte & ChipSysEcEnable) == 0)) || ((LocalCfgPtr->Imc.ImcEnableOverWrite == 2) && ((PortStatusByte & ChipSysEcEnable) == ChipSysEcEnable))) { + if (ValidateImcFirmware (LocalCfgPtr)) { + SoftwareToggleImcStrapping (LocalCfgPtr); + } + } + + FchInitEnvEc (LocalCfgPtr); +} + +/** + * ValidateImcFirmware - Validate IMC Firmware. + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + * @retval TRUE Pass + * @retval FALSE Failed + */ +BOOLEAN +ValidateImcFirmware ( + IN VOID *FchDataPtr + ) +{ + UINT32 ImcSig; + UINT32 ImcSigAddr; + UINT32 ImcAddr; + UINT32 CurAddr; + UINT32 ImcBinSig0; + UINT32 ImcBinSig1; + UINT16 ImcBinSig2; + UINT8 IMCChecksumeByte; + UINT8 IMCByte; + + ImcAddr = 0; + + // + // Software IMC enable + // + ImcSigAddr = 0x80000; /// start from 512k to 64M + ImcSig = 0x0; + + while ( ( ImcSig != 0x55aa55aa ) && ( ImcSigAddr <= 0x4000000 ) ) { + CurAddr = 0xffffffff - ImcSigAddr + 0x20001; + ReadMem (CurAddr, AccessWidth32, &ImcSig); + ReadMem ((CurAddr + 4), AccessWidth32, &ImcAddr); + ImcSigAddr <<= 1; + } + + IMCChecksumeByte = 0xff; + + if ( ImcSig == 0x55aa55aa ) { + // + // "_AMD_IMC_C" at offset 0x2000 of the binary + // + ReadMem ((ImcAddr + 0x2000), AccessWidth32, &ImcBinSig0); + ReadMem ((ImcAddr + 0x2004), AccessWidth32, &ImcBinSig1); + ReadMem ((ImcAddr + 0x2008), AccessWidth16, &ImcBinSig2); + + if ((ImcBinSig0 == 0x444D415F) && (ImcBinSig1 == 0x434D495F) && (ImcBinSig2 == 0x435F) ) { + IMCChecksumeByte = 0; + + for ( CurAddr = ImcAddr; CurAddr < ImcAddr + 0x10000; CurAddr++ ) { + ReadMem (CurAddr, AccessWidth8, &IMCByte); + IMCChecksumeByte = IMCChecksumeByte + IMCByte; + } + } + } + + if ( IMCChecksumeByte ) { + return FALSE; + } else { + return TRUE; + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcLate.c new file mode 100644 index 0000000..43f8669 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcLate.c @@ -0,0 +1,108 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Imc controller + * + * Init Imc Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_IMC_IMCLATE_FILECODE + +/** + * FchInitLateImc - Prepare Imc controller to boot to OS. + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitLateImc ( + IN VOID *FchDataPtr + ) +{ + FchInitLateEc (FchDataPtr); +} + +/** + * ImcDisarmSurebootTimer - IMC Disarm Sureboot Timer. + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +ImcDisarmSurebootTimer ( + IN VOID *FchDataPtr + ) +{ + FCH_DATA_BLOCK *LocalCfgPtr; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + + ImcDisableSurebootTimer (LocalCfgPtr); + LocalCfgPtr->Imc.ImcSureBootTimer = 0; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcLib.c new file mode 100644 index 0000000..6f8903c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcLib.c @@ -0,0 +1,312 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH IMC lib + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_IMC_IMCLIB_FILECODE + +VOID +WriteECmsg ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 Index; + + OpFlag = OpFlag & 0x7f; + if (OpFlag == 0x02) { + OpFlag = 0x03; + } + + for (Index = 0; Index <= OpFlag; Index++) { + /// EC_LDN9_MAILBOX_BASE_ADDRESS + LibAmdIoWrite (AccessWidth8, 0x3E, &Address, StdHeader); + Address++; + /// EC_LDN9_MAILBOX_BASE_ADDRESS + LibAmdIoWrite (AccessWidth8, 0x3F, (UINT8 *)Value + Index, StdHeader); + } +} + +VOID +ReadECmsg ( + IN UINT8 Address, + IN UINT8 OpFlag, + OUT VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 Index; + + OpFlag = OpFlag & 0x7f; + if (OpFlag == 0x02) { + OpFlag = 0x03; + } + + for (Index = 0; Index <= OpFlag; Index++) { + /// EC_LDN9_MAILBOX_BASE_ADDRESS + LibAmdIoWrite (AccessWidth8, 0x3E, &Address, StdHeader); + Address++; + /// EC_LDN9_MAILBOX_BASE_ADDRESS + LibAmdIoRead (AccessWidth8, 0x3F, (UINT8 *)Value + Index, StdHeader); + } +} + +VOID +WaitForEcLDN9MailboxCmdAck ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 Msgdata; + UINT16 Delaytime; + + Msgdata = 0; + + for (Delaytime = 0; Delaytime <= 100000; Delaytime++) { + ReadECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader); + if ( Msgdata == 0xfa) { + break; + } + + FchStall (5, StdHeader); /// Wait for 1ms + } +} + +/** + * ImcSleep - IMC Sleep. + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +ImcSleep ( + IN VOID *FchDataPtr + ) +{ + UINT8 Msgdata; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + if (!(IsImcEnabled (StdHeader)) ) { + return; ///IMC is not enabled + } + + Msgdata = 0x00; + WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader); + Msgdata = 0xB4; + WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader); + Msgdata = 0x00; + WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader); + Msgdata = 0x96; + WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader); + WaitForEcLDN9MailboxCmdAck (StdHeader); +} + + +/** + * ImcEnableSurebootTimer - IMC Enable Sureboot Timer. + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +ImcEnableSurebootTimer ( + IN VOID *FchDataPtr + ) +{ + UINT8 Msgdata; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + ImcDisableSurebootTimer (LocalCfgPtr); + + Msgdata = 0x00; + + if (!(IsImcEnabled (StdHeader)) || (LocalCfgPtr->Imc.ImcSureBootTimer == 0)) { + return; ///IMC is not enabled + } + + ImcWakeup (FchDataPtr); + WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader); + Msgdata = 0x01; + WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader); + Msgdata = ( (LocalCfgPtr->Imc.ImcSureBootTimer) << 6) -1; + WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader); + Msgdata = 0x94; + WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader); + WaitForEcLDN9MailboxCmdAck (StdHeader); + ImcSleep (FchDataPtr); +} + +/** + * ImcDisableSurebootTimer - IMC Disable Sureboot Timer. + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +ImcDisableSurebootTimer ( + IN VOID *FchDataPtr + ) +{ + UINT8 Msgdata; + AMD_CONFIG_PARAMS *StdHeader; + + StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader; + + if (!(IsImcEnabled (StdHeader)) ) { + return; ///IMC is not enabled + } + + ImcWakeup (FchDataPtr); + Msgdata = 0x00; + WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader); + Msgdata = 0x01; + WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader); + Msgdata = 0x00; + WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader); + Msgdata = 0x94; + WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader); + WaitForEcLDN9MailboxCmdAck (StdHeader); + ImcSleep (FchDataPtr); +} + +/** + * ImcWakeup - IMC Wakeup. + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +ImcWakeup ( + IN VOID *FchDataPtr + ) +{ + UINT8 Msgdata; + AMD_CONFIG_PARAMS *StdHeader; + + StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader; + if (!(IsImcEnabled (StdHeader)) ) { + return; ///IMC is not enabled + } + + Msgdata = 0x00; + WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader); + Msgdata = 0xB5; + WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader); + Msgdata = 0x00; + WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader); + Msgdata = 0x96; + WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader); + WaitForEcLDN9MailboxCmdAck (StdHeader); +} + +/** + * ImcIdle - IMC Idle. + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +ImcIdle ( + IN VOID *FchDataPtr + ) +{ + UINT8 Msgdata; + AMD_CONFIG_PARAMS *StdHeader; + + StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader; + + if (!(IsImcEnabled (StdHeader)) ) { + return; ///IMC is not enabled + } + + Msgdata = 0x00; + WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader); + Msgdata = 0x01; + WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader); + Msgdata = 0x00; + WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader); + Msgdata = 0x98; + WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader); + WaitForEcLDN9MailboxCmdAck (StdHeader); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcMid.c new file mode 100644 index 0000000..78d9a97 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcMid.c @@ -0,0 +1,89 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Imc controller + * + * Init Imc Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63441 $ @e $Date: 2011-12-22 17:18:09 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_IMC_IMCMID_FILECODE + +/** + * FchInitMidImc - Config Imc controller after PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidImc ( + IN VOID *FchDataPtr + ) +{ + FchInitMidEc (FchDataPtr); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcReset.c new file mode 100644 index 0000000..4c851e4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Imc/ImcReset.c @@ -0,0 +1,105 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Imc controller + * + * Init Imc Controller features (PEI phase). + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_IMC_IMCRESET_FILECODE + +/** + * FchInitResetImc - Config Imc controller during Power-On + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitResetImc ( + IN VOID *FchDataPtr + ) +{ + UINT8 PortStatusByte; + AMD_CONFIG_PARAMS *StdHeader; + + StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader; + GetChipSysMode (&PortStatusByte, StdHeader); + + if ( ((PortStatusByte & ChipSysEcEnable) == 0x00) ) { + // + // EC is disabled by jumper setting or board config + // + RwPci (((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA4), AccessWidth16, 0xFFFE, BIT0, StdHeader); + } else { + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC4, AccessWidth8, 0xF7, 0x08); + FchInitResetEc (FchDataPtr); + // ecPowerOnInit ( FchDataPtr); + ImcSleep (FchDataPtr); + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c new file mode 100644 index 0000000..f9c29d9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c @@ -0,0 +1,377 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Graphics Controller family specific service procedure + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "FchPlatform.h" +#include "Filecode.h" +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * Default FCH interface settings at InitEnv phase. + *---------------------------------------------------------------------------------------- + */ +CONST FCH_INTERFACE ROMDATA FchInterfaceDefault = { + SdAmda, // SdConfig + hdaconf2 , // AzaliaControl + IrRxTx0Tx1, // IrConfig + TRUE, // UmiGen2 + SataAhci, // SataClass + TRUE, // SataEnable + TRUE, // IdeEnable + TRUE, // SataIdeMode + TRUE, // Ohci1Enable + TRUE, // Ohci2Enable + TRUE, // Ohci3Enable + TRUE, // Ohci4Enable + TRUE, // XhciSwitch + TRUE, // GppEnable + AlwaysOff // FchPowerFail +}; + + +/*---------------------------------------------------------------- + * InitEnv Phase Data Block Default (Failsafe) + *---------------------------------------------------------------- + */ +FCH_DATA_BLOCK InitEnvCfgDefault = { + NULL, // StdHeader + + { // FCH_ACPI + 0xB00, // Smbus0BaseAddress + 0xB20, // Smbus1BaseAddress + 0xE00, // SioPmeBaseAddress + 0xFEC000F0, // WatchDogTimerBase + 0x800, // AcpiPm1EvtBlkAddr + 0x804, // AcpiPm1CntBlkAddr + 0x808, // AcpiPmTmrBlkAddr + 0x810, // CpuControlBlkAddr + 0x820, // AcpiGpe0BlkAddr + 0x00B0, // SmiCmdPortAddr + 0xFE00, // AcpiPmaCntBlkAddr + TRUE, // AnyHt200MhzLink + TRUE, // SpreadSpectrum + AlwaysOff, // PwrFailShadow + 0, // StressResetMode + FALSE, // MtC1eEnable + NULL // OemProgrammingTablePtr + }, + + { // FCH_AB + FALSE, // AbMsiEnable + 0, // ALinkClkGateOff + 0, // BLinkClkGateOff + 0, // AbClockGating + 0, // GppClockGating + 0, // UmiL1TimerOverride + 0, // UmiLinkWidth + 0, // UmiDynamicSpeedChange + 0, // PcieRefClockOverClocking + 0, // UmiGppTxDriverStrength + TRUE, // NbSbGen2 + 0, // FchPcieOrderRule + 0, // SlowSpeedAbLinkClock + 0, // ResetCpuOnSyncFlood + FALSE, // AbDmaMemoryWrtie3264B + FALSE, // AbMemoryPowerSaving + FALSE, // SbgDmaMemoryWrtie3264ByteCount + FALSE // SbgMemoryPowerSaving + }, + + {{{0}}}, // FCH_GPP + + { // FCH_USB + TRUE, // Ohci1Enable + TRUE, // Ohci2Enable + TRUE, // Ohci3Enable + TRUE, // Ohci4Enable + TRUE, // Ehci1Enable + TRUE, // Ehci2Enable + TRUE, // Ehci3Enable + TRUE, // Xhci0Enable + TRUE, // Xhci1Enable + FALSE, // UsbMsiEnable + 0, // OhciSsid + 0, // Ohci4Ssid + 0, // EhciSsid + 0, // XhciSsid + FALSE, // UsbPhyPowerDown + 0 // UserDefineXhciRomAddr + }, + + { // FCH_SATA + FALSE, // SataMsiEnable + 0x00000000, // SataIdeSsid + 0x00000000, // SataRaidSsid + 0x00000000, // SataRaid5Ssid + 0x00000000, // SataAhciSsid + { // SATA_ST + 0, // SataModeReg + TRUE, // SataEnable + 0, // Sata6AhciCap + FALSE, // SataSetMaxGen2 + TRUE, // IdeEnable + 9, // SataClkMode + }, + SataAhci, // SataClass + 1, // SataIdeMode + 0, // SataDisUnusedIdePChannel + 0, // SataDisUnusedIdeSChannel + 0, // IdeDisUnusedIdePChannel + 0, // IdeDisUnusedIdeSChannel + 0, // SataOptionReserved + { // SATA_PORT_ST + 0, // SataPortReg + FALSE, // Port0 + FALSE, // Port1 + FALSE, // Port2 + FALSE, // Port3 + FALSE, // Port4 + FALSE, // Port5 + FALSE, // Port6 + FALSE, // Port7 + }, + { // SATA_PORT_ST + 0, // SataPortReg + FALSE, // Port0 + FALSE, // Port1 + FALSE, // Port2 + FALSE, // Port3 + FALSE, // Port4 + FALSE, // Port5 + FALSE, // Port6 + FALSE, // Port7 + }, + { // SATA_PORT_MD + 0, // SataPortMode + 0, // Port0 + 0, // Port1 + 0, // Port2 + 0, // Port3 + 0, // Port4 + 0, // Port5 + 0, // Port6 + 0, // Port7 + }, + 0, // SataAggrLinkPmCap + 0, // SataPortMultCap + 0, // SataClkAutoOff + 0, // SataPscCap + 0, // BiosOsHandOff + 0, // SataFisBasedSwitching + 0, // SataCccSupport + 0, // SataSscCap + 0, // SataMsiCapability + 0, // SataForceRaid + 0, // SataInternal100Spread + 0, // SataDebugDummy + 0, // SataTargetSupport8Device + 0, // SataDisableGenericMode + FALSE, // SataAhciEnclosureManagement + 0, // SataSgpio0 + 0, // SataSgpio1 + 0, // SataPhyPllShutDown + TRUE, // SataHotRemovalEnh + { // SATA_PORT_ST + 0, // SataPortReg + FALSE, // Port0 + FALSE, // Port1 + FALSE, // Port2 + FALSE, // Port3 + FALSE, // Port4 + FALSE, // Port5 + FALSE, // Port6 + FALSE, // Port7 + }, + 0 // TempMmio + }, + + { // FCH_SMBUS + 0x00000000 // SmbusSsid + }, + + { // FCH_IDE + TRUE, // IdeEnable + FALSE, // IdeMsiEnable + 0x00000000 // IdeSsid + }, + + { // FCH_AZALIA + hdaconf2, // AzaliaEnable + FALSE, // AzaliaMsiEnable + 0x00000000, // AzaliaSsid + 1, // AzaliaPinCfg + 0, // AzaliaFrontPanel + 0, // FrontPanelDetected + 0, // AzaliaSnoop + 0, // AzaliaDummy + { // AZALIA_PIN + 2, // AzaliaSdin0 + 2, // AzaliaSdin1 + 2, // AzaliaSdin2 + 2, // AzaliaSdin3 + }, + NULL, // *AzaliaOemCodecTablePtr + NULL, // *AzaliaOemFpCodecTablePtr + }, + + { // FCH_SPI + FALSE, // LpcMsiEnable + 0x00000000, // LpcSsid + 0, // RomBaseAddress + 0, // Speed + 0, // FastSpeed + 0, // WriteSpeed + 0, // Mode + 0, // AutoMode + 0, // BurstWrite + }, + + { // FCH_PCIB + FALSE, // PcibMsiEnable + 0x00000000, // PcibSsid + 0x0F, // PciClks + 0, // PcibClkStopOverride + FALSE, // PcibClockRun + }, + + { // FCH_GEC + FALSE, // GecEnable + 0, // GecPhyStatus + 0, // GecPowerPolicy + 0, // GecDebugBus + 0xFED61000, // GecShadowRomBase + NULL, // *PtrDynamicGecRomAddress + }, + + { // FCH_SD + SdAmda, // SdConfig + 0, // Speed + 0, // BitWidth + 0x00000000, // SdSsid + Sd50MhzTraceCableLengthWithinSixInches, // SdClockControl + FALSE, + 0, + 0 + }, + + {0}, // FCH_HWM + + {0, // FCH_IR + 0x23, // IrPinControl + }, + + { // FCH_HPET + TRUE, // HpetEnable + TRUE, // HpetMsiDis + 0xFED00000 // HpetBase + }, + + { // FCH_GCPU + 0, // AcDcMsg + 0, // TimerTickTrack + 0, // ClockInterruptTag + 0, // OhciTrafficHanding + 0, // EhciTrafficHanding + 0, // GcpuMsgCMultiCore + 0, // GcpuMsgCStage + }, + + {0}, // FCH_IMC + + { // FCH_MISC + FALSE, // NativePcieSupport + FALSE, // S3Resume + FALSE, // RebootRequired + 0, // FchVariant + 0, // CG2PLL + { // TIMER_SMI-LongTimer + FALSE, // Enable + FALSE, // StartNow + 1000 // CycleDuration + }, + { // TIMER_SMI-ShortTimer + FALSE, // Enable + FALSE, // StartNow + 0x7FFF // CycleDuration + } + } +}; + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c new file mode 100644 index 0000000..37e7a42 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c @@ -0,0 +1,185 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Graphics Controller family specific service procedure + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "FchPlatform.h" +#include "Filecode.h" +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------------------- + * Default FCH interface settings at InitReset phase. + *---------------------------------------------------------------------------------------- + */ +CONST FCH_RESET_INTERFACE ROMDATA FchResetInterfaceDefault = { + TRUE, // UmiGen2 + TRUE, // SataEnable + TRUE, // IdeEnable + TRUE, // GppEnable + TRUE, // Xhci0Enable + TRUE // Xhci1Enable +}; + + +/*---------------------------------------------------------------- + * InitReset Phase Data Block Default (Failsafe) + *---------------------------------------------------------------- + */ +FCH_RESET_DATA_BLOCK InitResetCfgDefault = { + NULL, // StdHeader + {0}, // FchReset + + 0, // FastSpeed + 0, // WriteSpeed + 0, // Mode + 0, // AutoMode + 0, // BurstWrite + FALSE, // SataIdeCombMdPriSecOpt + 0, // Cg2Pll + FALSE, // EcKbd + FALSE, // LegacyFree + FALSE, // SataSetMaxGen2 + 9, // SataClkMode + 0, // SataModeReg + FALSE, // SataInternal100Spread + 2, // SpiSpeed + FALSE, // EcChannel0 + + { // FCH_GPP + { // Array of FCH_GPP_PORT_CONFIG PortCfg[4] + { + FALSE, // PortPresent + FALSE, // PortDetected + FALSE, // PortIsGen2 + FALSE, // PortHotPlug + 0, // PortMisc + }, + { + FALSE, // PortPresent + FALSE, // PortDetected + FALSE, // PortIsGen2 + FALSE, // PortHotPlug + 0, // PortMisc + }, + { + FALSE, // PortPresent + FALSE, // PortDetected + FALSE, // PortIsGen2 + FALSE, // PortHotPlug + 0, // PortMisc + }, + { + FALSE, // PortPresent + FALSE, // PortDetected + FALSE, // PortIsGen2 + FALSE, // PortHotPlug + 0, // PortMisc + }, + }, + PortA1B1C1D1, // GppLinkConfig + FALSE, // GppFunctionEnable + FALSE, // GppToggleReset + 0, // GppHotPlugGeventNum + 0, // GppFoundGfxDev + FALSE, // GppGen2 + 0, // GppGen2Strap + FALSE, // GppMemWrImprove + FALSE, // GppUnhidePorts + 0, // GppPortAspm + FALSE, // GppLaneReversal + TRUE, // GppPhyPllPowerDown + TRUE , // GppDynamicPowerSaving + FALSE, // PcieAer + FALSE, // PcieRas + FALSE, // PcieCompliance + FALSE, // PcieSoftwareDownGrade + TRUE, // UmiPhyPllPowerDown + FALSE, // SerialDebugBusEnable + 0, // GppHardwareDownGrade + 0, // GppL1ImmediateAck + TRUE, // NewGppAlgorithm + 0, // HotPlugPortsStatus + 0, // FailPortsStatus + 40, // GppPortMinPollingTime + }, + NULL // OemResetProgrammingTablePtr +}; + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitEnv.c new file mode 100644 index 0000000..2929a8a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitEnv.c @@ -0,0 +1,142 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH Initialization. + * + * Init IOAPIC/IOMMU/Misc NB features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ + +#include "FchPlatform.h" +#include "FchTaskLauncher.h" +#include "heapManager.h" +#include "Ids.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_INTERFACE_FCHINITENV_FILECODE + +extern FCH_TASK_ENTRY *FchInitEnvTaskTable[]; +extern FCH_INTERFACE FchInterfaceDefault; + +FCH_DATA_BLOCK* +FchInitEnvCreatePrivateData ( + IN AMD_ENV_PARAMS *EnvParams + ); + +AGESA_STATUS +FchInitEnv ( + IN AMD_ENV_PARAMS *EnvParams + ); + +AGESA_STATUS +FchEnvConstructor ( + IN AMD_ENV_PARAMS *EnvParams + ); +/*----------------------------------------------------------------------------------------*/ +/** + * FchInitEnv - Config Fch before PCI emulation + * + * + * + * @param[in] EnvParams + * + */ +AGESA_STATUS +FchInitEnv ( + IN AMD_ENV_PARAMS *EnvParams + ) +{ + FCH_DATA_BLOCK *FchParams; + AGESA_STATUS Status; + + IDS_HDT_CONSOLE (FCH_TRACE, " FchInitEnv Enter... \n"); + FchParams = FchInitEnvCreatePrivateData (EnvParams); + + // Override internal data with IDS (Optional, internal build only) + IDS_OPTION_CALLOUT (IDS_CALLOUT_FCH_INIT_ENV, FchParams, FchParams->StdHeader); + + AgesaFchOemCallout (FchParams); + Status = FchTaskLauncher (&FchInitEnvTaskTable[0], FchParams, TpFchInitEnvDispatching); + IDS_HDT_CONSOLE (FCH_TRACE, " FchInitEnv Exit... Status = [0x%x]\n", Status); + return Status; +} + + +/** + * A constructor for FCH build parameter structure at InitEnv stage + * + * Sets inputs to valid, basic level, defaults. + * + * @param[in,out] EnvParams InitEnv configuration data block + * + * @retval AGESA_SUCCESS Constructors are not allowed to fail +*/ +AGESA_STATUS +FchEnvConstructor ( + IN AMD_ENV_PARAMS *EnvParams + ) +{ + EnvParams->FchInterface = FchInterfaceDefault; + return AGESA_SUCCESS; +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitLate.c new file mode 100644 index 0000000..19016a3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitLate.c @@ -0,0 +1,129 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH Initialization. + * + * Init IOAPIC/IOMMU/Misc NB features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ + +#include "FchPlatform.h" +#include "FchTaskLauncher.h" +#include "heapManager.h" +#include "Ids.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_INTERFACE_FCHINITLATE_FILECODE + +extern FCH_TASK_ENTRY *FchInitLateTaskTable[]; + +AGESA_STATUS +FchInitLate ( + IN AMD_S3SAVE_PARAMS *LateParams + ); + +AGESA_STATUS +FchLateConstructor ( + IN AMD_LATE_PARAMS *LateParams + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * FchInitLate - Prepare Fch to boot to OS. + * + * + * + * @param[in] LateParams + * + */ +AGESA_STATUS +FchInitLate ( + IN AMD_S3SAVE_PARAMS *LateParams + ) +{ + FCH_DATA_BLOCK *FchParams; + AGESA_STATUS Status; + + IDS_HDT_CONSOLE (FCH_TRACE, " FchInitLate Enter... \n"); + FchParams = FchInitLoadDataBlock (&LateParams->FchInterface, &LateParams->StdHeader); + Status = FchTaskLauncher (&FchInitLateTaskTable[0], FchParams, TpFchInitLateDispatching); + IDS_HDT_CONSOLE (FCH_TRACE, " FchInitLate Exit... Status = [0x%x]\n", Status); + return Status; +} + + +/** + * A constructor for FCH build parameter structure at InitLate stage + * + * Sets inputs to valid, basic level, defaults. + * + * @param[in,out] LateParams + * + * @retval AGESA_SUCCESS Constructors are not allowed to fail +*/ +AGESA_STATUS +FchLateConstructor ( + IN AMD_LATE_PARAMS *LateParams + ) +{ + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitMid.c new file mode 100644 index 0000000..0ab6817 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitMid.c @@ -0,0 +1,127 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH Initialization. + * + * Init IOAPIC/IOMMU/Misc NB features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ + +#include "FchPlatform.h" +#include "FchTaskLauncher.h" +#include "heapManager.h" +#include "Ids.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_INTERFACE_FCHINITMID_FILECODE + +extern FCH_TASK_ENTRY *FchInitMidTaskTable[]; + +AGESA_STATUS +FchInitMid ( + IN AMD_MID_PARAMS *MidParams + ); + +AGESA_STATUS +FchMidConstructor ( + IN AMD_MID_PARAMS *MidParams + ); +/** + * FchInitMid - Config Fch after PCI emulation + * + * + * + * @param[in] MidParams Fch configuration structure pointer. + * + */ +AGESA_STATUS +FchInitMid ( + IN AMD_MID_PARAMS *MidParams + ) +{ + FCH_DATA_BLOCK *FchParams; + AGESA_STATUS Status; + + IDS_HDT_CONSOLE (FCH_TRACE, " FchInitMid Enter... \n"); + FchParams = FchInitLoadDataBlock (&MidParams->FchInterface, &MidParams->StdHeader); + Status = FchTaskLauncher (&FchInitMidTaskTable[0], FchParams, TpFchInitMidDispatching); + IDS_HDT_CONSOLE (FCH_TRACE, " FchInitMid Exit... Status = [0x%x]\n", Status); + return Status; +} + + +/** + * A constructor for FCH build parameter structure at InitEnv stage + * + * Sets inputs to valid, basic level, defaults. + * + * @param[in] MidParams + * + * @retval AGESA_SUCCESS Constructors are not allowed to fail +*/ +AGESA_STATUS +FchMidConstructor ( + IN AMD_MID_PARAMS *MidParams + ) +{ + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitReset.c new file mode 100644 index 0000000..79561ac --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitReset.c @@ -0,0 +1,143 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH Init during Power-On Reset + * + * Prepare FCH environment during power on stage + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ + +#include "FchPlatform.h" +#include "FchTaskLauncher.h" +#include "heapManager.h" +#include "Ids.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_INTERFACE_FCHINITRESET_FILECODE + +extern FCH_TASK_ENTRY *FchInitResetTaskTable[]; +extern FCH_RESET_INTERFACE FchResetInterfaceDefault; + +FCH_RESET_DATA_BLOCK* +FchInitResetLoadPrivateDefault ( + IN AMD_RESET_PARAMS *ResetParams + ); + +AGESA_STATUS +FchInitReset ( + IN AMD_RESET_PARAMS *ResetParams + ); + +AGESA_STATUS +FchResetConstructor ( + IN AMD_RESET_PARAMS *ResetParams + ); + +/** + * FchInitReset - Config Fch during power on stage. + * + * + * + * @param[in] ResetParams + * + */ +AGESA_STATUS +FchInitReset ( + IN AMD_RESET_PARAMS *ResetParams + ) +{ + FCH_RESET_DATA_BLOCK *FchParams; + + // Load private data block with default + FchParams = FchInitResetLoadPrivateDefault (ResetParams); + + // Override external data with input parameters + FchParams->StdHeader = &ResetParams->StdHeader; + FchParams->FchReset = ResetParams->FchInterface; + FchParams->Gpp.GppFunctionEnable = ResetParams->FchInterface.GppEnable; + + // Override internal data with IDS (Optional, internal build only) + IDS_OPTION_CALLOUT (IDS_CALLOUT_FCH_INIT_RESET, FchParams, &ResetParams->StdHeader); + + AgesaFchOemCallout (FchParams); + return FchTaskLauncher (&FchInitResetTaskTable[0], FchParams, TpFchInitResetDispatching); +} + + +/** + * A constructor for FCH build parameter structure at InitReset stage + * + * Sets inputs to valid, basic level, defaults. + * + * @param[in] ResetParams + * + * @retval AGESA_SUCCESS Constructors are not allowed to fail +*/ +AGESA_STATUS +FchResetConstructor ( + IN AMD_RESET_PARAMS *ResetParams + ) +{ + ResetParams->FchInterface = FchResetInterfaceDefault; + return AGESA_SUCCESS; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitS3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitS3.c new file mode 100644 index 0000000..5abec4c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchInitS3.c @@ -0,0 +1,129 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH Initialization. + * + * Init IOAPIC/IOMMU/Misc NB features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ + +#include "FchPlatform.h" +#include "FchTaskLauncher.h" +#define FILECODE PROC_FCH_INTERFACE_FCHINITS3_FILECODE + +extern FCH_TASK_ENTRY *FchInitS3EarlyTaskTable[]; +extern FCH_TASK_ENTRY *FchInitS3LateTaskTable[]; + +VOID +FchInitS3EarlyRestore ( + IN FCH_DATA_BLOCK *FchDataPtr + ); + +VOID +FchInitS3LateRestore ( + IN FCH_DATA_BLOCK *FchDataPtr + ); +/*----------------------------------------------------------------------------------------*/ +/** + * FchInitS3EarlyRestore - Config Fch before ACPI S3 resume PCI config device restore + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ + +VOID +FchInitS3EarlyRestore ( + IN FCH_DATA_BLOCK *FchDataPtr + ) +{ + AGESA_STATUS AgesaStatus; + + FchDataPtr->Misc.S3Resume = 1; + AgesaStatus = FchTaskLauncher (&FchInitS3EarlyTaskTable[0], FchDataPtr, TpFchInitS3EarlyDispatching); + FchDataPtr->Misc.S3Resume = 0; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * FchInitS3LateRestore - Config Fch after ACPI S3 resume PCI config device restore + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ + +VOID +FchInitS3LateRestore ( + IN FCH_DATA_BLOCK *FchDataPtr + ) +{ + AGESA_STATUS AgesaStatus; + + FchDataPtr->Misc.S3Resume = 1; + AgesaStatus = FchTaskLauncher (&FchInitS3LateTaskTable[0], FchDataPtr, TpFchInitS3LateDispatching); + FchDataPtr->Misc.S3Resume = 0; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchTaskLauncher.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchTaskLauncher.c new file mode 100644 index 0000000..b6d94f9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchTaskLauncher.c @@ -0,0 +1,91 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH task launcher + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Ids.h" +#include "FchTaskLauncher.h" +#define FILECODE PROC_FCH_INTERFACE_FCHTASKLAUNCHER_FILECODE + + +AGESA_STATUS +FchTaskLauncher ( + IN FCH_TASK_ENTRY **TaskPtr, + IN VOID *FchCfg, + IN AGESA_TP TestPoint + ) +{ + AGESA_TESTPOINT (TestPoint, *(AMD_CONFIG_PARAMS **) FchCfg); + while (*TaskPtr != NULL) { + (*TaskPtr) (FchCfg); + TaskPtr++; + } + return AGESA_SUCCESS; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchTaskLauncher.h b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchTaskLauncher.h new file mode 100644 index 0000000..8cc1a20 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/FchTaskLauncher.h @@ -0,0 +1,89 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH task launcher + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#ifndef _FCH_TASK_LAUNCHER_H_ +#define _FCH_TASK_LAUNCHER_H_ + +#include "Ids.h" + +FCH_DATA_BLOCK* +FchInitLoadDataBlock ( + IN FCH_INTERFACE *FchInterface, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +FchTaskLauncher ( + IN FCH_TASK_ENTRY **TaskPtr, + IN VOID *FchCfg, + IN AGESA_TP TestPoint + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitEnvDef.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitEnvDef.c new file mode 100644 index 0000000..b4ff312 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitEnvDef.c @@ -0,0 +1,223 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Fch Init during POWER-ON + * + * Prepare Fch environment during power on stage. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ + +#include "FchPlatform.h" +#include "Ids.h" +#include "heapManager.h" +#include "Filecode.h" + +#define FILECODE PROC_FCH_INTERFACE_INITENVDEF_FILECODE + +extern FCH_DATA_BLOCK InitEnvCfgDefault; + +FCH_DATA_BLOCK* +FchInitEnvCreatePrivateData ( + IN AMD_ENV_PARAMS *EnvParams + ); + +FCH_DATA_BLOCK* +FchInitLoadDataBlock ( + IN FCH_INTERFACE *FchInterface, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +FCH_DATA_BLOCK* +FchInitLoadDataBlock ( + IN FCH_INTERFACE *FchInterface, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + FCH_DATA_BLOCK *FchParams; + LOCATE_HEAP_PTR LocHeapPtr; + AMD_CONFIG_PARAMS TempStdHeader; + AGESA_STATUS AgesaStatus; + + TempStdHeader = *StdHeader; + TempStdHeader.HeapStatus = HEAP_SYSTEM_MEM; + + // Locate the internal data block via heap manager + LocHeapPtr.BufferHandle = AMD_FCH_DATA_BLOCK_HANDLE; + AgesaStatus = HeapLocateBuffer (&LocHeapPtr, &TempStdHeader); + ASSERT (!AgesaStatus); + + FchParams = (FCH_DATA_BLOCK *) LocHeapPtr.BufferPtr; + ASSERT (FchParams != NULL); + FchParams->StdHeader = StdHeader; + return FchParams; +} + + +STATIC VOID +RetrieveDataBlockFromInitReset ( + IN FCH_DATA_BLOCK *FchParams + ) +{ + LOCATE_HEAP_PTR LocHeapPtr; + FCH_RESET_DATA_BLOCK *ResetDb; + AGESA_STATUS AgesaStatus; + + LocHeapPtr.BufferHandle = AMD_FCH_RESET_DATA_BLOCK_HANDLE; + AgesaStatus = HeapLocateBuffer (&LocHeapPtr, FchParams->StdHeader); + if (AgesaStatus == AGESA_SUCCESS) { + ASSERT (LocHeapPtr.BufferPtr != NULL); + ResetDb = (FCH_RESET_DATA_BLOCK *) (LocHeapPtr.BufferPtr - sizeof (ResetDb) + sizeof (UINT32)); + // Override FchParams with contents in ResetDb + + FchParams->Usb.Xhci0Enable = ResetDb->FchReset.Xhci0Enable; + FchParams->Usb.Xhci1Enable = ResetDb->FchReset.Xhci1Enable; + FchParams->Spi.SpiFastSpeed = ResetDb->FastSpeed; + FchParams->Spi.WriteSpeed = ResetDb->WriteSpeed; + FchParams->Spi.SpiMode = ResetDb->Mode; + FchParams->Spi.AutoMode = ResetDb->AutoMode; + FchParams->Spi.SpiBurstWrite = ResetDb->BurstWrite; + FchParams->Sata.SataMode.Sata6AhciCap = (UINT8) ResetDb->Sata6AhciCap; + FchParams->Misc.Cg2Pll = ResetDb->Cg2Pll; + FchParams->Sata.SataMode.SataSetMaxGen2 = ResetDb->SataSetMaxGen2; + FchParams->Sata.SataMode.SataClkMode = ResetDb->SataClkMode; + FchParams->Sata.SataMode.SataModeReg = ResetDb->SataModeReg; + FchParams->Sata.SataInternal100Spread = (UINT8) ResetDb->SataInternal100Spread; + FchParams->Spi.SpiSpeed = ResetDb->SpiSpeed; + FchParams->Gpp = ResetDb->Gpp; + } +} + + +FCH_DATA_BLOCK* +FchInitEnvCreatePrivateData ( + IN AMD_ENV_PARAMS *EnvParams + ) +{ + FCH_DATA_BLOCK *FchParams; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + AGESA_STATUS AgesaStatus; + + // First allocate internal data block via heap manager + AllocHeapParams.RequestedBufferSize = sizeof (FCH_DATA_BLOCK); + AllocHeapParams.Persist = HEAP_SYSTEM_MEM; + AllocHeapParams.BufferHandle = AMD_FCH_DATA_BLOCK_HANDLE; + AgesaStatus = HeapAllocateBuffer (&AllocHeapParams, &EnvParams->StdHeader); + ASSERT (!AgesaStatus); + + FchParams = (FCH_DATA_BLOCK *) AllocHeapParams.BufferPtr; + ASSERT (FchParams != NULL); + IDS_HDT_CONSOLE (FCH_TRACE, " FCH Data Block Allocation: [0x%x], Ptr = 0x%08x\n", AgesaStatus, FchParams); + + // Load private data block with default + *FchParams = InitEnvCfgDefault; + FchParams->StdHeader = &EnvParams->StdHeader; + + RetrieveDataBlockFromInitReset (FchParams); + + // Update with external parameters + FchParams->Sd.SdConfig = EnvParams->FchInterface.SdConfig; + FchParams->Ir.IrConfig = EnvParams->FchInterface.IrConfig; + FchParams->Ab.NbSbGen2 = EnvParams->FchInterface.UmiGen2; + FchParams->Sata.SataClass = EnvParams->FchInterface.SataClass; + FchParams->Sata.SataMode.SataEnable = EnvParams->FchInterface.SataEnable; + FchParams->Sata.SataMode.IdeEnable = EnvParams->FchInterface.IdeEnable; + FchParams->Sata.SataIdeMode = EnvParams->FchInterface.SataIdeMode; + FchParams->Usb.Ohci1Enable = EnvParams->FchInterface.Ohci1Enable; + FchParams->Usb.Ehci1Enable = EnvParams->FchInterface.Ohci1Enable; + FchParams->Usb.Ohci2Enable = EnvParams->FchInterface.Ohci2Enable; + FchParams->Usb.Ehci2Enable = EnvParams->FchInterface.Ohci2Enable; + FchParams->Usb.Ohci3Enable = EnvParams->FchInterface.Ohci3Enable; + FchParams->Usb.Ehci3Enable = EnvParams->FchInterface.Ohci3Enable; + FchParams->Usb.Ohci4Enable = EnvParams->FchInterface.Ohci4Enable; + FchParams->HwAcpi.PwrFailShadow = EnvParams->FchInterface.FchPowerFail; + FchParams->HwAcpi.Smbus0BaseAddress = UserOptions.FchBldCfg->CfgSmbus0BaseAddress; + FchParams->HwAcpi.Smbus1BaseAddress = UserOptions.FchBldCfg->CfgSmbus1BaseAddress; + FchParams->HwAcpi.SioPmeBaseAddress = UserOptions.FchBldCfg->CfgSioPmeBaseAddress; + FchParams->HwAcpi.AcpiPm1EvtBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr; + FchParams->HwAcpi.AcpiPm1CntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr; + FchParams->HwAcpi.AcpiPmTmrBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr; + FchParams->HwAcpi.CpuControlBlkAddr = UserOptions.FchBldCfg->CfgCpuControlBlkAddr; + FchParams->HwAcpi.AcpiGpe0BlkAddr = UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr; + FchParams->HwAcpi.SmiCmdPortAddr = UserOptions.FchBldCfg->CfgSmiCmdPortAddr; + FchParams->HwAcpi.AcpiPmaCntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr; + FchParams->HwAcpi.WatchDogTimerBase = UserOptions.FchBldCfg->CfgWatchDogTimerBase; + FchParams->Sata.SataRaid5Ssid = UserOptions.FchBldCfg->CfgSataRaid5Ssid; + FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid; + FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid; + FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid; + FchParams->Gec.GecShadowRomBase = UserOptions.FchBldCfg->CfgGecShadowRomBase; + FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress; + FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid; + FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid; + FchParams->Hpet.HpetBase = UserOptions.FchBldCfg->CfgHpetBaseAddress; + FchParams->Smbus.SmbusSsid = UserOptions.FchBldCfg->CfgSmbusSsid; + FchParams->Ide.IdeSsid = UserOptions.FchBldCfg->CfgIdeSsid; + FchParams->Usb.EhciSsid = UserOptions.FchBldCfg->CfgEhciSsid; + FchParams->Usb.OhciSsid = UserOptions.FchBldCfg->CfgOhciSsid; + FchParams->Usb.XhciSsid = UserOptions.FchBldCfg->CfgXhciSsid; + FchParams->Ir.IrPinControl = UserOptions.FchBldCfg->CfgFchIrPinControl; + FchParams->Sd.SdClockControl = UserOptions.FchBldCfg->CfgFchSdClockControl; + return FchParams; +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitResetDef.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitResetDef.c new file mode 100644 index 0000000..b0c44d5 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitResetDef.c @@ -0,0 +1,117 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Fch Init during POWER-ON + * + * Prepare Fch environment during power on stage. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ + +#include "FchPlatform.h" +#include "Ids.h" +#include "heapManager.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_INTERFACE_INITRESETDEF_FILECODE + +extern FCH_RESET_DATA_BLOCK InitResetCfgDefault; + +FCH_RESET_DATA_BLOCK* +FchInitResetLoadPrivateDefault ( + IN AMD_RESET_PARAMS *ResetParams + ); + +FCH_RESET_DATA_BLOCK* +FchInitResetLoadPrivateDefault ( + IN AMD_RESET_PARAMS *ResetParams + ) +{ + FCH_RESET_DATA_BLOCK *FchParams; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + AGESA_STATUS AgesaStatus; + + // First allocate internal data block via heap manager + AllocHeapParams.RequestedBufferSize = sizeof (FCH_RESET_DATA_BLOCK); + AllocHeapParams.Persist = HEAP_TEMP_MEM + 1; + AllocHeapParams.BufferHandle = AMD_FCH_RESET_DATA_BLOCK_HANDLE; + AgesaStatus = HeapAllocateBuffer (&AllocHeapParams, &ResetParams->StdHeader); + ASSERT (!AgesaStatus); + + FchParams = (FCH_RESET_DATA_BLOCK *) AllocHeapParams.BufferPtr; + ASSERT (FchParams != NULL); + IDS_HDT_CONSOLE (FCH_TRACE, " FCH Reset Data Block Allocation: [0x%x], Ptr = 0x%08x\n", AgesaStatus, FchParams); + + *FchParams = InitResetCfgDefault; + + FchParams->Gpp.GppLinkConfig = UserOptions.FchBldCfg->CfgFchGppLinkConfig; + FchParams->Gpp.PortCfg[0].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort0Present; + FchParams->Gpp.PortCfg[1].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort1Present; + FchParams->Gpp.PortCfg[2].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort2Present; + FchParams->Gpp.PortCfg[3].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort3Present; + FchParams->Gpp.PortCfg[0].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort0HotPlug; + FchParams->Gpp.PortCfg[1].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort1HotPlug; + FchParams->Gpp.PortCfg[2].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort2HotPlug; + FchParams->Gpp.PortCfg[3].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort3HotPlug; + + return FchParams; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ir/IrEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ir/IrEnv.c new file mode 100644 index 0000000..59780b4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ir/IrEnv.c @@ -0,0 +1,135 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Ir controller + * + * Init Ir Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_IR_IRENV_FILECODE + +/** + * FchInitEnvIr - Config Ir controller before PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvIr ( + IN VOID *FchDataPtr + ) +{ + IR_CONFIG FchIrConfig; + UINT8 FchIrPinControl; + UINT8 Data; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + FchIrConfig = LocalCfgPtr->Ir.IrConfig; + FchIrPinControl = LocalCfgPtr->Ir.IrPinControl; + + // + //IR init Logical device 0x05 + // + if (FchIrConfig != IrDisable) { + EnterEcConfig (StdHeader); + + RwEc8 (0x07, 0x00, 0x05, StdHeader); ///Select logical device 05, IR controller + RwEc8 (0x60, 0x00, 0x05, StdHeader); ///Set Base Address to 550h + RwEc8 (0x61, 0x00, 0x50, StdHeader); + RwEc8 (0x70, 0xF0, 0x05, StdHeader); ///Set IRQ to 05h + RwEc8 (0x30, 0x00, 0x01, StdHeader); ///Enable logical device 5, IR controller + + Data = 0xAB; + LibAmdIoWrite (AccessWidth8, 0x550, &Data, StdHeader); + LibAmdIoRead (AccessWidth8, 0x551, &Data, StdHeader); + Data = (UINT8) (FchIrPinControl & 0xFC); ///Take out enable bits + Data |= FchIrPinControl & FchIrConfig & 0x03; ///Put back enable bits + LibAmdIoWrite (AccessWidth8, 0x551, &Data, StdHeader); + + ExitEcConfig (StdHeader); + + Data = 0xA0; /// EC APIC index + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Data, StdHeader); + Data = 0x05; /// IRQ5 + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Data, StdHeader); + } else { + EnterEcConfig (StdHeader); + + RwEc8 (0x07, 0x00, 0x05, StdHeader); ///Select logical device 05, IR controller + RwEc8 (0x30, 0x00, 0x00, StdHeader); ///Disable logical device 5, IR controller + Data = 0xAB; + LibAmdIoWrite (AccessWidth8, 0x550, &Data, StdHeader); + LibAmdIoRead (AccessWidth8, 0x551, &Data, StdHeader); + Data = ((UINT8) FchIrPinControl) & 0xFC; //Clear Enable bits + LibAmdIoWrite (AccessWidth8, 0x551, &Data, StdHeader); + ExitEcConfig (StdHeader); + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ir/IrLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ir/IrLate.c new file mode 100644 index 0000000..c8dcfc0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ir/IrLate.c @@ -0,0 +1,87 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Ir controller + * + * Init Ir Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_IR_IRLATE_FILECODE + +/** + * FchInitLateIr - Prepare Ir controller to boot to OS. + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitLateIr ( + IN VOID *FchDataPtr + ) +{ +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ir/IrMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ir/IrMid.c new file mode 100644 index 0000000..7ec4513 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Ir/IrMid.c @@ -0,0 +1,87 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Ir controller + * + * Init Ir Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_IR_IRMID_FILECODE + +/** + * FchInitMidIr - Config Ir controller after PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidIr ( + IN VOID *FchDataPtr + ) +{ +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibEnv.c new file mode 100644 index 0000000..e0c604a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibEnv.c @@ -0,0 +1,134 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Pcib controller + * + * Init Pcib Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_PCIB_PCIBENV_FILECODE + +/** + * FchInitEnvPcibPciTable - PCI device registers initial during + * early POST. + * + */ +REG8_MASK FchInitEnvPcibPciTable[] = +{ + // + // PCIB Bridge (Bus 0, Dev 20, Func 4) + // + {0x00, PCIB_BUS_DEV_FUN, 0}, + {FCH_PCIB_REG40, 0xFF, BIT5}, /// PCI-bridge Subtractive Decode + {FCH_PCIB_REG4B, 0xFF, BIT7}, /// + {0x66 , 0xFF, BIT4}, /// Enabling One-Prefetch-Channel Mode, PCIB_PCI_config 0x64 [20] + {0x65 , 0xFF, BIT7}, /// proper operation of CLKRUN#. + {FCH_PCIB_REG0D, 0x00, 0x40}, /// Setting Latency Timers to 0x40, Enables the PCIB to retain ownership + {FCH_PCIB_REG1B, 0x00, 0x40}, /// of the bus on the Primary side and on the Secondary side when GNT# is deasserted. + {FCH_PCIB_REG66 + 1, 0xFF, BIT1}, /// Enable PCI bus GNT3#.. + {0xFF, 0xFF, 0xFF}, +}; + +/** + * FchInitEnvPcib - Config Pcib controller before PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvPcib ( + IN VOID *FchDataPtr + ) +{ + UINT8 VerbPciClks; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + // + //Early post initialization of pci config space + // + ProgramPciByteTable ((REG8_MASK*) (&FchInitEnvPcibPciTable[0]), sizeof (FchInitEnvPcibPciTable) / sizeof (REG8_MASK), StdHeader); + + // + //Disable or Enable PCI Clks based on input + // + VerbPciClks = ((LocalCfgPtr->Pcib.PciClks & 0x0F) << 2); + RwPci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG42, AccessWidth8, (UINT32)~(BIT5 + BIT4 + BIT3 + BIT2), VerbPciClks, StdHeader); + VerbPciClks = ((LocalCfgPtr->Pcib.PciClks & 0x10) >> 4); + RwPci ((PCIB_BUS_DEV_FUN << 16) + 0x4A , AccessWidth8, (UINT32)~BIT0, VerbPciClks, StdHeader); + // + // PCIB MSI + // + if (LocalCfgPtr->Pcib.PcibMsiEnable) { + RwPci ((PCIB_BUS_DEV_FUN << 16) + 0x40 , AccessWidth8, (UINT32)~BIT3, BIT3, StdHeader); + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibLate.c new file mode 100644 index 0000000..91b3a65 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibLate.c @@ -0,0 +1,121 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Pcib controller + * + * Init Pcib Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_PCIB_PCIBLATE_FILECODE + +/** + * FchInitLatePcib - Prepare Pcib controller to boot to OS. + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitLatePcib ( + IN VOID *FchDataPtr + ) +{ + UINT8 Value; + UINT8 NStBit; + UINT8 NSBit; + UINT32 VarDd; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + // + // We need to do the following setting in late post also because some bios core pci enumeration changes these values + // programmed during early post. + // Master Latency Timer + // + Value = 0x40; + WritePci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG0D, AccessWidth8, &Value, StdHeader); + WritePci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG1B, AccessWidth8, &Value, StdHeader); + + // + // CLKRUN# + // FCH P2P AutoClock control settings. + // VarDd = (FchDataPtr->PcibAutoClkCtrlLow) | (FchDataPtr->PcibAutoClkCtrlLow); + // + if ( LocalCfgPtr->Pcib.PcibClockRun ) { + ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG54, AccessWidth8, &Value); + NStBit = Value & 0x03; + NSBit = (Value & 0x3F ) >> 2; + VarDd = (4 + (NStBit * 2) + (( 17 + NSBit) * 3) + 4) | 0x01; + + VarDd = 9; // for A12 + WritePci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG4C, AccessWidth32, &VarDd, StdHeader); + } + + VarDd = (LocalCfgPtr->Pcib.PcibClkStopOverride); + RwPci ((PCIB_BUS_DEV_FUN << 16) + 0x50 , AccessWidth16, 0x3F, (UINT16) (VarDd << 6), StdHeader); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibMid.c new file mode 100644 index 0000000..02f6dd7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibMid.c @@ -0,0 +1,87 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Pcib controller + * + * Init Pcib Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_PCIB_PCIBMID_FILECODE + +/** + * FchInitMidPcib - Config Pcib controller after PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidPcib ( + IN VOID *FchDataPtr + ) +{ +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibReset.c new file mode 100644 index 0000000..231b9f2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibReset.c @@ -0,0 +1,163 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Pcib controller + * + * Init Pcib Controller features (PEI phase). + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_PCIB_PCIBRESET_FILECODE +/** + * FchInitResetPcibPciTable - Pcib device registers initial + * during the power on stage. + * + * + * + * + */ +REG8_MASK FchInitResetPcibPciTable[] = +{ + // + // P2P Bridge (Bus 0, Dev 20, Func 4) + // + {0x00, PCIB_BUS_DEV_FUN, 0}, + {FCH_PCIB_REG4B, 0xFF, BIT6 + BIT7 + BIT4}, + {FCH_PCIB_REG40, 0xDF, 0x20}, + {0x50 , 0x02, 0x01}, + {0xFF, 0xFF, 0xFF}, +}; + +/** + * FchInitResetPcib - Config Pcib controller during Power-On + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitResetPcib ( + IN VOID *FchDataPtr + ) +{ + AMD_CONFIG_PARAMS *StdHeader; + + StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader; + + ProgramPciByteTable ( + (REG8_MASK*) (&FchInitResetPcibPciTable[0]), + sizeof (FchInitResetPcibPciTable) / sizeof (REG8_MASK), + StdHeader + ); + if ( UserOptions.FchBldCfg->CfgFchPort80BehindPcib ) { + FchInitResetPcibPort80Enable (FchDataPtr); + } +} + +/** + * FchInitResetPcibPort80Enable - Pcib device registers initial + * during the power on stage. + * + * + * + * + */ +REG8_MASK FchInitResetPcibPort80EnableTable[] = +{ + // + // P2P Bridge (Bus 0, Dev 20, Func 4) + // + {0x00, PCIB_BUS_DEV_FUN, 0}, + {0x1C , 0x00, 0xF0}, + {0x1D , 0x00, 0x00}, + {0x04 , 0x00, 0x21}, + {0xFF, 0xFF, 0xFF}, +}; + +/** + * FchInitResetPcibPort80Enable - Enable Port80 Behind PCIB + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitResetPcibPort80Enable ( + IN VOID *FchDataPtr + ) +{ + AMD_CONFIG_PARAMS *StdHeader; + + StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader; + + ProgramPciByteTable ( + (REG8_MASK*) (&FchInitResetPcibPort80EnableTable[0]), + sizeof (FchInitResetPcibPort80EnableTable) / sizeof (REG8_MASK), + StdHeader + ); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbEnv.c new file mode 100644 index 0000000..e72ed25 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbEnv.c @@ -0,0 +1,106 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Ab Bridge + * + * Init Ab Bridge features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_PCIE_ABENV_FILECODE + +/** + * FchInitEnvAb - Config Ab Bridge before PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvAb ( + IN VOID *FchDataPtr + ) +{ + FchInitEnvAbLinkInit (FchDataPtr); +} + +/** + * FchInitEnvAbSpecial - Config Ab Bridge special timing + * + * This routine must separate with FchInitEnvAb and give Ab + * bridge little time to get ready + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvAbSpecial ( + IN VOID *FchDataPtr + ) +{ +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbLate.c new file mode 100644 index 0000000..d610b2a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbLate.c @@ -0,0 +1,94 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Ab Bridge + * + * Init Ab Bridge features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_PCIE_ABLATE_FILECODE + +/** + * FchInitLateAb - Prepare Ab Bridge to boot to OS. + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitLateAb ( + IN VOID *FchDataPtr + ) +{ + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + FchAbLateProgram (FchDataPtr); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbMid.c new file mode 100644 index 0000000..a883876 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbMid.c @@ -0,0 +1,89 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Ab Bridge + * + * Init Ab Bridge features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_PCIE_ABMID_FILECODE + +/** + * FchInitMidAb - Config Ab Bridge after PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidAb ( + IN VOID *FchDataPtr + ) +{ +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbReset.c new file mode 100644 index 0000000..dbb3973 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/AbReset.c @@ -0,0 +1,91 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Ab Bridge + * + * Init Ab Bridge features (PEI phase). + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#include "FchDef.h" +#define FILECODE PROC_FCH_PCIE_ABRESET_FILECODE + +/** + * FchInitResetAb - Config Ab Bridge during Power-On + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitResetAb ( + IN VOID *FchDataPtr + ) +{ + FchProgramAbPowerOnReset (FchDataPtr); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbEnvService.c new file mode 100644 index 0000000..af00e01 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbEnvService.c @@ -0,0 +1,387 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Hudson2 AB + * + * Init AB bridge. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABENVSERVICE_FILECODE + +// +// Declaration of local functions +// +VOID AbCfgTbl (IN AB_TBL_ENTRY *ABTbl, IN AMD_CONFIG_PARAMS *StdHeader); + +/** + * Hudson2PcieOrderRule - AB-Link Configuration Table for ablink + * Post Pass Np Downstream/Upstream Feature + * + */ +AB_TBL_ENTRY Hudson2PcieOrderRule[] = +{ + // + // abPostPassNpDownStreamTbl + // + {ABCFG, FCH_ABCFG_REG10060, BIT31, BIT31}, + {ABCFG, FCH_ABCFG_REG1009C, BIT4 + BIT5, BIT4 + BIT5}, + {ABCFG, FCH_ABCFG_REG9C, BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7, BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7}, + {ABCFG, FCH_ABCFG_REG90, BIT21 + BIT22 + BIT23, BIT21 + BIT22 + BIT23}, + {ABCFG, FCH_ABCFG_REGF0, BIT6 + BIT5, BIT6 + BIT5}, + {AXINDC, FCH_AX_INDXC_REG02, BIT9, BIT9}, + {ABCFG, FCH_ABCFG_REG10090, BIT9 + BIT10 + BIT11 + BIT12, BIT9 + BIT10 + BIT11 + BIT12}, + + // + // abPostPassNpUpStreamTbl + // + {ABCFG, FCH_ABCFG_REG58, BIT10, BIT10}, + {ABCFG, FCH_ABCFG_REGF0, BIT3 + BIT4, BIT3 + BIT4}, + {ABCFG, FCH_ABCFG_REG54, BIT1, BIT1}, + { (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF}, +}; + +/** + * Hudson2InitEnvAbTable - AB-Link Configuration Table for Hudson2 + * + */ +AB_TBL_ENTRY Hudson2InitEnvAbTable[] = +{ + // + // Enable downstream posted transactions to pass non-posted transactions. + // + {ABCFG, FCH_ABCFG_REG10090, BIT8 + BIT16, BIT8 + BIT16}, + + // + // Enable Hudson-2 to issue memory read/write requests in the upstream direction. + // + {AXCFG, FCH_AB_REG04, BIT2, BIT2}, + + // + // Enabling IDE/PCIB Prefetch for Performance Enhancement + // PCIB prefetch ABCFG 0x10060 [20] = 1 ABCFG 0x10064 [20] = 1 + // + {ABCFG, FCH_ABCFG_REG10060, BIT20, BIT20}, /// PCIB prefetch enable + {ABCFG, FCH_ABCFG_REG10064, BIT20, BIT20}, /// PCIB prefetch enable + + // + // Controls the USB OHCI controller prefetch used for enhancing performance of ISO out devices. + // Setting B-Link Prefetch Mode (ABCFG 0x80 [18:17] = 11) + // + {ABCFG, FCH_ABCFG_REG80, BIT0 + BIT17 + BIT18, BIT0 + BIT17 + BIT18}, + + // + // Enabled SMI ordering enhancement. ABCFG 0x90[21] + // USB Delay A-Link Express L1 State. ABCFG 0x90[17] + // + {ABCFG, FCH_ABCFG_REG90, BIT21 + BIT17, BIT21 + BIT17}, + + // + // Disable the credit variable in the downstream arbitration equation + // Register bit to qualify additional address bits into downstream register programming. (A12 BIT1 default is set) + // + {ABCFG, FCH_ABCFG_REG9C, BIT0, BIT0}, + + // + // Enabling Detection of Upstream Interrupts ABCFG 0x94 [20] = 1 + // ABCFG 0x94 [19:0] = cpu interrupt delivery address [39:20] + // + {ABCFG, FCH_ABCFG_REG94, BIT20, BIT20 + 0x00FEE}, + + // + // Programming cycle delay for AB and BIF clock gating + // Enable the AB and BIF clock-gating logic. + // Enable the A-Link int_arbiter enhancement to allow the A-Link bandwidth to be used more efficiently + // Enable the requester ID for upstream traffic. [16]: SB/NB link [17]: GPP + // + {ABCFG, FCH_ABCFG_REG10054, 0x00FFFFFF, 0x010407FF}, + {ABCFG, FCH_ABCFG_REG98, 0xFFFC00FF, 0x00034700}, + {ABCFG, FCH_ABCFG_REG54, 0x00FF0000, 0x00040000}, + + // + // Non-Posted Memory Write Support + // + {AXINDC, FCH_AX_INDXC_REG10, BIT9, BIT9}, + + // + // UMI L1 Configuration + //Step 1: AXINDC_Reg 0x02[0] = 0x1 Set REGS_DLP_IGNORE_IN_L1_EN to ignore DLLPs during L1 so that txclk can be turned off. + //Step 2: AXINDP_Reg 0x02[15] = 0x1 Sets REGS_LC_ALLOW_TX_L1_CONTROL to allow TX to prevent LC from going to L1 when there are outstanding completions. + // + {AXINDC, FCH_AX_INDXC_REG02, BIT0, BIT0}, + {AXINDP, FCH_AX_INDXP_REG02, BIT15, BIT15}, + {ABCFG, 0, 0, (UINT8) 0xFF}, /// This dummy entry is to clear ab index + { (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF}, +}; + +/** + * FchInitEnvAbLinkInit - Set ABCFG registers before PCI + * emulation. + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvAbLinkInit ( + IN VOID *FchDataPtr + ) +{ + UINT32 AbValue; + UINT16 AbTempVar; + UINT8 AbValue8; + UINT8 FchALinkClkGateOff; + UINT8 FchBLinkClkGateOff; + UINT32 FchResetCpuOnSyncFlood; + AB_TBL_ENTRY *AbTblPtr; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + FchALinkClkGateOff = (UINT8) LocalCfgPtr->Ab.ALinkClkGateOff; + FchBLinkClkGateOff = (UINT8) LocalCfgPtr->Ab.BLinkClkGateOff; + // + // AB CFG programming + // + if ( LocalCfgPtr->Ab.SlowSpeedAbLinkClock ) { + RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, (UINT32)~BIT1, BIT1); + } else { + RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, (UINT32)~BIT1, 0); + } + + // + // Read Arbiter address, Arbiter address is in PMIO 6Ch + // + ReadMem (ACPI_MMIO_BASE + PMIO_BASE + 0x6C , AccessWidth16, &AbTempVar); + /// Write 0 to enable the arbiter + AbValue8 = 0; + LibAmdIoWrite (AccessWidth8, AbTempVar, &AbValue8, StdHeader); + + + FchResetCpuOnSyncFlood = LocalCfgPtr->Ab.ResetCpuOnSyncFlood; + + if ( LocalCfgPtr->Ab.PcieOrderRule == 1 ) { + AbTblPtr = (AB_TBL_ENTRY *) (&Hudson2PcieOrderRule[0]); + AbCfgTbl (AbTblPtr, StdHeader); + } + + if ( LocalCfgPtr->Ab.PcieOrderRule == 2 ) { + RwAlink (FCH_ABCFG_REG10090 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x7 << 10), (UINT32) (0x7 << 10), StdHeader); + RwAlink (FCH_ABCFG_REG58 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1F << 11), (UINT32) (0x1C << 11), StdHeader); + RwAlink (FCH_ABCFG_REGB4 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x3 << 0), (UINT32) (0x3 << 0), StdHeader); + } + + AbTblPtr = (AB_TBL_ENTRY *) (&Hudson2InitEnvAbTable[0]); + AbCfgTbl (AbTblPtr, StdHeader); + + if ( FchResetCpuOnSyncFlood ) { + RwAlink (FCH_ABCFG_REG10050 | (UINT32) (ABCFG << 29), (UINT32)~BIT2, BIT2, StdHeader); + } + + if ( LocalCfgPtr->Ab.AbClockGating ) { + RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16), StdHeader); + RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16), StdHeader); + RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x1 << 24), StdHeader); + RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x1 << 24), StdHeader); + } else { + RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x0 << 24), StdHeader); + RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x0 << 24), StdHeader); + } + + + if ( LocalCfgPtr->Ab.GppClockGating ) { + RwAlink (FCH_ABCFG_REG98 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xF << 12), (UINT32) (0x4 << 12), StdHeader); + RwAlink (FCH_ABCFG_REG98 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xF << 8), (UINT32) (0x7 << 8), StdHeader); + RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x1 << 0), StdHeader); + } else { + RwAlink (FCH_ABCFG_REG98 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xF << 8), (UINT32) (0x0 << 8), StdHeader); + RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x0 << 0), StdHeader); + } + + if ( LocalCfgPtr->Ab.UmiL1TimerOverride ) { + RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x7 << 12), (UINT32) (LocalCfgPtr->Ab.UmiL1TimerOverride << 12), StdHeader); + RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 15), (UINT32) (0x1 << 15), StdHeader); + } + + if ( LocalCfgPtr->Ab.UmiLinkWidth ) { +// RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16)); + } + + if ( LocalCfgPtr->Ab.UmiDynamicSpeedChange ) { + RwAlink ((UINT32) FCH_AX_INDXP_REGA4, ~ (UINT32) (0x1 << 0), (UINT32) (0x1 << 0), StdHeader); + RwAlink ((UINT32) FCH_AX_CFG_REG88, ~ (UINT32) (0xF << 0), (UINT32) (0x2 << 0), StdHeader); + RwAlink ((UINT32) FCH_AX_INDXP_REGA4, ~ (UINT32) (0x1 << 18), (UINT32) (0x1 << 18), StdHeader); + } + + if ( LocalCfgPtr->Ab.PcieRefClockOverClocking ) { +// RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16)); + } + + if ( LocalCfgPtr->Ab.UmiGppTxDriverStrength ) { + RwAlink (FCH_ABCFG_REGA8 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x3 << 18), (UINT32) ((LocalCfgPtr->Ab.UmiGppTxDriverStrength - 1) << 18), StdHeader); + RwAlink (FCH_ABCFG_REGA0 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 8), (UINT32) (0x1 << 8), StdHeader); + } + + if ( LocalCfgPtr->Gpp.PcieAer ) { +// RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16)); + } + + if ( LocalCfgPtr->Gpp.PcieRas ) { +// RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16)); + } + + // + // Ab Bridge MSI + // + if ( LocalCfgPtr->Ab.AbMsiEnable) { + AbValue = ReadAlink (FCH_ABCFG_REG94 | (UINT32) (ABCFG << 29), StdHeader); + AbValue = AbValue | BIT20; + WriteAlink (FCH_ABCFG_REG94 | (UINT32) (ABCFG << 29), AbValue, StdHeader); + } + + // + // A/B Clock Gate-OFF + // + if ( FchALinkClkGateOff ) { + RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x2E, AccessWidth8, 0xFE, BIT0); + } else { + RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x2E, AccessWidth8, 0xFE, 0x00); + } + + if ( FchBLinkClkGateOff ) { + //RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x2D, AccessWidth8, 0xEF, 0x10); /// A11 Only + RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x2E, AccessWidth8, 0xFD, BIT1); + } else { + RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x2E, AccessWidth8, 0xFD, 0x00); + } +} + +/** + * AbCfgTbl - Program ABCFG by input table. + * + * + * @param[in] ABTbl ABCFG config table. + * @param[in] StdHeader + * + */ +VOID +AbCfgTbl ( + IN AB_TBL_ENTRY *ABTbl, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 AbValue; + + while ( (ABTbl->RegType) != 0xFF ) { + if ( ABTbl->RegType == AXINDC ) { + AbValue = 0x30 | (ABTbl->RegType << 29); + WriteAlink (AbValue, (ABTbl->RegIndex & 0x00FFFFFF), StdHeader); + AbValue = 0x34 | (ABTbl->RegType << 29); + WriteAlink (AbValue, ((ReadAlink (AbValue, StdHeader)) & (0xFFFFFFFF^ (ABTbl->RegMask))) | ABTbl->RegData, StdHeader); + } else if ( ABTbl->RegType == AXINDP ) { + AbValue = 0x38 | (ABTbl->RegType << 29); + WriteAlink (AbValue, (ABTbl->RegIndex & 0x00FFFFFF), StdHeader); + AbValue = 0x3C | (ABTbl->RegType << 29); + WriteAlink (AbValue, ((ReadAlink (AbValue, StdHeader)) & (0xFFFFFFFF^ (ABTbl->RegMask))) | ABTbl->RegData, StdHeader); + } else { + AbValue = ABTbl->RegIndex | (ABTbl->RegType << 29); + WriteAlink (AbValue, ((ReadAlink (AbValue, StdHeader)) & (0xFFFFFFFF^ (ABTbl->RegMask))) | ABTbl->RegData, StdHeader); + } + + ++ABTbl; + } + + // + //Clear ALink Access Index + // + AbValue = 0; + LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &AbValue, StdHeader); +} + +/** + * Is UMI One Lane GEN1 Mode? + * + * + * @retval TRUE or FALSE + * + */ +BOOLEAN +IsUmiOneLaneGen1Mode ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 AbValue; + + AbValue = ReadAlink ((UINT32) (FCH_AX_CFG_REG68), StdHeader); + AbValue >>= 16; + if (((AbValue & 0x0f) == 1) && ((AbValue & 0x03f0) == 0x0010)) { + return (TRUE); + } else { + return (FALSE); + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c new file mode 100644 index 0000000..ffed1ff --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c @@ -0,0 +1,145 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Hudson2 AB + * + * Init AB bridge. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABRESETSERVICE_FILECODE + + +/** + * FchProgramAbPowerOnReset - Config Ab Bridge during Power-On + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchProgramAbPowerOnReset ( + IN VOID *FchDataPtr + ) +{ + UINT32 AbValue; + FCH_RESET_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + UINT8 EfuseValue; + + LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + // + // Set A-Link bridge access address. + // This is an I/O address. The I/O address must be on 16-byte boundary. + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGE0, AccessWidth32, 00, ALINK_ACCESS_INDEX); + + // + // Enable Hudson-2 to issue memory read/write requests in the upstream direction + // + WriteAlink (0x80000004, 0x04, StdHeader); + + // + // Disable the credit variable in the downstream arbitration equation + // + AbValue = ReadAlink (FCH_ABCFG_REG9C | (UINT32) (ABCFG << 29), StdHeader); + AbValue = AbValue | BIT0; + WriteAlink (FCH_ABCFG_REG9C | (UINT32) (ABCFG << 29), AbValue, StdHeader); + + // + // AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform. + // + WriteAlink (0x30, 0x10, StdHeader); + WriteAlink (0x34, ReadAlink (0x34, StdHeader) | BIT9, StdHeader); + + RwAlink (FCH_ABCFG_REG10050 | (UINT32) (ABCFG << 29), (UINT32)~BIT2, 0x00, StdHeader); + + // + // Configure UMI target link speed + // + EfuseValue = PCIE_FORCE_GEN1_EFUSE_LOCATION; + GetEfuseStatus (&EfuseValue, StdHeader); + if ( EfuseValue & BIT0 ) { + LocalCfgPtr->FchReset.UmiGen2 = FALSE; + } + + EfuseValue = FCH_Variant_EFUSE_LOCATION; + GetEfuseStatus (&EfuseValue, StdHeader); + if ((EfuseValue == 0x07) || (EfuseValue == 0x08)) { + LocalCfgPtr->FchReset.UmiGen2 = FALSE; + } + + AbValue = LocalCfgPtr->FchReset.UmiGen2 ? 2 : 1; + RwAlink ((UINT32)FCH_AX_CFG_REG88, 0xFFFFFFF0, AbValue, StdHeader); + + AbValue = LocalCfgPtr->FchReset.UmiGen2 ? BIT0 : 0; + RwAlink (FCH_AX_INDXP_REGA4, 0xFFFFFFFE, AbValue, StdHeader); + +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbService.c new file mode 100644 index 0000000..46a7253 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbService.c @@ -0,0 +1,101 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Hudson2 AB + * + * Init AB bridge. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABSERVICE_FILECODE + +/** + * FchAbLateProgram - Set ABCFG registers during late POST + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchAbLateProgram ( + IN VOID *FchDataPtr + ) +{ + UINT32 AbValue; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + AbValue = ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader); + AbValue &= 0xf0; + + if ( LocalCfgPtr->Ab.PcieOrderRule && AbValue ) { + AbValue = ReadAlink (FCH_RCINDXC_REG02, StdHeader); + AbValue = AbValue | BIT9; + WriteAlink (FCH_RCINDXC_REG02, AbValue, StdHeader); + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c new file mode 100644 index 0000000..5635a5e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c @@ -0,0 +1,150 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Hudson2 Pcie controller + * + * Init GPP (pcie Controller) features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPRESETSERVICE_FILECODE + + +/** + * ProgramFchGppInitReset - Config Gpp at PowerOnReset + * + * + * @param[in] FchGpp Pointer to Fch GPP configuration structure + * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS + * + */ +VOID +ProgramFchGppInitReset ( + IN FCH_GPP *FchGpp, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + // + // Toggle GEVENT4 to reset all GPP devices + // + ProgramGppTogglePcieReset (FchGpp->GppToggleReset, StdHeader); + if (FchGpp->SerialDebugBusEnable) { + RwAlink (FCH_ABCFG_REGC0, (UINT32) (ABCFG << 29), (UINT32)~BIT12, 0x00); + } +} + +/** + * FchResetPcie - Toggle GEVENT4 to assert/deassert GPP device + * reset + * + * + * @param[in] ResetBlock - PCIE reset for FCH GPP or NB PCIE + * @param[in] ResetOp - Assert or deassert PCIE reset + * @param[in] StdHeader + * + */ +VOID +FchResetPcie ( + IN RESET_BLOCK ResetBlock, + IN RESET_OP ResetOp, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 Or8; + UINT8 Mask8; + + if (ResetBlock == NbBlock) { + if (ResetOp == AssertReset) { + Or8 = BIT4; + Mask8 = 0; + LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC4), &Or8, &Mask8, StdHeader); + } else if (ResetOp == DeassertReset) { + Or8 = 0; + Mask8 = BIT4; + LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC4), &Or8, &Mask8, StdHeader); + } + } else if (ResetBlock == FchBlock) { + Or8 = BIT1; + Mask8 = BIT1 + BIT0; + LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GEVENT_REG04), &Or8, &Mask8, StdHeader); + if (ResetOp == AssertReset) { + Or8 = 0; + Mask8 = BIT5; + LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + GPIO_BASE + FCH_GEVENT_REG04), &Or8, &Mask8, StdHeader); + Or8 = BIT4; + Mask8 = 0; + LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBF), &Or8, &Mask8, StdHeader); + } else if (ResetOp == DeassertReset) { + Or8 = 0; + Mask8 = BIT4; + LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBF), &Or8, &Mask8, StdHeader); + Or8 = BIT5; + Mask8 = 0; + LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + GPIO_BASE + FCH_GEVENT_REG04), &Or8, &Mask8, StdHeader); + } + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c new file mode 100644 index 0000000..f1e2f42 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c @@ -0,0 +1,223 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Hudson2 Pcie controller + * + * Init GPP (pcie Controller) features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Ids.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPSERVICE_FILECODE + +/** + * ProgramGppTogglePcieReset - Toggle PCIE_RST2# + * + * + * @param[in] DoToggling + * @param[in] StdHeader + * + */ +VOID +ProgramGppTogglePcieReset ( + IN BOOLEAN DoToggling, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + if (DoToggling) { + FchResetPcie (FchBlock, AssertReset, StdHeader); + FchStall (500, StdHeader); + FchResetPcie (FchBlock, DeassertReset, StdHeader); + } else { + RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GEVENT_REG04, AccessWidth8, (UINT32)~(BIT1 + BIT0), 0x02); + } +} + +/** + * FchGppDynamicPowerSaving - GPP Dynamic Power Saving + * + * + * @param[in] FchGpp Pointer to Fch GPP configuration structure + * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS + * + */ +VOID +FchGppDynamicPowerSaving ( + IN FCH_GPP *FchGpp, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + FCH_GPP_PORT_CONFIG *PortCfg; + UINT32 GppData32; + UINT32 HoldGppData32; + UINT32 AbValue; + + if (!FchGpp->GppDynamicPowerSaving || FchGpp->SerialDebugBusEnable) { + return; + } + + if (FchGpp->GppHardwareDownGrade) { + PortCfg = &FchGpp->PortCfg[FchGpp->GppHardwareDownGrade - 1]; + PortCfg->PortDetected = TRUE; + } + + GppData32 = 0; + HoldGppData32 = 0; + + switch ( FchGpp->GppLinkConfig ) { + case PortA4: + PortCfg = &FchGpp->PortCfg[0]; + if ( PortCfg->PortDetected == FALSE ) { + GppData32 |= 0x0f0f; + HoldGppData32 |= 0x1000; + } + break; + + case PortA2B2: + PortCfg = &FchGpp->PortCfg[0]; + if ( PortCfg->PortDetected == FALSE ) { + GppData32 |= ( FchGpp->GppLaneReversal )? 0x0c0c:0x0303; + HoldGppData32 |= 0x1000; + } + + PortCfg = &FchGpp->PortCfg[1]; + if ( PortCfg->PortDetected == FALSE ) { + GppData32 |= ( FchGpp->GppLaneReversal )? 0x0303:0x0c0c; + HoldGppData32 |= 0x2000; + } + break; + + case PortA2B1C1: + PortCfg = &FchGpp->PortCfg[0]; + if ( PortCfg->PortDetected == FALSE ) { + GppData32 |= ( FchGpp->GppLaneReversal )? 0x0c0c:0x0303; + HoldGppData32 |= 0x1000; + } + + PortCfg = &FchGpp->PortCfg[1]; + if ( PortCfg->PortDetected == FALSE ) { + GppData32 |= ( FchGpp->GppLaneReversal )? 0x0202:0x0404; + HoldGppData32 |= 0x2000; + } + + PortCfg = &FchGpp->PortCfg[2]; + if ( PortCfg->PortDetected == FALSE ) { + GppData32 |= ( FchGpp->GppLaneReversal )? 0x0101:0x0808; + HoldGppData32 |= 0x4000; + } + break; + + case PortA1B1C1D1: + PortCfg = &FchGpp->PortCfg[0]; + if ( PortCfg->PortDetected == FALSE ) { + GppData32 |= ( FchGpp->GppLaneReversal )? 0x0808:0x0101; + HoldGppData32 |= 0x1000; + } + + PortCfg = &FchGpp->PortCfg[1]; + if ( PortCfg->PortDetected == FALSE ) { + GppData32 |= ( FchGpp->GppLaneReversal )? 0x0404:0x0202; + HoldGppData32 |= 0x2000; + } + + PortCfg = &FchGpp->PortCfg[2]; + if ( PortCfg->PortDetected == FALSE ) { + GppData32 |= ( FchGpp->GppLaneReversal )? 0x0202:0x0404; + HoldGppData32 |= 0x4000; + } + + PortCfg = &FchGpp->PortCfg[3]; + if ( PortCfg->PortDetected == FALSE ) { + GppData32 |= ( FchGpp->GppLaneReversal )? 0x0101:0x0808; + HoldGppData32 |= 0x8000; + } + break; + + default: + ASSERT (FALSE); + break; + } + + // + // Power Saving With GPP Disable + // ABCFG 0xC0[8] = 0x0 + // ABCFG 0xC0[15:12] = 0xF + // Enable "Power Saving Feature for A-Link Express Lanes" + // Enable "Power Saving Feature for GPP Lanes" + // ABCFG 0x90[19] = 1 + // ABCFG 0x90[6] = 1 + // RCINDC_Reg 0x65 [27:0] = 0xFFFFFFF + // ABCFG 0xC0[7:4] = 0x0 + // + if (FchGpp->UmiPhyPllPowerDown && FchGpp->GppPhyPllPowerDown ) { + AbValue = ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader); + WriteAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), (( AbValue | HoldGppData32 ) & (~ BIT8 )), StdHeader); + RwAlink (FCH_AX_INDXC_REG40, (UINT32)~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12), StdHeader); + RwAlink ((FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29)), 0xFFFFFFFF, (BIT6 + BIT19), StdHeader); + RwAlink (FCH_RCINDXC_REG65, 0xFFFFFFFF, ((GppData32 & 0x0F) == 0x0F) ? GppData32 | 0x0CFF0000 : GppData32, StdHeader); + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieEnvService.c new file mode 100644 index 0000000..0b554da --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieEnvService.c @@ -0,0 +1,104 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Hudson2 Pcie controller + * + * Init Pcie Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIEENVSERVICE_FILECODE + + +/** + * ProgramPcieNativeMode - Config Pcie Native Mode + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +ProgramPcieNativeMode ( + IN VOID *FchDataPtr + ) +{ + UINT8 FchNativepciesupport; + FCH_DATA_BLOCK *LocalCfgPtr; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + FchNativepciesupport = (UINT8) LocalCfgPtr->Misc.NativePcieSupport; + + // + // PCIE Native setting + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBA + 1, AccessWidth8, (UINT32)~BIT14, 0); + if ( FchNativepciesupport == 1) { + RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0x74 + 3, AccessWidth8, (UINT32)~(BIT3 + BIT1 + BIT0), BIT3 + BIT2 + BIT0); + } else { + RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0x74 + 3, AccessWidth8, (UINT32)~(BIT3 + BIT1 + BIT0), BIT3 + BIT2); + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieService.c new file mode 100644 index 0000000..2d93377 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieService.c @@ -0,0 +1,73 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Hudson2 Pcie controller + * + * Init Pcie Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIESERVICE_FILECODE diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppEnv.c new file mode 100644 index 0000000..6f1f51d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppEnv.c @@ -0,0 +1,127 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Gpp controller + * + * Init Gpp Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Ids.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_PCIE_GPPENV_FILECODE + +VOID +FchInitEnvGppPhaseII ( + IN VOID *FchDataPtr + ); + +/** + * FchInitEnvGpp - Config Gpp controller before PCI emulation + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvGpp ( + IN VOID *FchDataPtr + ) +{ + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + if ( !LocalCfgPtr->Gpp.NewGppAlgorithm) { + ProgramFchGppInitReset (&LocalCfgPtr->Gpp, StdHeader); + FchStall (5000, StdHeader); + } + FchGppPortInit (&LocalCfgPtr->Gpp, StdHeader); +} + +/** + * FchInitEnvGppPhaseII - Config Gpp controller before PCI emulation (For New Algorithm) + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvGppPhaseII ( + IN VOID *FchDataPtr + ) +{ + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + if ( LocalCfgPtr->Gpp.NewGppAlgorithm == TRUE ) { + FchGppPortInitPhaseII (&LocalCfgPtr->Gpp, StdHeader); + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppHp.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppHp.c new file mode 100644 index 0000000..5a52f89 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppHp.c @@ -0,0 +1,220 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch GPP controller + * + * Init GPP features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Ids.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_PCIE_GPPHP_FILECODE + +VOID +FchGppHotplugSmiCallback ( + IN VOID *DataPtr + ); + +/** + * GPP hot plug handler + * + * + * @param[in] FchGpp Pointer to Fch GPP configuration structure + * @param[in] HpPort The hot plug port number + * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS + * + */ +STATIC VOID +FchGppHotPlugSmiProcess ( + IN FCH_GPP *FchGpp, + IN UINT32 HpPort, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 FailedPort; + UINT8 GppS3Data; + + GppS3Data = 0x00; + ReadMem ( ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D, AccessWidth8, &GppS3Data); + RwAlink (FCH_RCINDXC_REG40, (UINT32)~BIT3, 0, StdHeader); + + // + // First restore GPP pads if needed + // + if (FchGpp->GppDynamicPowerSaving && FchGpp->UmiPhyPllPowerDown && FchGpp->GppPhyPllPowerDown) { + RwAlink (0xC0 | (UINT32) (ABCFG << 29), ~(UINT32) (1 << (12 + HpPort)), 0, StdHeader); + RwAlink (FCH_RCINDXC_REG65, ~(UINT32) (0x101 << HpPort), 0, StdHeader); + FchStall (1000, StdHeader); + } + + FailedPort = (UINT8) (1 << HpPort); + if (FchGpp->GppGen2 && FchGpp->GppGen2Strap) { + GppS3Data &= (UINT8) !(1 << HpPort); + if (GppPortPollingLtssm (FchGpp, FailedPort, TRUE, StdHeader)) { + FchGppForceGen1 (FchGpp, FailedPort, StdHeader); + FailedPort = GppPortPollingLtssm (FchGpp, FailedPort, FALSE, StdHeader); + GppS3Data |= (UINT8) (1 << HpPort); + } + } else { + FchGppForceGen1 (FchGpp, FailedPort, StdHeader); + FailedPort = GppPortPollingLtssm (FchGpp, FailedPort, FALSE, StdHeader); + GppS3Data |= (UINT8) (1 << HpPort); + } + GppS3Data |= (UINT8) (1 << (HpPort + 4)); + RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D, AccessWidth8, 0, GppS3Data); + GppGen2Workaround (FchGpp, StdHeader); +} + + +/** + * GPP hot-unplug handler + * + * + * @param[in] FchGpp Pointer to Fch GPP configuration structure + * @param[in] HpPort The hot plug port number. + * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS + * + */ +STATIC VOID +FchGppHotUnplugSmiProcess ( + IN FCH_GPP *FchGpp, + IN UINT32 HpPort, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 GppS3Data; + + GppS3Data = 0x00; + ReadMem ( ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D, AccessWidth8, &GppS3Data); + FchGpp->PortCfg[HpPort].PortDetected = FALSE; + GppS3Data &= (UINT8) !(1 << (HpPort + 4)); + + if (FchGpp->GppGen2 && FchGpp->GppGen2Strap) { + FchGppForceGen2 (FchGpp, (UINT8) (1 << HpPort), StdHeader); + } + + if (FchGpp->GppDynamicPowerSaving && FchGpp->UmiPhyPllPowerDown && FchGpp->GppPhyPllPowerDown) { + RwAlink (FCH_RCINDXP_REGA2 | HpPort << 24, ~(UINT32) (BIT17), BIT17, StdHeader); + RwAlink (FCH_RCINDXP_REGA2 | HpPort << 24, ~(UINT32) (BIT8), BIT8, StdHeader); + RwAlink (0xC0 | (UINT32) (ABCFG << 29), ~(UINT32) (1 << (12 + HpPort)), (1 << (12 + HpPort)), StdHeader); + RwAlink (FCH_RCINDXP_REGA2 | HpPort << 24, ~(UINT32) (BIT17), 0, StdHeader); + + GppGen2Workaround (FchGpp, StdHeader); + + // Finally re-configure GPP pads if needed + FchGppDynamicPowerSaving (FchGpp, StdHeader); + } + RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D, AccessWidth8, 0, GppS3Data); +} + + +/** + * SMI handler for GPP hot-plug + * + * + * @param[in] DataPtr Fch configuration structure pointer. + * + */ +VOID +FchGppHotplugSmiCallback ( + IN VOID *DataPtr + ) +{ + UINT32 PortNum; + UINT32 HpPort; + FCH_DATA_BLOCK *FchDb; + UINT8 HpGeventNum; + UINT8 GpioPinState; + + FchDb = (FCH_DATA_BLOCK*) DataPtr; + if (!FchDb->Gpp.GppFunctionEnable) { + return; + } + + HpPort = 0xff; + for (PortNum = 0; PortNum < MAX_GPP_PORTS; PortNum++) { + if (FchDb->Gpp.PortCfg[PortNum].PortHotPlug == TRUE) { + HpPort = PortNum; + break; + } + } + + if (HpPort == 0xff) { + return; + } + + HpGeventNum = FchDb->Gpp.GppHotPlugGeventNum & 31; + GpioPinState = ACPIMMIO8 (ACPI_MMIO_BASE + GPIO_BASE + FCH_GEVENT_REG00 + HpGeventNum) >> 7; + if (!GpioPinState) { + AGESA_TESTPOINT (TpFchGppHotPlugging, FchDb->StdHeader); + FchGppHotPlugSmiProcess (&FchDb->Gpp, HpPort, FchDb->StdHeader); + } else { + AGESA_TESTPOINT (TpFchGppHotUnplugging, FchDb->StdHeader); + FchGppHotUnplugSmiProcess (&FchDb->Gpp, HpPort, FchDb->StdHeader); + } + + ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG98) ^= (1 << HpGeventNum); // Swap SmiTrig +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppLate.c new file mode 100644 index 0000000..bf10647 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppLate.c @@ -0,0 +1,313 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Gpp controller + * + * Init Gpp Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Ids.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_PCIE_GPPLATE_FILECODE + +// +// Declaration of local functions +// + + +/** + * FchGppSetAspm - Set GPP ASPM + * + * + * @param[in] PciAddress PCI Address. + * @param[in] LxState Lane State. + * @param[in] StdHeader + * + */ +STATIC VOID +FchGppSetAspm ( + IN UINT32 PciAddress, + IN UINT8 LxState, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 PcieCapOffset; + UINT8 DeviceType; + + PcieCapOffset = FchFindPciCap (PciAddress, PCIE_CAP_ID, StdHeader); + + if (PcieCapOffset) { + // + // Read link capabilities register (0x0C[11:10] - ASPM support) + // + ReadPci (PciAddress + PcieCapOffset + 0x0D, AccessWidth8, &DeviceType, StdHeader); + if (DeviceType & BIT2) { + DeviceType = (DeviceType >> 2) & (BIT1 + BIT0); + // + // Set ASPM state in link control register + // + RwPci (PciAddress + PcieCapOffset + 0x10, AccessWidth8, 0xffffffff, LxState & DeviceType, StdHeader); + } + } +} + +/** + * FchGppSetEpAspm - Set EP ASPM + * + * + * @param[in] PciAddress PCI Address. + * @param[in] LxState Lane State. + * @param[in] StdHeader + * + */ +STATIC VOID +FchGppSetEpAspm ( + IN UINT32 PciAddress, + IN UINT8 LxState, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 DeviceType; + UINT8 MaxFuncs; + UINT32 DevBDF; + + MaxFuncs = 1; + ReadPci (PciAddress + 0x0E, AccessWidth8, &DeviceType, StdHeader); + + if (DeviceType & BIT7) { + MaxFuncs = 8; /// multi-function device + } + + while (MaxFuncs != 0) { + DevBDF = PciAddress + (UINT32) ((MaxFuncs - 1) << 16); + FchGppSetAspm (DevBDF, LxState, StdHeader); + MaxFuncs--; + } +} + +/** + * FchGppValidateAspm - Validate EndPoint support for GPP ASPM + * + * + * @param[in] PciAddress PCI Address. + * @param[in] LxState Lane State. + * @param[in] StdHeader + * + */ +STATIC VOID +FchGppValidateAspm ( + IN UINT32 PciAddress, + IN UINT8 *LxState, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 PcieCapOffset; + UINT8 DeviceType; + UINT8 MaxFuncs; + UINT32 DevBDF; + + MaxFuncs = 1; + ReadPci (PciAddress + 0x0E, AccessWidth8, &DeviceType, StdHeader); + + if (DeviceType & BIT7) { + MaxFuncs = 8; /// multi-function device + } + + while (MaxFuncs != 0) { + DevBDF = PciAddress + (UINT32) ((MaxFuncs - 1) << 16); + PcieCapOffset = FchFindPciCap (DevBDF, PCIE_CAP_ID, StdHeader); + + if (PcieCapOffset) { + // + // Read link capabilities register (0x0C[11:10] - ASPM support) + // + ReadPci (DevBDF + PcieCapOffset + 0x0D, AccessWidth8, &DeviceType, StdHeader); + if (DeviceType & BIT2) { + DeviceType = (DeviceType >> 2) & (BIT1 + BIT0); + // + // Update ASPM state as what endpoint support + // + *LxState &= DeviceType; + } + } + MaxFuncs--; + } +} + + +/** + * FchInitLateGpp - Prepare Gpp controller to boot to OS. + * + * PcieGppLateInit + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitLateGpp ( + IN VOID *FchDataPtr + ) +{ + UINT8 PortId; + UINT8 BusNum; + UINT8 PortAspmValue; + UINT8 AllowStrapControlByAB; + UINT8 GppS3Data; + FCH_GPP_PORT_CONFIG *PortCfg; + UINT32 PciAspmValue; + UINT32 AbValue; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + // + // Disable hidden register decode and serial number capability + // + AbValue = ReadAlink (FCH_ABCFG_REG330 | (UINT32) (ABCFG << 29), StdHeader); + WriteAlink (FCH_ABCFG_REG330 | (UINT32) (ABCFG << 29), AbValue & ~(BIT26 + BIT10), StdHeader); + // + // Configure ASPM & Save GPP port status into CMOS + // + AllowStrapControlByAB = 0x01; + GppS3Data = 0x00; + + for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) { + // + // write pci_reg3d with 0x01 to fix yellow mark for GPP bridge under some OS + // when native PCIE is enabled but MSI is not available + // BIF/GPP allowing strap STRAP_BIF_INTERRUPT_PIN_SB controlled by AB reg + // + PortCfg = &LocalCfgPtr->Gpp.PortCfg[PortId]; + if (PortCfg->PortDetected) { + GppS3Data |= 1 << (PortId + 4); + if (PortCfg->PortIsGen2 == FALSE) { + GppS3Data |= 1 << (PortId); + } + } + if (PortCfg->PortHotPlug) { + RwPci (PCI_ADDRESS (0, 21, PortId, 0x04), AccessWidth8, 0xFE, 0x00, StdHeader); ///clear IO enable to fix possible hotplug hang + } + + WritePci (PCI_ADDRESS (0, 21, PortId, 0x3d), AccessWidth8, &AllowStrapControlByAB, StdHeader); + ReadPci (PCI_ADDRESS (0, 21, PortId, 0x19), AccessWidth8, &BusNum, StdHeader); + + if (BusNum != 0xFF) { + ReadPci (PCI_ADDRESS (BusNum, 0, 0, 0x00), AccessWidth32, &PciAspmValue, StdHeader); + if (PciAspmValue != 0xffffffff) { + PortAspmValue = LocalCfgPtr->Gpp.GppPortAspm; + // + // Validate ASPM support on EP side + // + FchGppValidateAspm (PCI_ADDRESS (BusNum, 0, 0, 0), &PortAspmValue, StdHeader); + // + // Set ASPM on EP side + // + FchGppSetEpAspm (PCI_ADDRESS (BusNum, 0, 0, 0), PortAspmValue, StdHeader); + // + // Set ASPM on port side + // + FchGppSetAspm (PCI_ADDRESS (0, 21, PortId, 0), PortAspmValue, StdHeader); + } + } + RwAlink ((FCH_RCINDXP_REG02 | (UINT32) (PortId << 24)), (UINT32)~BIT15, BIT15, StdHeader); + } + RwAlink (FCH_RCINDXC_REG02, (UINT32)~BIT0, BIT0, StdHeader); + + if ( LocalCfgPtr->Gpp.GppPhyPllPowerDown == TRUE ) { + // + // Power Saving Feature for GPP Lanes + // + // Set PCIE_P_CNTL in Alink PCIEIND space + // + AbValue = ReadAlink (FCH_RCINDXC_REG40, StdHeader); + AbValue |= BIT12 + BIT0; + AbValue &= ~(BIT9 + BIT4); + WriteAlink (FCH_RCINDXC_REG40, AbValue, StdHeader); + RwAlink (FCH_RCINDXC_REG02, (UINT32)~(BIT8 + BIT3), BIT8 + BIT3, StdHeader); + GppGen2Workaround (&LocalCfgPtr->Gpp, StdHeader); + } + + // + // Configure Lock HWInit registers + // + AbValue = ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader); + if (AbValue & 0xF0) { + AbValue = ReadAlink (FCH_RCINDXC_REG10, StdHeader); + WriteAlink (FCH_RCINDXC_REG10, AbValue | BIT0, StdHeader); /// Set HWINIT_WR_LOCK + } + + // + // Restore strap0 via override + // + if (LocalCfgPtr->Gpp.PcieAer) { + RwAlink (0x310 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT7, StdHeader); + RwAlink (FCH_RCINDXC_REGC0, 0xFFFFFFFF, BIT9, StdHeader); + } + RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D, AccessWidth8, 0, GppS3Data); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppLib.c new file mode 100644 index 0000000..0a20d0f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppLib.c @@ -0,0 +1,361 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Fch Gpp Library + * + * Gpp Library + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#include "FchDef.h" +#define FILECODE PROC_FCH_PCIE_GPPLIB_FILECODE + +/** + * FchGppForceGen2 - Set GPP to Gen2 + * + * + * @param[in] FchGpp Pointer to Fch GPP configuration structure + * @param[in] ActivePorts Activate Ports + * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS + * + */ +VOID +FchGppForceGen2 ( + IN FCH_GPP *FchGpp, + IN CONST UINT8 ActivePorts, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 PortId; + + for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) { + if (ActivePorts & (1 << PortId)) { + RwAlink (FCH_RCINDXP_REGA4 | PortId << 24, 0xFFFFFFFF, BIT29 + BIT0, StdHeader); + RwAlink ((FCH_ABCFG_REG340 + PortId * 4) | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT21, StdHeader); + RwAlink (FCH_RCINDXP_REGA2 | PortId << 24, (UINT32)~BIT13, 0, StdHeader); + RwAlink (FCH_RCINDXP_REGC0 | PortId << 24, (UINT32)~BIT15, 0, StdHeader); + RwPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x88), AccessWidth8, 0xf0, 0x02, StdHeader); + + (&FchGpp->PortCfg[PortId])->PortIsGen2 = TRUE; + } + } +} + +/** + * FchGppForceGen1 - Set GPP to Gen1 + * + * + * @param[in] FchGpp Pointer to Fch GPP configuration structure + * @param[in] ActivePorts Activate Ports + * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS + * + */ +VOID +FchGppForceGen1 ( + IN FCH_GPP *FchGpp, + IN CONST UINT8 ActivePorts, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 PortId; + + for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) { + if (ActivePorts & (1 << PortId) && FchGpp->GppHardwareDownGrade != PortId + 1) { + RwAlink ((FCH_ABCFG_REG340 + PortId * 4) | (UINT32) (ABCFG << 29), (UINT32)~BIT21, 0, StdHeader); + RwAlink (FCH_RCINDXP_REGA4 | PortId << 24, (UINT32)~BIT0, BIT29, StdHeader); + RwAlink (FCH_RCINDXP_REGA2 | PortId << 24, 0xFFFFFFFF, BIT13, StdHeader); + RwAlink (FCH_RCINDXP_REGC0 | PortId << 24, (UINT32)~BIT15, 0, StdHeader); + RwPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x88), AccessWidth8, 0xf0, 0x01, StdHeader); + + (&FchGpp->PortCfg[PortId])->PortIsGen2 = FALSE; + } + } +} + +/** + * GppPortPollingLtssm - Loop polling the LTSSM for each GPP port marked in PortMap + * + * + * @param[in] FchGpp Pointer to Fch GPP configuration structure + * @param[in] ActivePorts A bitmap of ports which should be polled + * @param[in] IsGen2 TRUE if the polling is in Gen2 mode + * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS + * + * @retval FailedPorts A bitmap of ports which failed to train + * + */ +UINT8 +GppPortPollingLtssm ( + IN FCH_GPP *FchGpp, + IN UINT8 ActivePorts, + IN BOOLEAN IsGen2, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 RetryCounter; + UINT8 PortId; + UINT8 FailedPorts; + UINT8 HotPlugPorts; + FCH_GPP_PORT_CONFIG *PortCfg; + UINT32 AbIndex; + UINT32 GppData32; + UINT8 EmptyPorts; + UINT8 Index; + UINT8 FixedPolling; + + FailedPorts = 0; + HotPlugPorts = 0; + RetryCounter = MAX_LT_POLLINGS; + EmptyPorts = ActivePorts; + FixedPolling = 200; + if ( FchGpp->NewGppAlgorithm == TRUE ) { + FixedPolling = FchGpp->GppPortMinPollingTime; + } + while (RetryCounter-- && ActivePorts) { + for (PortId = 0; PortId < MAX_GPP_PORTS; PortId++) { + if (ActivePorts & (1 << PortId)) { + PortCfg = &FchGpp->PortCfg[PortId]; + if ( PortCfg->PortHotPlug == TRUE ) { + HotPlugPorts |= ( 1 << PortId); + } + AbIndex = FCH_RCINDXP_REGA5 | (UINT32) (PortId << 24); + GppData32 = ReadAlink (AbIndex, StdHeader) & 0x3F3F3F3F; + + if ((UINT8) (GppData32) > 0x04) { + EmptyPorts &= ~(1 << PortId); + } + + if ((UINT8) (GppData32) == 0x10) { + ActivePorts &= ~(1 << PortId); + PortCfg->PortDetected = TRUE; + break; + } + + if (IsGen2) { + for (Index = 0; Index < 4; Index++) { + if ((UINT8) (GppData32) == 0x29 || (UINT8) (GppData32) == 0x2A ) { + ActivePorts &= ~(1 << PortId); + FailedPorts |= (1 << PortId); + break; + } + GppData32 >>= 8; + } + } + } + } + if (EmptyPorts && RetryCounter < (MAX_LT_POLLINGS - (UINT32) FixedPolling)) { + ActivePorts &= ~EmptyPorts; + } + FchStall (1000, StdHeader); + } + FchGpp->HotPlugPortsStatus = HotPlugPorts; + + FailedPorts |= ActivePorts; + return FailedPorts; +} + + +/** + * FchFindPciCap - Find PCI Cap + * + * + * @param[in] PciAddress PCI Address. + * @param[in] TargetCapId Target Cap ID. + * @param[in] StdHeader + * + */ +UINT8 +FchFindPciCap ( + IN UINT32 PciAddress, + IN UINT8 TargetCapId, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 NextCapPtr; + UINT8 CapId; + + NextCapPtr = 0x34; + while (NextCapPtr != 0) { + ReadPci (PciAddress + NextCapPtr, AccessWidth8, &NextCapPtr, StdHeader); + + if (NextCapPtr == 0xff) { + return 0; + } + + if (NextCapPtr != 0) { + ReadPci (PciAddress + NextCapPtr, AccessWidth8, &CapId, StdHeader); + if (CapId == TargetCapId) { + break; + } else { + NextCapPtr++; + } + } + } + return NextCapPtr; +} + +STATIC +BOOLEAN +IsDeviceGen2Capable ( + IN UINT32 pciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 pcieCapOffset; + UINT8 value8; + UINT16 value16; + + pcieCapOffset = FchFindPciCap (pciAddress, PCIE_CAP_ID, StdHeader); + if (pcieCapOffset) { + ReadPci (pciAddress + pcieCapOffset + 0x0C, AccessWidth8, &value8, StdHeader); + if (value8 & BIT1) { + return TRUE; + } else { + ReadPci (pciAddress, AccessWidth16, &value16, StdHeader); + if ((value16 == AMD_FCH_VID) || (value16 == ATI_VID)) { + return TRUE; + } + } + } + return FALSE; +} + + +/** + * + * 5/10/2011 - BIOS workaround for PLLPD hangup issue (applied for both POST and hotplug phases): + * + * if (GppPhyPllPowerDown == TRUE) { + * if (GppGen2 == TRUE && GppGen2Strap == TRUE) { + * if ((Any EP is GEN2 capable) || (Any EP is AMD/ATI GFX card)) { + * INDXC_REG40[3] = 0; + * } else { + * INDXC_REG40[3] = 1; + * } + * } else { + * INDXC_REG40[3] = 1; + * } + * } + * + * + * + * @param[in] FchGpp Pointer to Fch GPP configuration structure + * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS + * + */ +VOID +GppGen2Workaround ( + IN FCH_GPP *FchGpp, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 portId; + UINT8 busNum; + UINT32 reg32Value; + BOOLEAN DisablePllPdInL1; + + if (FchGpp->GppPhyPllPowerDown == TRUE) { + DisablePllPdInL1 = FALSE; + if (FchGpp->GppGen2 && FchGpp->GppGen2Strap) { + // Search all EP for max link speed capability + for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) { + ReadPci (PCI_ADDRESS (0, FCH_GPP_DEV, portId, 0x19), AccessWidth8, &busNum, StdHeader); + if (busNum != 0xFF) { + ReadPci (PCI_ADDRESS (busNum, 0, 0, 0x00), AccessWidth32, ®32Value, StdHeader); + if (reg32Value != 0xffffffff) { + DisablePllPdInL1 = IsDeviceGen2Capable (PCI_ADDRESS (busNum, 0, 0, 0), StdHeader); + if (DisablePllPdInL1 == TRUE) { + break; + } + } + } + } + } + + if (DisablePllPdInL1 == TRUE) { + RwAlink (FCH_RCINDXC_REG40, (UINT32)~BIT3, 0, StdHeader); + } else { + RwAlink (FCH_RCINDXC_REG40, (UINT32)~BIT3, BIT3, StdHeader); + } + } +} + +UINT32 +GppGetFchTempBus ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 FchTempBus; + UINT8 TempValue; + UINT64 MmioMsr; + + LibAmdMsrRead (0xC0010058, &MmioMsr, StdHeader); + TempValue = (UINT8) ((MmioMsr & 0x03C) >> 2); + FchTempBus = ( 0x01 << TempValue); + FchTempBus--; + FchTempBus--; + return ( FchTempBus); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppMid.c new file mode 100644 index 0000000..a32e9b5 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppMid.c @@ -0,0 +1,91 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Gpp controller + * + * Init Gpp Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_PCIE_GPPMID_FILECODE +// +// Declaration of local functions +// + +/** + * FchInitMidGpp - Config Gpp controller after PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidGpp ( + IN VOID *FchDataPtr + ) +{ +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppPortInit.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppPortInit.c new file mode 100644 index 0000000..e9b8056 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppPortInit.c @@ -0,0 +1,760 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config and Train Fch Gpp Ports + * + * Init Gpp Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Ids.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_PCIE_GPPPORTINIT_FILECODE + +// +// Declaration of local functions +// +/** + * GppPortPollingLtssmS3 - Loop polling the LTSSM for each GPP port marked in PortMap (New Algorithm S3) + * + * + * @param[in] FchGpp Pointer to Fch GPP configuration structure + * @param[in] ActivePorts A bitmap of ports which should be polled + * @param[in] IsGen2 TRUE if the polling is in Gen2 mode + * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS + * + * @retval FailedPorts A bitmap of ports which failed to train + * + */ +STATIC UINT8 +GppPortPollingLtssmS3 ( + IN FCH_GPP *FchGpp, + IN UINT8 ActivePorts, + IN BOOLEAN IsGen2, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 PortId; + UINT8 FailedPorts; + FCH_GPP_PORT_CONFIG *PortCfg; + UINT32 AbIndex; + UINT32 GppData32; + UINT8 EmptyPorts; + UINT8 RetryCounter; + + FailedPorts = 0; + EmptyPorts = ActivePorts; + RetryCounter = 2; + + while (RetryCounter-- ) { + for (PortId = 0; PortId < MAX_GPP_PORTS; PortId++) { + if (ActivePorts & (1 << PortId)) { + PortCfg = &FchGpp->PortCfg[PortId]; + if ( PortCfg->PortDetected == TRUE ) { + AbIndex = FCH_RCINDXP_REGA5 | (UINT32) (PortId << 24); + GppData32 = ReadAlink (AbIndex, StdHeader) & 0x3F3F3F3F; + + if ((UINT8) (GppData32) > 0x04) { + EmptyPorts &= ~(1 << PortId); + } + + if ((UINT8) (GppData32) == 0x10) { + break; + } + } + } + } + FchStall (180, StdHeader); + } + FailedPorts |= ActivePorts; + return FailedPorts; +} + +/** + * PreInitGppLink - Enable GPP link training. + * + * + * + * @param[in] FchGpp Pointer to Fch GPP configuration structure + * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS + * + */ +STATIC VOID +PreInitGppLink ( + IN FCH_GPP *FchGpp, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GPP_LINKMODE CfgMode; + UINT8 PortId; + UINT32 GppPortCfg; + UINT16 Tmp16Value; + UINT8 GppS3Data; + UINT8 HotPlugPorts; + + UINT8 PortMask[5] = { + 0x01, + 0x00, + 0x03, + 0x07, + 0x0F + }; + + HotPlugPorts = 0; + // + // PCIE_GPP_ENABLE (abcfg:0xC0): + // + // GPP_LINK_CONFIG ([3:0]) PortA PortB PortC PortD Description + // ---------------------------------------------------------------------------------- + // 0000 0-3 x4 Config + // 0001 N/A + // 0010 0-1 2-3 0 2:2 Config + // 0011 0-1 2 3 2:1:1 Config + // 0100 0 1 2 3 1:1:1:1 Config + // + // For A12 and above: + // ABCFG:0xC0[12] - Port A hold training (default 1) + // ABCFG:0xC0[13] - Port B hold training (default 1) + // ABCFG:0xC0[14] - Port C hold training (default 1) + // ABCFG:0xC0[15] - Port D hold training (default 1) + // + // + // + // Set port enable bit fields based on current GPP link configuration mode + // + CfgMode = FchGpp->GppLinkConfig; + ASSERT (CfgMode == PortA4 || CfgMode == PortA2B2 || CfgMode == PortA2B1C1 || CfgMode == PortA1B1C1D1); + GppPortCfg = (UINT32) PortMask[CfgMode]; + + // + // Mask out non-applicable ports according to the target link configuration mode + // + for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) { + FchGpp->PortCfg[PortId].PortPresent &= (UINT8 ) (GppPortCfg >> PortId) & BIT0; + if ( FchGpp->PortCfg[PortId].PortHotPlug == TRUE ) { + HotPlugPorts |= ( 1 << PortId); + } + } + + // + // Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0) + // + Tmp16Value = (UINT16) (~GppPortCfg << 12); + GppPortCfg = (UINT32) (Tmp16Value + (GppPortCfg << 4) + CfgMode); + WriteAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), GppPortCfg, StdHeader); + + GppPortCfg = ReadAlink (0xC0 | (UINT32) (RCINDXC << 29), StdHeader); + WriteAlink (0xC0 | (UINT32) (RCINDXC << 29), GppPortCfg | 0x400, StdHeader); /// Set STRAP_F0_MSI_EN + + // + // A-Link L1 Entry Delay Shortening + // AXINDP_Reg 0xA0[7:4] = 0x3 + // KR Does not need this portion of code. + RwAlink (FCH_AX_INDXP_REGA0, 0xFFFFFF0F, 0x30, StdHeader); + RwAlink (FCH_AX_INDXP_REGB1, 0xFFFFFFFF, BIT19, StdHeader); + RwAlink (FCH_AX_INDXP_REGB1, 0xFFFFFFFF, BIT28, StdHeader); + + // + // GPP L1 Entry Delay Shortening + // RCINDP_Reg 0xA0[7:4] = 0x1 Enter L1 sooner after ACK'ing PM request. + // This is done to reduce number of NAK received with L1 enabled. + // + for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) { + RwAlink (FCH_RCINDXP_REGA0 | PortId << 24, 0xFFFFFF0F, 0x10, StdHeader); + // Hard System Hang running MeatGrinder Test on multiple blocks + // GPP Error Reporting Configuration + RwAlink (FCH_RCINDXP_REG6A | PortId << 24, (UINT32)~(BIT1), 0, StdHeader); + } + + + if (ReadFchSleepType (StdHeader) == ACPI_SLPTYP_S3) { + + ReadMem ( ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D, AccessWidth8, &GppS3Data); + for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) { + if ( GppS3Data & (1 << (PortId + 4))) { + if ( GppS3Data & (1 << PortId)) { + FchGppForceGen1 (FchGpp, (1 << PortId), StdHeader); + } else { + FchGppForceGen2 (FchGpp, (1 << PortId), StdHeader); + } + } + } + } + // + // Obtain original Gen2 strap value (LC_GEN2_EN_STRAP) + // + FchGpp->GppGen2Strap = (UINT8) (ReadAlink (FCH_RCINDXP_REGA4 | 0 << 24, StdHeader) & BIT0); + FchGpp->HotPlugPortsStatus = HotPlugPorts; +} + + +/** + * CheckGppLinkStatus - loop polling the link status for each GPP port + * + * + * Return: ToggleStatus[3:0] = Port bitmap for those need to clear De-emphasis + * + * @param[in] FchGpp Pointer to Fch GPP configuration structure + * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS + * + */ +STATIC UINT8 +CheckGppLinkStatus ( + IN FCH_GPP *FchGpp, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 PortId; + UINT8 PortScanMap; + UINT8 GppHwDowngrade; + FCH_GPP_PORT_CONFIG *PortCfg; + UINT8 FailedPorts; + + PortScanMap = 0; + FailedPorts = 0; + + // + // Obtain a list of ports to be checked + // + for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) { + PortCfg = &FchGpp->PortCfg[PortId]; + if ( PortCfg->PortPresent == TRUE && PortCfg->PortDetected == FALSE ) { + PortScanMap |= 1 << PortId; + } + } + + GppHwDowngrade = (UINT8) FchGpp->GppHardwareDownGrade; + if (GppHwDowngrade != 0) { + // + // Skip polling and always assume this port to be present + // + PortScanMap &= ~(1 << (GppHwDowngrade - 1)); + } + + FchStall (5000, StdHeader); + if (FchGpp->GppGen2 && FchGpp->GppGen2Strap) { + AGESA_TESTPOINT (TpFchGppGen2PortPolling, StdHeader); + FchGppForceGen2 (FchGpp, PortScanMap, StdHeader); + FailedPorts = GppPortPollingLtssm (FchGpp, PortScanMap, TRUE, StdHeader); + + if (FailedPorts) { + AGESA_TESTPOINT (TpFchGppGen1PortPolling, StdHeader); + FchGppForceGen1 (FchGpp, FailedPorts, StdHeader); + FailedPorts = GppPortPollingLtssm (FchGpp, FailedPorts, FALSE, StdHeader); + } + } else { + AGESA_TESTPOINT (TpFchGppGen1PortPolling, StdHeader); + FchGppForceGen1 (FchGpp, PortScanMap, StdHeader); + FailedPorts = GppPortPollingLtssm (FchGpp, PortScanMap, FALSE, StdHeader); + } + return FailedPorts; +} + +STATIC +BOOLEAN +FoundInfiniteCrs ( + IN FCH_GPP *FchGpp, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 PortId; + UINT32 Value32; + UINT32 RegBusNo; + UINT32 FchTempBus; + FCH_GPP_PORT_CONFIG *PortCfg; + + FchTempBus = GppGetFchTempBus (StdHeader); + for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) { + PortCfg = &FchGpp->PortCfg[PortId]; + if ( PortCfg->PortDetected == TRUE ) { + RegBusNo = (FchTempBus << 16) + (FchTempBus << 8); + WritePci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x18), AccessWidth32, &RegBusNo, StdHeader); + ReadPci (PCI_ADDRESS (FchTempBus, 0, 0, 0x08), AccessWidth32, &Value32, StdHeader); + RegBusNo = 0; + WritePci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x18), AccessWidth32, &RegBusNo, StdHeader); + + if ( Value32 == 0xFFFFFFFF ) { + return TRUE; + } + } + } + return FALSE; +} + + +/** + * AfterGppLinkInit + * - Search for display device behind each GPP port + * - If the port is empty AND not hotplug-capable: + * * Turn off link training + * * (optional) Power down the port + * * Hide the configuration space (Turn off the port) + * + * @param[in] FchGpp Pointer to Fch GPP configuration structure + * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS + * + */ +STATIC VOID +AfterGppLinkInit ( + IN FCH_GPP *FchGpp, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 PortId; + FCH_GPP_PORT_CONFIG *PortCfg; + UINT32 RegBusNumber; + UINT32 FchTempBus; + UINT32 AbValue; + UINT32 AbIndex; + UINT8 Value; + + FchGpp->GppFoundGfxDev = 0; + AbValue = ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader); + // + // Link Bandwidth Notification Capability Enable + //RCINDC:0xC1[0] = 1 + // + RwAlink (FCH_RCINDXC_REGC1, 0xFFFFFFFF, BIT0, StdHeader); + + for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) { + // + // Program requester ID for every port + // + AbIndex = FCH_RCINDXP_REG21 | (UINT32) (PortId << 24); + WriteAlink (AbIndex, (FCH_GPP_DEV << 3) + PortId, StdHeader); + // + // Link Bandwidth Notification Capability Enable + //PCIe Cfg 0x68[10] = 0 + //PCIe Cfg 0x68[11] = 0 + // + RwPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x68), AccessWidth16, (UINT32)~(BIT10 + BIT11), 0, StdHeader); + + PortCfg = &FchGpp->PortCfg[PortId]; + // + // Check if there is GFX device behind each GPP port + // + FchTempBus = GppGetFchTempBus (StdHeader); + if ( PortCfg->PortDetected == TRUE ) { + RegBusNumber = (FchTempBus << 16) + (FchTempBus << 8); + WritePci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x18), AccessWidth32, &RegBusNumber, StdHeader); + ReadPci (PCI_ADDRESS (FchTempBus, 0, 0, 0x0B), AccessWidth8, &Value, StdHeader); + if ( Value == 3 ) { + FchGpp->GppFoundGfxDev |= (1 << PortId); + } + + RegBusNumber = 0; + WritePci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x18), AccessWidth32, &RegBusNumber, StdHeader); + } else if ( PortCfg->PortPresent == FALSE || PortCfg->PortHotPlug == FALSE ) { + // + // Mask off non-applicable ports + // + AbValue &= ~(1 << (PortId + 4)); + } + + if ( PortCfg->PortHotPlug == TRUE ) { + // + // Hot Plug: PCIe Native Support + // RCINDP_Reg 0x10[3] = 0x1 + // PCIe_Cfg 0x5A[8] = 0x1 + // PCIe_Cfg 0x6C[6] = 0x1 + // RCINDP_Reg 0x20[19] = 0x0 + // + RwAlink ((FCH_RCINDXP_REG10 | (UINT32) (PortId << 24)), 0xFFFFFFFF, BIT3, StdHeader); + RwPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x5b), AccessWidth8, 0xff, BIT0, StdHeader); + RwPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x6c), AccessWidth8, 0xff, BIT6, StdHeader); + RwAlink ((FCH_RCINDXP_REG20 | (UINT32) (PortId << 24)), (UINT32)~BIT19, 0, StdHeader); + } + } + + if ( FchGpp->GppUnhidePorts == FALSE ) { + if ((AbValue & 0xF0) == 0) { + //comment out the following line for BUG284426: GPP_RESET causes S3 resume hard hang on Pumori + //AbValue = BIT8; // if all ports are empty set GPP_RESET + } else if ((AbValue & 0xE0) != 0 && (AbValue & 0x10) == 0) { + AbValue |= BIT4; // PortA should always be visible whenever other ports are exist + } + + // + // Update GPP_Portx_Enable (abcfg:0xC0[7:5]) + // + WriteAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), AbValue, StdHeader); + } + + // + // Common initialization for open GPP ports + // + for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) { + ReadPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x80), AccessWidth8, &Value, StdHeader); + if (Value != 0xff) { + // + // Set pciCfg:PCIE_DEVICE_CNTL2[3:0] = 4'h6 (0x80[3:0]) + // + Value &= 0xf0; + Value |= 0x06; + WritePci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x80), AccessWidth8, &Value, StdHeader); + + // + // Set PCIEIND_P:PCIE_RX_CNTL[RX_RCB_CPL_TIMEOUT_MODE] (0x70:[19]) = 1 + // + AbIndex = FCH_RCINDXP_REG70 | (UINT32) (PortId << 24); + AbValue = ReadAlink (AbIndex, StdHeader) | BIT19; + WriteAlink (AbIndex, AbValue, StdHeader); + + // + // Set PCIEIND_P:PCIE_TX_CNTL[TX_FLUSH_TLP_DIS] (0x20:[19]) = 0 + // + AbIndex = FCH_RCINDXP_REG20 | (UINT32) (PortId << 24); + AbValue = ReadAlink (AbIndex, StdHeader) & ~BIT19; + WriteAlink (AbIndex, AbValue, StdHeader); + + // + // Set Immediate Ack PM_Active_State_Request_L1 (0xA0:[23]) = 1 + // + AbIndex = FCH_RCINDXP_REGA0 | (UINT32) (PortId << 24); + AbValue = ReadAlink (AbIndex, StdHeader) & ~BIT23; + if ( FchGpp->GppL1ImmediateAck == 0) { + AbValue |= BIT23; + } + WriteAlink (AbIndex, AbValue, StdHeader); + } + } +} + + +/** + * FchGppAerInitialization - Initializing AER + * + * + * @param[in] FchGpp Pointer to Fch GPP configuration structure + * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS + * + */ +STATIC VOID +FchGppAerInitialization ( + IN FCH_GPP *FchGpp, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + if (FchGpp->PcieAer) { + // + // GPP strap configuration + // + RwAlink (0x310 | (UINT32) (ABCFG << 29), (UINT32)~(BIT7 + BIT4), BIT28 + BIT27 + BIT26 + BIT1, StdHeader); + RwAlink (0x314 | (UINT32) (ABCFG << 29), ~(UINT32) (0xfff << 15), 0, StdHeader); + + // + // AB strap configuration + // + RwAlink (FCH_ABCFG_REGF0 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT15 + BIT14, StdHeader); + RwAlink (FCH_ABCFG_REGF4 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT3, StdHeader); + } else { + // + // Hard System Hang running MeatGrinder Test on multiple blocks + // GPP Error Reporting Configuration + RwAlink (FCH_ABCFG_REGF0 | (UINT32) (ABCFG << 29), (UINT32)~(BIT1), 0, StdHeader); + } + +} + +/** + * FchGppRasInitialization - Initializing RAS + * + * + * @param[in] FchGpp Pointer to Fch GPP configuration structure + * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS + * + */ +STATIC VOID +FchGppRasInitialization ( + IN FCH_GPP *FchGpp, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + if (FchGpp->PcieRas) { + RwAlink (FCH_ABCFG_REGF4 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT0, StdHeader); + } +} + + +/** + * FchGppPortInit - GPP port training and initialization + * + * + * @param[in] FchGpp Pointer to Fch GPP configuration structure + * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS + * + */ +VOID +FchGppPortInit ( + IN FCH_GPP *FchGpp, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + // + // GppEarlyInit + // + UINT32 AbValue; + UINT8 ResetCounter; + UINT8 FailPorts; + + AGESA_TESTPOINT (TpFchGppBeforePortTraining, StdHeader); + + // + // Configure NB-FCH link PCIE PHY PLL power down for L1 + // + if ( FchGpp->UmiPhyPllPowerDown == TRUE ) { + // + // Set PCIE_P_CNTL in Alink PCIEIND space + // + WriteAlink (FCH_AX_INDXC_REG30 | (UINT32) (AXINDC << 29), 0x40, StdHeader); + AbValue = ReadAlink (FCH_AX_DATAC_REG34 | (UINT32) (AXINDC << 29), StdHeader); + AbValue |= BIT12 + BIT3 + BIT0; + AbValue &= (UINT32)~(BIT9 + BIT4); + WriteAlink (FCH_AX_DATAC_REG34 | (UINT32) (AXINDC << 29), AbValue, StdHeader); + RwAlink (FCH_AX_INDXC_REG02 | (UINT32) (AXINDC << 29), (UINT32)~(BIT8), (BIT8), StdHeader); + RwAlink (FCH_AX_INDXC_REG02 | (UINT32) (AXINDC << 29), (UINT32)~(BIT3), (BIT3), StdHeader); + } + + // + // AXINDC_Reg 0xA4[18] = 0x1 + // + WriteAlink (FCH_AX_INDXP_REG38 | (UINT32) (AXINDP << 29), 0xA4, StdHeader); + AbValue = ReadAlink (FCH_AX_DATAP_REG3C | (UINT32) (AXINDP << 29), StdHeader); + AbValue |= BIT18; + WriteAlink (FCH_AX_DATAP_REG3C | (UINT32) (AXINDP << 29), AbValue, StdHeader); + + // + // Set ABCFG 0x031C[0] = 1 to enable lane reversal + // + AbValue = ReadAlink (FCH_ABCFG_REG31C | (UINT32) (ABCFG << 29), StdHeader); + if ( FchGpp->GppLaneReversal == TRUE ) { + WriteAlink (FCH_ABCFG_REG31C | (UINT32) (ABCFG << 29), AbValue | BIT0, StdHeader); + } else { + WriteAlink (FCH_ABCFG_REG31C | (UINT32) (ABCFG << 29), AbValue | 0x00, StdHeader); + } + + // + // Set abcfg:0x90[20] = 1 to enable GPP bridge multi-function + // + AbValue = ReadAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), StdHeader); + WriteAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), AbValue | BIT20, StdHeader); + + // + // Initialize and configure GPP + // + if (FchGpp->GppFunctionEnable) { + if (( FchGpp->NewGppAlgorithm == FALSE ) || ( (ReadFchSleepType (StdHeader) != ACPI_SLPTYP_S3) )) { + ProgramGppTogglePcieReset (FchGpp->GppToggleReset, StdHeader); + } + FchGppAerInitialization (FchGpp, StdHeader); + FchGppRasInitialization (FchGpp, StdHeader); + + // + // PreInit - Enable GPP link training + // + if (( FchGpp->NewGppAlgorithm == FALSE ) || ( (ReadFchSleepType (StdHeader) != ACPI_SLPTYP_S3) )) { + PreInitGppLink (FchGpp, StdHeader); + } + // + // GPP Upstream Memory Write Arbitration Enhancement ABCFG 0x54[26] = 1 + // GPP Memory Write Max Payload Improvement RCINDC_Reg 0x10[12:10] = 0x4 + // + if ( FchGpp->GppMemWrImprove == TRUE ) { + RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), (UINT32)~BIT26, (BIT26), StdHeader); + RwAlink (FCH_RCINDXC_REG10, (UINT32)~(BIT12 + BIT11 + BIT10), (BIT12), StdHeader); + } + + if ( FchGpp->NewGppAlgorithm == TRUE ) { + if (ReadFchSleepType (StdHeader) == ACPI_SLPTYP_S3) { + if ( FchGpp->HotPlugPortsStatus == 0 ) { + // S3 Procedure + FchStall (5000, StdHeader); + FailPorts = FchGpp->FailPortsStatus; + if ( FchGpp->FailPortsStatus != 0 ) { + AGESA_TESTPOINT (TpFchGppGen1PortPolling, StdHeader); + FchGppForceGen1 (FchGpp, FailPorts, StdHeader); + } + } + } + } else { + ResetCounter = 3; + while (ResetCounter--) { + FailPorts = CheckGppLinkStatus (FchGpp, StdHeader); + if (FoundInfiniteCrs (FchGpp, StdHeader)) { + ProgramGppTogglePcieReset (TRUE, StdHeader); + } else if ((FailPorts != 0) && (ReadFchSleepType (StdHeader) != ACPI_SLPTYP_S3)) { + ProgramGppTogglePcieReset (FchGpp->GppToggleReset, StdHeader); + } else { + break; + } + } + } + + // + // Misc operations after link training + // + if ( FchGpp->NewGppAlgorithm == FALSE ) { + AfterGppLinkInit (FchGpp, StdHeader); + } + } + if ( FchGpp->NewGppAlgorithm == FALSE ) { + FchGppDynamicPowerSaving (FchGpp, StdHeader); + AGESA_TESTPOINT (TpFchGppAfterPortTraining, StdHeader); + } +} + +/** + * FchGppPortInitS3Phase - GPP port training and initialization S3 phase for new algorithm + * + * + * @param[in] FchGpp Pointer to Fch GPP configuration structure + * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS + * + */ +VOID +FchGppPortInitS3Phase ( + IN FCH_GPP *FchGpp, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 ResetCounter; + UINT8 FailPorts; + + if (FchGpp->GppFunctionEnable) { + ProgramGppTogglePcieReset (FchGpp->GppToggleReset, StdHeader); + PreInitGppLink (FchGpp, StdHeader); + // For S3 With HotPlug port setting. + if ( FchGpp->HotPlugPortsStatus != 0 ) { + ResetCounter = 3; + while (ResetCounter--) { + FailPorts = CheckGppLinkStatus (FchGpp, StdHeader); + if (FoundInfiniteCrs (FchGpp, StdHeader)) { + ProgramGppTogglePcieReset (TRUE, StdHeader); + } else if (FailPorts != 0) { + ProgramGppTogglePcieReset (FchGpp->GppToggleReset, StdHeader); + } else { + break; + } + } + AfterGppLinkInit (FchGpp, StdHeader); + } + } +} + +/** + * FchGppPortInitPhaseII - GPP port training and initialization phase II for new algorithm + * + * + * @param[in] FchGpp Pointer to Fch GPP configuration structure + * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS + * + */ +VOID +FchGppPortInitPhaseII ( + IN FCH_GPP *FchGpp, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 ResetCounter; + UINT8 FailPorts; + UINT8 HotPlugPorts; + + if (FchGpp->GppFunctionEnable) { + // + // Check Link status for the new algorithm + // + HotPlugPorts = 0; + FailPorts = 0; + // + // Read previously HotPlug port status + // + if ( ReadFchSleepType (StdHeader) == ACPI_SLPTYP_S3) { + if ( FchGpp->HotPlugPortsStatus == 0 ) { + FailPorts = FchGpp->FailPortsStatus; + FailPorts = GppPortPollingLtssmS3 (FchGpp, FailPorts, FALSE, StdHeader); + AfterGppLinkInit (FchGpp, StdHeader); + } + } else { + ResetCounter = 3; + while (ResetCounter--) { + FailPorts = CheckGppLinkStatus (FchGpp, StdHeader); + if (FoundInfiniteCrs (FchGpp, StdHeader)) { + ProgramGppTogglePcieReset (TRUE, StdHeader); + } else if ((FailPorts != 0) && (ReadFchSleepType (StdHeader) != ACPI_SLPTYP_S3)) { + // CMOS record need + FchGpp->FailPortsStatus = FailPorts; + ProgramGppTogglePcieReset (FchGpp->GppToggleReset, StdHeader); + } else { + // CMOS clear need + FchGpp->FailPortsStatus = FailPorts; + break; + } + } + AfterGppLinkInit (FchGpp, StdHeader); + } + } + FchGppDynamicPowerSaving (FchGpp, StdHeader); + AGESA_TESTPOINT (TpFchGppAfterPortTraining, StdHeader); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppReset.c new file mode 100644 index 0000000..b12d2c5 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppReset.c @@ -0,0 +1,126 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Gpp controller + * + * Init Gpp features (PEI phase). + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_PCIE_GPPRESET_FILECODE + + +// +//----------------------------------------------------------------------------------- +// Early GPP initialization sequence: +// +// 1) Set port enable bit fields by current GPP link configuration mode +// 2) Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0) +// 3) Loop polling for the link status of all ports +// 4) Misc operations after link training: +// - (optional) Detect GFX device +// - Hide empty GPP configuration spaces (Disable empty GPP ports) +// - (optional) Power down unused GPP ports +// - (optional) Configure PCIE_P2P_Int_Map (abcfg:0xC4[7:0]) +// 5) GPP init completed +// +// +// *) Gen2 vs Gen1 +// Gen2 mode Gen1 mode +// --------------------------------------------------------------- +// STRAP_PHY_PLL_CLKF[6:0] 7'h32 7'h19 +// STRAP_BIF_GEN2_EN 1 0 +// +// PCIE_PHY_PLL clock locks @ 5GHz +// +// + +/** + * FchInitResetGpp - Config Gpp during Power-On + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitResetGpp ( + IN VOID *FchDataPtr + ) +{ + FCH_RESET_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + if ( LocalCfgPtr->Gpp.NewGppAlgorithm == TRUE ) { + if (ReadFchSleepType (StdHeader) == ACPI_SLPTYP_S3) { + FchGppPortInitS3Phase (&LocalCfgPtr->Gpp, StdHeader); + } + } +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieEnv.c new file mode 100644 index 0000000..c68064c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieEnv.c @@ -0,0 +1,94 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Pcie controller + * + * Init Pcie Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#include "FchDef.h" +#define FILECODE PROC_FCH_PCIE_PCIEENV_FILECODE + +/** + * FchInitEnvPcie - Config Pcie before PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvPcie ( + IN VOID *FchDataPtr + ) +{ + // + // PCIE Native setting + // + ProgramPcieNativeMode (FchDataPtr); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieLate.c new file mode 100644 index 0000000..f580710 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieLate.c @@ -0,0 +1,88 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Pcie controller + * + * Init Pcie Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_PCIE_PCIELATE_FILECODE + +/** + * FchInitLatePcie - Prepare Pcie to boot to OS. + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitLatePcie ( + IN VOID *FchDataPtr + ) +{ +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieMid.c new file mode 100644 index 0000000..1474301 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieMid.c @@ -0,0 +1,88 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Pcie controller + * + * Init Pcie Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_PCIE_PCIEMID_FILECODE + +/** + * FchInitMidPcie - Config Pcie after PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidPcie ( + IN VOID *FchDataPtr + ) +{ +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieReset.c new file mode 100644 index 0000000..ae79e2e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/PcieReset.c @@ -0,0 +1,90 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Pcie Component + * + * Init Pcie features (PEI phase). + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_PCIE_PCIERESET_FILECODE + +/** + * FchInitResetPcie - Config Pcie controller during Power-On + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitResetPcie ( + IN VOID *FchDataPtr + ) +{ +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/AhciEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/AhciEnv.c new file mode 100644 index 0000000..e4b4d51 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/AhciEnv.c @@ -0,0 +1,113 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch SATA controller (AHCI mode) + * + * Init SATA AHCI features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SATA_AHCIENV_FILECODE + +/** + * FchInitEnvSataAhci - Config SATA Ahci controller before PCI + * emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvSataAhci ( + IN VOID *FchDataPtr + ) +{ + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + // + // Class code + // + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x08), AccessWidth32, 0, 0x01060140, StdHeader); + // + // Device ID + // + if ( LocalCfgPtr->Sata.SataClass == SataAhci7804 ) { + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x02), AccessWidth16, 0, FCH_SATA_AMDAHCI_DID, StdHeader); + } else { + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x02), AccessWidth16, 0, FCH_SATA_AHCI_DID, StdHeader); + } + // + // SSID + // + if (LocalCfgPtr->Sata.SataAhciSsid != 0 ) { + RwPci ((SATA_BUS_DEV_FUN << 16) + 0x2C, AccessWidth32, 0x00, LocalCfgPtr->Sata.SataAhciSsid, StdHeader); + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/AhciLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/AhciLate.c new file mode 100644 index 0000000..9eb22d1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/AhciLate.c @@ -0,0 +1,94 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch SATA controller (AHCI mode) + * + * Init SATA AHCI features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SATA_AHCILATE_FILECODE + +/** + * FchInitLateSataAhci - Prepare SATA AHCI controller to boot to + * OS. + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitLateSataAhci ( + IN VOID *FchDataPtr + ) +{ + UINT32 Bar5; + FCH_DATA_BLOCK *LocalCfgPtr; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + SataBar5setting (LocalCfgPtr, &Bar5); + ShutdownUnconnectedSataPortClock (LocalCfgPtr, Bar5); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/AhciLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/AhciLib.c new file mode 100644 index 0000000..625c803 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/AhciLib.c @@ -0,0 +1,95 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Fch SATA AHCI controller Library + * + * SATA AHCI Library + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SATA_AHCILIB_FILECODE + +/** + * sataAhciSetDeviceNumMsi - Program AHCI controller support + * device number cap & MSI cap + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +SataAhciSetDeviceNumMsi ( + IN VOID *FchDataPtr + ) +{ + + FCH_INTERFACE *LocalCfgPtr; + + LocalCfgPtr = (FCH_INTERFACE *)FchDataPtr; + + SataSetDeviceNumMsi (LocalCfgPtr); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/AhciMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/AhciMid.c new file mode 100644 index 0000000..a7ed24d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/AhciMid.c @@ -0,0 +1,94 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch SATA controller (AHCI mode) + * + * Init SATA AHCI features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SATA_AHCIMID_FILECODE + +/** + * FchInitMidSataAhci - Config SATA Ahci controller after PCI + * emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidSataAhci ( + IN VOID *FchDataPtr + ) +{ + FCH_DATA_BLOCK *LocalCfgPtr; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + SataAhciSetDeviceNumMsi (LocalCfgPtr); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c new file mode 100644 index 0000000..a90771f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c @@ -0,0 +1,307 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Graphics Controller family specific service procedure + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63460 $ @e $Date: 2011-12-22 19:04:22 -0600 (Thu, 22 Dec 2011) $ + * + */ + +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +*/ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATAENVSERVICE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +// +// Local Routine +// +VOID FchSataCombineControlDataByte (IN UINT8 *ControlReg); +VOID FchSataCombineControlDataWord (IN UINT16 *ControlReg); + +SATA_PHY_SETTING SataPhyTable[] = +{ + //Gen3 + {0x0030, 0x0057A607}, + {0x0031, 0x0057A607}, + {0x0032, 0x0057A407}, + {0x0033, 0x0057A407}, + {0x0034, 0x0057A607}, + {0x0035, 0x0057A607}, + {0x0036, 0x0057A403}, + {0x0037, 0x0057A403}, + + //Gen2 + {0x0120, 0x00071302}, + + //Gen1 + {0x0110, 0x00174101} +}; + +/** + * FchInitEnvProgramSataPciRegs - Sata Pci Configuration Space + * register setting + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvProgramSataPciRegs ( + IN VOID *FchDataPtr + ) +{ + UINT8 *PortRegByte; + UINT16 *PortRegWord; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + // + // Caculate SataPortReg for SATA_ESP_PORT + // + PortRegByte = &(LocalCfgPtr->Sata.SataEspPort.SataPortReg); + FchSataCombineControlDataByte (PortRegByte); + PortRegByte = &(LocalCfgPtr->Sata.SataPortPower.SataPortReg); + FchSataCombineControlDataByte (PortRegByte); + PortRegWord = &(LocalCfgPtr->Sata.SataPortMd.SataPortMode); + FchSataCombineControlDataWord (PortRegWord); + PortRegByte = &(LocalCfgPtr->Sata.SataHotRemovalEnhPort.SataPortReg); + FchSataCombineControlDataByte (PortRegByte); + + // + // Set Sata PCI Configuration Space Write enable + // + SataEnableWriteAccess (StdHeader); + + // + // Enables the SATA watchdog timer register prior to the SATA BIOS post + // + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x44), AccessWidth8, 0xff, BIT0, StdHeader); + + // + // SATA PCI Watchdog timer setting + // Set timer out to 0x20 to fix IDE to SATA Bridge dropping drive issue. + // + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x44 + 2), AccessWidth8, 0, 0x20, StdHeader); + + // + // BIT4:disable fast boot + // + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x040 ), AccessWidth8, 0xff, BIT4, StdHeader); + + // + // Enable IDE DMA read enhancement + // + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x48 + 3), AccessWidth8, 0xff, BIT7, StdHeader); + + // + // Unused SATA Ports Disabled + // + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x040 + 2), AccessWidth8, 0, LocalCfgPtr->Sata.SataPortPower.SataPortReg, StdHeader); + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x48), AccessWidth32, (UINT32) (~ (0x01 << 11)), (UINT32) (0x01 << 11), StdHeader); + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x084 ), AccessWidth32, (UINT32) (~ (0x01 << 31)), (UINT32) (0x00 << 31), StdHeader); + //RPR 9.22 Design Enhancement + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04C ), AccessWidth32, (UINT32) (~ (0x1 << 18)), (UINT32) (0x1 << 18), StdHeader); + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04C ), AccessWidth32, (UINT32) (~ (0x1 << 20)), (UINT32) (0x1 << 20), StdHeader); + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04C ), AccessWidth32, (UINT32) (~ (0x1 << 21)), (UINT32) (0x1 << 21), StdHeader); + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04C ), AccessWidth32, (UINT32) (~ (0x7 << 26)), (UINT32) (0x7 << 26), StdHeader); + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04C ), AccessWidth32, (UINT32) (~ (0x3 << 30)), (UINT32) (0x3 << 30), StdHeader); + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x48), AccessWidth32, (UINT32) (~ (0x1 << 30)), (UINT32) (0x1 << 30), StdHeader); + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04C ), AccessWidth32, (UINT32) (~ (0x1 << 29)), (UINT32) (0x1 << 29), StdHeader); +} + +/** + * FchSataCombineControlDataByte - Combine port control options + * to one control byte. + * + * + * @param[in] *ControlReg - Data pointer for control byte. + * + */ +VOID +FchSataCombineControlDataByte ( + IN UINT8 *ControlReg + ) +{ + UINT8 Index; + UINT8 PortControl; + + *ControlReg = 0; + for ( Index = 0; Index < 8; Index++ ) { + PortControl = *( ControlReg + 1 + Index ); + *ControlReg |= PortControl << Index; + } +} +/** + * FchSataCombineControlDataWord - Combine port control options + * to one control Word. + * + * + * @param[in] *ControlReg - Data pointer for control byte. + * + */ +VOID +FchSataCombineControlDataWord ( + IN UINT16 *ControlReg + ) +{ + UINT8 Index; + UINT8 PortControl; + + *ControlReg = 0; + for ( Index = 0; Index < 8; Index++ ) { + PortControl = *( (UINT8 *)ControlReg + 2 + Index ); + *ControlReg |= PortControl << (Index * 2); + } +} + + +VOID +FchProgramSataPhy ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + SATA_PHY_SETTING *PhyTablePtr; + UINT16 Index; + + PhyTablePtr = &SataPhyTable[0]; + + for (Index = 0; Index < (sizeof (SataPhyTable) / sizeof (SATA_PHY_SETTING)); Index++) { + RwPci ((SATA_BUS_DEV_FUN << 16) + 0x80, AccessWidth16, 0x00, PhyTablePtr->PhyCoreControlWord, StdHeader); + RwPci ((SATA_BUS_DEV_FUN << 16) + 0x98, AccessWidth32, 0x00, PhyTablePtr->PhyFineTuneDword, StdHeader); + ++PhyTablePtr; + } + + + RwPci ((SATA_BUS_DEV_FUN << 16) + 0x80, AccessWidth16, 0x00, 0x110, StdHeader); + RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C , AccessWidth32, (UINT32) (~(0x7 << 4)), (UINT32) (0x2 << 4), StdHeader); + RwPci ((SATA_BUS_DEV_FUN << 16) + 0x80, AccessWidth16, 0x00, 0x10, StdHeader); +} + +/** + * FchInitEnvSataRaidProgram - Configuration SATA Raid + * controller + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvSataRaidProgram ( + IN VOID *FchDataPtr + ) +{ + UINT32 SataSSIDValue; + UINT32 DeviceId; + UINT8 EfuseValue; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + // + // Class code + // + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x08), AccessWidth32, 0, 0x01040040, StdHeader); + // + // Device ID + // + SataSSIDValue = 0; + if (LocalCfgPtr->Sata.SataRaid5Ssid != 0 ) { + SataSSIDValue = LocalCfgPtr->Sata.SataRaid5Ssid; + } + + DeviceId = FCH_SATA_RAID5_DID; + EfuseValue = SATA_EFUSE_LOCATION; + GetEfuseStatus (&EfuseValue, StdHeader); + + if (( EfuseValue & SATA_EFUSE_BIT ) || ( LocalCfgPtr->Sata.SataForceRaid == 1 )) { + DeviceId = FCH_SATA_RAID_DID; + if (LocalCfgPtr->Sata.SataRaidSsid != 0 ) { + SataSSIDValue = LocalCfgPtr->Sata.SataRaidSsid; + } + } + + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x02), AccessWidth16, 0, DeviceId, StdHeader); + // + // SSID + // + if (SataSSIDValue != 0 ) { + RwPci ((SATA_BUS_DEV_FUN << 16) + 0x2C, AccessWidth32, 0, SataSSIDValue, StdHeader); + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataResetService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataResetService.c new file mode 100644 index 0000000..be32489 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataResetService.c @@ -0,0 +1,166 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Sata controller + * + * Init Sata Controller features (PEI phase). + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATARESETSERVICE_FILECODE + +/** + * FchInitResetSataProgram - Config Sata controller during + * Power-On + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitResetSataProgram ( + IN VOID *FchDataPtr + ) +{ + UINT8 SataPortNum; + UINT8 PortStatusByte; + UINT8 EfuseByte; + UINT8 FchSataMode; + UINT8 FchSataInternal100Spread; + FCH_RESET_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + // + //FchSataMode = LocalCfgPtr->Sata.SATA_MODE.SataMode.SataModeReg; + //New structure need calculate Sata Register value + // + FchSataMode = 0; + if ( LocalCfgPtr->FchReset.SataEnable ) { + FchSataMode |= 0x01; + } + if ( LocalCfgPtr->Sata6AhciCap ) { + FchSataMode |= 0x02; + } + if ( LocalCfgPtr->SataSetMaxGen2 ) { + FchSataMode |= 0x04; + } + if ( LocalCfgPtr->FchReset.IdeEnable ) { + FchSataMode |= 0x08; + } + + FchSataMode |= (( LocalCfgPtr->SataClkMode ) << 4 ) ; + LocalCfgPtr->SataModeReg = FchSataMode; ///Save Back to Structure + + FchSataInternal100Spread = ( UINT8 ) LocalCfgPtr->SataInternal100Spread; + SataPortNum = 0; + + // + // Sata Workaround + // + for ( SataPortNum = 0; SataPortNum < 0x08; SataPortNum++ ) { + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x040 + 2), AccessWidth8, 0xFF, 1 << SataPortNum, StdHeader); + FchStall (2, StdHeader); + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x040 + 2), AccessWidth8, (0xFF ^ (1 << SataPortNum)) , 0x00, StdHeader); + FchStall (2, StdHeader); + } + + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x084 + 3), AccessWidth8, (UINT32)~BIT2, 0, StdHeader); + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x0A0 ), AccessWidth8, (UINT32)~(BIT2 + BIT3 + BIT4 + BIT5 + BIT6), BIT2 + BIT3 + BIT4 + BIT5, StdHeader); + + // + // Sata Setting for clock mode only + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xDA , AccessWidth8, 0, FchSataMode); + + if ( FchSataInternal100Spread ) { + RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x1E, AccessWidth8, 0xFF, BIT4); + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x084 ), AccessWidth32, 0xFFFFFFFB, 0x00, StdHeader); + } else { + RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x1E, AccessWidth8, (UINT32)~BIT4, 0x00); + } + + EfuseByte = SATA_FIS_BASE_EFUSE_LOC; + GetEfuseStatus (&EfuseByte, StdHeader); + + if (EfuseByte & BIT0) { + RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xDA , AccessWidth8, 0xFB, 0x04); + } + + ReadMem (ACPI_MMIO_BASE + PMIO_BASE + 0xDA , AccessWidth8, &PortStatusByte); + if ( ((PortStatusByte & 0xF0) == 0x10) ) { + RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_PMIOA_REG08, AccessWidth8, 0, BIT5); + } + + if ( FchSataInternal100Spread ) { + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x084 ), AccessWidth32, 0xFFFFFFFF, 0x04, StdHeader); + } +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c new file mode 100644 index 0000000..d3eb263 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c @@ -0,0 +1,711 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Graphics Controller family specific service procedure + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ + +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +*/ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATASERVICE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +UINT8 NumOfSataPorts = 8; + +/** + * FchSataGpioInitial - Sata GPIO function Procedure + * + * - Private function + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchSataGpioInitial ( + IN VOID *FchDataPtr + ) +{ + UINT32 Bar5; + UINT32 FchSataBarRegDword; + UINT32 EMb; + UINT32 SataGpioVariableDword; + UINT8 FchSataSgpio0; + FCH_DATA_BLOCK *LocalCfgPtr; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + + Bar5 = 0; + EMb = 0; + FchSataSgpio0 = (UINT8) LocalCfgPtr->Sata.SataSgpio0; + + SataBar5setting (LocalCfgPtr, &Bar5); + ReadMem (Bar5 + 0x1C , AccessWidth32, &FchSataBarRegDword); + EMb = (Bar5 + (( FchSataBarRegDword & 0xFFFF0000) >> 14)); + + if ( EMb ) { + SataGpioVariableDword = 0x03040C00; + WriteMem ( Bar5 + EMb, AccessWidth32, &SataGpioVariableDword); + SataGpioVariableDword = 0x00C08240; + WriteMem ( Bar5 + EMb + 4, AccessWidth32, &SataGpioVariableDword); + SataGpioVariableDword = 0x00000001; + WriteMem ( Bar5 + EMb + 8, AccessWidth32, &SataGpioVariableDword); + + if ( FchSataSgpio0 ) { + SataGpioVariableDword = 0x00000060; + } else { + SataGpioVariableDword = 0x00000061; + } + + WriteMem ( Bar5 + EMb + 0x0C, AccessWidth32, &SataGpioVariableDword); + RwMem ((Bar5 + 0x20), AccessWidth16, (UINT32)~(BIT8), BIT8); + + do { + ReadMem (Bar5 + 0x20 , AccessWidth32, &FchSataBarRegDword); + FchSataBarRegDword = FchSataBarRegDword & BIT8; + } while ( FchSataBarRegDword != 0 ); + + SataGpioVariableDword = 0x03040F00; + WriteMem ( Bar5 + EMb, AccessWidth32, &SataGpioVariableDword); + SataGpioVariableDword = 0x00008240; + WriteMem ( Bar5 + EMb + 4, AccessWidth32, &SataGpioVariableDword); + SataGpioVariableDword = 0x00000002; + WriteMem ( Bar5 + EMb + 8, AccessWidth32, &SataGpioVariableDword); + SataGpioVariableDword = 0x00800000; + WriteMem ( Bar5 + EMb + 0x0C, AccessWidth32, &SataGpioVariableDword); + SataGpioVariableDword = 0x0F003700; + WriteMem ( Bar5 + EMb + 0x0C, AccessWidth32, &SataGpioVariableDword); + RwMem ((Bar5 + 0x20), AccessWidth16, (UINT32)~(BIT8), BIT8); + + do { + ReadMem (Bar5 + 0x20 , AccessWidth32, &FchSataBarRegDword); + FchSataBarRegDword = FchSataBarRegDword & BIT8; + } while ( FchSataBarRegDword != 0 ); + } +} + +/** + * FchInitMidProgramSataRegs - Sata Pci Configuration Space + * register setting + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidProgramSataRegs ( + IN VOID *FchDataPtr + ) +{ + UINT8 FchSataMsiCapability; + UINT8 FchSataTargetSupport8Device; + UINT8 FchSataDisableGenericMode; + UINT8 FchSataSgpio0; + UINT8 FchSataSgpio1; + UINT8 FchSataPhyPllShutDown; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + FchSataMsiCapability = (UINT8) LocalCfgPtr->Sata.SataMsiCapability; + FchSataTargetSupport8Device = (UINT8) LocalCfgPtr->Sata.SataTargetSupport8Device; + FchSataDisableGenericMode = (UINT8) LocalCfgPtr->Sata.SataDisableGenericMode; + FchSataSgpio0 = (UINT8) LocalCfgPtr->Sata.SataSgpio0; + FchSataSgpio1 = (UINT8) LocalCfgPtr->Sata.SataSgpio1; + FchSataPhyPllShutDown = (UINT8) LocalCfgPtr->Sata.SataPhyPllShutDown; + + if ((LocalCfgPtr->Sata.SataClass == SataNativeIde) || (LocalCfgPtr->Sata.SataClass == SataLegacyIde)) { + FchSataMsiCapability = 0; + } + // + // Enabled SATA MSI capability + // SATA MSI and D3 Power State Capability + // + if ( FchSataMsiCapability ) { + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x34), AccessWidth8, 0, 0x50, StdHeader); + } else { + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x34), AccessWidth8, 0, 0x70, StdHeader); + } + + // + // Disable SATA FLR Capability + // + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x70), AccessWidth16, 0x00FF, 0x00, StdHeader); + + // + // Sata Target Support 8 devices function + // + if ( FchSataTargetSupport8Device ) { + RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xDA , AccessWidth16, (UINT32)~BIT12, BIT12); + } else { + RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xDA , AccessWidth16, (UINT32)~BIT12, 0x00); + } + + // + // Sata Generic Mode setting + // + if ( FchSataDisableGenericMode ) { + RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xDA , AccessWidth16, (UINT32)~BIT13, BIT13); + } else { + RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xDA , AccessWidth16, (UINT32)~BIT13, 0x00); + } + + // + // Sata GPIO Initial + // + if ( FchSataSgpio0 ) { + FchSataGpioInitial ( LocalCfgPtr ); + } + + if ( FchSataSgpio1 ) { + FchSataGpioInitial ( LocalCfgPtr ); + } + + // + // Sata Phy Pll Shutdown setting + // + if ( FchSataPhyPllShutDown ) { + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x87), AccessWidth8, (UINT32)~(BIT6), BIT6, StdHeader); + } else { + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x87), AccessWidth8, (UINT32)~(BIT6), 0x00, StdHeader); + } + + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04C ), AccessWidth32, (UINT32) (~ (0x3f << 26)), (UINT32) (0x3f << 26), StdHeader); + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x48), AccessWidth32, (UINT32) (~ (0x01 << 11)), (UINT32) (0x01 << 11), StdHeader); + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x084 ), AccessWidth32, (UINT32) (~ (0x01 << 31)), (UINT32) (0x00 << 31), StdHeader); +} + + +/** + * FchInitLateProgramSataRegs - Sata Pci Configuration Space + * register setting + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitLateProgramSataRegs ( + IN VOID *FchDataPtr + ) +{ + UINT8 PortNumByte; + UINT32 Bar5; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + SataBar5setting (LocalCfgPtr, &Bar5); + // + //Clear error status + // + RwMem ((Bar5 + FCH_SATA_BAR5_REG130), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF); + RwMem ((Bar5 + FCH_SATA_BAR5_REG1B0), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF); + RwMem ((Bar5 + FCH_SATA_BAR5_REG230), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF); + RwMem ((Bar5 + FCH_SATA_BAR5_REG2B0), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF); + RwMem ((Bar5 + FCH_SATA_BAR5_REG330), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF); + RwMem ((Bar5 + FCH_SATA_BAR5_REG3B0), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF); + RwMem ((Bar5 + 0x0430 ), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF); + RwMem ((Bar5 + 0x04B0 ), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF); + + for ( PortNumByte = 0; PortNumByte < MAX_SATA_PORTS; PortNumByte++ ) { + RwMem ((Bar5 + 0x110 + (PortNumByte * 0x80)), AccessWidth32, 0xFFFFFFFF, 0x00); + } +} + +/** + * sataBar5RegSet - Sata Bar5 register setting + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +SataBar5RegSet ( + IN VOID *FchDataPtr + ) +{ + UINT32 AndMaskDword; + UINT32 OrMaskDword; + UINT32 Bar5; + UINT8 EfuseByte; + UINT8 FchSataAggrLinkPmCap; + UINT8 FchSataPortMultCap; + UINT8 FchSataPscCap; + UINT8 FchSataSscCap; + UINT8 FchSataFisBasedSwitching; + UINT8 FchSataCccSupport; + UINT8 FchSataAhciEnclosureManagement; + FCH_DATA_BLOCK *LocalCfgPtr; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + + FchSataAggrLinkPmCap = (UINT8) LocalCfgPtr->Sata.SataAggrLinkPmCap; + FchSataPortMultCap = (UINT8) LocalCfgPtr->Sata.SataPortMultCap; + FchSataPscCap = (UINT8) LocalCfgPtr->Sata.SataPscCap; + FchSataSscCap = (UINT8) LocalCfgPtr->Sata.SataSscCap; + FchSataFisBasedSwitching = (UINT8) LocalCfgPtr->Sata.SataFisBasedSwitching; + FchSataCccSupport = (UINT8) LocalCfgPtr->Sata.SataCccSupport; + FchSataAhciEnclosureManagement = (UINT8) LocalCfgPtr->Sata.SataAhciEnclosureManagement; + + AndMaskDword = 0; + OrMaskDword = 0; + Bar5 = 0; + + SataBar5setting (LocalCfgPtr, &Bar5); + EfuseByte = SATA_FIS_BASE_EFUSE_LOC; + GetEfuseStatus (&EfuseByte, LocalCfgPtr->StdHeader); + + if ( !FchSataPortMultCap ) { + AndMaskDword |= BIT12; + } + + if ( FchSataAggrLinkPmCap ) { + OrMaskDword |= BIT11; + } else { + AndMaskDword |= BIT11; + } + + if ( FchSataPscCap ) { + OrMaskDword |= BIT1; + } else { + AndMaskDword |= BIT1; + } + + if ( FchSataSscCap ) { + OrMaskDword |= BIT26; + } else { + AndMaskDword |= BIT26; + } + + if ( FchSataFisBasedSwitching ) { + if (EfuseByte & BIT1) { + AndMaskDword |= BIT10; + } else { + OrMaskDword |= BIT10; + } + } else { + AndMaskDword |= BIT10; + } + + // + // Disabling CCC (Command Completion Coalescing) support. + // + if ( FchSataCccSupport ) { + OrMaskDword |= BIT19; + } else { + AndMaskDword |= BIT19; + } + + if ( FchSataAhciEnclosureManagement ) { + OrMaskDword |= BIT27; + } else { + AndMaskDword |= BIT27; + } + + RwMem ((Bar5 + 0xFC), AccessWidth32, ~AndMaskDword, OrMaskDword); + + // + // SATA ESP port setting + // These config bits are set for SATA driver to identify which ports are external SATA ports and need to + // support hotplug. If a port is set as an external SATA port and need to support hotplug, then driver will + // not enable power management (HIPM & DIPM) for these ports. + // + if ( LocalCfgPtr->Sata.SataEspPort.SataPortReg != 0 ) { + RwMem ((Bar5 + 0xF8), AccessWidth32, ~(LocalCfgPtr->Sata.SataEspPort.SataPortReg), 0); + RwMem ((Bar5 + 0xF8), AccessWidth32, 0xFF00FF00, (LocalCfgPtr->Sata.SataEspPort.SataPortReg << 16)); + // + // External SATA Port Indication Registers + // If any of the ports was programmed as an external port, HCAP.SXS should also be set + // + RwMem ((Bar5 + 0xFC), AccessWidth32, (UINT32)~(BIT20), BIT20); + } else { + // + // External SATA Port Indication Registers + // If any of the ports was programmed as an external port, HCAP.SXS should also be set (Clear for no ESP port) + // + RwMem ((Bar5 + 0xF8), AccessWidth32, 0xFF00FF00, 0x00); + RwMem ((Bar5 + 0xFC), AccessWidth32, (UINT32)~(BIT20), 0x00); + } + + if ( FchSataFisBasedSwitching ) { + if (EfuseByte & BIT1) { + RwMem ((Bar5 + 0xF8), AccessWidth32, 0x00FFFFFF, 0x00); + } else { + RwMem ((Bar5 + 0xF8), AccessWidth32, 0x00FFFFFF, 0xFF000000); + } + } else { + RwMem ((Bar5 + 0xF8), AccessWidth32, 0x00FFFFFF, 0x00); + } + + if ( LocalCfgPtr->Sata.BiosOsHandOff == 1 ) { + RwMem ((Bar5 + 0x24), AccessWidth8, (UINT32)~BIT0, BIT0); + } else { + RwMem ((Bar5 + 0x24), AccessWidth8, (UINT32)~BIT0, 0x00); + } +} + +/** + * FchSataSetDeviceNumMsi - Program Sata controller support + * device number cap & MSI cap + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchSataSetDeviceNumMsi ( + IN VOID *FchDataPtr + ) +{ + UINT32 Bar5; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + Bar5 = 0; + SataBar5setting (LocalCfgPtr, &Bar5); + // + // RAID or AHCI + // + if (LocalCfgPtr->Sata.SataMode.IdeEnable == DISABLED) { + // + // IDE2 Controller is enabled + // + if (LocalCfgPtr->Sata.SataMode.Sata6AhciCap == ENABLED) { + // + // 6 AHCI mode + // + RwMem ((Bar5 + 0x0C), AccessWidth8, 0x00, 0x3F); + RwMem ((Bar5 + 0x00), AccessWidth8, (UINT32)~(BIT2 + BIT1 + BIT0), BIT2 + BIT0); + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x50 + 2), AccessWidth8, (UINT32)~(BIT3 + BIT2 + BIT1), BIT2 + BIT1, StdHeader); + RwMem ((Bar5 + 0xFC), AccessWidth8, 0x07, 0x30); + } else { + RwMem ((Bar5 + 0x0C), AccessWidth8, 0x00, 0x0F); + if ( LocalCfgPtr->Sata.SataCccSupport ) { + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x50 + 2), AccessWidth8, (UINT32)~(BIT3 + BIT2 + BIT1), BIT2 + BIT1, StdHeader); + RwMem ((Bar5 + 0xFC), AccessWidth8, 0x07, 0x20); + } else { + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x50 + 2), AccessWidth8, (UINT32)~(BIT3 + BIT2 + BIT1), BIT2, StdHeader); + } + } + } else { + // + // IDE2 Controller is disabled + // + RwMem ((Bar5 + 0x00), AccessWidth8, (UINT32)~(BIT2 + BIT1 + BIT0), BIT2 + BIT1 + BIT0); + RwMem ((Bar5 + 0x0C), AccessWidth8, 0x00, 0xFF); + if ( LocalCfgPtr->Sata.SataCccSupport ) { + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x50 + 2), AccessWidth8, (UINT32)~(BIT3 + BIT2 + BIT1), BIT3, StdHeader); + RwMem ((Bar5 + 0xFC), AccessWidth8, 0x07, 0x40); + } else { + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x50 + 2), AccessWidth8, (UINT32)~(BIT3 + BIT2 + BIT1), BIT2 + BIT1, StdHeader); + } + } +} + + +/** + * FchSataDriveDetection - Sata drive detection + * + * - Sata Ide & Sata Ide to Ahci only + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * @param[in] *Bar5Ptr Sata BAR5 base address. + * + */ +VOID +FchSataDriveDetection ( + IN VOID *FchDataPtr, + IN UINT32 *Bar5Ptr + ) +{ + UINT32 SataBarInfo; + UINT8 PortNumByte; + UINT8 SataPortType; + UINT16 IoBaseWord; + UINT32 SataLoopVarDWord; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + for ( PortNumByte = 0; PortNumByte < 4; PortNumByte++ ) { + + ReadMem (*Bar5Ptr + FCH_SATA_BAR5_REG128 + PortNumByte * 0x80, AccessWidth32, &SataBarInfo); + + if ( ( SataBarInfo & 0x0F ) == 0x03 ) { + if ( PortNumByte & BIT0 ) { + // + //this port belongs to secondary channel + // + ReadPci (((UINT32) (SATA_BUS_DEV_FUN << 16) + 0x18), AccessWidth16, &IoBaseWord, StdHeader); + } else { + // + //this port belongs to primary channel + // + ReadPci (((UINT32) (SATA_BUS_DEV_FUN << 16) + 0x10), AccessWidth16, &IoBaseWord, StdHeader); + } + + // + //if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them + // + if ( LocalCfgPtr->Sata.SataClass == SataLegacyIde ) { + IoBaseWord = ( (0x170) | ((UINT16) ( (~((UINT8) (PortNumByte & BIT0) << 7)) & 0x80 )) ); + } + + if ( PortNumByte & BIT1 ) { + // + //this port is slave + // + SataPortType = 0xB0; + } else { + // + //this port is master + // + SataPortType = 0xA0; + } + + IoBaseWord &= 0xFFF8; + LibAmdIoWrite (AccessWidth8, IoBaseWord + 6, &SataPortType, StdHeader); + + // + //Wait in loop for 30s for the drive to become ready + // + for ( SataLoopVarDWord = 0; SataLoopVarDWord < 300000; SataLoopVarDWord++ ) { + LibAmdIoRead (AccessWidth8, IoBaseWord + 7, &SataPortType, StdHeader); + if ( (SataPortType & 0x88) == 0 ) { + break; + } + FchStall (100, StdHeader); + } + } + } +} + +/** + * FchShutdownUnconnectedSataPortClock - Shutdown unconnected + * Sata port clock + * + * - Sata Ide & Sata Ide to Ahci only + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * @param[in] Bar5 Sata BAR5 base address. + * + */ +VOID +FchShutdownUnconnectedSataPortClock ( + IN VOID *FchDataPtr, + IN UINT32 Bar5 + ) +{ + UINT8 PortNumByte; + UINT8 PortSataStatusByte; + UINT8 NumOfPorts; + UINT8 FchSataClkAutoOff; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + FchSataClkAutoOff = (UINT8) LocalCfgPtr->Sata.SataClkAutoOff; + + NumOfPorts = 0; + // + // Enable SATA auto clock control by default + // + for ( PortNumByte = 0; PortNumByte < MAX_SATA_PORTS; PortNumByte++ ) { + ReadMem (Bar5 + FCH_SATA_BAR5_REG128 + (PortNumByte * 0x80), AccessWidth8, &PortSataStatusByte); + // + // Shutdown the clock for the port and do the necessary port reporting changes. + // Error port status should be 1 not 3 + // + if ( ((PortSataStatusByte & 0x0F) != 0x03) && (! ((LocalCfgPtr->Sata.SataEspPort.SataPortReg) & (1 << PortNumByte))) ) { + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x040 + 2), AccessWidth8, 0xFF, (1 << PortNumByte), StdHeader); + RwMem (Bar5 + 0x0C, AccessWidth8, ~(1 << PortNumByte), 00); + } + } ///end of for (PortNumByte=0;PortNumByte<6;PortNumByte++) + + ReadMem (Bar5 + 0x0C, AccessWidth8, &PortSataStatusByte); + + // + //if all ports are in disabled state, report at least one port + // + if ( (PortSataStatusByte & 0xFF) == 0) { + RwMem (Bar5 + 0x0C, AccessWidth8, (UINT32) ~(0xFF), 01); + } + + ReadMem (Bar5 + 0x0C, AccessWidth8, &PortSataStatusByte); + + for (PortNumByte = 0; PortNumByte < MAX_SATA_PORTS; PortNumByte ++) { + if (PortSataStatusByte & (1 << PortNumByte)) { + NumOfPorts++; + } + } + + if ( NumOfPorts == 0) { + NumOfPorts = 0x01; + } + + RwMem (Bar5 + 0x00, AccessWidth8, 0xE0, NumOfPorts - 1); +} + +/** + * FchSataSetPortGenMode - Set Sata port mode (each) for + * Gen1/Gen2/Gen3 + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchSataSetPortGenMode ( + IN VOID *FchDataPtr + ) +{ + UINT32 Bar5; + UINT8 PortNumByte; + UINT8 PortModeByte; + UINT16 SataPortMode; + BOOLEAN FchSataHotRemovalEnh; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + FchSataHotRemovalEnh = LocalCfgPtr->Sata.SataHotRemovalEnh; + + SataBar5setting (LocalCfgPtr, &Bar5); + SataPortMode = (UINT16)LocalCfgPtr->Sata.SataPortMd.SataPortMode; + PortNumByte = 0; + + while ( PortNumByte < 8 ) { + PortModeByte = (UINT8) (SataPortMode & 3); + if ( (PortModeByte == BIT0) || (PortModeByte == BIT1) ) { + if ( PortModeByte == BIT0 ) { + // + // set GEN 1 + // + RwMem (Bar5 + FCH_SATA_BAR5_REG12C + PortNumByte * 0x80, AccessWidth8, 0x0F, 0x10); + } + + if ( PortModeByte == BIT1 ) { + // + // set GEN2 (default is GEN3) + // + RwMem (Bar5 + FCH_SATA_BAR5_REG12C + PortNumByte * 0x80, AccessWidth8, 0x0F, 0x20); + } + + RwMem (Bar5 + FCH_SATA_BAR5_REG12C + PortNumByte * 0x80, AccessWidth8, 0xFF, 0x01); + } + + SataPortMode >>= 2; + PortNumByte ++; + } + + FchStall (1000, StdHeader); + SataPortMode = (UINT16)LocalCfgPtr->Sata.SataPortMd.SataPortMode; + PortNumByte = 0; + + while ( PortNumByte < 8 ) { + PortModeByte = (UINT8) (SataPortMode & 3); + + if ( (PortModeByte == BIT0) || (PortModeByte == BIT1) ) { + RwMem (Bar5 + FCH_SATA_BAR5_REG12C + PortNumByte * 0x80, AccessWidth8, 0xFE, 0x00); + } + + PortNumByte ++; + SataPortMode >>= 2; + } + + // + // Sata Hot Removal Enhance setting + // + if ( FchSataHotRemovalEnh ) { + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x80), AccessWidth16, (UINT32)~BIT8, BIT8, StdHeader); + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x0A8 ), AccessWidth16, (UINT32)~BIT0, BIT0, StdHeader); + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x80), AccessWidth16, (UINT32)~BIT8, 0, StdHeader); + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciEnv.c new file mode 100644 index 0000000..6f07174 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciEnv.c @@ -0,0 +1,109 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch SATA controller (Ide2Ahci mode) + * + * Init SATA Ide2Ahci features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. 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BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SATA_IDE2AHCIENV_FILECODE + +/** + * FchInitEnvSataIde2Ahci - Config SATA Ide2Ahci controller + * before PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvSataIde2Ahci ( + IN VOID *FchDataPtr + ) +{ + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + // + // Class code + // + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x08), AccessWidth32, 0, 0x01018F40, StdHeader); + // + // Device ID + // + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x02), AccessWidth16, 0, FCH_SATA_DID, StdHeader); + // + // SSID + // + if (LocalCfgPtr->Sata.SataAhciSsid != 0 ) { + RwPci ((SATA_BUS_DEV_FUN << 16) + 0x2C, AccessWidth32, 0x00, LocalCfgPtr->Sata.SataAhciSsid, StdHeader); + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciLate.c new file mode 100644 index 0000000..3ff2bdf --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciLate.c @@ -0,0 +1,116 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch SATA controller (Ide2Ahci mode) + * + * Init SATA Ide2Ahci features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SATA_IDE2AHCILATE_FILECODE + +/** + * FchInitLateSataIde2Ahci - Prepare SATA Ide2Ahci controller to + * boot to OS. + * + * - Set class ID to Ide2Ahci (if set to Ide2Ahci * Mode) + * - Enable Ide2Ahci interrupt + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitLateSataIde2Ahci ( + IN VOID *FchDataPtr + ) +{ + UINT32 Bar5; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + // + //program the AHCI class code + // + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x08), AccessWidth32, 0, 0x01060100, StdHeader); + // + // Device ID + // + if ( LocalCfgPtr->Sata.SataClass == SataIde2Ahci7804 ) { + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x02), AccessWidth16, 0, FCH_SATA_AMDAHCI_DID, StdHeader); + } else { + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x02), AccessWidth16, 0, FCH_SATA_AHCI_DID, StdHeader); + } + SataBar5setting (LocalCfgPtr, &Bar5); + + // + //Set interrupt enable bit + // + RwMem ((Bar5 + 0x04), AccessWidth8, (UINT32)~0, BIT1); + ShutdownUnconnectedSataPortClock (LocalCfgPtr, Bar5); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciLib.c new file mode 100644 index 0000000..9007b51 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciLib.c @@ -0,0 +1,94 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Fch SATA Ide2Ahci controller Library + * + * SATA Ide2Ahci Library + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SATA_IDE2AHCILIB_FILECODE + +/** + * sataIde2AhciSetDeviceNumMsi - Program Ide2Ahci controller support + * device number cap & MSI cap + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +SataIde2AhciSetDeviceNumMsi ( + IN VOID *FchDataPtr + ) +{ + FCH_INTERFACE *LocalCfgPtr; + + LocalCfgPtr = (FCH_INTERFACE *)FchDataPtr; + + SataSetDeviceNumMsi (LocalCfgPtr); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciMid.c new file mode 100644 index 0000000..8cb2fc9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Ide2AhciMid.c @@ -0,0 +1,103 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch SATA controller (Ide2Ahci mode) + * + * Init SATA Ide2Ahci features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SATA_IDE2AHCIMID_FILECODE + +/** + * FchInitMidSataIde2Ahci - Config SATA Ide2Ahci controller + * after PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidSataIde2Ahci ( + IN VOID *FchDataPtr + ) +{ + UINT32 Bar5; + FCH_DATA_BLOCK *LocalCfgPtr; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + + SataIde2AhciSetDeviceNumMsi (LocalCfgPtr); + + SataBar5setting (LocalCfgPtr, &Bar5); + // + //If this is not S3 resume and also if SATA set to one of IDE mode, them implement drive detection workaround. + // + if ( ! (LocalCfgPtr->Misc.S3Resume) ) { + SataDriveDetection (LocalCfgPtr, &Bar5); + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidEnv.c new file mode 100644 index 0000000..02b6c25 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidEnv.c @@ -0,0 +1,103 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch SATA controller (Raid mode) + * + * Init SATA Raid features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SATA_RAIDENV_FILECODE + + + +// +// Declaration of local functions +// + +/** + * FchInitEnvSataRaid - Config SATA Raid controller before PCI + * emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvSataRaid ( + IN VOID *FchDataPtr + ) +{ + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + FchInitEnvSataRaidProgram (FchDataPtr); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidLate.c new file mode 100644 index 0000000..e5dad1a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidLate.c @@ -0,0 +1,92 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch SATA controller (Raid mode) + * + * Init SATA Raid features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SATA_RAIDLATE_FILECODE +// +// Declaration of local functions +// + +/** + * FchInitLateSataRaid - Prepare SATA Raid controller to boot to + * OS. + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitLateSataRaid ( + IN VOID *FchDataPtr + ) +{ +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidLib.c new file mode 100644 index 0000000..a997162 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidLib.c @@ -0,0 +1,96 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Fch SATA AHCI/RAID controller Library + * + * SATA AHCI/RAID Library + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SATA_RAIDLIB_FILECODE + +/** + * sataRaidSetDeviceNumMsi - Program RAID controller support + * device number cap & MSI cap + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +SataRaidSetDeviceNumMsi ( + IN VOID *FchDataPtr + ) +{ + FCH_INTERFACE *LocalCfgPtr; + + LocalCfgPtr = (FCH_INTERFACE *)FchDataPtr; + + SataSetDeviceNumMsi (LocalCfgPtr); +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidMid.c new file mode 100644 index 0000000..fe0fb7c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/RaidMid.c @@ -0,0 +1,101 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch SATA controller (Raid mode) + * + * Init SATA Raid features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SATA_RAIDMID_FILECODE +// +// Declaration of local functions +// + +/** + * FchInitMidSataRaid - Config SATA Raid controller after PCI + * emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidSataRaid ( + IN VOID *FchDataPtr + ) +{ + UINT32 Bar5; + FCH_DATA_BLOCK *LocalCfgPtr; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + + SataRaidSetDeviceNumMsi (LocalCfgPtr); + SataBar5setting (LocalCfgPtr, &Bar5); + ShutdownUnconnectedSataPortClock (LocalCfgPtr, Bar5); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataEnv.c new file mode 100644 index 0000000..eb9cf10 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataEnv.c @@ -0,0 +1,132 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch SATA controller + * + * Init SATA features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SATA_SATAENV_FILECODE + + + +/** + * FchInitEnvSata - Config SATA controller before PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvSata ( + IN VOID *FchDataPtr + ) +{ + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + if ( LocalCfgPtr->Sata.SataMode.SataEnable == 0 ) { + return; //return if SATA controller is disabled. + } + + FchInitEnvProgramSataPciRegs (FchDataPtr); + // + // Call Sub-function for each Sata mode + // + if (( LocalCfgPtr->Sata.SataClass == SataAhci7804) || (LocalCfgPtr->Sata.SataClass == SataAhci )) { + FchInitEnvSataAhci ( LocalCfgPtr ); + } + + if (( LocalCfgPtr->Sata.SataClass == SataIde2Ahci) || (LocalCfgPtr->Sata.SataClass == SataIde2Ahci7804 )) { + FchInitEnvSataIde2Ahci ( LocalCfgPtr ); + } + + if (( LocalCfgPtr->Sata.SataClass == SataNativeIde) || (LocalCfgPtr->Sata.SataClass == SataLegacyIde )) { + FchInitEnvSataIde ( LocalCfgPtr ); + } + + if ( LocalCfgPtr->Sata.SataClass == SataRaid) { + FchInitEnvSataRaid ( LocalCfgPtr ); + } + + // + // SATA IRQ Resource + // + SataSetIrqIntResource (LocalCfgPtr, StdHeader); + + // + // SATA PHY Programming Sequence + // + FchProgramSataPhy (StdHeader); + + SataDisableWriteAccess (StdHeader); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataEnvLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataEnvLib.c new file mode 100644 index 0000000..8e2bf7f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataEnvLib.c @@ -0,0 +1,115 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Fch SATA controller Library + * + * SATA Library + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SATA_SATAENVLIB_FILECODE + +/** + * sataSetIrqIntResource - Config SATA IRQ/INT# resource + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * @param[in] StdHeader + * + */ +VOID +SataSetIrqIntResource ( + IN VOID *FchDataPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 ValueByte; + FCH_DATA_BLOCK *LocalCfgPtr; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + // + // IRQ14/IRQ15 come from IDE or SATA + // + ValueByte = 0x08; + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &ValueByte, StdHeader); + LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &ValueByte, StdHeader); + ValueByte = ValueByte & 0x0F; + + if (LocalCfgPtr->Sata.SataClass == SataLegacyIde) { + ValueByte = ValueByte | 0x50; + } else { + if (LocalCfgPtr->Sata.SataIdeMode == 1) { + // + // Both IDE & SATA set to Native mode + // + ValueByte = ValueByte | 0xF0; + } + } + + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &ValueByte, StdHeader); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeEnv.c new file mode 100644 index 0000000..ea6a23d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeEnv.c @@ -0,0 +1,130 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch SATA (IDE mode) controller + * + * Init SATA IDE (Native IDE) mode features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SATA_SATAIDEENV_FILECODE + +/** + * FchInitEnvSataIde - Config SATA IDE controller before PCI + * emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvSataIde ( + IN VOID *FchDataPtr + ) +{ + UINT8 ChannelByte; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + // + // Class code + // + if ( LocalCfgPtr->Sata.SataClass == SataLegacyIde ) { + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x08), AccessWidth32, 0, 0x01018A40, StdHeader); + } else { + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x08), AccessWidth32, 0, 0x01018F40, StdHeader); + } + // + // Device ID + // + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x02), AccessWidth16, 0, FCH_SATA_DID, StdHeader); + // + // SSID + // + if (LocalCfgPtr->Sata.SataIdeSsid != 0 ) { + RwPci ((SATA_BUS_DEV_FUN << 16) + 0x2C, AccessWidth32, 0x00, LocalCfgPtr->Sata.SataIdeSsid, StdHeader); + } + // + // Sata IDE Channel configuration + // + ChannelByte = 0x00; + ReadPci (((SATA_BUS_DEV_FUN << 16) + 0x48 + 3), AccessWidth8, &ChannelByte, StdHeader); + ChannelByte &= 0xCF; + + if ( LocalCfgPtr->Sata.SataDisUnusedIdePChannel ) { + ChannelByte |= 0x10; + } + + if ( LocalCfgPtr->Sata.SataDisUnusedIdeSChannel ) { + ChannelByte |= 0x20; + } + + WritePci (((SATA_BUS_DEV_FUN << 16) + 0x48 + 3), AccessWidth8, &ChannelByte, StdHeader); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeLate.c new file mode 100644 index 0000000..fac4766 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeLate.c @@ -0,0 +1,98 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch SATA (IDE mode) controller + * + * Init SATA IDE (Native IDE) mode features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SATA_SATAIDELATE_FILECODE + +/** + * FchInitLateSataIde - Prepare SATA controller to boot to OS. + * + * - Set class ID to AHCI (if set to AHCI * Mode) + * - Enable AHCI interrupt + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitLateSataIde ( + IN VOID *FchDataPtr + ) +{ + UINT32 Bar5; + FCH_DATA_BLOCK *LocalCfgPtr; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + + SataBar5setting (LocalCfgPtr, &Bar5); + ShutdownUnconnectedSataPortClock (LocalCfgPtr, Bar5); +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeLib.c new file mode 100644 index 0000000..6463e25 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeLib.c @@ -0,0 +1,73 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Fch SATA Ide controller Library + * + * SATA Ide2Ahci Library + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SATA_SATAIDELIB_FILECODE diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeMid.c new file mode 100644 index 0000000..ba89d45 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataIdeMid.c @@ -0,0 +1,102 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch SATA (IDE mode) controller + * + * Init SATA IDE (Native IDE) mode features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SATA_SATAIDEMID_FILECODE + +/** + * FchInitMidSataIde - Config SATA controller after PCI + * emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidSataIde ( + IN VOID *FchDataPtr + ) +{ + UINT32 Bar5; + FCH_DATA_BLOCK *LocalCfgPtr; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + + Bar5 = 0; + SataBar5setting (LocalCfgPtr, &Bar5); + // + //If this is not S3 resume and also if SATA set to one of IDE mode, them implement drive detection workaround. + // + if ( ! (LocalCfgPtr->Misc.S3Resume) ) { + SataDriveDetection (LocalCfgPtr, &Bar5); + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataLate.c new file mode 100644 index 0000000..3049e92 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataLate.c @@ -0,0 +1,145 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch SATA controller + * + * Init SATA features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SATA_SATALATE_FILECODE + + + +/** + * FchInitLateSata - Prepare SATA controller to boot to OS. + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitLateSata ( + IN VOID *FchDataPtr + ) +{ + UINT8 SataPciCommandByte; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + // + //Return immediately is sata controller is not enabled + // + if ( LocalCfgPtr->Sata.SataMode.SataEnable == 0 ) { + return; + } + + // + // Set Sata PCI Configuration Space Write enable + // + SataEnableWriteAccess (StdHeader); + + // + // Set Sata Controller Memory & IO access enable + // + ReadPci (((SATA_BUS_DEV_FUN << 16) + 0x04), AccessWidth8, &SataPciCommandByte, StdHeader); + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04), AccessWidth8, 0xFF, 0x03, StdHeader); + + // + // Call Sub-function for each Sata mode + // + if (( LocalCfgPtr->Sata.SataClass == SataAhci7804) || (LocalCfgPtr->Sata.SataClass == SataAhci )) { + FchInitLateSataAhci ( LocalCfgPtr ); + } + + if (( LocalCfgPtr->Sata.SataClass == SataIde2Ahci) || (LocalCfgPtr->Sata.SataClass == SataIde2Ahci7804 )) { + FchInitLateSataIde2Ahci ( LocalCfgPtr ); + } + + if (( LocalCfgPtr->Sata.SataClass == SataNativeIde) || (LocalCfgPtr->Sata.SataClass == SataLegacyIde )) { + FchInitLateSataIde ( LocalCfgPtr ); + } + + if ( LocalCfgPtr->Sata.SataClass == SataRaid) { + FchInitLateSataRaid ( LocalCfgPtr ); + } + + FchInitLateProgramSataRegs ( LocalCfgPtr ); + + // + // Restore Sata Controller Memory & IO access status + // + WritePci (((SATA_BUS_DEV_FUN << 16) + 0x04), AccessWidth8, &SataPciCommandByte, StdHeader); + + // + // Set Sata PCI Configuration Space Write disable + // + SataDisableWriteAccess (StdHeader); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataLib.c new file mode 100644 index 0000000..9208cf7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataLib.c @@ -0,0 +1,287 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Fch SATA controller Library + * + * SATA Library + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SATA_SATALIB_FILECODE + + + +/** + * sataBar5setting - Config SATA BAR5 + * + * + * @param[in] FchDataPtr - Fch configuration structure pointer. + * @param[in] *Bar5Ptr - SATA BAR5 buffer. + * + */ +VOID +SataBar5setting ( + IN VOID *FchDataPtr, + IN UINT32 *Bar5Ptr + ) +{ + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + // + //Get BAR5 value + // + ReadPci (((SATA_BUS_DEV_FUN << 16) + 0x24), AccessWidth32, Bar5Ptr, StdHeader); + + // + //Assign temporary BAR if is not already assigned + // + if ( (*Bar5Ptr == 0) || (*Bar5Ptr == - 1) ) { + // + //assign temporary BAR5 + // + if ( (LocalCfgPtr->Sata.TempMmio == 0) || (LocalCfgPtr->Sata.TempMmio == - 1) ) { + *Bar5Ptr = 0xFEC01000; + } else { + *Bar5Ptr = LocalCfgPtr->Sata.TempMmio; + } + WritePci (((SATA_BUS_DEV_FUN << 16) + 0x24), AccessWidth32, Bar5Ptr, StdHeader); + } + + // + //Clear Bits 9:0 + // + *Bar5Ptr = *Bar5Ptr & 0xFFFFFC00; +} + +/** + * sataEnableWriteAccess - Enable Sata PCI configuration space + * + * @param[in] StdHeader + * + */ +VOID +SataEnableWriteAccess ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + // + // BIT0 Enable write access to PCI header + // + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x040 ), AccessWidth8, 0xff, BIT0, StdHeader); +} + +/** + * sataDisableWriteAccess - Disable Sata PCI configuration space + * + * @param[in] StdHeader + * + */ +VOID +SataDisableWriteAccess ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + // + // Disable write access to PCI header + // + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x040 ), AccessWidth8, (UINT32)~BIT0, 0, StdHeader); +} + + + +#ifdef SATA_BUS_DEV_FUN_FPGA + +/** + * FchSataBar5settingFpga + * + * @param[in] LocalCfgPtr + * @param[in] Bar5 + * + */ +VOID +FchSataBar5settingFpga ( + IN FCH_DATA_BLOCK *LocalCfgPtr, + IN UINT32 *Bar5 + ) +{ + UINT8 Value; + + //Get BAR5 value + ReadPci (((SATA_BUS_DEV_FUN_FPGA << 16) + 0x24), AccWidthUint32, Bar5); + + //Assign temporary BAR if is not already assigned + if ( (*Bar5 == 0) || (*Bar5 == - 1) ) { + //assign temporary BAR5 + if ( (LocalCfgPtr->Sata.TempMMIO == 0) || (LocalCfgPtr->Sata.TempMMIO == - 1) ) { + *Bar5 = 0xFEC01000; + } else { + *Bar5 = LocalCfgPtr->Sata.TempMMIO; + } + WritePci (((SATA_BUS_DEV_FUN_FPGA << 16) + 0x24), AccWidthUint32, Bar5); + } + + //Clear Bits 9:0 + *Bar5 = *Bar5 & 0xFFFFFC00; + Value = 0x07; + WritePci (((SATA_BUS_DEV_FUN_FPGA << 16) + 0x04), AccWidthUint8, &Value); + WritePci (((PCIB_BUS_DEV_FUN << 16) + 0x04), AccWidthUint8, &Value); +} + +/** + * FchSataDriveDetectionFpga + * + * @param[in] LocalCfgPtr + * @param[in] Bar5 + * + */ +VOID +FchSataDriveDetectionFpga ( + IN FCH_DATA_BLOCK *LocalCfgPtr, + IN UINT32 *Bar5 + ) +{ + UINT32 SataBarFpgaInfo; + UINT8 PortNum; + UINT8 SataFpaPortType; + UINT16 IoBase; + UINT16 SataFpgaLoopVarWord; + AMD_CONFIG_PARAMS *StdHeader; + + StdHeader = LocalCfgPtr->StdHeader; + + TRACE ((DMSG_FCH_TRACE, "FCH - Entering sata drive detection procedure\n\n")); + TRACE ((DMSG_FCH_TRACE, "SATA BAR5 is %X \n", *pBar5)); + + for ( PortNum = 0; PortNum < 4; PortNum++ ) { + ReadMem (*Bar5 + FCH_SATA_BAR5_REG128 + PortNum * 0x80, AccWidthUint32, &SataBarFpgaInfo); + if ( ( SataBarFpgaInfo & 0x0F ) == 0x03 ) { + if ( PortNum & BIT0 ) { + //this port belongs to secondary channel + ReadPci (((UINT32) (SATA_BUS_DEV_FUN_FPGA << 16) + 0x18), AccWidthUint16, &IoBase); + } else { + //this port belongs to primary channel + ReadPci (((UINT32) (SATA_BUS_DEV_FUN_FPGA << 16) + 0x10), AccWidthUint16, &IoBase); + } + + //if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them + if ( LocalCfgPtr->Sata.SataClass == SataLegacyIde ) { + IoBase = ( (0x170) | ((UINT16) ( (~((UINT8) (PortNum & BIT0) << 7)) & 0x80 )) ); + } + + if ( PortNum & BIT1 ) { + //this port is slave + SataFpaPortType = 0xB0; + } else { + //this port is master + SataFpaPortType = 0xA0; + } + + IoBase &= 0xFFF8; + LibAmdIoWrite (AccessWidth8, IoBase + 6, &SataFpaPortType, StdHeader); + + //Wait in loop for 30s for the drive to become ready + for ( SataFpgaLoopVarWord = 0; SataFpgaLoopVarWord < 300000; SataFpgaLoopVarWord++ ) { + LibAmdIoRead (AccessWidth8, IoBase + 7, &SataFpaPortType, StdHeader); + if ( (SataFpaPortType & 0x88) == 0 ) { + break; + } + FchStall (100, StdHeader); + } + } + } +} + +/** + * FchSataDriveFpga - + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchSataDriveFpga ( + IN VOID *FchDataPtr + ) +{ + UINT32 Bar5; + FCH_DATA_BLOCK *LocalCfgPtr; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + + Bar5 = 0; + SataBar5setting (LocalCfgPtr, &Bar5); + + FchSataBar5settingFpga (LocalCfgPtr, &Bar5); + FchSataDriveDetectionFpga (LocalCfgPtr, &Bar5); +} + +#endif + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataMid.c new file mode 100644 index 0000000..09d6dc7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataMid.c @@ -0,0 +1,225 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch SATA controller + * + * Init SATA features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SATA_SATAMID_FILECODE + + + +/** + * FchInitMidSata - Config SATA controller after PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidSata ( + IN VOID *FchDataPtr + ) +{ + UINT8 SataPciCommandByte; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + if ( LocalCfgPtr->Sata.SataMode.SataEnable == 0 ) { + return; ///return if SATA controller is disabled. + } + + // + // Set Sata PCI Configuration Space Write enable + // + SataEnableWriteAccess (StdHeader); + + // + // Set Sata Controller Memory & IO access enable + // + ReadPci (((SATA_BUS_DEV_FUN << 16) + 0x04), AccessWidth8, &SataPciCommandByte, StdHeader); + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04), AccessWidth8, 0xFF, 0x03, StdHeader); + + // + // Sata Bar5 register setting for Index 0xFC + // + SataBar5RegSet ( LocalCfgPtr ); + + FchInitMidProgramSataRegs ( LocalCfgPtr ); + + // + // Set Sata port mode (each) for Gen1/Gen2/Gen3 + // + SataSetPortGenMode ( LocalCfgPtr ); + + // + // Call Sub-function for each Sata mode + // + if (( LocalCfgPtr->Sata.SataClass == SataAhci7804) || (LocalCfgPtr->Sata.SataClass == SataAhci )) { + FchInitMidSataAhci ( LocalCfgPtr ); + } + + if (( LocalCfgPtr->Sata.SataClass == SataIde2Ahci) || (LocalCfgPtr->Sata.SataClass == SataIde2Ahci7804 )) { + FchInitMidSataIde2Ahci ( LocalCfgPtr ); + } + + if (( LocalCfgPtr->Sata.SataClass == SataNativeIde) || (LocalCfgPtr->Sata.SataClass == SataLegacyIde )) { + FchInitMidSataIde ( LocalCfgPtr ); + } + + if ( LocalCfgPtr->Sata.SataClass == SataRaid) { + FchInitMidSataRaid ( LocalCfgPtr ); + } + +#ifdef SATA_BUS_DEV_FUN_FPGA + FchSataDriveFpga ( LocalCfgPtr ); +#endif + + // + // Restore Sata Controller Memory & IO access status + // + WritePci (((SATA_BUS_DEV_FUN << 16) + 0x04), AccessWidth8, &SataPciCommandByte, StdHeader); + + // + // Set Sata PCI Configuration Space Write disable + // + SataDisableWriteAccess (StdHeader); +} + +/** + * SataSetDeviceNumMsi - Program Sata controller support device + * number cap & MSI cap + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +SataSetDeviceNumMsi ( + IN VOID *FchDataPtr + ) +{ + FchSataSetDeviceNumMsi ( FchDataPtr ); +} + +/** + * SataDriveDetection - Sata drive detection + * + * - Sata Ide & Sata Ide to Ahci only + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * @param[in] *Bar5Ptr Sata BAR5 base address. + * + */ +VOID +SataDriveDetection ( + IN VOID *FchDataPtr, + IN UINT32 *Bar5Ptr + ) +{ + FchSataDriveDetection ( FchDataPtr, Bar5Ptr ); +} + +/** + * shutdownUnconnectedSataPortClock - Shutdown unconnected Sata port clock + * + * - Sata Ide & Sata Ide to Ahci only + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * @param[in] Bar5 Sata BAR5 base address. + * + */ +VOID +ShutdownUnconnectedSataPortClock ( + IN VOID *FchDataPtr, + IN UINT32 Bar5 + ) +{ + FchShutdownUnconnectedSataPortClock ( FchDataPtr, Bar5); +} + +/** + * SataSetPortGenMode - Set Sata port mode (each) for + * Gen1/Gen2/Gen3 + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +SataSetPortGenMode ( + IN VOID *FchDataPtr + ) +{ + FchSataSetPortGenMode ( FchDataPtr ); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataReset.c new file mode 100644 index 0000000..f790887 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/SataReset.c @@ -0,0 +1,92 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Sata controller + * + * Init Sata Controller features (PEI phase). + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SATA_SATARESET_FILECODE + + + +/** + * FchInitResetSata - Config Sata controller during Power-On + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitResetSata ( + IN VOID *FchDataPtr + ) +{ + FchInitResetSataProgram ( FchDataPtr ); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/Family/Hudson2/Hudson2SdEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/Family/Hudson2/Hudson2SdEnvService.c new file mode 100644 index 0000000..5df3a78 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/Family/Hudson2/Hudson2SdEnvService.c @@ -0,0 +1,133 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Hudson2 SD + * + * Init SD Controller. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SD_FAMILY_HUDSON2_HUDSON2SDENVSERVICE_FILECODE + +/** + * FchInitEnvSdProgram - Config SD controller before PCI + * emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvSdProgram ( + IN VOID *FchDataPtr + ) +{ + UINT32 SdData32; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + UINT8 SdClockControl; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + SdClockControl = (UINT8) (LocalCfgPtr->Sd.SdClockControl); + if (( SdClockControl != 4 ) && ( SdClockControl != 6 ) && ( SdClockControl != 7 )) { + SdClockControl = 4; + } + SdClockControl = SdClockControl << 1; + // + // SD Configuration + // + if ( LocalCfgPtr->Sd.SdConfig != SdDisable) { + RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xD3 , AccessWidth8, 0xBF, 0x40); + RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG41, AccessWidth8, 0xF1, 0x40 | SdClockControl ); + RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG42, AccessWidth8, 0xFE, 0x00); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGE7, AccessWidth8, 0x00, 0x12); + + ReadPci ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGA4, AccessWidth32, &SdData32, StdHeader); + SdData32 |= BIT31 + BIT24 + BIT18 + BIT16; ///ADMA + + if ( LocalCfgPtr->Sd.SdConfig == SdDma) { + SdData32 &= ~(BIT16 + BIT24); ///DMA + } else if ( LocalCfgPtr->Sd.SdConfig == SdPio) { + SdData32 &= ~(BIT16 + BIT18 + BIT24); ///PIO + } + + SdData32 &= ~(BIT17 + BIT23); ///clear bitwidth + SdData32 |= (LocalCfgPtr->Sd.SdSpeed << 17) + (LocalCfgPtr->Sd.SdBitWidth << 23); + RwPci ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGA4, AccessWidth32, 0, SdData32, StdHeader); + + // SD: Some SD cards cannot be detected in HIGH speed mode + RwPci ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGB0, AccessWidth32, (UINT32) (~ (0x03 << 10)), (UINT32) (0x03 << 10), StdHeader); + if (LocalCfgPtr->Sd.SdSsid != 0 ) { + RwPci ((SD_BUS_DEV_FUN << 16) + SD_PCI_REG2C, AccessWidth32, 0, LocalCfgPtr->Sd.SdSsid, StdHeader); + } + RwPci ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGAC, AccessWidth32, ~(UINT32)BIT1, 0, StdHeader); + } else { + RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xD3 , AccessWidth8, 0xBF, 0x00); + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/Family/Hudson2/Hudson2SdResetService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/Family/Hudson2/Hudson2SdResetService.c new file mode 100644 index 0000000..0c7f93f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/Family/Hudson2/Hudson2SdResetService.c @@ -0,0 +1,73 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Hudson2 SD Controller + * + * Init SD Controller. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SD_FAMILY_HUDSON2_HUDSON2SDRESETSERVICE_FILECODE diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/Family/Hudson2/Hudson2SdService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/Family/Hudson2/Hudson2SdService.c new file mode 100644 index 0000000..c7b59b7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/Family/Hudson2/Hudson2SdService.c @@ -0,0 +1,74 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Hudson2 SD Controller + * + * Init SD Controller. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SD_FAMILY_HUDSON2_HUDSON2SDSERVICE_FILECODE + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdEnv.c new file mode 100644 index 0000000..547ebad --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdEnv.c @@ -0,0 +1,93 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch SD controller + * + * Init SD Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_SD_SDENV_FILECODE + + +/** + * FchInitEnvSd - Config SD controller before PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvSd ( + IN VOID *FchDataPtr + ) +{ + FCH_DATA_BLOCK *LocalCfgPtr; + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + + FchInitEnvSdProgram (FchDataPtr); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdLate.c new file mode 100644 index 0000000..f6da5d8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdLate.c @@ -0,0 +1,87 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch SD controller + * + * Init SD Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_SD_SDLATE_FILECODE + +/** + * FchInitLateSd - Prepare SD controller to boot to OS. + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitLateSd ( + IN VOID *FchDataPtr + ) +{ +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdMid.c new file mode 100644 index 0000000..0b1e7b7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sd/SdMid.c @@ -0,0 +1,88 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch SD controller + * + * Init SD Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_SD_SDMID_FILECODE + +/** + * FchInitMidSd - Config SD controller after PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidSd ( + IN VOID *FchDataPtr + ) +{ +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcEnvService.c new file mode 100644 index 0000000..236b4c5 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcEnvService.c @@ -0,0 +1,119 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch LPC controller + * + * Init LPC Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_SPI_FAMILY_HUDSON2_HUDSON2LPCENVSERVICE_FILECODE + +/** + * FchInitHudson2EnvLpcPciTable - PCI device registers initial + * during early POST. + * + */ +REG8_MASK FchInitHudson2EnvLpcPciTable[] = +{ + // + // LPC Device (Bus 0, Dev 20, Func 3) + // + {0x00, LPC_BUS_DEV_FUN, 0}, + {FCH_LPC_REG40, (UINT8)~BIT2, BIT2}, /// Enabling LPC DMA Function 0x40[2]=1b 0x78[0]=0b + {FCH_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2}, + {0x78 , 0xFC, 00}, /// Enabling LPC DMA Function 0x40[2]=1b 0x78[0]=0b / Disables MSI capability + {FCH_LPC_REGBB, (UINT8)~BIT0, (BIT0 + BIT3 + BIT4 + BIT5)}, /// Enabled SPI Prefetch from HOST. + {0xFF, 0xFF, 0xFF}, +}; + +/** + * FchInitEnvLpcProgram - Config LPC controller before PCI + * emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvLpcProgram ( + IN VOID *FchDataPtr + ) +{ + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + ProgramPciByteTable ((REG8_MASK*) (&FchInitHudson2EnvLpcPciTable[0]), sizeof (FchInitHudson2EnvLpcPciTable) / sizeof (REG8_MASK), StdHeader); + + // + // Disable LPC A-Link Cycle Bypass + // + RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG50 + 2, AccessWidth8, 0xF7, BIT3); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c new file mode 100644 index 0000000..cd8ac2f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c @@ -0,0 +1,152 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch LPC controller + * + * Init LPC Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" + +#define FILECODE PROC_FCH_SPI_FAMILY_HUDSON2_HUDSON2LPCRESETSERVICE_FILECODE + +/** + * FchInitHudson2ResetLpcPciTable - Lpc (Spi) device registers + * initial during the power on stage. + * + * + * + * + */ +REG8_MASK FchInitHudson2ResetLpcPciTable[] = +{ + // + // LPC Device (Bus 0, Dev 20, Func 3) + // + {0x00, LPC_BUS_DEV_FUN, 0}, + + {FCH_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2}, + {FCH_LPC_REG7C, 0x00, BIT0 + BIT2}, + {0x78 , 0xF0, BIT2 + BIT3}, /// Enable LDRQ pin + {FCH_LPC_REGBB, 0xFF, BIT3 + BIT4 + BIT5}, + // + // Set 0xBB [5:3] = 111 to improve SPI timing margin. + // Set 0xBA [6:5] = 11 improve SPI timing margin. (SPI Prefetch enhancement) + // + {FCH_LPC_REGBB, 0xBE, BIT0 + BIT3 + BIT4 + BIT5}, + {FCH_LPC_REGBA, 0x9F, BIT5 + BIT6}, + // Force EC_PortActive to 1 to fix possible IR non function issue when NO_EC_SUPPORT is defined + {FCH_LPC_REGA4, (UINT8)~ BIT0, BIT0}, + {0xFF, 0xFF, 0xFF}, +}; + +/** + * FchInitResetLpcProgram - Config Lpc controller during Power-On + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitResetLpcProgram ( + IN VOID *FchDataPtr + ) +{ + FCH_RESET_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + // + // enable prefetch on Host, set LPC cfg 0xBB bit 0 to 1 + // + RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBA, AccessWidth16, 0xFFFF, BIT8, StdHeader); + + RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG6C, AccessWidth32, 0xFFFFFF00, 0, StdHeader); + + ProgramPciByteTable ( (REG8_MASK*) (&FchInitHudson2ResetLpcPciTable[0]), sizeof (FchInitHudson2ResetLpcPciTable) / sizeof (REG8_MASK), StdHeader); + + // + // Enabling ClkRun Function + // + RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBB, AccessWidth8, 0xFB, BIT2, StdHeader); + RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGD0, AccessWidth8, 0xFB, 0, StdHeader); + // + // LPC CLK0 Power-Down Function + // + if (!IsImcEnabled (StdHeader)) { + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD2, AccessWidth8, 0xFF, BIT3); + } else { + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD2, AccessWidth8, (UINT32)~ (BIT3), 0); + } + + if ( LocalCfgPtr->LegacyFree ) { + RwPci (((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG44), AccessWidth32, 00, 0x0003C000, StdHeader); + } else { + RwPci (((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG44), AccessWidth32, 00, 0xFF03FFD5, StdHeader); + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcEnv.c new file mode 100644 index 0000000..8c154a5 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcEnv.c @@ -0,0 +1,122 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch LPC controller + * + * Init LPC Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_SPI_LPCENV_FILECODE + + + +/** + * FchInitEnvLpc - Config LPC controller before PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvLpc ( + IN VOID *FchDataPtr + ) +{ + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + // + // LPC CFG programming + // + // + // Turn on and configure LPC clock (48MHz) + // + RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x28, AccessWidth32, (UINT32)~(BIT21 + BIT20 + BIT19), 2 << 19); + RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, (UINT32)~BIT7, 0); + + // + // Initialization of pci config space + // + FchInitEnvLpcProgram (FchDataPtr); + + // + // SSID for LPC Controller + // + if (LocalCfgPtr->Spi.LpcSsid != 0 ) { + RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Spi.LpcSsid, StdHeader); + } + // + // LPC MSI + // + if ( LocalCfgPtr->Spi.LpcMsiEnable ) { + RwPci ((LPC_BUS_DEV_FUN << 16) + 0x78 , AccessWidth32, (UINT32)~BIT1, (UINT32)BIT1, StdHeader); + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcLate.c new file mode 100644 index 0000000..4d2d7e6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcLate.c @@ -0,0 +1,86 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch LPC controller + * + * Init LPC Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_SPI_LPCLATE_FILECODE + +/** + * FchInitLateLpc - Prepare Ir controller to boot to OS. + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitLateLpc ( + IN VOID *FchDataPtr + ) +{ + RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBB, AccessWidth8, 0xBF, BIT3 + BIT4 + BIT5, ((FCH_DATA_BLOCK *)FchDataPtr)->StdHeader); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcMid.c new file mode 100644 index 0000000..428cb7e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcMid.c @@ -0,0 +1,87 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch LPC controller + * + * Init LPC Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_SPI_LPCMID_FILECODE + +/** + * FchInitMidLpc - Config Lpc controller after PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidLpc ( + IN VOID *FchDataPtr + ) +{ +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcReset.c new file mode 100644 index 0000000..0c3607a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/LpcReset.c @@ -0,0 +1,98 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch LPC controller + * + * Init LPC Controller features (PEI phase). + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_SPI_LPCRESET_FILECODE + + + +/** + * FchInitResetLpc - Config Lpc controller during Power-On + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitResetLpc ( + IN VOID *FchDataPtr + ) +{ + FCH_RESET_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + FchInitResetLpcProgram (FchDataPtr); + +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/SpiEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/SpiEnv.c new file mode 100644 index 0000000..562c274 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/SpiEnv.c @@ -0,0 +1,88 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Spi (Lpc) controller + * + * Init Spi (Lpc) Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_SPI_SPIENV_FILECODE + +/** + * FchInitEnvSpi - Config Spi controller before PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvSpi ( + IN VOID *FchDataPtr + ) +{ + FchInitEnvLpc (FchDataPtr); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/SpiLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/SpiLate.c new file mode 100644 index 0000000..b8016ae --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/SpiLate.c @@ -0,0 +1,140 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Spi (Lpc) controller + * + * Init Spi (Lpc) Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_SPI_SPILATE_FILECODE + +/** + * FchInitLateSpi - Prepare Spi controller to boot to OS. + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitLateSpi ( + IN VOID *FchDataPtr + ) +{ + FchInitLateLpc (FchDataPtr); +} + +/** + * FchSpiUnlock - Fch SPI Unlock + * + * + * @param[in] FchDataPtr + * + */ +VOID +FchSpiUnlock ( + IN VOID *FchDataPtr + ) +{ + UINT32 SpiRomBase; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + SpiRomBase = LocalCfgPtr->Spi.RomBaseAddress; + + RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG50, AccessWidth32, (UINT32)~(BIT0 + BIT1), 0, StdHeader); + RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG54, AccessWidth32, (UINT32)~(BIT0 + BIT1), 0, StdHeader); + RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG58, AccessWidth32, (UINT32)~(BIT0 + BIT1), 0, StdHeader); + RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG5C, AccessWidth32, (UINT32)~(BIT0 + BIT1), 0, StdHeader); + RwMem (SpiRomBase + FCH_SPI_MMIO_REG00, AccessWidth32, (UINT32)~(BIT22 + BIT23), (UINT32)(BIT22 + BIT23)); +} + +/** + * FchSpiLock - Fch SPI lock + * + * + * @param[in] FchDataPtr + * + */ +VOID +FchSpiLock ( + IN VOID *FchDataPtr + ) +{ + UINT32 SpiRomBase; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + SpiRomBase = LocalCfgPtr->Spi.RomBaseAddress; + + RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG50, AccessWidth32, (UINT32)~(BIT0 + BIT1), (UINT32)(BIT0 + BIT1), StdHeader); + RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG54, AccessWidth32, (UINT32)~(BIT0 + BIT1), (UINT32)(BIT0 + BIT1), StdHeader); + RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG58, AccessWidth32, (UINT32)~(BIT0 + BIT1), (UINT32)(BIT0 + BIT1), StdHeader); + RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG5C, AccessWidth32, (UINT32)~(BIT0 + BIT1), (UINT32)(BIT0 + BIT1), StdHeader); + RwMem (SpiRomBase + FCH_SPI_MMIO_REG00, AccessWidth32, (UINT32)~(BIT22 + BIT23), 0); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/SpiMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/SpiMid.c new file mode 100644 index 0000000..c924ee2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/SpiMid.c @@ -0,0 +1,88 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Spi (Lpc) controller + * + * Init Spi (Lpc) Controller features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_SPI_SPIMID_FILECODE + +/** + * FchInitMidSpi - Config Spi controller after PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidSpi ( + IN VOID *FchDataPtr + ) +{ + FchInitMidLpc (FchDataPtr); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/SpiReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/SpiReset.c new file mode 100644 index 0000000..f1f62b1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/SpiReset.c @@ -0,0 +1,543 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Spi controller + * + * Init Spi Controller features (PEI phase). + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 64064 $ @e $Date: 2012-01-15 22:36:53 -0600 (Sun, 15 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_SPI_SPIRESET_FILECODE + +/** + * FchDummy2 - Dummy2 + * + * + * + * @param[in] SpiRomBase - Spi Rom Base. + * + */ +VOID +FchDummy2 ( + IN UINT32 SpiRomBase + ); + +VOID +FchDummy ( + IN UINT32 SpiRomBase + ); + +VOID +FchSpiExecute ( + IN UINT32 SpiRomBase + ); + +VOID +FchResetFifo ( + IN UINT32 SpiRomBase + ); + +VOID +FchResetFifoToLast ( + IN UINT32 SpiRomBase + ); + +UINT32 +FchReadSpiId ( + IN UINT32 SpiRomBase, + IN BOOLEAN Flag + ); + +BOOLEAN +FchReadSpiQe ( + IN UINT32 SpiRomBase, + IN UINT32 DeviceID + ); + +VOID +FchWriteSpiQe ( + IN UINT32 SpiRomBase, + IN UINT32 DeviceID + ); + +VOID +FchSetQualMode ( + IN UINT32 SpiQualMode, + IN UINT32 SpiRomBase, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +FchClearQualMode ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +FchCheckSpiQe ( + IN UINT32 SpiRomBase, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/** + * FchDummy - Dummy + * + * + * + * @param[in] SpiRomBase - Spi Rom Base. + * + */ +VOID +FchDummy ( + IN UINT32 SpiRomBase + ) +{ + ACPIMMIO32 (SpiRomBase + FCH_SPI_MMIO_REG00); +} +/** + * FchSpiExecute - SPI Execute + * + * + * + * @param[in] SpiRomBase - Spi Rom Base. + * + */ +VOID +FchSpiExecute ( + IN UINT32 SpiRomBase + ) +{ + UINT32 SpiReg00; + SpiReg00 = BIT31 + BIT16; + ACPIMMIO32 (SpiRomBase + FCH_SPI_MMIO_REG00) |= BIT16; + do { + SpiReg00 = ACPIMMIO32 (SpiRomBase + FCH_SPI_MMIO_REG00); + } while ((SpiReg00 & (BIT31 + BIT16))); +} +/** + * FchResetFifo - Reset SPI FIFO + * + * + * + * @param[in] SpiRomBase - Spi Rom Base. + * + */ +VOID +FchResetFifo ( + IN UINT32 SpiRomBase + ) +{ + ACPIMMIO32 (SpiRomBase + FCH_SPI_MMIO_REG00) |= BIT20; + //ACPIMMIO32 (SpiRomBase + FCH_SPI_MMIO_REG00) |= BIT21; +} +/** + * FchResetFifoToLast - Reset SPI FIFO to last + * + * + * + * @param[in] SpiRomBase - Spi Rom Base. + * + */ +VOID +FchResetFifoToLast ( + IN UINT32 SpiRomBase + ) +{ + ACPIMMIO32 (SpiRomBase + FCH_SPI_MMIO_REG00) |= BIT20; +} + +/** + * FchReadSpiId - Read SPI ID + * + * + * + * @param[in] SpiRomBase - Spi Rom Base. + * @param[in] Flag - Read Flag. + * + */ +UINT32 +FchReadSpiId ( + IN UINT32 SpiRomBase, + IN BOOLEAN Flag + ) +{ + UINT32 DeviceID; + UINT8 i; + DeviceID = 0; + if (Flag) { + ACPIMMIO16 (SpiRomBase + FCH_SPI_MMIO_REG00) = 0x409F; + FchSpiExecute (SpiRomBase); + FchResetFifo (SpiRomBase); + for (i = 0; i < 3; i++) { + DeviceID |= ((UINT32) (ACPIMMIO8 (SpiRomBase + FCH_SPI_MMIO_REG0C)) << (i*8)); + } + } else { + FchDummy (SpiRomBase); + FchDummy2 (SpiRomBase); + } + return DeviceID; +} +/** + * FchReadSpiQe - Read SPI Qual Enable + * + * + * + * @param[in] SpiRomBase - Spi Rom Base. + * @param[in] DeviceID - Devic ID. + * + */ +BOOLEAN +FchReadSpiQe ( + IN UINT32 SpiRomBase, + IN UINT32 DeviceID + ) +{ + UINT8 StatusLen; + UINT8 dbStatus; + UINT8 dbStatus1; + UINT8 StatusRead; + UINT8 StatusWrite; + UINT8 QualEnable; + UINT8 QualEnable1; + + StatusLen = 0x02; + StatusRead = 0x05; + StatusWrite = 0x01; + QualEnable = 0; + QualEnable1 = 0; + + switch (DeviceID) { + case 0x0024C2: //Macronix_MX25L1633E + case 0x0025C2: //Macronix_MX25L1636E + case 0x005EC2: //Macronix_MX25L3235D + case 0x165EC2: //Macronix_MX25L3235D:tested + QualEnable = 0x40; + break; + + case 0x0014ef: //Wnbond_W25X16= S25FL016K + case 0x004015: //Wnbond_W25Q16CV + StatusLen = 0x02; + StatusRead = 0x35; + QualEnable1 = 0x02; + break; + + case 0x00861F: //Atmel_AT25DQ161 + StatusRead = 0x3F; + StatusRead = 0x3E; + QualEnable = 0x80; + break; + + default: + return FALSE; + } + RwMem (SpiRomBase + FCH_SPI_MMIO_REG00, AccessWidth16, 0, (StatusLen << 12) | StatusRead); + FchSpiExecute (SpiRomBase); + FchResetFifo (SpiRomBase); + ReadMem (SpiRomBase + FCH_SPI_MMIO_REG0C, AccessWidth8, &dbStatus); + ReadMem (SpiRomBase + FCH_SPI_MMIO_REG0C, AccessWidth8, &dbStatus); + ReadMem (SpiRomBase + FCH_SPI_MMIO_REG0C, AccessWidth8, &dbStatus1); + if ((dbStatus & QualEnable) || (dbStatus1 & QualEnable1) ) { + return TRUE; + } + return FALSE; +} +/** + * FchWriteSpiQe - Write SPI Qual Enable + * + * + * + * @param[in] SpiRomBase - Spi Rom Base. + * @param[in] DeviceID - Devic ID. + * + */ +VOID +FchWriteSpiQe ( + IN UINT32 SpiRomBase, + IN UINT32 DeviceID + ) +{ + UINT8 StatusLen; + UINT8 StatusWriteLen; + UINT8 dbStatus; + UINT8 dbStatus1; + UINT8 StatusRead; + UINT8 StatusWrite; + UINT8 QualEnable; + UINT8 QualEnable1; + + StatusLen = 0x02; + StatusRead = 0x05; + StatusWrite = 0x01; + StatusWriteLen = 0x01; + QualEnable = 0; + QualEnable1 = 0; + + switch (DeviceID) { + case 0x0024C2: //Macronix_MX25L1633E + case 0x0025C2: //Macronix_MX25L1636E + case 0x005EC2: //Macronix_MX25L3235D + case 0x165EC2: //Macronix_MX25L3235D:tested + QualEnable = 0x40; + break; + + case 0x0014ef: //Wnbond_W25X16= S25FL016K + case 0x004015: //Wnbond_W25Q16CV + StatusLen = 0x02; + StatusRead = 0x35; + QualEnable1 = 0x02; + break; + + case 0x00861F: //Atmel_AT25DQ161 + StatusRead = 0x3F; + StatusRead = 0x3E; + QualEnable = 0x80; + break; + + default: + return ; + } + RwMem (SpiRomBase + FCH_SPI_MMIO_REG00, AccessWidth16, 0, (StatusLen << 12) | StatusRead); + FchSpiExecute (SpiRomBase); + FchResetFifo (SpiRomBase); + ReadMem (SpiRomBase + FCH_SPI_MMIO_REG0C, AccessWidth8, &dbStatus); + ReadMem (SpiRomBase + FCH_SPI_MMIO_REG0C, AccessWidth8, &dbStatus1); + + RwMem (SpiRomBase + FCH_SPI_MMIO_REG00, AccessWidth16, 0, 0x0006); + FchSpiExecute (SpiRomBase); + + FchResetFifo (SpiRomBase); + dbStatus |= QualEnable; + dbStatus1 |= QualEnable1; + WriteMem (SpiRomBase + FCH_SPI_MMIO_REG0C, AccessWidth8, &dbStatus); + WriteMem (SpiRomBase + FCH_SPI_MMIO_REG0C, AccessWidth8, &dbStatus1); + RwMem (SpiRomBase + FCH_SPI_MMIO_REG00, AccessWidth16, 0, (StatusWriteLen << 8) | StatusWrite); + FchSpiExecute (SpiRomBase); +} +/** + * FchSetQualMode - Set SPI Qual Mode + * + * + * + * @param[in] SpiQualMode- Spi Qual Mode. + * @param[in] SpiRomBase - Spi Rom Base. + * @param[in] StdHeader - Standard Header. + * + */ +VOID +FchSetQualMode ( + IN UINT32 SpiQualMode, + IN UINT32 SpiRomBase, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GEVENT_REG09, AccessWidth8, (UINT32)~BIT3, (UINT32)BIT3); + RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBB, AccessWidth8, (UINT32)~BIT0, (UINT32)BIT0, StdHeader); + RwMem (SpiRomBase + FCH_SPI_MMIO_REG00, AccessWidth32, (UINT32)~( BIT18 + BIT29 + BIT30), ((SpiQualMode & 1) << 18) + ((SpiQualMode & 6) << 28)); +} +/** + * FchClearQualMode - Clear SPI Qual Mode + * + * + * + * @param[in] StdHeader - Standard Header. + * + */ +VOID +FchClearQualMode ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 SpiRomBase; + // + // Get Spi ROM Base Address + // + ReadPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA0, AccessWidth32, &SpiRomBase, StdHeader); + RwMem (SpiRomBase + FCH_SPI_MMIO_REG00, AccessWidth32, (UINT32)~( BIT18 + BIT29 + BIT30), 0); + RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GEVENT_REG09, AccessWidth8, (UINT32)~BIT3, 0); + RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBB, AccessWidth8, (UINT32)~ BIT0, 0, StdHeader); +} +/** + * FchCheckSpiQe - Check SPI Qual Enable + * + * + * + * @param[in] SpiRomBase - Spi Rom Base. + * @param[in] StdHeader - Standard Header. + * + */ +BOOLEAN +FchCheckSpiQe ( + IN UINT32 SpiRomBase, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 DeviceID; + //FchClearQualMode (SpiRomBase, StdHeader); + FchReadSpiId (SpiRomBase, FALSE); + DeviceID = FchReadSpiId (SpiRomBase, TRUE); + //if (DeviceID != 0x165EC2) FCH_DEADLOOP(); + switch (DeviceID) { + case 0x0024C2: //Macronix_MX25L1633E + case 0x0025C2: //Macronix_MX25L1636E + case 0x005EC2: //Macronix_MX25L3235D + case 0x165EC2: //Macronix_MX25L3235D:tested + case 0x0014ef: //Wnbond_W25X16= S25FL016K + case 0x004015: //Wnbond_W25Q16CV + case 0x00861F: //Atmel_AT25DQ161 + if (FchReadSpiQe (SpiRomBase, DeviceID)) { + return TRUE; + } else { + do { + FchWriteSpiQe (SpiRomBase, DeviceID); + if (FchReadSpiQe (SpiRomBase, DeviceID)) { + return TRUE; + } + } while (!FchReadSpiQe (SpiRomBase, DeviceID)); + } + break; + } + return FALSE; +} +/** + * FchInitResetSpi - Config Spi controller during Power-On + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitResetSpi ( + IN VOID *FchDataPtr + ) +{ + UINT32 SpiModeByte; + UINT32 SpiRomBase; + FCH_RESET_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + SpiRomBase = UserOptions.FchBldCfg->CfgSpiRomBaseAddress; + + // + // Set Spi ROM Base Address + // + RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA0, AccessWidth32, 0x001F, SpiRomBase, StdHeader); + + // + // Spi Mode Initial + // + RwMem (SpiRomBase + FCH_SPI_MMIO_REG00, AccessWidth32, 0xFFFFFFFF, (BIT19 + BIT24 + BIT25 + BIT26)); + RwMem (SpiRomBase + FCH_SPI_MMIO_REG0C, AccessWidth32, 0xFFC0FFFF, 0 ); + + if (LocalCfgPtr->SpiSpeed) { + RwMem (SpiRomBase + FCH_SPI_MMIO_REG0C, AccessWidth32, (UINT32)~(BIT13 + BIT12), ((LocalCfgPtr->SpiSpeed - 1 ) << 12)); + } + + if (LocalCfgPtr->FastSpeed) { + RwMem (SpiRomBase + FCH_SPI_MMIO_REG0C, AccessWidth32, (UINT32)~(BIT15 + BIT14), ((LocalCfgPtr->FastSpeed - 1 ) << 14)); + } + + RwMem (SpiRomBase + FCH_SPI_MMIO_REG1C, AccessWidth32, (UINT32)~(BIT10), ((LocalCfgPtr->BurstWrite) << 10)); + + SpiModeByte = LocalCfgPtr->Mode; + if (LocalCfgPtr->Mode) { + if ((SpiModeByte == FCH_SPI_MODE_QUAL_114) || (SpiModeByte == FCH_SPI_MODE_QUAL_144)) { + if (FchCheckSpiQe (SpiRomBase, StdHeader)) { + FchSetQualMode (SpiModeByte, SpiRomBase, StdHeader); + } + } else { + RwMem (SpiRomBase + FCH_SPI_MMIO_REG00, AccessWidth32, (UINT32)~( BIT18 + BIT29 + BIT30), ((LocalCfgPtr->Mode & 1) << 18) + ((LocalCfgPtr->Mode & 6) << 28)); + } + } else { + if (FchCheckSpiQe (SpiRomBase, StdHeader)) { + SpiModeByte = FCH_SPI_MODE_QUAL_144; + //FchSetQualMode (SpiModeByte, SpiRomBase, StdHeader); + } + } + // Enabling SPI ROM Prefetch + // Set LPC cfg 0xBA bit 8 + RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBA, AccessWidth16, 0xFFFF, BIT8, StdHeader); + + // Enable SPI Prefetch for USB, set LPC cfg 0xBA bit 7 to 1. + RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBA, AccessWidth16, 0xFFFF, BIT7, StdHeader); +} +/** + * FchDummy2 - Dummy2 + * + * + * + * @param[in] SpiRomBase - Spi Rom Base. + * + */ +VOID +FchDummy2 ( + IN UINT32 SpiRomBase + ) +{ + ACPIMMIO32 (SpiRomBase + FCH_SPI_MMIO_REG00); +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciEnv.c new file mode 100644 index 0000000..babd852 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciEnv.c @@ -0,0 +1,87 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch USB EHCI controller + * + * Init USB EHCI features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_EHCIENV_FILECODE + +/** + * FchInitEnvUsbEhci - Config USB EHCI controller before PCI + * emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvUsbEhci ( + IN VOID *FchDataPtr + ) +{ +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciLate.c new file mode 100644 index 0000000..819aa1a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciLate.c @@ -0,0 +1,87 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch USB EHCI controller + * + * Init USB EHCI features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_EHCILATE_FILECODE + +/** + * FchInitLateUsbEhci - Config USB EHCI controller before OS + * boot + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitLateUsbEhci ( + IN VOID *FchDataPtr + ) +{ +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciMid.c new file mode 100644 index 0000000..8afb6d0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciMid.c @@ -0,0 +1,186 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch USB EHCI controller + * + * Init USB EHCI features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_EHCIMID_FILECODE + +/* extern VOID FchEhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr); */ +// +// Declaration of local functions +// +/** + * EhciInitAfterPciInit - Config USB controller after PCI emulation + * + * @param[in] Value Controller PCI config address (bus# + device# + function#) + * @param[in] FchDataPtr Fch configuration structure pointer. + */ +VOID EhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr); + +/** + * FchInitMidUsbEhci - Config USB EHCI controller after PCI + * emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidUsbEhci ( + IN VOID *FchDataPtr + ) +{ + FCH_DATA_BLOCK *LocalCfgPtr; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + + FchInitMidUsbEhci1 (LocalCfgPtr); + FchInitMidUsbEhci2 (LocalCfgPtr); + FchInitMidUsbEhci3 (LocalCfgPtr); +} + +/** + * FchInitMidUsbEhci1 - Config USB1 EHCI controller after PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidUsbEhci1 ( + IN FCH_DATA_BLOCK *FchDataPtr + ) +{ + UINT32 DeviceId; + + DeviceId = (USB1_EHCI_BUS_DEV_FUN << 16); + EhciInitAfterPciInit (DeviceId, FchDataPtr); + +} + +/** + * FchInitMidUsbEhci2 - Config USB2 EHCI controller after PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidUsbEhci2 ( + IN FCH_DATA_BLOCK *FchDataPtr + ) +{ + UINT32 DeviceId; + + DeviceId = (USB2_EHCI_BUS_DEV_FUN << 16); + EhciInitAfterPciInit (DeviceId, FchDataPtr); + +} + +/** + * FchInitMidUsbEhci3 - Config USB3 EHCI controller after PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ + +VOID +FchInitMidUsbEhci3 ( + IN FCH_DATA_BLOCK *FchDataPtr + ) +{ + UINT32 DeviceId; + + DeviceId = (USB3_EHCI_BUS_DEV_FUN << 16); + EhciInitAfterPciInit (DeviceId, FchDataPtr); + +} + +/** + * EhciInitAfterPciInit - Config EHCI controller after PCI + * emulation + * + * + * @param[in] Value EHCI Controler info. + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +EhciInitAfterPciInit ( + IN UINT32 Value, + IN FCH_DATA_BLOCK *FchDataPtr + ) +{ + FchEhciInitAfterPciInit ( Value, FchDataPtr); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciReset.c new file mode 100644 index 0000000..e6e8c5d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/EhciReset.c @@ -0,0 +1,89 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Ehci controller + * + * Init Ehci Controller features (PEI phase). + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_EHCIRESET_FILECODE + +/** + * FchInitResetEhci - Config Ehci controller during Power-On + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitResetEhci ( + IN VOID *FchDataPtr + ) +{ +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciEnvService.c new file mode 100644 index 0000000..d3fc9b4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciEnvService.c @@ -0,0 +1,71 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch USB EHCI controller + * + * Init USB EHCI features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCIENVSERVICE_FILECODE diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciLateService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciLateService.c new file mode 100644 index 0000000..91122ff --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciLateService.c @@ -0,0 +1,74 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch USB EHCI controller + * + * Init USB EHCI features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCILATESERVICE_FILECODE +// +// Declaration of local functions +// diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c new file mode 100644 index 0000000..31b1079 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c @@ -0,0 +1,210 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch USB EHCI controller + * + * Init USB EHCI features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCIMIDSERVICE_FILECODE +// +// Declaration of local functions +// + +/** + * FchEhciInitAfterPciInit - Config USB controller after PCI emulation + * + * @param[in] Value Controller PCI config address (bus# + device# + function#) + * @param[in] FchDataPtr Fch configuration structure pointer. + */ +VOID +FchEhciInitAfterPciInit ( + IN UINT32 Value, + IN FCH_DATA_BLOCK *FchDataPtr + ) +{ + UINT32 BarAddress; + UINT32 Var; + + // + //Get BAR address + // + ReadPci ((UINT32) Value + FCH_EHCI_REG10, AccessWidth32, &BarAddress, FchDataPtr->StdHeader); + if ( (BarAddress != - 1) && (BarAddress != 0) ) { + // + //Enable Memory access + // + RwPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth8, 0, BIT1, FchDataPtr->StdHeader); + if (FchDataPtr->Usb.EhciSsid != 0 ) { + RwPci ((UINT32) Value + FCH_EHCI_REG2C, AccessWidth32, 0x00, FchDataPtr->Usb.EhciSsid, FchDataPtr->StdHeader); + } + // + //USB Common PHY CAL & Control Register setting + // + Var = 0x00020F00; + WriteMem (BarAddress + 0x0C0 , AccessWidth32, &Var); + // + // IN AND OUT DATA PACKET FIFO THRESHOLD + // EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40 //OUT threshold bits[23:16]=0x40 + // + RwMem (BarAddress + FCH_EHCI_BAR_REGA4, AccessWidth32, 0xFF00FF00, 0x00400040); + // + // EHCI Dynamic Clock Gating Feature + // Enable Global Clock Gating (BIT14) + // + RwMem (BarAddress + FCH_EHCI_BAR_REGBC, AccessWidth32, (UINT32)~( BIT12 + BIT14), (UINT32)(BIT12 + BIT14)); + RwMem (BarAddress + 0x0B0 , AccessWidth32, (UINT32)~BIT5, (UINT32)BIT5); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth16, (UINT32)~BIT12, (UINT32)BIT12); + //RPR 8.26 Incorrect gated signals in xhc_to_s5 + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, (UINT32)~BIT16, (UINT32)BIT16); + // + // Enable adding extra flops to PHY rsync path + // Step 1: + // EHCI_BAR 0xB4 [6] = 1 + // EHCI_BAR 0xB4 [7] = 0 + // EHCI_BAR 0xB4 [12] = 0 ("VLoad") + // All other bit field untouched + // Step 2: + // EHCI_BAR 0xB4[12] = 1 + // + // USB 2.0 Ports Driving Strength + // Step1 is done by default + // Step2 + RwMem (BarAddress + FCH_EHCI_BAR_REGB4, AccessWidth32, (UINT32)~BIT12, (UINT32)BIT12); + // Step3 + RwMem (BarAddress + FCH_EHCI_BAR_REGC4, AccessWidth32, (UINT32) (~ 0x00000f00), 0x00000200); + RwMem (BarAddress + 0x0C0 , AccessWidth32, (UINT32) (~ 0x0000ff00), 0x00000f00); + + //Set EHCI_pci_configx50[6]='1' to disable EHCI MSI support + RwPci ((UINT32) Value + 0x50 , AccessWidth32, ~ ((UINT32) (0x01 << 6)), (UINT32) (0x01 << 6), FchDataPtr->StdHeader); + // EHCI Async Park Mode + //Set EHCI_pci_configx50[11:8]=0x1 + //Set EHCI_pci_configx50[15:12]=0x1 + //Set EHCI_pci_configx50[17]=0x1 + RwPci ((UINT32) Value + 0x50 , AccessWidth32, ~ ((UINT32) (0x0F << 8)), (UINT32) (0x01 << 8), FchDataPtr->StdHeader); + RwPci ((UINT32) Value + 0x50 , AccessWidth32, ~ ((UINT32) (0x0F << 12)), (UINT32) (0x01 << 12), FchDataPtr->StdHeader); + RwPci ((UINT32) Value + 0x50 , AccessWidth32, ~ ((UINT32) (0x01 << 17)), (UINT32) (0x01 << 17), FchDataPtr->StdHeader); + //RPR 7.14 Extend InterPacket Gap + RwPci ((UINT32) Value + 0x50 , AccessWidth32, ~ ((UINT32) (0x01 << 21)), (UINT32) (0x01 << 21), FchDataPtr->StdHeader); + + // Enabling EHCI Async Stop Enhancement + //Set EHCI_pci_configx50[29]='1' to disableEnabling EHCI Async Stop Enhancement + // + RwPci ((UINT32) Value + 0x50 , AccessWidth32, ~ ((UINT32) (0x01 << 29)), (UINT32) (0x01 << 29), FchDataPtr->StdHeader); + // + // recommended setting "EHCI Advance PHY Power Savings" + // Set EHCI_pci_configx50[31]='1' + // Fix for EHCI controller driver yellow sign issue under device manager + // when used in conjunction with HSET tool driver. EHCI PCI config 0x50[20]=1 + // Disable USB data cache to resolve USB controller hang issue with Lan adaptor. + // EHCI PCI config register 50h bit 26 to `1'. + // + RwPci ((UINT32) Value + 0x50 + 2, AccessWidth16, (UINT16)0xFFFF, BIT16 + BIT10, FchDataPtr->StdHeader); + // + // USB Delay A-Link Express L1 State + // PING Response Fix Enable EHCI_PCI_Config x54[1] = 1 + // Enable empty list mode. x54[3] + // Enable "L1 Early Exit" functionality. 0x54 [6:5] = 0x3 0x54 [9:7] = 0x4 + // + RwPci ((UINT32) Value + 0x54 , AccessWidth32, (UINT32)~BIT0, 0x0000027b, FchDataPtr->StdHeader); + RwAlink ((FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29)), 0xFFFEFFFF, (UINT32)BIT16, FchDataPtr->StdHeader); + if ( FchDataPtr->Usb.UsbMsiEnable) { + RwPci ((UINT32) Value + 0x50 , AccessWidth32, (UINT32)~BIT6, 0x00, FchDataPtr->StdHeader); + } + // Long Delay on Framelist Read Causing EHCI DMA to Address 0 - Fix + // RWPCI ((UINT32) Value + 0x54 , AccWidthUint32 | S3_SAVE, ~BIT13, BIT13); + // LS connection can't wake up system from S3/S4/S5 when EHCI owns the port - Fix + RwPci ((UINT32) Value + 0x54 , AccessWidth32, (UINT32)~BIT4, (UINT32)BIT4, FchDataPtr->StdHeader); + // EHCI lMU Hangs when Run/Stop is Set First and PDC is Enabled Near End uFrame 7 - Fix Enable + RwPci ((UINT32) Value + 0x54 , AccessWidth32, (UINT32)~BIT11, (UINT32)BIT11, FchDataPtr->StdHeader); + // RPR 7.25 SB02674 + RwPci ((UINT32) Value + 0x54 , AccessWidth16, (UINT16)0x5FFF, BIT13 + BIT15, FchDataPtr->StdHeader); + // RPR 7.26 SB02684 + RwPci ((UINT32) Value + 0x50 + 2, AccessWidth16, (UINT32)~BIT3, (UINT32)BIT3, FchDataPtr->StdHeader); + // RPR 7.26 SB02687 + RwPci ((UINT32) Value + 0x54 + 2, AccessWidth16, (UINT16)0xFFFC, BIT0 + BIT1, FchDataPtr->StdHeader); + // RPR 7.28 SB02700 + RwPci ((UINT32) Value + 0x54 + 2, AccessWidth16, (UINT16)0xFFFB, BIT2, FchDataPtr->StdHeader); + // RPR 7.29 SB02703 + RwPci ((UINT32) Value + 0x54 + 2, AccessWidth16, (UINT16)0xFFF7, BIT3, FchDataPtr->StdHeader); + } else { + // + // Fake Bar + // + BarAddress = FCH_FAKE_USB_BAR_ADDRESS; + WritePci ((UINT32) Value + FCH_EHCI_REG10, AccessWidth32, &BarAddress, FchDataPtr->StdHeader); + // + //Enable Memory access + // + RwPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth8, 0, BIT1, FchDataPtr->StdHeader); + // + // Enable Global Clock Gating (BIT14) + // + RwMem (BarAddress + FCH_EHCI_BAR_REGBC, AccessWidth32, (UINT32)~( BIT12 + BIT14), (UINT32)(BIT12 + BIT14)); + RwMem (BarAddress + 0x0B0 , AccessWidth32, (UINT32)~BIT5, (UINT32)BIT5); + RwPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth8, 0, 0, FchDataPtr->StdHeader); + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciEnvService.c new file mode 100644 index 0000000..3d40cb4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciEnvService.c @@ -0,0 +1,130 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH USB OHCI controller + * + * Init USB OHCI features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCIENVSERVICE_FILECODE +// +// Declaration of local functions +// +// +// Declaration of local functions +// +/** + * FchSetUsbEnableReg + * emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchSetUsbEnableReg ( + IN FCH_DATA_BLOCK *FchDataPtr + ) +{ + UINT8 UsbModeReg; + UINT8 XhciReg00; + UsbModeReg = 0; + + // Overwrite EHCI3/OHCI3 by Xhci1Enable + ReadMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth8, &XhciReg00); + if (XhciReg00 & BIT0) { + FchDataPtr->Usb.Ohci3Enable = FALSE; + FchDataPtr->Usb.Ehci3Enable = FALSE; + UsbModeReg |= 0x80; + } else { + UsbModeReg &= 0x7F; + } + + if ( FchDataPtr->Usb.Ohci1Enable ) { + UsbModeReg |= 0x01; + } + if ( FchDataPtr->Usb.Ehci1Enable ) { + UsbModeReg |= 0x02; + } + if ( FchDataPtr->Usb.Ohci2Enable ) { + UsbModeReg |= 0x04; + } + if ( FchDataPtr->Usb.Ehci2Enable ) { + UsbModeReg |= 0x08; + } + if ( FchDataPtr->Usb.Ohci3Enable ) { + UsbModeReg |= 0x10; + } + if ( FchDataPtr->Usb.Ehci3Enable ) { + UsbModeReg |= 0x20; + } + if ( FchDataPtr->Usb.Ohci4Enable ) { + UsbModeReg |= 0x40; + } + + RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xEF , AccessWidth8, 0, UsbModeReg); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c new file mode 100644 index 0000000..b1498a4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c @@ -0,0 +1,75 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH USB OHCI controller + * + * Init USB OHCI features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCILATESERVICE_FILECODE +// +// Declaration of local functions +// + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciMidService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciMidService.c new file mode 100644 index 0000000..1fd3035 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciMidService.c @@ -0,0 +1,133 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH USB OHCI controller + * + * Init USB OHCI features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCIMIDSERVICE_FILECODE +// +// Declaration of local functions +// + +/** + * FchOhciInitAfterPciInit - Config USB OHCI controller after + * PCI emulation + * + * @param[in] Value Controller PCI config address (bus# + device# + function#) + * @param[in] FchDataPtr Fch configuration structure pointer. + */ +VOID +FchOhciInitAfterPciInit ( + IN UINT32 Value, + IN FCH_DATA_BLOCK *FchDataPtr + ) +{ + // + // Disable the MSI capability of USB host controllers + // + RwPci ((UINT32) Value + FCH_OHCI_REG40 + 1, AccessWidth8, 0xFF, BIT0, FchDataPtr->StdHeader); + RwPci ((UINT32) Value + 0x50 , AccessWidth8, (UINT32)~(BIT0 + BIT5 + BIT12), 0, FchDataPtr->StdHeader); + // + // USB SMI Handshake + // + RwPci ((UINT32) Value + 0x50 + 1, AccessWidth8, (UINT32)~BIT4, 0x00, FchDataPtr->StdHeader); + + if (Value != (USB4_OHCI_BUS_DEV_FUN << 16)) { + if ( FchDataPtr->Usb.OhciSsid != 0 ) { + RwPci ((UINT32) Value + FCH_OHCI_REG2C, AccessWidth32, 0x00, FchDataPtr->Usb.OhciSsid, FchDataPtr->StdHeader); + } + } + // + // recommended setting to, enable fix to cover the corner case S3 wake up issue from some USB 1.1 devices + //OHCI 0_PCI_Config 0x50[30] = 1 + // + RwPci ((UINT32) Value + 0x50 + 3, AccessWidth8, (UINT32)~BIT6, (UINT32)BIT6, FchDataPtr->StdHeader); + // + // L1 Early Exit + // Set OHCI Arbiter Mode. + // Set Enable Global Clock Gating. + // + RwPci ((UINT32) Value + FCH_OHCI_REG80, AccessWidth8, (UINT32)~(BIT0 + BIT4 + BIT5 + BIT6 + BIT7), (UINT32)(BIT0 + BIT4 + BIT7), FchDataPtr->StdHeader); + RwPci ((UINT32) Value + FCH_OHCI_REG80, AccessWidth16, (UINT32)~(BIT4 + BIT5 + BIT8), (UINT32)(BIT4 + BIT5 + BIT8), FchDataPtr->StdHeader); + // + // Enable OHCI SOF Synchronization. + // Enable OHCI Periodic List Advance. + // + RwPci ((UINT32) Value + 0x50 + 2, AccessWidth8, (UINT32)~(BIT3 + BIT4 + BIT6 + BIT7), (UINT32)(BIT3 + BIT4 + BIT6 + BIT7), FchDataPtr->StdHeader); + if ( FchDataPtr->Usb.UsbMsiEnable) { + RwPci ((UINT32) Value + FCH_OHCI_REG40 + 1, AccessWidth8, (UINT32)~BIT0, 0x00, FchDataPtr->StdHeader); + RwPci ((UINT32) Value + 0x50 , AccessWidth8, (UINT32)~BIT5, (UINT32)BIT5, FchDataPtr->StdHeader); + } + // full-speed false crc errors detected. Issue - fix enable + RwPci ((UINT32) Value + FCH_OHCI_REG80, AccessWidth32, (UINT32) (~(0x01 << 10)), (UINT32) (0x01 << 10), FchDataPtr->StdHeader); + // SB02643 + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGB4, AccessWidth8, (UINT32)~BIT7, (UINT32)BIT7); + // RPR 7.27 SB02686 + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGED, AccessWidth8, (UINT32)~BIT2, (UINT32)BIT2); + // SB02698 + RwPci ((UINT32) Value + 0x50 , AccessWidth8, (UINT32)~BIT0, 0, FchDataPtr->StdHeader); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciEnvService.c new file mode 100644 index 0000000..26f9626 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciEnvService.c @@ -0,0 +1,432 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH USB3 controller + * + * Init USB3 features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 65854 $ @e $Date: 2012-02-26 01:52:07 -0600 (Sun, 26 Feb 2012) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIENVSERVICE_FILECODE + +// +// Declaration of local functions +// + +/** + * FchXhciInitIndirectReg - Config XHCI Indirect Registers + * + * + * + * @param[in] StdHeader AMD Standard Header + * + */ +VOID +FchXhciInitIndirectReg ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 DrivingStrength; + UINT32 Port; + UINT32 Register; + UINT32 RegValue; + UINT8 Index; + DrivingStrength = 0; + Port = 0; + // + // SuperSpeed PHY Configuration (adaptation mode setting) + // + RwXhciIndReg ( FCH_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021, StdHeader); + RwXhciIndReg ( FCH_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021, StdHeader); + // + // SuperSpeed PHY Configuration (CR phase and frequency filter settings) + // + RwXhciIndReg ( FCH_XHCI_IND_REG98, 0xFFFFFFC0, 0x0000000A, StdHeader); + RwXhciIndReg ( FCH_XHCI_IND_REGD8, 0xFFFFFFC0, 0x0000000A, StdHeader); + // + // BLM Meaasge + // + RwXhciIndReg ( FCH_XHCI_IND_REG00, 0xF8FFFFFF, 0x07000000, StdHeader); + // + // xHCI USB 2.0 PHY Settings + // Step 1 is done by hardware default + // Step 2 + for (Port = 0; Port < 4; Port ++) { + DrivingStrength = BIT2; + if (Port < 2) { + RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE1E78, (Port << 13) + DrivingStrength, StdHeader); + RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE1E78, (Port << 13) + BIT8 + BIT7 + DrivingStrength, StdHeader); + RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0E78, (Port << 13) + BIT8 + BIT7 + DrivingStrength, StdHeader); + Register = FCH_XHCI_IND60_REG00; + Index = 0; + do { + WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader); + ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader); + Index++; + FchStall (10, StdHeader); + } while ((RegValue & BIT17) && (Index < 10 )); + RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000, StdHeader); + } else { + RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE1E78, ((Port - 2) << 13) + DrivingStrength, StdHeader); + RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE1E78, ((Port - 2) << 13) + BIT8 + BIT7 + DrivingStrength, StdHeader); + RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0E78, ((Port - 2) << 13) + BIT8 + BIT7 + DrivingStrength, StdHeader); + Register = FCH_XHCI_IND60_REG00; + Index = 0; + do { + WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader); + ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader); + Index++; + FchStall (10, StdHeader); + } while ((RegValue & BIT17) && (Index < 10 )); + RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000, StdHeader); + } + } + + // Step 3 + RwXhciIndReg ( FCH_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8)), StdHeader); + RwXhciIndReg ( FCH_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x0f << 8)), StdHeader); +} + +/** + * XhciA12Fix - Config XHCI A12 Fix + * + * + */ +STATIC +VOID +XhciA12Fix ( + OUT VOID + ) +{ + // + // PLUG/UNPLUG of USB 2.0 devices make the XHCI USB 2.0 ports unfunctional - fix enable + // ACPI_USB3.0_REG 0x20[12:11] = 2'b11 + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x3 << 11)), (UINT32) (0x3 << 11)); + // + // XHC 2 USB2 ports interactional issue - fix enable + // ACPI_USB3.0_REG 0x20[16] = 1'b1 + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x1 << 16)), (UINT32) (0x1 << 16)); + // + // XHC USB2.0 Ports suspend Enhancement + // ACPI_USB3.0_REG 0x20[15] = 1'b1 + // + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x1 << 15)), (UINT32) (0x1 << 15)); + // + // XHC HS/FS IN Data Buffer Underflow issue - fix enable + // ACPI_USB3.0_REG 0x20[20:18] = 0x7 + // + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x7 << 18)), (UINT32) (0x7 << 18)); + // + // XHC stuck in U3 after system resuming from S3 -fix enable + // ACPI_USB3.0_REG 0x98[19] = 1'b1 + // + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG98, AccessWidth32, ~((UINT32) (0x1 << 19)), (UINT32) (0x1 << 19)); + // + // Change XHC1 ( Dev 16 function 1) Interrupt Pin register to INTB# - Fix enable + // ACPI_PMIO_F0[18] =1 + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 18)), (UINT32) (0x1 << 18)); + // + // EHCI3/OHCI3 blocks Blink Global Clock Gating when EHCI/OHCI Dev 22 fn 0/2 are disabled + // ACPI_PMIO_F0[13] =1 + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 13)), (UINT32) (0x1 << 13)); + // + // Access register through JTAG fail when switch from XHCI to EHCI/OHCI - Fix enable + // ACPI_PMIO_F0[17] =1 + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 17)), (UINT32) (0x1 << 17)); + // + // USB leakage current on differential lines when ports are switched to XHCI - Fix enable + // ACPI_PMIO_F0[14] =1 + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 14)), (UINT32) (0x1 << 14)); +} + +/** + * IsLpcRom - Is LPC Rom? + * + * + * @retval TRUE or FALSE + * + */ +BOOLEAN +IsLpcRom ( + OUT VOID + ) +{ + return ( (BOOLEAN) ((ACPIMMIO32 (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80) & BIT1) == 0) ); +} + +/** + * FchXhciInitBeforePciInit - Config XHCI controller before PCI + * emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchXhciInitBeforePciInit ( + IN FCH_DATA_BLOCK *FchDataPtr + ) +{ + UINT16 BcdAddress; + UINT16 BcdSize; + UINT16 AcdAddress; + UINT16 AcdSize; + UINT16 FwAddress; + UINT16 FwSize; + UINTN XhciFwStarting; + UINT32 SpiValidBase; + UINT32 RegData; + UINT16 Index; + BOOLEAN Xhci0Enable; + BOOLEAN Xhci1Enable; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + Xhci0Enable = LocalCfgPtr->Usb.Xhci0Enable; + Xhci1Enable = LocalCfgPtr->Usb.Xhci1Enable; + + if (( Xhci0Enable == 0 ) && (Xhci1Enable == 0)) { + return; + } + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0x00000000, 0x00400700); + FchStall (20, StdHeader); + + if ( LocalCfgPtr->Usb.UserDefineXhciRomAddr == 0 ) { + // + // Get ROM SIG starting address for USB firmware starting address (offset 0x0C to SIG address) + // + GetRomSigPtr (&XhciFwStarting, StdHeader); + + if (XhciFwStarting == 0) { + return; + } + XhciFwStarting = ACPIMMIO32 (XhciFwStarting + FW_TO_SIGADDR_OFFSET); + } else { + XhciFwStarting = ( UINTN ) LocalCfgPtr->Usb.UserDefineXhciRomAddr; + } + if (IsLpcRom ()) { + // + // XHCI firmware re-load + // + RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGCC, AccessWidth32, (UINT32)~BIT2, (UINT32)(BIT2 + BIT1 + BIT0), StdHeader); + RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGCC, AccessWidth32, 0x00000FFF, (UINT32) (XhciFwStarting), StdHeader); + } + + // + // Enable SuperSpeed receive special error case logic. 0x20 bit8 + // Enable USB2.0 RX_Valid Synchronization. 0x20 bit9 + // Enable USB2.0 DIN/SE0 Synchronization. 0x20 bit10 + // + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, 0xFFFFF8FF, 0x00000700); + // + // SuperSpeed PHY Configuration (adaptation timer setting) + // XHC U1 LFPS Exit time + // + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccessWidth32, 0xCFF00000, 0x000AAAAA); + //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90 + 0x40, AccessWidth32, 0xFFF00000, 0x000AAAAA); + + // + // Step 1. to enable Xhci IO and Firmware load mode + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, (UINT32)~(BIT4 + BIT5), 0); /// Disable Device 22 + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, (UINT32)~(BIT7), (UINT32)BIT7); /// Enable 2.0 devices + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0xF0FFFFFC, (Xhci0Enable + (Xhci1Enable << 1)) & 0x03); + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0xEFFFFFFF, 0x10000000); + + // + // Step 2. to read a portion of the USB3_APPLICATION_CODE from BIOS ROM area and program certain registers. + // + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA0, AccessWidth32, 0x00000000, (SPI_HEAD_LENGTH << 16)); + + BcdAddress = ACPIMMIO16 (XhciFwStarting + BCD_ADDR_OFFSET); + BcdSize = ACPIMMIO16 (XhciFwStarting + BCD_SIZE_OFFSET); + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4, AccessWidth16, 0x0000, BcdAddress); + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4 + 2, AccessWidth16, 0x0000, BcdSize); + + AcdAddress = ACPIMMIO16 (XhciFwStarting + ACD_ADDR_OFFSET); + AcdSize = ACPIMMIO16 (XhciFwStarting + ACD_SIZE_OFFSET); + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8, AccessWidth16, 0x0000, AcdAddress); + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8 + 2, AccessWidth16, 0x0000, AcdSize); + + SpiValidBase = SPI_BASE2 (XhciFwStarting + 4) | SPI_BAR0_VLD | SPI_BASE0 | SPI_BAR1_VLD | SPI_BASE1 | SPI_BAR2_VLD; + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB0, AccessWidth32, 0x00000000, SpiValidBase); + // + // Copy Type0/1/2 data block from ROM image to MMIO starting from 0xC0 + // + for (Index = 0; Index < SPI_HEAD_LENGTH; Index++) { + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + Index, AccessWidth8, 0, ACPIMMIO8 (XhciFwStarting + Index)); + } + + for (Index = 0; Index < BcdSize; Index++) { + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + Index, AccessWidth8, 0, ACPIMMIO8 (XhciFwStarting + BcdAddress + Index)); + } + + for (Index = 0; Index < AcdSize; Index++) { + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + BcdSize + Index, AccessWidth8, 0, ACPIMMIO8 (XhciFwStarting + AcdAddress + Index)); + } + + // + // Step 3. to enable the instruction RAM preload functionality. + // + FwAddress = ACPIMMIO16 (XhciFwStarting + FW_ADDR_OFFSET); + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth16, 0x0000, ACPIMMIO16 (XhciFwStarting + FwAddress)); + FwAddress += 2; + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04, AccessWidth16, 0x0000, FwAddress); + + FwSize = ACPIMMIO16 (XhciFwStarting + FW_SIZE_OFFSET); + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04 + 2, AccessWidth16, 0x0000, FwSize); + // + // Set the starting address offset for Instruction RAM preload. + // + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG08, AccessWidth16, 0x0000, 0); + + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, (UINT32)~BIT29, (UINT32)BIT29); + + for (;;) { + ReadMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccessWidth32, &RegData); + if (RegData & BIT30) { + break; + } + } + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, (UINT32)~BIT29, 0); + + // + // Step 4. to release resets in XHCI_ACPI_MMIO_AMD_REG00. wait for USPLL to lock by polling USPLL lock. + // + + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, (UINT32)~U3PLL_RESET, 0); ///Release U3PLLreset + for (;;) { + ReadMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccessWidth32, &RegData); + if (RegData & U3PLL_LOCK) { + break; + } + } + + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, (UINT32)~U3PHY_RESET, 0); ///Release U3PHY + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, (UINT32)~U3CORE_RESET, 0); ///Release core reset + + // + // SuperSpeed PHY Configuration + // + //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccessWidth32, 0xFFF00000, 0x000AAAAA); + //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGD0, AccessWidth32, 0xFFF00000, 0x000AAAAA); + + FchXhciInitIndirectReg (StdHeader); + + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, (UINT32)~(BIT4 + BIT5), 0); /// Disable Device 22 + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, (UINT32)~(BIT7), (UINT32)BIT7); /// Enable 2.0 devices + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, (UINT32)~(BIT21), (UINT32)BIT21); + // + // Step 5. + // + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, (UINT32)~(BIT17 + BIT18 + BIT19), (UINT32)(BIT17 + BIT18)); + + XhciA12Fix (); + + // + // UMI Lane Configuration Information for XHCI Firmware to Calculate the Bandwidth for USB 3.0 ISOC Devices + // + if (!(IsUmiOneLaneGen1Mode (StdHeader))) { + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, (UINT32)~(BIT25 + BIT24), (UINT32)BIT24); + } + // RPR 8.23 FS/LS devices not functional after resume from S4 fix enable (SB02699) + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, (UINT32)~(BIT22), (UINT32)BIT22); + // RPR 8.24 XHC USB2.0 Hub disable issue fix enable (SB02702) + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, (UINT32)~(BIT20), (UINT32)BIT20); +} + +/** + * FchXhciPowerSavingProgram - Config XHCI for Power Saving mode + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchXhciPowerSavingProgram ( + IN FCH_DATA_BLOCK *FchDataPtr + ) +{ + UINT8 XhciEfuse; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + // add Efuse checking for Xhci enable/disable + XhciEfuse = XHCI_EFUSE_LOCATION; + GetEfuseStatus (&XhciEfuse, StdHeader); + if ((XhciEfuse & (BIT0 + BIT1)) != (BIT0 + BIT1)) { + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0xF0FFFBFF, 0x0); + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciLateService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciLateService.c new file mode 100644 index 0000000..664b7ef --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciLateService.c @@ -0,0 +1,158 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH USB3 controller + * + * Init USB3 features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCILATESERVICE_FILECODE + +// +// Declaration of local functions +// + +/** + * FchInitLateUsbXhciProgram - Config USB3 controller before OS + * Boot + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitLateUsbXhciProgram ( + IN VOID *FchDataPtr + ) +{ + UINT8 IndexValue; + UINT8 Value; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + if ( LocalCfgPtr->Usb.Xhci1Enable == TRUE ) { + ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x10, AccessWidth8, &Value, StdHeader); + IndexValue = XHCI_REGISTER_BAR00; + WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader); + + ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x11, AccessWidth8, &Value, StdHeader); + IndexValue = XHCI_REGISTER_BAR01; + WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader); + + ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x12, AccessWidth8, &Value, StdHeader); + IndexValue = XHCI_REGISTER_BAR02; + WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader); + + ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x13, AccessWidth8, &Value, StdHeader); + IndexValue = XHCI_REGISTER_BAR03; + WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader); + + ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x04, AccessWidth8, &Value, StdHeader); + IndexValue = XHCI_REGISTER_04H; + WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader); + + ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x0C, AccessWidth8, &Value, StdHeader); + IndexValue = XHCI_REGISTER_0CH; + WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader); + + ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x3C, AccessWidth8, &Value, StdHeader); + IndexValue = XHCI_REGISTER_3CH; + WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader); + + ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x10, AccessWidth8, &Value, StdHeader); + IndexValue = XHCI1_REGISTER_BAR00; + WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader); + + ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x11, AccessWidth8, &Value, StdHeader); + IndexValue = XHCI1_REGISTER_BAR01; + WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader); + + ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x12, AccessWidth8, &Value, StdHeader); + IndexValue = XHCI1_REGISTER_BAR02; + WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader); + + ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x13, AccessWidth8, &Value, StdHeader); + IndexValue = XHCI1_REGISTER_BAR03; + WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader); + + ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x04, AccessWidth8, &Value, StdHeader); + IndexValue = XHCI1_REGISTER_04H; + WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader); + + ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x0C, AccessWidth8, &Value, StdHeader); + IndexValue = XHCI1_REGISTER_0CH; + WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader); + + ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x3C, AccessWidth8, &Value, StdHeader); + IndexValue = XHCI1_REGISTER_3CH; + WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader); + } + //RPR 8.12 xHCI controller PCI configuration space "Read Only" registers write lock enable + RwXhciIndReg ( FCH_XHCI_IND_REG04, (UINT32)~BIT8, (UINT32)BIT8, StdHeader); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciMidService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciMidService.c new file mode 100644 index 0000000..92b2928 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciMidService.c @@ -0,0 +1,75 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH USB3 controller + * + * Init USB3 features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIMIDSERVICE_FILECODE + +// +// Declaration of local functions +// diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c new file mode 100644 index 0000000..bf5227f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c @@ -0,0 +1,152 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config FCH Xhci controller + * + * Init Xhci Controller features (PEI phase). + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIRESETSERVICE_FILECODE + +/** + * FchInitResetXhciProgram - Config Xhci controller during + * Power-On + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitResetXhciProgram ( + IN VOID *FchDataPtr + ) +{ + UINT8 IndexValue; + UINT32 ValueDword; + UINT8 ValueByte; + FCH_RESET_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + BOOLEAN Xhci0Enable; + BOOLEAN Xhci1Enable; + + LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + Xhci0Enable = LocalCfgPtr->FchReset.Xhci0Enable; + Xhci1Enable = LocalCfgPtr->FchReset.Xhci1Enable; + + if ( Xhci0Enable ) { + ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccessWidth32, &ValueDword, StdHeader); + if ( ValueDword == (FCH_USB_XHCI_DID << 16) + FCH_USB_XHCI_VID) { + // + // First Xhci controller. + // + ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccessWidth32, &ValueDword, StdHeader); + ValueDword = 0; + + IndexValue = XHCI_REGISTER_BAR00; + ReadBiosram (IndexValue, AccessWidth32, &ValueDword, StdHeader); + WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x10, AccessWidth32, &ValueDword, StdHeader); + + IndexValue = XHCI_REGISTER_04H; + ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader); + WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x04, AccessWidth8, &ValueByte, StdHeader); + + IndexValue = XHCI_REGISTER_0CH; + ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader); + WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x0C, AccessWidth8, &ValueByte, StdHeader); + + IndexValue = XHCI_REGISTER_3CH; + ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader); + WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x3C, AccessWidth8, &ValueByte, StdHeader); + // + // Second Xhci controller. + // + ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x00, AccessWidth32, &ValueDword, StdHeader); + ValueDword = 0; + + IndexValue = XHCI1_REGISTER_BAR00; + ReadBiosram (IndexValue, AccessWidth32, &ValueDword, StdHeader); + WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x10, AccessWidth32, &ValueDword, StdHeader); + + IndexValue = XHCI1_REGISTER_04H; + ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader); + WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x04, AccessWidth8, &ValueByte, StdHeader); + + IndexValue = XHCI1_REGISTER_0CH; + ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader); + WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x0C, AccessWidth8, &ValueByte, StdHeader); + + IndexValue = XHCI1_REGISTER_3CH; + ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader); + WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x3C, AccessWidth8, &ValueByte, StdHeader); + } + } else { + RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0x00000000, 0x00400700); + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/OhciEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/OhciEnv.c new file mode 100644 index 0000000..7ad99cb --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/OhciEnv.c @@ -0,0 +1,87 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch USB OHCI controller + * + * Init USB OHCI features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_OHCIENV_FILECODE + +/** + * FchInitEnvUsbOhci - Config USB OHCI controller before PCI + * emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvUsbOhci ( + IN VOID *FchDataPtr + ) +{ +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/OhciLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/OhciLate.c new file mode 100644 index 0000000..b54b624 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/OhciLate.c @@ -0,0 +1,87 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch USB OHCI controller + * + * Init USB OHCI features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_OHCILATE_FILECODE + +/** + * FchInitLateUsbOhci - Config USB OHCI controller before OS + * Boot + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitLateUsbOhci ( + IN VOID *FchDataPtr + ) +{ +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/OhciMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/OhciMid.c new file mode 100644 index 0000000..71b203b --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/OhciMid.c @@ -0,0 +1,241 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch USB OHCI controller + * + * Init USB OHCI features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_OHCIMID_FILECODE +// +// Declaration of local functions +// + +/* extern VOID FchOhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr); */ +/** + * OhciInitAfterPciInit - Config USB OHCI controller after PCI emulation + * + * @param[in] Value Controller PCI config address (bus# + device# + function#) + * @param[in] FchDataPtr Fch configuration structure pointer. + */ +VOID OhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr); + +/** + * FchInitMidUsbOhci - Config USB OHCI controller after PCI + * emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidUsbOhci ( + IN VOID *FchDataPtr + ) +{ + FCH_INTERFACE *LocalCfgPtr; + + LocalCfgPtr = (FCH_INTERFACE *)FchDataPtr; + + FchInitMidUsbOhci1 (LocalCfgPtr); + FchInitMidUsbOhci2 (LocalCfgPtr); + FchInitMidUsbOhci3 (LocalCfgPtr); + FchInitMidUsbOhci4 (LocalCfgPtr); +} + +/** + * FchInitMidUsbOhci1 - Config USB1 OHCI controller after PCI + * emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidUsbOhci1 ( + IN VOID *FchDataPtr + ) +{ + UINT32 DeviceId; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + DeviceId = (USB1_OHCI_BUS_DEV_FUN << 16); + OhciInitAfterPciInit (DeviceId, LocalCfgPtr); + + if (LocalCfgPtr->Usb.OhciSsid != 0 ) { + RwPci ((USB1_OHCI_BUS_DEV_FUN << 16) + FCH_OHCI_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Usb.OhciSsid, StdHeader); + } +} + +/** + * FchInitMidUsbOhci2 - Config USB2 OHCI controller after PCI + * emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidUsbOhci2 ( + IN VOID *FchDataPtr + ) +{ + UINT32 DeviceId; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + DeviceId = (USB2_OHCI_BUS_DEV_FUN << 16); + OhciInitAfterPciInit (DeviceId, LocalCfgPtr); + + if (LocalCfgPtr->Usb.OhciSsid != 0 ) { + RwPci ((USB2_OHCI_BUS_DEV_FUN << 16) + FCH_OHCI_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Usb.OhciSsid, StdHeader); + } +} + +/** + * FchInitMidUsbOhci3 - Config USB3 OHCI controller after PCI + * emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidUsbOhci3 ( + IN VOID *FchDataPtr + ) +{ + UINT32 DeviceId; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + DeviceId = (USB3_OHCI_BUS_DEV_FUN << 16); + OhciInitAfterPciInit (DeviceId, LocalCfgPtr); + + if (LocalCfgPtr->Usb.OhciSsid != 0 ) { + RwPci ((USB3_OHCI_BUS_DEV_FUN << 16) + FCH_OHCI_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Usb.OhciSsid, StdHeader); + } +} + +/** + * FchInitMidUsbOhci4 - Config USB4 OHCI controller after PCI + * emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidUsbOhci4 ( + IN VOID *FchDataPtr + ) +{ + UINT32 DeviceId; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + DeviceId = (USB4_OHCI_BUS_DEV_FUN << 16); + OhciInitAfterPciInit (DeviceId, LocalCfgPtr); + + if (LocalCfgPtr->Usb.OhciSsid != 0 ) { + RwPci ((USB4_OHCI_BUS_DEV_FUN << 16) + FCH_OHCI_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Usb.OhciSsid, StdHeader); + } +} + +/** + * OhciInitAfterPciInit - Config OHCI controller after PCI + * emulation + * + * + * @param[in] Value OHCI Controler info. + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +OhciInitAfterPciInit ( + IN UINT32 Value, + IN FCH_DATA_BLOCK *FchDataPtr + ) +{ + FchOhciInitAfterPciInit ( Value, FchDataPtr); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/OhciReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/OhciReset.c new file mode 100644 index 0000000..ba6baab --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/OhciReset.c @@ -0,0 +1,89 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Ohci controller + * + * Init Ohci Controller features (PEI phase). + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_OHCIRESET_FILECODE + +/** + * FchInitResetOhci - Config Ohci controller during Power-On + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitResetOhci ( + IN VOID *FchDataPtr + ) +{ +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbEnv.c new file mode 100644 index 0000000..09fca7d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbEnv.c @@ -0,0 +1,101 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch USB controller + * + * Init USB features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_USBENV_FILECODE + +/* extern VOID FchSetUsbEnableReg (IN FCH_DATA_BLOCK *FchDataPtr); */ + +/** + * FchInitEnvUsb - Config USB controller before PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvUsb ( + IN VOID *FchDataPtr + ) +{ + // + // Disabled All USB controller *** Move to each controller *** + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, BIT7, 0); + // + // Clear PM_IO 0x65[4] UsbResetByPciRstEnable, Set this bit so that usb gets reset whenever there is PCIRST. + // USB SleepCtrl set as BIT9+BIT8 (6 uframes) + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xF0 , AccessWidth16, (UINT32)~BIT2, (UINT32)(BIT2 + BIT7 + BIT8 + BIT9)); + + FchSetUsbEnableReg (FchDataPtr); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEE, AccessWidth8, (UINT32)~(BIT2), 0 ); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbLate.c new file mode 100644 index 0000000..5702bdd --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbLate.c @@ -0,0 +1,88 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch USB controller + * + * Init USB features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_USBLATE_FILECODE + +/** + * FchInitLateUsb - Config USB controller before OS Boot + * emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitLateUsb ( + IN VOID *FchDataPtr + ) +{ +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbMid.c new file mode 100644 index 0000000..764ad6e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbMid.c @@ -0,0 +1,95 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch USB controller + * + * Init USB features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_USBMID_FILECODE + +/** + * FchInitMidUsb - Config USB controller after PCI emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidUsb ( + IN VOID *FchDataPtr + ) +{ + FCH_DATA_BLOCK *LocalCfgPtr; + + LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; + if ( LocalCfgPtr->Usb.UsbPhyPowerDown ) { + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth8, (UINT32)~BIT0, (UINT32)BIT0); + } else { + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth8, (UINT32)~BIT0, 0); + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbReset.c new file mode 100644 index 0000000..d4d4461 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/UsbReset.c @@ -0,0 +1,89 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Usb controller + * + * Init Usb Controller features (PEI phase). + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_USBRESET_FILECODE + +/** + * FchInitResetUsb - Config Usb controller during Power-On + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitResetUsb ( + IN VOID *FchDataPtr + ) +{ +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciEnv.c new file mode 100644 index 0000000..9116e67 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciEnv.c @@ -0,0 +1,147 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch USB3 controller + * + * Init USB3 features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_XHCIENV_FILECODE + +/* extern VOID FchXhciInitBeforePciInit (IN FCH_DATA_BLOCK* FchDataPtr); */ +/* extern VOID FchXhciInitIndirectReg (IN AMD_CONFIG_PARAMS *StdHeader); */ +/* extern VOID FchXhciPowerSavingProgram (IN FCH_DATA_BLOCK* FchDataPtr); */ +// +// Declaration of local functions +// +VOID XhciInitBeforePciInit (IN FCH_DATA_BLOCK* FchDataPtr); +VOID XhciInitIndirectReg (IN AMD_CONFIG_PARAMS *StdHeader); + +/** + * FchInitEnvUsbXhci - Config XHCI controller before PCI + * emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitEnvUsbXhci ( + IN VOID *FchDataPtr + ) +{ + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + if ( LocalCfgPtr->Usb.Xhci0Enable == TRUE ) { + if ( LocalCfgPtr->Misc.S3Resume == 0 ) { + XhciInitBeforePciInit (LocalCfgPtr); + } else { + XhciInitIndirectReg (StdHeader); + } + } else { + // + // for power saving. + // + FchXhciPowerSavingProgram (LocalCfgPtr); + } +} + +/** + * XhciInitIndirectReg - Config XHCI Indirect Registers + * + * + * + * @param[in] StdHeader AMD Standard Header + * + */ +VOID +XhciInitIndirectReg ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + FchXhciInitIndirectReg (StdHeader); +} + +/** + * XhciInitBeforePciInit - Config XHCI controller before PCI + * emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +XhciInitBeforePciInit ( + IN FCH_DATA_BLOCK *FchDataPtr + ) +{ + FchXhciInitBeforePciInit ( FchDataPtr ); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciLate.c new file mode 100644 index 0000000..bd9ef1b --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciLate.c @@ -0,0 +1,90 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch USB3 controller + * + * Init USB3 features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_XHCILATE_FILECODE + +/* extern VOID FchInitLateUsbXhciProgram (IN VOID *FchDataPtr); */ + +/** + * FchInitLateUsbXhci - Config USB3 controller before OS Boot + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitLateUsbXhci ( + IN VOID *FchDataPtr + ) +{ + FchInitLateUsbXhciProgram ( FchDataPtr ); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciMid.c new file mode 100644 index 0000000..e8dd235 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciMid.c @@ -0,0 +1,107 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch USB3 controller + * + * Init USB3 features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/*;******************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;*********************************************************************************/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_XHCIMID_FILECODE + +/** + * FchInitMidUsbXhci - Config USB3 controller after PCI + * emulation + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitMidUsbXhci ( + IN VOID *FchDataPtr + ) +{ + FCH_DATA_BLOCK *LocalCfgPtr; + + LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr; + if ( LocalCfgPtr->Usb.Xhci0Enable == TRUE ) { + RwPci ((USB_XHCI_BUS_DEV_FUN << 16) + FCH_XHCI_REG04, AccessWidth8, 0, BIT1, ((FCH_DATA_BLOCK *)FchDataPtr)->StdHeader); + if (((FCH_DATA_BLOCK *)FchDataPtr)->Usb.XhciSsid != 0 ) { + RwPci ((USB_XHCI_BUS_DEV_FUN << 16) + FCH_XHCI_REG2C, AccessWidth32, 0x00, ((FCH_DATA_BLOCK *)FchDataPtr)->Usb.XhciSsid, ((FCH_DATA_BLOCK *)FchDataPtr)->StdHeader); + } + } + + if ( LocalCfgPtr->Usb.Xhci1Enable == TRUE ) { + RwPci ((USB_XHCI1_BUS_DEV_FUN << 16) + FCH_XHCI_REG04, AccessWidth8, 0, BIT1, ((FCH_DATA_BLOCK *)FchDataPtr)->StdHeader); + if (((FCH_DATA_BLOCK *)FchDataPtr)->Usb.XhciSsid != 0 ) { + RwPci ((USB_XHCI1_BUS_DEV_FUN << 16) + FCH_XHCI_REG2C, AccessWidth32, 0x00, ((FCH_DATA_BLOCK *)FchDataPtr)->Usb.XhciSsid, ((FCH_DATA_BLOCK *)FchDataPtr)->StdHeader); + } + // + // Block Write to DID & SID to pass DTM + // + RwXhciIndReg (FCH_XHCI_IND_REG04, (UINT32)~BIT8, (UINT32)BIT8, ((FCH_DATA_BLOCK *)FchDataPtr)->StdHeader); + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciRecovery.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciRecovery.c new file mode 100644 index 0000000..82ea9b7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciRecovery.c @@ -0,0 +1,75 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Xhci controller + * + * Init Xhci Controller features (PEI phase). + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_XHCIRECOVERY_FILECODE + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciReset.c new file mode 100644 index 0000000..f2438af --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Usb/XhciReset.c @@ -0,0 +1,102 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Config Fch Xhci controller + * + * Init Xhci Controller features (PEI phase). + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +**************************************************************************** +*/ +#include "FchPlatform.h" +#include "Filecode.h" +#define FILECODE PROC_FCH_USB_XHCIRESET_FILECODE + + + +/** + * FchInitResetXhci - Config Xhci controller during Power-On + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +FchInitResetXhci ( + IN VOID *FchDataPtr + ) +{ + FchInitResetXhciProgram ( FchDataPtr ); +} + +/** + * FchInitRecoveryLpc - Config Xhci controller during Crisis + * Recovery + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/Gnb.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/Gnb.h new file mode 100644 index 0000000..32bfc95 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/Gnb.h @@ -0,0 +1,194 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Misc common definition + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNB_H_ +#define _GNB_H_ + +#pragma pack (push, 1) + +#define GNB_DEADLOOP() \ +{ \ + VOLATILE BOOLEAN k; \ + k = TRUE; \ + while (k) { \ + } \ +} +#ifdef IDSOPT_TRACING_ENABLED + #if (IDSOPT_TRACING_ENABLED == TRUE) + #define GNB_TRACE_ENABLE + #endif +#endif + + +#ifndef GNB_DEBUG_CODE + #ifdef GNB_TRACE_ENABLE + #define GNB_DEBUG_CODE(Code) Code + #else + #define GNB_DEBUG_CODE(Code) + #endif +#endif + +#ifndef MIN + #define MIN(x, y) (((x) > (y))? (y):(x)) +#endif + +#ifndef MAX + #define MAX(x, y) (((x) > (y))? (x):(y)) +#endif + +#define OFF 0 + +#define PVOID UINT64 + +#define STRING_TO_UINT32(a, b, c, d) ((UINT32) ((d << 24) | (c << 16) | (b << 8) | a)) + +#define GnbLibGetHeader(x) ((AMD_CONFIG_PARAMS*) (x)->StdHeader) + +#define AGESA_STATUS_UPDATE(Current, Aggregated) \ +if (Current > Aggregated) { \ + Aggregated = Current; \ +} + +#ifndef offsetof + #define offsetof(s, m) (UINTN)&(((s *)0)->m) +#endif + + +//Table properties + +#define TABLE_PROPERTY_DEAFULT 0x00000000ul +#define TABLE_PROPERTY_IGFX_DISABLED 0x00000001ul +#define TABLE_PROPERTY_IOMMU_DISABLED 0x00000002ul +#define TABLE_PROPERTY_LCLK_DEEP_SLEEP 0x00000004ul +#define TABLE_PROPERTY_ORB_CLK_GATING 0x00000008ul +#define TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING 0x00000010ul +#define TABLE_PROPERTY_IOC_SCLK_CLOCK_GATING 0x00000020ul +#define TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING 0x00000040ul +#define TABLE_PROPERTY_IOMMU_L2_CLOCK_GATING 0x00000080ul +#define TABLE_PROPERTY_BAPM 0x00000100ul +#define TABLE_PROPERTY_SECONDARY_GNB 0x00000200ul +#define TABLE_PROPERTY_NMI_SYNCFLOOD 0x00000400ul +#define TABLE_PROPERTY_NBDPM 0x00000800ul +#define TABLE_PROPERTY_LOADLINE_ENABLE 0x00001000ul +#define TABLE_PROPERTY_SMU_SCLK_CLOCK_GATING 0x00002000ul + +//Register access flags Flags +#define GNB_REG_ACC_FLAG_S3SAVE 0x00000001ul + +/// LCLK DPM enable control +typedef enum { + LclkDpmDisabled, ///<LCLK DPM disabled + LclkDpmRcActivity, ///<LCLK DPM enabled and use Root Complex Activity monitor method +} LCLK_DPM_MODE; + + +/// Power gaiter data setting (do not change this structure definition) +typedef struct { + UINT16 pwrdata0 ; + UINT16 pwrdata1 ; + UINT16 pwrdata2 ; + UINT16 pwrdata3 ; + UINT16 ResetTimer; ///< Reset Timer + UINT16 IsoTimer; ///< Isolation Timer +} POWER_GATE_DATA; + + +/// Topology information +typedef struct { + BOOLEAN PhantomFunction; ///< PCIe topology have device with phantom function + BOOLEAN PcieToPciexBridge; ///< PCIe topology have device with Pcieto Pcix bridge +} GNB_TOPOLOGY_INFO; + + +/// GNB installable services +typedef enum { + GnbPcieFamConfigService, ///< PCIe config service + GnbPcieFamInitService, ///< PCIe Init service + GnbPcieFamDebugService, ///< PCIe Debug service + GnbRegisterAccessService, ///< GNB register access service + GnbIommuService ///< GNB IOMMU config service +} GNB_SERVICE_ID; + +/// GNB service entry +typedef struct _GNB_SERVICE { + GNB_SERVICE_ID ServiceId; ///< Service ID + UINT64 Family; ///< CPU family + VOID *ServiceProtocol; ///< Service protocol + struct _GNB_SERVICE *NextService; ///< Pointer to next service +} GNB_SERVICE; + +#define GNB_STRINGIZE(x) #x +#define GNB_SERVICE_DEFINITIONS(x) GNB_STRINGIZE (Services/x/x.h) +#define GNB_MODULE_DEFINITIONS(x) GNB_STRINGIZE (Modules/x/x.h) +#define GNB_MODULE_INSTALL(x) GNB_STRINGIZE (Modules/x/x##Install.h) +#pragma pack (pop) + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbFamServices.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbFamServices.h new file mode 100644 index 0000000..3a54cf9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbFamServices.h @@ -0,0 +1,147 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe family specific services. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBFAMSERVICES_H_ +#define _GNBFAMSERVICES_H_ + +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbIommu.h" + +typedef AGESA_STATUS (F_GNB_REGISTER_ACCESS) ( + IN GNB_HANDLE *GnbHandle, + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + IN VOID *Value, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader +); + +/// Register Read/Write protocol +typedef struct { + F_GNB_REGISTER_ACCESS *Read; ///< Read Register + F_GNB_REGISTER_ACCESS *Write; ///< Write Register +} GNB_REGISTER_SERVICE; + +AGESA_STATUS +GnbFmCreateIvrsEntry ( + IN GNB_HANDLE *GnbHandle, + IN IVRS_BLOCK_TYPE Type, + IN VOID *Ivrs, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef AGESA_STATUS F_GNBFMCREATEIVRSENTRY ( + IN GNB_HANDLE *GnbHandle, + IN IVRS_BLOCK_TYPE Type, + IN VOID *Ivrs, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GnbFmCheckIommuPresent ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef BOOLEAN F_GNBFMCHECKIOMMUPRESENT ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// GNB IOMMU services +typedef struct { + F_GNBFMCHECKIOMMUPRESENT *GnbFmCheckIommuPresent; ///< GnbFmCheckIommuPresent + F_GNBFMCREATEIVRSENTRY *GnbFmCreateIvrsEntry; ///< GnbFmCreateIvrsEntry +} GNB_FAM_IOMMU_SERVICES; + + +PCI_ADDR +GnbFmGetPciAddress ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbFmGetBusDecodeRange ( + IN GNB_HANDLE *GnbHandle, + OUT UINT8 *StartBusNumber, + OUT UINT8 *EndBusNumber, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbFmGetLinkId ( + IN GNB_HANDLE *GnbHandle, + OUT UINT8 *LinkId, + IN AMD_CONFIG_PARAMS *StdHeader + ); +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbFuseTable.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbFuseTable.h new file mode 100644 index 0000000..02c38d6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbFuseTable.h @@ -0,0 +1,118 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Graphics controller BIF straps control services. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + +#ifndef _GNBFUSETABLE_H_ +#define _GNBFUSETABLE_H_ + +#pragma pack (push, 1) + +#define PP_FUSE_MAX_NUM_DPM_STATE 5 +#define PP_FUSE_MAX_NUM_SW_STATE 6 + +/// Fuse definition structure +typedef struct { + UINT8 PPlayTableRev; ///< PP table revision + UINT8 SclkDpmValid[6]; ///< Valid DPM states + UINT8 SclkDpmDid[6]; ///< Sclk DPM DID + UINT8 SclkDpmVid[6]; ///< Sclk DPM VID + UINT8 SclkDpmCac[5]; ///< Sclk DPM Cac + UINT8 PolicyFlags[6]; ///< State policy flags + UINT8 PolicyLabel[6]; ///< State policy label + UINT8 VclkDid[4]; ///< VCLK DID + UINT8 DclkDid[4]; ///< DCLK DID + UINT8 SclkThermDid; ///< Thermal SCLK + UINT8 VclkDclkSel[6]; ///< Vclk/Dclk selector + UINT8 LclkDpmValid[4]; ///< Valid Lclk DPM states + UINT8 LclkDpmDid[4]; ///< Lclk DPM DID + UINT8 LclkDpmVid[4]; ///< Lclk DPM VID + UINT8 DisplclkDid[4]; ///< Displclk DID + UINT8 PcieGen2Vid; ///< Pcie Gen 2 VID + UINT8 MainPllId; ///< Main PLL Id from fuses + UINT8 WrCkDid; ///< WRCK SMU clock Divisor + UINT8 SclkVid[4]; ///< Sclk VID + UINT8 GpuBoostCap; ///< GPU boost cap + UINT16 SclkDpmTdpLimit[6]; ///< Sclk DPM TDP limit + UINT16 SclkDpmTdpLimitPG; ///< TDP limit PG + UINT32 SclkDpmBoostMargin; ///< Boost margin + UINT32 SclkDpmThrottleMargin; ///< Throttle margin + BOOLEAN VceSateTableSupport; ///< Support VCE in PP table + UINT8 VceFlags[4]; ///< VCE Flags + UINT8 VceMclk[4]; ///< MCLK for VCE + UINT8 VceReqSclkSel[4]; ///< SCLK selector for VCE + UINT8 EclkDid[4]; ///< Eclk DID +} PP_FUSE_ARRAY; + +#pragma pack (pop) + +#endif + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbGfx.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbGfx.h new file mode 100644 index 0000000..1c8eab0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbGfx.h @@ -0,0 +1,472 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize GFX configuration data structure. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 64730 $ @e $Date: 2012-01-30 02:05:39 -0600 (Mon, 30 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _GNBGFX_H_ +#define _GNBGFX_H_ + +//#ifndef PVOID +// typedef UINT64 PVOID; +//#endif + +#define DEVICE_DFP 0x1 +#define DEVICE_CRT 0x2 +#define DEVICE_LCD 0x3 + + +#define CONNECTOR_DISPLAYPORT_ENUM 0x3013 +#define CONNECTOR_HDMI_TYPE_A_ENUM 0x300c +#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM 0x3003 +#define CONNECTOR_DUAL_LINK_DVI_D_ENUM 0x3004 +#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM 0x3001 +#define CONNECTOR_DUAL_LINK_DVI_I_ENUM 0x3002 +#define CONNECTOR_VGA_ENUM 0x3005 +#define CONNECTOR_LVDS_ENUM 0x300E +#define CONNECTOR_eDP_ENUM 0x3014 +#define CONNECTOR_LVDS_eDP_ENUM 0x3016 +#define ENCODER_TRAVIS_ENUM_ID1 0x2123 +#define ENCODER_TRAVIS_ENUM_ID2 0x2223 +#define ENCODER_ALMOND_ENUM_ID1 0x2122 +#define ENCODER_NOT_PRESENT 0x0000 + +// no eDP->LVDS translator chip +#define eDP_TO_LVDS_RX_DISABLE 0x00 +// common eDP->LVDS translator chip without AMD SW init +#define eDP_TO_LVDS_COMMON_ID 0x01 +// Realtek tansaltor which require AMD SW init +#define eDP_TO_LVDS_REALTEK_ID 0x02 + + +#define ATOM_DEVICE_CRT1_SUPPORT 0x0001 +#define ATOM_DEVICE_DFP1_SUPPORT 0x0008 +#define ATOM_DEVICE_DFP6_SUPPORT 0x0040 +#define ATOM_DEVICE_DFP2_SUPPORT 0x0080 +#define ATOM_DEVICE_DFP3_SUPPORT 0x0200 +#define ATOM_DEVICE_DFP4_SUPPORT 0x0400 +#define ATOM_DEVICE_DFP5_SUPPORT 0x0800 +#define ATOM_DEVICE_LCD1_SUPPORT 0x0002 + +/// Graphics card information structure +typedef struct { + UINT32 AmdPcieGfxCardBitmap; ///< AMD PCIE graphics card information + UINT32 PcieGfxCardBitmap; ///< All PCIE graphics card information + UINT32 PciGfxCardBitmap; ///< All PCI graphics card information +} GFX_CARD_CARD_INFO; + +typedef enum { + iGpuVgaAdapter, ///< Configure iGPU as VGA adapter + iGpuVgaNonAdapter ///< Configure iGPU as non VGA adapter +} GFX_IGPU_VGA_MODE; + +typedef enum { + excel992, + excel993 +} UMA_STEERING; + +/// User Options +typedef enum { + OptionDisabled, ///< Disabled + OptionEnabled ///< Enabled +} CONTROL_OPTION; + +/// GFX enable Policy +typedef enum { + GmcPowerGatingDisabled, ///< Disable Power gating + GmcPowerGatingStutterOnly, ///< GMC Stutter Only mode + GmcPowerGatingWidthStutter ///< GMC Power gating with Stutter mode +} GMC_POWER_GATING; + +/// Internal GFX mode +typedef enum { + GfxControllerLegacyBridgeMode, ///< APC bridge Legacy mode + GfxControllerPcieEndpointMode, ///< IGFX PCIE Bus 0, Device 1 +} GFX_CONTROLLER_MODE; + +/// Graphics Platform Configuration +typedef struct { + UINT32 StdHeader; ///< Standard Header TODO: Used to be PVOID + PCI_ADDR GfxPciAddress; ///< Graphics PCI Address + UMA_INFO UmaInfo; ///< UMA Information + UINT32 GmmBase; ///< GMM Base + UINT8 GnbHdAudio; ///< Control GFX HD Audio controller(Used for HDMI and DP display output), + ///< essentially it enables function 1 of graphics device. + ///< @li 0 = HD Audio disable + ///< @li 1 = HD Audio enable + UINT8 AbmSupport; ///< Automatic adjust LVDS/eDP Back light level support.It is + ///< characteristic specific to display panel which used by platform design. + ///< @li 0 = ABM support disabled + ///< @li 1 = ABM support enabled + UINT8 DynamicRefreshRate; ///< Adjust refresh rate on LVDS/eDP. + UINT16 LcdBackLightControl; ///< The PWM frequency to LCD backlight control. + ///< If equal to 0 backlight not controlled by iGPU. + UINT32 AmdPlatformType; ///< Platform type + UMA_STEERING UmaSteering; ///< UMA Steering + GFX_IGPU_VGA_MODE iGpuVgaMode; ///< iGPU VGA mode + BOOLEAN GmcClockGating; ///< Clock gating + BOOLEAN GmcLockRegisters; ///< GmcLock Registers + BOOLEAN GfxFusedOff; ///< Record if GFX is fused off. + GMC_POWER_GATING GmcPowerGating; ///< Gmc Power Gating. + UINT8 Gnb3dStereoPinIndex; ///< 3D Stereo Pin ID + GFX_CONTROLLER_MODE GfxControllerMode; ///< Gfx controller mode + UINT16 LvdsSpreadSpectrum; ///< Spread spectrum value in 0.01 % + UINT16 LvdsSpreadSpectrumRate; ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz + UINT8 LvdsPowerOnSeqDigonToDe; ///< Panel initialization timing. + UINT8 LvdsPowerOnSeqDeToVaryBl; ///< Panel initialization timing. + UINT8 LvdsPowerOnSeqDeToDigon; ///< Panel initialization timing. + UINT8 LvdsPowerOnSeqVaryBlToDe; ///< Panel initialization timing. + UINT8 LvdsPowerOnSeqOnToOffDelay; ///< Panel initialization timing. + UINT8 LvdsPowerOnSeqVaryBlToBlon; ///< Panel initialization timing. + UINT8 LvdsPowerOnSeqBlonToVaryBl; ///< Panel initialization timing. + UINT16 LvdsMaxPixelClockFreq; ///< The maximum pixel clock frequency supported. + UINT32 LcdBitDepthControlValue; ///< The LCD bit depth control settings. + UINT8 Lvds24bbpPanelMode; ///< The LVDS 24 BBP mode. + LVDS_MISC_CONTROL LvdsMiscControl; ///< THe LVDS swap/Hsync/Vsync/BLON/Volt-overwrite control + GFX_CARD_CARD_INFO GfxDiscreteCardInfo; ///< Discrete GFX card info + UINT16 PcieRefClkSpreadSpectrum; ///< Spread spectrum value in 0.01 % + BOOLEAN GnbRemoteDisplaySupport; ///< Wireless Display Enable + UINT8 gfxplmcfg0 ; + DISPLAY_MISC_CONTROL DisplayMiscControl; ///< The Display misc control +} GFX_PLATFORM_CONFIG; + + +typedef UINT32 ULONG; +typedef UINT16 USHORT; +typedef UINT8 UCHAR; + +/// Driver interface header structure +typedef struct _ATOM_COMMON_TABLE_HEADER { + USHORT usStructureSize; ///< Structure size + UCHAR ucTableFormatRevision; ///< Format revision number + UCHAR ucTableContentRevision; ///< Contents revision number +} ATOM_COMMON_TABLE_HEADER; + +/// Link ping mapping for DP/eDP/LVDS +typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING { + UCHAR ucDP_Lane0_Source :2; ///< Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 + UCHAR ucDP_Lane1_Source :2; ///< Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 + UCHAR ucDP_Lane2_Source :2; ///< Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 + UCHAR ucDP_Lane3_Source :2; ///< Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 +} ATOM_DP_CONN_CHANNEL_MAPPING; + +/// Link ping mapping for DVI/HDMI +typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING { + UCHAR ucDVI_DATA2_Source :2; ///< Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 + UCHAR ucDVI_DATA1_Source :2; ///< Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 + UCHAR ucDVI_DATA0_Source :2; ///< Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 + UCHAR ucDVI_CLK_Source :2; ///< Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 +} ATOM_DVI_CONN_CHANNEL_MAPPING; + + +/// External Display Path +typedef struct _EXT_DISPLAY_PATH { + USHORT usDeviceTag; ///< A bit vector to show what devices are supported + USHORT usDeviceACPIEnum; ///< 16bit device ACPI id. + USHORT usDeviceConnector; ///< A physical connector for displays to plug in, using object connector definitions + UCHAR ucExtAUXDDCLutIndex; ///< An index into external AUX/DDC channel LUT + UCHAR ucExtHPDPINLutIndex; ///< An index into external HPD pin LUT + USHORT usExtEncoderObjId; ///< external encoder object id + union { ///< Lane mapping + UCHAR ucChannelMapping; ///< lane mapping on connector (ucChannelMapping=0 use default) + ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping; ///< lane mapping on connector (ucChannelMapping=0 use default) + ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping; ///< lane mapping on connector (ucChannelMapping=0 use default) + } ChannelMapping; + UCHAR ucChPNInvert; ///< Bit vector for up to 8 lanes. 0: P and N is not invert, 1: P and N is inverted + USHORT usCaps; ///< Capabilities IF BIT[0] == 1, downgrade phy link to DP1.1 + USHORT usReserved; ///< Reserved +} EXT_DISPLAY_PATH; + +/// External Display Connection Information +typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO { + ATOM_COMMON_TABLE_HEADER sHeader; ///< Standard Header + UCHAR ucGuid [16]; ///< Guid + EXT_DISPLAY_PATH sPath[7]; ///< External Display Path + UCHAR ucChecksum; ///< Checksum + UCHAR uc3DStereoPinId; ///< 3D Stereo Pin ID + UCHAR ucRemoteDisplayConfig; ///< Bit0=1:Enable Wireless Display through APU VCE HW function + UCHAR uceDPToLVDSRxId; ///< 3rd party eDP to LVDS translator chip presented. 0:no, 1:chip without AMD SW init, 2:Realtek tansaltor which require AMD SW init + UCHAR Reserved [4]; ///< Reserved +} ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; + +/// Displclk to VID relation table +typedef struct _ATOM_CLK_VOLT_CAPABILITY { + ULONG ulVoltageIndex; ///< The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table + ULONG ulMaximumSupportedCLK;///< Maximum clock supported with specified voltage index, unit in 10kHz +} ATOM_CLK_VOLT_CAPABILITY; + +/// Available Sclk table +typedef struct _ATOM_AVAILABLE_SCLK_LIST { + ULONG ulSupportedSCLK; ///< Maximum clock supported with specified voltage index, unit in 10kHz + USHORT usVoltageIndex; ///< The Voltage Index indicated by FUSE for specified SCLK + USHORT usVoltageID; ///< The Voltage ID indicated by FUSE for specified SCLK +} ATOM_AVAILABLE_SCLK_LIST; + +/// Integrate System Info Table is used for Llano/Ontario APU +typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 { + ATOM_COMMON_TABLE_HEADER sHeader; ///< Standard Header + ULONG ulBootUpEngineClock; ///< VBIOS bootup Engine clock frequency, in 10kHz unit. + ULONG excel994; + ULONG ulBootUpUMAClock; ///< System memory boot up clock frequency in 10Khz unit. + ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; ///< Report Display clock voltage requirement. + ULONG ulBootUpReqDisplayVector; /**< VBIOS boot up display IDs, following are supported devices in Llano/Fam 12 and Ontario/Fam 14 projects: + * ATOM_DEVICE_CRT1_SUPPORT 0x0001 + * ATOM_DEVICE_CRT2_SUPPORT 0x0010 + * ATOM_DEVICE_DFP1_SUPPORT 0x0008 + * ATOM_DEVICE_DFP6_SUPPORT 0x0040 + * ATOM_DEVICE_DFP2_SUPPORT 0x0080 + * ATOM_DEVICE_DFP3_SUPPORT 0x0200 + * ATOM_DEVICE_DFP4_SUPPORT 0x0400 + * ATOM_DEVICE_DFP5_SUPPORT 0x0800 + * ATOM_DEVICE_LCD1_SUPPORT 0x0002 + */ + ULONG ulOtherDisplayMisc; ///< Other display related flags, not defined yet. + ULONG ulGPUCapInfo; /**> @li BIT[0] - TMDS/HDMI Coherent Mode 0: use cascade PLL mode, 1: use signel PLL mode. + * @li BIT[1] - DP mode 0: use cascade PLL mode, 1: use single PLL mode + * @li BIT[3] - AUX HW mode detection logic 0: Enable, 1: Disable + */ + ULONG ulSB_MMIO_Base_Addr; ///< Physical Base address to SB MMIO space. Driver need to initialize it for SMU usage. + USHORT usRequestedPWMFreqInHz; ///< Panel Required PWM frequency. if this parameter is 0 PWM from to control LCD Backlight will be disabled. + UCHAR ucHtcTmpLmt; ///< HTC temperature limit.The processor enters HTC-active state when Tctl reaches or exceeds HtcHystLmt. + UCHAR ucHtcHystLmt; ///< HTC hysteresis.The processor exits HTC-active state when Tctl is less than HtcTmpLmt minus HtcHystLmt. + ULONG ulMinEngineClock; ///< Min SCLK + ULONG ulSystemConfig; /**< System configuration + * @li BIT[0] - 0: PCIE Power Gating Disabled, 1: PCIE Power Gating Enabled. + * @li BIT[1] - 0: DDR-DLL shut-down feature disabled, 1: DDR-DLL shut-down feature enabled. + * @li BIT[2] - 0: DDR-PLL Power down feature disabled, 1: DDR-PLL Power down feature enabled. + */ + ULONG ulCPUCapInfo; ///< TBD + USHORT usNBP0Voltage; ///< VID for voltage on NB P0 State + USHORT usNBP1Voltage; ///< VID for voltage on NB P1 State + USHORT usBootUpNBVoltage; ///< Voltage Index of GNB voltage configured by SBIOS, which is sufficient to support VBIOS DISPCLK requirement. + USHORT usExtDispConnInfoOffset; ///< Offset to sExtDispConnInfo inside the structure + USHORT usPanelRefreshRateRange; /**< Bit vector for LVDS/eDP supported refresh rate range. If DRR is enabled, 2 of the bits must be set. + * SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 + * SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 + * SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 + * SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 + */ + UCHAR ucMemoryType; ///< Memory type (3 for DDR3) + UCHAR ucUMAChannelNumber; ///< System memory channel numbers. + ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; ///< Arrays with values for CSR M3 arbiter for default. + ULONG ulCSR_M3_ARB_CNTL_UVD[10]; ///< Arrays with values for CSR M3 arbiter for UVD playback. + ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; ///< Arrays with values for CSR M3 arbiter for Full Screen 3D applications. + ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; ///< Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high + ULONG ulGMCRestoreResetTime; ///< GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. + ULONG ulMinimumNClk; ///< Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. + ULONG ulIdleNClk; ///< NCLK speed while memory runs in self-refresh state. Unit in 10kHz. + ULONG ulDDR_DLL_PowerUpTime; ///< DDR PHY DLL power up time. Unit in ns. + ULONG ulDDR_PLL_PowerUpTime; ///< DDR PHY PLL power up time. Unit in ns + USHORT usPCIEClkSSPercentage; ///< usPCIEClkSSPercentage + USHORT usPCIEClkSSType; ///< usPCIEClkSSType + USHORT usLvdsSSPercentage; ///< usLvdsSSPercentage + USHORT usLvdsSSpreadRateIn10Hz; ///< usLvdsSSpreadRateIn10Hz + USHORT usHDMISSPercentage; ///< usHDMISSPercentage + USHORT usHDMISSpreadRateIn10Hz; ///< usHDMISSpreadRateIn10Hz + USHORT usDVISSPercentage; ///< usDVISSPercentage + USHORT usDVISSpreadRateIn10Hz; ///< usDVISSpreadRateIn10Hz + ULONG SclkDpmBoostMargin; ///< SclkDpmBoostMargin + ULONG SclkDpmThrottleMargin; ///< SclkDpmThrottleMargin + USHORT SclkDpmTdpLimitPG; ///< SclkDpmTdpLimitPG + USHORT SclkDpmTdpLimitBoost; ///< SclkDpmTdpLimitBoost + ULONG ulBoostEngineCLock; ///< ulBoostEngineCLock + UCHAR ulBoostVid_2bit; ///< ulBoostVid_2bit + UCHAR EnableBoost; ///< EnableBoost + USHORT GnbTdpLimit; ///< GnbTdpLimit + USHORT usMaxLVDSPclkFreqInSingleLink; ///< usMaxLVDSPclkFreqInSingleLink + UCHAR ucLvdsMisc; ///< ucLvdsMisc + UCHAR ucLVDSReserved; ///< ucLVDSReserved + ULONG ulReserved3[15]; ///< Reserved + ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; ///< Display connector definition +} ATOM_INTEGRATED_SYSTEM_INFO_V6; + +/// this Table is used for Llano/Ontario APU +typedef struct _ATOM_FUSION_SYSTEM_INFO_V1 { + ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo; ///< Refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition. + ULONG ulPowerplayTable[128]; ///< This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0] +} ATOM_FUSION_SYSTEM_INFO_V1; + +/// Integrated Info table +/// Upgrade is followed by Trinity SBIOS/VBIOS & Driver interface Design Document VER 0.5 +typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 { + ATOM_COMMON_TABLE_HEADER sHeader; ///< Standard Header + ULONG ulBootUpEngineClock; ///< VBIOS bootup Engine clock frequency, in 10kHz unit. + ULONG ulDentistVCOFreq; ///< Dentist VCO clock in 10kHz unit. + ULONG ulBootUpUMAClock; ///< System memory boot up clock frequency in 10Khz unit. + ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; ///< Report Display clock voltage requirement. + ULONG ulBootUpReqDisplayVector; /**< VBIOS boot up display IDs, following are supported devices in Llano/Fam 12 and Ontario/Fam 14 projects: + * ATOM_DEVICE_CRT1_SUPPORT 0x0001 + * ATOM_DEVICE_CRT2_SUPPORT 0x0010 + * ATOM_DEVICE_DFP1_SUPPORT 0x0008 + * ATOM_DEVICE_DFP6_SUPPORT 0x0040 + * ATOM_DEVICE_DFP2_SUPPORT 0x0080 + * ATOM_DEVICE_DFP3_SUPPORT 0x0200 + * ATOM_DEVICE_DFP4_SUPPORT 0x0400 + * ATOM_DEVICE_DFP5_SUPPORT 0x0800 + * ATOM_DEVICE_LCD1_SUPPORT 0x0002 + */ + ULONG ulOtherDisplayMisc; ///< Other display related flags, not defined yet. + ULONG ulGPUCapInfo; /**> @li BIT[0] - TMDS/HDMI Coherent Mode 0: use cascade PLL mode, 1: use signel PLL mode. + * @li BIT[1] - DP mode 0: use cascade PLL mode, 1: use single PLL mode + * @li BIT[3] - AUX HW mode detection logic 0: Enable, 1: Disable + */ + ULONG ulSB_MMIO_Base_Addr; ///< Physical Base address to SB MMIO space. Driver need to initialize it for SMU usage. + USHORT usRequestedPWMFreqInHz; ///< Panel Required PWM frequency. if this parameter is 0 PWM from to control LCD Backlight will be disabled. + UCHAR ucHtcTmpLmt; ///< HTC temperature limit.The processor enters HTC-active state when Tctl reaches or exceeds HtcHystLmt. + UCHAR ucHtcHystLmt; ///< HTC hysteresis.The processor exits HTC-active state when Tctl is less than HtcTmpLmt minus HtcHystLmt. + ULONG ulMinEngineClock; ///< Min SCLK + ULONG ulSystemConfig; ///< TBD + ULONG ulCPUCapInfo; ///< TBD + USHORT usNBP0Voltage; ///< VID for voltage on NB P0 State + USHORT usNBP1Voltage; ///< VID for voltage on NB P1 State + USHORT usBootUpNBVoltage; ///< Voltage Index of GNB voltage configured by SBIOS, which is sufficient to support VBIOS DISPCLK requirement. + USHORT usExtDispConnInfoOffset; ///< Offset to sExtDispConnInfo inside the structure + USHORT usPanelRefreshRateRange; /**< Bit vector for LVDS/eDP supported refresh rate range. If DRR is enabled, 2 of the bits must be set. + * SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 + * SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 + * SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 + * SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 + */ + UCHAR ucMemoryType; ///< Memory type (3 for DDR3) + UCHAR ucUMAChannelNumber; ///< System memory channel numbers. + UCHAR strVBIOSMsg[40]; ///< Allow customer to have its own VBIOS message + ULONG ulReserved[20]; ///< + ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; ///< Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high + ULONG ulGMCRestoreResetTime; ///< GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. + ULONG ulMinimumNClk; ///< Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. + ULONG ulIdleNClk; ///< NCLK speed while memory runs in self-refresh state. Unit in 10kHz. + ULONG ulDDR_DLL_PowerUpTime; ///< DDR PHY DLL power up time. Unit in ns. + ULONG ulDDR_PLL_PowerUpTime; ///< DDR PHY PLL power up time. Unit in ns + USHORT usPCIEClkSSPercentage; ///< + USHORT usPCIEClkSSType; ///< + USHORT usLvdsSSPercentage; ///< + USHORT usLvdsSSpreadRateIn10Hz; ///< + USHORT usHDMISSPercentage; ///< + USHORT usHDMISSpreadRateIn10Hz; ///< + USHORT usDVISSPercentage; ///< + USHORT usDVISSpreadRateIn10Hz; ///< + ULONG SclkDpmBoostMargin; ///< + ULONG SclkDpmThrottleMargin; ///< + USHORT SclkDpmTdpLimitPG; ///< + USHORT SclkDpmTdpLimitBoost; ///< + ULONG ulBoostEngineCLock; ///< + UCHAR ulBoostVid_2bit; ///< + UCHAR EnableBoost; ///< + USHORT GnbTdpLimit; ///< + USHORT usMaxLVDSPclkFreqInSingleLink; ///< + UCHAR ucLvdsMisc; ///< + UCHAR gnbgfxline429 ; ///< + UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; ///< + UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; ///< + UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; ///< + UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; ///< + UCHAR ucLVDSOffToOnDelay_in4Ms; ///< + UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; ///< + UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; ///< + UCHAR ucLVDSReserved1; ///< + ULONG ulLCDBitDepthControlVal; ///< + ULONG ulNbpStateMemclkFreq[4]; ///< + USHORT usNBP2Voltage; ///< + USHORT usNBP3Voltage; ///< + ULONG ulNbpStateNClkFreq[4]; ///< + UCHAR ucNBDPMEnable; ///< + UCHAR ucReserved[3]; ///< + UCHAR ucDPMState0VclkFid; ///< + UCHAR ucDPMState0DclkFid; ///< + UCHAR ucDPMState1VclkFid; ///< + UCHAR ucDPMState1DclkFid; ///< + UCHAR ucDPMState2VclkFid; ///< + UCHAR ucDPMState2DclkFid; ///< + UCHAR ucDPMState3VclkFid; ///< + UCHAR ucDPMState3DclkFid; ///< + ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; ///< +} ATOM_INTEGRATED_SYSTEM_INFO_V1_7; + +/// this Table is used for Llano/Ontario APU +typedef struct _ATOM_FUSION_SYSTEM_INFO_V2 { + ATOM_INTEGRATED_SYSTEM_INFO_V1_7 sIntegratedSysInfo; ///< Refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_7 definition. + ULONG ulPowerplayTable[128]; ///< This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0] +} ATOM_FUSION_SYSTEM_INFO_V2; + +#define GNB_SBDFO MAKE_SBDFO(0, 0, 0, 0, 0) + +/// Define configuration values for ulGPUCapInfo +// BIT[0] - TMDS/HDMI Coherent Mode 0: use cascade PLL mode, 1: use signel PLL mode. +#define GPUCAPINFO_TMDS_HDMI_USE_CASCADE_PLL_MODE 0x00ul +#define GPUCAPINFO_TMDS_HDMI_USE_SINGLE_PLL_MODE 0x01ul + +// BIT[1] - DP mode 0: use cascade PLL mode, 1: use single PLL mode +#define GPUCAPINFO_DP_MODE_USE_CASCADE_PLL_MODE 0x00ul +#define GPUCAPINFO_DP_USE_SINGLE_PLL_MODE 0x02ul + +// BIT[3] - AUX HW mode detection logic 0: Enable, 1: Disable +#define GPUCAPINFO_AUX_HW_MODE_DETECTION_ENABLE 0x00ul +#define GPUCAPINFO_AUX_HW_MODE_DETECTION_DISABLE 0x08ul + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbGfxFamServices.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbGfxFamServices.h new file mode 100644 index 0000000..0957f9d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbGfxFamServices.h @@ -0,0 +1,108 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe family specific services. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBGFXFAMSERVICES_H_ +#define _GNBGFXFAMSERVICES_H_ + +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbPcie.h" + + +AGESA_STATUS +GfxFmMapEngineToDisplayPath ( + IN PCIe_ENGINE_CONFIG *Engine, + OUT EXT_DISPLAY_PATH *DisplayPathList, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +UINT32 +GfxFmCalculateClock ( + IN UINT8 Did, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GfxFmSetIdleVoltageMode ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +BOOLEAN +GfxFmIsVbiosPosted ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxFmDisableController ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbIommu.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbIommu.h new file mode 100644 index 0000000..2a3d024 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbIommu.h @@ -0,0 +1,222 @@ +/** + * @file + * + * Misc common definition + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBIOMMU_H_ +#define _GNBIOMMU_H_ + +#pragma pack (push, 1) + + +/// IVRS block +typedef enum { + IvrsIvhdBlock = 0x10, ///< I/O Virtualization Hardware Definition Block + IvrsIvmdBlock = 0x20, ///< I/O Virtualization Memory Definition Block for all peripherals + IvrsIvmdBlockSingle = 0x21, ///< IVMD block for specified peripheral + IvrsIvmdBlockRange = 0x22, ///< IVMD block for peripheral range + IvrsIvhdrBlock = 0x40, ///< IVHDR (Relative) block + IvrsIvmdrBlock = 0x50, ///< IVMDR (Relative) block for all peripherals + IvrsIvmdrBlockSingle = 0x51 ///< IVMDR block for last IVHDR +} IVRS_BLOCK_TYPE; + +#define DEVICE_ID(PciAddress) (UINT16) (((PciAddress).Address.Bus << 8) | ((PciAddress).Address.Device << 3) | (PciAddress).Address.Function) + +/// IVHD entry types +typedef enum { + IvhdEntryPadding = 0, ///< Table padding + IvhdEntrySelect = 2, ///< Select + IvhdEntryStartRange = 3, ///< Start Range + IvhdEntryEndRange = 4, ///< End Range + IvhdEntryAliasSelect = 66, ///< Alias select + IvhdEntryAliasStartRange = 67, ///< Alias start range + IvhdEntryExtendedSelect = 70, ///< Extended select + IvhdEntryExtendedStartRange = 71, ///< Extended Start range + IvhdEntrySpecialDevice = 72 ///< Special device +} IVHD_ENTRY_TYPE; + +/// Special device variety +typedef enum { + IvhdSpecialDeviceIoapic = 0x1, ///< IOAPIC + IvhdSpecialDeviceHpet = 0x2 ///< HPET +} IVHD_SPECIAL_DEVICE; + + +#define IVHD_FLAG_COHERENT BIT5 +#define IVHD_FLAG_IOTLBSUP BIT4 +#define IVHD_FLAG_ISOC BIT3 +#define IVHD_FLAG_RESPASSPW BIT2 +#define IVHD_FLAG_PASSPW BIT1 +#define IVHD_FLAG_PPRSUB BIT7 +#define IVHD_FLAG_PREFSUP BIT6 + +#define IVHD_EFR_XTSUP_OFFSET 0 +#define IVHD_EFR_NXSUP_OFFSET 1 +#define IVHD_EFR_GTSUP_OFFSET 2 +#define IVHD_EFR_GLXSUP_OFFSET 3 +#define IVHD_EFR_IASUP_OFFSET 5 +#define IVHD_EFR_GASUP_OFFSET 6 +#define IVHD_EFR_HESUP_OFFSET 7 +#define IVHD_EFR_PASMAX_OFFSET 8 +#define IVHD_EFR_PNCOUNTERS_OFFSET 13 +#define IVHD_EFR_PNBANKS_OFFSET 17 +#define IVHD_EFR_MSINUMPPR_OFFSET 23 +#define IVHD_EFR_GATS_OFFSET 28 +#define IVHD_EFR_HATS_OFFSET 30 + +#define IVINFO_HTATSRESV_MASK 0x00400000ul +#define IVINFO_VASIZE_MASK 0x003F8000ul +#define IVINFO_PASIZE_MASK 0x00007F00ul +#define IVINFO_GASIZE_MASK 0x000000E0ul + +#define IVHD_INFO_MSINUM_OFFSET 0 +#define IVHD_INFO_UNITID_OFFSET 8 + +#define IVMD_FLAG_EXCLUSION_RANGE BIT3 +#define IVMD_FLAG_IW BIT2 +#define IVMD_FLAG_IR BIT1 +#define IVMD_FLAG_UNITY BIT0 + +/// IVRS header +typedef struct { + UINT8 Sign[4]; ///< Signature + UINT32 TableLength; ///< Table Length + UINT8 Revision; ///< Revision + UINT8 Checksum; ///< Checksum + UINT8 OemId[6]; ///< OEM ID + UINT8 OemTableId[8]; ///< OEM Tabled ID + UINT32 OemRev; ///< OEM Revision + UINT8 CreatorId[4]; ///< Creator ID + UINT32 CreatorRev; ///< Creator Revision + UINT32 IvInfo; ///< IvInfo + UINT64 Reserved; ///< Reserved +} IOMMU_IVRS_HEADER; + +/// IVRS IVHD Entry +typedef struct { + UINT8 Type; ///< Type + UINT8 Flags; ///< Flags + UINT16 Length; ///< Length + UINT16 DeviceId; ///< DeviceId + UINT16 CapabilityOffset; ///< CapabilityOffset + UINT64 BaseAddress; ///< BaseAddress + UINT16 PciSegment; ///< Pci segment + UINT16 IommuInfo; ///< IOMMU info + UINT32 IommuEfr; ///< reserved +} IVRS_IVHD_ENTRY; + +/// IVHD generic entry +typedef struct { + UINT8 Type; ///< Type + UINT16 DeviceId; ///< Device id + UINT8 DataSetting; ///< Data settings +} IVHD_GENERIC_ENTRY; + +///IVHD alias entry +typedef struct { + UINT8 Type; ///< Type + UINT16 DeviceId; ///< Device id + UINT8 DataSetting; ///< Data settings + UINT8 Reserved; ///< Reserved + UINT16 AliasDeviceId; ///< Alias device id + UINT8 Reserved2; ///< Reserved +} IVHD_ALIAS_ENTRY; + +///IVHD extended entry +typedef struct { + UINT8 Type; ///< Type + UINT16 DeviceId; ///< Device id + UINT8 DataSetting; ///< Data settings + UINT32 ExtSetting; ///< Extended settings +} IVHD_EXT_ENTRY; + +/// IVHD special entry +typedef struct { + UINT8 Type; ///< Type + UINT16 Reserved; ///< Reserved + UINT8 DataSetting; ///< Data settings + UINT8 Handle; ///< Handle + UINT16 AliasDeviceId; ///< Alis device id + UINT8 Variety; ///< Variety +} IVHD_SPECIAL_ENTRY; + +/// IVRS IVMD Entry +typedef struct { + UINT8 Type; ///< Type + UINT8 Flags; ///< Flags + UINT16 Length; ///< Length + UINT16 DeviceId; ///< DeviceId + UINT16 AuxiliaryData; ///< Auxiliary data + UINT64 Reserved; ///< Reserved (0000_0000_0000_0000) + UINT64 BlockStart; ///< IVMD start address + UINT64 BlockLength; ///< IVMD memory block length +} IVRS_IVMD_ENTRY; + +#pragma pack (pop) + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbLibFeatures.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbLibFeatures.c new file mode 100644 index 0000000..1985beb --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbLibFeatures.c @@ -0,0 +1,132 @@ +/* $NoKeywords:$ */ + /** + * @file + * + * GNB register access services. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "Gnb.h" +#include "OptionGnb.h" +#include "GnbLibFeatures.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + + + +/*----------------------------------------------------------------------------------------*/ +/** + * DIspathc feature tanle + * + * + */ + +AGESA_STATUS +GnbLibDispatchFeatures ( + IN OPTION_GNB_CONFIGURATION *ConfigTable, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + CPU_LOGICAL_ID LogicalId; + + AgesaStatus = AGESA_SUCCESS; + GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); + while (ConfigTable->GnbFeature != NULL) { + if ((ConfigTable->Type & LogicalId.Family) != 0) { + Status = ConfigTable->GnbFeature (StdHeader); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } + ConfigTable++; + } + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbLibFeatures.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbLibFeatures.h new file mode 100644 index 0000000..dfbbc9e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbLibFeatures.h @@ -0,0 +1,82 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB register access services. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBLIBFEATURES_H_ +#define _GNBLIBFEATURES_H_ + + +AGESA_STATUS +GnbLibDispatchFeatures ( + IN OPTION_GNB_CONFIGURATION *ConfigTable, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcie.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcie.h new file mode 100644 index 0000000..fbb8d3b --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcie.h @@ -0,0 +1,418 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe component definitions. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** + +* +*/ + +#ifndef _GNBPCIE_H_ +#define _GNBPCIE_H_ + +#pragma pack (push, 1) + +#define MAX_NUMBER_OF_COMPLEXES 4 + +#define DESCRIPTOR_TERMINATE_GNB 0x40000000ull +#define DESCRIPTOR_TERMINATE_TOPOLOGY 0x20000000ull +#define DESCRIPTOR_ALLOCATED 0x10000000ull +#define DESCRIPTOR_VIRTUAL 0x08000000ull +#define DESCRIPTOR_PLATFORM 0x04000000ull +#define DESCRIPTOR_COMPLEX 0x02000000ull +#define DESCRIPTOR_SILICON 0x01000000ull +#define DESCRIPTOR_PCIE_WRAPPER 0x00800000ull +#define DESCRIPTOR_DDI_WRAPPER 0x00400000ull +#define DESCRIPTOR_PCIE_ENGINE 0x00200000ull +#define DESCRIPTOR_DDI_ENGINE 0x00100000ull + +#define DESCRIPTOR_ALL_WRAPPERS (DESCRIPTOR_DDI_WRAPPER | DESCRIPTOR_PCIE_WRAPPER) +#define DESCRIPTOR_ALL_ENGINES (DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_PCIE_ENGINE) + +#define DESCRIPTOR_ALL_TYPES (DESCRIPTOR_ALL_WRAPPERS | DESCRIPTOR_ALL_ENGINES | DESCRIPTOR_SILICON | DESCRIPTOR_PLATFORM) + +#define UNUSED_LANE_ID 128 +//#define PCIE_LINK_RECEIVER_DETECTION_POOLING (60 * 1000) +//#define PCIE_LINK_L0_POOLING (60 * 1000) +//#define PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000) +//#define PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000) + +// Get lowest PHY lane on engine +#define PcieLibGetLoPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.EndLane : Engine->EngineData.StartLane) : 0) +// Get highest PHY lane on engine +#define PcieLibGetHiPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.StartLane : Engine->EngineData.EndLane) : 0) +// Get number of lanes on wrapper +#define PcieLibWrapperNumberOfLanes(Wrapper) (Wrapper != NULL ? ((UINT8)(Wrapper->EndPhyLane - Wrapper->StartPhyLane + 1)) : 0) +// Check if virtual descriptor +#define PcieLibIsVirtualDesciptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_VIRTUAL) != 0) : FALSE) +// Check if it is allocated descriptor +#define PcieLibIsEngineAllocated(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0) : FALSE) +// Check if it is last descriptor in list +#define PcieLibIsLastDescriptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) != 0) : TRUE) +// Check if descriptor a PCIe engine +#define PcieLibIsPcieEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_ENGINE) != 0) : FALSE) +// Check if descriptor a DDI engine +#define PcieLibIsDdiEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_ENGINE) != 0) : FALSE) +// Check if descriptor a DDI wrapper +#define PcieLibIsDdiWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_WRAPPER) != 0) : FALSE) +// Check if descriptor a PCIe wrapper +#define PcieLibIsPcieWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_WRAPPER) != 0) : FALSE) +// Check if descriptor a PCIe wrapper +#define PcieLibGetNextDescriptor(Descriptor) (Descriptor != NULL ? (((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (Descriptor+1)) : NULL) + +#define LANE_TYPE_PCIE_CORE_CONFIG 0x00000001ul +#define LANE_TYPE_PCIE_CORE_ALLOC 0x00000002ul +#define LANE_TYPE_PCIE_CORE_ACTIVE 0x00000004ul +#define LANE_TYPE_PCIE_SB_CORE_CONFIG 0x00000008ul +#define LANE_TYPE_PCIE_CORE_HOTPLUG 0x00000010ul +#define LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE 0x00000020ul +#define LANE_TYPE_PCIE_PHY 0x00000100ul +#define LANE_TYPE_PCIE_PHY_NATIVE 0x00000200ul +#define LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE 0x00000400ul +#define LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG 0x00000800ul +#define LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE 0x00001000ul +#define LANE_TYPE_DDI_PHY 0x00010000ul +#define LANE_TYPE_DDI_PHY_NATIVE 0x00020000ul +#define LANE_TYPE_DDI_PHY_NATIVE_ACTIVE 0x00040000ul +#define LANE_TYPE_PHY_NATIVE_ALL 0x00100000ul +#define LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL 0x00200000ul +#define LANE_TYPE_CORE_ALL LANE_TYPE_PHY_NATIVE_ALL +#define LANE_TYPE_ALL LANE_TYPE_PHY_NATIVE_ALL + +#define LANE_TYPE_PCIE_LANES (LANE_TYPE_PCIE_CORE_ACTIVE | LANE_TYPE_PCIE_SB_CORE_CONFIG | \ + LANE_TYPE_PCIE_CORE_HOTPLUG | LANE_TYPE_PCIE_CORE_ALLOC | \ + LANE_TYPE_PCIE_PHY | LANE_TYPE_PCIE_PHY_NATIVE | \ + LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG | \ + LANE_TYPE_PCIE_CORE_CONFIG | LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | \ + LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE) + +#define LANE_TYPE_DDI_LANES (LANE_TYPE_DDI_PHY | LANE_TYPE_DDI_PHY_NATIVE | LANE_TYPE_DDI_PHY_NATIVE_ACTIVE) + + +#define INIT_STATUS_PCIE_PORT_GEN2_RECOVERY 0x00000001ull +#define INIT_STATUS_PCIE_PORT_BROKEN_LANE_RECOVERY 0x00000002ull +#define INIT_STATUS_PCIE_PORT_TRAINING_FAIL 0x00000004ull +#define INIT_STATUS_PCIE_TRAINING_SUCCESS 0x00000008ull +#define INIT_STATUS_PCIE_EP_NOT_PRESENT 0x00000010ull +#define INIT_STATUS_PCIE_PORT_IN_COMPLIANCE 0x00000020ull +#define INIT_STATUS_DDI_ACTIVE 0x00000040ull +#define INIT_STATUS_ALLOCATED 0x00000080ull + +#define PCIE_PORT_GEN_CAP_BOOT 0x00000001ul +#define PCIE_PORT_GEN_CAP_MAX 0x00000002ul +#define PCIE_GLOBAL_GEN_CAP_ALL_PORTS 0x00000010ul +#define PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS 0x00000011ul +#define PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS 0x00000012ul + +#define PCIE_POWERGATING_SKIP_CORE 0x00000001ul +#define PCIE_POWERGATING_SKIP_PHY 0x00000002ul + +/// PCIe Link Training State +typedef enum { + PcieTrainingStandard, ///< Standard training algorithm. Training contained to AmdEarlyInit. + ///< PCIe device accessible after AmdEarlyInit complete + PcieTrainingDistributed, ///< Distribute training algorithm. Training distributed across AmdEarlyInit/AmdPostInit/AmdS3LateRestore + ///< PCIe device accessible after AmdPostInit complete. + ///< Algorithm potentially save up to 60ms in S3 resume time by skipping training empty slots. +} PCIE_TRAINING_ALGORITHM; + +/// PCIe Link Training State +typedef enum { + LinkStateResetAssert, ///< Assert port GPIO reset + LinkStateResetDuration, ///< Timeout for reset duration + LinkStateResetExit, ///< Deassert port GPIO reset + LinkTrainingResetTimeout, ///< Port GPIO reset timeout + LinkStateReleaseTraining, ///< Release link training + LinkStateDetectPresence, ///< Detect device presence + LinkStateDetecting, ///< Detect link training. + LinkStateBrokenLane, ///< Check and handle broken lane + LinkStateGen2Fail, ///< Check and handle device that fail training if GEN2 capability advertised + LinkStateL0, ///< Device trained to L0 + LinkStateVcoNegotiation, ///< Check VCO negotiation complete + LinkStateRetrain, ///< Force retrain link. + LinkStateTrainingFail, ///< Link training fail + LinkStateTrainingSuccess, ///< Link training success + LinkStateGfxWorkaround, ///< GFX workaround + LinkStateCompliance, ///< Link in compliance mode + LinkStateDeviceNotPresent, ///< Link is not connected + LinkStateTrainingCompleted ///< Link training completed +} PCIE_LINK_TRAINING_STATE; + +/// PCIe Port Visibility +typedef enum { + UnhidePorts, ///< Command to unhide port + HidePorts, ///< Command to hide unused ports +} PCIE_PORT_VISIBILITY; + + +/// Table Register Entry +typedef struct { + UINT16 Reg; ///< Address + UINT32 Mask; ///< Mask + UINT32 Data; ///< Data +} PCIE_PORT_REGISTER_ENTRY; + +/// Table Register Entry +typedef struct { + PCIE_PORT_REGISTER_ENTRY *Table; ///< Table + UINT32 Length; ///< Length +} PCIE_PORT_REGISTER_TABLE_HEADER; + +/// Table Register Entry +typedef struct { + UINT32 Reg; ///< Address + UINT32 Mask; ///< Mask + UINT32 Data; ///< Data +} PCIE_HOST_REGISTER_ENTRY; + +/// Table Register Entry +typedef struct { + PCIE_HOST_REGISTER_ENTRY *Table; ///< Table + UINT32 Length; ///< Length +} PCIE_HOST_REGISTER_TABLE_HEADER; + +///Link ASPM info +typedef struct { + PCI_ADDR DownstreamPort; ///< PCI address of downstream port + PCIE_ASPM_TYPE DownstreamAspm; ///< Downstream Device Aspm + PCI_ADDR UpstreamPort; ///< PCI address of upstream port + PCIE_ASPM_TYPE UpstreamAspm; ///< Upstream Device Capability + PCIE_ASPM_TYPE RequestedAspm; ///< Requested ASPM +} PCIe_LINK_ASPM; + +///PCIe ASPM Latency Information +typedef struct { + UINT8 MaxL0sExitLatency; ///< Max L0s exit latency in us + UINT8 MaxL1ExitLatency; ///< Max L1 exit latency in us +} PCIe_ASPM_LATENCY_INFO; + +/// PCI address association +typedef struct { + UINT8 NewDeviceAddress; ///< New PCI address (Device,Fucntion) + UINT8 NativeDeviceAddress; ///< Native PCI address (Device,Fucntion) +} PCI_ADDR_LIST; + +/// The return status for GFX Card Workaround. +typedef enum { + GFX_WORKAROUND_DEVICE_NOT_READY, ///< GFX Workaround device is not ready. + GFX_WORKAROUND_RESET_DEVICE, ///< GFX Workaround device need reset. + GFX_WORKAROUND_SUCCESS ///< The service completed normally. +} GFX_WORKAROUND_STATUS; + +/// GFX workaround control +typedef enum { + GfxWorkaroundDisable, ///< GFX Workaround disabled + GfxWorkaroundEnable ///< GFX Workaround enabled +} GFX_WORKAROUND_CONTROL; + +/// PIF lane power state +typedef enum { + PifPowerStateL0, ///< + PifPowerStateLS1, ///< + PifPowerStateLS2, ///< + PifPowerStateOff = 0x7, ///< +} PCIE_PIF_POWER_STATE; + +/// PIF lane power control +typedef enum { + PowerDownPifs, ///< + PowerUpPifs ///< +} PCIE_PIF_POWER_CONTROL; + +///PLL rumup time +typedef enum { + NormalRampup, ///< + LongRampup, ///< +} PCIE_PLL_RAMPUP_TIME; + +typedef UINT16 PCIe_ENGINE_INIT_STATUS; + +/// PCIe port configuration info +typedef struct { + PCIe_PORT_DATA PortData; ///< Port data + UINT8 StartCoreLane; ///< Start Core Lane + UINT8 EndCoreLane; ///< End Core lane + UINT8 NativeDevNumber :5; ///< Native PCI device number of the port + UINT8 NativeFunNumber :3; ///< Native PCI function number of the port + UINT8 CoreId :4; ///< PCIe core ID + UINT8 PortId :4; ///< Port ID on wrapper + PCI_ADDR Address; ///< PCI address of the port + UINT8 State; ///< Training state + UINT8 PcieBridgeId:4; ///< IOC PCIe bridge ID + UINT16 UnitId:12; ///< Port start unit ID + UINT16 NumberOfUnitId:4; ///< Def number of unitIDs assigned to port + UINT8 GfxWrkRetryCount:4; ///< Number of retry for GFX workaround + UINT32 TimeStamp; ///< Time stamp used to during training process + UINT8 LogicalBridgeId; ///< Logical Bridge ID +} PCIe_PORT_CONFIG; + +///Descriptor header +typedef struct { + UINT32 DescriptorFlags; ///< Descriptor flags + UINT16 Parent; ///< Offset of parent descriptor + UINT16 Peer; ///< Offset of the peer descriptor + UINT16 Child; ///< Offset of the list of child descriptors +} PCIe_DESCRIPTOR_HEADER; + +/// DDI (Digital Display Interface) configuration info +typedef struct { + PCIe_DDI_DATA DdiData; ///< DDI Data + UINT8 DisplayPriorityIndex; ///< Display priority index + UINT8 ConnectorId; ///< Connector id determined by enumeration + UINT8 DisplayDeviceId; ///< Display device id determined by enumeration +} PCIe_DDI_CONFIG; + + +/// Engine configuration data +typedef struct { + PCIe_DESCRIPTOR_HEADER Header; ///< Descripto header + PCIe_ENGINE_DATA EngineData; ///< Engine Data + PCIe_ENGINE_INIT_STATUS InitStatus; ///< Initialization Status + UINT8 Scratch; ///< Scratch pad + union { + PCIe_PORT_CONFIG Port; ///< PCIe port configuration data + PCIe_DDI_CONFIG Ddi; ///< DDI configuration data + } Type; +} PCIe_ENGINE_CONFIG; + +/// Wrapper configuration data +typedef struct { + PCIe_DESCRIPTOR_HEADER Header; ///< Descrptor Header + UINT8 WrapId; ///< Wrapper ID + UINT8 NumberOfPIFs; ///< Number of PIFs on wrapper + UINT8 StartPhyLane; ///< Start PHY Lane + UINT8 EndPhyLane; ///< End PHY Lane + UINT8 StartPcieCoreId:4; ///< Start PCIe Core ID + UINT8 EndPcieCoreId:4; ///< End PCIe Core ID + UINT8 NumberOfLanes; ///< Number of lanes + struct { + UINT8 PowerOffUnusedLanes:1; ///< Power Off unused lanes + UINT8 PowerOffUnusedPlls:1; ///< Power Off unused Plls + UINT8 ClkGating:1; ///< TXCLK gating + UINT8 LclkGating:1; ///< LCLK gating + UINT8 TxclkGatingPllPowerDown:1; ///< TXCLK clock gating PLL power down + UINT8 PllOffInL1:1; ///< PLL off in L1 + UINT8 AccessEncoding:1; ///< Reg access encoding + } Features; + UINT8 MasterPll; ///< Bitmap of master PLL +} PCIe_WRAPPER_CONFIG; + + +/// Silicon configuration data +typedef struct { + PCIe_DESCRIPTOR_HEADER Header; ///< Descrptor Header + UINT8 SiliconId; ///< Gnb silicon(module) ID + UINT8 NodeId; ///< Node to which GNB connected + UINT8 LinkId; ///< Link to which GNB connected if LinkId > 3 GNB connected to sublink = LinkId - 4 + PCI_ADDR Address; ///< PCI address of GNB host bridge +} PCIe_SILICON_CONFIG; + +typedef PCIe_SILICON_CONFIG GNB_HANDLE; + +/// Complex configuration data +typedef struct { + PCIe_DESCRIPTOR_HEADER Header; ///< Descrptor Header + UINT8 SocketId; ///< Processor socket ID +} PCIe_COMPLEX_CONFIG; + +/// PCIe platform configuration info +typedef struct { + PCIe_DESCRIPTOR_HEADER Header; ///< Descrptor Header + UINT32 StdHeader; ///< Standard configuration header TODO:Used to be PVOID + UINT32 LinkReceiverDetectionPooling; ///< Receiver pooling detection time in us. + UINT32 LinkL0Pooling; ///< Pooling for link to get to L0 in us + UINT32 LinkGpioResetAssertionTime; ///< Gpio reset assertion time in us + UINT32 LinkResetToTrainingTime; ///< Time duration between deassert GPIO reset and release training in us /// + UINT8 GfxCardWorkaround; ///< GFX Card Workaround + UINT8 PsppPolicy; ///< PSPP policy + UINT8 TrainingExitState; ///< State at which training should exit (see PCIE_LINK_TRAINING_STATE) + UINT8 TrainingAlgorithm; ///< Training algorithm (see PCIE_TRAINING_ALGORITHM) + PCIe_COMPLEX_CONFIG ComplexList[MAX_NUMBER_OF_COMPLEXES]; ///< Complex +} PCIe_PLATFORM_CONFIG; + +/// PCIe Engine Description +typedef struct { + UINT32 Flags; /**< Descriptor flags + * @li @b Bit31 - last descriptor on wrapper + * @li @b Bit30 - Descriptor allocated for PCIe port or DDI + */ + PCIe_ENGINE_DATA EngineData; ///< Engine Data +} PCIe_ENGINE_DESCRIPTOR; + +/// PCIe Lane allocation descriptor +typedef struct { + UINT32 Flags; ///< Flags + UINT8 WrapId; ///< Wrapper ID + UINT8 EngineType; ///< Engine Type + UINT8 NumberOfEngines; ///< Number of engines to configure + UINT8 NumberOfConfigurations; ///< Number of possible configurations + UINT8 *ConfigTable; ///< Pointer to config table +} PCIe_LANE_ALLOC_DESCRIPTOR; + +#pragma pack (pop) + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcieFamServices.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcieFamServices.h new file mode 100644 index 0000000..5942a71 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcieFamServices.h @@ -0,0 +1,275 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe family specific services. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBPCIEFAMSERVICES_H_ +#define _GNBPCIEFAMSERVICES_H_ + +#include "Gnb.h" +#include "GnbPcie.h" + +AGESA_STATUS +PcieFmGetComplexDataLength ( + IN UINT8 SocketId, + OUT UINTN *Length, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef AGESA_STATUS F_PCIEFMGETCOMPLEXDATALENGTH ( + IN UINT8 SocketId, + OUT UINTN *Length, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PcieFmBuildComplexConfiguration ( + IN UINT8 SocketId, + OUT VOID *Buffer, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef AGESA_STATUS F_PCIEFMBUILDCOMPLEXCONFIGURATION ( + IN UINT8 SocketId, + OUT VOID *Buffer, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PcieFmConfigureEnginesLaneAllocation ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIE_ENGINE_TYPE EngineType, + IN UINT8 ConfigurationId + ); + +typedef AGESA_STATUS F_PCIEFMCONFIGUREENGINESLANEALLOCATION ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIE_ENGINE_TYPE EngineType, + IN UINT8 ConfigurationId + ); + +AGESA_STATUS +PcieFmGetCoreConfigurationValue ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 CoreId, + IN UINT64 ConfigurationSignature, + IN UINT8 *ConfigurationValue + ); + +typedef AGESA_STATUS F_PCIEFMGETCORECONFIGURATIONVALUE ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 CoreId, + IN UINT64 ConfigurationSignature, + IN UINT8 *ConfigurationValue + ); + +BOOLEAN +PcieFmCheckPortPciDeviceMapping ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ); + +typedef BOOLEAN F_PCIEFMCHECKPORTPCIDEVICEMAPPING ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ); + +AGESA_STATUS +PcieFmMapPortPciAddress ( + IN PCIe_ENGINE_CONFIG *Engine + ); + +typedef AGESA_STATUS F_PCIEFMMAPPORTPCIADDRESS ( + IN PCIe_ENGINE_CONFIG *Engine + ); + +BOOLEAN +PcieFmCheckPortPcieLaneCanBeMuxed ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ); + +typedef BOOLEAN F_PCIEFMCHECKPORTPCIELANECANBEMUXED ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ); + +CONST CHAR8* +PcieFmDebugGetCoreConfigurationString ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationValue + ); + +typedef CONST CHAR8* F_PCIEFMDEBUGGETCORECONFIGURATIONSTRING ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationValue + ); + +CONST CHAR8* +PcieFmDebugGetWrapperNameString ( + IN PCIe_WRAPPER_CONFIG *Wrapper + ); + +typedef CONST CHAR8* F_PCIEFMDEBUGGETWRAPPERNAMESTRING ( + IN PCIe_WRAPPER_CONFIG *Wrapper + ); + +CONST CHAR8* +PcieFmDebugGetHostRegAddressSpaceString ( + IN PCIe_SILICON_CONFIG *Silicon, + IN UINT16 AddressFrame + ); + +typedef CONST CHAR8* F_PCIEFMDEBUGGETHOSTREGADDRESSSPACESTRING ( + IN PCIe_SILICON_CONFIG *Silicon, + IN UINT16 AddressFrame + ); + +PCIE_LINK_SPEED_CAP +PcieFmGetLinkSpeedCap ( + IN UINT32 Flags, + IN PCIe_ENGINE_CONFIG *Engine + ); + +typedef PCIE_LINK_SPEED_CAP F_PCIEFMGETLINKSPEEDCAP ( + IN UINT32 Flags, + IN PCIe_ENGINE_CONFIG *Engine + ); + +VOID +PcieFmSetLinkSpeedCap ( + IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +typedef VOID F_PCIEFMSETLINKSPEEDCAP ( + IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +UINT32 +PcieFmGetNativePhyLaneBitmap ( + IN UINT32 PhyLaneBitmap, + IN PCIe_ENGINE_CONFIG *Engine + ); + +typedef UINT32 F_PCIEFMGETNATIVEPHYLANEBITMAP ( + IN UINT32 PhyLaneBitmap, + IN PCIe_ENGINE_CONFIG *Engine + ); + +AGESA_STATUS +PcieFmAlibBuildAcpiTable ( + IN VOID *AlibSsdtPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PcieFmGetSbConfigInfo ( + IN UINT8 SocketId, + OUT PCIe_PORT_DESCRIPTOR *SbPort, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef AGESA_STATUS F_PCIEFMGETSBCONFIGINFO ( + IN UINT8 SocketId, + OUT PCIe_PORT_DESCRIPTOR *SbPort, + IN AMD_CONFIG_PARAMS *StdHeader + ); + + +/// PCIe config services +typedef struct { + F_PCIEFMGETCOMPLEXDATALENGTH *PcieFmGetComplexDataLength; ///< PcieFmGetComplexDataLength + F_PCIEFMBUILDCOMPLEXCONFIGURATION *PcieFmBuildComplexConfiguration; ///< PcieFmBuildComplexConfiguration + F_PCIEFMCONFIGUREENGINESLANEALLOCATION *PcieFmConfigureEnginesLaneAllocation; ///< PcieFmConfigureEnginesLaneAllocation + F_PCIEFMCHECKPORTPCIDEVICEMAPPING *PcieFmCheckPortPciDeviceMapping; ///< PcieFmCheckPortPciDeviceMapping + F_PCIEFMMAPPORTPCIADDRESS *PcieFmMapPortPciAddress; ///< PcieFmMapPortPciAddress + F_PCIEFMCHECKPORTPCIELANECANBEMUXED *PcieFmCheckPortPcieLaneCanBeMuxed; ///< PcieFmCheckPortPcieLaneCanBeMuxed + F_PCIEFMGETSBCONFIGINFO *PcieFmGetSbConfigInfo; ///< PcieFmGetSbConfigInfo +} PCIe_FAM_CONFIG_SERVICES; + +/// PCIe init services +typedef struct { + F_PCIEFMGETCORECONFIGURATIONVALUE *PcieFmGetCoreConfigurationValue; ///< PcieFmGetCoreConfigurationValue + F_PCIEFMGETLINKSPEEDCAP *PcieFmGetLinkSpeedCap; ///< PcieFmGetLinkSpeedCap + F_PCIEFMGETNATIVEPHYLANEBITMAP *PcieFmGetNativePhyLaneBitmap; ///< PcieFmGetNativePhyLaneBitmap + F_PCIEFMSETLINKSPEEDCAP *PcieFmSetLinkSpeedCap; ///< PcieFmSetLinkSpeedCap +} PCIe_FAM_INIT_SERVICES; + +///PCIe debug services +typedef struct { + F_PCIEFMDEBUGGETHOSTREGADDRESSSPACESTRING *PcieFmDebugGetHostRegAddressSpaceString; ///< PcieFmGetCoreConfigurationValue + F_PCIEFMDEBUGGETWRAPPERNAMESTRING *PcieFmDebugGetWrapperNameString; ///< PcieFmDebugGetWrapperNameString + F_PCIEFMDEBUGGETCORECONFIGURATIONSTRING *PcieFmDebugGetCoreConfigurationString; ///< PcieFmDebugGetCoreConfigurationString +} PCIe_FAM_DEBUG_SERVICES; + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbRegistersLN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbRegistersLN.h new file mode 100644 index 0000000..4282420 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbRegistersLN.h @@ -0,0 +1,10111 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Register definitions + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _GNBREGISTERSLN_H_ +#define _GNBREGISTERSLN_H_ +#define TYPE_D0F0 0x1 +#define TYPE_D0F0x64 0x2 +#define TYPE_D0F0x98 0x3 +#define TYPE_D0F0xE4 0x5 +#define TYPE_DxF0 0x6 +#define TYPE_DxF0xE4 0x7 +#define TYPE_D18F1 0xb +#define TYPE_D18F2 0xc +#define TYPE_D18F3 0xd +#define TYPE_MSR 0x10 +#define TYPE_D1F0 0x11 +#define TYPE_GMM 0x12 +#define D18F2x9C 0xe +#define GMM 0x11 +#ifndef WRAP_SPACE + #define WRAP_SPACE(w, x) (0x01300000 | (w << 16) | (x)) +#endif +#ifndef CORE_SPACE + #define CORE_SPACE(c, x) (0x00010000 | (c << 24) | (x)) +#endif +#ifndef PHY_SPACE + #define PHY_SPACE(w, p, x) (0x00200000 | ((p + 1) << 24) | (w << 16) | (x)) +#endif +#ifndef PIF_SPACE + #define PIF_SPACE(w, p, x) (0x00100000 | ((p + 1) << 24) | (w << 16) | (x)) +#endif +// **** D0F0x00 Register Definition **** +// Address +#define D0F0x00_ADDRESS 0x0 + +// Type +#define D0F0x00_TYPE TYPE_D0F0 +// Field Data +#define D0F0x00_VendorID_OFFSET 0 +#define D0F0x00_VendorID_WIDTH 16 +#define D0F0x00_VendorID_MASK 0xffff +#define D0F0x00_DeviceID_OFFSET 16 +#define D0F0x00_DeviceID_WIDTH 16 +#define D0F0x00_DeviceID_MASK 0xffff0000 + +/// D0F0x00 +typedef union { + struct { ///< + UINT32 VendorID:16; ///< + UINT32 DeviceID:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x00_STRUCT; + +// **** D0F0x04 Register Definition **** +// Address +#define D0F0x04_ADDRESS 0x4 + +// Type +#define D0F0x04_TYPE TYPE_D0F0 +// Field Data +#define D0F0x04_IoAccessEn_OFFSET 0 +#define D0F0x04_IoAccessEn_WIDTH 1 +#define D0F0x04_IoAccessEn_MASK 0x1 +#define D0F0x04_MemAccessEn_OFFSET 1 +#define D0F0x04_MemAccessEn_WIDTH 1 +#define D0F0x04_MemAccessEn_MASK 0x2 +#define D0F0x04_BusMasterEn_OFFSET 2 +#define D0F0x04_BusMasterEn_WIDTH 1 +#define D0F0x04_BusMasterEn_MASK 0x4 +#define D0F0x04_SpecialCycleEn_OFFSET 3 +#define D0F0x04_SpecialCycleEn_WIDTH 1 +#define D0F0x04_SpecialCycleEn_MASK 0x8 +#define D0F0x04_MemWriteInvalidateEn_OFFSET 4 +#define D0F0x04_MemWriteInvalidateEn_WIDTH 1 +#define D0F0x04_MemWriteInvalidateEn_MASK 0x10 +#define D0F0x04_PalSnoopEn_OFFSET 5 +#define D0F0x04_PalSnoopEn_WIDTH 1 +#define D0F0x04_PalSnoopEn_MASK 0x20 +#define D0F0x04_ParityErrorEn_OFFSET 6 +#define D0F0x04_ParityErrorEn_WIDTH 1 +#define D0F0x04_ParityErrorEn_MASK 0x40 +#define D0F0x04_Reserved_7_7_OFFSET 7 +#define D0F0x04_Reserved_7_7_WIDTH 1 +#define D0F0x04_Reserved_7_7_MASK 0x80 +#define D0F0x04_SerrEn_OFFSET 8 +#define D0F0x04_SerrEn_WIDTH 1 +#define D0F0x04_SerrEn_MASK 0x100 +#define D0F0x04_FastB2BEn_OFFSET 9 +#define D0F0x04_FastB2BEn_WIDTH 1 +#define D0F0x04_FastB2BEn_MASK 0x200 +#define D0F0x04_Reserved_19_10_OFFSET 10 +#define D0F0x04_Reserved_19_10_WIDTH 10 +#define D0F0x04_Reserved_19_10_MASK 0xffc00 +#define D0F0x04_CapList_OFFSET 20 +#define D0F0x04_CapList_WIDTH 1 +#define D0F0x04_CapList_MASK 0x100000 +#define D0F0x04_PCI66En_OFFSET 21 +#define D0F0x04_PCI66En_WIDTH 1 +#define D0F0x04_PCI66En_MASK 0x200000 +#define D0F0x04_Reserved_22_22_OFFSET 22 +#define D0F0x04_Reserved_22_22_WIDTH 1 +#define D0F0x04_Reserved_22_22_MASK 0x400000 +#define D0F0x04_FastBackCapable_OFFSET 23 +#define D0F0x04_FastBackCapable_WIDTH 1 +#define D0F0x04_FastBackCapable_MASK 0x800000 +#define D0F0x04_Reserved_24_24_OFFSET 24 +#define D0F0x04_Reserved_24_24_WIDTH 1 +#define D0F0x04_Reserved_24_24_MASK 0x1000000 +#define D0F0x04_DevselTiming_OFFSET 25 +#define D0F0x04_DevselTiming_WIDTH 2 +#define D0F0x04_DevselTiming_MASK 0x6000000 +#define D0F0x04_SignalTargetAbort_OFFSET 27 +#define D0F0x04_SignalTargetAbort_WIDTH 1 +#define D0F0x04_SignalTargetAbort_MASK 0x8000000 +#define D0F0x04_ReceivedTargetAbort_OFFSET 28 +#define D0F0x04_ReceivedTargetAbort_WIDTH 1 +#define D0F0x04_ReceivedTargetAbort_MASK 0x10000000 +#define D0F0x04_ReceivedMasterAbort_OFFSET 29 +#define D0F0x04_ReceivedMasterAbort_WIDTH 1 +#define D0F0x04_ReceivedMasterAbort_MASK 0x20000000 +#define D0F0x04_SignaledSystemError_OFFSET 30 +#define D0F0x04_SignaledSystemError_WIDTH 1 +#define D0F0x04_SignaledSystemError_MASK 0x40000000 +#define D0F0x04_ParityErrorDetected_OFFSET 31 +#define D0F0x04_ParityErrorDetected_WIDTH 1 +#define D0F0x04_ParityErrorDetected_MASK 0x80000000 + +/// D0F0x04 +typedef union { + struct { ///< + UINT32 IoAccessEn:1 ; ///< + UINT32 MemAccessEn:1 ; ///< + UINT32 BusMasterEn:1 ; ///< + UINT32 SpecialCycleEn:1 ; ///< + UINT32 MemWriteInvalidateEn:1 ; ///< + UINT32 PalSnoopEn:1 ; ///< + UINT32 ParityErrorEn:1 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 SerrEn:1 ; ///< + UINT32 FastB2BEn:1 ; ///< + UINT32 Reserved_19_10:10; ///< + UINT32 CapList:1 ; ///< + UINT32 PCI66En:1 ; ///< + UINT32 Reserved_22_22:1 ; ///< + UINT32 FastBackCapable:1 ; ///< + UINT32 Reserved_24_24:1 ; ///< + UINT32 DevselTiming:2 ; ///< + UINT32 SignalTargetAbort:1 ; ///< + UINT32 ReceivedTargetAbort:1 ; ///< + UINT32 ReceivedMasterAbort:1 ; ///< + UINT32 SignaledSystemError:1 ; ///< + UINT32 ParityErrorDetected:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x04_STRUCT; + +// **** D0F0x08 Register Definition **** +// Address +#define D0F0x08_ADDRESS 0x8 + +// Type +#define D0F0x08_TYPE TYPE_D0F0 +// Field Data +#define D0F0x08_RevID_OFFSET 0 +#define D0F0x08_RevID_WIDTH 8 +#define D0F0x08_RevID_MASK 0xff +#define D0F0x08_ClassCode_OFFSET 8 +#define D0F0x08_ClassCode_WIDTH 24 +#define D0F0x08_ClassCode_MASK 0xffffff00 + +/// D0F0x08 +typedef union { + struct { ///< + UINT32 RevID:8 ; ///< + UINT32 ClassCode:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x08_STRUCT; + +// **** D0F0x0C Register Definition **** +// Address +#define D0F0x0C_ADDRESS 0xc + +// Type +#define D0F0x0C_TYPE TYPE_D0F0 +// Field Data +#define D0F0x0C_CacheLineSize_OFFSET 0 +#define D0F0x0C_CacheLineSize_WIDTH 8 +#define D0F0x0C_CacheLineSize_MASK 0xff +#define D0F0x0C_LatencyTimer_OFFSET 8 +#define D0F0x0C_LatencyTimer_WIDTH 8 +#define D0F0x0C_LatencyTimer_MASK 0xff00 +#define D0F0x0C_HeaderTypeReg_OFFSET 16 +#define D0F0x0C_HeaderTypeReg_WIDTH 8 +#define D0F0x0C_HeaderTypeReg_MASK 0xff0000 +#define D0F0x0C_BIST_OFFSET 24 +#define D0F0x0C_BIST_WIDTH 8 +#define D0F0x0C_BIST_MASK 0xff000000 + +/// D0F0x0C +typedef union { + struct { ///< + UINT32 CacheLineSize:8 ; ///< + UINT32 LatencyTimer:8 ; ///< + UINT32 HeaderTypeReg:8 ; ///< + UINT32 BIST:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x0C_STRUCT; + +// **** D0F0x2C Register Definition **** +// Address +#define D0F0x2C_ADDRESS 0x2c + +// Type +#define D0F0x2C_TYPE TYPE_D0F0 +// Field Data +#define D0F0x2C_SubsystemVendorID_OFFSET 0 +#define D0F0x2C_SubsystemVendorID_WIDTH 16 +#define D0F0x2C_SubsystemVendorID_MASK 0xffff +#define D0F0x2C_SubsystemID_OFFSET 16 +#define D0F0x2C_SubsystemID_WIDTH 16 +#define D0F0x2C_SubsystemID_MASK 0xffff0000 + +/// D0F0x2C +typedef union { + struct { ///< + UINT32 SubsystemVendorID:16; ///< + UINT32 SubsystemID:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x2C_STRUCT; + +// **** D0F0x34 Register Definition **** +// Address +#define D0F0x34_ADDRESS 0x34 + +// Type +#define D0F0x34_TYPE TYPE_D0F0 +// Field Data +#define D0F0x34_CapPtr_OFFSET 0 +#define D0F0x34_CapPtr_WIDTH 8 +#define D0F0x34_CapPtr_MASK 0xff +#define D0F0x34_Reserved_31_8_OFFSET 8 +#define D0F0x34_Reserved_31_8_WIDTH 24 +#define D0F0x34_Reserved_31_8_MASK 0xffffff00 + +/// D0F0x34 +typedef union { + struct { ///< + UINT32 CapPtr:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x34_STRUCT; + +// **** D0F0x4C Register Definition **** +// Address +#define D0F0x4C_ADDRESS 0x4c + +// Type +#define D0F0x4C_TYPE TYPE_D0F0 +// Field Data +#define D0F0x4C_Function1Enable_OFFSET 0 +#define D0F0x4C_Function1Enable_WIDTH 1 +#define D0F0x4C_Function1Enable_MASK 0x1 +#define D0F0x4C_ApicEnable_OFFSET 1 +#define D0F0x4C_ApicEnable_WIDTH 1 +#define D0F0x4C_ApicEnable_MASK 0x2 +#define D0F0x4C_Reserved_2_2_OFFSET 2 +#define D0F0x4C_Reserved_2_2_WIDTH 1 +#define D0F0x4C_Reserved_2_2_MASK 0x4 +#define D0F0x4C_Cf8Dis_OFFSET 3 +#define D0F0x4C_Cf8Dis_WIDTH 1 +#define D0F0x4C_Cf8Dis_MASK 0x8 +#define D0F0x4C_PMEDis_OFFSET 4 +#define D0F0x4C_PMEDis_WIDTH 1 +#define D0F0x4C_PMEDis_MASK 0x10 +#define D0F0x4C_SerrDis_OFFSET 5 +#define D0F0x4C_SerrDis_WIDTH 1 +#define D0F0x4C_SerrDis_MASK 0x20 +#define D0F0x4C_Reserved_10_6_OFFSET 6 +#define D0F0x4C_Reserved_10_6_WIDTH 5 +#define D0F0x4C_Reserved_10_6_MASK 0x7c0 +#define D0F0x4C_CRS_OFFSET 11 +#define D0F0x4C_CRS_WIDTH 1 +#define D0F0x4C_CRS_MASK 0x800 +#define D0F0x4C_CfgRdTime_OFFSET 12 +#define D0F0x4C_CfgRdTime_WIDTH 3 +#define D0F0x4C_CfgRdTime_MASK 0x7000 +#define D0F0x4C_Reserved_22_15_OFFSET 15 +#define D0F0x4C_Reserved_22_15_WIDTH 8 +#define D0F0x4C_Reserved_22_15_MASK 0x7f8000 +#define D0F0x4C_MMIOEnable_OFFSET 23 +#define D0F0x4C_MMIOEnable_WIDTH 1 +#define D0F0x4C_MMIOEnable_MASK 0x800000 +#define D0F0x4C_Reserved_25_24_OFFSET 24 +#define D0F0x4C_Reserved_25_24_WIDTH 2 +#define D0F0x4C_Reserved_25_24_MASK 0x3000000 +#define D0F0x4C_HPDis_OFFSET 26 +#define D0F0x4C_HPDis_WIDTH 1 +#define D0F0x4C_HPDis_MASK 0x4000000 +#define D0F0x4C_Reserved_31_27_OFFSET 27 +#define D0F0x4C_Reserved_31_27_WIDTH 5 +#define D0F0x4C_Reserved_31_27_MASK 0xf8000000 + +/// D0F0x4C +typedef union { + struct { ///< + UINT32 Function1Enable:1 ; ///< + UINT32 ApicEnable:1 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 Cf8Dis:1 ; ///< + UINT32 PMEDis:1 ; ///< + UINT32 SerrDis:1 ; ///< + UINT32 Reserved_10_6:5 ; ///< + UINT32 CRS:1 ; ///< + UINT32 CfgRdTime:3 ; ///< + UINT32 Reserved_22_15:8 ; ///< + UINT32 MMIOEnable:1 ; ///< + UINT32 Reserved_25_24:2 ; ///< + UINT32 HPDis:1 ; ///< + UINT32 Reserved_31_27:5 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x4C_STRUCT; + +// **** D0F0x60 Register Definition **** +// Address +#define D0F0x60_ADDRESS 0x60 + +// Type +#define D0F0x60_TYPE TYPE_D0F0 +// Field Data +#define D0F0x60_MiscIndAddr_OFFSET 0 +#define D0F0x60_MiscIndAddr_WIDTH 7 +#define D0F0x60_MiscIndAddr_MASK 0x7f +#define D0F0x60_MiscIndWrEn_OFFSET 7 +#define D0F0x60_MiscIndWrEn_WIDTH 1 +#define D0F0x60_MiscIndWrEn_MASK 0x80 +#define D0F0x60_Reserved_31_8_OFFSET 8 +#define D0F0x60_Reserved_31_8_WIDTH 24 +#define D0F0x60_Reserved_31_8_MASK 0xffffff00 + +/// D0F0x60 +typedef union { + struct { ///< + UINT32 MiscIndAddr:7 ; ///< + UINT32 MiscIndWrEn:1 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x60_STRUCT; + +// **** D0F0x64 Register Definition **** +// Address +#define D0F0x64_ADDRESS 0x64 + +// Type +#define D0F0x64_TYPE TYPE_D0F0 +// Field Data +#define D0F0x64_MiscIndData_OFFSET 0 +#define D0F0x64_MiscIndData_WIDTH 32 +#define D0F0x64_MiscIndData_MASK 0xffffffff + +/// D0F0x64 +typedef union { + struct { ///< + UINT32 MiscIndData:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_STRUCT; + + +/// D0F0x78 +typedef union { + struct { ///< + UINT32 Scratch:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x78_STRUCT; + +// **** D0F0x7C Register Definition **** +// Address +#define D0F0x7C_ADDRESS 0x7c + +// Type +#define D0F0x7C_TYPE TYPE_D0F0 +// Field Data +#define D0F0x7C_ForceIntGFXDisable_OFFSET 0 +#define D0F0x7C_ForceIntGFXDisable_WIDTH 1 +#define D0F0x7C_ForceIntGFXDisable_MASK 0x1 +#define D0F0x7C_Reserved_31_1_OFFSET 1 +#define D0F0x7C_Reserved_31_1_WIDTH 31 +#define D0F0x7C_Reserved_31_1_MASK 0xfffffffe + +/// D0F0x7C +typedef union { + struct { ///< + UINT32 ForceIntGFXDisable:1 ; ///< + UINT32 Reserved_31_1:31; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x7C_STRUCT; + +// **** D0F0x84 Register Definition **** +// Address +#define D0F0x84_ADDRESS 0x84 + +// Type +#define D0F0x84_TYPE TYPE_D0F0 +// Field Data +#define D0F0x84_Reserved_3_0_OFFSET 0 +#define D0F0x84_Reserved_3_0_WIDTH 4 +#define D0F0x84_Reserved_3_0_MASK 0xf +#define D0F0x84_Ev6Mode_OFFSET 4 +#define D0F0x84_Ev6Mode_WIDTH 1 +#define D0F0x84_Ev6Mode_MASK 0x10 +#define D0F0x84_Reserved_7_5_OFFSET 5 +#define D0F0x84_Reserved_7_5_WIDTH 3 +#define D0F0x84_Reserved_7_5_MASK 0xe0 +#define D0F0x84_PmeMode_OFFSET 8 +#define D0F0x84_PmeMode_WIDTH 1 +#define D0F0x84_PmeMode_MASK 0x100 +#define D0F0x84_PmeTurnOff_OFFSET 9 +#define D0F0x84_PmeTurnOff_WIDTH 1 +#define D0F0x84_PmeTurnOff_MASK 0x200 +#define D0F0x84_Reserved_31_10_OFFSET 10 +#define D0F0x84_Reserved_31_10_WIDTH 22 +#define D0F0x84_Reserved_31_10_MASK 0xfffffc00 + +/// D0F0x84 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 Ev6Mode:1 ; ///< + UINT32 Reserved_7_5:3 ; ///< + UINT32 PmeMode:1 ; ///< + UINT32 PmeTurnOff:1 ; ///< + UINT32 Reserved_31_10:22; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x84_STRUCT; + +// **** D0F0x90 Register Definition **** +// Address +#define D0F0x90_ADDRESS 0x90 + +// Type +#define D0F0x90_TYPE TYPE_D0F0 +// Field Data +#define D0F0x90_Reserved_22_0_OFFSET 0 +#define D0F0x90_Reserved_22_0_WIDTH 23 +#define D0F0x90_Reserved_22_0_MASK 0x7fffff +#define D0F0x90_TopOfDram_OFFSET 23 +#define D0F0x90_TopOfDram_WIDTH 9 +#define D0F0x90_TopOfDram_MASK 0xff800000 + +/// D0F0x90 +typedef union { + struct { ///< + UINT32 Reserved_22_0:23; ///< + UINT32 TopOfDram:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x90_STRUCT; + +// **** D0F0x94 Register Definition **** +// Address +#define D0F0x94_ADDRESS 0x94 + +// Type +#define D0F0x94_TYPE TYPE_D0F0 +// Field Data +#define D0F0x94_OrbIndAddr_OFFSET 0 +#define D0F0x94_OrbIndAddr_WIDTH 7 +#define D0F0x94_OrbIndAddr_MASK 0x7f +#define D0F0x94_Reserved_7_7_OFFSET 7 +#define D0F0x94_Reserved_7_7_WIDTH 1 +#define D0F0x94_Reserved_7_7_MASK 0x80 +#define D0F0x94_OrbIndWrEn_OFFSET 8 +#define D0F0x94_OrbIndWrEn_WIDTH 1 +#define D0F0x94_OrbIndWrEn_MASK 0x100 +#define D0F0x94_Reserved_31_9_OFFSET 9 +#define D0F0x94_Reserved_31_9_WIDTH 23 +#define D0F0x94_Reserved_31_9_MASK 0xfffffe00 + +/// D0F0x94 +typedef union { + struct { ///< + UINT32 OrbIndAddr:7 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 OrbIndWrEn:1 ; ///< + UINT32 Reserved_31_9:23; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x94_STRUCT; + +// **** D0F0x98 Register Definition **** +// Address +#define D0F0x98_ADDRESS 0x98 + +// Type +#define D0F0x98_TYPE TYPE_D0F0 +// Field Data +#define D0F0x98_OrbIndData_OFFSET 0 +#define D0F0x98_OrbIndData_WIDTH 32 +#define D0F0x98_OrbIndData_MASK 0xffffffff + +/// D0F0x98 +typedef union { + struct { ///< + UINT32 OrbIndData:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_STRUCT; + +// **** D0F0xE0 Register Definition **** +// Address +#define D0F0xE0_ADDRESS 0xe0 + +// Type +#define D0F0xE0_TYPE TYPE_D0F0 +// Field Data +#define D0F0xE0_PcieIndxAddr_OFFSET 0 +#define D0F0xE0_PcieIndxAddr_WIDTH 16 +#define D0F0xE0_PcieIndxAddr_MASK 0xffff +#define D0F0xE0_FrameType_OFFSET 16 +#define D0F0xE0_FrameType_WIDTH 8 +#define D0F0xE0_FrameType_MASK 0xff0000 +#define D0F0xE0_BlockSelect_OFFSET 24 +#define D0F0xE0_BlockSelect_WIDTH 8 +#define D0F0xE0_BlockSelect_MASK 0xff000000 + +/// D0F0xE0 +typedef union { + struct { ///< + UINT32 PcieIndxAddr:16; ///< + UINT32 FrameType:8 ; ///< + UINT32 BlockSelect:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE0_STRUCT; + +// **** D0F0xE4 Register Definition **** +// Address +#define D0F0xE4_ADDRESS 0xe4 + +// Type +#define D0F0xE4_TYPE TYPE_D0F0 +// Field Data +#define D0F0xE4_PcieIndxData_OFFSET 0 +#define D0F0xE4_PcieIndxData_WIDTH 32 +#define D0F0xE4_PcieIndxData_MASK 0xffffffff + +/// D0F0xE4 +typedef union { + struct { ///< + UINT32 PcieIndxData:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_STRUCT; + +// **** D18F1xF0 Register Definition **** +// Address +#define D18F1xF0_ADDRESS 0xf0 + +// Type +#define D18F1xF0_TYPE TYPE_D18F1 +// Field Data +#define D18F1xF0_DramHoleValid_OFFSET 0 +#define D18F1xF0_DramHoleValid_WIDTH 1 +#define D18F1xF0_DramHoleValid_MASK 0x1 +#define D18F1xF0_Reserved_6_1_OFFSET 1 +#define D18F1xF0_Reserved_6_1_WIDTH 6 +#define D18F1xF0_Reserved_6_1_MASK 0x7e +#define D18F1xF0_DramHoleOffset_31_23__OFFSET 7 +#define D18F1xF0_DramHoleOffset_31_23__WIDTH 9 +#define D18F1xF0_DramHoleOffset_31_23__MASK 0xff80 +#define D18F1xF0_Reserved_23_16_OFFSET 16 +#define D18F1xF0_Reserved_23_16_WIDTH 8 +#define D18F1xF0_Reserved_23_16_MASK 0xff0000 +#define D18F1xF0_DramHoleBase_31_24__OFFSET 24 +#define D18F1xF0_DramHoleBase_31_24__WIDTH 8 +#define D18F1xF0_DramHoleBase_31_24__MASK 0xff000000 + +/// D18F1xF0 +typedef union { + struct { ///< + UINT32 DramHoleValid:1 ; ///< + UINT32 Reserved_6_1:6 ; ///< + UINT32 DramHoleOffset_31_23_:9 ; ///< + UINT32 Reserved_23_16:8 ; ///< + UINT32 DramHoleBase_31_24_:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1xF0_STRUCT; + +// **** D18F2x00 Register Definition **** +// Address +#define D18F2x00_ADDRESS 0x0 + +// Type +#define D18F2x00_TYPE TYPE_D18F2 +// Field Data +#define D18F2x00_VendorID_OFFSET 0 +#define D18F2x00_VendorID_WIDTH 16 +#define D18F2x00_VendorID_MASK 0xffff +#define D18F2x00_DeviceID_OFFSET 16 +#define D18F2x00_DeviceID_WIDTH 16 +#define D18F2x00_DeviceID_MASK 0xffff0000 + +/// D18F2x00 +typedef union { + struct { ///< + UINT32 VendorID:16; ///< + UINT32 DeviceID:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x00_STRUCT; + + +// **** D18F2x08 Register Definition **** +// Address +#define D18F2x08_ADDRESS 0x8 + +// Type +#define D18F2x08_TYPE TYPE_D18F2 +// Field Data +#define D18F2x08_RevID_OFFSET 0 +#define D18F2x08_RevID_WIDTH 8 +#define D18F2x08_RevID_MASK 0xff +#define D18F2x08_ClassCode_OFFSET 8 +#define D18F2x08_ClassCode_WIDTH 24 +#define D18F2x08_ClassCode_MASK 0xffffff00 + +/// D18F2x08 +typedef union { + struct { ///< + UINT32 RevID:8 ; ///< + UINT32 ClassCode:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x08_STRUCT; + +// **** D18F2x0C Register Definition **** +// Address +#define D18F2x0C_ADDRESS 0xc + +// Type +#define D18F2x0C_TYPE TYPE_D18F2 +// Field Data +#define D18F2x0C_HeaderTypeReg_OFFSET 0 +#define D18F2x0C_HeaderTypeReg_WIDTH 32 +#define D18F2x0C_HeaderTypeReg_MASK 0xffffffff + +/// D18F2x0C +typedef union { + struct { ///< + UINT32 HeaderTypeReg:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x0C_STRUCT; + + +// **** D18F2x040 Register Definition **** +// Address +#define D18F2x040_ADDRESS 0x40 + +// Type +#define D18F2x040_TYPE TYPE_D18F2 +// Field Data +#define D18F2x040_CSEnable_OFFSET 0 +#define D18F2x040_CSEnable_WIDTH 1 +#define D18F2x040_CSEnable_MASK 0x1 +#define D18F2x040_Reserved_1_1_OFFSET 1 +#define D18F2x040_Reserved_1_1_WIDTH 1 +#define D18F2x040_Reserved_1_1_MASK 0x2 +#define D18F2x040_TestFail_OFFSET 2 +#define D18F2x040_TestFail_WIDTH 1 +#define D18F2x040_TestFail_MASK 0x4 +#define D18F2x040_OnDimmMirror_OFFSET 3 +#define D18F2x040_OnDimmMirror_WIDTH 1 +#define D18F2x040_OnDimmMirror_MASK 0x8 +#define D18F2x040_Reserved_4_4_OFFSET 4 +#define D18F2x040_Reserved_4_4_WIDTH 1 +#define D18F2x040_Reserved_4_4_MASK 0x10 +#define D18F2x040_Reserved_31_29_OFFSET 29 +#define D18F2x040_Reserved_31_29_WIDTH 3 +#define D18F2x040_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x040 +typedef union { + struct { ///< + UINT32 CSEnable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 TestFail:1 ; ///< + UINT32 OnDimmMirror:1 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 :9 ; ///< + UINT32 Reserved_18_14:5 ; ///< + UINT32 :10; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x040_STRUCT; + +// **** D18F2x044 Register Definition **** +// Address +#define D18F2x044_ADDRESS 0x44 + +// Type +#define D18F2x044_TYPE TYPE_D18F2 +// Field Data +#define D18F2x044_CSEnable_OFFSET 0 +#define D18F2x044_CSEnable_WIDTH 1 +#define D18F2x044_CSEnable_MASK 0x1 +#define D18F2x044_Reserved_1_1_OFFSET 1 +#define D18F2x044_Reserved_1_1_WIDTH 1 +#define D18F2x044_Reserved_1_1_MASK 0x2 +#define D18F2x044_TestFail_OFFSET 2 +#define D18F2x044_TestFail_WIDTH 1 +#define D18F2x044_TestFail_MASK 0x4 +#define D18F2x044_OnDimmMirror_OFFSET 3 +#define D18F2x044_OnDimmMirror_WIDTH 1 +#define D18F2x044_OnDimmMirror_MASK 0x8 +#define D18F2x044_Reserved_4_4_OFFSET 4 +#define D18F2x044_Reserved_4_4_WIDTH 1 +#define D18F2x044_Reserved_4_4_MASK 0x10 +#define D18F2x044_Reserved_31_29_OFFSET 29 +#define D18F2x044_Reserved_31_29_WIDTH 3 +#define D18F2x044_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x044 +typedef union { + struct { ///< + UINT32 CSEnable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 TestFail:1 ; ///< + UINT32 OnDimmMirror:1 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 :9 ; ///< + UINT32 Reserved_18_14:5 ; ///< + UINT32 :10; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x044_STRUCT; + +// **** D18F2x048 Register Definition **** +// Address +#define D18F2x048_ADDRESS 0x48 + +// Type +#define D18F2x048_TYPE TYPE_D18F2 +// Field Data +#define D18F2x048_CSEnable_OFFSET 0 +#define D18F2x048_CSEnable_WIDTH 1 +#define D18F2x048_CSEnable_MASK 0x1 +#define D18F2x048_Reserved_1_1_OFFSET 1 +#define D18F2x048_Reserved_1_1_WIDTH 1 +#define D18F2x048_Reserved_1_1_MASK 0x2 +#define D18F2x048_TestFail_OFFSET 2 +#define D18F2x048_TestFail_WIDTH 1 +#define D18F2x048_TestFail_MASK 0x4 +#define D18F2x048_OnDimmMirror_OFFSET 3 +#define D18F2x048_OnDimmMirror_WIDTH 1 +#define D18F2x048_OnDimmMirror_MASK 0x8 +#define D18F2x048_Reserved_4_4_OFFSET 4 +#define D18F2x048_Reserved_4_4_WIDTH 1 +#define D18F2x048_Reserved_4_4_MASK 0x10 +#define D18F2x048_Reserved_31_29_OFFSET 29 +#define D18F2x048_Reserved_31_29_WIDTH 3 +#define D18F2x048_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x048 +typedef union { + struct { ///< + UINT32 CSEnable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 TestFail:1 ; ///< + UINT32 OnDimmMirror:1 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 :9 ; ///< + UINT32 Reserved_18_14:5 ; ///< + UINT32 :10; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x048_STRUCT; + +// **** D18F2x04C Register Definition **** +// Address +#define D18F2x04C_ADDRESS 0x4c + +// Type +#define D18F2x04C_TYPE TYPE_D18F2 +// Field Data +#define D18F2x04C_CSEnable_OFFSET 0 +#define D18F2x04C_CSEnable_WIDTH 1 +#define D18F2x04C_CSEnable_MASK 0x1 +#define D18F2x04C_Reserved_1_1_OFFSET 1 +#define D18F2x04C_Reserved_1_1_WIDTH 1 +#define D18F2x04C_Reserved_1_1_MASK 0x2 +#define D18F2x04C_TestFail_OFFSET 2 +#define D18F2x04C_TestFail_WIDTH 1 +#define D18F2x04C_TestFail_MASK 0x4 +#define D18F2x04C_OnDimmMirror_OFFSET 3 +#define D18F2x04C_OnDimmMirror_WIDTH 1 +#define D18F2x04C_OnDimmMirror_MASK 0x8 +#define D18F2x04C_Reserved_4_4_OFFSET 4 +#define D18F2x04C_Reserved_4_4_WIDTH 1 +#define D18F2x04C_Reserved_4_4_MASK 0x10 +#define D18F2x04C_Reserved_31_29_OFFSET 29 +#define D18F2x04C_Reserved_31_29_WIDTH 3 +#define D18F2x04C_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x04C +typedef union { + struct { ///< + UINT32 CSEnable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 TestFail:1 ; ///< + UINT32 OnDimmMirror:1 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 :9 ; ///< + UINT32 Reserved_18_14:5 ; ///< + UINT32 :10; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x04C_STRUCT; + +// **** D18F2x060 Register Definition **** +// Address +#define D18F2x060_ADDRESS 0x60 + +// Type +#define D18F2x060_TYPE TYPE_D18F2 +// Field Data +#define D18F2x060_Reserved_4_0_OFFSET 0 +#define D18F2x060_Reserved_4_0_WIDTH 5 +#define D18F2x060_Reserved_4_0_MASK 0x1f +#define D18F2x060_Reserved_31_29_OFFSET 29 +#define D18F2x060_Reserved_31_29_WIDTH 3 +#define D18F2x060_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x060 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 :9 ; ///< + UINT32 Reserved_18_14:5 ; ///< + UINT32 :10; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x060_STRUCT; + +// **** D18F2x064 Register Definition **** +// Address +#define D18F2x064_ADDRESS 0x64 + +// Type +#define D18F2x064_TYPE TYPE_D18F2 +// Field Data +#define D18F2x064_Reserved_4_0_OFFSET 0 +#define D18F2x064_Reserved_4_0_WIDTH 5 +#define D18F2x064_Reserved_4_0_MASK 0x1f +#define D18F2x064_Reserved_31_29_OFFSET 29 +#define D18F2x064_Reserved_31_29_WIDTH 3 +#define D18F2x064_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x064 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 :9 ; ///< + UINT32 Reserved_18_14:5 ; ///< + UINT32 :10; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x064_STRUCT; + +// **** D18F2x078 Register Definition **** +// Address +#define D18F2x078_ADDRESS 0x78 + +// Type +#define D18F2x078_TYPE TYPE_D18F2 +// Field Data +#define D18F2x078_Reserved_14_14_OFFSET 14 +#define D18F2x078_Reserved_14_14_WIDTH 1 +#define D18F2x078_Reserved_14_14_MASK 0x4000 +#define D18F2x078_Reserved_15_15_OFFSET 15 +#define D18F2x078_Reserved_15_15_WIDTH 1 +#define D18F2x078_Reserved_15_15_MASK 0x8000 +#define D18F2x078_Reserved_16_16_OFFSET 16 +#define D18F2x078_Reserved_16_16_WIDTH 1 +#define D18F2x078_Reserved_16_16_MASK 0x10000 +#define D18F2x078_AddrCmdTriEn_OFFSET 17 +#define D18F2x078_AddrCmdTriEn_WIDTH 1 +#define D18F2x078_AddrCmdTriEn_MASK 0x20000 +#define D18F2x078_Reserved_18_18_OFFSET 18 +#define D18F2x078_Reserved_18_18_WIDTH 1 +#define D18F2x078_Reserved_18_18_MASK 0x40000 +#define D18F2x078_Reserved_19_19_OFFSET 19 +#define D18F2x078_Reserved_19_19_WIDTH 1 +#define D18F2x078_Reserved_19_19_MASK 0x80000 + +/// D18F2x078 +typedef union { + struct { ///< + UINT32 :4 ; ///< + UINT32 :2 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :2 ; ///< + UINT32 :2 ; ///< + UINT32 :2 ; ///< + UINT32 Reserved_14_14:1 ; ///< + UINT32 Reserved_15_15:1 ; ///< + UINT32 Reserved_16_16:1 ; ///< + UINT32 AddrCmdTriEn:1 ; ///< + UINT32 Reserved_18_18:1 ; ///< + UINT32 Reserved_19_19:1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :10; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x078_STRUCT; + + + +// **** D18F2x084 Register Definition **** +// Address +#define D18F2x084_ADDRESS 0x84 + +// Type +#define D18F2x084_TYPE TYPE_D18F2 +// Field Data +#define D18F2x084_BurstCtrl_OFFSET 0 +#define D18F2x084_BurstCtrl_WIDTH 2 +#define D18F2x084_BurstCtrl_MASK 0x3 +#define D18F2x084_Reserved_3_2_OFFSET 2 +#define D18F2x084_Reserved_3_2_WIDTH 2 +#define D18F2x084_Reserved_3_2_MASK 0xc +#define D18F2x084_Reserved_19_7_OFFSET 7 +#define D18F2x084_Reserved_19_7_WIDTH 13 +#define D18F2x084_Reserved_19_7_MASK 0xfff80 +#define D18F2x084_PchgPDModeSel_OFFSET 23 +#define D18F2x084_PchgPDModeSel_WIDTH 1 +#define D18F2x084_PchgPDModeSel_MASK 0x800000 +#define D18F2x084_Reserved_31_24_OFFSET 24 +#define D18F2x084_Reserved_31_24_WIDTH 8 +#define D18F2x084_Reserved_31_24_MASK 0xff000000 + +/// D18F2x084 +typedef union { + struct { ///< + UINT32 BurstCtrl:2 ; ///< + UINT32 Reserved_3_2:2 ; ///< + UINT32 :3 ; ///< + UINT32 Reserved_19_7:13; ///< + UINT32 :3 ; ///< + UINT32 PchgPDModeSel:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x084_STRUCT; + +// **** D18F2x088 Register Definition **** +// Address +#define D18F2x088_ADDRESS 0x88 + +// Type +#define D18F2x088_TYPE TYPE_D18F2 +// Field Data +#define D18F2x088_Reserved_23_4_OFFSET 4 +#define D18F2x088_Reserved_23_4_WIDTH 20 +#define D18F2x088_Reserved_23_4_MASK 0xfffff0 + +/// D18F2x088 +typedef union { + struct { ///< + UINT32 :4 ; ///< + UINT32 Reserved_23_4:20; ///< + UINT32 :8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x088_STRUCT; + + + + +// **** D18F2x098 Register Definition **** +// Address +#define D18F2x098_ADDRESS 0x98 + +// Type +#define D18F2x098_TYPE TYPE_D18F2 +// Field Data +#define D18F2x098_DctOffset_OFFSET 0 +#define D18F2x098_DctOffset_WIDTH 30 +#define D18F2x098_DctOffset_MASK 0x3fffffff +#define D18F2x098_DctAccessWrite_OFFSET 30 +#define D18F2x098_DctAccessWrite_WIDTH 1 +#define D18F2x098_DctAccessWrite_MASK 0x40000000 +#define D18F2x098_Reserved_31_31_OFFSET 31 +#define D18F2x098_Reserved_31_31_WIDTH 1 +#define D18F2x098_Reserved_31_31_MASK 0x80000000 + +/// D18F2x098 +typedef union { + struct { ///< + UINT32 DctOffset:30; ///< + UINT32 DctAccessWrite:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x098_STRUCT; + +// **** D18F2x09C Register Definition **** +// Address +#define D18F2x09C_ADDRESS 0x9c + +// Type +#define D18F2x09C_TYPE TYPE_D18F2 +// Field Data +#define D18F2x09C_DctDataPort_OFFSET 0 +#define D18F2x09C_DctDataPort_WIDTH 32 +#define D18F2x09C_DctDataPort_MASK 0xffffffff + +/// D18F2x09C +typedef union { + struct { ///< + UINT32 DctDataPort:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_STRUCT; + + +// **** D18F2xA4 Register Definition **** +// Address +#define D18F2xA4_ADDRESS 0xa4 + +// Type +#define D18F2xA4_TYPE TYPE_D18F2 +// Field Data +#define D18F2xA4_DoubleTrefRateEn_OFFSET 0 +#define D18F2xA4_DoubleTrefRateEn_WIDTH 1 + + +// **** D18F2xAC Register Definition **** +// Address +#define D18F2xAC_ADDRESS 0xac + +// Type +#define D18F2xAC_TYPE TYPE_D18F2 +// Field Data +#define D18F2xAC_Reserved_31_1_OFFSET 1 +#define D18F2xAC_Reserved_31_1_WIDTH 31 +#define D18F2xAC_Reserved_31_1_MASK 0xfffffffe + +/// D18F2xAC +typedef union { + struct { ///< + UINT32 MemTempHot:1 ; ///< + UINT32 Reserved_31_1:31; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xAC_STRUCT; + + + +// **** D18F2x114 Register Definition **** +// Address +#define D18F2x114_ADDRESS 0x114 + +// Type +#define D18F2x114_TYPE TYPE_D18F2 +// Field Data +#define D18F2x114_Reserved_8_0_OFFSET 0 +#define D18F2x114_Reserved_8_0_WIDTH 9 +#define D18F2x114_Reserved_8_0_MASK 0x1ff +#define D18F2x114_DctSelIntLvAddr_2__OFFSET 9 +#define D18F2x114_DctSelIntLvAddr_2__WIDTH 1 +#define D18F2x114_DctSelIntLvAddr_2__MASK 0x200 + +/// D18F2x114 +typedef union { + struct { ///< + UINT32 Reserved_8_0:9 ; ///< + UINT32 DctSelIntLvAddr_2_:1 ; ///< + UINT32 :14; ///< + UINT32 :8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x114_STRUCT; + + +// **** D18F3x00 Register Definition **** +// Address +#define D18F3x00_ADDRESS 0x0 + +// Type +#define D18F3x00_TYPE TYPE_D18F3 +// Field Data +#define D18F3x00_VendorID_OFFSET 0 +#define D18F3x00_VendorID_WIDTH 16 +#define D18F3x00_VendorID_MASK 0xffff +#define D18F3x00_DeviceID_OFFSET 16 +#define D18F3x00_DeviceID_WIDTH 16 +#define D18F3x00_DeviceID_MASK 0xffff0000 + +/// D18F3x00 +typedef union { + struct { ///< + UINT32 VendorID:16; ///< + UINT32 DeviceID:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x00_STRUCT; + +// **** D18F3x04 Register Definition **** +// Address +#define D18F3x04_ADDRESS 0x4 + +// Type +#define D18F3x04_TYPE TYPE_D18F3 +// Field Data +#define D18F3x04_Command_OFFSET 0 +#define D18F3x04_Command_WIDTH 16 +#define D18F3x04_Command_MASK 0xffff +#define D18F3x04_Status_OFFSET 16 +#define D18F3x04_Status_WIDTH 16 +#define D18F3x04_Status_MASK 0xffff0000 + +/// D18F3x04 +typedef union { + struct { ///< + UINT32 Command:16; ///< + UINT32 Status:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x04_STRUCT; + +// **** D18F3x08 Register Definition **** +// Address +#define D18F3x08_ADDRESS 0x8 + +// Type +#define D18F3x08_TYPE TYPE_D18F3 +// Field Data +#define D18F3x08_RevID_OFFSET 0 +#define D18F3x08_RevID_WIDTH 8 +#define D18F3x08_RevID_MASK 0xff +#define D18F3x08_ClassCode_OFFSET 8 +#define D18F3x08_ClassCode_WIDTH 24 +#define D18F3x08_ClassCode_MASK 0xffffff00 + +/// D18F3x08 +typedef union { + struct { ///< + UINT32 RevID:8 ; ///< + UINT32 ClassCode:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x08_STRUCT; + +// **** D18F3x0C Register Definition **** +// Address +#define D18F3x0C_ADDRESS 0xc + +// Type +#define D18F3x0C_TYPE TYPE_D18F3 +// Field Data +#define D18F3x0C_HeaderTypeReg_OFFSET 0 +#define D18F3x0C_HeaderTypeReg_WIDTH 32 +#define D18F3x0C_HeaderTypeReg_MASK 0xffffffff + +/// D18F3x0C +typedef union { + struct { ///< + UINT32 HeaderTypeReg:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x0C_STRUCT; + +// **** D18F3x34 Register Definition **** +// Address +#define D18F3x34_ADDRESS 0x34 + +// Type +#define D18F3x34_TYPE TYPE_D18F3 +// Field Data +#define D18F3x34_CapPtr_OFFSET 0 +#define D18F3x34_CapPtr_WIDTH 8 +#define D18F3x34_CapPtr_MASK 0xff +#define D18F3x34_Reserved_31_8_OFFSET 8 +#define D18F3x34_Reserved_31_8_WIDTH 24 +#define D18F3x34_Reserved_31_8_MASK 0xffffff00 + +/// D18F3x34 +typedef union { + struct { ///< + UINT32 CapPtr:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x34_STRUCT; + + +// **** D18F3x48 Register Definition **** +// Address +#define D18F3x48_ADDRESS 0x48 + +// Type +#define D18F3x48_TYPE TYPE_D18F3 +// Field Data +#define D18F3x48_ErrorCode_OFFSET 0 +#define D18F3x48_ErrorCode_WIDTH 16 +#define D18F3x48_ErrorCode_MASK 0xffff +#define D18F3x48_ErrorCodeExt_OFFSET 16 +#define D18F3x48_ErrorCodeExt_WIDTH 5 +#define D18F3x48_ErrorCodeExt_MASK 0x1f0000 +#define D18F3x48_Reserved_31_21_OFFSET 21 +#define D18F3x48_Reserved_31_21_WIDTH 11 +#define D18F3x48_Reserved_31_21_MASK 0xffe00000 + +/// D18F3x48 +typedef union { + struct { ///< + UINT32 ErrorCode:16; ///< + UINT32 ErrorCodeExt:5 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x48_STRUCT; + + +// **** D18F3x64 Register Definition **** +// Address +#define D18F3x64_ADDRESS 0x64 + +// Type +#define D18F3x64_TYPE TYPE_D18F3 +// Field Data +#define D18F3x64_HtcEn_OFFSET 0 +#define D18F3x64_HtcEn_WIDTH 1 +#define D18F3x64_HtcEn_MASK 0x1 +#define D18F3x64_Reserved_3_1_OFFSET 1 +#define D18F3x64_Reserved_3_1_WIDTH 3 +#define D18F3x64_Reserved_3_1_MASK 0xe +#define D18F3x64_HtcAct_OFFSET 4 +#define D18F3x64_HtcAct_WIDTH 1 +#define D18F3x64_HtcAct_MASK 0x10 +#define D18F3x64_HtcActSts_OFFSET 5 +#define D18F3x64_HtcActSts_WIDTH 1 +#define D18F3x64_HtcActSts_MASK 0x20 +#define D18F3x64_PslApicHiEn_OFFSET 6 +#define D18F3x64_PslApicHiEn_WIDTH 1 +#define D18F3x64_PslApicHiEn_MASK 0x40 +#define D18F3x64_PslApicLoEn_OFFSET 7 +#define D18F3x64_PslApicLoEn_WIDTH 1 +#define D18F3x64_PslApicLoEn_MASK 0x80 +#define D18F3x64_Reserved_15_8_OFFSET 8 +#define D18F3x64_Reserved_15_8_WIDTH 8 +#define D18F3x64_Reserved_15_8_MASK 0xff00 +#define D18F3x64_HtcTmpLmt_OFFSET 16 +#define D18F3x64_HtcTmpLmt_WIDTH 7 +#define D18F3x64_HtcTmpLmt_MASK 0x7f0000 +#define D18F3x64_HtcSlewSel_OFFSET 23 +#define D18F3x64_HtcSlewSel_WIDTH 1 +#define D18F3x64_HtcSlewSel_MASK 0x800000 +#define D18F3x64_HtcHystLmt_OFFSET 24 +#define D18F3x64_HtcHystLmt_WIDTH 4 +#define D18F3x64_HtcHystLmt_MASK 0xf000000 +#define D18F3x64_HtcPstateLimit_OFFSET 28 +#define D18F3x64_HtcPstateLimit_WIDTH 3 +#define D18F3x64_HtcPstateLimit_MASK 0x70000000 + +/// D18F3x64 +typedef union { + struct { ///< + UINT32 HtcEn:1 ; ///< + UINT32 Reserved_3_1:3 ; ///< + UINT32 HtcAct:1 ; ///< + UINT32 HtcActSts:1 ; ///< + UINT32 PslApicHiEn:1 ; ///< + UINT32 PslApicLoEn:1 ; ///< + UINT32 Reserved_15_8:8 ; ///< + UINT32 HtcTmpLmt:7 ; ///< + UINT32 HtcSlewSel:1 ; ///< + UINT32 HtcHystLmt:4 ; ///< + UINT32 HtcPstateLimit:3 ; ///< + UINT32 :1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x64_STRUCT; + + +// **** D18F3x88 Register Definition **** +// Address +#define D18F3x88_ADDRESS 0x88 + +// Type +#define D18F3x88_TYPE TYPE_D18F3 +// Field Data +#define D18F3x88_Reserved_31_0_OFFSET 0 +#define D18F3x88_Reserved_31_0_WIDTH 32 +#define D18F3x88_Reserved_31_0_MASK 0xffffffff + +/// D18F3x88 +typedef union { + struct { ///< + UINT32 Reserved_31_0:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x88_STRUCT; + + +// **** D18F3xE4 Register Definition **** +// Address +#define D18F3xE4_ADDRESS 0xe4 + +// Type +#define D18F3xE4_TYPE TYPE_D18F3 +// Field Data +#define D18F3xE4_Reserved_0_0_OFFSET 0 +#define D18F3xE4_Reserved_0_0_WIDTH 1 +#define D18F3xE4_Reserved_0_0_MASK 0x1 +#define D18F3xE4_Thermtp_OFFSET 1 +#define D18F3xE4_Thermtp_WIDTH 1 +#define D18F3xE4_Thermtp_MASK 0x2 +#define D18F3xE4_Reserved_2_2_OFFSET 2 +#define D18F3xE4_Reserved_2_2_WIDTH 1 +#define D18F3xE4_Reserved_2_2_MASK 0x4 +#define D18F3xE4_ThermtpSense_OFFSET 3 +#define D18F3xE4_ThermtpSense_WIDTH 1 +#define D18F3xE4_ThermtpSense_MASK 0x8 +#define D18F3xE4_Reserved_4_4_OFFSET 4 +#define D18F3xE4_Reserved_4_4_WIDTH 1 +#define D18F3xE4_Reserved_4_4_MASK 0x10 +#define D18F3xE4_ThermtpEn_OFFSET 5 +#define D18F3xE4_ThermtpEn_WIDTH 1 +#define D18F3xE4_ThermtpEn_MASK 0x20 +#define D18F3xE4_Reserved_7_6_OFFSET 6 +#define D18F3xE4_Reserved_7_6_WIDTH 2 +#define D18F3xE4_Reserved_7_6_MASK 0xc0 +#define D18F3xE4_Reserved_30_8_OFFSET 8 +#define D18F3xE4_Reserved_30_8_WIDTH 23 +#define D18F3xE4_Reserved_30_8_MASK 0x7fffff00 +#define D18F3xE4_SwThermtp_OFFSET 31 +#define D18F3xE4_SwThermtp_WIDTH 1 +#define D18F3xE4_SwThermtp_MASK 0x80000000 + +/// D18F3xE4 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 Thermtp:1 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 ThermtpSense:1 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 ThermtpEn:1 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 Reserved_30_8:23; ///< + UINT32 SwThermtp:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3xE4_STRUCT; + + +// **** D18F3xF0 Register Definition **** +// Address +#define D18F3xF0_ADDRESS 0xf0 + +// Type +#define D18F3xF0_TYPE TYPE_D18F3 +// Field Data +#define D18F3xF0_Reserved_31_0_OFFSET 0 +#define D18F3xF0_Reserved_31_0_WIDTH 32 +#define D18F3xF0_Reserved_31_0_MASK 0xffffffff + +/// D18F3xF0 +typedef union { + struct { ///< + UINT32 Reserved_31_0:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3xF0_STRUCT; + +// **** D18F3xF4 Register Definition **** +// Address +#define D18F3xF4_ADDRESS 0xf4 + +// Type +#define D18F3xF4_TYPE TYPE_D18F3 +// Field Data +#define D18F3xF4_Reserved_31_0_OFFSET 0 +#define D18F3xF4_Reserved_31_0_WIDTH 32 +#define D18F3xF4_Reserved_31_0_MASK 0xffffffff + +/// D18F3xF4 +typedef union { + struct { ///< + UINT32 Reserved_31_0:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3xF4_STRUCT; + +// **** D18F3xF8 Register Definition **** +// Address +#define D18F3xF8_ADDRESS 0xf8 + +// Type +#define D18F3xF8_TYPE TYPE_D18F3 +// Field Data +#define D18F3xF8_Reserved_31_0_OFFSET 0 +#define D18F3xF8_Reserved_31_0_WIDTH 32 +#define D18F3xF8_Reserved_31_0_MASK 0xffffffff + +/// D18F3xF8 +typedef union { + struct { ///< + UINT32 Reserved_31_0:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3xF8_STRUCT; + +// **** D18F3xFC Register Definition **** +// Address +#define D18F3xFC_ADDRESS 0xfc + +// Type +#define D18F3xFC_TYPE TYPE_D18F3 +// Field Data +#define D18F3xFC_Stepping_OFFSET 0 +#define D18F3xFC_Stepping_WIDTH 4 +#define D18F3xFC_Stepping_MASK 0xf +#define D18F3xFC_BaseModel_OFFSET 4 +#define D18F3xFC_BaseModel_WIDTH 4 +#define D18F3xFC_BaseModel_MASK 0xf0 +#define D18F3xFC_BaseFamily_OFFSET 8 +#define D18F3xFC_BaseFamily_WIDTH 4 +#define D18F3xFC_BaseFamily_MASK 0xf00 +#define D18F3xFC_Reserved_15_12_OFFSET 12 +#define D18F3xFC_Reserved_15_12_WIDTH 4 +#define D18F3xFC_Reserved_15_12_MASK 0xf000 +#define D18F3xFC_ExtModel_OFFSET 16 +#define D18F3xFC_ExtModel_WIDTH 4 +#define D18F3xFC_ExtModel_MASK 0xf0000 +#define D18F3xFC_ExtFamily_OFFSET 20 +#define D18F3xFC_ExtFamily_WIDTH 8 +#define D18F3xFC_ExtFamily_MASK 0xff00000 +#define D18F3xFC_Reserved_31_28_OFFSET 28 +#define D18F3xFC_Reserved_31_28_WIDTH 4 +#define D18F3xFC_Reserved_31_28_MASK 0xf0000000 + +/// D18F3xFC +typedef union { + struct { ///< + UINT32 Stepping:4 ; ///< + UINT32 BaseModel:4 ; ///< + UINT32 BaseFamily:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 ExtModel:4 ; ///< + UINT32 ExtFamily:8 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3xFC_STRUCT; + + + + + + + +// **** D18F3x1CC Register Definition **** +// Address +#define D18F3x1CC_ADDRESS 0x1cc + +// Type +#define D18F3x1CC_TYPE TYPE_D18F3 +// Field Data +#define D18F3x1CC_LvtOffset_OFFSET 0 +#define D18F3x1CC_LvtOffset_WIDTH 4 +#define D18F3x1CC_LvtOffset_MASK 0xf +#define D18F3x1CC_Reserved_7_4_OFFSET 4 +#define D18F3x1CC_Reserved_7_4_WIDTH 4 +#define D18F3x1CC_Reserved_7_4_MASK 0xf0 +#define D18F3x1CC_LvtOffsetVal_OFFSET 8 +#define D18F3x1CC_LvtOffsetVal_WIDTH 1 +#define D18F3x1CC_LvtOffsetVal_MASK 0x100 +#define D18F3x1CC_Reserved_31_9_OFFSET 9 +#define D18F3x1CC_Reserved_31_9_WIDTH 23 +#define D18F3x1CC_Reserved_31_9_MASK 0xfffffe00 + +/// D18F3x1CC +typedef union { + struct { ///< + UINT32 LvtOffset:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 LvtOffsetVal:1 ; ///< + UINT32 Reserved_31_9:23; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x1CC_STRUCT; + + + + + + + + + + + +// **** DxF0x00 Register Definition **** +// Address +#define DxF0x00_ADDRESS 0x0 + +// Type +#define DxF0x00_TYPE TYPE_D4F0 +// Field Data +#define DxF0x00_VendorID_OFFSET 0 +#define DxF0x00_VendorID_WIDTH 16 +#define DxF0x00_VendorID_MASK 0xffff +#define DxF0x00_DeviceID_OFFSET 16 +#define DxF0x00_DeviceID_WIDTH 16 +#define DxF0x00_DeviceID_MASK 0xffff0000 + +/// DxF0x00 +typedef union { + struct { ///< + UINT32 VendorID:16; ///< + UINT32 DeviceID:16; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x00_STRUCT; + + +// **** DxF0x08 Register Definition **** +// Address +#define DxF0x08_ADDRESS 0x8 + +// Type +#define DxF0x08_TYPE TYPE_D4F0 +// Field Data +#define DxF0x08_RevID_OFFSET 0 +#define DxF0x08_RevID_WIDTH 8 +#define DxF0x08_RevID_MASK 0xff +#define DxF0x08_ClassCode_OFFSET 8 +#define DxF0x08_ClassCode_WIDTH 24 +#define DxF0x08_ClassCode_MASK 0xffffff00 + +/// DxF0x08 +typedef union { + struct { ///< + UINT32 RevID:8 ; ///< + UINT32 ClassCode:24; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x08_STRUCT; + +// **** DxF0x0C Register Definition **** +// Address +#define DxF0x0C_ADDRESS 0xc + +// Type +#define DxF0x0C_TYPE TYPE_D4F0 +// Field Data +#define DxF0x0C_CacheLineSize_OFFSET 0 +#define DxF0x0C_CacheLineSize_WIDTH 8 +#define DxF0x0C_CacheLineSize_MASK 0xff +#define DxF0x0C_LatencyTimer_OFFSET 8 +#define DxF0x0C_LatencyTimer_WIDTH 8 +#define DxF0x0C_LatencyTimer_MASK 0xff00 +#define DxF0x0C_HeaderTypeReg_OFFSET 16 +#define DxF0x0C_HeaderTypeReg_WIDTH 8 +#define DxF0x0C_HeaderTypeReg_MASK 0xff0000 +#define DxF0x0C_BIST_OFFSET 24 +#define DxF0x0C_BIST_WIDTH 8 +#define DxF0x0C_BIST_MASK 0xff000000 + +/// DxF0x0C +typedef union { + struct { ///< + UINT32 CacheLineSize:8 ; ///< + UINT32 LatencyTimer:8 ; ///< + UINT32 HeaderTypeReg:8 ; ///< + UINT32 BIST:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x0C_STRUCT; + +// **** DxF0x18 Register Definition **** +// Address +#define DxF0x18_ADDRESS 0x18 + +// Type +#define DxF0x18_TYPE TYPE_D4F0 +// Field Data +#define DxF0x18_PrimaryBus_OFFSET 0 +#define DxF0x18_PrimaryBus_WIDTH 8 +#define DxF0x18_PrimaryBus_MASK 0xff +#define DxF0x18_SecondaryBus_OFFSET 8 +#define DxF0x18_SecondaryBus_WIDTH 8 +#define DxF0x18_SecondaryBus_MASK 0xff00 +#define DxF0x18_SubBusNumber_OFFSET 16 +#define DxF0x18_SubBusNumber_WIDTH 8 +#define DxF0x18_SubBusNumber_MASK 0xff0000 +#define DxF0x18_SecondaryLatencyTimer_OFFSET 24 +#define DxF0x18_SecondaryLatencyTimer_WIDTH 8 +#define DxF0x18_SecondaryLatencyTimer_MASK 0xff000000 + +/// DxF0x18 +typedef union { + struct { ///< + UINT32 PrimaryBus:8 ; ///< + UINT32 SecondaryBus:8 ; ///< + UINT32 SubBusNumber:8 ; ///< + UINT32 SecondaryLatencyTimer:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x18_STRUCT; + + +// **** DxF0x20 Register Definition **** +// Address +#define DxF0x20_ADDRESS 0x20 + +// Type +#define DxF0x20_TYPE TYPE_D4F0 +// Field Data +#define DxF0x20_Reserved_3_0_OFFSET 0 +#define DxF0x20_Reserved_3_0_WIDTH 4 +#define DxF0x20_Reserved_3_0_MASK 0xf +#define DxF0x20_MemBase_OFFSET 4 +#define DxF0x20_MemBase_WIDTH 12 +#define DxF0x20_MemBase_MASK 0xfff0 +#define DxF0x20_Reserved_19_16_OFFSET 16 +#define DxF0x20_Reserved_19_16_WIDTH 4 +#define DxF0x20_Reserved_19_16_MASK 0xf0000 +#define DxF0x20_MemLimit_OFFSET 20 +#define DxF0x20_MemLimit_WIDTH 12 +#define DxF0x20_MemLimit_MASK 0xfff00000 + +/// DxF0x20 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 MemBase:12; ///< + UINT32 Reserved_19_16:4 ; ///< + UINT32 MemLimit:12; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x20_STRUCT; + +// **** DxF0x24 Register Definition **** +// Address +#define DxF0x24_ADDRESS 0x24 + +// Type +#define DxF0x24_TYPE TYPE_D4F0 +// Field Data +#define DxF0x24_PrefMemBaseR_OFFSET 0 +#define DxF0x24_PrefMemBaseR_WIDTH 4 +#define DxF0x24_PrefMemBaseR_MASK 0xf +#define DxF0x24_PrefMemBase_31_20__OFFSET 4 +#define DxF0x24_PrefMemBase_31_20__WIDTH 12 +#define DxF0x24_PrefMemBase_31_20__MASK 0xfff0 +#define DxF0x24_PrefMemLimitR_OFFSET 16 +#define DxF0x24_PrefMemLimitR_WIDTH 4 +#define DxF0x24_PrefMemLimitR_MASK 0xf0000 +#define DxF0x24_PrefMemLimit_OFFSET 20 +#define DxF0x24_PrefMemLimit_WIDTH 12 +#define DxF0x24_PrefMemLimit_MASK 0xfff00000 + +/// DxF0x24 +typedef union { + struct { ///< + UINT32 PrefMemBaseR:4 ; ///< + UINT32 PrefMemBase_31_20_:12; ///< + UINT32 PrefMemLimitR:4 ; ///< + UINT32 PrefMemLimit:12; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x24_STRUCT; + +// **** DxF0x28 Register Definition **** +// Address +#define DxF0x28_ADDRESS 0x28 + +// Type +#define DxF0x28_TYPE TYPE_D4F0 +// Field Data +#define DxF0x28_PrefMemBase_63_32__OFFSET 0 +#define DxF0x28_PrefMemBase_63_32__WIDTH 32 +#define DxF0x28_PrefMemBase_63_32__MASK 0xffffffff + +/// DxF0x28 +typedef union { + struct { ///< + UINT32 PrefMemBase_63_32_:32; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x28_STRUCT; + +// **** DxF0x2C Register Definition **** +// Address +#define DxF0x2C_ADDRESS 0x2c + +// Type +#define DxF0x2C_TYPE TYPE_D4F0 +// Field Data +#define DxF0x2C_PrefMemLimit_63_32__OFFSET 0 +#define DxF0x2C_PrefMemLimit_63_32__WIDTH 32 +#define DxF0x2C_PrefMemLimit_63_32__MASK 0xffffffff + +/// DxF0x2C +typedef union { + struct { ///< + UINT32 PrefMemLimit_63_32_:32; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x2C_STRUCT; + +// **** DxF0x30 Register Definition **** +// Address +#define DxF0x30_ADDRESS 0x30 + +// Type +#define DxF0x30_TYPE TYPE_D4F0 +// Field Data +#define DxF0x30_IOBase_31_16__OFFSET 0 +#define DxF0x30_IOBase_31_16__WIDTH 16 +#define DxF0x30_IOBase_31_16__MASK 0xffff +#define DxF0x30_IOLimit_31_16__OFFSET 16 +#define DxF0x30_IOLimit_31_16__WIDTH 16 +#define DxF0x30_IOLimit_31_16__MASK 0xffff0000 + +/// DxF0x30 +typedef union { + struct { ///< + UINT32 IOBase_31_16_:16; ///< + UINT32 IOLimit_31_16_:16; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x30_STRUCT; + +// **** DxF0x34 Register Definition **** +// Address +#define DxF0x34_ADDRESS 0x34 + +// Type +#define DxF0x34_TYPE TYPE_D4F0 +// Field Data +#define DxF0x34_CapPtr_OFFSET 0 +#define DxF0x34_CapPtr_WIDTH 8 +#define DxF0x34_CapPtr_MASK 0xff +#define DxF0x34_Reserved_31_8_OFFSET 8 +#define DxF0x34_Reserved_31_8_WIDTH 24 +#define DxF0x34_Reserved_31_8_MASK 0xffffff00 + +/// DxF0x34 +typedef union { + struct { ///< + UINT32 CapPtr:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x34_STRUCT; + +// **** DxF0x3C Register Definition **** +// Address +#define DxF0x3C_ADDRESS 0x3c + +// Type +#define DxF0x3C_TYPE TYPE_D4F0 +// Field Data +#define DxF0x3C_IntLine_OFFSET 0 +#define DxF0x3C_IntLine_WIDTH 8 +#define DxF0x3C_IntLine_MASK 0xff +#define DxF0x3C_IntPin_OFFSET 8 +#define DxF0x3C_IntPin_WIDTH 3 +#define DxF0x3C_IntPin_MASK 0x700 +#define DxF0x3C_IntPinR_OFFSET 11 +#define DxF0x3C_IntPinR_WIDTH 5 +#define DxF0x3C_IntPinR_MASK 0xf800 +#define DxF0x3C_ParityResponseEn_OFFSET 16 +#define DxF0x3C_ParityResponseEn_WIDTH 1 +#define DxF0x3C_ParityResponseEn_MASK 0x10000 +#define DxF0x3C_SerrEn_OFFSET 17 +#define DxF0x3C_SerrEn_WIDTH 1 +#define DxF0x3C_SerrEn_MASK 0x20000 +#define DxF0x3C_IsaEn_OFFSET 18 +#define DxF0x3C_IsaEn_WIDTH 1 +#define DxF0x3C_IsaEn_MASK 0x40000 +#define DxF0x3C_VgaEn_OFFSET 19 +#define DxF0x3C_VgaEn_WIDTH 1 +#define DxF0x3C_VgaEn_MASK 0x80000 +#define DxF0x3C_Vga16En_OFFSET 20 +#define DxF0x3C_Vga16En_WIDTH 1 +#define DxF0x3C_Vga16En_MASK 0x100000 +#define DxF0x3C_MasterAbortMode_OFFSET 21 +#define DxF0x3C_MasterAbortMode_WIDTH 1 +#define DxF0x3C_MasterAbortMode_MASK 0x200000 +#define DxF0x3C_SecondaryBusReset_OFFSET 22 +#define DxF0x3C_SecondaryBusReset_WIDTH 1 +#define DxF0x3C_SecondaryBusReset_MASK 0x400000 +#define DxF0x3C_FastB2BCap_OFFSET 23 +#define DxF0x3C_FastB2BCap_WIDTH 1 +#define DxF0x3C_FastB2BCap_MASK 0x800000 +#define DxF0x3C_Reserved_31_24_OFFSET 24 +#define DxF0x3C_Reserved_31_24_WIDTH 8 +#define DxF0x3C_Reserved_31_24_MASK 0xff000000 + +/// DxF0x3C +typedef union { + struct { ///< + UINT32 IntLine:8 ; ///< + UINT32 IntPin:3 ; ///< + UINT32 IntPinR:5 ; ///< + UINT32 ParityResponseEn:1 ; ///< + UINT32 SerrEn:1 ; ///< + UINT32 IsaEn:1 ; ///< + UINT32 VgaEn:1 ; ///< + UINT32 Vga16En:1 ; ///< + UINT32 MasterAbortMode:1 ; ///< + UINT32 SecondaryBusReset:1 ; ///< + UINT32 FastB2BCap:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x3C_STRUCT; + +// **** DxF0x50 Register Definition **** +// Address +#define DxF0x50_ADDRESS 0x50 + +// Type +#define DxF0x50_TYPE TYPE_D4F0 +// Field Data +#define DxF0x50_CapID_OFFSET 0 +#define DxF0x50_CapID_WIDTH 8 +#define DxF0x50_CapID_MASK 0xff +#define DxF0x50_NextPtr_OFFSET 8 +#define DxF0x50_NextPtr_WIDTH 8 +#define DxF0x50_NextPtr_MASK 0xff00 +#define DxF0x50_Version_OFFSET 16 +#define DxF0x50_Version_WIDTH 3 +#define DxF0x50_Version_MASK 0x70000 +#define DxF0x50_PmeClock_OFFSET 19 +#define DxF0x50_PmeClock_WIDTH 1 +#define DxF0x50_PmeClock_MASK 0x80000 +#define DxF0x50_Reserved_20_20_OFFSET 20 +#define DxF0x50_Reserved_20_20_WIDTH 1 +#define DxF0x50_Reserved_20_20_MASK 0x100000 +#define DxF0x50_DevSpecificInit_OFFSET 21 +#define DxF0x50_DevSpecificInit_WIDTH 1 +#define DxF0x50_DevSpecificInit_MASK 0x200000 +#define DxF0x50_AuxCurrent_OFFSET 22 +#define DxF0x50_AuxCurrent_WIDTH 3 +#define DxF0x50_AuxCurrent_MASK 0x1c00000 +#define DxF0x50_D1Support_OFFSET 25 +#define DxF0x50_D1Support_WIDTH 1 +#define DxF0x50_D1Support_MASK 0x2000000 +#define DxF0x50_D2Support_OFFSET 26 +#define DxF0x50_D2Support_WIDTH 1 +#define DxF0x50_D2Support_MASK 0x4000000 +#define DxF0x50_PmeSupport_OFFSET 27 +#define DxF0x50_PmeSupport_WIDTH 5 +#define DxF0x50_PmeSupport_MASK 0xf8000000 + +/// DxF0x50 +typedef union { + struct { ///< + UINT32 CapID:8 ; ///< + UINT32 NextPtr:8 ; ///< + UINT32 Version:3 ; ///< + UINT32 PmeClock:1 ; ///< + UINT32 Reserved_20_20:1 ; ///< + UINT32 DevSpecificInit:1 ; ///< + UINT32 AuxCurrent:3 ; ///< + UINT32 D1Support:1 ; ///< + UINT32 D2Support:1 ; ///< + UINT32 PmeSupport:5 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x50_STRUCT; + +// **** DxF0x54 Register Definition **** +// Address +#define DxF0x54_ADDRESS 0x54 + +// Type +#define DxF0x54_TYPE TYPE_D4F0 +// Field Data +#define DxF0x54_PowerState_OFFSET 0 +#define DxF0x54_PowerState_WIDTH 2 +#define DxF0x54_PowerState_MASK 0x3 +#define DxF0x54_Reserved_2_2_OFFSET 2 +#define DxF0x54_Reserved_2_2_WIDTH 1 +#define DxF0x54_Reserved_2_2_MASK 0x4 +#define DxF0x54_NoSoftReset_OFFSET 3 +#define DxF0x54_NoSoftReset_WIDTH 1 +#define DxF0x54_NoSoftReset_MASK 0x8 +#define DxF0x54_Reserved_7_4_OFFSET 4 +#define DxF0x54_Reserved_7_4_WIDTH 4 +#define DxF0x54_Reserved_7_4_MASK 0xf0 +#define DxF0x54_PmeEn_OFFSET 8 +#define DxF0x54_PmeEn_WIDTH 1 +#define DxF0x54_PmeEn_MASK 0x100 +#define DxF0x54_DataSelect_OFFSET 9 +#define DxF0x54_DataSelect_WIDTH 4 +#define DxF0x54_DataSelect_MASK 0x1e00 +#define DxF0x54_DataScale_OFFSET 13 +#define DxF0x54_DataScale_WIDTH 2 +#define DxF0x54_DataScale_MASK 0x6000 +#define DxF0x54_PmeStatus_OFFSET 15 +#define DxF0x54_PmeStatus_WIDTH 1 +#define DxF0x54_PmeStatus_MASK 0x8000 +#define DxF0x54_Reserved_21_16_OFFSET 16 +#define DxF0x54_Reserved_21_16_WIDTH 6 +#define DxF0x54_Reserved_21_16_MASK 0x3f0000 +#define DxF0x54_B2B3Support_OFFSET 22 +#define DxF0x54_B2B3Support_WIDTH 1 +#define DxF0x54_B2B3Support_MASK 0x400000 +#define DxF0x54_BusPwrEn_OFFSET 23 +#define DxF0x54_BusPwrEn_WIDTH 1 +#define DxF0x54_BusPwrEn_MASK 0x800000 +#define DxF0x54_PmeData_OFFSET 24 +#define DxF0x54_PmeData_WIDTH 8 +#define DxF0x54_PmeData_MASK 0xff000000 + +/// DxF0x54 +typedef union { + struct { ///< + UINT32 PowerState:2 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 NoSoftReset:1 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 PmeEn:1 ; ///< + UINT32 DataSelect:4 ; ///< + UINT32 DataScale:2 ; ///< + UINT32 PmeStatus:1 ; ///< + UINT32 Reserved_21_16:6 ; ///< + UINT32 B2B3Support:1 ; ///< + UINT32 BusPwrEn:1 ; ///< + UINT32 PmeData:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x54_STRUCT; + +// **** DxF0x58 Register Definition **** +// Address +#define DxF0x58_ADDRESS 0x58 + +// Type +#define DxF0x58_TYPE TYPE_D4F0 +// Field Data +#define DxF0x58_CapID_OFFSET 0 +#define DxF0x58_CapID_WIDTH 8 +#define DxF0x58_CapID_MASK 0xff +#define DxF0x58_NextPtr_OFFSET 8 +#define DxF0x58_NextPtr_WIDTH 8 +#define DxF0x58_NextPtr_MASK 0xff00 +#define DxF0x58_Version_OFFSET 16 +#define DxF0x58_Version_WIDTH 4 +#define DxF0x58_Version_MASK 0xf0000 +#define DxF0x58_DeviceType_OFFSET 20 +#define DxF0x58_DeviceType_WIDTH 4 +#define DxF0x58_DeviceType_MASK 0xf00000 +#define DxF0x58_SlotImplemented_OFFSET 24 +#define DxF0x58_SlotImplemented_WIDTH 1 +#define DxF0x58_SlotImplemented_MASK 0x1000000 +#define DxF0x58_IntMessageNum_OFFSET 25 +#define DxF0x58_IntMessageNum_WIDTH 5 +#define DxF0x58_IntMessageNum_MASK 0x3e000000 +#define DxF0x58_Reserved_31_30_OFFSET 30 +#define DxF0x58_Reserved_31_30_WIDTH 2 +#define DxF0x58_Reserved_31_30_MASK 0xc0000000 + +/// DxF0x58 +typedef union { + struct { ///< + UINT32 CapID:8 ; ///< + UINT32 NextPtr:8 ; ///< + UINT32 Version:4 ; ///< + UINT32 DeviceType:4 ; ///< + UINT32 SlotImplemented:1 ; ///< + UINT32 IntMessageNum:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x58_STRUCT; + +// **** DxF0x5C Register Definition **** +// Address +#define DxF0x5C_ADDRESS 0x5c + +// Type +#define DxF0x5C_TYPE TYPE_D4F0 +// Field Data +#define DxF0x5C_MaxPayloadSupport_OFFSET 0 +#define DxF0x5C_MaxPayloadSupport_WIDTH 3 +#define DxF0x5C_MaxPayloadSupport_MASK 0x7 +#define DxF0x5C_PhantomFunc_OFFSET 3 +#define DxF0x5C_PhantomFunc_WIDTH 2 +#define DxF0x5C_PhantomFunc_MASK 0x18 +#define DxF0x5C_ExtendedTag_OFFSET 5 +#define DxF0x5C_ExtendedTag_WIDTH 1 +#define DxF0x5C_ExtendedTag_MASK 0x20 +#define DxF0x5C_L0SAcceptableLatency_OFFSET 6 +#define DxF0x5C_L0SAcceptableLatency_WIDTH 3 +#define DxF0x5C_L0SAcceptableLatency_MASK 0x1c0 +#define DxF0x5C_L1AcceptableLatency_OFFSET 9 +#define DxF0x5C_L1AcceptableLatency_WIDTH 3 +#define DxF0x5C_L1AcceptableLatency_MASK 0xe00 +#define DxF0x5C_Reserved_14_12_OFFSET 12 +#define DxF0x5C_Reserved_14_12_WIDTH 3 +#define DxF0x5C_Reserved_14_12_MASK 0x7000 +#define DxF0x5C_RoleBasedErrReporting_OFFSET 15 +#define DxF0x5C_RoleBasedErrReporting_WIDTH 1 +#define DxF0x5C_RoleBasedErrReporting_MASK 0x8000 +#define DxF0x5C_Reserved_17_16_OFFSET 16 +#define DxF0x5C_Reserved_17_16_WIDTH 2 +#define DxF0x5C_Reserved_17_16_MASK 0x30000 +#define DxF0x5C_CapturedSlotPowerLimit_OFFSET 18 +#define DxF0x5C_CapturedSlotPowerLimit_WIDTH 8 +#define DxF0x5C_CapturedSlotPowerLimit_MASK 0x3fc0000 +#define DxF0x5C_CapturedSlotPowerScale_OFFSET 26 +#define DxF0x5C_CapturedSlotPowerScale_WIDTH 2 +#define DxF0x5C_CapturedSlotPowerScale_MASK 0xc000000 +#define DxF0x5C_FlrCapable_OFFSET 28 +#define DxF0x5C_FlrCapable_WIDTH 1 +#define DxF0x5C_FlrCapable_MASK 0x10000000 +#define DxF0x5C_Reserved_31_29_OFFSET 29 +#define DxF0x5C_Reserved_31_29_WIDTH 3 +#define DxF0x5C_Reserved_31_29_MASK 0xe0000000 + +/// DxF0x5C +typedef union { + struct { ///< + UINT32 MaxPayloadSupport:3 ; ///< + UINT32 PhantomFunc:2 ; ///< + UINT32 ExtendedTag:1 ; ///< + UINT32 L0SAcceptableLatency:3 ; ///< + UINT32 L1AcceptableLatency:3 ; ///< + UINT32 Reserved_14_12:3 ; ///< + UINT32 RoleBasedErrReporting:1 ; ///< + UINT32 Reserved_17_16:2 ; ///< + UINT32 CapturedSlotPowerLimit:8 ; ///< + UINT32 CapturedSlotPowerScale:2 ; ///< + UINT32 FlrCapable:1 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x5C_STRUCT; + +// **** DxF0x60 Register Definition **** +// Address +#define DxF0x60_ADDRESS 0x60 + +// Type +#define DxF0x60_TYPE TYPE_D4F0 +// Field Data +#define DxF0x60_CorrErrEn_OFFSET 0 +#define DxF0x60_CorrErrEn_WIDTH 1 +#define DxF0x60_CorrErrEn_MASK 0x1 +#define DxF0x60_NonFatalErrEn_OFFSET 1 +#define DxF0x60_NonFatalErrEn_WIDTH 1 +#define DxF0x60_NonFatalErrEn_MASK 0x2 +#define DxF0x60_FatalErrEn_OFFSET 2 +#define DxF0x60_FatalErrEn_WIDTH 1 +#define DxF0x60_FatalErrEn_MASK 0x4 +#define DxF0x60_UsrReportEn_OFFSET 3 +#define DxF0x60_UsrReportEn_WIDTH 1 +#define DxF0x60_UsrReportEn_MASK 0x8 +#define DxF0x60_RelaxedOrdEn_OFFSET 4 +#define DxF0x60_RelaxedOrdEn_WIDTH 1 +#define DxF0x60_RelaxedOrdEn_MASK 0x10 +#define DxF0x60_MaxPayloadSize_OFFSET 5 +#define DxF0x60_MaxPayloadSize_WIDTH 3 +#define DxF0x60_MaxPayloadSize_MASK 0xe0 +#define DxF0x60_ExtendedTagEn_OFFSET 8 +#define DxF0x60_ExtendedTagEn_WIDTH 1 +#define DxF0x60_ExtendedTagEn_MASK 0x100 +#define DxF0x60_PhantomFuncEn_OFFSET 9 +#define DxF0x60_PhantomFuncEn_WIDTH 1 +#define DxF0x60_PhantomFuncEn_MASK 0x200 +#define DxF0x60_AuxPowerPmEn_OFFSET 10 +#define DxF0x60_AuxPowerPmEn_WIDTH 1 +#define DxF0x60_AuxPowerPmEn_MASK 0x400 +#define DxF0x60_NoSnoopEnable_OFFSET 11 +#define DxF0x60_NoSnoopEnable_WIDTH 1 +#define DxF0x60_NoSnoopEnable_MASK 0x800 +#define DxF0x60_MaxRequestSize_OFFSET 12 +#define DxF0x60_MaxRequestSize_WIDTH 3 +#define DxF0x60_MaxRequestSize_MASK 0x7000 +#define DxF0x60_BridgeCfgRetryEn_OFFSET 15 +#define DxF0x60_BridgeCfgRetryEn_WIDTH 1 +#define DxF0x60_BridgeCfgRetryEn_MASK 0x8000 +#define DxF0x60_CorrErr_OFFSET 16 +#define DxF0x60_CorrErr_WIDTH 1 +#define DxF0x60_CorrErr_MASK 0x10000 +#define DxF0x60_NonFatalErr_OFFSET 17 +#define DxF0x60_NonFatalErr_WIDTH 1 +#define DxF0x60_NonFatalErr_MASK 0x20000 +#define DxF0x60_FatalErr_OFFSET 18 +#define DxF0x60_FatalErr_WIDTH 1 +#define DxF0x60_FatalErr_MASK 0x40000 +#define DxF0x60_UsrDetected_OFFSET 19 +#define DxF0x60_UsrDetected_WIDTH 1 +#define DxF0x60_UsrDetected_MASK 0x80000 +#define DxF0x60_AuxPwr_OFFSET 20 +#define DxF0x60_AuxPwr_WIDTH 1 +#define DxF0x60_AuxPwr_MASK 0x100000 +#define DxF0x60_TransactionsPending_OFFSET 21 +#define DxF0x60_TransactionsPending_WIDTH 1 +#define DxF0x60_TransactionsPending_MASK 0x200000 +#define DxF0x60_Reserved_31_22_OFFSET 22 +#define DxF0x60_Reserved_31_22_WIDTH 10 +#define DxF0x60_Reserved_31_22_MASK 0xffc00000 + +/// DxF0x60 +typedef union { + struct { ///< + UINT32 CorrErrEn:1 ; ///< + UINT32 NonFatalErrEn:1 ; ///< + UINT32 FatalErrEn:1 ; ///< + UINT32 UsrReportEn:1 ; ///< + UINT32 RelaxedOrdEn:1 ; ///< + UINT32 MaxPayloadSize:3 ; ///< + UINT32 ExtendedTagEn:1 ; ///< + UINT32 PhantomFuncEn:1 ; ///< + UINT32 AuxPowerPmEn:1 ; ///< + UINT32 NoSnoopEnable:1 ; ///< + UINT32 MaxRequestSize:3 ; ///< + UINT32 BridgeCfgRetryEn:1 ; ///< + UINT32 CorrErr:1 ; ///< + UINT32 NonFatalErr:1 ; ///< + UINT32 FatalErr:1 ; ///< + UINT32 UsrDetected:1 ; ///< + UINT32 AuxPwr:1 ; ///< + UINT32 TransactionsPending:1 ; ///< + UINT32 Reserved_31_22:10; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x60_STRUCT; + + +// **** DxF0x68 Register Definition **** +// Address +#define DxF0x68_ADDRESS 0x68 + +// Type +#define DxF0x68_TYPE TYPE_D4F0 +// Field Data +#define DxF0x68_PmControl_OFFSET 0 +#define DxF0x68_PmControl_WIDTH 2 +#define DxF0x68_PmControl_MASK 0x3 +#define DxF0x68_Reserved_2_2_OFFSET 2 +#define DxF0x68_Reserved_2_2_WIDTH 1 +#define DxF0x68_Reserved_2_2_MASK 0x4 +#define DxF0x68_ReadCplBoundary_OFFSET 3 +#define DxF0x68_ReadCplBoundary_WIDTH 1 +#define DxF0x68_ReadCplBoundary_MASK 0x8 +#define DxF0x68_LinkDis_OFFSET 4 +#define DxF0x68_LinkDis_WIDTH 1 +#define DxF0x68_LinkDis_MASK 0x10 +#define DxF0x68_RetrainLink_OFFSET 5 +#define DxF0x68_RetrainLink_WIDTH 1 +#define DxF0x68_RetrainLink_MASK 0x20 +#define DxF0x68_CommonClockCfg_OFFSET 6 +#define DxF0x68_CommonClockCfg_WIDTH 1 +#define DxF0x68_CommonClockCfg_MASK 0x40 +#define DxF0x68_ExtendedSync_OFFSET 7 +#define DxF0x68_ExtendedSync_WIDTH 1 +#define DxF0x68_ExtendedSync_MASK 0x80 +#define DxF0x68_ClockPowerManagementEn_OFFSET 8 +#define DxF0x68_ClockPowerManagementEn_WIDTH 1 +#define DxF0x68_ClockPowerManagementEn_MASK 0x100 +#define DxF0x68_HWAutonomousWidthDisable_OFFSET 9 +#define DxF0x68_HWAutonomousWidthDisable_WIDTH 1 +#define DxF0x68_HWAutonomousWidthDisable_MASK 0x200 +#define DxF0x68_LinkBWManagementEn_OFFSET 10 +#define DxF0x68_LinkBWManagementEn_WIDTH 1 +#define DxF0x68_LinkBWManagementEn_MASK 0x400 +#define DxF0x68_LinkAutonomousBWIntEn_OFFSET 11 +#define DxF0x68_LinkAutonomousBWIntEn_WIDTH 1 +#define DxF0x68_LinkAutonomousBWIntEn_MASK 0x800 +#define DxF0x68_Reserved_15_12_OFFSET 12 +#define DxF0x68_Reserved_15_12_WIDTH 4 +#define DxF0x68_Reserved_15_12_MASK 0xf000 +#define DxF0x68_LinkSpeed_OFFSET 16 +#define DxF0x68_LinkSpeed_WIDTH 4 +#define DxF0x68_LinkSpeed_MASK 0xf0000 +#define DxF0x68_NegotiatedLinkWidth_OFFSET 20 +#define DxF0x68_NegotiatedLinkWidth_WIDTH 6 +#define DxF0x68_NegotiatedLinkWidth_MASK 0x3f00000 +#define DxF0x68_Reserved_26_26_OFFSET 26 +#define DxF0x68_Reserved_26_26_WIDTH 1 +#define DxF0x68_Reserved_26_26_MASK 0x4000000 +#define DxF0x68_LinkTraining_OFFSET 27 +#define DxF0x68_LinkTraining_WIDTH 1 +#define DxF0x68_LinkTraining_MASK 0x8000000 +#define DxF0x68_SlotClockCfg_OFFSET 28 +#define DxF0x68_SlotClockCfg_WIDTH 1 +#define DxF0x68_SlotClockCfg_MASK 0x10000000 +#define DxF0x68_DlActive_OFFSET 29 +#define DxF0x68_DlActive_WIDTH 1 +#define DxF0x68_DlActive_MASK 0x20000000 +#define DxF0x68_LinkBWManagementStatus_OFFSET 30 +#define DxF0x68_LinkBWManagementStatus_WIDTH 1 +#define DxF0x68_LinkBWManagementStatus_MASK 0x40000000 +#define DxF0x68_LinkAutonomousBWStatus_OFFSET 31 +#define DxF0x68_LinkAutonomousBWStatus_WIDTH 1 +#define DxF0x68_LinkAutonomousBWStatus_MASK 0x80000000 + +/// DxF0x68 +typedef union { + struct { ///< + UINT32 PmControl:2 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 ReadCplBoundary:1 ; ///< + UINT32 LinkDis:1 ; ///< + UINT32 RetrainLink:1 ; ///< + UINT32 CommonClockCfg:1 ; ///< + UINT32 ExtendedSync:1 ; ///< + UINT32 ClockPowerManagementEn:1 ; ///< + UINT32 HWAutonomousWidthDisable:1 ; ///< + UINT32 LinkBWManagementEn:1 ; ///< + UINT32 LinkAutonomousBWIntEn:1 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 LinkSpeed:4 ; ///< + UINT32 NegotiatedLinkWidth:6 ; ///< + UINT32 Reserved_26_26:1 ; ///< + UINT32 LinkTraining:1 ; ///< + UINT32 SlotClockCfg:1 ; ///< + UINT32 DlActive:1 ; ///< + UINT32 LinkBWManagementStatus:1 ; ///< + UINT32 LinkAutonomousBWStatus:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x68_STRUCT; + +// **** DxF0x6C Register Definition **** +// Address +#define DxF0x6C_ADDRESS 0x6c + +// Type +#define DxF0x6C_TYPE TYPE_D4F0 +// Field Data +#define DxF0x6C_AttnButtonPresent_OFFSET 0 +#define DxF0x6C_AttnButtonPresent_WIDTH 1 +#define DxF0x6C_AttnButtonPresent_MASK 0x1 +#define DxF0x6C_PwrControllerPresent_OFFSET 1 +#define DxF0x6C_PwrControllerPresent_WIDTH 1 +#define DxF0x6C_PwrControllerPresent_MASK 0x2 +#define DxF0x6C_MrlSensorPresent_OFFSET 2 +#define DxF0x6C_MrlSensorPresent_WIDTH 1 +#define DxF0x6C_MrlSensorPresent_MASK 0x4 +#define DxF0x6C_AttnIndicatorPresent_OFFSET 3 +#define DxF0x6C_AttnIndicatorPresent_WIDTH 1 +#define DxF0x6C_AttnIndicatorPresent_MASK 0x8 +#define DxF0x6C_PwrIndicatorPresent_OFFSET 4 +#define DxF0x6C_PwrIndicatorPresent_WIDTH 1 +#define DxF0x6C_PwrIndicatorPresent_MASK 0x10 +#define DxF0x6C_HotplugSurprise_OFFSET 5 +#define DxF0x6C_HotplugSurprise_WIDTH 1 +#define DxF0x6C_HotplugSurprise_MASK 0x20 +#define DxF0x6C_HotplugCapable_OFFSET 6 +#define DxF0x6C_HotplugCapable_WIDTH 1 +#define DxF0x6C_HotplugCapable_MASK 0x40 +#define DxF0x6C_SlotPwrLimitValue_OFFSET 7 +#define DxF0x6C_SlotPwrLimitValue_WIDTH 8 +#define DxF0x6C_SlotPwrLimitValue_MASK 0x7f80 +#define DxF0x6C_SlotPwrLimitScale_OFFSET 15 +#define DxF0x6C_SlotPwrLimitScale_WIDTH 2 +#define DxF0x6C_SlotPwrLimitScale_MASK 0x18000 +#define DxF0x6C_ElecMechIlPresent_OFFSET 17 +#define DxF0x6C_ElecMechIlPresent_WIDTH 1 +#define DxF0x6C_ElecMechIlPresent_MASK 0x20000 +#define DxF0x6C_NoCmdCplSupport_OFFSET 18 +#define DxF0x6C_NoCmdCplSupport_WIDTH 1 +#define DxF0x6C_NoCmdCplSupport_MASK 0x40000 +#define DxF0x6C_PhysicalSlotNumber_OFFSET 19 +#define DxF0x6C_PhysicalSlotNumber_WIDTH 13 +#define DxF0x6C_PhysicalSlotNumber_MASK 0xfff80000 + +/// DxF0x6C +typedef union { + struct { ///< + UINT32 AttnButtonPresent:1 ; ///< + UINT32 PwrControllerPresent:1 ; ///< + UINT32 MrlSensorPresent:1 ; ///< + UINT32 AttnIndicatorPresent:1 ; ///< + UINT32 PwrIndicatorPresent:1 ; ///< + UINT32 HotplugSurprise:1 ; ///< + UINT32 HotplugCapable:1 ; ///< + UINT32 SlotPwrLimitValue:8 ; ///< + UINT32 SlotPwrLimitScale:2 ; ///< + UINT32 ElecMechIlPresent:1 ; ///< + UINT32 NoCmdCplSupport:1 ; ///< + UINT32 PhysicalSlotNumber:13; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x6C_STRUCT; + +// **** DxF0x70 Register Definition **** +// Address +#define DxF0x70_ADDRESS 0x70 + +// Type +#define DxF0x70_TYPE TYPE_D4F0 +// Field Data +#define DxF0x70_AttnButtonPressedEn_OFFSET 0 +#define DxF0x70_AttnButtonPressedEn_WIDTH 1 +#define DxF0x70_AttnButtonPressedEn_MASK 0x1 +#define DxF0x70_PwrFaultDetectedEn_OFFSET 1 +#define DxF0x70_PwrFaultDetectedEn_WIDTH 1 +#define DxF0x70_PwrFaultDetectedEn_MASK 0x2 +#define DxF0x70_MrlSensorChangedEn_OFFSET 2 +#define DxF0x70_MrlSensorChangedEn_WIDTH 1 +#define DxF0x70_MrlSensorChangedEn_MASK 0x4 +#define DxF0x70_PresenceDetectChangedEn_OFFSET 3 +#define DxF0x70_PresenceDetectChangedEn_WIDTH 1 +#define DxF0x70_PresenceDetectChangedEn_MASK 0x8 +#define DxF0x70_CmdCplIntrEn_OFFSET 4 +#define DxF0x70_CmdCplIntrEn_WIDTH 1 +#define DxF0x70_CmdCplIntrEn_MASK 0x10 +#define DxF0x70_HotplugIntrEn_OFFSET 5 +#define DxF0x70_HotplugIntrEn_WIDTH 1 +#define DxF0x70_HotplugIntrEn_MASK 0x20 +#define DxF0x70_AttnIndicatorControl_OFFSET 6 +#define DxF0x70_AttnIndicatorControl_WIDTH 2 +#define DxF0x70_AttnIndicatorControl_MASK 0xc0 +#define DxF0x70_PwrIndicatorCntl_OFFSET 8 +#define DxF0x70_PwrIndicatorCntl_WIDTH 2 +#define DxF0x70_PwrIndicatorCntl_MASK 0x300 +#define DxF0x70_PwrControllerCntl_OFFSET 10 +#define DxF0x70_PwrControllerCntl_WIDTH 1 +#define DxF0x70_PwrControllerCntl_MASK 0x400 +#define DxF0x70_ElecMechIlCntl_OFFSET 11 +#define DxF0x70_ElecMechIlCntl_WIDTH 1 +#define DxF0x70_ElecMechIlCntl_MASK 0x800 +#define DxF0x70_DlStateChangedEn_OFFSET 12 +#define DxF0x70_DlStateChangedEn_WIDTH 1 +#define DxF0x70_DlStateChangedEn_MASK 0x1000 +#define DxF0x70_Reserved_15_13_OFFSET 13 +#define DxF0x70_Reserved_15_13_WIDTH 3 +#define DxF0x70_Reserved_15_13_MASK 0xe000 +#define DxF0x70_AttnButtonPressed_OFFSET 16 +#define DxF0x70_AttnButtonPressed_WIDTH 1 +#define DxF0x70_AttnButtonPressed_MASK 0x10000 +#define DxF0x70_PwrFaultDetected_OFFSET 17 +#define DxF0x70_PwrFaultDetected_WIDTH 1 +#define DxF0x70_PwrFaultDetected_MASK 0x20000 +#define DxF0x70_MrlSensorChanged_OFFSET 18 +#define DxF0x70_MrlSensorChanged_WIDTH 1 +#define DxF0x70_MrlSensorChanged_MASK 0x40000 +#define DxF0x70_PresenceDetectChanged_OFFSET 19 +#define DxF0x70_PresenceDetectChanged_WIDTH 1 +#define DxF0x70_PresenceDetectChanged_MASK 0x80000 +#define DxF0x70_CmdCpl_OFFSET 20 +#define DxF0x70_CmdCpl_WIDTH 1 +#define DxF0x70_CmdCpl_MASK 0x100000 +#define DxF0x70_MrlSensorState_OFFSET 21 +#define DxF0x70_MrlSensorState_WIDTH 1 +#define DxF0x70_MrlSensorState_MASK 0x200000 +#define DxF0x70_PresenceDetectState_OFFSET 22 +#define DxF0x70_PresenceDetectState_WIDTH 1 +#define DxF0x70_PresenceDetectState_MASK 0x400000 +#define DxF0x70_ElecMechIlSts_OFFSET 23 +#define DxF0x70_ElecMechIlSts_WIDTH 1 +#define DxF0x70_ElecMechIlSts_MASK 0x800000 +#define DxF0x70_DlStateChanged_OFFSET 24 +#define DxF0x70_DlStateChanged_WIDTH 1 +#define DxF0x70_DlStateChanged_MASK 0x1000000 +#define DxF0x70_Reserved_31_25_OFFSET 25 +#define DxF0x70_Reserved_31_25_WIDTH 7 +#define DxF0x70_Reserved_31_25_MASK 0xfe000000 + +/// DxF0x70 +typedef union { + struct { ///< + UINT32 AttnButtonPressedEn:1 ; ///< + UINT32 PwrFaultDetectedEn:1 ; ///< + UINT32 MrlSensorChangedEn:1 ; ///< + UINT32 PresenceDetectChangedEn:1 ; ///< + UINT32 CmdCplIntrEn:1 ; ///< + UINT32 HotplugIntrEn:1 ; ///< + UINT32 AttnIndicatorControl:2 ; ///< + UINT32 PwrIndicatorCntl:2 ; ///< + UINT32 PwrControllerCntl:1 ; ///< + UINT32 ElecMechIlCntl:1 ; ///< + UINT32 DlStateChangedEn:1 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 AttnButtonPressed:1 ; ///< + UINT32 PwrFaultDetected:1 ; ///< + UINT32 MrlSensorChanged:1 ; ///< + UINT32 PresenceDetectChanged:1 ; ///< + UINT32 CmdCpl:1 ; ///< + UINT32 MrlSensorState:1 ; ///< + UINT32 PresenceDetectState:1 ; ///< + UINT32 ElecMechIlSts:1 ; ///< + UINT32 DlStateChanged:1 ; ///< + UINT32 Reserved_31_25:7 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x70_STRUCT; + +// **** DxF0x74 Register Definition **** +// Address +#define DxF0x74_ADDRESS 0x74 + +// Type +#define DxF0x74_TYPE TYPE_D4F0 +// Field Data +#define DxF0x74_SerrOnCorrErrEn_OFFSET 0 +#define DxF0x74_SerrOnCorrErrEn_WIDTH 1 +#define DxF0x74_SerrOnCorrErrEn_MASK 0x1 +#define DxF0x74_SerrOnNonFatalErrEn_OFFSET 1 +#define DxF0x74_SerrOnNonFatalErrEn_WIDTH 1 +#define DxF0x74_SerrOnNonFatalErrEn_MASK 0x2 +#define DxF0x74_SerrOnFatalErrEn_OFFSET 2 +#define DxF0x74_SerrOnFatalErrEn_WIDTH 1 +#define DxF0x74_SerrOnFatalErrEn_MASK 0x4 +#define DxF0x74_PmIntEn_OFFSET 3 +#define DxF0x74_PmIntEn_WIDTH 1 +#define DxF0x74_PmIntEn_MASK 0x8 +#define DxF0x74_CrsSoftVisibilityEn_OFFSET 4 +#define DxF0x74_CrsSoftVisibilityEn_WIDTH 1 +#define DxF0x74_CrsSoftVisibilityEn_MASK 0x10 +#define DxF0x74_Reserved_15_5_OFFSET 5 +#define DxF0x74_Reserved_15_5_WIDTH 11 +#define DxF0x74_Reserved_15_5_MASK 0xffe0 +#define DxF0x74_CrsSoftVisibility_OFFSET 16 +#define DxF0x74_CrsSoftVisibility_WIDTH 1 +#define DxF0x74_CrsSoftVisibility_MASK 0x10000 +#define DxF0x74_Reserved_31_17_OFFSET 17 +#define DxF0x74_Reserved_31_17_WIDTH 15 +#define DxF0x74_Reserved_31_17_MASK 0xfffe0000 + +/// DxF0x74 +typedef union { + struct { ///< + UINT32 SerrOnCorrErrEn:1 ; ///< + UINT32 SerrOnNonFatalErrEn:1 ; ///< + UINT32 SerrOnFatalErrEn:1 ; ///< + UINT32 PmIntEn:1 ; ///< + UINT32 CrsSoftVisibilityEn:1 ; ///< + UINT32 Reserved_15_5:11; ///< + UINT32 CrsSoftVisibility:1 ; ///< + UINT32 Reserved_31_17:15; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x74_STRUCT; + +// **** DxF0x78 Register Definition **** +// Address +#define DxF0x78_ADDRESS 0x78 + +// Type +#define DxF0x78_TYPE TYPE_D4F0 +// Field Data +#define DxF0x78_PmeRequestorId_OFFSET 0 +#define DxF0x78_PmeRequestorId_WIDTH 16 +#define DxF0x78_PmeRequestorId_MASK 0xffff +#define DxF0x78_PmeStatus_OFFSET 16 +#define DxF0x78_PmeStatus_WIDTH 1 +#define DxF0x78_PmeStatus_MASK 0x10000 +#define DxF0x78_PmePending_OFFSET 17 +#define DxF0x78_PmePending_WIDTH 1 +#define DxF0x78_PmePending_MASK 0x20000 +#define DxF0x78_Reserved_31_18_OFFSET 18 +#define DxF0x78_Reserved_31_18_WIDTH 14 +#define DxF0x78_Reserved_31_18_MASK 0xfffc0000 + +/// DxF0x78 +typedef union { + struct { ///< + UINT32 PmeRequestorId:16; ///< + UINT32 PmeStatus:1 ; ///< + UINT32 PmePending:1 ; ///< + UINT32 Reserved_31_18:14; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x78_STRUCT; + +// **** DxF0x7C Register Definition **** +// Address +#define DxF0x7C_ADDRESS 0x7c + +// Type +#define DxF0x7C_TYPE TYPE_D4F0 +// Field Data +#define DxF0x7C_CplTimeoutRangeSup_OFFSET 0 +#define DxF0x7C_CplTimeoutRangeSup_WIDTH 4 +#define DxF0x7C_CplTimeoutRangeSup_MASK 0xf +#define DxF0x7C_CplTimeoutDisSup_OFFSET 4 +#define DxF0x7C_CplTimeoutDisSup_WIDTH 1 +#define DxF0x7C_CplTimeoutDisSup_MASK 0x10 +#define DxF0x7C_AriForwardingSupported_OFFSET 5 +#define DxF0x7C_AriForwardingSupported_WIDTH 1 +#define DxF0x7C_AriForwardingSupported_MASK 0x20 +#define DxF0x7C_Reserved_31_6_OFFSET 6 +#define DxF0x7C_Reserved_31_6_WIDTH 26 +#define DxF0x7C_Reserved_31_6_MASK 0xffffffc0 + +/// DxF0x7C +typedef union { + struct { ///< + UINT32 CplTimeoutRangeSup:4 ; ///< + UINT32 CplTimeoutDisSup:1 ; ///< + UINT32 AriForwardingSupported:1 ; ///< + UINT32 Reserved_31_6:26; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x7C_STRUCT; + +// **** DxF0x80 Register Definition **** +// Address +#define DxF0x80_ADDRESS 0x80 + +// Type +#define DxF0x80_TYPE TYPE_D4F0 +// Field Data +#define DxF0x80_CplTimeoutValue_OFFSET 0 +#define DxF0x80_CplTimeoutValue_WIDTH 4 +#define DxF0x80_CplTimeoutValue_MASK 0xf +#define DxF0x80_CplTimeoutDis_OFFSET 4 +#define DxF0x80_CplTimeoutDis_WIDTH 1 +#define DxF0x80_CplTimeoutDis_MASK 0x10 +#define DxF0x80_AriForwardingEn_OFFSET 5 +#define DxF0x80_AriForwardingEn_WIDTH 1 +#define DxF0x80_AriForwardingEn_MASK 0x20 +#define DxF0x80_Reserved_31_6_OFFSET 6 +#define DxF0x80_Reserved_31_6_WIDTH 26 +#define DxF0x80_Reserved_31_6_MASK 0xffffffc0 + +/// DxF0x80 +typedef union { + struct { ///< + UINT32 CplTimeoutValue:4 ; ///< + UINT32 CplTimeoutDis:1 ; ///< + UINT32 AriForwardingEn:1 ; ///< + UINT32 Reserved_31_6:26; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x80_STRUCT; + +// **** DxF0x84 Register Definition **** +// Address +#define DxF0x84_ADDRESS 0x84 + +// Type +#define DxF0x84_TYPE TYPE_D4F0 +// Field Data +#define DxF0x84_Reserved_31_0_OFFSET 0 +#define DxF0x84_Reserved_31_0_WIDTH 32 +#define DxF0x84_Reserved_31_0_MASK 0xffffffff + +/// DxF0x84 +typedef union { + struct { ///< + UINT32 Reserved_31_0:32; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x84_STRUCT; + +// **** DxF0x88 Register Definition **** +// Address +#define DxF0x88_ADDRESS 0x88 + +// Type +#define DxF0x88_TYPE TYPE_D4F0 +// Field Data +#define DxF0x88_TargetLinkSpeed_OFFSET 0 +#define DxF0x88_TargetLinkSpeed_WIDTH 4 +#define DxF0x88_TargetLinkSpeed_MASK 0xf +#define DxF0x88_EnterCompliance_OFFSET 4 +#define DxF0x88_EnterCompliance_WIDTH 1 +#define DxF0x88_EnterCompliance_MASK 0x10 +#define DxF0x88_HwAutonomousSpeedDisable_OFFSET 5 +#define DxF0x88_HwAutonomousSpeedDisable_WIDTH 1 +#define DxF0x88_HwAutonomousSpeedDisable_MASK 0x20 +#define DxF0x88_SelectableDeemphasis_OFFSET 6 +#define DxF0x88_SelectableDeemphasis_WIDTH 1 +#define DxF0x88_SelectableDeemphasis_MASK 0x40 +#define DxF0x88_XmitMargin_OFFSET 7 +#define DxF0x88_XmitMargin_WIDTH 3 +#define DxF0x88_XmitMargin_MASK 0x380 +#define DxF0x88_EnterModCompliance_OFFSET 10 +#define DxF0x88_EnterModCompliance_WIDTH 1 +#define DxF0x88_EnterModCompliance_MASK 0x400 +#define DxF0x88_ComplianceSOS_OFFSET 11 +#define DxF0x88_ComplianceSOS_WIDTH 1 +#define DxF0x88_ComplianceSOS_MASK 0x800 +#define DxF0x88_ComplianceDeemphasis_OFFSET 12 +#define DxF0x88_ComplianceDeemphasis_WIDTH 1 +#define DxF0x88_ComplianceDeemphasis_MASK 0x1000 +#define DxF0x88_Reserved_15_13_OFFSET 13 +#define DxF0x88_Reserved_15_13_WIDTH 3 +#define DxF0x88_Reserved_15_13_MASK 0xe000 +#define DxF0x88_CurDeemphasisLevel_OFFSET 16 +#define DxF0x88_CurDeemphasisLevel_WIDTH 1 +#define DxF0x88_CurDeemphasisLevel_MASK 0x10000 +#define DxF0x88_Reserved_31_17_OFFSET 17 +#define DxF0x88_Reserved_31_17_WIDTH 15 +#define DxF0x88_Reserved_31_17_MASK 0xfffe0000 + +/// DxF0x88 +typedef union { + struct { ///< + UINT32 TargetLinkSpeed:4 ; ///< + UINT32 EnterCompliance:1 ; ///< + UINT32 HwAutonomousSpeedDisable:1 ; ///< + UINT32 SelectableDeemphasis:1 ; ///< + UINT32 XmitMargin:3 ; ///< + UINT32 EnterModCompliance:1 ; ///< + UINT32 ComplianceSOS:1 ; ///< + UINT32 ComplianceDeemphasis:1 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 CurDeemphasisLevel:1 ; ///< + UINT32 Reserved_31_17:15; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x88_STRUCT; + +// **** DxF0x8C Register Definition **** +// Address +#define DxF0x8C_ADDRESS 0x8c + +// Type +#define DxF0x8C_TYPE TYPE_D4F0 +// Field Data +#define DxF0x8C_Reserved_31_0_OFFSET 0 +#define DxF0x8C_Reserved_31_0_WIDTH 32 +#define DxF0x8C_Reserved_31_0_MASK 0xffffffff + +/// DxF0x8C +typedef union { + struct { ///< + UINT32 Reserved_31_0:32; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x8C_STRUCT; + +// **** DxF0x90 Register Definition **** +// Address +#define DxF0x90_ADDRESS 0x90 + +// Type +#define DxF0x90_TYPE TYPE_D4F0 +// Field Data +#define DxF0x90_Reserved_31_0_OFFSET 0 +#define DxF0x90_Reserved_31_0_WIDTH 32 +#define DxF0x90_Reserved_31_0_MASK 0xffffffff + +/// DxF0x90 +typedef union { + struct { ///< + UINT32 Reserved_31_0:32; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x90_STRUCT; + +// **** DxF0x128 Register Definition **** +// Address +#define DxF0x128_ADDRESS 0x128 + +// Type +#define DxF0x128_TYPE TYPE_D4F0 +// Field Data +#define DxF0x128_Reserved_15_0_OFFSET 0 +#define DxF0x128_Reserved_15_0_WIDTH 16 +#define DxF0x128_Reserved_15_0_MASK 0xffff +#define DxF0x128_PortArbTableStatus_OFFSET 16 +#define DxF0x128_PortArbTableStatus_WIDTH 1 +#define DxF0x128_PortArbTableStatus_MASK 0x10000 +#define DxF0x128_VcNegotiationPending_OFFSET 17 +#define DxF0x128_VcNegotiationPending_WIDTH 1 +#define DxF0x128_VcNegotiationPending_MASK 0x20000 +#define DxF0x128_Reserved_31_18_OFFSET 18 +#define DxF0x128_Reserved_31_18_WIDTH 14 +#define DxF0x128_Reserved_31_18_MASK 0xfffc0000 + +/// DxF0x128 +typedef union { + struct { ///< + UINT32 Reserved_15_0:16; ///< + UINT32 PortArbTableStatus:1 ; ///< + UINT32 VcNegotiationPending:1 ; ///< + UINT32 Reserved_31_18:14; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x128_STRUCT; + + + + + + + + + + + + + + + + +// **** D0F0x64_x00 Register Definition **** +// Address +#define D0F0x64_x00_ADDRESS 0x0 + +// Type +#define D0F0x64_x00_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x00_Reserved_5_0_OFFSET 0 +#define D0F0x64_x00_Reserved_5_0_WIDTH 6 +#define D0F0x64_x00_Reserved_5_0_MASK 0x3f +#define D0F0x64_x00_NbFchCfgEn_OFFSET 6 +#define D0F0x64_x00_NbFchCfgEn_WIDTH 1 +#define D0F0x64_x00_NbFchCfgEn_MASK 0x40 +#define D0F0x64_x00_HwInitWrLock_OFFSET 7 +#define D0F0x64_x00_HwInitWrLock_WIDTH 1 +#define D0F0x64_x00_HwInitWrLock_MASK 0x80 +#define D0F0x64_x00_Reserved_31_8_OFFSET 8 +#define D0F0x64_x00_Reserved_31_8_WIDTH 24 +#define D0F0x64_x00_Reserved_31_8_MASK 0xffffff00 + +/// D0F0x64_x00 +typedef union { + struct { ///< + UINT32 Reserved_5_0:6 ; ///< + UINT32 NbFchCfgEn:1 ; ///< + UINT32 HwInitWrLock:1 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x00_STRUCT; + +// **** D0F0x64_x0B Register Definition **** +// Address +#define D0F0x64_x0B_ADDRESS 0xb + +// Type +#define D0F0x64_x0B_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x0B_Reserved_19_0_OFFSET 0 +#define D0F0x64_x0B_Reserved_19_0_WIDTH 20 +#define D0F0x64_x0B_Reserved_19_0_MASK 0xfffff +#define D0F0x64_x0B_SetPowEn_OFFSET 20 +#define D0F0x64_x0B_SetPowEn_WIDTH 1 +#define D0F0x64_x0B_SetPowEn_MASK 0x100000 +#define D0F0x64_x0B_IocFchSetPowEn_OFFSET 21 +#define D0F0x64_x0B_IocFchSetPowEn_WIDTH 1 +#define D0F0x64_x0B_IocFchSetPowEn_MASK 0x200000 +#define D0F0x64_x0B_Reserved_22_22_OFFSET 22 +#define D0F0x64_x0B_Reserved_22_22_WIDTH 1 +#define D0F0x64_x0B_Reserved_22_22_MASK 0x400000 +#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_OFFSET 23 +#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_WIDTH 1 +#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_MASK 0x800000 +#define D0F0x64_x0B_Reserved_31_24_OFFSET 24 +#define D0F0x64_x0B_Reserved_31_24_WIDTH 8 +#define D0F0x64_x0B_Reserved_31_24_MASK 0xff000000 + +/// D0F0x64_x0B +typedef union { + struct { ///< + UINT32 Reserved_19_0:20; ///< + UINT32 SetPowEn:1 ; ///< + UINT32 IocFchSetPowEn:1 ; ///< + UINT32 Reserved_22_22:1 ; ///< + UINT32 IocFchSetPmeTurnOffEn:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x0B_STRUCT; + +// **** D0F0x64_x0C Register Definition **** +// Address +#define D0F0x64_x0C_ADDRESS 0xc + +// Type +#define D0F0x64_x0C_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x0C_Reserved_1_0_OFFSET 0 +#define D0F0x64_x0C_Reserved_1_0_WIDTH 2 +#define D0F0x64_x0C_Reserved_1_0_MASK 0x3 +#define D0F0x64_x0C_Dev2BridgeDis_OFFSET 2 +#define D0F0x64_x0C_Dev2BridgeDis_WIDTH 1 +#define D0F0x64_x0C_Dev2BridgeDis_MASK 0x4 +#define D0F0x64_x0C_Dev3BridgeDis_OFFSET 3 +#define D0F0x64_x0C_Dev3BridgeDis_WIDTH 1 +#define D0F0x64_x0C_Dev3BridgeDis_MASK 0x8 +#define D0F0x64_x0C_Dev4BridgeDis_OFFSET 4 +#define D0F0x64_x0C_Dev4BridgeDis_WIDTH 1 +#define D0F0x64_x0C_Dev4BridgeDis_MASK 0x10 +#define D0F0x64_x0C_Dev5BridgeDis_OFFSET 5 +#define D0F0x64_x0C_Dev5BridgeDis_WIDTH 1 +#define D0F0x64_x0C_Dev5BridgeDis_MASK 0x20 +#define D0F0x64_x0C_Dev6BridgeDis_OFFSET 6 +#define D0F0x64_x0C_Dev6BridgeDis_WIDTH 1 +#define D0F0x64_x0C_Dev6BridgeDis_MASK 0x40 +#define D0F0x64_x0C_Dev7BridgeDis_OFFSET 7 +#define D0F0x64_x0C_Dev7BridgeDis_WIDTH 1 +#define D0F0x64_x0C_Dev7BridgeDis_MASK 0x80 +#define D0F0x64_x0C_Reserved_31_8_OFFSET 8 +#define D0F0x64_x0C_Reserved_31_8_WIDTH 24 +#define D0F0x64_x0C_Reserved_31_8_MASK 0xffffff00 + +/// D0F0x64_x0C +typedef union { + struct { ///< + UINT32 Reserved_1_0:2 ; ///< + UINT32 Dev2BridgeDis:1 ; ///< + UINT32 Dev3BridgeDis:1 ; ///< + UINT32 Dev4BridgeDis:1 ; ///< + UINT32 Dev5BridgeDis:1 ; ///< + UINT32 Dev6BridgeDis:1 ; ///< + UINT32 Dev7BridgeDis:1 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x0C_STRUCT; + +// **** D0F0x64_x19 Register Definition **** +// Address +#define D0F0x64_x19_ADDRESS 0x19 + +// Type +#define D0F0x64_x19_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x19_TomEn_OFFSET 0 +#define D0F0x64_x19_TomEn_WIDTH 1 +#define D0F0x64_x19_TomEn_MASK 0x1 +#define D0F0x64_x19_Reserved_22_1_OFFSET 1 +#define D0F0x64_x19_Reserved_22_1_WIDTH 22 +#define D0F0x64_x19_Reserved_22_1_MASK 0x7ffffe +#define D0F0x64_x19_Tom2_31_23__OFFSET 23 +#define D0F0x64_x19_Tom2_31_23__WIDTH 9 +#define D0F0x64_x19_Tom2_31_23__MASK 0xff800000 + +/// D0F0x64_x19 +typedef union { + struct { ///< + UINT32 TomEn:1 ; ///< + UINT32 Reserved_22_1:22; ///< + UINT32 Tom2_31_23_:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x19_STRUCT; + +// **** D0F0x64_x1A Register Definition **** +// Address +#define D0F0x64_x1A_ADDRESS 0x1a + +// Type +#define D0F0x64_x1A_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x1A_Tom2_39_32__OFFSET 0 +#define D0F0x64_x1A_Tom2_39_32__WIDTH 8 +#define D0F0x64_x1A_Tom2_39_32__MASK 0xff +#define D0F0x64_x1A_Reserved_31_8_OFFSET 8 +#define D0F0x64_x1A_Reserved_31_8_WIDTH 24 +#define D0F0x64_x1A_Reserved_31_8_MASK 0xffffff00 + +/// D0F0x64_x1A +typedef union { + struct { ///< + UINT32 Tom2_39_32_:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x1A_STRUCT; + +// **** D0F0x64_x1D Register Definition **** +// Address +#define D0F0x64_x1D_ADDRESS 0x1d + +// Type +#define D0F0x64_x1D_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x1D_IntGfxAsPcieEn_OFFSET 0 +#define D0F0x64_x1D_IntGfxAsPcieEn_WIDTH 1 +#define D0F0x64_x1D_IntGfxAsPcieEn_MASK 0x1 +#define D0F0x64_x1D_VgaEn_OFFSET 1 +#define D0F0x64_x1D_VgaEn_WIDTH 1 +#define D0F0x64_x1D_VgaEn_MASK 0x2 +#define D0F0x64_x1D_Reserved_2_2_OFFSET 2 +#define D0F0x64_x1D_Reserved_2_2_WIDTH 1 +#define D0F0x64_x1D_Reserved_2_2_MASK 0x4 +#define D0F0x64_x1D_Vga16En_OFFSET 3 +#define D0F0x64_x1D_Vga16En_WIDTH 1 +#define D0F0x64_x1D_Vga16En_MASK 0x8 +#define D0F0x64_x1D_Reserved_31_4_OFFSET 4 +#define D0F0x64_x1D_Reserved_31_4_WIDTH 28 +#define D0F0x64_x1D_Reserved_31_4_MASK 0xfffffff0 + +/// D0F0x64_x1D +typedef union { + struct { ///< + UINT32 IntGfxAsPcieEn:1 ; ///< + UINT32 VgaEn:1 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 Vga16En:1 ; ///< + UINT32 Reserved_31_4:28; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x1D_STRUCT; + + + + + + + + +// **** D0F0x64_x53 Register Definition **** +// Address +#define D0F0x64_x53_ADDRESS 0x53 + +// Type +#define D0F0x64_x53_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x53_Reserved_19_0_OFFSET 0 +#define D0F0x64_x53_Reserved_19_0_WIDTH 20 +#define D0F0x64_x53_Reserved_19_0_MASK 0xfffff +#define D0F0x64_x53_SetPowEn_OFFSET 20 +#define D0F0x64_x53_SetPowEn_WIDTH 1 +#define D0F0x64_x53_SetPowEn_MASK 0x100000 +#define D0F0x64_x53_Reserved_31_21_OFFSET 21 +#define D0F0x64_x53_Reserved_31_21_WIDTH 11 +#define D0F0x64_x53_Reserved_31_21_MASK 0xffe00000 + +/// D0F0x64_x53 +typedef union { + struct { ///< + UINT32 Reserved_19_0:20; ///< + UINT32 SetPowEn:1 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x53_STRUCT; + +// **** D0F0x64_x55 Register Definition **** +// Address +#define D0F0x64_x55_ADDRESS 0x55 + +// Type +#define D0F0x64_x55_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x55_Reserved_19_0_OFFSET 0 +#define D0F0x64_x55_Reserved_19_0_WIDTH 20 +#define D0F0x64_x55_Reserved_19_0_MASK 0xfffff +#define D0F0x64_x55_SetPowEn_OFFSET 20 +#define D0F0x64_x55_SetPowEn_WIDTH 1 +#define D0F0x64_x55_SetPowEn_MASK 0x100000 +#define D0F0x64_x55_Reserved_31_21_OFFSET 21 +#define D0F0x64_x55_Reserved_31_21_WIDTH 11 +#define D0F0x64_x55_Reserved_31_21_MASK 0xffe00000 + +/// D0F0x64_x55 +typedef union { + struct { ///< + UINT32 Reserved_19_0:20; ///< + UINT32 SetPowEn:1 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x55_STRUCT; + +// **** D0F0x64_x57 Register Definition **** +// Address +#define D0F0x64_x57_ADDRESS 0x57 + +// Type +#define D0F0x64_x57_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x57_Reserved_19_0_OFFSET 0 +#define D0F0x64_x57_Reserved_19_0_WIDTH 20 +#define D0F0x64_x57_Reserved_19_0_MASK 0xfffff +#define D0F0x64_x57_SetPowEn_OFFSET 20 +#define D0F0x64_x57_SetPowEn_WIDTH 1 +#define D0F0x64_x57_SetPowEn_MASK 0x100000 +#define D0F0x64_x57_Reserved_31_21_OFFSET 21 +#define D0F0x64_x57_Reserved_31_21_WIDTH 11 +#define D0F0x64_x57_Reserved_31_21_MASK 0xffe00000 + +/// D0F0x64_x57 +typedef union { + struct { ///< + UINT32 Reserved_19_0:20; ///< + UINT32 SetPowEn:1 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x57_STRUCT; + +// **** D0F0x64_x59 Register Definition **** +// Address +#define D0F0x64_x59_ADDRESS 0x59 + +// Type +#define D0F0x64_x59_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x59_Reserved_19_0_OFFSET 0 +#define D0F0x64_x59_Reserved_19_0_WIDTH 20 +#define D0F0x64_x59_Reserved_19_0_MASK 0xfffff +#define D0F0x64_x59_SetPowEn_OFFSET 20 +#define D0F0x64_x59_SetPowEn_WIDTH 1 +#define D0F0x64_x59_SetPowEn_MASK 0x100000 +#define D0F0x64_x59_Reserved_31_21_OFFSET 21 +#define D0F0x64_x59_Reserved_31_21_WIDTH 11 +#define D0F0x64_x59_Reserved_31_21_MASK 0xffe00000 + +/// D0F0x64_x59 +typedef union { + struct { ///< + UINT32 Reserved_19_0:20; ///< + UINT32 SetPowEn:1 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x59_STRUCT; + +// **** D0F0x64_x5B Register Definition **** +// Address +#define D0F0x64_x5B_ADDRESS 0x5b + +// Type +#define D0F0x64_x5B_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x5B_Reserved_19_0_OFFSET 0 +#define D0F0x64_x5B_Reserved_19_0_WIDTH 20 +#define D0F0x64_x5B_Reserved_19_0_MASK 0xfffff +#define D0F0x64_x5B_SetPowEn_OFFSET 20 +#define D0F0x64_x5B_SetPowEn_WIDTH 1 +#define D0F0x64_x5B_SetPowEn_MASK 0x100000 +#define D0F0x64_x5B_Reserved_31_21_OFFSET 21 +#define D0F0x64_x5B_Reserved_31_21_WIDTH 11 +#define D0F0x64_x5B_Reserved_31_21_MASK 0xffe00000 + +/// D0F0x64_x5B +typedef union { + struct { ///< + UINT32 Reserved_19_0:20; ///< + UINT32 SetPowEn:1 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x5B_STRUCT; + +/// D0F0x64_x6A +typedef union { + struct { ///< + UINT32 VoltageForceEn:1 ; ///< + UINT32 VoltageChangeEn:1 ; ///< + UINT32 VoltageChangeReq:1 ; ///< + UINT32 VoltageLevel:2 ; ///< + UINT32 Reserved_31_5:27; ///< + } Field; ///< + UINT32 Value; ///< +} ex488_STRUCT; + +/// D0F0x64_x6B +typedef union { + struct { ///< + UINT32 VoltageChangeAck:1 ; ///< + UINT32 CurrentVoltageLevel:2 ; ///< + UINT32 Reserved_31_3:29; ///< + } Field; ///< + UINT32 Value; ///< +} ex489_STRUCT; + +// **** D0F0x98_x06 Register Definition **** +// Address +#define D0F0x98_x06_ADDRESS 0x6 + +// Type +#define D0F0x98_x06_TYPE TYPE_D0F0x98 +// Field Data +#define D0F0x98_x06_Reserved_25_0_OFFSET 0 +#define D0F0x98_x06_Reserved_25_0_WIDTH 26 +#define D0F0x98_x06_Reserved_25_0_MASK 0x3ffffff +#define D0F0x98_x06_UmiNpMemWrEn_OFFSET 26 +#define D0F0x98_x06_UmiNpMemWrEn_WIDTH 1 +#define D0F0x98_x06_UmiNpMemWrEn_MASK 0x4000000 +#define D0F0x98_x06_Reserved_31_27_OFFSET 27 +#define D0F0x98_x06_Reserved_31_27_WIDTH 5 +#define D0F0x98_x06_Reserved_31_27_MASK 0xf8000000 + +/// D0F0x98_x06 +typedef union { + struct { ///< + UINT32 Reserved_25_0:26; ///< + UINT32 UmiNpMemWrEn:1 ; ///< + UINT32 Reserved_31_27:5 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_x06_STRUCT; + + + + + +// **** D0F0x98_x1E Register Definition **** +// Address +#define D0F0x98_x1E_ADDRESS 0x1e + +// Type +#define D0F0x98_x1E_TYPE TYPE_D0F0x98 +// Field Data +#define D0F0x98_x1E_Reserved_0_0_OFFSET 0 +#define D0F0x98_x1E_Reserved_0_0_WIDTH 1 +#define D0F0x98_x1E_Reserved_0_0_MASK 0x1 +#define D0F0x98_x1E_HiPriEn_OFFSET 1 +#define D0F0x98_x1E_HiPriEn_WIDTH 1 +#define D0F0x98_x1E_HiPriEn_MASK 0x2 +#define D0F0x98_x1E_Reserved_31_2_OFFSET 2 +#define D0F0x98_x1E_Reserved_31_2_WIDTH 30 +#define D0F0x98_x1E_Reserved_31_2_MASK 0xfffffffc + +/// D0F0x98_x1E +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 HiPriEn:1 ; ///< + UINT32 Reserved_31_2:30; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_x1E_STRUCT; + + +/// D0F0x98_x2C +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 ex495_1:1; + UINT32 Reserved_15_2:14; ///< + UINT32 ex495_3:16; + } Field; ///< + UINT32 Value; ///< +} ex495_STRUCT; + + +// **** D0F0x98_x49 Register Definition **** +// Address +#define D0F0x98_x49_ADDRESS 0x49 + +// Type +#define D0F0x98_x49_TYPE TYPE_D0F0x98 +// Field Data +#define D0F0x98_x49_Reserved_3_0_OFFSET 0 +#define D0F0x98_x49_Reserved_3_0_WIDTH 4 +#define D0F0x98_x49_Reserved_3_0_MASK 0xf +#define D0F0x98_x49_Reserved_23_12_OFFSET 12 +#define D0F0x98_x49_Reserved_23_12_WIDTH 12 +#define D0F0x98_x49_Reserved_23_12_MASK 0xfff000 +#define D0F0x98_x49_SoftOverrideClk6_OFFSET 24 +#define D0F0x98_x49_SoftOverrideClk6_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk6_MASK 0x1000000 +#define D0F0x98_x49_SoftOverrideClk5_OFFSET 25 +#define D0F0x98_x49_SoftOverrideClk5_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk5_MASK 0x2000000 +#define D0F0x98_x49_SoftOverrideClk4_OFFSET 26 +#define D0F0x98_x49_SoftOverrideClk4_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk4_MASK 0x4000000 +#define D0F0x98_x49_SoftOverrideClk3_OFFSET 27 +#define D0F0x98_x49_SoftOverrideClk3_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk3_MASK 0x8000000 +#define D0F0x98_x49_SoftOverrideClk2_OFFSET 28 +#define D0F0x98_x49_SoftOverrideClk2_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk2_MASK 0x10000000 +#define D0F0x98_x49_SoftOverrideClk1_OFFSET 29 +#define D0F0x98_x49_SoftOverrideClk1_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk1_MASK 0x20000000 +#define D0F0x98_x49_SoftOverrideClk0_OFFSET 30 +#define D0F0x98_x49_SoftOverrideClk0_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk0_MASK 0x40000000 +#define D0F0x98_x49_Reserved_31_31_OFFSET 31 +#define D0F0x98_x49_Reserved_31_31_WIDTH 1 +#define D0F0x98_x49_Reserved_31_31_MASK 0x80000000 + +/// D0F0x98_x49 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 :8 ; ///< + UINT32 Reserved_23_12:12; ///< + UINT32 SoftOverrideClk6:1 ; ///< + UINT32 SoftOverrideClk5:1 ; ///< + UINT32 SoftOverrideClk4:1 ; ///< + UINT32 SoftOverrideClk3:1 ; ///< + UINT32 SoftOverrideClk2:1 ; ///< + UINT32 SoftOverrideClk1:1 ; ///< + UINT32 SoftOverrideClk0:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_x49_STRUCT; + +// **** D0F0x98_x4A Register Definition **** +// Address +#define D0F0x98_x4A_ADDRESS 0x4a + +// Type +#define D0F0x98_x4A_TYPE TYPE_D0F0x98 +// Field Data +#define D0F0x98_x4A_Reserved_3_0_OFFSET 0 +#define D0F0x98_x4A_Reserved_3_0_WIDTH 4 +#define D0F0x98_x4A_Reserved_3_0_MASK 0xf +#define D0F0x98_x4A_Reserved_23_12_OFFSET 12 +#define D0F0x98_x4A_Reserved_23_12_WIDTH 12 +#define D0F0x98_x4A_Reserved_23_12_MASK 0xfff000 +#define D0F0x98_x4A_SoftOverrideClk6_OFFSET 24 +#define D0F0x98_x4A_SoftOverrideClk6_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk6_MASK 0x1000000 +#define D0F0x98_x4A_SoftOverrideClk5_OFFSET 25 +#define D0F0x98_x4A_SoftOverrideClk5_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk5_MASK 0x2000000 +#define D0F0x98_x4A_SoftOverrideClk4_OFFSET 26 +#define D0F0x98_x4A_SoftOverrideClk4_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk4_MASK 0x4000000 +#define D0F0x98_x4A_SoftOverrideClk3_OFFSET 27 +#define D0F0x98_x4A_SoftOverrideClk3_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk3_MASK 0x8000000 +#define D0F0x98_x4A_SoftOverrideClk2_OFFSET 28 +#define D0F0x98_x4A_SoftOverrideClk2_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk2_MASK 0x10000000 +#define D0F0x98_x4A_SoftOverrideClk1_OFFSET 29 +#define D0F0x98_x4A_SoftOverrideClk1_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk1_MASK 0x20000000 +#define D0F0x98_x4A_SoftOverrideClk0_OFFSET 30 +#define D0F0x98_x4A_SoftOverrideClk0_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk0_MASK 0x40000000 +#define D0F0x98_x4A_Reserved_31_31_OFFSET 31 +#define D0F0x98_x4A_Reserved_31_31_WIDTH 1 +#define D0F0x98_x4A_Reserved_31_31_MASK 0x80000000 + +/// D0F0x98_x4A +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 :8 ; ///< + UINT32 Reserved_23_12:12; ///< + UINT32 SoftOverrideClk6:1 ; ///< + UINT32 SoftOverrideClk5:1 ; ///< + UINT32 SoftOverrideClk4:1 ; ///< + UINT32 SoftOverrideClk3:1 ; ///< + UINT32 SoftOverrideClk2:1 ; ///< + UINT32 SoftOverrideClk1:1 ; ///< + UINT32 SoftOverrideClk0:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_x4A_STRUCT; + + +// **** D0F0xE4_WRAP_0080 Register Definition **** +// Address +#define D0F0xE4_WRAP_0080_ADDRESS 0x80 + +// Type +#define D0F0xE4_WRAP_0080_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_OFFSET 0 +#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_WIDTH 4 +#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_MASK 0xf +#define D0F0xE4_WRAP_0080_Reserved_31_4_OFFSET 4 +#define D0F0xE4_WRAP_0080_Reserved_31_4_WIDTH 28 +#define D0F0xE4_WRAP_0080_Reserved_31_4_MASK 0xfffffff0 + +/// D0F0xE4_WRAP_0080 +typedef union { + struct { ///< + UINT32 StrapBifLinkConfig:4 ; ///< + UINT32 Reserved_31_4:28; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_0080_STRUCT; + +// **** D0F0xE4_WRAP_0800 Register Definition **** +// Address +#define D0F0xE4_WRAP_0800_ADDRESS 0x800 + +// Type +#define D0F0xE4_WRAP_0800_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_0800_HoldTraining_OFFSET 0 +#define D0F0xE4_WRAP_0800_HoldTraining_WIDTH 1 +#define D0F0xE4_WRAP_0800_HoldTraining_MASK 0x1 +#define D0F0xE4_WRAP_0800_Reserved_31_1_OFFSET 1 +#define D0F0xE4_WRAP_0800_Reserved_31_1_WIDTH 31 +#define D0F0xE4_WRAP_0800_Reserved_31_1_MASK 0xfffffffe + +/// D0F0xE4_WRAP_0800 +typedef union { + struct { ///< + UINT32 HoldTraining:1 ; ///< + UINT32 Reserved_31_1:31; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_0800_STRUCT; + +// **** D0F0xE4_WRAP_0803 Register Definition **** +// Address +#define D0F0xE4_WRAP_0803_ADDRESS 0x803 + +// Type +#define D0F0xE4_WRAP_0803_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_0803_Reserved_4_0_OFFSET 0 +#define D0F0xE4_WRAP_0803_Reserved_4_0_WIDTH 5 +#define D0F0xE4_WRAP_0803_Reserved_4_0_MASK 0x1f +#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET 5 +#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH 1 +#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_MASK 0x20 +#define D0F0xE4_WRAP_0803_Reserved_31_6_OFFSET 6 +#define D0F0xE4_WRAP_0803_Reserved_31_6_WIDTH 26 +#define D0F0xE4_WRAP_0803_Reserved_31_6_MASK 0xffffffc0 + +/// D0F0xE4_WRAP_0803 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 StrapBifDeemphasisSel:1 ; ///< + UINT32 Reserved_31_6:26; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_0803_STRUCT; + +// **** D0F0xE4_WRAP_0903 Register Definition **** +// Address +#define D0F0xE4_WRAP_0903_ADDRESS 0x903 + +// Type +#define D0F0xE4_WRAP_0903_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_0903_Reserved_4_0_OFFSET 0 +#define D0F0xE4_WRAP_0903_Reserved_4_0_WIDTH 5 +#define D0F0xE4_WRAP_0903_Reserved_4_0_MASK 0x1f +#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_OFFSET 5 +#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_WIDTH 1 +#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_MASK 0x20 +#define D0F0xE4_WRAP_0903_Reserved_31_6_OFFSET 6 +#define D0F0xE4_WRAP_0903_Reserved_31_6_WIDTH 26 +#define D0F0xE4_WRAP_0903_Reserved_31_6_MASK 0xffffffc0 + +/// D0F0xE4_WRAP_0903 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 StrapBifDeemphasisSel:1 ; ///< + UINT32 Reserved_31_6:26; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_0903_STRUCT; + + +/// D0F0xE4_WRAP_8011 +typedef union { + struct { ///< + UINT32 TxclkDynGateLatency:6 ; ///< + UINT32 TxclkPermGateEven:1 ; ///< + UINT32 TxclkDynGateEnable:1 ; ///< + UINT32 TxclkPermStop:1 ; ///< + UINT32 TxclkRegsGateEnable:1 ; ///< + UINT32 TxclkRegsGateLatency:6 ; ///< + UINT32 RcvrDetClkEnable:1 ; ///< + UINT32 TxclkPermGateLatency:6 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 TxclkLcntGateEnable:1 ; ///< + UINT32 Reserved_30_25:6 ; ///< + UINT32 StrapBifValid:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} ex501_STRUCT; + +// **** D0F0xE4_WRAP_8012 Register Definition **** +// Address +#define D0F0xE4_WRAP_8012_ADDRESS 0x8012 + +// Type +#define D0F0xE4_WRAP_8012_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_OFFSET 0 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_MASK 0x3f +#define D0F0xE4_WRAP_8012_Reserved_6_6_OFFSET 6 +#define D0F0xE4_WRAP_8012_Reserved_6_6_WIDTH 1 +#define D0F0xE4_WRAP_8012_Reserved_6_6_MASK 0x40 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_OFFSET 7 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_MASK 0x80 +#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_OFFSET 8 +#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_WIDTH 6 +#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_MASK 0x3f00 +#define D0F0xE4_WRAP_8012_Reserved_15_14_OFFSET 14 +#define D0F0xE4_WRAP_8012_Reserved_15_14_WIDTH 2 +#define D0F0xE4_WRAP_8012_Reserved_15_14_MASK 0xc000 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_OFFSET 16 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_MASK 0x3f0000 +#define D0F0xE4_WRAP_8012_Reserved_22_22_OFFSET 22 +#define D0F0xE4_WRAP_8012_Reserved_22_22_WIDTH 1 +#define D0F0xE4_WRAP_8012_Reserved_22_22_MASK 0x400000 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_OFFSET 23 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_MASK 0x800000 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_OFFSET 24 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_WIDTH 6 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_MASK 0x3f000000 +#define D0F0xE4_WRAP_8012_Reserved_31_30_OFFSET 30 +#define D0F0xE4_WRAP_8012_Reserved_31_30_WIDTH 2 +#define D0F0xE4_WRAP_8012_Reserved_31_30_MASK 0xc0000000 + +/// D0F0xE4_WRAP_8012 +typedef union { + struct { ///< + UINT32 Pif1xIdleGateLatency:6 ; ///< + UINT32 Reserved_6_6:1 ; ///< + UINT32 Pif1xIdleGateEnable:1 ; ///< + UINT32 Pif1xIdleResumeLatency:6 ; ///< + UINT32 Reserved_15_14:2 ; ///< + UINT32 Pif2p5xIdleGateLatency:6 ; ///< + UINT32 Reserved_22_22:1 ; ///< + UINT32 Pif2p5xIdleGateEnable:1 ; ///< + UINT32 Pif2p5xIdleResumeLatency:6 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8012_STRUCT; + + +// **** D0F0xE4_WRAP_8021 Register Definition **** +// Address +#define D0F0xE4_WRAP_8021_ADDRESS 0x8021 + +// Type +#define D0F0xE4_WRAP_8021_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8021_Lanes10_OFFSET 0 +#define D0F0xE4_WRAP_8021_Lanes10_WIDTH 4 +#define D0F0xE4_WRAP_8021_Lanes10_MASK 0xf +#define D0F0xE4_WRAP_8021_Lanes32_OFFSET 4 +#define D0F0xE4_WRAP_8021_Lanes32_WIDTH 4 +#define D0F0xE4_WRAP_8021_Lanes32_MASK 0xf0 +#define D0F0xE4_WRAP_8021_Lanes54_OFFSET 8 +#define D0F0xE4_WRAP_8021_Lanes54_WIDTH 4 +#define D0F0xE4_WRAP_8021_Lanes54_MASK 0xf00 +#define D0F0xE4_WRAP_8021_Lanes76_OFFSET 12 +#define D0F0xE4_WRAP_8021_Lanes76_WIDTH 4 +#define D0F0xE4_WRAP_8021_Lanes76_MASK 0xf000 +#define D0F0xE4_WRAP_8021_Lanes98_OFFSET 16 +#define D0F0xE4_WRAP_8021_Lanes98_WIDTH 4 +#define D0F0xE4_WRAP_8021_Lanes98_MASK 0xf0000 +#define D0F0xE4_WRAP_8021_Lanes1110_OFFSET 20 +#define D0F0xE4_WRAP_8021_Lanes1110_WIDTH 4 +#define D0F0xE4_WRAP_8021_Lanes1110_MASK 0xf00000 +#define D0F0xE4_WRAP_8021_Lanes1312_OFFSET 24 +#define D0F0xE4_WRAP_8021_Lanes1312_WIDTH 4 +#define D0F0xE4_WRAP_8021_Lanes1312_MASK 0xf000000 +#define D0F0xE4_WRAP_8021_Lanes1514_OFFSET 28 +#define D0F0xE4_WRAP_8021_Lanes1514_WIDTH 4 +#define D0F0xE4_WRAP_8021_Lanes1514_MASK 0xf0000000 + +/// D0F0xE4_WRAP_8021 +typedef union { + struct { ///< + UINT32 Lanes10:4 ; ///< + UINT32 Lanes32:4 ; ///< + UINT32 Lanes54:4 ; ///< + UINT32 Lanes76:4 ; ///< + UINT32 Lanes98:4 ; ///< + UINT32 Lanes1110:4 ; ///< + UINT32 Lanes1312:4 ; ///< + UINT32 Lanes1514:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8021_STRUCT; + +// **** D0F0xE4_WRAP_8022 Register Definition **** +// Address +#define D0F0xE4_WRAP_8022_ADDRESS 0x8022 + +// Type +#define D0F0xE4_WRAP_8022_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8022_Lanes10_OFFSET 0 +#define D0F0xE4_WRAP_8022_Lanes10_WIDTH 4 +#define D0F0xE4_WRAP_8022_Lanes10_MASK 0xf +#define D0F0xE4_WRAP_8022_Lanes32_OFFSET 4 +#define D0F0xE4_WRAP_8022_Lanes32_WIDTH 4 +#define D0F0xE4_WRAP_8022_Lanes32_MASK 0xf0 +#define D0F0xE4_WRAP_8022_Lanes54_OFFSET 8 +#define D0F0xE4_WRAP_8022_Lanes54_WIDTH 4 +#define D0F0xE4_WRAP_8022_Lanes54_MASK 0xf00 +#define D0F0xE4_WRAP_8022_Lanes76_OFFSET 12 +#define D0F0xE4_WRAP_8022_Lanes76_WIDTH 4 +#define D0F0xE4_WRAP_8022_Lanes76_MASK 0xf000 +#define D0F0xE4_WRAP_8022_Lanes98_OFFSET 16 +#define D0F0xE4_WRAP_8022_Lanes98_WIDTH 4 +#define D0F0xE4_WRAP_8022_Lanes98_MASK 0xf0000 +#define D0F0xE4_WRAP_8022_Lanes1110_OFFSET 20 +#define D0F0xE4_WRAP_8022_Lanes1110_WIDTH 4 +#define D0F0xE4_WRAP_8022_Lanes1110_MASK 0xf00000 +#define D0F0xE4_WRAP_8022_Lanes1312_OFFSET 24 +#define D0F0xE4_WRAP_8022_Lanes1312_WIDTH 4 +#define D0F0xE4_WRAP_8022_Lanes1312_MASK 0xf000000 +#define D0F0xE4_WRAP_8022_Lanes1514_OFFSET 28 +#define D0F0xE4_WRAP_8022_Lanes1514_WIDTH 4 +#define D0F0xE4_WRAP_8022_Lanes1514_MASK 0xf0000000 + +/// D0F0xE4_WRAP_8022 +typedef union { + struct { ///< + UINT32 Lanes10:4 ; ///< + UINT32 Lanes32:4 ; ///< + UINT32 Lanes54:4 ; ///< + UINT32 Lanes76:4 ; ///< + UINT32 Lanes98:4 ; ///< + UINT32 Lanes1110:4 ; ///< + UINT32 Lanes1312:4 ; ///< + UINT32 Lanes1514:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8022_STRUCT; + +// **** D0F0xE4_WRAP_8023 Register Definition **** +// Address +#define D0F0xE4_WRAP_8023_ADDRESS 0x8023 + +// Type +#define D0F0xE4_WRAP_8023_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8023_LaneEnable_OFFSET 0 +#define D0F0xE4_WRAP_8023_LaneEnable_WIDTH 16 +#define D0F0xE4_WRAP_8023_LaneEnable_MASK 0xffff +#define D0F0xE4_WRAP_8023_Reserved_31_16_OFFSET 16 +#define D0F0xE4_WRAP_8023_Reserved_31_16_WIDTH 16 +#define D0F0xE4_WRAP_8023_Reserved_31_16_MASK 0xffff0000 + +/// D0F0xE4_WRAP_8023 +typedef union { + struct { ///< + UINT32 LaneEnable:16; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8023_STRUCT; + +// **** D0F0xE4_WRAP_8025 Register Definition **** +// Address +#define D0F0xE4_WRAP_8025_ADDRESS 0x8025 + +// Type +#define D0F0xE4_WRAP_8025_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_OFFSET 0 +#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_WIDTH 3 +#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_MASK 0x7 +#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_OFFSET 3 +#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_WIDTH 2 +#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_MASK 0x18 +#define D0F0xE4_WRAP_8025_LMLinkSpeed0_OFFSET 5 +#define D0F0xE4_WRAP_8025_LMLinkSpeed0_WIDTH 1 +#define D0F0xE4_WRAP_8025_LMLinkSpeed0_MASK 0x20 +#define D0F0xE4_WRAP_8025_Reserved_7_6_OFFSET 6 +#define D0F0xE4_WRAP_8025_Reserved_7_6_WIDTH 2 +#define D0F0xE4_WRAP_8025_Reserved_7_6_MASK 0xc0 +#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_OFFSET 8 +#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_WIDTH 3 +#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_MASK 0x700 +#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_OFFSET 11 +#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_WIDTH 2 +#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_MASK 0x1800 +#define D0F0xE4_WRAP_8025_LMLinkSpeed1_OFFSET 13 +#define D0F0xE4_WRAP_8025_LMLinkSpeed1_WIDTH 1 +#define D0F0xE4_WRAP_8025_LMLinkSpeed1_MASK 0x2000 +#define D0F0xE4_WRAP_8025_Reserved_15_14_OFFSET 14 +#define D0F0xE4_WRAP_8025_Reserved_15_14_WIDTH 2 +#define D0F0xE4_WRAP_8025_Reserved_15_14_MASK 0xc000 +#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_OFFSET 16 +#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_WIDTH 3 +#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_MASK 0x70000 +#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_OFFSET 19 +#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_WIDTH 2 +#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_MASK 0x180000 +#define D0F0xE4_WRAP_8025_LMLinkSpeed2_OFFSET 21 +#define D0F0xE4_WRAP_8025_LMLinkSpeed2_WIDTH 1 +#define D0F0xE4_WRAP_8025_LMLinkSpeed2_MASK 0x200000 +#define D0F0xE4_WRAP_8025_Reserved_23_22_OFFSET 22 +#define D0F0xE4_WRAP_8025_Reserved_23_22_WIDTH 2 +#define D0F0xE4_WRAP_8025_Reserved_23_22_MASK 0xc00000 +#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_OFFSET 24 +#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_WIDTH 3 +#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_MASK 0x7000000 +#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_OFFSET 27 +#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_WIDTH 2 +#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_MASK 0x18000000 +#define D0F0xE4_WRAP_8025_LMLinkSpeed3_OFFSET 29 +#define D0F0xE4_WRAP_8025_LMLinkSpeed3_WIDTH 1 +#define D0F0xE4_WRAP_8025_LMLinkSpeed3_MASK 0x20000000 +#define D0F0xE4_WRAP_8025_Reserved_31_30_OFFSET 30 +#define D0F0xE4_WRAP_8025_Reserved_31_30_WIDTH 2 +#define D0F0xE4_WRAP_8025_Reserved_31_30_MASK 0xc0000000 + +/// D0F0xE4_WRAP_8025 +typedef union { + struct { ///< + UINT32 LMTxPhyCmd0:3 ; ///< + UINT32 LMRxPhyCmd0:2 ; ///< + UINT32 LMLinkSpeed0:1 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 LMTxPhyCmd1:3 ; ///< + UINT32 LMRxPhyCmd1:2 ; ///< + UINT32 LMLinkSpeed1:1 ; ///< + UINT32 Reserved_15_14:2 ; ///< + UINT32 LMTxPhyCmd2:3 ; ///< + UINT32 LMRxPhyCmd2:2 ; ///< + UINT32 LMLinkSpeed2:1 ; ///< + UINT32 Reserved_23_22:2 ; ///< + UINT32 LMTxPhyCmd3:3 ; ///< + UINT32 LMRxPhyCmd3:2 ; ///< + UINT32 LMLinkSpeed3:1 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8025_STRUCT; + +// **** D0F0xE4_WRAP_8031 Register Definition **** +// Address +#define D0F0xE4_WRAP_8031_ADDRESS 0x8031 + +// Type +#define D0F0xE4_WRAP_8031_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8031_LnCntBandwidth_OFFSET 0 +#define D0F0xE4_WRAP_8031_LnCntBandwidth_WIDTH 10 +#define D0F0xE4_WRAP_8031_LnCntBandwidth_MASK 0x3ff +#define D0F0xE4_WRAP_8031_Reserved_15_10_OFFSET 10 +#define D0F0xE4_WRAP_8031_Reserved_15_10_WIDTH 6 +#define D0F0xE4_WRAP_8031_Reserved_15_10_MASK 0xfc00 +#define D0F0xE4_WRAP_8031_LnCntValid_OFFSET 16 +#define D0F0xE4_WRAP_8031_LnCntValid_WIDTH 1 +#define D0F0xE4_WRAP_8031_LnCntValid_MASK 0x10000 +#define D0F0xE4_WRAP_8031_Reserved_31_17_OFFSET 17 +#define D0F0xE4_WRAP_8031_Reserved_31_17_WIDTH 15 +#define D0F0xE4_WRAP_8031_Reserved_31_17_MASK 0xfffe0000 + +/// D0F0xE4_WRAP_8031 +typedef union { + struct { ///< + UINT32 LnCntBandwidth:10; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 LnCntValid:1 ; ///< + UINT32 Reserved_31_17:15; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8031_STRUCT; + +/// D0F0xE4_WRAP_8040 +typedef union { + struct { ///< + UINT32 OwnPhyA:1 ; ///< + UINT32 OwnPhyB:1 ; ///< + UINT32 OwnPhyC:1 ; ///< + UINT32 OwnPhyD:1 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 DigaPwrdnValue:3 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 DigbPwrdnValue:3 ; ///< + UINT32 Reserved_15_15:1 ; ///< + UINT32 CntPhyA:1 ; ///< + UINT32 CntPhyB:1 ; ///< + UINT32 CntPhyC:1 ; ///< + UINT32 CntPhyD:1 ; ///< + UINT32 CntDigA:1 ; ///< + UINT32 CntDigB:1 ; ///< + UINT32 ChangeLnSpd:1 ; ///< + UINT32 Reserved_31_23:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} ex502_STRUCT; + +// **** D0F0xE4_WRAP_8060 Register Definition **** +// Address +#define D0F0xE4_WRAP_8060_ADDRESS 0x8060 + +// Type +#define D0F0xE4_WRAP_8060_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8060_Reconfigure_OFFSET 0 +#define D0F0xE4_WRAP_8060_Reconfigure_WIDTH 1 +#define D0F0xE4_WRAP_8060_Reconfigure_MASK 0x1 +#define D0F0xE4_WRAP_8060_Reserved_1_1_OFFSET 1 +#define D0F0xE4_WRAP_8060_Reserved_1_1_WIDTH 1 +#define D0F0xE4_WRAP_8060_Reserved_1_1_MASK 0x2 +#define D0F0xE4_WRAP_8060_ResetComplete_OFFSET 2 +#define D0F0xE4_WRAP_8060_ResetComplete_WIDTH 1 +#define D0F0xE4_WRAP_8060_ResetComplete_MASK 0x4 +#define D0F0xE4_WRAP_8060_Reserved_15_3_OFFSET 3 +#define D0F0xE4_WRAP_8060_Reserved_15_3_WIDTH 13 +#define D0F0xE4_WRAP_8060_Reserved_15_3_MASK 0xfff8 +#define D0F0xE4_WRAP_8060_Reserved_31_18_OFFSET 18 +#define D0F0xE4_WRAP_8060_Reserved_31_18_WIDTH 14 +#define D0F0xE4_WRAP_8060_Reserved_31_18_MASK 0xfffc0000 + +/// D0F0xE4_WRAP_8060 +typedef union { + struct { ///< + UINT32 Reconfigure:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 ResetComplete:1 ; ///< + UINT32 Reserved_15_3:13; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 Reserved_31_18:14; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8060_STRUCT; + +// **** D0F0xE4_WRAP_8062 Register Definition **** +// Address +#define D0F0xE4_WRAP_8062_ADDRESS 0x8062 + +// Type +#define D0F0xE4_WRAP_8062_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8062_ReconfigureEn_OFFSET 0 +#define D0F0xE4_WRAP_8062_ReconfigureEn_WIDTH 1 +#define D0F0xE4_WRAP_8062_ReconfigureEn_MASK 0x1 +#define D0F0xE4_WRAP_8062_Reserved_1_1_OFFSET 1 +#define D0F0xE4_WRAP_8062_Reserved_1_1_WIDTH 1 +#define D0F0xE4_WRAP_8062_Reserved_1_1_MASK 0x2 +#define D0F0xE4_WRAP_8062_ResetPeriod_OFFSET 2 +#define D0F0xE4_WRAP_8062_ResetPeriod_WIDTH 3 +#define D0F0xE4_WRAP_8062_ResetPeriod_MASK 0x1c +#define D0F0xE4_WRAP_8062_Reserved_9_5_OFFSET 5 +#define D0F0xE4_WRAP_8062_Reserved_9_5_WIDTH 5 +#define D0F0xE4_WRAP_8062_Reserved_9_5_MASK 0x3e0 +#define D0F0xE4_WRAP_8062_BlockOnIdle_OFFSET 10 +#define D0F0xE4_WRAP_8062_BlockOnIdle_WIDTH 1 +#define D0F0xE4_WRAP_8062_BlockOnIdle_MASK 0x400 +#define D0F0xE4_WRAP_8062_ConfigXferMode_OFFSET 11 +#define D0F0xE4_WRAP_8062_ConfigXferMode_WIDTH 1 +#define D0F0xE4_WRAP_8062_ConfigXferMode_MASK 0x800 +#define D0F0xE4_WRAP_8062_Reserved_31_12_OFFSET 12 +#define D0F0xE4_WRAP_8062_Reserved_31_12_WIDTH 20 +#define D0F0xE4_WRAP_8062_Reserved_31_12_MASK 0xfffff000 + +/// D0F0xE4_WRAP_8062 +typedef union { + struct { ///< + UINT32 ReconfigureEn:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 ResetPeriod:3 ; ///< + UINT32 Reserved_9_5:5 ; ///< + UINT32 BlockOnIdle:1 ; ///< + UINT32 ConfigXferMode:1 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8062_STRUCT; + +// **** D0F0xE4_WRAP_80F0 Register Definition **** +// Address +#define D0F0xE4_WRAP_80F0_ADDRESS 0x80f0 + +// Type +#define D0F0xE4_WRAP_80F0_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_80F0_MicroSeconds_OFFSET 0 +#define D0F0xE4_WRAP_80F0_MicroSeconds_WIDTH 32 +#define D0F0xE4_WRAP_80F0_MicroSeconds_MASK 0xffffffff + +/// D0F0xE4_WRAP_80F0 +typedef union { + struct { ///< + UINT32 MicroSeconds:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_80F0_STRUCT; + +// **** D0F0xE4_WRAP_80F1 Register Definition **** +// Address +#define D0F0xE4_WRAP_80F1_ADDRESS 0x80f1 + +// Type +#define D0F0xE4_WRAP_80F1_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_80F1_ClockRate_OFFSET 0 +#define D0F0xE4_WRAP_80F1_ClockRate_WIDTH 8 +#define D0F0xE4_WRAP_80F1_ClockRate_MASK 0xff +#define D0F0xE4_WRAP_80F1_Reserved_31_8_OFFSET 8 +#define D0F0xE4_WRAP_80F1_Reserved_31_8_WIDTH 24 +#define D0F0xE4_WRAP_80F1_Reserved_31_8_MASK 0xffffff00 + +/// D0F0xE4_WRAP_80F1 +typedef union { + struct { ///< + UINT32 ClockRate:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_80F1_STRUCT; + +// **** D0F0xE4_PIF_0010 Register Definition **** +// Address +#define D0F0xE4_PIF_0010_ADDRESS 0x10 + +// Type +#define D0F0xE4_PIF_0010_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PIF_0010_Reserved_3_0_OFFSET 0 +#define D0F0xE4_PIF_0010_Reserved_3_0_WIDTH 4 +#define D0F0xE4_PIF_0010_Reserved_3_0_MASK 0xf +#define D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET 4 +#define D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH 1 +#define D0F0xE4_PIF_0010_EiDetCycleMode_MASK 0x10 +#define D0F0xE4_PIF_0010_Reserved_5_5_OFFSET 5 +#define D0F0xE4_PIF_0010_Reserved_5_5_WIDTH 1 +#define D0F0xE4_PIF_0010_Reserved_5_5_MASK 0x20 +#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_OFFSET 6 +#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_WIDTH 1 +#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_MASK 0x40 +#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_OFFSET 7 +#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_WIDTH 1 +#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_MASK 0x80 +#define D0F0xE4_PIF_0010_Reserved_16_8_OFFSET 8 +#define D0F0xE4_PIF_0010_Reserved_16_8_WIDTH 9 +#define D0F0xE4_PIF_0010_Reserved_16_8_MASK 0x1ff00 +#define D0F0xE4_PIF_0010_Ls2ExitTime_OFFSET 17 +#define D0F0xE4_PIF_0010_Ls2ExitTime_WIDTH 3 +#define D0F0xE4_PIF_0010_Ls2ExitTime_MASK 0xe0000 +#define D0F0xE4_PIF_0010_Reserved_31_23_OFFSET 23 +#define D0F0xE4_PIF_0010_Reserved_31_23_WIDTH 9 +#define D0F0xE4_PIF_0010_Reserved_31_23_MASK 0xff800000 + +/// D0F0xE4_PIF_0010 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 EiDetCycleMode:1 ; ///< + UINT32 Reserved_5_5:1 ; ///< + UINT32 RxDetectFifoResetMode:1 ; ///< + UINT32 RxDetectTxPwrMode:1 ; ///< + UINT32 Reserved_16_8:9 ; ///< + UINT32 Ls2ExitTime:3 ; ///< + UINT32 :3 ; ///< + UINT32 Reserved_31_23:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PIF_0010_STRUCT; + +// **** D0F0xE4_PIF_0011 Register Definition **** +// Address +#define D0F0xE4_PIF_0011_ADDRESS 0x11 + +// Type +#define D0F0xE4_PIF_0011_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PIF_0011_X2Lane10_OFFSET 0 +#define D0F0xE4_PIF_0011_X2Lane10_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane10_MASK 0x1 +#define D0F0xE4_PIF_0011_X2Lane32_OFFSET 1 +#define D0F0xE4_PIF_0011_X2Lane32_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane32_MASK 0x2 +#define D0F0xE4_PIF_0011_X2Lane54_OFFSET 2 +#define D0F0xE4_PIF_0011_X2Lane54_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane54_MASK 0x4 +#define D0F0xE4_PIF_0011_X2Lane76_OFFSET 3 +#define D0F0xE4_PIF_0011_X2Lane76_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane76_MASK 0x8 +#define D0F0xE4_PIF_0011_Reserved_7_4_OFFSET 4 +#define D0F0xE4_PIF_0011_Reserved_7_4_WIDTH 4 +#define D0F0xE4_PIF_0011_Reserved_7_4_MASK 0xf0 +#define D0F0xE4_PIF_0011_X4Lane30_OFFSET 8 +#define D0F0xE4_PIF_0011_X4Lane30_WIDTH 1 +#define D0F0xE4_PIF_0011_X4Lane30_MASK 0x100 +#define D0F0xE4_PIF_0011_X4Lane74_OFFSET 9 +#define D0F0xE4_PIF_0011_X4Lane74_WIDTH 1 +#define D0F0xE4_PIF_0011_X4Lane74_MASK 0x200 +#define D0F0xE4_PIF_0011_Reserved_11_10_OFFSET 10 +#define D0F0xE4_PIF_0011_Reserved_11_10_WIDTH 2 +#define D0F0xE4_PIF_0011_Reserved_11_10_MASK 0xc00 +#define D0F0xE4_PIF_0011_X4Lane52_OFFSET 12 +#define D0F0xE4_PIF_0011_X4Lane52_WIDTH 1 +#define D0F0xE4_PIF_0011_X4Lane52_MASK 0x1000 +#define D0F0xE4_PIF_0011_Reserved_15_13_OFFSET 13 +#define D0F0xE4_PIF_0011_Reserved_15_13_WIDTH 3 +#define D0F0xE4_PIF_0011_Reserved_15_13_MASK 0xe000 +#define D0F0xE4_PIF_0011_X8Lane70_OFFSET 16 +#define D0F0xE4_PIF_0011_X8Lane70_WIDTH 1 +#define D0F0xE4_PIF_0011_X8Lane70_MASK 0x10000 +#define D0F0xE4_PIF_0011_Reserved_24_17_OFFSET 17 +#define D0F0xE4_PIF_0011_Reserved_24_17_WIDTH 8 +#define D0F0xE4_PIF_0011_Reserved_24_17_MASK 0x1fe0000 +#define D0F0xE4_PIF_0011_MultiPif_OFFSET 25 +#define D0F0xE4_PIF_0011_MultiPif_WIDTH 1 +#define D0F0xE4_PIF_0011_MultiPif_MASK 0x2000000 +#define D0F0xE4_PIF_0011_Reserved_31_26_OFFSET 26 +#define D0F0xE4_PIF_0011_Reserved_31_26_WIDTH 6 +#define D0F0xE4_PIF_0011_Reserved_31_26_MASK 0xfc000000 + +/// D0F0xE4_PIF_0011 +typedef union { + struct { ///< + UINT32 X2Lane10:1 ; ///< + UINT32 X2Lane32:1 ; ///< + UINT32 X2Lane54:1 ; ///< + UINT32 X2Lane76:1 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 X4Lane30:1 ; ///< + UINT32 X4Lane74:1 ; ///< + UINT32 Reserved_11_10:2 ; ///< + UINT32 X4Lane52:1 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 X8Lane70:1 ; ///< + UINT32 Reserved_24_17:8 ; ///< + UINT32 MultiPif:1 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PIF_0011_STRUCT; + +// **** D0F0xE4_PIF_0012 Register Definition **** +// Address +#define D0F0xE4_PIF_0012_ADDRESS 0x12 + +// Type +#define D0F0xE4_PIF_0012_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_OFFSET 0 +#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_WIDTH 3 +#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_MASK 0x7 +#define D0F0xE4_PIF_0012_ForceRxEnInL0s_OFFSET 3 +#define D0F0xE4_PIF_0012_ForceRxEnInL0s_WIDTH 1 +#define D0F0xE4_PIF_0012_ForceRxEnInL0s_MASK 0x8 +#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_OFFSET 4 +#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_WIDTH 3 +#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_MASK 0x70 +#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_OFFSET 7 +#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_WIDTH 3 +#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_MASK 0x380 +#define D0F0xE4_PIF_0012_PllPowerStateInOff_OFFSET 10 +#define D0F0xE4_PIF_0012_PllPowerStateInOff_WIDTH 3 +#define D0F0xE4_PIF_0012_PllPowerStateInOff_MASK 0x1c00 +#define D0F0xE4_PIF_0012_Reserved_15_13_OFFSET 13 +#define D0F0xE4_PIF_0012_Reserved_15_13_WIDTH 3 +#define D0F0xE4_PIF_0012_Reserved_15_13_MASK 0xe000 +#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_OFFSET 16 +#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_WIDTH 1 +#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_MASK 0x10000 +#define D0F0xE4_PIF_0012_Reserved_23_17_OFFSET 17 +#define D0F0xE4_PIF_0012_Reserved_23_17_WIDTH 7 +#define D0F0xE4_PIF_0012_Reserved_23_17_MASK 0xfe0000 +#define D0F0xE4_PIF_0012_PllRampUpTime_OFFSET 24 +#define D0F0xE4_PIF_0012_PllRampUpTime_WIDTH 3 +#define D0F0xE4_PIF_0012_PllRampUpTime_MASK 0x7000000 +#define D0F0xE4_PIF_0012_Reserved_27_27_OFFSET 27 +#define D0F0xE4_PIF_0012_Reserved_27_27_WIDTH 1 +#define D0F0xE4_PIF_0012_Reserved_27_27_MASK 0x8000000 +#define D0F0xE4_PIF_0012_PllPwrOverrideEn_OFFSET 28 +#define D0F0xE4_PIF_0012_PllPwrOverrideEn_WIDTH 1 +#define D0F0xE4_PIF_0012_PllPwrOverrideEn_MASK 0x10000000 +#define D0F0xE4_PIF_0012_PllPwrOverrideVal_OFFSET 29 +#define D0F0xE4_PIF_0012_PllPwrOverrideVal_WIDTH 3 +#define D0F0xE4_PIF_0012_PllPwrOverrideVal_MASK 0xe0000000 + +/// D0F0xE4_PIF_0012 +typedef union { + struct { ///< + UINT32 TxPowerStateInTxs2:3 ; ///< + UINT32 ForceRxEnInL0s:1 ; ///< + UINT32 RxPowerStateInRxs2:3 ; ///< + UINT32 PllPowerStateInTxs2:3 ; ///< + UINT32 PllPowerStateInOff:3 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 Tx2p5clkClockGatingEn:1 ; ///< + UINT32 Reserved_23_17:7 ; ///< + UINT32 PllRampUpTime:3 ; ///< + UINT32 Reserved_27_27:1 ; ///< + UINT32 PllPwrOverrideEn:1 ; ///< + UINT32 PllPwrOverrideVal:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PIF_0012_STRUCT; + +// **** D0F0xE4_PIF_0013 Register Definition **** +// Address +#define D0F0xE4_PIF_0013_ADDRESS 0x13 + +// Type +#define D0F0xE4_PIF_0013_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_OFFSET 0 +#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_WIDTH 3 +#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_MASK 0x7 +#define D0F0xE4_PIF_0013_ForceRxEnInL0s_OFFSET 3 +#define D0F0xE4_PIF_0013_ForceRxEnInL0s_WIDTH 1 +#define D0F0xE4_PIF_0013_ForceRxEnInL0s_MASK 0x8 +#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_OFFSET 4 +#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_WIDTH 3 +#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_MASK 0x70 +#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_OFFSET 7 +#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_WIDTH 3 +#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_MASK 0x380 +#define D0F0xE4_PIF_0013_PllPowerStateInOff_OFFSET 10 +#define D0F0xE4_PIF_0013_PllPowerStateInOff_WIDTH 3 +#define D0F0xE4_PIF_0013_PllPowerStateInOff_MASK 0x1c00 +#define D0F0xE4_PIF_0013_Reserved_15_13_OFFSET 13 +#define D0F0xE4_PIF_0013_Reserved_15_13_WIDTH 3 +#define D0F0xE4_PIF_0013_Reserved_15_13_MASK 0xe000 +#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_OFFSET 16 +#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_WIDTH 1 +#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_MASK 0x10000 +#define D0F0xE4_PIF_0013_Reserved_23_17_OFFSET 17 +#define D0F0xE4_PIF_0013_Reserved_23_17_WIDTH 7 +#define D0F0xE4_PIF_0013_Reserved_23_17_MASK 0xfe0000 +#define D0F0xE4_PIF_0013_PllRampUpTime_OFFSET 24 +#define D0F0xE4_PIF_0013_PllRampUpTime_WIDTH 3 +#define D0F0xE4_PIF_0013_PllRampUpTime_MASK 0x7000000 +#define D0F0xE4_PIF_0013_Reserved_27_27_OFFSET 27 +#define D0F0xE4_PIF_0013_Reserved_27_27_WIDTH 1 +#define D0F0xE4_PIF_0013_Reserved_27_27_MASK 0x8000000 +#define D0F0xE4_PIF_0013_PllPwrOverrideEn_OFFSET 28 +#define D0F0xE4_PIF_0013_PllPwrOverrideEn_WIDTH 1 +#define D0F0xE4_PIF_0013_PllPwrOverrideEn_MASK 0x10000000 +#define D0F0xE4_PIF_0013_PllPwrOverrideVal_OFFSET 29 +#define D0F0xE4_PIF_0013_PllPwrOverrideVal_WIDTH 3 +#define D0F0xE4_PIF_0013_PllPwrOverrideVal_MASK 0xe0000000 + +/// D0F0xE4_PIF_0013 +typedef union { + struct { ///< + UINT32 TxPowerStateInTxs2:3 ; ///< + UINT32 ForceRxEnInL0s:1 ; ///< + UINT32 RxPowerStateInRxs2:3 ; ///< + UINT32 PllPowerStateInTxs2:3 ; ///< + UINT32 PllPowerStateInOff:3 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 Tx2p5clkClockGatingEn:1 ; ///< + UINT32 Reserved_23_17:7 ; ///< + UINT32 PllRampUpTime:3 ; ///< + UINT32 Reserved_27_27:1 ; ///< + UINT32 PllPwrOverrideEn:1 ; ///< + UINT32 PllPwrOverrideVal:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PIF_0013_STRUCT; + +// **** D0F0xE4_PIF_0015 Register Definition **** +// Address +#define D0F0xE4_PIF_0015_ADDRESS 0x15 + +// Type +#define D0F0xE4_PIF_0015_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PIF_0015_TxPhyStatus00_OFFSET 0 +#define D0F0xE4_PIF_0015_TxPhyStatus00_WIDTH 1 +#define D0F0xE4_PIF_0015_TxPhyStatus00_MASK 0x1 +#define D0F0xE4_PIF_0015_TxPhyStatus01_OFFSET 1 +#define D0F0xE4_PIF_0015_TxPhyStatus01_WIDTH 1 +#define D0F0xE4_PIF_0015_TxPhyStatus01_MASK 0x2 +#define D0F0xE4_PIF_0015_TxPhyStatus02_OFFSET 2 +#define D0F0xE4_PIF_0015_TxPhyStatus02_WIDTH 1 +#define D0F0xE4_PIF_0015_TxPhyStatus02_MASK 0x4 +#define D0F0xE4_PIF_0015_TxPhyStatus03_OFFSET 3 +#define D0F0xE4_PIF_0015_TxPhyStatus03_WIDTH 1 +#define D0F0xE4_PIF_0015_TxPhyStatus03_MASK 0x8 +#define D0F0xE4_PIF_0015_TxPhyStatus04_OFFSET 4 +#define D0F0xE4_PIF_0015_TxPhyStatus04_WIDTH 1 +#define D0F0xE4_PIF_0015_TxPhyStatus04_MASK 0x10 +#define D0F0xE4_PIF_0015_TxPhyStatus05_OFFSET 5 +#define D0F0xE4_PIF_0015_TxPhyStatus05_WIDTH 1 +#define D0F0xE4_PIF_0015_TxPhyStatus05_MASK 0x20 +#define D0F0xE4_PIF_0015_TxPhyStatus06_OFFSET 6 +#define D0F0xE4_PIF_0015_TxPhyStatus06_WIDTH 1 +#define D0F0xE4_PIF_0015_TxPhyStatus06_MASK 0x40 +#define D0F0xE4_PIF_0015_TxPhyStatus07_OFFSET 7 +#define D0F0xE4_PIF_0015_TxPhyStatus07_WIDTH 1 +#define D0F0xE4_PIF_0015_TxPhyStatus07_MASK 0x80 +#define D0F0xE4_PIF_0015_Reserved_31_8_OFFSET 8 +#define D0F0xE4_PIF_0015_Reserved_31_8_WIDTH 24 +#define D0F0xE4_PIF_0015_Reserved_31_8_MASK 0xffffff00 + +/// D0F0xE4_PIF_0015 +typedef union { + struct { ///< + UINT32 TxPhyStatus00:1 ; ///< + UINT32 TxPhyStatus01:1 ; ///< + UINT32 TxPhyStatus02:1 ; ///< + UINT32 TxPhyStatus03:1 ; ///< + UINT32 TxPhyStatus04:1 ; ///< + UINT32 TxPhyStatus05:1 ; ///< + UINT32 TxPhyStatus06:1 ; ///< + UINT32 TxPhyStatus07:1 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PIF_0015_STRUCT; + +// **** D0F0xE4_CORE_0002 Register Definition **** +// Address +#define D0F0xE4_CORE_0002_ADDRESS 0x2 + +// Type +#define D0F0xE4_CORE_0002_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_0002_HwDebug_0__OFFSET 0 +#define D0F0xE4_CORE_0002_HwDebug_0__WIDTH 1 +#define D0F0xE4_CORE_0002_HwDebug_0__MASK 0x1 +#define D0F0xE4_CORE_0002_Reserved_31_1_OFFSET 1 +#define D0F0xE4_CORE_0002_Reserved_31_1_WIDTH 31 +#define D0F0xE4_CORE_0002_Reserved_31_1_MASK 0xfffffffe + +/// D0F0xE4_CORE_0002 +typedef union { + struct { ///< + UINT32 HwDebug_0_:1 ; ///< + UINT32 Reserved_31_1:31; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_0002_STRUCT; + + + +// **** D0F0xE4_CORE_001C Register Definition **** +// Address +#define D0F0xE4_CORE_001C_ADDRESS 0x1c + +// Type +#define D0F0xE4_CORE_001C_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET 0 +#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_WIDTH 1 +#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK 0x1 +#define D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET 1 +#define D0F0xE4_CORE_001C_TxArbSlvLimit_WIDTH 5 +#define D0F0xE4_CORE_001C_TxArbSlvLimit_MASK 0x3e +#define D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET 6 +#define D0F0xE4_CORE_001C_TxArbMstLimit_WIDTH 5 +#define D0F0xE4_CORE_001C_TxArbMstLimit_MASK 0x7c0 +#define D0F0xE4_CORE_001C_Reserved_31_11_OFFSET 11 +#define D0F0xE4_CORE_001C_Reserved_31_11_WIDTH 21 +#define D0F0xE4_CORE_001C_Reserved_31_11_MASK 0xfffff800 + +/// D0F0xE4_CORE_001C +typedef union { + struct { ///< + UINT32 TxArbRoundRobinEn:1 ; ///< + UINT32 TxArbSlvLimit:5 ; ///< + UINT32 TxArbMstLimit:5 ; ///< + UINT32 Reserved_31_11:21; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_001C_STRUCT; + +// **** D0F0xE4_CORE_0040 Register Definition **** +// Address +#define D0F0xE4_CORE_0040_ADDRESS 0x40 + +// Type +#define D0F0xE4_CORE_0040_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_0040_Reserved_13_0_OFFSET 0 +#define D0F0xE4_CORE_0040_Reserved_13_0_WIDTH 14 +#define D0F0xE4_CORE_0040_Reserved_13_0_MASK 0x3fff +#define D0F0xE4_CORE_0040_PElecIdleMode_OFFSET 14 +#define D0F0xE4_CORE_0040_PElecIdleMode_WIDTH 2 +#define D0F0xE4_CORE_0040_PElecIdleMode_MASK 0xc000 +#define D0F0xE4_CORE_0040_Reserved_31_16_OFFSET 16 +#define D0F0xE4_CORE_0040_Reserved_31_16_WIDTH 16 +#define D0F0xE4_CORE_0040_Reserved_31_16_MASK 0xffff0000 + +/// D0F0xE4_CORE_0040 +typedef union { + struct { ///< + UINT32 Reserved_13_0:14; ///< + UINT32 PElecIdleMode:2 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_0040_STRUCT; + +// **** D0F0xE4_CORE_00B0 Register Definition **** +// Address +#define D0F0xE4_CORE_00B0_ADDRESS 0xb0 + +// Type +#define D0F0xE4_CORE_00B0_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_00B0_Reserved_1_0_OFFSET 0 +#define D0F0xE4_CORE_00B0_Reserved_1_0_WIDTH 2 +#define D0F0xE4_CORE_00B0_Reserved_1_0_MASK 0x3 +#define D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET 2 +#define D0F0xE4_CORE_00B0_StrapF0MsiEn_WIDTH 1 +#define D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK 0x4 +#define D0F0xE4_CORE_00B0_Reserved_4_3_OFFSET 3 +#define D0F0xE4_CORE_00B0_Reserved_4_3_WIDTH 2 +#define D0F0xE4_CORE_00B0_Reserved_4_3_MASK 0x18 +#define D0F0xE4_CORE_00B0_StrapF0AerEn_OFFSET 5 +#define D0F0xE4_CORE_00B0_StrapF0AerEn_WIDTH 1 +#define D0F0xE4_CORE_00B0_StrapF0AerEn_MASK 0x20 +#define D0F0xE4_CORE_00B0_Reserved_31_6_OFFSET 6 +#define D0F0xE4_CORE_00B0_Reserved_31_6_WIDTH 26 +#define D0F0xE4_CORE_00B0_Reserved_31_6_MASK 0xffffffc0 + +/// D0F0xE4_CORE_00B0 +typedef union { + struct { ///< + UINT32 Reserved_1_0:2 ; ///< + UINT32 StrapF0MsiEn:1 ; ///< + UINT32 Reserved_4_3:2 ; ///< + UINT32 StrapF0AerEn:1 ; ///< + UINT32 Reserved_31_6:26; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_00B0_STRUCT; + + +// **** D0F0xE4_CORE_00C1 Register Definition **** +// Address +#define D0F0xE4_CORE_00C1_ADDRESS 0xc1 + +// Type +#define D0F0xE4_CORE_00C1_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET 0 +#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_WIDTH 1 +#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK 0x1 +#define D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET 1 +#define D0F0xE4_CORE_00C1_StrapGen2Compliance_WIDTH 1 +#define D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK 0x2 +#define D0F0xE4_CORE_00C1_Reserved_31_2_OFFSET 2 +#define D0F0xE4_CORE_00C1_Reserved_31_2_WIDTH 30 +#define D0F0xE4_CORE_00C1_Reserved_31_2_MASK 0xfffffffc + +/// D0F0xE4_CORE_00C1 +typedef union { + struct { ///< + UINT32 StrapLinkBwNotificationCapEn:1 ; ///< + UINT32 StrapGen2Compliance:1 ; ///< + UINT32 Reserved_31_2:30; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_00C1_STRUCT; + +// **** D0F0xE4_PHY_0009 Register Definition **** +// Address +#define D0F0xE4_PHY_0009_ADDRESS 0x9 + +// Type +#define D0F0xE4_PHY_0009_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_0009_Reserved_23_0_OFFSET 0 +#define D0F0xE4_PHY_0009_Reserved_23_0_WIDTH 24 +#define D0F0xE4_PHY_0009_Reserved_23_0_MASK 0xffffff +#define D0F0xE4_PHY_0009_ClkOff_OFFSET 24 +#define D0F0xE4_PHY_0009_ClkOff_WIDTH 1 +#define D0F0xE4_PHY_0009_ClkOff_MASK 0x1000000 +#define D0F0xE4_PHY_0009_DisplayStream_OFFSET 25 +#define D0F0xE4_PHY_0009_DisplayStream_WIDTH 1 +#define D0F0xE4_PHY_0009_DisplayStream_MASK 0x2000000 +#define D0F0xE4_PHY_0009_Reserved_27_26_OFFSET 26 +#define D0F0xE4_PHY_0009_Reserved_27_26_WIDTH 2 +#define D0F0xE4_PHY_0009_Reserved_27_26_MASK 0xc000000 +#define D0F0xE4_PHY_0009_CascadedPllSel_OFFSET 28 +#define D0F0xE4_PHY_0009_CascadedPllSel_WIDTH 1 +#define D0F0xE4_PHY_0009_CascadedPllSel_MASK 0x10000000 +#define D0F0xE4_PHY_0009_Reserved_30_29_OFFSET 29 +#define D0F0xE4_PHY_0009_Reserved_30_29_WIDTH 2 +#define D0F0xE4_PHY_0009_Reserved_30_29_MASK 0x60000000 +#define D0F0xE4_PHY_0009_PCIePllSel_OFFSET 31 +#define D0F0xE4_PHY_0009_PCIePllSel_WIDTH 1 +#define D0F0xE4_PHY_0009_PCIePllSel_MASK 0x80000000 + +/// D0F0xE4_PHY_0009 +typedef union { + struct { ///< + UINT32 Reserved_23_0:24; ///< + UINT32 ClkOff:1 ; ///< + UINT32 DisplayStream:1 ; ///< + UINT32 Reserved_27_26:2 ; ///< + UINT32 CascadedPllSel:1 ; ///< + UINT32 Reserved_30_29:2 ; ///< + UINT32 PCIePllSel:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_0009_STRUCT; + +// **** D0F0xE4_PHY_000A Register Definition **** +// Address +#define D0F0xE4_PHY_000A_ADDRESS 0xa + +// Type +#define D0F0xE4_PHY_000A_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_000A_Reserved_23_0_OFFSET 0 +#define D0F0xE4_PHY_000A_Reserved_23_0_WIDTH 24 +#define D0F0xE4_PHY_000A_Reserved_23_0_MASK 0xffffff +#define D0F0xE4_PHY_000A_ClkOff_OFFSET 24 +#define D0F0xE4_PHY_000A_ClkOff_WIDTH 1 +#define D0F0xE4_PHY_000A_ClkOff_MASK 0x1000000 +#define D0F0xE4_PHY_000A_DisplayStream_OFFSET 25 +#define D0F0xE4_PHY_000A_DisplayStream_WIDTH 1 +#define D0F0xE4_PHY_000A_DisplayStream_MASK 0x2000000 +#define D0F0xE4_PHY_000A_Reserved_27_26_OFFSET 26 +#define D0F0xE4_PHY_000A_Reserved_27_26_WIDTH 2 +#define D0F0xE4_PHY_000A_Reserved_27_26_MASK 0xc000000 +#define D0F0xE4_PHY_000A_CascadedPllSel_OFFSET 28 +#define D0F0xE4_PHY_000A_CascadedPllSel_WIDTH 1 +#define D0F0xE4_PHY_000A_CascadedPllSel_MASK 0x10000000 +#define D0F0xE4_PHY_000A_Reserved_30_29_OFFSET 29 +#define D0F0xE4_PHY_000A_Reserved_30_29_WIDTH 2 +#define D0F0xE4_PHY_000A_Reserved_30_29_MASK 0x60000000 +#define D0F0xE4_PHY_000A_PCIePllSel_OFFSET 31 +#define D0F0xE4_PHY_000A_PCIePllSel_WIDTH 1 +#define D0F0xE4_PHY_000A_PCIePllSel_MASK 0x80000000 + +/// D0F0xE4_PHY_000A +typedef union { + struct { ///< + UINT32 Reserved_23_0:24; ///< + UINT32 ClkOff:1 ; ///< + UINT32 DisplayStream:1 ; ///< + UINT32 Reserved_27_26:2 ; ///< + UINT32 CascadedPllSel:1 ; ///< + UINT32 Reserved_30_29:2 ; ///< + UINT32 PCIePllSel:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_000A_STRUCT; + +// **** D0F0xE4_PHY_000B Register Definition **** +// Address +#define D0F0xE4_PHY_000B_ADDRESS 0xb + +// Type +#define D0F0xE4_PHY_000B_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_000B_TxPwrSbiEn_OFFSET 0 +#define D0F0xE4_PHY_000B_TxPwrSbiEn_WIDTH 1 +#define D0F0xE4_PHY_000B_TxPwrSbiEn_MASK 0x1 +#define D0F0xE4_PHY_000B_RxPwrSbiEn_OFFSET 1 +#define D0F0xE4_PHY_000B_RxPwrSbiEn_WIDTH 1 +#define D0F0xE4_PHY_000B_RxPwrSbiEn_MASK 0x2 +#define D0F0xE4_PHY_000B_PcieModeSbiEn_OFFSET 2 +#define D0F0xE4_PHY_000B_PcieModeSbiEn_WIDTH 1 +#define D0F0xE4_PHY_000B_PcieModeSbiEn_MASK 0x4 +#define D0F0xE4_PHY_000B_FreqDivSbiEn_OFFSET 3 +#define D0F0xE4_PHY_000B_FreqDivSbiEn_WIDTH 1 +#define D0F0xE4_PHY_000B_FreqDivSbiEn_MASK 0x8 +#define D0F0xE4_PHY_000B_DllLockSbiEn_OFFSET 4 +#define D0F0xE4_PHY_000B_DllLockSbiEn_WIDTH 1 +#define D0F0xE4_PHY_000B_DllLockSbiEn_MASK 0x10 +#define D0F0xE4_PHY_000B_OffsetCancelSbiEn_OFFSET 5 +#define D0F0xE4_PHY_000B_OffsetCancelSbiEn_WIDTH 1 +#define D0F0xE4_PHY_000B_OffsetCancelSbiEn_MASK 0x20 +#define D0F0xE4_PHY_000B_SkipBitSbiEn_OFFSET 6 +#define D0F0xE4_PHY_000B_SkipBitSbiEn_WIDTH 1 +#define D0F0xE4_PHY_000B_SkipBitSbiEn_MASK 0x40 +#define D0F0xE4_PHY_000B_IncoherentClkSbiEn_OFFSET 7 +#define D0F0xE4_PHY_000B_IncoherentClkSbiEn_WIDTH 1 +#define D0F0xE4_PHY_000B_IncoherentClkSbiEn_MASK 0x80 +#define D0F0xE4_PHY_000B_EiDetSbiEn_OFFSET 8 +#define D0F0xE4_PHY_000B_EiDetSbiEn_WIDTH 1 +#define D0F0xE4_PHY_000B_EiDetSbiEn_MASK 0x100 +#define D0F0xE4_PHY_000B_Reserved_13_9_OFFSET 9 +#define D0F0xE4_PHY_000B_Reserved_13_9_WIDTH 5 +#define D0F0xE4_PHY_000B_Reserved_13_9_MASK 0x3e00 +#define D0F0xE4_PHY_000B_MargPktSbiEn_OFFSET 14 +#define D0F0xE4_PHY_000B_MargPktSbiEn_WIDTH 1 +#define D0F0xE4_PHY_000B_MargPktSbiEn_MASK 0x4000 +#define D0F0xE4_PHY_000B_PllCmpPktSbiEn_OFFSET 15 +#define D0F0xE4_PHY_000B_PllCmpPktSbiEn_WIDTH 1 +#define D0F0xE4_PHY_000B_PllCmpPktSbiEn_MASK 0x8000 +#define D0F0xE4_PHY_000B_Reserved_31_16_OFFSET 16 +#define D0F0xE4_PHY_000B_Reserved_31_16_WIDTH 16 +#define D0F0xE4_PHY_000B_Reserved_31_16_MASK 0xffff0000 + +/// D0F0xE4_PHY_000B +typedef union { + struct { ///< + UINT32 TxPwrSbiEn:1 ; ///< + UINT32 RxPwrSbiEn:1 ; ///< + UINT32 PcieModeSbiEn:1 ; ///< + UINT32 FreqDivSbiEn:1 ; ///< + UINT32 DllLockSbiEn:1 ; ///< + UINT32 OffsetCancelSbiEn:1 ; ///< + UINT32 SkipBitSbiEn:1 ; ///< + UINT32 IncoherentClkSbiEn:1 ; ///< + UINT32 EiDetSbiEn:1 ; ///< + UINT32 Reserved_13_9:5 ; ///< + UINT32 MargPktSbiEn:1 ; ///< + UINT32 PllCmpPktSbiEn:1 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_000B_STRUCT; + +// **** D0F0xE4_PHY_2000 Register Definition **** +// Address +#define D0F0xE4_PHY_2000_ADDRESS 0x2000 + +// Type +#define D0F0xE4_PHY_2000_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_2000_PllPowerDownEn_OFFSET 0 +#define D0F0xE4_PHY_2000_PllPowerDownEn_WIDTH 3 +#define D0F0xE4_PHY_2000_PllPowerDownEn_MASK 0x7 +#define D0F0xE4_PHY_2000_PllAutoPwrDownDis_OFFSET 3 +#define D0F0xE4_PHY_2000_PllAutoPwrDownDis_WIDTH 1 +#define D0F0xE4_PHY_2000_PllAutoPwrDownDis_MASK 0x8 +#define D0F0xE4_PHY_2000_Reserved_31_4_OFFSET 4 +#define D0F0xE4_PHY_2000_Reserved_31_4_WIDTH 28 +#define D0F0xE4_PHY_2000_Reserved_31_4_MASK 0xfffffff0 + +/// D0F0xE4_PHY_2000 +typedef union { + struct { ///< + UINT32 PllPowerDownEn:3 ; ///< + UINT32 PllAutoPwrDownDis:1 ; ///< + UINT32 Reserved_31_4:28; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_2000_STRUCT; + + +// **** D0F0xE4_PHY_2005 Register Definition **** +// Address +#define D0F0xE4_PHY_2005_ADDRESS 0x2005 + +// Type +#define D0F0xE4_PHY_2005_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_2005_PllClkFreq_OFFSET 0 +#define D0F0xE4_PHY_2005_PllClkFreq_WIDTH 4 +#define D0F0xE4_PHY_2005_PllClkFreq_MASK 0xf +#define D0F0xE4_PHY_2005_Reserved_8_4_OFFSET 4 +#define D0F0xE4_PHY_2005_Reserved_8_4_WIDTH 5 +#define D0F0xE4_PHY_2005_Reserved_8_4_MASK 0x1f0 +#define D0F0xE4_PHY_2005_PllClkFreqExt_OFFSET 9 +#define D0F0xE4_PHY_2005_PllClkFreqExt_WIDTH 2 +#define D0F0xE4_PHY_2005_PllClkFreqExt_MASK 0x600 +#define D0F0xE4_PHY_2005_Reserved_12_11_OFFSET 11 +#define D0F0xE4_PHY_2005_Reserved_12_11_WIDTH 2 +#define D0F0xE4_PHY_2005_Reserved_12_11_MASK 0x1800 +#define D0F0xE4_PHY_2005_PllMode_OFFSET 13 +#define D0F0xE4_PHY_2005_PllMode_WIDTH 2 +#define D0F0xE4_PHY_2005_PllMode_MASK 0x6000 +#define D0F0xE4_PHY_2005_Reserved_31_15_OFFSET 15 +#define D0F0xE4_PHY_2005_Reserved_31_15_WIDTH 17 +#define D0F0xE4_PHY_2005_Reserved_31_15_MASK 0xffff8000 + +/// D0F0xE4_PHY_2005 +typedef union { + struct { ///< + UINT32 PllClkFreq:4 ; ///< + UINT32 Reserved_8_4:5 ; ///< + UINT32 PllClkFreqExt:2 ; ///< + UINT32 Reserved_12_11:2 ; ///< + UINT32 PllMode:2 ; ///< + UINT32 Reserved_31_15:17; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_2005_STRUCT; + +// **** D0F0xE4_PHY_2008 Register Definition **** +// Address +#define D0F0xE4_PHY_2008_ADDRESS 0x2008 + +// Type +#define D0F0xE4_PHY_2008_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_2008_PllControlUpdate_OFFSET 0 +#define D0F0xE4_PHY_2008_PllControlUpdate_WIDTH 1 +#define D0F0xE4_PHY_2008_PllControlUpdate_MASK 0x1 +#define D0F0xE4_PHY_2008_Reserved_22_1_OFFSET 1 +#define D0F0xE4_PHY_2008_Reserved_22_1_WIDTH 22 +#define D0F0xE4_PHY_2008_Reserved_22_1_MASK 0x7ffffe +#define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__OFFSET 23 +#define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__WIDTH 3 +#define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__MASK 0x3800000 +#define D0F0xE4_PHY_2008_Reserved_28_26_OFFSET 26 +#define D0F0xE4_PHY_2008_Reserved_28_26_WIDTH 3 +#define D0F0xE4_PHY_2008_Reserved_28_26_MASK 0x1c000000 +#define D0F0xE4_PHY_2008_VdDetectEn_OFFSET 29 +#define D0F0xE4_PHY_2008_VdDetectEn_WIDTH 1 +#define D0F0xE4_PHY_2008_VdDetectEn_MASK 0x20000000 +#define D0F0xE4_PHY_2008_Reserved_31_30_OFFSET 30 +#define D0F0xE4_PHY_2008_Reserved_31_30_WIDTH 2 +#define D0F0xE4_PHY_2008_Reserved_31_30_MASK 0xc0000000 + +/// D0F0xE4_PHY_2008 +typedef union { + struct { ///< + UINT32 PllControlUpdate:1 ; ///< + UINT32 Reserved_22_1:22; ///< + UINT32 MeasCycCntVal_2_0_:3 ; ///< + UINT32 Reserved_28_26:3 ; ///< + UINT32 VdDetectEn:1 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_2008_STRUCT; + +// **** D0F0xE4_PHY_4001 Register Definition **** +// Address +#define D0F0xE4_PHY_4001_ADDRESS 0x4001 + +// Type +#define D0F0xE4_PHY_4001_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_4001_Reserved_14_0_OFFSET 0 +#define D0F0xE4_PHY_4001_Reserved_14_0_WIDTH 15 +#define D0F0xE4_PHY_4001_Reserved_14_0_MASK 0x7fff +#define D0F0xE4_PHY_4001_ForceDccRecalc_OFFSET 15 +#define D0F0xE4_PHY_4001_ForceDccRecalc_WIDTH 1 +#define D0F0xE4_PHY_4001_ForceDccRecalc_MASK 0x8000 +#define D0F0xE4_PHY_4001_Reserved_31_16_OFFSET 16 +#define D0F0xE4_PHY_4001_Reserved_31_16_WIDTH 16 +#define D0F0xE4_PHY_4001_Reserved_31_16_MASK 0xffff0000 + +/// D0F0xE4_PHY_4001 +typedef union { + struct { ///< + UINT32 Reserved_14_0:15; ///< + UINT32 ForceDccRecalc:1 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_4001_STRUCT; + +// **** D0F0xE4_PHY_4002 Register Definition **** +// Address +#define D0F0xE4_PHY_4002_ADDRESS 0x4002 + +// Type +#define D0F0xE4_PHY_4002_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_4002_Reserved_2_0_OFFSET 0 +#define D0F0xE4_PHY_4002_Reserved_2_0_WIDTH 3 +#define D0F0xE4_PHY_4002_Reserved_2_0_MASK 0x7 +#define D0F0xE4_PHY_4002_SamClkPiOffsetSign_OFFSET 3 +#define D0F0xE4_PHY_4002_SamClkPiOffsetSign_WIDTH 1 +#define D0F0xE4_PHY_4002_SamClkPiOffsetSign_MASK 0x8 +#define D0F0xE4_PHY_4002_SamClkPiOffset_OFFSET 4 +#define D0F0xE4_PHY_4002_SamClkPiOffset_WIDTH 3 +#define D0F0xE4_PHY_4002_SamClkPiOffset_MASK 0x70 +#define D0F0xE4_PHY_4002_SamClkPiOffsetEn_OFFSET 7 +#define D0F0xE4_PHY_4002_SamClkPiOffsetEn_WIDTH 1 +#define D0F0xE4_PHY_4002_SamClkPiOffsetEn_MASK 0x80 +#define D0F0xE4_PHY_4002_Reserved_13_8_OFFSET 8 +#define D0F0xE4_PHY_4002_Reserved_13_8_WIDTH 6 +#define D0F0xE4_PHY_4002_Reserved_13_8_MASK 0x3f00 +#define D0F0xE4_PHY_4002_LfcMin_OFFSET 14 +#define D0F0xE4_PHY_4002_LfcMin_WIDTH 8 +#define D0F0xE4_PHY_4002_LfcMin_MASK 0x3fc000 +#define D0F0xE4_PHY_4002_LfcMax_OFFSET 22 +#define D0F0xE4_PHY_4002_LfcMax_WIDTH 8 +#define D0F0xE4_PHY_4002_LfcMax_MASK 0x3fc00000 +#define D0F0xE4_PHY_4002_Reserved_31_30_OFFSET 30 +#define D0F0xE4_PHY_4002_Reserved_31_30_WIDTH 2 +#define D0F0xE4_PHY_4002_Reserved_31_30_MASK 0xc0000000 + +/// D0F0xE4_PHY_4002 +typedef union { + struct { ///< + UINT32 Reserved_2_0:3 ; ///< + UINT32 SamClkPiOffsetSign:1 ; ///< + UINT32 SamClkPiOffset:3 ; ///< + UINT32 SamClkPiOffsetEn:1 ; ///< + UINT32 Reserved_13_8:6 ; ///< + UINT32 LfcMin:8 ; ///< + UINT32 LfcMax:8 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_4002_STRUCT; + +// **** D0F0xE4_PHY_4005 Register Definition **** +// Address +#define D0F0xE4_PHY_4005_ADDRESS 0x4005 + +// Type +#define D0F0xE4_PHY_4005_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_4005_Reserved_8_0_OFFSET 0 +#define D0F0xE4_PHY_4005_Reserved_8_0_WIDTH 9 +#define D0F0xE4_PHY_4005_Reserved_8_0_MASK 0x1ff +#define D0F0xE4_PHY_4005_JitterInjHold_OFFSET 9 +#define D0F0xE4_PHY_4005_JitterInjHold_WIDTH 1 +#define D0F0xE4_PHY_4005_JitterInjHold_MASK 0x200 +#define D0F0xE4_PHY_4005_JitterInjOffCnt_OFFSET 10 +#define D0F0xE4_PHY_4005_JitterInjOffCnt_WIDTH 6 +#define D0F0xE4_PHY_4005_JitterInjOffCnt_MASK 0xfc00 +#define D0F0xE4_PHY_4005_Reserved_22_16_OFFSET 16 +#define D0F0xE4_PHY_4005_Reserved_22_16_WIDTH 7 +#define D0F0xE4_PHY_4005_Reserved_22_16_MASK 0x7f0000 +#define D0F0xE4_PHY_4005_JitterInjOnCnt_OFFSET 23 +#define D0F0xE4_PHY_4005_JitterInjOnCnt_WIDTH 6 +#define D0F0xE4_PHY_4005_JitterInjOnCnt_MASK 0x1f800000 +#define D0F0xE4_PHY_4005_JitterInjDir_OFFSET 29 +#define D0F0xE4_PHY_4005_JitterInjDir_WIDTH 1 +#define D0F0xE4_PHY_4005_JitterInjDir_MASK 0x20000000 +#define D0F0xE4_PHY_4005_JitterInjEn_OFFSET 30 +#define D0F0xE4_PHY_4005_JitterInjEn_WIDTH 1 +#define D0F0xE4_PHY_4005_JitterInjEn_MASK 0x40000000 +#define D0F0xE4_PHY_4005_Reserved_31_31_OFFSET 31 +#define D0F0xE4_PHY_4005_Reserved_31_31_WIDTH 1 +#define D0F0xE4_PHY_4005_Reserved_31_31_MASK 0x80000000 + +/// D0F0xE4_PHY_4005 +typedef union { + struct { ///< + UINT32 Reserved_8_0:9 ; ///< + UINT32 JitterInjHold:1 ; ///< + UINT32 JitterInjOffCnt:6 ; ///< + UINT32 Reserved_22_16:7 ; ///< + UINT32 JitterInjOnCnt:6 ; ///< + UINT32 JitterInjDir:1 ; ///< + UINT32 JitterInjEn:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_4005_STRUCT; + +// **** D0F0xE4_PHY_4006 Register Definition **** +// Address +#define D0F0xE4_PHY_4006_ADDRESS 0x4006 + +// Type +#define D0F0xE4_PHY_4006_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_4006_Reserved_4_0_OFFSET 0 +#define D0F0xE4_PHY_4006_Reserved_4_0_WIDTH 5 +#define D0F0xE4_PHY_4006_Reserved_4_0_MASK 0x1f +#define D0F0xE4_PHY_4006_DfeVoltage_OFFSET 5 +#define D0F0xE4_PHY_4006_DfeVoltage_WIDTH 2 +#define D0F0xE4_PHY_4006_DfeVoltage_MASK 0x60 +#define D0F0xE4_PHY_4006_DfeEn_OFFSET 7 +#define D0F0xE4_PHY_4006_DfeEn_WIDTH 1 +#define D0F0xE4_PHY_4006_DfeEn_MASK 0x80 +#define D0F0xE4_PHY_4006_Reserved_31_8_OFFSET 8 +#define D0F0xE4_PHY_4006_Reserved_31_8_WIDTH 24 +#define D0F0xE4_PHY_4006_Reserved_31_8_MASK 0xffffff00 + +/// D0F0xE4_PHY_4006 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 DfeVoltage:2 ; ///< + UINT32 DfeEn:1 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_4006_STRUCT; + +// **** D0F0xE4_PHY_400A Register Definition **** +// Address +#define D0F0xE4_PHY_400A_ADDRESS 0x400a + +// Type +#define D0F0xE4_PHY_400A_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_400A_EnCoreLoopFirst_OFFSET 0 +#define D0F0xE4_PHY_400A_EnCoreLoopFirst_WIDTH 1 +#define D0F0xE4_PHY_400A_EnCoreLoopFirst_MASK 0x1 +#define D0F0xE4_PHY_400A_Reserved_3_1_OFFSET 1 +#define D0F0xE4_PHY_400A_Reserved_3_1_WIDTH 3 +#define D0F0xE4_PHY_400A_Reserved_3_1_MASK 0xe +#define D0F0xE4_PHY_400A_LockDetOnLs2Exit_OFFSET 4 +#define D0F0xE4_PHY_400A_LockDetOnLs2Exit_WIDTH 1 +#define D0F0xE4_PHY_400A_LockDetOnLs2Exit_MASK 0x10 +#define D0F0xE4_PHY_400A_Reserved_6_5_OFFSET 5 +#define D0F0xE4_PHY_400A_Reserved_6_5_WIDTH 2 +#define D0F0xE4_PHY_400A_Reserved_6_5_MASK 0x60 +#define D0F0xE4_PHY_400A_BiasDisInLs2_OFFSET 7 +#define D0F0xE4_PHY_400A_BiasDisInLs2_WIDTH 1 +#define D0F0xE4_PHY_400A_BiasDisInLs2_MASK 0x80 +#define D0F0xE4_PHY_400A_Reserved_12_8_OFFSET 8 +#define D0F0xE4_PHY_400A_Reserved_12_8_WIDTH 5 +#define D0F0xE4_PHY_400A_Reserved_12_8_MASK 0x1f00 +#define D0F0xE4_PHY_400A_AnalogWaitTime_OFFSET 13 +#define D0F0xE4_PHY_400A_AnalogWaitTime_WIDTH 2 +#define D0F0xE4_PHY_400A_AnalogWaitTime_MASK 0x6000 +#define D0F0xE4_PHY_400A_Reserved_16_15_OFFSET 15 +#define D0F0xE4_PHY_400A_Reserved_16_15_WIDTH 2 +#define D0F0xE4_PHY_400A_Reserved_16_15_MASK 0x18000 +#define D0F0xE4_PHY_400A_DllLockFastModeEn_OFFSET 17 +#define D0F0xE4_PHY_400A_DllLockFastModeEn_WIDTH 1 +#define D0F0xE4_PHY_400A_DllLockFastModeEn_MASK 0x20000 +#define D0F0xE4_PHY_400A_Reserved_28_18_OFFSET 18 +#define D0F0xE4_PHY_400A_Reserved_28_18_WIDTH 11 +#define D0F0xE4_PHY_400A_Reserved_28_18_MASK 0x1ffc0000 +#define D0F0xE4_PHY_400A_Ls2ExitTime_OFFSET 29 +#define D0F0xE4_PHY_400A_Ls2ExitTime_WIDTH 3 +#define D0F0xE4_PHY_400A_Ls2ExitTime_MASK 0xe0000000 + +/// D0F0xE4_PHY_400A +typedef union { + struct { ///< + UINT32 EnCoreLoopFirst:1 ; ///< + UINT32 Reserved_3_1:3 ; ///< + UINT32 LockDetOnLs2Exit:1 ; ///< + UINT32 Reserved_6_5:2 ; ///< + UINT32 BiasDisInLs2:1 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 AnalogWaitTime:2 ; ///< + UINT32 Reserved_16_15:2 ; ///< + UINT32 DllLockFastModeEn:1 ; ///< + UINT32 Reserved_28_18:11; ///< + UINT32 Ls2ExitTime:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_400A_STRUCT; + +// **** D0F0xE4_PHY_6005 Register Definition **** +// Address +#define D0F0xE4_PHY_6005_ADDRESS 0x6005 + +// Type +#define D0F0xE4_PHY_6005_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_6005_Reserved_28_0_OFFSET 0 +#define D0F0xE4_PHY_6005_Reserved_28_0_WIDTH 29 +#define D0F0xE4_PHY_6005_Reserved_28_0_MASK 0x1fffffff +#define D0F0xE4_PHY_6005_IsOwnMstr_OFFSET 29 +#define D0F0xE4_PHY_6005_IsOwnMstr_WIDTH 1 +#define D0F0xE4_PHY_6005_IsOwnMstr_MASK 0x20000000 +#define D0F0xE4_PHY_6005_Reserved_30_30_OFFSET 30 +#define D0F0xE4_PHY_6005_Reserved_30_30_WIDTH 1 +#define D0F0xE4_PHY_6005_Reserved_30_30_MASK 0x40000000 +#define D0F0xE4_PHY_6005_GangedModeEn_OFFSET 31 +#define D0F0xE4_PHY_6005_GangedModeEn_WIDTH 1 +#define D0F0xE4_PHY_6005_GangedModeEn_MASK 0x80000000 + +/// D0F0xE4_PHY_6005 +typedef union { + struct { ///< + UINT32 Reserved_28_0:29; ///< + UINT32 IsOwnMstr:1 ; ///< + UINT32 Reserved_30_30:1 ; ///< + UINT32 GangedModeEn:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_6005_STRUCT; + +// **** D18F2x09C_x0000_0000 Register Definition **** +// Address +#define D18F2x09C_x0000_0000_ADDRESS 0x0 + +// Type +#define D18F2x09C_x0000_0000_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0000_0000_CkeDrvStren_OFFSET 0 +#define D18F2x09C_x0000_0000_CkeDrvStren_WIDTH 3 +#define D18F2x09C_x0000_0000_CkeDrvStren_MASK 0x7 +#define D18F2x09C_x0000_0000_Reserved_3_3_OFFSET 3 +#define D18F2x09C_x0000_0000_Reserved_3_3_WIDTH 1 +#define D18F2x09C_x0000_0000_Reserved_3_3_MASK 0x8 +#define D18F2x09C_x0000_0000_CsOdtDrvStren_OFFSET 4 +#define D18F2x09C_x0000_0000_CsOdtDrvStren_WIDTH 3 +#define D18F2x09C_x0000_0000_CsOdtDrvStren_MASK 0x70 +#define D18F2x09C_x0000_0000_Reserved_7_7_OFFSET 7 +#define D18F2x09C_x0000_0000_Reserved_7_7_WIDTH 1 +#define D18F2x09C_x0000_0000_Reserved_7_7_MASK 0x80 +#define D18F2x09C_x0000_0000_AddrCmdDrvStren_OFFSET 8 +#define D18F2x09C_x0000_0000_AddrCmdDrvStren_WIDTH 3 +#define D18F2x09C_x0000_0000_AddrCmdDrvStren_MASK 0x700 +#define D18F2x09C_x0000_0000_Reserved_11_11_OFFSET 11 +#define D18F2x09C_x0000_0000_Reserved_11_11_WIDTH 1 +#define D18F2x09C_x0000_0000_Reserved_11_11_MASK 0x800 +#define D18F2x09C_x0000_0000_ClkDrvStren_OFFSET 12 +#define D18F2x09C_x0000_0000_ClkDrvStren_WIDTH 3 +#define D18F2x09C_x0000_0000_ClkDrvStren_MASK 0x7000 +#define D18F2x09C_x0000_0000_Reserved_15_15_OFFSET 15 +#define D18F2x09C_x0000_0000_Reserved_15_15_WIDTH 1 +#define D18F2x09C_x0000_0000_Reserved_15_15_MASK 0x8000 +#define D18F2x09C_x0000_0000_DataDrvStren_OFFSET 16 +#define D18F2x09C_x0000_0000_DataDrvStren_WIDTH 3 +#define D18F2x09C_x0000_0000_DataDrvStren_MASK 0x70000 +#define D18F2x09C_x0000_0000_Reserved_19_19_OFFSET 19 +#define D18F2x09C_x0000_0000_Reserved_19_19_WIDTH 1 +#define D18F2x09C_x0000_0000_Reserved_19_19_MASK 0x80000 +#define D18F2x09C_x0000_0000_DqsDrvStren_OFFSET 20 +#define D18F2x09C_x0000_0000_DqsDrvStren_WIDTH 3 +#define D18F2x09C_x0000_0000_DqsDrvStren_MASK 0x700000 +#define D18F2x09C_x0000_0000_Reserved_27_23_OFFSET 23 +#define D18F2x09C_x0000_0000_Reserved_27_23_WIDTH 5 +#define D18F2x09C_x0000_0000_Reserved_27_23_MASK 0xf800000 +#define D18F2x09C_x0000_0000_ProcOdt_OFFSET 28 +#define D18F2x09C_x0000_0000_ProcOdt_WIDTH 3 +#define D18F2x09C_x0000_0000_ProcOdt_MASK 0x70000000 +#define D18F2x09C_x0000_0000_Reserved_31_31_OFFSET 31 +#define D18F2x09C_x0000_0000_Reserved_31_31_WIDTH 1 +#define D18F2x09C_x0000_0000_Reserved_31_31_MASK 0x80000000 + +/// D18F2x09C_x0000_0000 +typedef union { + struct { ///< + UINT32 CkeDrvStren:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 CsOdtDrvStren:3 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 AddrCmdDrvStren:3 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 ClkDrvStren:3 ; ///< + UINT32 Reserved_15_15:1 ; ///< + UINT32 DataDrvStren:3 ; ///< + UINT32 Reserved_19_19:1 ; ///< + UINT32 DqsDrvStren:3 ; ///< + UINT32 Reserved_27_23:5 ; ///< + UINT32 ProcOdt:3 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0000_0000_STRUCT; + +// **** D18F2x09C_x0000_0001 Register Definition **** +// Address +#define D18F2x09C_x0000_0001_ADDRESS 0x1 + +// Type +#define D18F2x09C_x0000_0001_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0000_0001_WrDatFineDly_Byte0_OFFSET 0 +#define D18F2x09C_x0000_0001_WrDatFineDly_Byte0_WIDTH 5 +#define D18F2x09C_x0000_0001_WrDatFineDly_Byte0_MASK 0x1f +#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte0_OFFSET 5 +#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte0_WIDTH 3 +#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte0_MASK 0xe0 +#define D18F2x09C_x0000_0001_WrDatFineDly_Byte1_OFFSET 8 +#define D18F2x09C_x0000_0001_WrDatFineDly_Byte1_WIDTH 5 +#define D18F2x09C_x0000_0001_WrDatFineDly_Byte1_MASK 0x1f00 +#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte1_OFFSET 13 +#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte1_WIDTH 3 +#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte1_MASK 0xe000 +#define D18F2x09C_x0000_0001_WrDatFineDly_Byte2_OFFSET 16 +#define D18F2x09C_x0000_0001_WrDatFineDly_Byte2_WIDTH 5 +#define D18F2x09C_x0000_0001_WrDatFineDly_Byte2_MASK 0x1f0000 +#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte2_OFFSET 21 +#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte2_WIDTH 3 +#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte2_MASK 0xe00000 +#define D18F2x09C_x0000_0001_WrDatFineDly_Byte3_OFFSET 24 +#define D18F2x09C_x0000_0001_WrDatFineDly_Byte3_WIDTH 5 +#define D18F2x09C_x0000_0001_WrDatFineDly_Byte3_MASK 0x1f000000 +#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte3_OFFSET 29 +#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte3_WIDTH 3 +#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte3_MASK 0xe0000000 + +/// D18F2x09C_x0000_0001 +typedef union { + struct { ///< + UINT32 WrDatFineDly_Byte0:5 ; ///< + UINT32 WrDatGrossDly_Byte0:3 ; ///< + UINT32 WrDatFineDly_Byte1:5 ; ///< + UINT32 WrDatGrossDly_Byte1:3 ; ///< + UINT32 WrDatFineDly_Byte2:5 ; ///< + UINT32 WrDatGrossDly_Byte2:3 ; ///< + UINT32 WrDatFineDly_Byte3:5 ; ///< + UINT32 WrDatGrossDly_Byte3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0000_0001_STRUCT; + +// **** D18F2x09C_x0000_0002 Register Definition **** +// Address +#define D18F2x09C_x0000_0002_ADDRESS 0x2 + +// Type +#define D18F2x09C_x0000_0002_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0000_0002_WrDatFineDly_Byte4_OFFSET 0 +#define D18F2x09C_x0000_0002_WrDatFineDly_Byte4_WIDTH 5 +#define D18F2x09C_x0000_0002_WrDatFineDly_Byte4_MASK 0x1f +#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte4_OFFSET 5 +#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte4_WIDTH 3 +#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte4_MASK 0xe0 +#define D18F2x09C_x0000_0002_WrDatFineDly_Byte5_OFFSET 8 +#define D18F2x09C_x0000_0002_WrDatFineDly_Byte5_WIDTH 5 +#define D18F2x09C_x0000_0002_WrDatFineDly_Byte5_MASK 0x1f00 +#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte5_OFFSET 13 +#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte5_WIDTH 3 +#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte5_MASK 0xe000 +#define D18F2x09C_x0000_0002_WrDatFineDly_Byte6_OFFSET 16 +#define D18F2x09C_x0000_0002_WrDatFineDly_Byte6_WIDTH 5 +#define D18F2x09C_x0000_0002_WrDatFineDly_Byte6_MASK 0x1f0000 +#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte6_OFFSET 21 +#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte6_WIDTH 3 +#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte6_MASK 0xe00000 +#define D18F2x09C_x0000_0002_WrDatFineDly_Byte7_OFFSET 24 +#define D18F2x09C_x0000_0002_WrDatFineDly_Byte7_WIDTH 5 +#define D18F2x09C_x0000_0002_WrDatFineDly_Byte7_MASK 0x1f000000 +#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte7_OFFSET 29 +#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte7_WIDTH 3 +#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte7_MASK 0xe0000000 + +/// D18F2x09C_x0000_0002 +typedef union { + struct { ///< + UINT32 WrDatFineDly_Byte4:5 ; ///< + UINT32 WrDatGrossDly_Byte4:3 ; ///< + UINT32 WrDatFineDly_Byte5:5 ; ///< + UINT32 WrDatGrossDly_Byte5:3 ; ///< + UINT32 WrDatFineDly_Byte6:5 ; ///< + UINT32 WrDatGrossDly_Byte6:3 ; ///< + UINT32 WrDatFineDly_Byte7:5 ; ///< + UINT32 WrDatGrossDly_Byte7:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0000_0002_STRUCT; + +// **** D18F2x09C_x0000_0004 Register Definition **** +// Address +#define D18F2x09C_x0000_0004_ADDRESS 0x4 + +// Type +#define D18F2x09C_x0000_0004_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0000_0004_CkeFineDelay_OFFSET 0 +#define D18F2x09C_x0000_0004_CkeFineDelay_WIDTH 5 +#define D18F2x09C_x0000_0004_CkeFineDelay_MASK 0x1f +#define D18F2x09C_x0000_0004_CkeSetup_OFFSET 5 +#define D18F2x09C_x0000_0004_CkeSetup_WIDTH 1 +#define D18F2x09C_x0000_0004_CkeSetup_MASK 0x20 +#define D18F2x09C_x0000_0004_Reserved_7_6_OFFSET 6 +#define D18F2x09C_x0000_0004_Reserved_7_6_WIDTH 2 +#define D18F2x09C_x0000_0004_Reserved_7_6_MASK 0xc0 +#define D18F2x09C_x0000_0004_CsOdtFineDelay_OFFSET 8 +#define D18F2x09C_x0000_0004_CsOdtFineDelay_WIDTH 5 +#define D18F2x09C_x0000_0004_CsOdtFineDelay_MASK 0x1f00 +#define D18F2x09C_x0000_0004_CsOdtSetup_OFFSET 13 +#define D18F2x09C_x0000_0004_CsOdtSetup_WIDTH 1 +#define D18F2x09C_x0000_0004_CsOdtSetup_MASK 0x2000 +#define D18F2x09C_x0000_0004_Reserved_15_14_OFFSET 14 +#define D18F2x09C_x0000_0004_Reserved_15_14_WIDTH 2 +#define D18F2x09C_x0000_0004_Reserved_15_14_MASK 0xc000 +#define D18F2x09C_x0000_0004_AddrCmdFineDelay_OFFSET 16 +#define D18F2x09C_x0000_0004_AddrCmdFineDelay_WIDTH 5 +#define D18F2x09C_x0000_0004_AddrCmdFineDelay_MASK 0x1f0000 +#define D18F2x09C_x0000_0004_AddrCmdSetup_OFFSET 21 +#define D18F2x09C_x0000_0004_AddrCmdSetup_WIDTH 1 +#define D18F2x09C_x0000_0004_AddrCmdSetup_MASK 0x200000 +#define D18F2x09C_x0000_0004_Reserved_31_22_OFFSET 22 +#define D18F2x09C_x0000_0004_Reserved_31_22_WIDTH 10 +#define D18F2x09C_x0000_0004_Reserved_31_22_MASK 0xffc00000 + +/// D18F2x09C_x0000_0004 +typedef union { + struct { ///< + UINT32 CkeFineDelay:5 ; ///< + UINT32 CkeSetup:1 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 CsOdtFineDelay:5 ; ///< + UINT32 CsOdtSetup:1 ; ///< + UINT32 Reserved_15_14:2 ; ///< + UINT32 AddrCmdFineDelay:5 ; ///< + UINT32 AddrCmdSetup:1 ; ///< + UINT32 Reserved_31_22:10; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0000_0004_STRUCT; + +// **** D18F2x09C_x0000_0005 Register Definition **** +// Address +#define D18F2x09C_x0000_0005_ADDRESS 0x5 + +// Type +#define D18F2x09C_x0000_0005_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0000_0005_Reserved_0_0_OFFSET 0 +#define D18F2x09C_x0000_0005_Reserved_0_0_WIDTH 1 +#define D18F2x09C_x0000_0005_Reserved_0_0_MASK 0x1 +#define D18F2x09C_x0000_0005_RdDqsTime_Byte0_OFFSET 1 +#define D18F2x09C_x0000_0005_RdDqsTime_Byte0_WIDTH 5 +#define D18F2x09C_x0000_0005_RdDqsTime_Byte0_MASK 0x3e +#define D18F2x09C_x0000_0005_Reserved_8_6_OFFSET 6 +#define D18F2x09C_x0000_0005_Reserved_8_6_WIDTH 3 +#define D18F2x09C_x0000_0005_Reserved_8_6_MASK 0x1c0 +#define D18F2x09C_x0000_0005_RdDqsTime_Byte1_OFFSET 9 +#define D18F2x09C_x0000_0005_RdDqsTime_Byte1_WIDTH 5 +#define D18F2x09C_x0000_0005_RdDqsTime_Byte1_MASK 0x3e00 +#define D18F2x09C_x0000_0005_Reserved_16_14_OFFSET 14 +#define D18F2x09C_x0000_0005_Reserved_16_14_WIDTH 3 +#define D18F2x09C_x0000_0005_Reserved_16_14_MASK 0x1c000 +#define D18F2x09C_x0000_0005_RdDqsTime_Byte2_OFFSET 17 +#define D18F2x09C_x0000_0005_RdDqsTime_Byte2_WIDTH 5 +#define D18F2x09C_x0000_0005_RdDqsTime_Byte2_MASK 0x3e0000 +#define D18F2x09C_x0000_0005_Reserved_24_22_OFFSET 22 +#define D18F2x09C_x0000_0005_Reserved_24_22_WIDTH 3 +#define D18F2x09C_x0000_0005_Reserved_24_22_MASK 0x1c00000 +#define D18F2x09C_x0000_0005_RdDqsTime_Byte3_OFFSET 25 +#define D18F2x09C_x0000_0005_RdDqsTime_Byte3_WIDTH 5 +#define D18F2x09C_x0000_0005_RdDqsTime_Byte3_MASK 0x3e000000 +#define D18F2x09C_x0000_0005_Reserved_31_30_OFFSET 30 +#define D18F2x09C_x0000_0005_Reserved_31_30_WIDTH 2 +#define D18F2x09C_x0000_0005_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x09C_x0000_0005 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime_Byte0:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime_Byte1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime_Byte2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime_Byte3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0000_0005_STRUCT; + +// **** D18F2x09C_x0000_0006 Register Definition **** +// Address +#define D18F2x09C_x0000_0006_ADDRESS 0x6 + +// Type +#define D18F2x09C_x0000_0006_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0000_0006_Reserved_0_0_OFFSET 0 +#define D18F2x09C_x0000_0006_Reserved_0_0_WIDTH 1 +#define D18F2x09C_x0000_0006_Reserved_0_0_MASK 0x1 +#define D18F2x09C_x0000_0006_RdDqsTime_Byte4_OFFSET 1 +#define D18F2x09C_x0000_0006_RdDqsTime_Byte4_WIDTH 5 +#define D18F2x09C_x0000_0006_RdDqsTime_Byte4_MASK 0x3e +#define D18F2x09C_x0000_0006_Reserved_8_6_OFFSET 6 +#define D18F2x09C_x0000_0006_Reserved_8_6_WIDTH 3 +#define D18F2x09C_x0000_0006_Reserved_8_6_MASK 0x1c0 +#define D18F2x09C_x0000_0006_RdDqsTime_Byte5_OFFSET 9 +#define D18F2x09C_x0000_0006_RdDqsTime_Byte5_WIDTH 5 +#define D18F2x09C_x0000_0006_RdDqsTime_Byte5_MASK 0x3e00 +#define D18F2x09C_x0000_0006_Reserved_16_14_OFFSET 14 +#define D18F2x09C_x0000_0006_Reserved_16_14_WIDTH 3 +#define D18F2x09C_x0000_0006_Reserved_16_14_MASK 0x1c000 +#define D18F2x09C_x0000_0006_RdDqsTime_Byte6_OFFSET 17 +#define D18F2x09C_x0000_0006_RdDqsTime_Byte6_WIDTH 5 +#define D18F2x09C_x0000_0006_RdDqsTime_Byte6_MASK 0x3e0000 +#define D18F2x09C_x0000_0006_Reserved_24_22_OFFSET 22 +#define D18F2x09C_x0000_0006_Reserved_24_22_WIDTH 3 +#define D18F2x09C_x0000_0006_Reserved_24_22_MASK 0x1c00000 +#define D18F2x09C_x0000_0006_RdDqsTime_Byte7_OFFSET 25 +#define D18F2x09C_x0000_0006_RdDqsTime_Byte7_WIDTH 5 +#define D18F2x09C_x0000_0006_RdDqsTime_Byte7_MASK 0x3e000000 +#define D18F2x09C_x0000_0006_Reserved_31_30_OFFSET 30 +#define D18F2x09C_x0000_0006_Reserved_31_30_WIDTH 2 +#define D18F2x09C_x0000_0006_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x09C_x0000_0006 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime_Byte4:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime_Byte5:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime_Byte6:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime_Byte7:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0000_0006_STRUCT; + + + +// **** D18F2x09C_x0000_000D Register Definition **** +// Address +#define D18F2x09C_x0000_000D_ADDRESS 0xd + +// Type +#define D18F2x09C_x0000_000D_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0000_000D_TxMaxDurDllNoLock_OFFSET 0 +#define D18F2x09C_x0000_000D_TxMaxDurDllNoLock_WIDTH 4 +#define D18F2x09C_x0000_000D_TxMaxDurDllNoLock_MASK 0xf +#define D18F2x09C_x0000_000D_TxCPUpdPeriod_OFFSET 4 +#define D18F2x09C_x0000_000D_TxCPUpdPeriod_WIDTH 3 +#define D18F2x09C_x0000_000D_TxCPUpdPeriod_MASK 0x70 +#define D18F2x09C_x0000_000D_Reserved_7_7_OFFSET 7 +#define D18F2x09C_x0000_000D_Reserved_7_7_WIDTH 1 +#define D18F2x09C_x0000_000D_Reserved_7_7_MASK 0x80 +#define D18F2x09C_x0000_000D_TxDLLWakeupTime_OFFSET 8 +#define D18F2x09C_x0000_000D_TxDLLWakeupTime_WIDTH 2 +#define D18F2x09C_x0000_000D_TxDLLWakeupTime_MASK 0x300 +#define D18F2x09C_x0000_000D_Reserved_15_10_OFFSET 10 +#define D18F2x09C_x0000_000D_Reserved_15_10_WIDTH 6 +#define D18F2x09C_x0000_000D_Reserved_15_10_MASK 0xfc00 +#define D18F2x09C_x0000_000D_RxMaxDurDllNoLock_OFFSET 16 +#define D18F2x09C_x0000_000D_RxMaxDurDllNoLock_WIDTH 4 +#define D18F2x09C_x0000_000D_RxMaxDurDllNoLock_MASK 0xf0000 +#define D18F2x09C_x0000_000D_RxCPUpdPeriod_OFFSET 20 +#define D18F2x09C_x0000_000D_RxCPUpdPeriod_WIDTH 3 +#define D18F2x09C_x0000_000D_RxCPUpdPeriod_MASK 0x700000 +#define D18F2x09C_x0000_000D_Reserved_23_23_OFFSET 23 +#define D18F2x09C_x0000_000D_Reserved_23_23_WIDTH 1 +#define D18F2x09C_x0000_000D_Reserved_23_23_MASK 0x800000 +#define D18F2x09C_x0000_000D_RxDLLWakeupTime_OFFSET 24 +#define D18F2x09C_x0000_000D_RxDLLWakeupTime_WIDTH 2 +#define D18F2x09C_x0000_000D_RxDLLWakeupTime_MASK 0x3000000 +#define D18F2x09C_x0000_000D_Reserved_31_26_OFFSET 26 +#define D18F2x09C_x0000_000D_Reserved_31_26_WIDTH 6 +#define D18F2x09C_x0000_000D_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x09C_x0000_000D +typedef union { + struct { ///< + UINT32 TxMaxDurDllNoLock:4 ; ///< + UINT32 TxCPUpdPeriod:3 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 TxDLLWakeupTime:2 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 RxMaxDurDllNoLock:4 ; ///< + UINT32 RxCPUpdPeriod:3 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 RxDLLWakeupTime:2 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0000_000D_STRUCT; + + +// **** D18F2x09C_x0000_0030 Register Definition **** +// Address +#define D18F2x09C_x0000_0030_ADDRESS 0x30 + +// Type +#define D18F2x09C_x0000_0030_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte0_OFFSET 0 +#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte0_WIDTH 5 +#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte0_MASK 0x1f +#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte0_OFFSET 5 +#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte0_WIDTH 3 +#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte0_MASK 0xe0 +#define D18F2x09C_x0000_0030_Reserved_15_8_OFFSET 8 +#define D18F2x09C_x0000_0030_Reserved_15_8_WIDTH 8 +#define D18F2x09C_x0000_0030_Reserved_15_8_MASK 0xff00 +#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte1_OFFSET 16 +#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte1_WIDTH 5 +#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte1_MASK 0x1f0000 +#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte1_OFFSET 21 +#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte1_WIDTH 3 +#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte1_MASK 0xe00000 +#define D18F2x09C_x0000_0030_Reserved_31_24_OFFSET 24 +#define D18F2x09C_x0000_0030_Reserved_31_24_WIDTH 8 +#define D18F2x09C_x0000_0030_Reserved_31_24_MASK 0xff000000 + +/// D18F2x09C_x0000_0030 +typedef union { + struct { ///< + UINT32 WrDqsFineDly_Byte0:5 ; ///< + UINT32 WrDqsGrossDly_Byte0:3 ; ///< + UINT32 Reserved_15_8:8 ; ///< + UINT32 WrDqsFineDly_Byte1:5 ; ///< + UINT32 WrDqsGrossDly_Byte1:3 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0000_0030_STRUCT; + +// **** D18F2x09C_x0000_0031 Register Definition **** +// Address +#define D18F2x09C_x0000_0031_ADDRESS 0x31 + +// Type +#define D18F2x09C_x0000_0031_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte2_OFFSET 0 +#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte2_WIDTH 5 +#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte2_MASK 0x1f +#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte2_OFFSET 5 +#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte2_WIDTH 3 +#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte2_MASK 0xe0 +#define D18F2x09C_x0000_0031_Reserved_15_8_OFFSET 8 +#define D18F2x09C_x0000_0031_Reserved_15_8_WIDTH 8 +#define D18F2x09C_x0000_0031_Reserved_15_8_MASK 0xff00 +#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte3_OFFSET 16 +#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte3_WIDTH 5 +#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte3_MASK 0x1f0000 +#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte3_OFFSET 21 +#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte3_WIDTH 3 +#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte3_MASK 0xe00000 +#define D18F2x09C_x0000_0031_Reserved_31_24_OFFSET 24 +#define D18F2x09C_x0000_0031_Reserved_31_24_WIDTH 8 +#define D18F2x09C_x0000_0031_Reserved_31_24_MASK 0xff000000 + +/// D18F2x09C_x0000_0031 +typedef union { + struct { ///< + UINT32 WrDqsFineDly_Byte2:5 ; ///< + UINT32 WrDqsGrossDly_Byte2:3 ; ///< + UINT32 Reserved_15_8:8 ; ///< + UINT32 WrDqsFineDly_Byte3:5 ; ///< + UINT32 WrDqsGrossDly_Byte3:3 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0000_0031_STRUCT; + +// **** D18F2x09C_x0000_0033 Register Definition **** +// Address +#define D18F2x09C_x0000_0033_ADDRESS 0x33 + +// Type +#define D18F2x09C_x0000_0033_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte0_OFFSET 0 +#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte0_WIDTH 5 +#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte0_MASK 0x1f +#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte0_OFFSET 5 +#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte0_WIDTH 3 +#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte0_MASK 0xe0 +#define D18F2x09C_x0000_0033_Reserved_15_8_OFFSET 8 +#define D18F2x09C_x0000_0033_Reserved_15_8_WIDTH 8 +#define D18F2x09C_x0000_0033_Reserved_15_8_MASK 0xff00 +#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte1_OFFSET 16 +#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte1_WIDTH 5 +#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte1_MASK 0x1f0000 +#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte1_OFFSET 21 +#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte1_WIDTH 3 +#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte1_MASK 0xe00000 +#define D18F2x09C_x0000_0033_Reserved_31_24_OFFSET 24 +#define D18F2x09C_x0000_0033_Reserved_31_24_WIDTH 8 +#define D18F2x09C_x0000_0033_Reserved_31_24_MASK 0xff000000 + +/// D18F2x09C_x0000_0033 +typedef union { + struct { ///< + UINT32 WrDqsFineDly_Byte0:5 ; ///< + UINT32 WrDqsGrossDly_Byte0:3 ; ///< + UINT32 Reserved_15_8:8 ; ///< + UINT32 WrDqsFineDly_Byte1:5 ; ///< + UINT32 WrDqsGrossDly_Byte1:3 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0000_0033_STRUCT; + +// **** D18F2x09C_x0000_0034 Register Definition **** +// Address +#define D18F2x09C_x0000_0034_ADDRESS 0x34 + +// Type +#define D18F2x09C_x0000_0034_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte2_OFFSET 0 +#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte2_WIDTH 5 +#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte2_MASK 0x1f +#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte2_OFFSET 5 +#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte2_WIDTH 3 +#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte2_MASK 0xe0 +#define D18F2x09C_x0000_0034_Reserved_15_8_OFFSET 8 +#define D18F2x09C_x0000_0034_Reserved_15_8_WIDTH 8 +#define D18F2x09C_x0000_0034_Reserved_15_8_MASK 0xff00 +#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte3_OFFSET 16 +#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte3_WIDTH 5 +#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte3_MASK 0x1f0000 +#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte3_OFFSET 21 +#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte3_WIDTH 3 +#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte3_MASK 0xe00000 +#define D18F2x09C_x0000_0034_Reserved_31_24_OFFSET 24 +#define D18F2x09C_x0000_0034_Reserved_31_24_WIDTH 8 +#define D18F2x09C_x0000_0034_Reserved_31_24_MASK 0xff000000 + +/// D18F2x09C_x0000_0034 +typedef union { + struct { ///< + UINT32 WrDqsFineDly_Byte2:5 ; ///< + UINT32 WrDqsGrossDly_Byte2:3 ; ///< + UINT32 Reserved_15_8:8 ; ///< + UINT32 WrDqsFineDly_Byte3:5 ; ///< + UINT32 WrDqsGrossDly_Byte3:3 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0000_0034_STRUCT; + +// **** D18F2x09C_x0000_0040 Register Definition **** +// Address +#define D18F2x09C_x0000_0040_ADDRESS 0x40 + +// Type +#define D18F2x09C_x0000_0040_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte4_OFFSET 0 +#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte4_WIDTH 5 +#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte4_MASK 0x1f +#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte4_OFFSET 5 +#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte4_WIDTH 3 +#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte4_MASK 0xe0 +#define D18F2x09C_x0000_0040_Reserved_15_8_OFFSET 8 +#define D18F2x09C_x0000_0040_Reserved_15_8_WIDTH 8 +#define D18F2x09C_x0000_0040_Reserved_15_8_MASK 0xff00 +#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte5_OFFSET 16 +#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte5_WIDTH 5 +#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte5_MASK 0x1f0000 +#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte5_OFFSET 21 +#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte5_WIDTH 3 +#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte5_MASK 0xe00000 +#define D18F2x09C_x0000_0040_Reserved_31_24_OFFSET 24 +#define D18F2x09C_x0000_0040_Reserved_31_24_WIDTH 8 +#define D18F2x09C_x0000_0040_Reserved_31_24_MASK 0xff000000 + +/// D18F2x09C_x0000_0040 +typedef union { + struct { ///< + UINT32 WrDqsFineDly_Byte4:5 ; ///< + UINT32 WrDqsGrossDly_Byte4:3 ; ///< + UINT32 Reserved_15_8:8 ; ///< + UINT32 WrDqsFineDly_Byte5:5 ; ///< + UINT32 WrDqsGrossDly_Byte5:3 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0000_0040_STRUCT; + +// **** D18F2x09C_x0000_0041 Register Definition **** +// Address +#define D18F2x09C_x0000_0041_ADDRESS 0x41 + +// Type +#define D18F2x09C_x0000_0041_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte6_OFFSET 0 +#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte6_WIDTH 5 +#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte6_MASK 0x1f +#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte6_OFFSET 5 +#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte6_WIDTH 3 +#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte6_MASK 0xe0 +#define D18F2x09C_x0000_0041_Reserved_15_8_OFFSET 8 +#define D18F2x09C_x0000_0041_Reserved_15_8_WIDTH 8 +#define D18F2x09C_x0000_0041_Reserved_15_8_MASK 0xff00 +#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte7_OFFSET 16 +#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte7_WIDTH 5 +#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte7_MASK 0x1f0000 +#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte7_OFFSET 21 +#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte7_WIDTH 3 +#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte7_MASK 0xe00000 +#define D18F2x09C_x0000_0041_Reserved_31_24_OFFSET 24 +#define D18F2x09C_x0000_0041_Reserved_31_24_WIDTH 8 +#define D18F2x09C_x0000_0041_Reserved_31_24_MASK 0xff000000 + +/// D18F2x09C_x0000_0041 +typedef union { + struct { ///< + UINT32 WrDqsFineDly_Byte6:5 ; ///< + UINT32 WrDqsGrossDly_Byte6:3 ; ///< + UINT32 Reserved_15_8:8 ; ///< + UINT32 WrDqsFineDly_Byte7:5 ; ///< + UINT32 WrDqsGrossDly_Byte7:3 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0000_0041_STRUCT; + +// **** D18F2x09C_x0000_0043 Register Definition **** +// Address +#define D18F2x09C_x0000_0043_ADDRESS 0x43 + +// Type +#define D18F2x09C_x0000_0043_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte4_OFFSET 0 +#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte4_WIDTH 5 +#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte4_MASK 0x1f +#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte4_OFFSET 5 +#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte4_WIDTH 3 +#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte4_MASK 0xe0 +#define D18F2x09C_x0000_0043_Reserved_15_8_OFFSET 8 +#define D18F2x09C_x0000_0043_Reserved_15_8_WIDTH 8 +#define D18F2x09C_x0000_0043_Reserved_15_8_MASK 0xff00 +#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte5_OFFSET 16 +#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte5_WIDTH 5 +#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte5_MASK 0x1f0000 +#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte5_OFFSET 21 +#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte5_WIDTH 3 +#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte5_MASK 0xe00000 +#define D18F2x09C_x0000_0043_Reserved_31_24_OFFSET 24 +#define D18F2x09C_x0000_0043_Reserved_31_24_WIDTH 8 +#define D18F2x09C_x0000_0043_Reserved_31_24_MASK 0xff000000 + +/// D18F2x09C_x0000_0043 +typedef union { + struct { ///< + UINT32 WrDqsFineDly_Byte4:5 ; ///< + UINT32 WrDqsGrossDly_Byte4:3 ; ///< + UINT32 Reserved_15_8:8 ; ///< + UINT32 WrDqsFineDly_Byte5:5 ; ///< + UINT32 WrDqsGrossDly_Byte5:3 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0000_0043_STRUCT; + +// **** D18F2x09C_x0000_0044 Register Definition **** +// Address +#define D18F2x09C_x0000_0044_ADDRESS 0x44 + +// Type +#define D18F2x09C_x0000_0044_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte6_OFFSET 0 +#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte6_WIDTH 5 +#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte6_MASK 0x1f +#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte6_OFFSET 5 +#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte6_WIDTH 3 +#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte6_MASK 0xe0 +#define D18F2x09C_x0000_0044_Reserved_15_8_OFFSET 8 +#define D18F2x09C_x0000_0044_Reserved_15_8_WIDTH 8 +#define D18F2x09C_x0000_0044_Reserved_15_8_MASK 0xff00 +#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte7_OFFSET 16 +#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte7_WIDTH 5 +#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte7_MASK 0x1f0000 +#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte7_OFFSET 21 +#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte7_WIDTH 3 +#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte7_MASK 0xe00000 +#define D18F2x09C_x0000_0044_Reserved_31_24_OFFSET 24 +#define D18F2x09C_x0000_0044_Reserved_31_24_WIDTH 8 +#define D18F2x09C_x0000_0044_Reserved_31_24_MASK 0xff000000 + +/// D18F2x09C_x0000_0044 +typedef union { + struct { ///< + UINT32 WrDqsFineDly_Byte6:5 ; ///< + UINT32 WrDqsGrossDly_Byte6:3 ; ///< + UINT32 Reserved_15_8:8 ; ///< + UINT32 WrDqsFineDly_Byte7:5 ; ///< + UINT32 WrDqsGrossDly_Byte7:3 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0000_0044_STRUCT; + +// **** D18F2x09C_x0000_0050 Register Definition **** +// Address +#define D18F2x09C_x0000_0050_ADDRESS 0x50 + +// Type +#define D18F2x09C_x0000_0050_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0000_0050_PhRecFineDly_Byte0_OFFSET 0 +#define D18F2x09C_x0000_0050_PhRecFineDly_Byte0_WIDTH 5 +#define D18F2x09C_x0000_0050_PhRecFineDly_Byte0_MASK 0x1f +#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte0_OFFSET 5 +#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte0_WIDTH 2 +#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte0_MASK 0x60 +#define D18F2x09C_x0000_0050_Reserved_7_7_OFFSET 7 +#define D18F2x09C_x0000_0050_Reserved_7_7_WIDTH 1 +#define D18F2x09C_x0000_0050_Reserved_7_7_MASK 0x80 +#define D18F2x09C_x0000_0050_PhRecFineDly_Byte1_OFFSET 8 +#define D18F2x09C_x0000_0050_PhRecFineDly_Byte1_WIDTH 5 +#define D18F2x09C_x0000_0050_PhRecFineDly_Byte1_MASK 0x1f00 +#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte1_OFFSET 13 +#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte1_WIDTH 2 +#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte1_MASK 0x6000 +#define D18F2x09C_x0000_0050_Reserved_15_15_OFFSET 15 +#define D18F2x09C_x0000_0050_Reserved_15_15_WIDTH 1 +#define D18F2x09C_x0000_0050_Reserved_15_15_MASK 0x8000 +#define D18F2x09C_x0000_0050_PhRecFineDly_Byte2_OFFSET 16 +#define D18F2x09C_x0000_0050_PhRecFineDly_Byte2_WIDTH 5 +#define D18F2x09C_x0000_0050_PhRecFineDly_Byte2_MASK 0x1f0000 +#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte2_OFFSET 21 +#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte2_WIDTH 2 +#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte2_MASK 0x600000 +#define D18F2x09C_x0000_0050_Reserved_23_23_OFFSET 23 +#define D18F2x09C_x0000_0050_Reserved_23_23_WIDTH 1 +#define D18F2x09C_x0000_0050_Reserved_23_23_MASK 0x800000 +#define D18F2x09C_x0000_0050_PhRecFineDly_Byte3_OFFSET 24 +#define D18F2x09C_x0000_0050_PhRecFineDly_Byte3_WIDTH 5 +#define D18F2x09C_x0000_0050_PhRecFineDly_Byte3_MASK 0x1f000000 +#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte3_OFFSET 29 +#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte3_WIDTH 2 +#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte3_MASK 0x60000000 +#define D18F2x09C_x0000_0050_Reserved_31_31_OFFSET 31 +#define D18F2x09C_x0000_0050_Reserved_31_31_WIDTH 1 +#define D18F2x09C_x0000_0050_Reserved_31_31_MASK 0x80000000 + +/// D18F2x09C_x0000_0050 +typedef union { + struct { ///< + UINT32 PhRecFineDly_Byte0:5 ; ///< + UINT32 PhRecGrossDly_Byte0:2 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 PhRecFineDly_Byte1:5 ; ///< + UINT32 PhRecGrossDly_Byte1:2 ; ///< + UINT32 Reserved_15_15:1 ; ///< + UINT32 PhRecFineDly_Byte2:5 ; ///< + UINT32 PhRecGrossDly_Byte2:2 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 PhRecFineDly_Byte3:5 ; ///< + UINT32 PhRecGrossDly_Byte3:2 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0000_0050_STRUCT; + +// **** D18F2x09C_x0000_0051 Register Definition **** +// Address +#define D18F2x09C_x0000_0051_ADDRESS 0x51 + +// Type +#define D18F2x09C_x0000_0051_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0000_0051_PhRecFineDly_Byte4_OFFSET 0 +#define D18F2x09C_x0000_0051_PhRecFineDly_Byte4_WIDTH 5 +#define D18F2x09C_x0000_0051_PhRecFineDly_Byte4_MASK 0x1f +#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte4_OFFSET 5 +#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte4_WIDTH 2 +#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte4_MASK 0x60 +#define D18F2x09C_x0000_0051_Reserved_7_7_OFFSET 7 +#define D18F2x09C_x0000_0051_Reserved_7_7_WIDTH 1 +#define D18F2x09C_x0000_0051_Reserved_7_7_MASK 0x80 +#define D18F2x09C_x0000_0051_PhRecFineDly_Byte5_OFFSET 8 +#define D18F2x09C_x0000_0051_PhRecFineDly_Byte5_WIDTH 5 +#define D18F2x09C_x0000_0051_PhRecFineDly_Byte5_MASK 0x1f00 +#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte5_OFFSET 13 +#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte5_WIDTH 2 +#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte5_MASK 0x6000 +#define D18F2x09C_x0000_0051_Reserved_15_15_OFFSET 15 +#define D18F2x09C_x0000_0051_Reserved_15_15_WIDTH 1 +#define D18F2x09C_x0000_0051_Reserved_15_15_MASK 0x8000 +#define D18F2x09C_x0000_0051_PhRecFineDly_Byte6_OFFSET 16 +#define D18F2x09C_x0000_0051_PhRecFineDly_Byte6_WIDTH 5 +#define D18F2x09C_x0000_0051_PhRecFineDly_Byte6_MASK 0x1f0000 +#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte6_OFFSET 21 +#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte6_WIDTH 2 +#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte6_MASK 0x600000 +#define D18F2x09C_x0000_0051_Reserved_23_23_OFFSET 23 +#define D18F2x09C_x0000_0051_Reserved_23_23_WIDTH 1 +#define D18F2x09C_x0000_0051_Reserved_23_23_MASK 0x800000 +#define D18F2x09C_x0000_0051_PhRecFineDly_Byte7_OFFSET 24 +#define D18F2x09C_x0000_0051_PhRecFineDly_Byte7_WIDTH 5 +#define D18F2x09C_x0000_0051_PhRecFineDly_Byte7_MASK 0x1f000000 +#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte7_OFFSET 29 +#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte7_WIDTH 2 +#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte7_MASK 0x60000000 +#define D18F2x09C_x0000_0051_Reserved_31_31_OFFSET 31 +#define D18F2x09C_x0000_0051_Reserved_31_31_WIDTH 1 +#define D18F2x09C_x0000_0051_Reserved_31_31_MASK 0x80000000 + +/// D18F2x09C_x0000_0051 +typedef union { + struct { ///< + UINT32 PhRecFineDly_Byte4:5 ; ///< + UINT32 PhRecGrossDly_Byte4:2 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 PhRecFineDly_Byte5:5 ; ///< + UINT32 PhRecGrossDly_Byte5:2 ; ///< + UINT32 Reserved_15_15:1 ; ///< + UINT32 PhRecFineDly_Byte6:5 ; ///< + UINT32 PhRecGrossDly_Byte6:2 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 PhRecFineDly_Byte7:5 ; ///< + UINT32 PhRecGrossDly_Byte7:2 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0000_0051_STRUCT; + + + + + +// **** D18F2x09C_x0D0F_0002 Register Definition **** +// Address +#define D18F2x09C_x0D0F_0002_ADDRESS 0xd0f0002 + +// Type +#define D18F2x09C_x0D0F_0002_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0002_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_0002_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_0002_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_0002_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_0002_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_0002_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_0002_Reserved_14_12_OFFSET 12 +#define D18F2x09C_x0D0F_0002_Reserved_14_12_WIDTH 3 +#define D18F2x09C_x0D0F_0002_Reserved_14_12_MASK 0x7000 +#define D18F2x09C_x0D0F_0002_ValidTxAndPre_OFFSET 15 +#define D18F2x09C_x0D0F_0002_ValidTxAndPre_WIDTH 1 +#define D18F2x09C_x0D0F_0002_ValidTxAndPre_MASK 0x8000 +#define D18F2x09C_x0D0F_0002_Reserved_31_16_OFFSET 16 +#define D18F2x09C_x0D0F_0002_Reserved_31_16_WIDTH 16 +#define D18F2x09C_x0D0F_0002_Reserved_31_16_MASK 0xffff0000 + +/// D18F2x09C_x0D0F_0002 +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_14_12:3 ; ///< + UINT32 ValidTxAndPre:1 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0002_STRUCT; + +// **** D18F2x09C_x0D0F_0006 Register Definition **** +// Address +#define D18F2x09C_x0D0F_0006_ADDRESS 0xd0f0006 + +// Type +#define D18F2x09C_x0D0F_0006_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0006_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_0006_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_0006_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_0006_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_0006_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_0006_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_0006_Reserved_31_12_OFFSET 12 +#define D18F2x09C_x0D0F_0006_Reserved_31_12_WIDTH 20 +#define D18F2x09C_x0D0F_0006_Reserved_31_12_MASK 0xfffff000 + +/// D18F2x09C_x0D0F_0006 +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0006_STRUCT; + +// **** D18F2x09C_x0D0F_000A Register Definition **** +// Address +#define D18F2x09C_x0D0F_000A_ADDRESS 0xd0f000a + +// Type +#define D18F2x09C_x0D0F_000A_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_000A_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_000A_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_000A_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_000A_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_000A_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_000A_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_000A_Reserved_31_12_OFFSET 12 +#define D18F2x09C_x0D0F_000A_Reserved_31_12_WIDTH 20 +#define D18F2x09C_x0D0F_000A_Reserved_31_12_MASK 0xfffff000 + +/// D18F2x09C_x0D0F_000A +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_000A_STRUCT; + +// **** D18F2x09C_x0D0F_000F Register Definition **** +// Address +#define D18F2x09C_x0D0F_000F_ADDRESS 0xd0f000f + +// Type +#define D18F2x09C_x0D0F_000F_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_000F_Reserved_11_0_OFFSET 0 +#define D18F2x09C_x0D0F_000F_Reserved_11_0_WIDTH 12 +#define D18F2x09C_x0D0F_000F_Reserved_11_0_MASK 0xfff +#define D18F2x09C_x0D0F_000F_AlwaysEnDllClks_OFFSET 12 +#define D18F2x09C_x0D0F_000F_AlwaysEnDllClks_WIDTH 3 +#define D18F2x09C_x0D0F_000F_AlwaysEnDllClks_MASK 0x7000 +#define D18F2x09C_x0D0F_000F_Reserved_31_15_OFFSET 15 +#define D18F2x09C_x0D0F_000F_Reserved_31_15_WIDTH 17 +#define D18F2x09C_x0D0F_000F_Reserved_31_15_MASK 0xffff8000 + +/// D18F2x09C_x0D0F_000F +typedef union { + struct { ///< + UINT32 Reserved_11_0:12; ///< + UINT32 AlwaysEnDllClks:3 ; ///< + UINT32 Reserved_31_15:17; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_000F_STRUCT; + +// **** D18F2x09C_x0D0F_0010 Register Definition **** +// Address +#define D18F2x09C_x0D0F_0010_ADDRESS 0xd0f0010 + +// Type +#define D18F2x09C_x0D0F_0010_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0010_Reserved_11_0_OFFSET 0 +#define D18F2x09C_x0D0F_0010_Reserved_11_0_WIDTH 12 +#define D18F2x09C_x0D0F_0010_Reserved_11_0_MASK 0xfff +#define D18F2x09C_x0D0F_0010_EnRxPadStandby_OFFSET 12 +#define D18F2x09C_x0D0F_0010_EnRxPadStandby_WIDTH 1 +#define D18F2x09C_x0D0F_0010_EnRxPadStandby_MASK 0x1000 +#define D18F2x09C_x0D0F_0010_Reserved_31_13_OFFSET 13 +#define D18F2x09C_x0D0F_0010_Reserved_31_13_WIDTH 19 +#define D18F2x09C_x0D0F_0010_Reserved_31_13_MASK 0xffffe000 + +/// D18F2x09C_x0D0F_0010 +typedef union { + struct { ///< + UINT32 Reserved_11_0:12; ///< + UINT32 EnRxPadStandby:1 ; ///< + UINT32 Reserved_31_13:19; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0010_STRUCT; + + + + +// **** D18F2x09C_x0D0F_0102 Register Definition **** +// Address +#define D18F2x09C_x0D0F_0102_ADDRESS 0xd0f0102 + +// Type +#define D18F2x09C_x0D0F_0102_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0102_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_0102_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_0102_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_0102_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_0102_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_0102_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_0102_Reserved_14_12_OFFSET 12 +#define D18F2x09C_x0D0F_0102_Reserved_14_12_WIDTH 3 +#define D18F2x09C_x0D0F_0102_Reserved_14_12_MASK 0x7000 +#define D18F2x09C_x0D0F_0102_ValidTxAndPre_OFFSET 15 +#define D18F2x09C_x0D0F_0102_ValidTxAndPre_WIDTH 1 +#define D18F2x09C_x0D0F_0102_ValidTxAndPre_MASK 0x8000 +#define D18F2x09C_x0D0F_0102_Reserved_31_16_OFFSET 16 +#define D18F2x09C_x0D0F_0102_Reserved_31_16_WIDTH 16 +#define D18F2x09C_x0D0F_0102_Reserved_31_16_MASK 0xffff0000 + +/// D18F2x09C_x0D0F_0102 +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_14_12:3 ; ///< + UINT32 ValidTxAndPre:1 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0102_STRUCT; + +// **** D18F2x09C_x0D0F_0106 Register Definition **** +// Address +#define D18F2x09C_x0D0F_0106_ADDRESS 0xd0f0106 + +// Type +#define D18F2x09C_x0D0F_0106_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0106_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_0106_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_0106_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_0106_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_0106_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_0106_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_0106_Reserved_31_12_OFFSET 12 +#define D18F2x09C_x0D0F_0106_Reserved_31_12_WIDTH 20 +#define D18F2x09C_x0D0F_0106_Reserved_31_12_MASK 0xfffff000 + +/// D18F2x09C_x0D0F_0106 +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0106_STRUCT; + +// **** D18F2x09C_x0D0F_010A Register Definition **** +// Address +#define D18F2x09C_x0D0F_010A_ADDRESS 0xd0f010a + +// Type +#define D18F2x09C_x0D0F_010A_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_010A_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_010A_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_010A_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_010A_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_010A_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_010A_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_010A_Reserved_31_12_OFFSET 12 +#define D18F2x09C_x0D0F_010A_Reserved_31_12_WIDTH 20 +#define D18F2x09C_x0D0F_010A_Reserved_31_12_MASK 0xfffff000 + +/// D18F2x09C_x0D0F_010A +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_010A_STRUCT; + +// **** D18F2x09C_x0D0F_010F Register Definition **** +// Address +#define D18F2x09C_x0D0F_010F_ADDRESS 0xd0f010f + +// Type +#define D18F2x09C_x0D0F_010F_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_010F_Reserved_11_0_OFFSET 0 +#define D18F2x09C_x0D0F_010F_Reserved_11_0_WIDTH 12 +#define D18F2x09C_x0D0F_010F_Reserved_11_0_MASK 0xfff +#define D18F2x09C_x0D0F_010F_AlwaysEnDllClks_OFFSET 12 +#define D18F2x09C_x0D0F_010F_AlwaysEnDllClks_WIDTH 3 +#define D18F2x09C_x0D0F_010F_AlwaysEnDllClks_MASK 0x7000 +#define D18F2x09C_x0D0F_010F_Reserved_31_15_OFFSET 15 +#define D18F2x09C_x0D0F_010F_Reserved_31_15_WIDTH 17 +#define D18F2x09C_x0D0F_010F_Reserved_31_15_MASK 0xffff8000 + +/// D18F2x09C_x0D0F_010F +typedef union { + struct { ///< + UINT32 Reserved_11_0:12; ///< + UINT32 AlwaysEnDllClks:3 ; ///< + UINT32 Reserved_31_15:17; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_010F_STRUCT; + +// **** D18F2x09C_x0D0F_0110 Register Definition **** +// Address +#define D18F2x09C_x0D0F_0110_ADDRESS 0xd0f0110 + +// Type +#define D18F2x09C_x0D0F_0110_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0110_Reserved_11_0_OFFSET 0 +#define D18F2x09C_x0D0F_0110_Reserved_11_0_WIDTH 12 +#define D18F2x09C_x0D0F_0110_Reserved_11_0_MASK 0xfff +#define D18F2x09C_x0D0F_0110_EnRxPadStandby_OFFSET 12 +#define D18F2x09C_x0D0F_0110_EnRxPadStandby_WIDTH 1 +#define D18F2x09C_x0D0F_0110_EnRxPadStandby_MASK 0x1000 +#define D18F2x09C_x0D0F_0110_Reserved_31_13_OFFSET 13 +#define D18F2x09C_x0D0F_0110_Reserved_31_13_WIDTH 19 +#define D18F2x09C_x0D0F_0110_Reserved_31_13_MASK 0xffffe000 + +/// D18F2x09C_x0D0F_0110 +typedef union { + struct { ///< + UINT32 Reserved_11_0:12; ///< + UINT32 EnRxPadStandby:1 ; ///< + UINT32 Reserved_31_13:19; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0110_STRUCT; + +// **** D18F2x09C_x0D0F_011F Register Definition **** +// Address +#define D18F2x09C_x0D0F_011F_ADDRESS 0xd0f011f + +// Type +#define D18F2x09C_x0D0F_011F_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_011F_Reserved_2_0_OFFSET 0 +#define D18F2x09C_x0D0F_011F_Reserved_2_0_WIDTH 3 +#define D18F2x09C_x0D0F_011F_Reserved_2_0_MASK 0x7 +#define D18F2x09C_x0D0F_011F_RxVioLvl_OFFSET 3 +#define D18F2x09C_x0D0F_011F_RxVioLvl_WIDTH 2 +#define D18F2x09C_x0D0F_011F_RxVioLvl_MASK 0x18 +#define D18F2x09C_x0D0F_011F_Reserved_31_5_OFFSET 5 +#define D18F2x09C_x0D0F_011F_Reserved_31_5_WIDTH 27 +#define D18F2x09C_x0D0F_011F_Reserved_31_5_MASK 0xffffffe0 + +/// D18F2x09C_x0D0F_011F +typedef union { + struct { ///< + UINT32 Reserved_2_0:3 ; ///< + UINT32 RxVioLvl:2 ; ///< + UINT32 Reserved_31_5:27; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_011F_STRUCT; + + + +// **** D18F2x09C_x0D0F_0202 Register Definition **** +// Address +#define D18F2x09C_x0D0F_0202_ADDRESS 0xd0f0202 + +// Type +#define D18F2x09C_x0D0F_0202_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0202_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_0202_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_0202_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_0202_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_0202_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_0202_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_0202_Reserved_14_12_OFFSET 12 +#define D18F2x09C_x0D0F_0202_Reserved_14_12_WIDTH 3 +#define D18F2x09C_x0D0F_0202_Reserved_14_12_MASK 0x7000 +#define D18F2x09C_x0D0F_0202_ValidTxAndPre_OFFSET 15 +#define D18F2x09C_x0D0F_0202_ValidTxAndPre_WIDTH 1 +#define D18F2x09C_x0D0F_0202_ValidTxAndPre_MASK 0x8000 +#define D18F2x09C_x0D0F_0202_Reserved_31_16_OFFSET 16 +#define D18F2x09C_x0D0F_0202_Reserved_31_16_WIDTH 16 +#define D18F2x09C_x0D0F_0202_Reserved_31_16_MASK 0xffff0000 + +/// D18F2x09C_x0D0F_0202 +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_14_12:3 ; ///< + UINT32 ValidTxAndPre:1 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0202_STRUCT; + +// **** D18F2x09C_x0D0F_0206 Register Definition **** +// Address +#define D18F2x09C_x0D0F_0206_ADDRESS 0xd0f0206 + +// Type +#define D18F2x09C_x0D0F_0206_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0206_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_0206_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_0206_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_0206_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_0206_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_0206_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_0206_Reserved_31_12_OFFSET 12 +#define D18F2x09C_x0D0F_0206_Reserved_31_12_WIDTH 20 +#define D18F2x09C_x0D0F_0206_Reserved_31_12_MASK 0xfffff000 + +/// D18F2x09C_x0D0F_0206 +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0206_STRUCT; + +// **** D18F2x09C_x0D0F_020A Register Definition **** +// Address +#define D18F2x09C_x0D0F_020A_ADDRESS 0xd0f020a + +// Type +#define D18F2x09C_x0D0F_020A_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_020A_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_020A_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_020A_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_020A_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_020A_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_020A_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_020A_Reserved_31_12_OFFSET 12 +#define D18F2x09C_x0D0F_020A_Reserved_31_12_WIDTH 20 +#define D18F2x09C_x0D0F_020A_Reserved_31_12_MASK 0xfffff000 + +/// D18F2x09C_x0D0F_020A +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_020A_STRUCT; + +// **** D18F2x09C_x0D0F_020F Register Definition **** +// Address +#define D18F2x09C_x0D0F_020F_ADDRESS 0xd0f020f + +// Type +#define D18F2x09C_x0D0F_020F_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_020F_Reserved_11_0_OFFSET 0 +#define D18F2x09C_x0D0F_020F_Reserved_11_0_WIDTH 12 +#define D18F2x09C_x0D0F_020F_Reserved_11_0_MASK 0xfff +#define D18F2x09C_x0D0F_020F_AlwaysEnDllClks_OFFSET 12 +#define D18F2x09C_x0D0F_020F_AlwaysEnDllClks_WIDTH 3 +#define D18F2x09C_x0D0F_020F_AlwaysEnDllClks_MASK 0x7000 +#define D18F2x09C_x0D0F_020F_Reserved_31_15_OFFSET 15 +#define D18F2x09C_x0D0F_020F_Reserved_31_15_WIDTH 17 +#define D18F2x09C_x0D0F_020F_Reserved_31_15_MASK 0xffff8000 + +/// D18F2x09C_x0D0F_020F +typedef union { + struct { ///< + UINT32 Reserved_11_0:12; ///< + UINT32 AlwaysEnDllClks:3 ; ///< + UINT32 Reserved_31_15:17; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_020F_STRUCT; + +// **** D18F2x09C_x0D0F_0210 Register Definition **** +// Address +#define D18F2x09C_x0D0F_0210_ADDRESS 0xd0f0210 + +// Type +#define D18F2x09C_x0D0F_0210_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0210_Reserved_11_0_OFFSET 0 +#define D18F2x09C_x0D0F_0210_Reserved_11_0_WIDTH 12 +#define D18F2x09C_x0D0F_0210_Reserved_11_0_MASK 0xfff +#define D18F2x09C_x0D0F_0210_EnRxPadStandby_OFFSET 12 +#define D18F2x09C_x0D0F_0210_EnRxPadStandby_WIDTH 1 +#define D18F2x09C_x0D0F_0210_EnRxPadStandby_MASK 0x1000 +#define D18F2x09C_x0D0F_0210_Reserved_31_13_OFFSET 13 +#define D18F2x09C_x0D0F_0210_Reserved_31_13_WIDTH 19 +#define D18F2x09C_x0D0F_0210_Reserved_31_13_MASK 0xffffe000 + +/// D18F2x09C_x0D0F_0210 +typedef union { + struct { ///< + UINT32 Reserved_11_0:12; ///< + UINT32 EnRxPadStandby:1 ; ///< + UINT32 Reserved_31_13:19; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0210_STRUCT; + +// **** D18F2x09C_x0D0F_021F Register Definition **** +// Address +#define D18F2x09C_x0D0F_021F_ADDRESS 0xd0f021f + +// Type +#define D18F2x09C_x0D0F_021F_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_021F_Reserved_2_0_OFFSET 0 +#define D18F2x09C_x0D0F_021F_Reserved_2_0_WIDTH 3 +#define D18F2x09C_x0D0F_021F_Reserved_2_0_MASK 0x7 +#define D18F2x09C_x0D0F_021F_RxVioLvl_OFFSET 3 +#define D18F2x09C_x0D0F_021F_RxVioLvl_WIDTH 2 +#define D18F2x09C_x0D0F_021F_RxVioLvl_MASK 0x18 +#define D18F2x09C_x0D0F_021F_Reserved_31_5_OFFSET 5 +#define D18F2x09C_x0D0F_021F_Reserved_31_5_WIDTH 27 +#define D18F2x09C_x0D0F_021F_Reserved_31_5_MASK 0xffffffe0 + +/// D18F2x09C_x0D0F_021F +typedef union { + struct { ///< + UINT32 Reserved_2_0:3 ; ///< + UINT32 RxVioLvl:2 ; ///< + UINT32 Reserved_31_5:27; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_021F_STRUCT; + + + +// **** D18F2x09C_x0D0F_0302 Register Definition **** +// Address +#define D18F2x09C_x0D0F_0302_ADDRESS 0xd0f0302 + +// Type +#define D18F2x09C_x0D0F_0302_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0302_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_0302_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_0302_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_0302_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_0302_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_0302_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_0302_Reserved_14_12_OFFSET 12 +#define D18F2x09C_x0D0F_0302_Reserved_14_12_WIDTH 3 +#define D18F2x09C_x0D0F_0302_Reserved_14_12_MASK 0x7000 +#define D18F2x09C_x0D0F_0302_ValidTxAndPre_OFFSET 15 +#define D18F2x09C_x0D0F_0302_ValidTxAndPre_WIDTH 1 +#define D18F2x09C_x0D0F_0302_ValidTxAndPre_MASK 0x8000 +#define D18F2x09C_x0D0F_0302_Reserved_31_16_OFFSET 16 +#define D18F2x09C_x0D0F_0302_Reserved_31_16_WIDTH 16 +#define D18F2x09C_x0D0F_0302_Reserved_31_16_MASK 0xffff0000 + +/// D18F2x09C_x0D0F_0302 +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_14_12:3 ; ///< + UINT32 ValidTxAndPre:1 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0302_STRUCT; + +// **** D18F2x09C_x0D0F_0306 Register Definition **** +// Address +#define D18F2x09C_x0D0F_0306_ADDRESS 0xd0f0306 + +// Type +#define D18F2x09C_x0D0F_0306_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0306_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_0306_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_0306_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_0306_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_0306_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_0306_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_0306_Reserved_31_12_OFFSET 12 +#define D18F2x09C_x0D0F_0306_Reserved_31_12_WIDTH 20 +#define D18F2x09C_x0D0F_0306_Reserved_31_12_MASK 0xfffff000 + +/// D18F2x09C_x0D0F_0306 +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0306_STRUCT; + +// **** D18F2x09C_x0D0F_030A Register Definition **** +// Address +#define D18F2x09C_x0D0F_030A_ADDRESS 0xd0f030a + +// Type +#define D18F2x09C_x0D0F_030A_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_030A_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_030A_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_030A_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_030A_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_030A_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_030A_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_030A_Reserved_31_12_OFFSET 12 +#define D18F2x09C_x0D0F_030A_Reserved_31_12_WIDTH 20 +#define D18F2x09C_x0D0F_030A_Reserved_31_12_MASK 0xfffff000 + +/// D18F2x09C_x0D0F_030A +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_030A_STRUCT; + +// **** D18F2x09C_x0D0F_030F Register Definition **** +// Address +#define D18F2x09C_x0D0F_030F_ADDRESS 0xd0f030f + +// Type +#define D18F2x09C_x0D0F_030F_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_030F_Reserved_11_0_OFFSET 0 +#define D18F2x09C_x0D0F_030F_Reserved_11_0_WIDTH 12 +#define D18F2x09C_x0D0F_030F_Reserved_11_0_MASK 0xfff +#define D18F2x09C_x0D0F_030F_AlwaysEnDllClks_OFFSET 12 +#define D18F2x09C_x0D0F_030F_AlwaysEnDllClks_WIDTH 3 +#define D18F2x09C_x0D0F_030F_AlwaysEnDllClks_MASK 0x7000 +#define D18F2x09C_x0D0F_030F_Reserved_31_15_OFFSET 15 +#define D18F2x09C_x0D0F_030F_Reserved_31_15_WIDTH 17 +#define D18F2x09C_x0D0F_030F_Reserved_31_15_MASK 0xffff8000 + +/// D18F2x09C_x0D0F_030F +typedef union { + struct { ///< + UINT32 Reserved_11_0:12; ///< + UINT32 AlwaysEnDllClks:3 ; ///< + UINT32 Reserved_31_15:17; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_030F_STRUCT; + +// **** D18F2x09C_x0D0F_0310 Register Definition **** +// Address +#define D18F2x09C_x0D0F_0310_ADDRESS 0xd0f0310 + +// Type +#define D18F2x09C_x0D0F_0310_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0310_Reserved_11_0_OFFSET 0 +#define D18F2x09C_x0D0F_0310_Reserved_11_0_WIDTH 12 +#define D18F2x09C_x0D0F_0310_Reserved_11_0_MASK 0xfff +#define D18F2x09C_x0D0F_0310_EnRxPadStandby_OFFSET 12 +#define D18F2x09C_x0D0F_0310_EnRxPadStandby_WIDTH 1 +#define D18F2x09C_x0D0F_0310_EnRxPadStandby_MASK 0x1000 +#define D18F2x09C_x0D0F_0310_Reserved_31_13_OFFSET 13 +#define D18F2x09C_x0D0F_0310_Reserved_31_13_WIDTH 19 +#define D18F2x09C_x0D0F_0310_Reserved_31_13_MASK 0xffffe000 + +/// D18F2x09C_x0D0F_0310 +typedef union { + struct { ///< + UINT32 Reserved_11_0:12; ///< + UINT32 EnRxPadStandby:1 ; ///< + UINT32 Reserved_31_13:19; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0310_STRUCT; + +// **** D18F2x09C_x0D0F_031F Register Definition **** +// Address +#define D18F2x09C_x0D0F_031F_ADDRESS 0xd0f031f + +// Type +#define D18F2x09C_x0D0F_031F_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_031F_Reserved_2_0_OFFSET 0 +#define D18F2x09C_x0D0F_031F_Reserved_2_0_WIDTH 3 +#define D18F2x09C_x0D0F_031F_Reserved_2_0_MASK 0x7 +#define D18F2x09C_x0D0F_031F_RxVioLvl_OFFSET 3 +#define D18F2x09C_x0D0F_031F_RxVioLvl_WIDTH 2 +#define D18F2x09C_x0D0F_031F_RxVioLvl_MASK 0x18 +#define D18F2x09C_x0D0F_031F_Reserved_31_5_OFFSET 5 +#define D18F2x09C_x0D0F_031F_Reserved_31_5_WIDTH 27 +#define D18F2x09C_x0D0F_031F_Reserved_31_5_MASK 0xffffffe0 + +/// D18F2x09C_x0D0F_031F +typedef union { + struct { ///< + UINT32 Reserved_2_0:3 ; ///< + UINT32 RxVioLvl:2 ; ///< + UINT32 Reserved_31_5:27; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_031F_STRUCT; + + + +// **** D18F2x09C_x0D0F_0402 Register Definition **** +// Address +#define D18F2x09C_x0D0F_0402_ADDRESS 0xd0f0402 + +// Type +#define D18F2x09C_x0D0F_0402_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0402_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_0402_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_0402_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_0402_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_0402_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_0402_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_0402_Reserved_14_12_OFFSET 12 +#define D18F2x09C_x0D0F_0402_Reserved_14_12_WIDTH 3 +#define D18F2x09C_x0D0F_0402_Reserved_14_12_MASK 0x7000 +#define D18F2x09C_x0D0F_0402_ValidTxAndPre_OFFSET 15 +#define D18F2x09C_x0D0F_0402_ValidTxAndPre_WIDTH 1 +#define D18F2x09C_x0D0F_0402_ValidTxAndPre_MASK 0x8000 +#define D18F2x09C_x0D0F_0402_Reserved_31_16_OFFSET 16 +#define D18F2x09C_x0D0F_0402_Reserved_31_16_WIDTH 16 +#define D18F2x09C_x0D0F_0402_Reserved_31_16_MASK 0xffff0000 + +/// D18F2x09C_x0D0F_0402 +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_14_12:3 ; ///< + UINT32 ValidTxAndPre:1 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0402_STRUCT; + +// **** D18F2x09C_x0D0F_0406 Register Definition **** +// Address +#define D18F2x09C_x0D0F_0406_ADDRESS 0xd0f0406 + +// Type +#define D18F2x09C_x0D0F_0406_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0406_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_0406_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_0406_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_0406_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_0406_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_0406_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_0406_Reserved_31_12_OFFSET 12 +#define D18F2x09C_x0D0F_0406_Reserved_31_12_WIDTH 20 +#define D18F2x09C_x0D0F_0406_Reserved_31_12_MASK 0xfffff000 + +/// D18F2x09C_x0D0F_0406 +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0406_STRUCT; + +// **** D18F2x09C_x0D0F_040A Register Definition **** +// Address +#define D18F2x09C_x0D0F_040A_ADDRESS 0xd0f040a + +// Type +#define D18F2x09C_x0D0F_040A_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_040A_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_040A_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_040A_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_040A_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_040A_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_040A_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_040A_Reserved_31_12_OFFSET 12 +#define D18F2x09C_x0D0F_040A_Reserved_31_12_WIDTH 20 +#define D18F2x09C_x0D0F_040A_Reserved_31_12_MASK 0xfffff000 + +/// D18F2x09C_x0D0F_040A +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_040A_STRUCT; + +// **** D18F2x09C_x0D0F_040F Register Definition **** +// Address +#define D18F2x09C_x0D0F_040F_ADDRESS 0xd0f040f + +// Type +#define D18F2x09C_x0D0F_040F_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_040F_Reserved_11_0_OFFSET 0 +#define D18F2x09C_x0D0F_040F_Reserved_11_0_WIDTH 12 +#define D18F2x09C_x0D0F_040F_Reserved_11_0_MASK 0xfff +#define D18F2x09C_x0D0F_040F_AlwaysEnDllClks_OFFSET 12 +#define D18F2x09C_x0D0F_040F_AlwaysEnDllClks_WIDTH 3 +#define D18F2x09C_x0D0F_040F_AlwaysEnDllClks_MASK 0x7000 +#define D18F2x09C_x0D0F_040F_Reserved_31_15_OFFSET 15 +#define D18F2x09C_x0D0F_040F_Reserved_31_15_WIDTH 17 +#define D18F2x09C_x0D0F_040F_Reserved_31_15_MASK 0xffff8000 + +/// D18F2x09C_x0D0F_040F +typedef union { + struct { ///< + UINT32 Reserved_11_0:12; ///< + UINT32 AlwaysEnDllClks:3 ; ///< + UINT32 Reserved_31_15:17; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_040F_STRUCT; + +// **** D18F2x09C_x0D0F_0410 Register Definition **** +// Address +#define D18F2x09C_x0D0F_0410_ADDRESS 0xd0f0410 + +// Type +#define D18F2x09C_x0D0F_0410_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0410_Reserved_11_0_OFFSET 0 +#define D18F2x09C_x0D0F_0410_Reserved_11_0_WIDTH 12 +#define D18F2x09C_x0D0F_0410_Reserved_11_0_MASK 0xfff +#define D18F2x09C_x0D0F_0410_EnRxPadStandby_OFFSET 12 +#define D18F2x09C_x0D0F_0410_EnRxPadStandby_WIDTH 1 +#define D18F2x09C_x0D0F_0410_EnRxPadStandby_MASK 0x1000 +#define D18F2x09C_x0D0F_0410_Reserved_31_13_OFFSET 13 +#define D18F2x09C_x0D0F_0410_Reserved_31_13_WIDTH 19 +#define D18F2x09C_x0D0F_0410_Reserved_31_13_MASK 0xffffe000 + +/// D18F2x09C_x0D0F_0410 +typedef union { + struct { ///< + UINT32 Reserved_11_0:12; ///< + UINT32 EnRxPadStandby:1 ; ///< + UINT32 Reserved_31_13:19; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0410_STRUCT; + +// **** D18F2x09C_x0D0F_041F Register Definition **** +// Address +#define D18F2x09C_x0D0F_041F_ADDRESS 0xd0f041f + +// Type +#define D18F2x09C_x0D0F_041F_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_041F_Reserved_2_0_OFFSET 0 +#define D18F2x09C_x0D0F_041F_Reserved_2_0_WIDTH 3 +#define D18F2x09C_x0D0F_041F_Reserved_2_0_MASK 0x7 +#define D18F2x09C_x0D0F_041F_RxVioLvl_OFFSET 3 +#define D18F2x09C_x0D0F_041F_RxVioLvl_WIDTH 2 +#define D18F2x09C_x0D0F_041F_RxVioLvl_MASK 0x18 +#define D18F2x09C_x0D0F_041F_Reserved_31_5_OFFSET 5 +#define D18F2x09C_x0D0F_041F_Reserved_31_5_WIDTH 27 +#define D18F2x09C_x0D0F_041F_Reserved_31_5_MASK 0xffffffe0 + +/// D18F2x09C_x0D0F_041F +typedef union { + struct { ///< + UINT32 Reserved_2_0:3 ; ///< + UINT32 RxVioLvl:2 ; ///< + UINT32 Reserved_31_5:27; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_041F_STRUCT; + + + +// **** D18F2x09C_x0D0F_0502 Register Definition **** +// Address +#define D18F2x09C_x0D0F_0502_ADDRESS 0xd0f0502 + +// Type +#define D18F2x09C_x0D0F_0502_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0502_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_0502_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_0502_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_0502_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_0502_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_0502_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_0502_Reserved_14_12_OFFSET 12 +#define D18F2x09C_x0D0F_0502_Reserved_14_12_WIDTH 3 +#define D18F2x09C_x0D0F_0502_Reserved_14_12_MASK 0x7000 +#define D18F2x09C_x0D0F_0502_ValidTxAndPre_OFFSET 15 +#define D18F2x09C_x0D0F_0502_ValidTxAndPre_WIDTH 1 +#define D18F2x09C_x0D0F_0502_ValidTxAndPre_MASK 0x8000 +#define D18F2x09C_x0D0F_0502_Reserved_31_16_OFFSET 16 +#define D18F2x09C_x0D0F_0502_Reserved_31_16_WIDTH 16 +#define D18F2x09C_x0D0F_0502_Reserved_31_16_MASK 0xffff0000 + +/// D18F2x09C_x0D0F_0502 +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_14_12:3 ; ///< + UINT32 ValidTxAndPre:1 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0502_STRUCT; + +// **** D18F2x09C_x0D0F_0506 Register Definition **** +// Address +#define D18F2x09C_x0D0F_0506_ADDRESS 0xd0f0506 + +// Type +#define D18F2x09C_x0D0F_0506_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0506_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_0506_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_0506_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_0506_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_0506_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_0506_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_0506_Reserved_31_12_OFFSET 12 +#define D18F2x09C_x0D0F_0506_Reserved_31_12_WIDTH 20 +#define D18F2x09C_x0D0F_0506_Reserved_31_12_MASK 0xfffff000 + +/// D18F2x09C_x0D0F_0506 +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0506_STRUCT; + +// **** D18F2x09C_x0D0F_050A Register Definition **** +// Address +#define D18F2x09C_x0D0F_050A_ADDRESS 0xd0f050a + +// Type +#define D18F2x09C_x0D0F_050A_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_050A_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_050A_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_050A_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_050A_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_050A_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_050A_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_050A_Reserved_31_12_OFFSET 12 +#define D18F2x09C_x0D0F_050A_Reserved_31_12_WIDTH 20 +#define D18F2x09C_x0D0F_050A_Reserved_31_12_MASK 0xfffff000 + +/// D18F2x09C_x0D0F_050A +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_050A_STRUCT; + +// **** D18F2x09C_x0D0F_050F Register Definition **** +// Address +#define D18F2x09C_x0D0F_050F_ADDRESS 0xd0f050f + +// Type +#define D18F2x09C_x0D0F_050F_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_050F_Reserved_11_0_OFFSET 0 +#define D18F2x09C_x0D0F_050F_Reserved_11_0_WIDTH 12 +#define D18F2x09C_x0D0F_050F_Reserved_11_0_MASK 0xfff +#define D18F2x09C_x0D0F_050F_AlwaysEnDllClks_OFFSET 12 +#define D18F2x09C_x0D0F_050F_AlwaysEnDllClks_WIDTH 3 +#define D18F2x09C_x0D0F_050F_AlwaysEnDllClks_MASK 0x7000 +#define D18F2x09C_x0D0F_050F_Reserved_31_15_OFFSET 15 +#define D18F2x09C_x0D0F_050F_Reserved_31_15_WIDTH 17 +#define D18F2x09C_x0D0F_050F_Reserved_31_15_MASK 0xffff8000 + +/// D18F2x09C_x0D0F_050F +typedef union { + struct { ///< + UINT32 Reserved_11_0:12; ///< + UINT32 AlwaysEnDllClks:3 ; ///< + UINT32 Reserved_31_15:17; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_050F_STRUCT; + +// **** D18F2x09C_x0D0F_0510 Register Definition **** +// Address +#define D18F2x09C_x0D0F_0510_ADDRESS 0xd0f0510 + +// Type +#define D18F2x09C_x0D0F_0510_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0510_Reserved_11_0_OFFSET 0 +#define D18F2x09C_x0D0F_0510_Reserved_11_0_WIDTH 12 +#define D18F2x09C_x0D0F_0510_Reserved_11_0_MASK 0xfff +#define D18F2x09C_x0D0F_0510_EnRxPadStandby_OFFSET 12 +#define D18F2x09C_x0D0F_0510_EnRxPadStandby_WIDTH 1 +#define D18F2x09C_x0D0F_0510_EnRxPadStandby_MASK 0x1000 +#define D18F2x09C_x0D0F_0510_Reserved_31_13_OFFSET 13 +#define D18F2x09C_x0D0F_0510_Reserved_31_13_WIDTH 19 +#define D18F2x09C_x0D0F_0510_Reserved_31_13_MASK 0xffffe000 + +/// D18F2x09C_x0D0F_0510 +typedef union { + struct { ///< + UINT32 Reserved_11_0:12; ///< + UINT32 EnRxPadStandby:1 ; ///< + UINT32 Reserved_31_13:19; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0510_STRUCT; + +// **** D18F2x09C_x0D0F_051F Register Definition **** +// Address +#define D18F2x09C_x0D0F_051F_ADDRESS 0xd0f051f + +// Type +#define D18F2x09C_x0D0F_051F_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_051F_Reserved_2_0_OFFSET 0 +#define D18F2x09C_x0D0F_051F_Reserved_2_0_WIDTH 3 +#define D18F2x09C_x0D0F_051F_Reserved_2_0_MASK 0x7 +#define D18F2x09C_x0D0F_051F_RxVioLvl_OFFSET 3 +#define D18F2x09C_x0D0F_051F_RxVioLvl_WIDTH 2 +#define D18F2x09C_x0D0F_051F_RxVioLvl_MASK 0x18 +#define D18F2x09C_x0D0F_051F_Reserved_31_5_OFFSET 5 +#define D18F2x09C_x0D0F_051F_Reserved_31_5_WIDTH 27 +#define D18F2x09C_x0D0F_051F_Reserved_31_5_MASK 0xffffffe0 + +/// D18F2x09C_x0D0F_051F +typedef union { + struct { ///< + UINT32 Reserved_2_0:3 ; ///< + UINT32 RxVioLvl:2 ; ///< + UINT32 Reserved_31_5:27; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_051F_STRUCT; + + + +// **** D18F2x09C_x0D0F_0602 Register Definition **** +// Address +#define D18F2x09C_x0D0F_0602_ADDRESS 0xd0f0602 + +// Type +#define D18F2x09C_x0D0F_0602_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0602_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_0602_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_0602_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_0602_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_0602_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_0602_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_0602_Reserved_14_12_OFFSET 12 +#define D18F2x09C_x0D0F_0602_Reserved_14_12_WIDTH 3 +#define D18F2x09C_x0D0F_0602_Reserved_14_12_MASK 0x7000 +#define D18F2x09C_x0D0F_0602_ValidTxAndPre_OFFSET 15 +#define D18F2x09C_x0D0F_0602_ValidTxAndPre_WIDTH 1 +#define D18F2x09C_x0D0F_0602_ValidTxAndPre_MASK 0x8000 +#define D18F2x09C_x0D0F_0602_Reserved_31_16_OFFSET 16 +#define D18F2x09C_x0D0F_0602_Reserved_31_16_WIDTH 16 +#define D18F2x09C_x0D0F_0602_Reserved_31_16_MASK 0xffff0000 + +/// D18F2x09C_x0D0F_0602 +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_14_12:3 ; ///< + UINT32 ValidTxAndPre:1 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0602_STRUCT; + +// **** D18F2x09C_x0D0F_0606 Register Definition **** +// Address +#define D18F2x09C_x0D0F_0606_ADDRESS 0xd0f0606 + +// Type +#define D18F2x09C_x0D0F_0606_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0606_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_0606_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_0606_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_0606_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_0606_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_0606_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_0606_Reserved_31_12_OFFSET 12 +#define D18F2x09C_x0D0F_0606_Reserved_31_12_WIDTH 20 +#define D18F2x09C_x0D0F_0606_Reserved_31_12_MASK 0xfffff000 + +/// D18F2x09C_x0D0F_0606 +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0606_STRUCT; + +// **** D18F2x09C_x0D0F_060A Register Definition **** +// Address +#define D18F2x09C_x0D0F_060A_ADDRESS 0xd0f060a + +// Type +#define D18F2x09C_x0D0F_060A_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_060A_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_060A_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_060A_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_060A_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_060A_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_060A_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_060A_Reserved_31_12_OFFSET 12 +#define D18F2x09C_x0D0F_060A_Reserved_31_12_WIDTH 20 +#define D18F2x09C_x0D0F_060A_Reserved_31_12_MASK 0xfffff000 + +/// D18F2x09C_x0D0F_060A +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_060A_STRUCT; + +// **** D18F2x09C_x0D0F_060F Register Definition **** +// Address +#define D18F2x09C_x0D0F_060F_ADDRESS 0xd0f060f + +// Type +#define D18F2x09C_x0D0F_060F_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_060F_Reserved_11_0_OFFSET 0 +#define D18F2x09C_x0D0F_060F_Reserved_11_0_WIDTH 12 +#define D18F2x09C_x0D0F_060F_Reserved_11_0_MASK 0xfff +#define D18F2x09C_x0D0F_060F_AlwaysEnDllClks_OFFSET 12 +#define D18F2x09C_x0D0F_060F_AlwaysEnDllClks_WIDTH 3 +#define D18F2x09C_x0D0F_060F_AlwaysEnDllClks_MASK 0x7000 +#define D18F2x09C_x0D0F_060F_Reserved_31_15_OFFSET 15 +#define D18F2x09C_x0D0F_060F_Reserved_31_15_WIDTH 17 +#define D18F2x09C_x0D0F_060F_Reserved_31_15_MASK 0xffff8000 + +/// D18F2x09C_x0D0F_060F +typedef union { + struct { ///< + UINT32 Reserved_11_0:12; ///< + UINT32 AlwaysEnDllClks:3 ; ///< + UINT32 Reserved_31_15:17; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_060F_STRUCT; + +// **** D18F2x09C_x0D0F_0610 Register Definition **** +// Address +#define D18F2x09C_x0D0F_0610_ADDRESS 0xd0f0610 + +// Type +#define D18F2x09C_x0D0F_0610_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0610_Reserved_11_0_OFFSET 0 +#define D18F2x09C_x0D0F_0610_Reserved_11_0_WIDTH 12 +#define D18F2x09C_x0D0F_0610_Reserved_11_0_MASK 0xfff +#define D18F2x09C_x0D0F_0610_EnRxPadStandby_OFFSET 12 +#define D18F2x09C_x0D0F_0610_EnRxPadStandby_WIDTH 1 +#define D18F2x09C_x0D0F_0610_EnRxPadStandby_MASK 0x1000 +#define D18F2x09C_x0D0F_0610_Reserved_31_13_OFFSET 13 +#define D18F2x09C_x0D0F_0610_Reserved_31_13_WIDTH 19 +#define D18F2x09C_x0D0F_0610_Reserved_31_13_MASK 0xffffe000 + +/// D18F2x09C_x0D0F_0610 +typedef union { + struct { ///< + UINT32 Reserved_11_0:12; ///< + UINT32 EnRxPadStandby:1 ; ///< + UINT32 Reserved_31_13:19; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0610_STRUCT; + +// **** D18F2x09C_x0D0F_061F Register Definition **** +// Address +#define D18F2x09C_x0D0F_061F_ADDRESS 0xd0f061f + +// Type +#define D18F2x09C_x0D0F_061F_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_061F_Reserved_2_0_OFFSET 0 +#define D18F2x09C_x0D0F_061F_Reserved_2_0_WIDTH 3 +#define D18F2x09C_x0D0F_061F_Reserved_2_0_MASK 0x7 +#define D18F2x09C_x0D0F_061F_RxVioLvl_OFFSET 3 +#define D18F2x09C_x0D0F_061F_RxVioLvl_WIDTH 2 +#define D18F2x09C_x0D0F_061F_RxVioLvl_MASK 0x18 +#define D18F2x09C_x0D0F_061F_Reserved_31_5_OFFSET 5 +#define D18F2x09C_x0D0F_061F_Reserved_31_5_WIDTH 27 +#define D18F2x09C_x0D0F_061F_Reserved_31_5_MASK 0xffffffe0 + +/// D18F2x09C_x0D0F_061F +typedef union { + struct { ///< + UINT32 Reserved_2_0:3 ; ///< + UINT32 RxVioLvl:2 ; ///< + UINT32 Reserved_31_5:27; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_061F_STRUCT; + + + +// **** D18F2x09C_x0D0F_0702 Register Definition **** +// Address +#define D18F2x09C_x0D0F_0702_ADDRESS 0xd0f0702 + +// Type +#define D18F2x09C_x0D0F_0702_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0702_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_0702_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_0702_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_0702_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_0702_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_0702_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_0702_Reserved_14_12_OFFSET 12 +#define D18F2x09C_x0D0F_0702_Reserved_14_12_WIDTH 3 +#define D18F2x09C_x0D0F_0702_Reserved_14_12_MASK 0x7000 +#define D18F2x09C_x0D0F_0702_ValidTxAndPre_OFFSET 15 +#define D18F2x09C_x0D0F_0702_ValidTxAndPre_WIDTH 1 +#define D18F2x09C_x0D0F_0702_ValidTxAndPre_MASK 0x8000 +#define D18F2x09C_x0D0F_0702_Reserved_31_16_OFFSET 16 +#define D18F2x09C_x0D0F_0702_Reserved_31_16_WIDTH 16 +#define D18F2x09C_x0D0F_0702_Reserved_31_16_MASK 0xffff0000 + +/// D18F2x09C_x0D0F_0702 +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_14_12:3 ; ///< + UINT32 ValidTxAndPre:1 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0702_STRUCT; + +// **** D18F2x09C_x0D0F_0706 Register Definition **** +// Address +#define D18F2x09C_x0D0F_0706_ADDRESS 0xd0f0706 + +// Type +#define D18F2x09C_x0D0F_0706_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0706_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_0706_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_0706_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_0706_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_0706_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_0706_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_0706_Reserved_31_12_OFFSET 12 +#define D18F2x09C_x0D0F_0706_Reserved_31_12_WIDTH 20 +#define D18F2x09C_x0D0F_0706_Reserved_31_12_MASK 0xfffff000 + +/// D18F2x09C_x0D0F_0706 +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0706_STRUCT; + +// **** D18F2x09C_x0D0F_070A Register Definition **** +// Address +#define D18F2x09C_x0D0F_070A_ADDRESS 0xd0f070a + +// Type +#define D18F2x09C_x0D0F_070A_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_070A_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_070A_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_070A_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_070A_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_070A_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_070A_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_070A_Reserved_31_12_OFFSET 12 +#define D18F2x09C_x0D0F_070A_Reserved_31_12_WIDTH 20 +#define D18F2x09C_x0D0F_070A_Reserved_31_12_MASK 0xfffff000 + +/// D18F2x09C_x0D0F_070A +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_070A_STRUCT; + +// **** D18F2x09C_x0D0F_070F Register Definition **** +// Address +#define D18F2x09C_x0D0F_070F_ADDRESS 0xd0f070f + +// Type +#define D18F2x09C_x0D0F_070F_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_070F_Reserved_11_0_OFFSET 0 +#define D18F2x09C_x0D0F_070F_Reserved_11_0_WIDTH 12 +#define D18F2x09C_x0D0F_070F_Reserved_11_0_MASK 0xfff +#define D18F2x09C_x0D0F_070F_AlwaysEnDllClks_OFFSET 12 +#define D18F2x09C_x0D0F_070F_AlwaysEnDllClks_WIDTH 3 +#define D18F2x09C_x0D0F_070F_AlwaysEnDllClks_MASK 0x7000 +#define D18F2x09C_x0D0F_070F_Reserved_31_15_OFFSET 15 +#define D18F2x09C_x0D0F_070F_Reserved_31_15_WIDTH 17 +#define D18F2x09C_x0D0F_070F_Reserved_31_15_MASK 0xffff8000 + +/// D18F2x09C_x0D0F_070F +typedef union { + struct { ///< + UINT32 Reserved_11_0:12; ///< + UINT32 AlwaysEnDllClks:3 ; ///< + UINT32 Reserved_31_15:17; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_070F_STRUCT; + +// **** D18F2x09C_x0D0F_0710 Register Definition **** +// Address +#define D18F2x09C_x0D0F_0710_ADDRESS 0xd0f0710 + +// Type +#define D18F2x09C_x0D0F_0710_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0710_Reserved_11_0_OFFSET 0 +#define D18F2x09C_x0D0F_0710_Reserved_11_0_WIDTH 12 +#define D18F2x09C_x0D0F_0710_Reserved_11_0_MASK 0xfff +#define D18F2x09C_x0D0F_0710_EnRxPadStandby_OFFSET 12 +#define D18F2x09C_x0D0F_0710_EnRxPadStandby_WIDTH 1 +#define D18F2x09C_x0D0F_0710_EnRxPadStandby_MASK 0x1000 +#define D18F2x09C_x0D0F_0710_Reserved_31_13_OFFSET 13 +#define D18F2x09C_x0D0F_0710_Reserved_31_13_WIDTH 19 +#define D18F2x09C_x0D0F_0710_Reserved_31_13_MASK 0xffffe000 + +/// D18F2x09C_x0D0F_0710 +typedef union { + struct { ///< + UINT32 Reserved_11_0:12; ///< + UINT32 EnRxPadStandby:1 ; ///< + UINT32 Reserved_31_13:19; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0710_STRUCT; + +// **** D18F2x09C_x0D0F_071F Register Definition **** +// Address +#define D18F2x09C_x0D0F_071F_ADDRESS 0xd0f071f + +// Type +#define D18F2x09C_x0D0F_071F_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_071F_Reserved_2_0_OFFSET 0 +#define D18F2x09C_x0D0F_071F_Reserved_2_0_WIDTH 3 +#define D18F2x09C_x0D0F_071F_Reserved_2_0_MASK 0x7 +#define D18F2x09C_x0D0F_071F_RxVioLvl_OFFSET 3 +#define D18F2x09C_x0D0F_071F_RxVioLvl_WIDTH 2 +#define D18F2x09C_x0D0F_071F_RxVioLvl_MASK 0x18 +#define D18F2x09C_x0D0F_071F_Reserved_31_5_OFFSET 5 +#define D18F2x09C_x0D0F_071F_Reserved_31_5_WIDTH 27 +#define D18F2x09C_x0D0F_071F_Reserved_31_5_MASK 0xffffffe0 + +/// D18F2x09C_x0D0F_071F +typedef union { + struct { ///< + UINT32 Reserved_2_0:3 ; ///< + UINT32 RxVioLvl:2 ; ///< + UINT32 Reserved_31_5:27; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_071F_STRUCT; + + + +// **** D18F2x09C_x0D0F_0F02 Register Definition **** +// Address +#define D18F2x09C_x0D0F_0F02_ADDRESS 0xd0f0f02 + +// Type +#define D18F2x09C_x0D0F_0F02_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0F02_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_0F02_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_0F02_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_0F02_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_0F02_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_0F02_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_0F02_Reserved_14_12_OFFSET 12 +#define D18F2x09C_x0D0F_0F02_Reserved_14_12_WIDTH 3 +#define D18F2x09C_x0D0F_0F02_Reserved_14_12_MASK 0x7000 +#define D18F2x09C_x0D0F_0F02_ValidTxAndPre_OFFSET 15 +#define D18F2x09C_x0D0F_0F02_ValidTxAndPre_WIDTH 1 +#define D18F2x09C_x0D0F_0F02_ValidTxAndPre_MASK 0x8000 +#define D18F2x09C_x0D0F_0F02_Reserved_31_16_OFFSET 16 +#define D18F2x09C_x0D0F_0F02_Reserved_31_16_WIDTH 16 +#define D18F2x09C_x0D0F_0F02_Reserved_31_16_MASK 0xffff0000 + +/// D18F2x09C_x0D0F_0F02 +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_14_12:3 ; ///< + UINT32 ValidTxAndPre:1 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0F02_STRUCT; + +// **** D18F2x09C_x0D0F_0F06 Register Definition **** +// Address +#define D18F2x09C_x0D0F_0F06_ADDRESS 0xd0f0f06 + +// Type +#define D18F2x09C_x0D0F_0F06_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0F06_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_0F06_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_0F06_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_0F06_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_0F06_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_0F06_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_0F06_Reserved_31_12_OFFSET 12 +#define D18F2x09C_x0D0F_0F06_Reserved_31_12_WIDTH 20 +#define D18F2x09C_x0D0F_0F06_Reserved_31_12_MASK 0xfffff000 + +/// D18F2x09C_x0D0F_0F06 +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0F06_STRUCT; + +// **** D18F2x09C_x0D0F_0F0A Register Definition **** +// Address +#define D18F2x09C_x0D0F_0F0A_ADDRESS 0xd0f0f0a + +// Type +#define D18F2x09C_x0D0F_0F0A_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0F0A_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_0F0A_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_0F0A_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_0F0A_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_0F0A_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_0F0A_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_0F0A_Reserved_31_12_OFFSET 12 +#define D18F2x09C_x0D0F_0F0A_Reserved_31_12_WIDTH 20 +#define D18F2x09C_x0D0F_0F0A_Reserved_31_12_MASK 0xfffff000 + +/// D18F2x09C_x0D0F_0F0A +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0F0A_STRUCT; + +// **** D18F2x09C_x0D0F_0F0F Register Definition **** +// Address +#define D18F2x09C_x0D0F_0F0F_ADDRESS 0xd0f0f0f + +// Type +#define D18F2x09C_x0D0F_0F0F_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0F0F_Reserved_11_0_OFFSET 0 +#define D18F2x09C_x0D0F_0F0F_Reserved_11_0_WIDTH 12 +#define D18F2x09C_x0D0F_0F0F_Reserved_11_0_MASK 0xfff +#define D18F2x09C_x0D0F_0F0F_AlwaysEnDllClks_OFFSET 12 +#define D18F2x09C_x0D0F_0F0F_AlwaysEnDllClks_WIDTH 3 +#define D18F2x09C_x0D0F_0F0F_AlwaysEnDllClks_MASK 0x7000 +#define D18F2x09C_x0D0F_0F0F_Reserved_31_15_OFFSET 15 +#define D18F2x09C_x0D0F_0F0F_Reserved_31_15_WIDTH 17 +#define D18F2x09C_x0D0F_0F0F_Reserved_31_15_MASK 0xffff8000 + +/// D18F2x09C_x0D0F_0F0F +typedef union { + struct { ///< + UINT32 Reserved_11_0:12; ///< + UINT32 AlwaysEnDllClks:3 ; ///< + UINT32 Reserved_31_15:17; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0F0F_STRUCT; + +// **** D18F2x09C_x0D0F_0F10 Register Definition **** +// Address +#define D18F2x09C_x0D0F_0F10_ADDRESS 0xd0f0f10 + +// Type +#define D18F2x09C_x0D0F_0F10_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0F10_Reserved_11_0_OFFSET 0 +#define D18F2x09C_x0D0F_0F10_Reserved_11_0_WIDTH 12 +#define D18F2x09C_x0D0F_0F10_Reserved_11_0_MASK 0xfff +#define D18F2x09C_x0D0F_0F10_EnRxPadStandby_OFFSET 12 +#define D18F2x09C_x0D0F_0F10_EnRxPadStandby_WIDTH 1 +#define D18F2x09C_x0D0F_0F10_EnRxPadStandby_MASK 0x1000 +#define D18F2x09C_x0D0F_0F10_Reserved_31_13_OFFSET 13 +#define D18F2x09C_x0D0F_0F10_Reserved_31_13_WIDTH 19 +#define D18F2x09C_x0D0F_0F10_Reserved_31_13_MASK 0xffffe000 + +/// D18F2x09C_x0D0F_0F10 +typedef union { + struct { ///< + UINT32 Reserved_11_0:12; ///< + UINT32 EnRxPadStandby:1 ; ///< + UINT32 Reserved_31_13:19; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0F10_STRUCT; + +// **** D18F2x09C_x0D0F_0F13 Register Definition **** +// Address +#define D18F2x09C_x0D0F_0F13_ADDRESS 0xd0f0f13 + +// Type +#define D18F2x09C_x0D0F_0F13_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0F13_DllDisEarlyL_OFFSET 0 +#define D18F2x09C_x0D0F_0F13_DllDisEarlyL_WIDTH 1 +#define D18F2x09C_x0D0F_0F13_DllDisEarlyL_MASK 0x1 +#define D18F2x09C_x0D0F_0F13_DllDisEarlyU_OFFSET 1 +#define D18F2x09C_x0D0F_0F13_DllDisEarlyU_WIDTH 1 +#define D18F2x09C_x0D0F_0F13_DllDisEarlyU_MASK 0x2 +#define D18F2x09C_x0D0F_0F13_Reserved_6_2_OFFSET 2 +#define D18F2x09C_x0D0F_0F13_Reserved_6_2_WIDTH 5 +#define D18F2x09C_x0D0F_0F13_Reserved_6_2_MASK 0x7c +#define D18F2x09C_x0D0F_0F13_RxDqsUDllPowerDown_OFFSET 7 +#define D18F2x09C_x0D0F_0F13_RxDqsUDllPowerDown_WIDTH 1 +#define D18F2x09C_x0D0F_0F13_RxDqsUDllPowerDown_MASK 0x80 +#define D18F2x09C_x0D0F_0F13_Reserved_13_8_OFFSET 8 +#define D18F2x09C_x0D0F_0F13_Reserved_13_8_WIDTH 6 +#define D18F2x09C_x0D0F_0F13_Reserved_13_8_MASK 0x3f00 +#define D18F2x09C_x0D0F_0F13_ProcOdtAdv_OFFSET 14 +#define D18F2x09C_x0D0F_0F13_ProcOdtAdv_WIDTH 1 +#define D18F2x09C_x0D0F_0F13_ProcOdtAdv_MASK 0x4000 +#define D18F2x09C_x0D0F_0F13_Reserved_31_15_OFFSET 15 +#define D18F2x09C_x0D0F_0F13_Reserved_31_15_WIDTH 17 +#define D18F2x09C_x0D0F_0F13_Reserved_31_15_MASK 0xffff8000 + +/// D18F2x09C_x0D0F_0F13 +typedef union { + struct { ///< + UINT32 DllDisEarlyL:1 ; ///< + UINT32 DllDisEarlyU:1 ; ///< + UINT32 Reserved_6_2:5 ; ///< + UINT32 RxDqsUDllPowerDown:1 ; ///< + UINT32 Reserved_13_8:6 ; ///< + UINT32 ProcOdtAdv:1 ; ///< + UINT32 Reserved_31_15:17; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0F13_STRUCT; + +// **** D18F2x09C_x0D0F_0F1F Register Definition **** +// Address +#define D18F2x09C_x0D0F_0F1F_ADDRESS 0xd0f0f1f + +// Type +#define D18F2x09C_x0D0F_0F1F_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_0F1F_Reserved_2_0_OFFSET 0 +#define D18F2x09C_x0D0F_0F1F_Reserved_2_0_WIDTH 3 +#define D18F2x09C_x0D0F_0F1F_Reserved_2_0_MASK 0x7 +#define D18F2x09C_x0D0F_0F1F_RxVioLvl_OFFSET 3 +#define D18F2x09C_x0D0F_0F1F_RxVioLvl_WIDTH 2 +#define D18F2x09C_x0D0F_0F1F_RxVioLvl_MASK 0x18 +#define D18F2x09C_x0D0F_0F1F_Reserved_31_5_OFFSET 5 +#define D18F2x09C_x0D0F_0F1F_Reserved_31_5_WIDTH 27 +#define D18F2x09C_x0D0F_0F1F_Reserved_31_5_MASK 0xffffffe0 + +/// D18F2x09C_x0D0F_0F1F +typedef union { + struct { ///< + UINT32 Reserved_2_0:3 ; ///< + UINT32 RxVioLvl:2 ; ///< + UINT32 Reserved_31_5:27; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_0F1F_STRUCT; + + + +// **** D18F2x09C_x0D0F_2002 Register Definition **** +// Address +#define D18F2x09C_x0D0F_2002_ADDRESS 0xd0f2002 + +// Type +#define D18F2x09C_x0D0F_2002_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_2002_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_2002_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_2002_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_2002_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_2002_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_2002_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_2002_Reserved_14_12_OFFSET 12 +#define D18F2x09C_x0D0F_2002_Reserved_14_12_WIDTH 3 +#define D18F2x09C_x0D0F_2002_Reserved_14_12_MASK 0x7000 +#define D18F2x09C_x0D0F_2002_ValidTxAndPre_OFFSET 15 +#define D18F2x09C_x0D0F_2002_ValidTxAndPre_WIDTH 1 +#define D18F2x09C_x0D0F_2002_ValidTxAndPre_MASK 0x8000 +#define D18F2x09C_x0D0F_2002_Reserved_31_16_OFFSET 16 +#define D18F2x09C_x0D0F_2002_Reserved_31_16_WIDTH 16 +#define D18F2x09C_x0D0F_2002_Reserved_31_16_MASK 0xffff0000 + +/// D18F2x09C_x0D0F_2002 +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_14_12:3 ; ///< + UINT32 ValidTxAndPre:1 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_2002_STRUCT; + +// **** D18F2x09C_x0D0F_201F Register Definition **** +// Address +#define D18F2x09C_x0D0F_201F_ADDRESS 0xd0f201f + +// Type +#define D18F2x09C_x0D0F_201F_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_201F_Reserved_2_0_OFFSET 0 +#define D18F2x09C_x0D0F_201F_Reserved_2_0_WIDTH 3 +#define D18F2x09C_x0D0F_201F_Reserved_2_0_MASK 0x7 +#define D18F2x09C_x0D0F_201F_RxVioLvl_OFFSET 3 +#define D18F2x09C_x0D0F_201F_RxVioLvl_WIDTH 2 +#define D18F2x09C_x0D0F_201F_RxVioLvl_MASK 0x18 +#define D18F2x09C_x0D0F_201F_Reserved_31_5_OFFSET 5 +#define D18F2x09C_x0D0F_201F_Reserved_31_5_WIDTH 27 +#define D18F2x09C_x0D0F_201F_Reserved_31_5_MASK 0xffffffe0 + +/// D18F2x09C_x0D0F_201F +typedef union { + struct { ///< + UINT32 Reserved_2_0:3 ; ///< + UINT32 RxVioLvl:2 ; ///< + UINT32 Reserved_31_5:27; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_201F_STRUCT; + + +// **** D18F2x09C_x0D0F_2030 Register Definition **** +// Address +#define D18F2x09C_x0D0F_2030_ADDRESS 0xd0f2030 + +// Type +#define D18F2x09C_x0D0F_2030_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_2030_Reserved_3_0_OFFSET 0 +#define D18F2x09C_x0D0F_2030_Reserved_3_0_WIDTH 4 +#define D18F2x09C_x0D0F_2030_Reserved_3_0_MASK 0xf +#define D18F2x09C_x0D0F_2030_PwrDn_OFFSET 4 +#define D18F2x09C_x0D0F_2030_PwrDn_WIDTH 1 +#define D18F2x09C_x0D0F_2030_PwrDn_MASK 0x10 +#define D18F2x09C_x0D0F_2030_Reserved_31_5_OFFSET 5 +#define D18F2x09C_x0D0F_2030_Reserved_31_5_WIDTH 27 +#define D18F2x09C_x0D0F_2030_Reserved_31_5_MASK 0xffffffe0 + +/// D18F2x09C_x0D0F_2030 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 PwrDn:1 ; ///< + UINT32 Reserved_31_5:27; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_2030_STRUCT; + + +// **** D18F2x09C_x0D0F_2102 Register Definition **** +// Address +#define D18F2x09C_x0D0F_2102_ADDRESS 0xd0f2102 + +// Type +#define D18F2x09C_x0D0F_2102_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_2102_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_2102_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_2102_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_2102_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_2102_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_2102_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_2102_Reserved_14_12_OFFSET 12 +#define D18F2x09C_x0D0F_2102_Reserved_14_12_WIDTH 3 +#define D18F2x09C_x0D0F_2102_Reserved_14_12_MASK 0x7000 +#define D18F2x09C_x0D0F_2102_ValidTxAndPre_OFFSET 15 +#define D18F2x09C_x0D0F_2102_ValidTxAndPre_WIDTH 1 +#define D18F2x09C_x0D0F_2102_ValidTxAndPre_MASK 0x8000 +#define D18F2x09C_x0D0F_2102_Reserved_31_16_OFFSET 16 +#define D18F2x09C_x0D0F_2102_Reserved_31_16_WIDTH 16 +#define D18F2x09C_x0D0F_2102_Reserved_31_16_MASK 0xffff0000 + +/// D18F2x09C_x0D0F_2102 +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_14_12:3 ; ///< + UINT32 ValidTxAndPre:1 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_2102_STRUCT; + +// **** D18F2x09C_x0D0F_211F Register Definition **** +// Address +#define D18F2x09C_x0D0F_211F_ADDRESS 0xd0f211f + +// Type +#define D18F2x09C_x0D0F_211F_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_211F_Reserved_2_0_OFFSET 0 +#define D18F2x09C_x0D0F_211F_Reserved_2_0_WIDTH 3 +#define D18F2x09C_x0D0F_211F_Reserved_2_0_MASK 0x7 +#define D18F2x09C_x0D0F_211F_RxVioLvl_OFFSET 3 +#define D18F2x09C_x0D0F_211F_RxVioLvl_WIDTH 2 +#define D18F2x09C_x0D0F_211F_RxVioLvl_MASK 0x18 +#define D18F2x09C_x0D0F_211F_Reserved_31_5_OFFSET 5 +#define D18F2x09C_x0D0F_211F_Reserved_31_5_WIDTH 27 +#define D18F2x09C_x0D0F_211F_Reserved_31_5_MASK 0xffffffe0 + +/// D18F2x09C_x0D0F_211F +typedef union { + struct { ///< + UINT32 Reserved_2_0:3 ; ///< + UINT32 RxVioLvl:2 ; ///< + UINT32 Reserved_31_5:27; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_211F_STRUCT; + + +// **** D18F2x09C_x0D0F_2130 Register Definition **** +// Address +#define D18F2x09C_x0D0F_2130_ADDRESS 0xd0f2130 + +// Type +#define D18F2x09C_x0D0F_2130_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_2130_Reserved_3_0_OFFSET 0 +#define D18F2x09C_x0D0F_2130_Reserved_3_0_WIDTH 4 +#define D18F2x09C_x0D0F_2130_Reserved_3_0_MASK 0xf +#define D18F2x09C_x0D0F_2130_PwrDn_OFFSET 4 +#define D18F2x09C_x0D0F_2130_PwrDn_WIDTH 1 +#define D18F2x09C_x0D0F_2130_PwrDn_MASK 0x10 +#define D18F2x09C_x0D0F_2130_Reserved_31_5_OFFSET 5 +#define D18F2x09C_x0D0F_2130_Reserved_31_5_WIDTH 27 +#define D18F2x09C_x0D0F_2130_Reserved_31_5_MASK 0xffffffe0 + +/// D18F2x09C_x0D0F_2130 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 PwrDn:1 ; ///< + UINT32 Reserved_31_5:27; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_2130_STRUCT; + +// Field Data +#define D18F2x09C_x0D0F_4009_Reserved_1_0_OFFSET 0 +#define D18F2x09C_x0D0F_4009_Reserved_1_0_WIDTH 2 +#define D18F2x09C_x0D0F_4009_Reserved_1_0_MASK 0x3 +#define D18F2x09C_x0D0F_4009_ComparatorAdjust_OFFSET 2 +#define D18F2x09C_x0D0F_4009_ComparatorAdjust_WIDTH 2 +#define D18F2x09C_x0D0F_4009_ComparatorAdjust_MASK 0xc +#define D18F2x09C_x0D0F_4009_Reserved_13_4_OFFSET 4 +#define D18F2x09C_x0D0F_4009_Reserved_13_4_WIDTH 10 +#define D18F2x09C_x0D0F_4009_Reserved_13_4_MASK 0x3ff0 +#define D18F2x09C_x0D0F_4009_CmpVioLvl_OFFSET 14 +#define D18F2x09C_x0D0F_4009_CmpVioLvl_WIDTH 2 +#define D18F2x09C_x0D0F_4009_CmpVioLvl_MASK 0xc000 +#define D18F2x09C_x0D0F_4009_Reserved_31_16_OFFSET 16 +#define D18F2x09C_x0D0F_4009_Reserved_31_16_WIDTH 16 +#define D18F2x09C_x0D0F_4009_Reserved_31_16_MASK 0xffff0000 + +/// D18F2x09C_x0D0F_4009 +typedef union { + struct { ///< + UINT32 Reserved_1_0:2 ; ///< + UINT32 ComparatorAdjust:2 ; ///< + UINT32 Reserved_13_4:10; ///< + UINT32 CmpVioLvl:2 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_4009_STRUCT; + +// **** D18F2x09C_x0D0F_8002 Register Definition **** +// Address +#define D18F2x09C_x0D0F_8002_ADDRESS 0xd0f8002 + +// Type +#define D18F2x09C_x0D0F_8002_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_8002_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_8002_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_8002_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_8002_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_8002_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_8002_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_8002_Reserved_14_12_OFFSET 12 +#define D18F2x09C_x0D0F_8002_Reserved_14_12_WIDTH 3 +#define D18F2x09C_x0D0F_8002_Reserved_14_12_MASK 0x7000 +#define D18F2x09C_x0D0F_8002_ValidTxAndPre_OFFSET 15 +#define D18F2x09C_x0D0F_8002_ValidTxAndPre_WIDTH 1 +#define D18F2x09C_x0D0F_8002_ValidTxAndPre_MASK 0x8000 +#define D18F2x09C_x0D0F_8002_Reserved_31_16_OFFSET 16 +#define D18F2x09C_x0D0F_8002_Reserved_31_16_WIDTH 16 +#define D18F2x09C_x0D0F_8002_Reserved_31_16_MASK 0xffff0000 + +/// D18F2x09C_x0D0F_8002 +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_14_12:3 ; ///< + UINT32 ValidTxAndPre:1 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_8002_STRUCT; + +// **** D18F2x09C_x0D0F_8006 Register Definition **** +// Address +#define D18F2x09C_x0D0F_8006_ADDRESS 0xd0f8006 + +// Type +#define D18F2x09C_x0D0F_8006_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_8006_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_8006_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_8006_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_8006_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_8006_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_8006_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_8006_Reserved_31_12_OFFSET 12 +#define D18F2x09C_x0D0F_8006_Reserved_31_12_WIDTH 20 +#define D18F2x09C_x0D0F_8006_Reserved_31_12_MASK 0xfffff000 + +/// D18F2x09C_x0D0F_8006 +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_8006_STRUCT; + +// **** D18F2x09C_x0D0F_800A Register Definition **** +// Address +#define D18F2x09C_x0D0F_800A_ADDRESS 0xd0f800a + +// Type +#define D18F2x09C_x0D0F_800A_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_800A_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_800A_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_800A_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_800A_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_800A_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_800A_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_800A_Reserved_31_12_OFFSET 12 +#define D18F2x09C_x0D0F_800A_Reserved_31_12_WIDTH 20 +#define D18F2x09C_x0D0F_800A_Reserved_31_12_MASK 0xfffff000 + +/// D18F2x09C_x0D0F_800A +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_800A_STRUCT; + + + +// **** D18F2x09C_x0D0F_8102 Register Definition **** +// Address +#define D18F2x09C_x0D0F_8102_ADDRESS 0xd0f8102 + +// Type +#define D18F2x09C_x0D0F_8102_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_8102_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_8102_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_8102_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_8102_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_8102_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_8102_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_8102_Reserved_14_12_OFFSET 12 +#define D18F2x09C_x0D0F_8102_Reserved_14_12_WIDTH 3 +#define D18F2x09C_x0D0F_8102_Reserved_14_12_MASK 0x7000 +#define D18F2x09C_x0D0F_8102_ValidTxAndPre_OFFSET 15 +#define D18F2x09C_x0D0F_8102_ValidTxAndPre_WIDTH 1 +#define D18F2x09C_x0D0F_8102_ValidTxAndPre_MASK 0x8000 +#define D18F2x09C_x0D0F_8102_Reserved_31_16_OFFSET 16 +#define D18F2x09C_x0D0F_8102_Reserved_31_16_WIDTH 16 +#define D18F2x09C_x0D0F_8102_Reserved_31_16_MASK 0xffff0000 + +/// D18F2x09C_x0D0F_8102 +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_14_12:3 ; ///< + UINT32 ValidTxAndPre:1 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_8102_STRUCT; + +// **** D18F2x09C_x0D0F_8106 Register Definition **** +// Address +#define D18F2x09C_x0D0F_8106_ADDRESS 0xd0f8106 + +// Type +#define D18F2x09C_x0D0F_8106_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_8106_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_8106_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_8106_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_8106_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_8106_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_8106_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_8106_Reserved_31_12_OFFSET 12 +#define D18F2x09C_x0D0F_8106_Reserved_31_12_WIDTH 20 +#define D18F2x09C_x0D0F_8106_Reserved_31_12_MASK 0xfffff000 + +/// D18F2x09C_x0D0F_8106 +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_8106_STRUCT; + +// **** D18F2x09C_x0D0F_810A Register Definition **** +// Address +#define D18F2x09C_x0D0F_810A_ADDRESS 0xd0f810a + +// Type +#define D18F2x09C_x0D0F_810A_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_810A_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_810A_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_810A_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_810A_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_810A_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_810A_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_810A_Reserved_31_12_OFFSET 12 +#define D18F2x09C_x0D0F_810A_Reserved_31_12_WIDTH 20 +#define D18F2x09C_x0D0F_810A_Reserved_31_12_MASK 0xfffff000 + +/// D18F2x09C_x0D0F_810A +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_810A_STRUCT; + + + + +// **** D18F2x09C_x0D0F_C000 Register Definition **** +// Address +#define D18F2x09C_x0D0F_C000_ADDRESS 0xd0fc000 + +// Type +#define D18F2x09C_x0D0F_C000_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_C000_Reserved_7_0_OFFSET 0 +#define D18F2x09C_x0D0F_C000_Reserved_7_0_WIDTH 8 +#define D18F2x09C_x0D0F_C000_Reserved_7_0_MASK 0xff +#define D18F2x09C_x0D0F_C000_LowPowerDrvStrengthEn_OFFSET 8 +#define D18F2x09C_x0D0F_C000_LowPowerDrvStrengthEn_WIDTH 1 +#define D18F2x09C_x0D0F_C000_LowPowerDrvStrengthEn_MASK 0x100 +#define D18F2x09C_x0D0F_C000_Reserved_31_9_OFFSET 9 +#define D18F2x09C_x0D0F_C000_Reserved_31_9_WIDTH 23 +#define D18F2x09C_x0D0F_C000_Reserved_31_9_MASK 0xfffffe00 + +/// D18F2x09C_x0D0F_C000 +typedef union { + struct { ///< + UINT32 Reserved_7_0:8 ; ///< + UINT32 LowPowerDrvStrengthEn:1 ; ///< + UINT32 Reserved_31_9:23; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_C000_STRUCT; + +// **** D18F2x09C_x0D0F_C002 Register Definition **** +// Address +#define D18F2x09C_x0D0F_C002_ADDRESS 0xd0fc002 + +// Type +#define D18F2x09C_x0D0F_C002_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_C002_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_C002_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_C002_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_C002_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_C002_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_C002_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_C002_Reserved_14_12_OFFSET 12 +#define D18F2x09C_x0D0F_C002_Reserved_14_12_WIDTH 3 +#define D18F2x09C_x0D0F_C002_Reserved_14_12_MASK 0x7000 +#define D18F2x09C_x0D0F_C002_ValidTxAndPre_OFFSET 15 +#define D18F2x09C_x0D0F_C002_ValidTxAndPre_WIDTH 1 +#define D18F2x09C_x0D0F_C002_ValidTxAndPre_MASK 0x8000 +#define D18F2x09C_x0D0F_C002_Reserved_31_16_OFFSET 16 +#define D18F2x09C_x0D0F_C002_Reserved_31_16_WIDTH 16 +#define D18F2x09C_x0D0F_C002_Reserved_31_16_MASK 0xffff0000 + +/// D18F2x09C_x0D0F_C002 +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_14_12:3 ; ///< + UINT32 ValidTxAndPre:1 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_C002_STRUCT; + +// **** D18F2x09C_x0D0F_C006 Register Definition **** +// Address +#define D18F2x09C_x0D0F_C006_ADDRESS 0xd0fc006 + +// Type +#define D18F2x09C_x0D0F_C006_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_C006_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_C006_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_C006_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_C006_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_C006_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_C006_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_C006_Reserved_31_12_OFFSET 12 +#define D18F2x09C_x0D0F_C006_Reserved_31_12_WIDTH 20 +#define D18F2x09C_x0D0F_C006_Reserved_31_12_MASK 0xfffff000 + +/// D18F2x09C_x0D0F_C006 +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_C006_STRUCT; + +// **** D18F2x09C_x0D0F_C00A Register Definition **** +// Address +#define D18F2x09C_x0D0F_C00A_ADDRESS 0xd0fc00a + +// Type +#define D18F2x09C_x0D0F_C00A_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_C00A_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_C00A_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_C00A_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_C00A_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_C00A_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_C00A_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_C00A_Reserved_31_12_OFFSET 12 +#define D18F2x09C_x0D0F_C00A_Reserved_31_12_WIDTH 20 +#define D18F2x09C_x0D0F_C00A_Reserved_31_12_MASK 0xfffff000 + +/// D18F2x09C_x0D0F_C00A +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_C00A_STRUCT; + +// **** D18F2x09C_x0D0F_C00E Register Definition **** +// Address +#define D18F2x09C_x0D0F_C00E_ADDRESS 0xd0fc00e + +// Type +#define D18F2x09C_x0D0F_C00E_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_C00E_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_C00E_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_C00E_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_C00E_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_C00E_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_C00E_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_C00E_Reserved_31_12_OFFSET 12 +#define D18F2x09C_x0D0F_C00E_Reserved_31_12_WIDTH 20 +#define D18F2x09C_x0D0F_C00E_Reserved_31_12_MASK 0xfffff000 + +/// D18F2x09C_x0D0F_C00E +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_C00E_STRUCT; + +// **** D18F2x09C_x0D0F_C012 Register Definition **** +// Address +#define D18F2x09C_x0D0F_C012_ADDRESS 0xd0fc012 + +// Type +#define D18F2x09C_x0D0F_C012_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_C012_TxPreN_OFFSET 0 +#define D18F2x09C_x0D0F_C012_TxPreN_WIDTH 6 +#define D18F2x09C_x0D0F_C012_TxPreN_MASK 0x3f +#define D18F2x09C_x0D0F_C012_TxPreP_OFFSET 6 +#define D18F2x09C_x0D0F_C012_TxPreP_WIDTH 6 +#define D18F2x09C_x0D0F_C012_TxPreP_MASK 0xfc0 +#define D18F2x09C_x0D0F_C012_Reserved_31_12_OFFSET 12 +#define D18F2x09C_x0D0F_C012_Reserved_31_12_WIDTH 20 +#define D18F2x09C_x0D0F_C012_Reserved_31_12_MASK 0xfffff000 + +/// D18F2x09C_x0D0F_C012 +typedef union { + struct { ///< + UINT32 TxPreN:6 ; ///< + UINT32 TxPreP:6 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_C012_STRUCT; + + + + +// **** D18F2x09C_x0D0F_E006 Register Definition **** +// Address +#define D18F2x09C_x0D0F_E006_ADDRESS 0xd0fe006 + +// Type +#define D18F2x09C_x0D0F_E006_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_E006_PllLockTime_OFFSET 0 +#define D18F2x09C_x0D0F_E006_PllLockTime_WIDTH 16 +#define D18F2x09C_x0D0F_E006_PllLockTime_MASK 0xffff +#define D18F2x09C_x0D0F_E006_Reserved_31_16_OFFSET 16 +#define D18F2x09C_x0D0F_E006_Reserved_31_16_WIDTH 16 +#define D18F2x09C_x0D0F_E006_Reserved_31_16_MASK 0xffff0000 + +/// D18F2x09C_x0D0F_E006 +typedef union { + struct { ///< + UINT32 PllLockTime:16; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_E006_STRUCT; + + +// **** D18F2x09C_x0D0F_E013 Register Definition **** +// Address +#define D18F2x09C_x0D0F_E013_ADDRESS 0xd0fe013 + +// Type +#define D18F2x09C_x0D0F_E013_TYPE TYPE_D18F2x09C +// Field Data +#define D18F2x09C_x0D0F_E013_PllRegWaitTime_OFFSET 0 +#define D18F2x09C_x0D0F_E013_PllRegWaitTime_WIDTH 16 +#define D18F2x09C_x0D0F_E013_PllRegWaitTime_MASK 0xffff +#define D18F2x09C_x0D0F_E013_Reserved_31_16_OFFSET 16 +#define D18F2x09C_x0D0F_E013_Reserved_31_16_WIDTH 16 +#define D18F2x09C_x0D0F_E013_Reserved_31_16_MASK 0xffff0000 + +/// D18F2x09C_x0D0F_E013 +typedef union { + struct { ///< + UINT32 PllRegWaitTime:16; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0F_E013_STRUCT; + + +// **** DxF0xE4_x02 Register Definition **** +// Address +#define DxF0xE4_x02_ADDRESS 0x2 + +// Type +#define DxF0xE4_x02_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_x02_Reserved_14_0_OFFSET 0 +#define DxF0xE4_x02_Reserved_14_0_WIDTH 15 +#define DxF0xE4_x02_Reserved_14_0_MASK 0x7fff +#define DxF0xE4_x02_RegsLcAllowTxL1Control_OFFSET 15 +#define DxF0xE4_x02_RegsLcAllowTxL1Control_WIDTH 1 +#define DxF0xE4_x02_RegsLcAllowTxL1Control_MASK 0x8000 +#define DxF0xE4_x02_Reserved_31_16_OFFSET 16 +#define DxF0xE4_x02_Reserved_31_16_WIDTH 16 +#define DxF0xE4_x02_Reserved_31_16_MASK 0xffff0000 + +/// DxF0xE4_x02 +typedef union { + struct { ///< + UINT32 Reserved_14_0:15; ///< + UINT32 RegsLcAllowTxL1Control:1 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_x02_STRUCT; + +// **** DxF0xE4_x20 Register Definition **** +// Address +#define DxF0xE4_x20_ADDRESS 0x20 + +// Type +#define DxF0xE4_x20_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_x20_Reserved_14_0_OFFSET 0 +#define DxF0xE4_x20_Reserved_14_0_WIDTH 15 +#define DxF0xE4_x20_Reserved_14_0_MASK 0x7fff +#define DxF0xE4_x20_TxFlushTlpDis_OFFSET 15 +#define DxF0xE4_x20_TxFlushTlpDis_WIDTH 1 +#define DxF0xE4_x20_TxFlushTlpDis_MASK 0x8000 +#define DxF0xE4_x20_Reserved_31_16_OFFSET 16 +#define DxF0xE4_x20_Reserved_31_16_WIDTH 16 +#define DxF0xE4_x20_Reserved_31_16_MASK 0xffff0000 + +/// DxF0xE4_x20 +typedef union { + struct { ///< + UINT32 Reserved_14_0:15; ///< + UINT32 TxFlushTlpDis:1 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_x20_STRUCT; + +// **** DxF0xE4_x50 Register Definition **** +// Address +#define DxF0xE4_x50_ADDRESS 0x50 + +// Type +#define DxF0xE4_x50_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_x50_PortLaneReversal_OFFSET 0 +#define DxF0xE4_x50_PortLaneReversal_WIDTH 1 +#define DxF0xE4_x50_PortLaneReversal_MASK 0x1 +#define DxF0xE4_x50_PhyLinkWidth_OFFSET 1 +#define DxF0xE4_x50_PhyLinkWidth_WIDTH 6 +#define DxF0xE4_x50_PhyLinkWidth_MASK 0x7e +#define DxF0xE4_x50_Reserved_31_7_OFFSET 7 +#define DxF0xE4_x50_Reserved_31_7_WIDTH 25 +#define DxF0xE4_x50_Reserved_31_7_MASK 0xffffff80 + +/// DxF0xE4_x50 +typedef union { + struct { ///< + UINT32 PortLaneReversal:1 ; ///< + UINT32 PhyLinkWidth:6 ; ///< + UINT32 Reserved_31_7:25; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_x50_STRUCT; + +// **** DxF0xE4_x70 Register Definition **** +// Address +#define DxF0xE4_x70_ADDRESS 0x70 + +// Type +#define DxF0xE4_x70_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_x70_Reserved_15_0_OFFSET 0 +#define DxF0xE4_x70_Reserved_15_0_WIDTH 16 +#define DxF0xE4_x70_Reserved_15_0_MASK 0xffff +#define DxF0xE4_x70_RxRcbCplTimeout_OFFSET 16 +#define DxF0xE4_x70_RxRcbCplTimeout_WIDTH 3 +#define DxF0xE4_x70_RxRcbCplTimeout_MASK 0x70000 +#define DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET 19 +#define DxF0xE4_x70_RxRcbCplTimeoutMode_WIDTH 1 +#define DxF0xE4_x70_RxRcbCplTimeoutMode_MASK 0x80000 +#define DxF0xE4_x70_Reserved_31_20_OFFSET 20 +#define DxF0xE4_x70_Reserved_31_20_WIDTH 12 +#define DxF0xE4_x70_Reserved_31_20_MASK 0xfff00000 + +/// DxF0xE4_x70 +typedef union { + struct { ///< + UINT32 Reserved_15_0:16; ///< + UINT32 RxRcbCplTimeout:3 ; ///< + UINT32 RxRcbCplTimeoutMode:1 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_x70_STRUCT; + +// **** DxF0xE4_xA0 Register Definition **** +// Address +#define DxF0xE4_xA0_ADDRESS 0xa0 + +// Type +#define DxF0xE4_xA0_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_xA0_Reserved_3_0_OFFSET 0 +#define DxF0xE4_xA0_Reserved_3_0_WIDTH 4 +#define DxF0xE4_xA0_Reserved_3_0_MASK 0xf +#define DxF0xE4_xA0_Lc16xClearTxPipe_OFFSET 4 +#define DxF0xE4_xA0_Lc16xClearTxPipe_WIDTH 4 +#define DxF0xE4_xA0_Lc16xClearTxPipe_MASK 0xf0 +#define DxF0xE4_xA0_LcL0sInactivity_OFFSET 8 +#define DxF0xE4_xA0_LcL0sInactivity_WIDTH 4 +#define DxF0xE4_xA0_LcL0sInactivity_MASK 0xf00 +#define DxF0xE4_xA0_LcL1Inactivity_OFFSET 12 +#define DxF0xE4_xA0_LcL1Inactivity_WIDTH 4 +#define DxF0xE4_xA0_LcL1Inactivity_MASK 0xf000 +#define DxF0xE4_xA0_Reserved_22_16_OFFSET 16 +#define DxF0xE4_xA0_Reserved_22_16_WIDTH 7 +#define DxF0xE4_xA0_Reserved_22_16_MASK 0x7f0000 +#define DxF0xE4_xA0_LcL1ImmediateAck_OFFSET 23 +#define DxF0xE4_xA0_LcL1ImmediateAck_WIDTH 1 +#define DxF0xE4_xA0_LcL1ImmediateAck_MASK 0x800000 +#define DxF0xE4_xA0_Reserved_31_24_OFFSET 24 +#define DxF0xE4_xA0_Reserved_31_24_WIDTH 8 +#define DxF0xE4_xA0_Reserved_31_24_MASK 0xff000000 + +/// DxF0xE4_xA0 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 Lc16xClearTxPipe:4 ; ///< + UINT32 LcL0sInactivity:4 ; ///< + UINT32 LcL1Inactivity:4 ; ///< + UINT32 Reserved_22_16:7 ; ///< + UINT32 LcL1ImmediateAck:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_xA0_STRUCT; + +// **** DxF0xE4_xA1 Register Definition **** +// Address +#define DxF0xE4_xA1_ADDRESS 0xa1 + +// Type +#define DxF0xE4_xA1_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_xA1_Reserved_10_0_OFFSET 0 +#define DxF0xE4_xA1_Reserved_10_0_WIDTH 11 +#define DxF0xE4_xA1_Reserved_10_0_MASK 0x7ff +#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_OFFSET 11 +#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_WIDTH 1 +#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_MASK 0x800 +#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_OFFSET 12 +#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_WIDTH 1 +#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_MASK 0x1000 +#define DxF0xE4_xA1_Reserved_31_13_OFFSET 13 +#define DxF0xE4_xA1_Reserved_31_13_WIDTH 19 +#define DxF0xE4_xA1_Reserved_31_13_MASK 0xffffe000 + +/// DxF0xE4_xA1 +typedef union { + struct { ///< + UINT32 Reserved_10_0:11; ///< + UINT32 LcDontGotoL0sifL1Armed:1 ; ///< + UINT32 LcInitSpdChgWithCsrEn:1 ; ///< + UINT32 Reserved_31_13:19; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_xA1_STRUCT; + +// **** DxF0xE4_xA2 Register Definition **** +// Address +#define DxF0xE4_xA2_ADDRESS 0xa2 + +// Type +#define DxF0xE4_xA2_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_xA2_LcLinkWidth_OFFSET 0 +#define DxF0xE4_xA2_LcLinkWidth_WIDTH 3 +#define DxF0xE4_xA2_LcLinkWidth_MASK 0x7 +#define DxF0xE4_xA2_Reserved_3_3_OFFSET 3 +#define DxF0xE4_xA2_Reserved_3_3_WIDTH 1 +#define DxF0xE4_xA2_Reserved_3_3_MASK 0x8 +#define DxF0xE4_xA2_LcLinkWidthRd_OFFSET 4 +#define DxF0xE4_xA2_LcLinkWidthRd_WIDTH 3 +#define DxF0xE4_xA2_LcLinkWidthRd_MASK 0x70 +#define DxF0xE4_xA2_LcReconfigArcMissingEscape_OFFSET 7 +#define DxF0xE4_xA2_LcReconfigArcMissingEscape_WIDTH 1 +#define DxF0xE4_xA2_LcReconfigArcMissingEscape_MASK 0x80 +#define DxF0xE4_xA2_LcReconfigNow_OFFSET 8 +#define DxF0xE4_xA2_LcReconfigNow_WIDTH 1 +#define DxF0xE4_xA2_LcReconfigNow_MASK 0x100 +#define DxF0xE4_xA2_LcRenegotiationSupport_OFFSET 9 +#define DxF0xE4_xA2_LcRenegotiationSupport_WIDTH 1 +#define DxF0xE4_xA2_LcRenegotiationSupport_MASK 0x200 +#define DxF0xE4_xA2_LcRenegotiateEn_OFFSET 10 +#define DxF0xE4_xA2_LcRenegotiateEn_WIDTH 1 +#define DxF0xE4_xA2_LcRenegotiateEn_MASK 0x400 +#define DxF0xE4_xA2_LcShortReconfigEn_OFFSET 11 +#define DxF0xE4_xA2_LcShortReconfigEn_WIDTH 1 +#define DxF0xE4_xA2_LcShortReconfigEn_MASK 0x800 +#define DxF0xE4_xA2_LcUpconfigureSupport_OFFSET 12 +#define DxF0xE4_xA2_LcUpconfigureSupport_WIDTH 1 +#define DxF0xE4_xA2_LcUpconfigureSupport_MASK 0x1000 +#define DxF0xE4_xA2_LcUpconfigureDis_OFFSET 13 +#define DxF0xE4_xA2_LcUpconfigureDis_WIDTH 1 +#define DxF0xE4_xA2_LcUpconfigureDis_MASK 0x2000 +#define DxF0xE4_xA2_Reserved_19_14_OFFSET 14 +#define DxF0xE4_xA2_Reserved_19_14_WIDTH 6 +#define DxF0xE4_xA2_Reserved_19_14_MASK 0xfc000 +#define DxF0xE4_xA2_LcUpconfigCapable_OFFSET 20 +#define DxF0xE4_xA2_LcUpconfigCapable_WIDTH 1 +#define DxF0xE4_xA2_LcUpconfigCapable_MASK 0x100000 +#define DxF0xE4_xA2_LcDynLanesPwrState_OFFSET 21 +#define DxF0xE4_xA2_LcDynLanesPwrState_WIDTH 2 +#define DxF0xE4_xA2_LcDynLanesPwrState_MASK 0x600000 +#define DxF0xE4_xA2_Reserved_31_23_OFFSET 23 +#define DxF0xE4_xA2_Reserved_31_23_WIDTH 9 +#define DxF0xE4_xA2_Reserved_31_23_MASK 0xff800000 + +/// DxF0xE4_xA2 +typedef union { + struct { ///< + UINT32 LcLinkWidth:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 LcLinkWidthRd:3 ; ///< + UINT32 LcReconfigArcMissingEscape:1 ; ///< + UINT32 LcReconfigNow:1 ; ///< + UINT32 LcRenegotiationSupport:1 ; ///< + UINT32 LcRenegotiateEn:1 ; ///< + UINT32 LcShortReconfigEn:1 ; ///< + UINT32 LcUpconfigureSupport:1 ; ///< + UINT32 LcUpconfigureDis:1 ; ///< + UINT32 Reserved_19_14:6 ; ///< + UINT32 LcUpconfigCapable:1 ; ///< + UINT32 LcDynLanesPwrState:2 ; ///< + UINT32 Reserved_31_23:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_xA2_STRUCT; + +// **** DxF0xE4_xA3 Register Definition **** +// Address +#define DxF0xE4_xA3_ADDRESS 0xa3 + +// Type +#define DxF0xE4_xA3_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_xA3_Reserved_8_0_OFFSET 0 +#define DxF0xE4_xA3_Reserved_8_0_WIDTH 9 +#define DxF0xE4_xA3_Reserved_8_0_MASK 0x1ff +#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_OFFSET 9 +#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_WIDTH 1 +#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_MASK 0x200 +#define DxF0xE4_xA3_Reserved_31_10_OFFSET 10 +#define DxF0xE4_xA3_Reserved_31_10_WIDTH 22 +#define DxF0xE4_xA3_Reserved_31_10_MASK 0xfffffc00 + +/// DxF0xE4_xA3 +typedef union { + struct { ///< + UINT32 Reserved_8_0:9 ; ///< + UINT32 LcXmitFtsBeforeRecovery:1 ; ///< + UINT32 Reserved_31_10:22; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_xA3_STRUCT; + +/// DxF0xE4_xA4 +typedef union { + struct { ///< + UINT32 LcGen2EnStrap:1 ; ///< + UINT32 Reserved_3_1:3 ; ///< + UINT32 LcForceDisSwSpeedChange:1 ; ///< + UINT32 Reserved_6_5:2 ; ///< + UINT32 LcInitiateLinkSpeedChange:1 ; ///< + UINT32 Reserved_9_8:2 ; ///< + UINT32 LcSpeedChangeAttemptFailed:1 ; ///< + UINT32 Reserved_17_11:7 ; ///< + UINT32 LcGoToRecovery:1 ; ///< + UINT32 Reserved_23_19:5 ; ///< + UINT32 LcOtherSideSupportsGen2:1 ; ///< + UINT32 Reserved_28_25:4 ; ///< + UINT32 LcMultUpstreamAutoSpdChngEn:1 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} ex548_STRUCT; + +// **** DxF0xE4_xA5 Register Definition **** +// Address +#define DxF0xE4_xA5_ADDRESS 0xa5 + +// Type +#define DxF0xE4_xA5_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_xA5_LcCurrentState_OFFSET 0 +#define DxF0xE4_xA5_LcCurrentState_WIDTH 6 +#define DxF0xE4_xA5_LcCurrentState_MASK 0x3f +#define DxF0xE4_xA5_Reserved_7_6_OFFSET 6 +#define DxF0xE4_xA5_Reserved_7_6_WIDTH 2 +#define DxF0xE4_xA5_Reserved_7_6_MASK 0xc0 +#define DxF0xE4_xA5_LcPrevState1_OFFSET 8 +#define DxF0xE4_xA5_LcPrevState1_WIDTH 6 +#define DxF0xE4_xA5_LcPrevState1_MASK 0x3f00 +#define DxF0xE4_xA5_Reserved_15_14_OFFSET 14 +#define DxF0xE4_xA5_Reserved_15_14_WIDTH 2 +#define DxF0xE4_xA5_Reserved_15_14_MASK 0xc000 +#define DxF0xE4_xA5_LcPrevState2_OFFSET 16 +#define DxF0xE4_xA5_LcPrevState2_WIDTH 6 +#define DxF0xE4_xA5_LcPrevState2_MASK 0x3f0000 +#define DxF0xE4_xA5_Reserved_23_22_OFFSET 22 +#define DxF0xE4_xA5_Reserved_23_22_WIDTH 2 +#define DxF0xE4_xA5_Reserved_23_22_MASK 0xc00000 +#define DxF0xE4_xA5_LcPrevState3_OFFSET 24 +#define DxF0xE4_xA5_LcPrevState3_WIDTH 6 +#define DxF0xE4_xA5_LcPrevState3_MASK 0x3f000000 +#define DxF0xE4_xA5_Reserved_31_30_OFFSET 30 +#define DxF0xE4_xA5_Reserved_31_30_WIDTH 2 +#define DxF0xE4_xA5_Reserved_31_30_MASK 0xc0000000 + +/// DxF0xE4_xA5 +typedef union { + struct { ///< + UINT32 LcCurrentState:6 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 LcPrevState1:6 ; ///< + UINT32 Reserved_15_14:2 ; ///< + UINT32 LcPrevState2:6 ; ///< + UINT32 Reserved_23_22:2 ; ///< + UINT32 LcPrevState3:6 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_xA5_STRUCT; + +// **** DxF0xE4_xB1 Register Definition **** +// Address +#define DxF0xE4_xB1_ADDRESS 0xb1 + +// Type +#define DxF0xE4_xB1_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_xB1_Reserved_18_0_OFFSET 0 +#define DxF0xE4_xB1_Reserved_18_0_WIDTH 19 +#define DxF0xE4_xB1_Reserved_18_0_MASK 0x7ffff +#define DxF0xE4_xB1_LcDeassertRxEnInL0s_OFFSET 19 +#define DxF0xE4_xB1_LcDeassertRxEnInL0s_WIDTH 1 +#define DxF0xE4_xB1_LcDeassertRxEnInL0s_MASK 0x80000 +#define DxF0xE4_xB1_LcBlockElIdleinL0_OFFSET 20 +#define DxF0xE4_xB1_LcBlockElIdleinL0_WIDTH 1 +#define DxF0xE4_xB1_LcBlockElIdleinL0_MASK 0x100000 +#define DxF0xE4_xB1_Reserved_31_21_OFFSET 21 +#define DxF0xE4_xB1_Reserved_31_21_WIDTH 11 +#define DxF0xE4_xB1_Reserved_31_21_MASK 0xffe00000 + +/// DxF0xE4_xB1 +typedef union { + struct { ///< + UINT32 Reserved_18_0:19; ///< + UINT32 LcDeassertRxEnInL0s:1 ; ///< + UINT32 LcBlockElIdleinL0:1 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_xB1_STRUCT; + +// **** DxF0xE4_xC0 Register Definition **** +// Address +#define DxF0xE4_xC0_ADDRESS 0xc0 + +// Type +#define DxF0xE4_xC0_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_xC0_Reserved_12_0_OFFSET 0 +#define DxF0xE4_xC0_Reserved_12_0_WIDTH 13 +#define DxF0xE4_xC0_Reserved_12_0_MASK 0x1fff +#define DxF0xE4_xC0_StrapForceCompliance_OFFSET 13 +#define DxF0xE4_xC0_StrapForceCompliance_WIDTH 1 +#define DxF0xE4_xC0_StrapForceCompliance_MASK 0x2000 +#define DxF0xE4_xC0_Reserved_14_14_OFFSET 14 +#define DxF0xE4_xC0_Reserved_14_14_WIDTH 1 +#define DxF0xE4_xC0_Reserved_14_14_MASK 0x4000 +#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET 15 +#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_WIDTH 1 +#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK 0x8000 +#define DxF0xE4_xC0_Reserved_31_16_OFFSET 16 +#define DxF0xE4_xC0_Reserved_31_16_WIDTH 16 +#define DxF0xE4_xC0_Reserved_31_16_MASK 0xffff0000 + +/// DxF0xE4_xC0 +typedef union { + struct { ///< + UINT32 Reserved_12_0:13; ///< + UINT32 StrapForceCompliance:1 ; ///< + UINT32 Reserved_14_14:1 ; ///< + UINT32 StrapAutoRcSpeedNegotiationDis:1 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_xC0_STRUCT; + + + +// **** GMMx4D0 Register Definition **** +// Address +#define GMMx4D0_ADDRESS 0x4d0 + +// Type +#define GMMx4D0_TYPE TYPE_GMM +// Field Data +#define GMMx4D0_DispclkDccgGateDisable_OFFSET 0 +#define GMMx4D0_DispclkDccgGateDisable_WIDTH 1 +#define GMMx4D0_DispclkDccgGateDisable_MASK 0x1 +#define GMMx4D0_DispclkRDccgGateDisable_OFFSET 1 +#define GMMx4D0_DispclkRDccgGateDisable_WIDTH 1 +#define GMMx4D0_DispclkRDccgGateDisable_MASK 0x2 +#define GMMx4D0_SclkGateDisable_OFFSET 2 +#define GMMx4D0_SclkGateDisable_WIDTH 1 +#define GMMx4D0_SclkGateDisable_MASK 0x4 +#define GMMx4D0_Reserved_7_3_OFFSET 3 +#define GMMx4D0_Reserved_7_3_WIDTH 5 +#define GMMx4D0_Reserved_7_3_MASK 0xf8 +#define GMMx4D0_SymclkaGateDisable_OFFSET 8 +#define GMMx4D0_SymclkaGateDisable_WIDTH 1 +#define GMMx4D0_SymclkaGateDisable_MASK 0x100 +#define GMMx4D0_SymclkbGateDisable_OFFSET 9 +#define GMMx4D0_SymclkbGateDisable_WIDTH 1 +#define GMMx4D0_SymclkbGateDisable_MASK 0x200 +#define GMMx4D0_Reserved_31_10_OFFSET 10 +#define GMMx4D0_Reserved_31_10_WIDTH 22 +#define GMMx4D0_Reserved_31_10_MASK 0xfffffc00 + +/// GMMx4D0 +typedef union { + struct { ///< + UINT32 DispclkDccgGateDisable:1 ; ///< + UINT32 DispclkRDccgGateDisable:1 ; ///< + UINT32 SclkGateDisable:1 ; ///< + UINT32 Reserved_7_3:5 ; ///< + UINT32 SymclkaGateDisable:1 ; ///< + UINT32 SymclkbGateDisable:1 ; ///< + UINT32 Reserved_31_10:22; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx4D0_STRUCT; + +// **** GMMx770 Register Definition **** +// Address +#define GMMx770_ADDRESS 0x770 + +// Type +#define GMMx770_TYPE TYPE_GMM +// Field Data +#define GMMx770_VoltageChangeReq_OFFSET 0 +#define GMMx770_VoltageChangeReq_WIDTH 1 +#define GMMx770_VoltageChangeReq_MASK 0x1 +#define GMMx770_VoltageLevel_OFFSET 1 +#define GMMx770_VoltageLevel_WIDTH 2 +#define GMMx770_VoltageLevel_MASK 0x6 +#define GMMx770_VoltageChangeEn_OFFSET 3 +#define GMMx770_VoltageChangeEn_WIDTH 1 +#define GMMx770_VoltageChangeEn_MASK 0x8 +#define GMMx770_VoltageForceEn_OFFSET 4 +#define GMMx770_VoltageForceEn_WIDTH 1 +#define GMMx770_VoltageForceEn_MASK 0x10 +#define GMMx770_Reserved_31_5_OFFSET 5 +#define GMMx770_Reserved_31_5_WIDTH 27 +#define GMMx770_Reserved_31_5_MASK 0xffffffe0 + +/// GMMx770 +typedef union { + struct { ///< + UINT32 VoltageChangeReq:1 ; ///< + UINT32 VoltageLevel:2 ; ///< + UINT32 VoltageChangeEn:1 ; ///< + UINT32 VoltageForceEn:1 ; ///< + UINT32 Reserved_31_5:27; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx770_STRUCT; + +// **** GMMx774 Register Definition **** +// Address +#define GMMx774_ADDRESS 0x774 + +// Type +#define GMMx774_TYPE TYPE_GMM +// Field Data +#define GMMx774_VoltageChangeAck_OFFSET 0 +#define GMMx774_VoltageChangeAck_WIDTH 1 +#define GMMx774_VoltageChangeAck_MASK 0x1 +#define GMMx774_CurrentVoltageLevel_OFFSET 1 +#define GMMx774_CurrentVoltageLevel_WIDTH 2 +#define GMMx774_CurrentVoltageLevel_MASK 0x6 +#define GMMx774_Reserved_31_3_OFFSET 3 +#define GMMx774_Reserved_31_3_WIDTH 29 +#define GMMx774_Reserved_31_3_MASK 0xfffffff8 + +/// GMMx774 +typedef union { + struct { ///< + UINT32 VoltageChangeAck:1 ; ///< + UINT32 CurrentVoltageLevel:2 ; ///< + UINT32 Reserved_31_3:29; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx774_STRUCT; + +// **** GMMx15C0 Register Definition **** +// Address +#define GMMx15C0_ADDRESS 0x15c0 + +// Type +#define GMMx15C0_TYPE TYPE_GMM +// Field Data +#define GMMx15C0_OnDly_OFFSET 0 +#define GMMx15C0_OnDly_WIDTH 6 +#define GMMx15C0_OnDly_MASK 0x3f +#define GMMx15C0_OffDly_OFFSET 6 +#define GMMx15C0_OffDly_WIDTH 6 +#define GMMx15C0_OffDly_MASK 0xfc0 +#define GMMx15C0_RdyDly_OFFSET 12 +#define GMMx15C0_RdyDly_WIDTH 6 +#define GMMx15C0_RdyDly_MASK 0x3f000 +#define GMMx15C0_Enable_OFFSET 18 +#define GMMx15C0_Enable_WIDTH 1 +#define GMMx15C0_Enable_MASK 0x40000 +#define GMMx15C0_Reserved_31_19_OFFSET 19 +#define GMMx15C0_Reserved_31_19_WIDTH 13 +#define GMMx15C0_Reserved_31_19_MASK 0xfff80000 + +/// GMMx15C0 +typedef union { + struct { ///< + UINT32 OnDly:6 ; ///< + UINT32 OffDly:6 ; ///< + UINT32 RdyDly:6 ; ///< + UINT32 Enable:1 ; ///< + UINT32 Reserved_31_19:13; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx15C0_STRUCT; + + + + + +// **** GMMx2024 Register Definition **** +// Address +#define GMMx2024_ADDRESS 0x2024 + +// Type +#define GMMx2024_TYPE TYPE_GMM +// Field Data +#define GMMx2024_Base_OFFSET 0 +#define GMMx2024_Base_WIDTH 16 +#define GMMx2024_Base_MASK 0xffff +#define GMMx2024_Top_OFFSET 16 +#define GMMx2024_Top_WIDTH 16 +#define GMMx2024_Top_MASK 0xffff0000 + +/// GMMx2024 +typedef union { + struct { ///< + UINT32 Base:16; ///< + UINT32 Top:16; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2024_STRUCT; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +// **** GMMx2814 Register Definition **** +// Address +#define GMMx2814_ADDRESS 0x2814 + +// Type +#define GMMx2814_TYPE TYPE_GMM +// Field Data +#define GMMx2814_WriteClks_OFFSET 0 +#define GMMx2814_WriteClks_WIDTH 9 +#define GMMx2814_WriteClks_MASK 0x1ff +#define GMMx2814_UvdHarshPriority_OFFSET 9 +#define GMMx2814_UvdHarshPriority_WIDTH 1 +#define GMMx2814_UvdHarshPriority_MASK 0x200 +#define GMMx2814_Reserved_31_10_OFFSET 10 +#define GMMx2814_Reserved_31_10_WIDTH 22 +#define GMMx2814_Reserved_31_10_MASK 0xfffffc00 + +/// GMMx2814 +typedef union { + struct { ///< + UINT32 WriteClks:9 ; ///< + UINT32 UvdHarshPriority:1 ; ///< + UINT32 Reserved_31_10:22; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2814_STRUCT; + +// **** GMMx281C Register Definition **** +// Address +#define GMMx281C_ADDRESS 0x281c + +// Type +#define GMMx281C_TYPE TYPE_GMM +// Field Data +#define GMMx281C_CSEnable_OFFSET 0 +#define GMMx281C_CSEnable_WIDTH 1 +#define GMMx281C_CSEnable_MASK 0x1 +#define GMMx281C_Reserved_4_1_OFFSET 1 +#define GMMx281C_Reserved_4_1_WIDTH 4 +#define GMMx281C_Reserved_4_1_MASK 0x1e +#define GMMx281C_BaseAddr_21_13__OFFSET 5 +#define GMMx281C_BaseAddr_21_13__WIDTH 9 +#define GMMx281C_BaseAddr_21_13__MASK 0x3fe0 +#define GMMx281C_Reserved_18_14_OFFSET 14 +#define GMMx281C_Reserved_18_14_WIDTH 5 +#define GMMx281C_Reserved_18_14_MASK 0x7c000 +#define GMMx281C_BaseAddr_36_27__OFFSET 19 +#define GMMx281C_BaseAddr_36_27__WIDTH 10 +#define GMMx281C_BaseAddr_36_27__MASK 0x1ff80000 +#define GMMx281C_Reserved_31_29_OFFSET 29 +#define GMMx281C_Reserved_31_29_WIDTH 3 +#define GMMx281C_Reserved_31_29_MASK 0xe0000000 + +/// GMMx281C +typedef union { + struct { ///< + UINT32 CSEnable:1 ; ///< + UINT32 Reserved_4_1:4 ; ///< + UINT32 BaseAddr_21_13_:9 ; ///< + UINT32 Reserved_18_14:5 ; ///< + UINT32 BaseAddr_36_27_:10; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx281C_STRUCT; + +// **** GMMx2820 Register Definition **** +// Address +#define GMMx2820_ADDRESS 0x2820 + +// Type +#define GMMx2820_TYPE TYPE_GMM +// Field Data +#define GMMx2820_CSEnable_OFFSET 0 +#define GMMx2820_CSEnable_WIDTH 1 +#define GMMx2820_CSEnable_MASK 0x1 +#define GMMx2820_Reserved_4_1_OFFSET 1 +#define GMMx2820_Reserved_4_1_WIDTH 4 +#define GMMx2820_Reserved_4_1_MASK 0x1e +#define GMMx2820_BaseAddr_21_13__OFFSET 5 +#define GMMx2820_BaseAddr_21_13__WIDTH 9 +#define GMMx2820_BaseAddr_21_13__MASK 0x3fe0 +#define GMMx2820_Reserved_18_14_OFFSET 14 +#define GMMx2820_Reserved_18_14_WIDTH 5 +#define GMMx2820_Reserved_18_14_MASK 0x7c000 +#define GMMx2820_BaseAddr_36_27__OFFSET 19 +#define GMMx2820_BaseAddr_36_27__WIDTH 10 +#define GMMx2820_BaseAddr_36_27__MASK 0x1ff80000 +#define GMMx2820_Reserved_31_29_OFFSET 29 +#define GMMx2820_Reserved_31_29_WIDTH 3 +#define GMMx2820_Reserved_31_29_MASK 0xe0000000 + +/// GMMx2820 +typedef union { + struct { ///< + UINT32 CSEnable:1 ; ///< + UINT32 Reserved_4_1:4 ; ///< + UINT32 BaseAddr_21_13_:9 ; ///< + UINT32 Reserved_18_14:5 ; ///< + UINT32 BaseAddr_36_27_:10; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2820_STRUCT; + +// **** GMMx2824 Register Definition **** +// Address +#define GMMx2824_ADDRESS 0x2824 + +// Type +#define GMMx2824_TYPE TYPE_GMM +// Field Data +#define GMMx2824_CSEnable_OFFSET 0 +#define GMMx2824_CSEnable_WIDTH 1 +#define GMMx2824_CSEnable_MASK 0x1 +#define GMMx2824_Reserved_4_1_OFFSET 1 +#define GMMx2824_Reserved_4_1_WIDTH 4 +#define GMMx2824_Reserved_4_1_MASK 0x1e +#define GMMx2824_BaseAddr_21_13__OFFSET 5 +#define GMMx2824_BaseAddr_21_13__WIDTH 9 +#define GMMx2824_BaseAddr_21_13__MASK 0x3fe0 +#define GMMx2824_Reserved_18_14_OFFSET 14 +#define GMMx2824_Reserved_18_14_WIDTH 5 +#define GMMx2824_Reserved_18_14_MASK 0x7c000 +#define GMMx2824_BaseAddr_36_27__OFFSET 19 +#define GMMx2824_BaseAddr_36_27__WIDTH 10 +#define GMMx2824_BaseAddr_36_27__MASK 0x1ff80000 +#define GMMx2824_Reserved_31_29_OFFSET 29 +#define GMMx2824_Reserved_31_29_WIDTH 3 +#define GMMx2824_Reserved_31_29_MASK 0xe0000000 + +/// GMMx2824 +typedef union { + struct { ///< + UINT32 CSEnable:1 ; ///< + UINT32 Reserved_4_1:4 ; ///< + UINT32 BaseAddr_21_13_:9 ; ///< + UINT32 Reserved_18_14:5 ; ///< + UINT32 BaseAddr_36_27_:10; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2824_STRUCT; + +// **** GMMx2828 Register Definition **** +// Address +#define GMMx2828_ADDRESS 0x2828 + +// Type +#define GMMx2828_TYPE TYPE_GMM +// Field Data +#define GMMx2828_CSEnable_OFFSET 0 +#define GMMx2828_CSEnable_WIDTH 1 +#define GMMx2828_CSEnable_MASK 0x1 +#define GMMx2828_Reserved_4_1_OFFSET 1 +#define GMMx2828_Reserved_4_1_WIDTH 4 +#define GMMx2828_Reserved_4_1_MASK 0x1e +#define GMMx2828_BaseAddr_21_13__OFFSET 5 +#define GMMx2828_BaseAddr_21_13__WIDTH 9 +#define GMMx2828_BaseAddr_21_13__MASK 0x3fe0 +#define GMMx2828_Reserved_18_14_OFFSET 14 +#define GMMx2828_Reserved_18_14_WIDTH 5 +#define GMMx2828_Reserved_18_14_MASK 0x7c000 +#define GMMx2828_BaseAddr_36_27__OFFSET 19 +#define GMMx2828_BaseAddr_36_27__WIDTH 10 +#define GMMx2828_BaseAddr_36_27__MASK 0x1ff80000 +#define GMMx2828_Reserved_31_29_OFFSET 29 +#define GMMx2828_Reserved_31_29_WIDTH 3 +#define GMMx2828_Reserved_31_29_MASK 0xe0000000 + +/// GMMx2828 +typedef union { + struct { ///< + UINT32 CSEnable:1 ; ///< + UINT32 Reserved_4_1:4 ; ///< + UINT32 BaseAddr_21_13_:9 ; ///< + UINT32 Reserved_18_14:5 ; ///< + UINT32 BaseAddr_36_27_:10; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2828_STRUCT; + +// **** GMMx282C Register Definition **** +// Address +#define GMMx282C_ADDRESS 0x282c + +// Type +#define GMMx282C_TYPE TYPE_GMM +// Field Data +#define GMMx282C_CSEnable_OFFSET 0 +#define GMMx282C_CSEnable_WIDTH 1 +#define GMMx282C_CSEnable_MASK 0x1 +#define GMMx282C_Reserved_4_1_OFFSET 1 +#define GMMx282C_Reserved_4_1_WIDTH 4 +#define GMMx282C_Reserved_4_1_MASK 0x1e +#define GMMx282C_BaseAddr_21_13__OFFSET 5 +#define GMMx282C_BaseAddr_21_13__WIDTH 9 +#define GMMx282C_BaseAddr_21_13__MASK 0x3fe0 +#define GMMx282C_Reserved_18_14_OFFSET 14 +#define GMMx282C_Reserved_18_14_WIDTH 5 +#define GMMx282C_Reserved_18_14_MASK 0x7c000 +#define GMMx282C_BaseAddr_36_27__OFFSET 19 +#define GMMx282C_BaseAddr_36_27__WIDTH 10 +#define GMMx282C_BaseAddr_36_27__MASK 0x1ff80000 +#define GMMx282C_Reserved_31_29_OFFSET 29 +#define GMMx282C_Reserved_31_29_WIDTH 3 +#define GMMx282C_Reserved_31_29_MASK 0xe0000000 + +/// GMMx282C +typedef union { + struct { ///< + UINT32 CSEnable:1 ; ///< + UINT32 Reserved_4_1:4 ; ///< + UINT32 BaseAddr_21_13_:9 ; ///< + UINT32 Reserved_18_14:5 ; ///< + UINT32 BaseAddr_36_27_:10; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx282C_STRUCT; + +// **** GMMx2830 Register Definition **** +// Address +#define GMMx2830_ADDRESS 0x2830 + +// Type +#define GMMx2830_TYPE TYPE_GMM +// Field Data +#define GMMx2830_CSEnable_OFFSET 0 +#define GMMx2830_CSEnable_WIDTH 1 +#define GMMx2830_CSEnable_MASK 0x1 +#define GMMx2830_Reserved_4_1_OFFSET 1 +#define GMMx2830_Reserved_4_1_WIDTH 4 +#define GMMx2830_Reserved_4_1_MASK 0x1e +#define GMMx2830_BaseAddr_21_13__OFFSET 5 +#define GMMx2830_BaseAddr_21_13__WIDTH 9 +#define GMMx2830_BaseAddr_21_13__MASK 0x3fe0 +#define GMMx2830_Reserved_18_14_OFFSET 14 +#define GMMx2830_Reserved_18_14_WIDTH 5 +#define GMMx2830_Reserved_18_14_MASK 0x7c000 +#define GMMx2830_BaseAddr_36_27__OFFSET 19 +#define GMMx2830_BaseAddr_36_27__WIDTH 10 +#define GMMx2830_BaseAddr_36_27__MASK 0x1ff80000 +#define GMMx2830_Reserved_31_29_OFFSET 29 +#define GMMx2830_Reserved_31_29_WIDTH 3 +#define GMMx2830_Reserved_31_29_MASK 0xe0000000 + +/// GMMx2830 +typedef union { + struct { ///< + UINT32 CSEnable:1 ; ///< + UINT32 Reserved_4_1:4 ; ///< + UINT32 BaseAddr_21_13_:9 ; ///< + UINT32 Reserved_18_14:5 ; ///< + UINT32 BaseAddr_36_27_:10; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2830_STRUCT; + +// **** GMMx2834 Register Definition **** +// Address +#define GMMx2834_ADDRESS 0x2834 + +// Type +#define GMMx2834_TYPE TYPE_GMM +// Field Data +#define GMMx2834_CSEnable_OFFSET 0 +#define GMMx2834_CSEnable_WIDTH 1 +#define GMMx2834_CSEnable_MASK 0x1 +#define GMMx2834_Reserved_4_1_OFFSET 1 +#define GMMx2834_Reserved_4_1_WIDTH 4 +#define GMMx2834_Reserved_4_1_MASK 0x1e +#define GMMx2834_BaseAddr_21_13__OFFSET 5 +#define GMMx2834_BaseAddr_21_13__WIDTH 9 +#define GMMx2834_BaseAddr_21_13__MASK 0x3fe0 +#define GMMx2834_Reserved_18_14_OFFSET 14 +#define GMMx2834_Reserved_18_14_WIDTH 5 +#define GMMx2834_Reserved_18_14_MASK 0x7c000 +#define GMMx2834_BaseAddr_36_27__OFFSET 19 +#define GMMx2834_BaseAddr_36_27__WIDTH 10 +#define GMMx2834_BaseAddr_36_27__MASK 0x1ff80000 +#define GMMx2834_Reserved_31_29_OFFSET 29 +#define GMMx2834_Reserved_31_29_WIDTH 3 +#define GMMx2834_Reserved_31_29_MASK 0xe0000000 + +/// GMMx2834 +typedef union { + struct { ///< + UINT32 CSEnable:1 ; ///< + UINT32 Reserved_4_1:4 ; ///< + UINT32 BaseAddr_21_13_:9 ; ///< + UINT32 Reserved_18_14:5 ; ///< + UINT32 BaseAddr_36_27_:10; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2834_STRUCT; + +// **** GMMx2838 Register Definition **** +// Address +#define GMMx2838_ADDRESS 0x2838 + +// Type +#define GMMx2838_TYPE TYPE_GMM +// Field Data +#define GMMx2838_CSEnable_OFFSET 0 +#define GMMx2838_CSEnable_WIDTH 1 +#define GMMx2838_CSEnable_MASK 0x1 +#define GMMx2838_Reserved_4_1_OFFSET 1 +#define GMMx2838_Reserved_4_1_WIDTH 4 +#define GMMx2838_Reserved_4_1_MASK 0x1e +#define GMMx2838_BaseAddr_21_13__OFFSET 5 +#define GMMx2838_BaseAddr_21_13__WIDTH 9 +#define GMMx2838_BaseAddr_21_13__MASK 0x3fe0 +#define GMMx2838_Reserved_18_14_OFFSET 14 +#define GMMx2838_Reserved_18_14_WIDTH 5 +#define GMMx2838_Reserved_18_14_MASK 0x7c000 +#define GMMx2838_BaseAddr_36_27__OFFSET 19 +#define GMMx2838_BaseAddr_36_27__WIDTH 10 +#define GMMx2838_BaseAddr_36_27__MASK 0x1ff80000 +#define GMMx2838_Reserved_31_29_OFFSET 29 +#define GMMx2838_Reserved_31_29_WIDTH 3 +#define GMMx2838_Reserved_31_29_MASK 0xe0000000 + +/// GMMx2838 +typedef union { + struct { ///< + UINT32 CSEnable:1 ; ///< + UINT32 Reserved_4_1:4 ; ///< + UINT32 BaseAddr_21_13_:9 ; ///< + UINT32 Reserved_18_14:5 ; ///< + UINT32 BaseAddr_36_27_:10; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2838_STRUCT; + +// **** GMMx283C Register Definition **** +// Address +#define GMMx283C_ADDRESS 0x283c + +// Type +#define GMMx283C_TYPE TYPE_GMM +// Field Data +#define GMMx283C_Reserved_4_0_OFFSET 0 +#define GMMx283C_Reserved_4_0_WIDTH 5 +#define GMMx283C_Reserved_4_0_MASK 0x1f +#define GMMx283C_AddrMask_21_13__OFFSET 5 +#define GMMx283C_AddrMask_21_13__WIDTH 9 +#define GMMx283C_AddrMask_21_13__MASK 0x3fe0 +#define GMMx283C_Reserved_18_14_OFFSET 14 +#define GMMx283C_Reserved_18_14_WIDTH 5 +#define GMMx283C_Reserved_18_14_MASK 0x7c000 +#define GMMx283C_AddrMask_36_27__OFFSET 19 +#define GMMx283C_AddrMask_36_27__WIDTH 10 +#define GMMx283C_AddrMask_36_27__MASK 0x1ff80000 +#define GMMx283C_Reserved_31_29_OFFSET 29 +#define GMMx283C_Reserved_31_29_WIDTH 3 +#define GMMx283C_Reserved_31_29_MASK 0xe0000000 + +/// GMMx283C +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 AddrMask_21_13_:9 ; ///< + UINT32 Reserved_18_14:5 ; ///< + UINT32 AddrMask_36_27_:10; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx283C_STRUCT; + +// **** GMMx2840 Register Definition **** +// Address +#define GMMx2840_ADDRESS 0x2840 + +// Type +#define GMMx2840_TYPE TYPE_GMM +// Field Data +#define GMMx2840_Reserved_4_0_OFFSET 0 +#define GMMx2840_Reserved_4_0_WIDTH 5 +#define GMMx2840_Reserved_4_0_MASK 0x1f +#define GMMx2840_AddrMask_21_13__OFFSET 5 +#define GMMx2840_AddrMask_21_13__WIDTH 9 +#define GMMx2840_AddrMask_21_13__MASK 0x3fe0 +#define GMMx2840_Reserved_18_14_OFFSET 14 +#define GMMx2840_Reserved_18_14_WIDTH 5 +#define GMMx2840_Reserved_18_14_MASK 0x7c000 +#define GMMx2840_AddrMask_36_27__OFFSET 19 +#define GMMx2840_AddrMask_36_27__WIDTH 10 +#define GMMx2840_AddrMask_36_27__MASK 0x1ff80000 +#define GMMx2840_Reserved_31_29_OFFSET 29 +#define GMMx2840_Reserved_31_29_WIDTH 3 +#define GMMx2840_Reserved_31_29_MASK 0xe0000000 + +/// GMMx2840 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 AddrMask_21_13_:9 ; ///< + UINT32 Reserved_18_14:5 ; ///< + UINT32 AddrMask_36_27_:10; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2840_STRUCT; + +// **** GMMx2844 Register Definition **** +// Address +#define GMMx2844_ADDRESS 0x2844 + +// Type +#define GMMx2844_TYPE TYPE_GMM +// Field Data +#define GMMx2844_Reserved_4_0_OFFSET 0 +#define GMMx2844_Reserved_4_0_WIDTH 5 +#define GMMx2844_Reserved_4_0_MASK 0x1f +#define GMMx2844_AddrMask_21_13__OFFSET 5 +#define GMMx2844_AddrMask_21_13__WIDTH 9 +#define GMMx2844_AddrMask_21_13__MASK 0x3fe0 +#define GMMx2844_Reserved_18_14_OFFSET 14 +#define GMMx2844_Reserved_18_14_WIDTH 5 +#define GMMx2844_Reserved_18_14_MASK 0x7c000 +#define GMMx2844_AddrMask_36_27__OFFSET 19 +#define GMMx2844_AddrMask_36_27__WIDTH 10 +#define GMMx2844_AddrMask_36_27__MASK 0x1ff80000 +#define GMMx2844_Reserved_31_29_OFFSET 29 +#define GMMx2844_Reserved_31_29_WIDTH 3 +#define GMMx2844_Reserved_31_29_MASK 0xe0000000 + +/// GMMx2844 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 AddrMask_21_13_:9 ; ///< + UINT32 Reserved_18_14:5 ; ///< + UINT32 AddrMask_36_27_:10; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2844_STRUCT; + +// **** GMMx2848 Register Definition **** +// Address +#define GMMx2848_ADDRESS 0x2848 + +// Type +#define GMMx2848_TYPE TYPE_GMM +// Field Data +#define GMMx2848_Reserved_4_0_OFFSET 0 +#define GMMx2848_Reserved_4_0_WIDTH 5 +#define GMMx2848_Reserved_4_0_MASK 0x1f +#define GMMx2848_AddrMask_21_13__OFFSET 5 +#define GMMx2848_AddrMask_21_13__WIDTH 9 +#define GMMx2848_AddrMask_21_13__MASK 0x3fe0 +#define GMMx2848_Reserved_18_14_OFFSET 14 +#define GMMx2848_Reserved_18_14_WIDTH 5 +#define GMMx2848_Reserved_18_14_MASK 0x7c000 +#define GMMx2848_AddrMask_36_27__OFFSET 19 +#define GMMx2848_AddrMask_36_27__WIDTH 10 +#define GMMx2848_AddrMask_36_27__MASK 0x1ff80000 +#define GMMx2848_Reserved_31_29_OFFSET 29 +#define GMMx2848_Reserved_31_29_WIDTH 3 +#define GMMx2848_Reserved_31_29_MASK 0xe0000000 + +/// GMMx2848 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 AddrMask_21_13_:9 ; ///< + UINT32 Reserved_18_14:5 ; ///< + UINT32 AddrMask_36_27_:10; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2848_STRUCT; + +// **** GMMx284C Register Definition **** +// Address +#define GMMx284C_ADDRESS 0x284c + +// Type +#define GMMx284C_TYPE TYPE_GMM +// Field Data +#define GMMx284C_Dimm0AddrMap_OFFSET 0 +#define GMMx284C_Dimm0AddrMap_WIDTH 4 +#define GMMx284C_Dimm0AddrMap_MASK 0xf +#define GMMx284C_Dimm1AddrMap_OFFSET 4 +#define GMMx284C_Dimm1AddrMap_WIDTH 4 +#define GMMx284C_Dimm1AddrMap_MASK 0xf0 +#define GMMx284C_Reserved_15_8_OFFSET 8 +#define GMMx284C_Reserved_15_8_WIDTH 8 +#define GMMx284C_Reserved_15_8_MASK 0xff00 +#define GMMx284C_BankSwizzleMode_OFFSET 16 +#define GMMx284C_BankSwizzleMode_WIDTH 1 +#define GMMx284C_BankSwizzleMode_MASK 0x10000 +#define GMMx284C_Ddr3Mode_OFFSET 17 +#define GMMx284C_Ddr3Mode_WIDTH 1 +#define GMMx284C_Ddr3Mode_MASK 0x20000 +#define GMMx284C_BurstLength32_OFFSET 18 +#define GMMx284C_BurstLength32_WIDTH 1 +#define GMMx284C_BurstLength32_MASK 0x40000 +#define GMMx284C_BankSwap_OFFSET 19 +#define GMMx284C_BankSwap_WIDTH 1 +#define GMMx284C_BankSwap_MASK 0x80000 +#define GMMx284C_Reserved_31_20_OFFSET 20 +#define GMMx284C_Reserved_31_20_WIDTH 12 +#define GMMx284C_Reserved_31_20_MASK 0xfff00000 + +/// GMMx284C +typedef union { + struct { ///< + UINT32 Dimm0AddrMap:4 ; ///< + UINT32 Dimm1AddrMap:4 ; ///< + UINT32 Reserved_15_8:8 ; ///< + UINT32 BankSwizzleMode:1 ; ///< + UINT32 Ddr3Mode:1 ; ///< + UINT32 BurstLength32:1 ; ///< + UINT32 BankSwap:1 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx284C_STRUCT; + +// **** GMMx2850 Register Definition **** +// Address +#define GMMx2850_ADDRESS 0x2850 + +// Type +#define GMMx2850_TYPE TYPE_GMM +// Field Data +#define GMMx2850_Dimm0AddrMap_OFFSET 0 +#define GMMx2850_Dimm0AddrMap_WIDTH 4 +#define GMMx2850_Dimm0AddrMap_MASK 0xf +#define GMMx2850_Dimm1AddrMap_OFFSET 4 +#define GMMx2850_Dimm1AddrMap_WIDTH 4 +#define GMMx2850_Dimm1AddrMap_MASK 0xf0 +#define GMMx2850_Reserved_15_8_OFFSET 8 +#define GMMx2850_Reserved_15_8_WIDTH 8 +#define GMMx2850_Reserved_15_8_MASK 0xff00 +#define GMMx2850_BankSwizzleMode_OFFSET 16 +#define GMMx2850_BankSwizzleMode_WIDTH 1 +#define GMMx2850_BankSwizzleMode_MASK 0x10000 +#define GMMx2850_Ddr3Mode_OFFSET 17 +#define GMMx2850_Ddr3Mode_WIDTH 1 +#define GMMx2850_Ddr3Mode_MASK 0x20000 +#define GMMx2850_BurstLength32_OFFSET 18 +#define GMMx2850_BurstLength32_WIDTH 1 +#define GMMx2850_BurstLength32_MASK 0x40000 +#define GMMx2850_BankSwap_OFFSET 19 +#define GMMx2850_BankSwap_WIDTH 1 +#define GMMx2850_BankSwap_MASK 0x80000 +#define GMMx2850_Reserved_31_20_OFFSET 20 +#define GMMx2850_Reserved_31_20_WIDTH 12 +#define GMMx2850_Reserved_31_20_MASK 0xfff00000 + +/// GMMx2850 +typedef union { + struct { ///< + UINT32 Dimm0AddrMap:4 ; ///< + UINT32 Dimm1AddrMap:4 ; ///< + UINT32 Reserved_15_8:8 ; ///< + UINT32 BankSwizzleMode:1 ; ///< + UINT32 Ddr3Mode:1 ; ///< + UINT32 BurstLength32:1 ; ///< + UINT32 BankSwap:1 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2850_STRUCT; + +// **** GMMx2854 Register Definition **** +// Address +#define GMMx2854_ADDRESS 0x2854 + +// Type +#define GMMx2854_TYPE TYPE_GMM +// Field Data +#define GMMx2854_DctSelHiRngEn_OFFSET 0 +#define GMMx2854_DctSelHiRngEn_WIDTH 1 +#define GMMx2854_DctSelHiRngEn_MASK 0x1 +#define GMMx2854_DctSelHi_OFFSET 1 +#define GMMx2854_DctSelHi_WIDTH 1 +#define GMMx2854_DctSelHi_MASK 0x2 +#define GMMx2854_DctSelIntLvEn_OFFSET 2 +#define GMMx2854_DctSelIntLvEn_WIDTH 1 +#define GMMx2854_DctSelIntLvEn_MASK 0x4 +#define GMMx2854_Reserved_5_3_OFFSET 3 +#define GMMx2854_Reserved_5_3_WIDTH 3 +#define GMMx2854_Reserved_5_3_MASK 0x38 +#define GMMx2854_DctSelIntLvAddr_1_0__OFFSET 6 +#define GMMx2854_DctSelIntLvAddr_1_0__WIDTH 2 +#define GMMx2854_DctSelIntLvAddr_1_0__MASK 0xc0 +#define GMMx2854_Reserved_10_8_OFFSET 8 +#define GMMx2854_Reserved_10_8_WIDTH 3 +#define GMMx2854_Reserved_10_8_MASK 0x700 +#define GMMx2854_DctSelBaseAddr_39_27__OFFSET 11 +#define GMMx2854_DctSelBaseAddr_39_27__WIDTH 13 +#define GMMx2854_DctSelBaseAddr_39_27__MASK 0xfff800 +#define GMMx2854_Reserved_31_24_OFFSET 24 +#define GMMx2854_Reserved_31_24_WIDTH 8 +#define GMMx2854_Reserved_31_24_MASK 0xff000000 + +/// GMMx2854 +typedef union { + struct { ///< + UINT32 DctSelHiRngEn:1 ; ///< + UINT32 DctSelHi:1 ; ///< + UINT32 DctSelIntLvEn:1 ; ///< + UINT32 Reserved_5_3:3 ; ///< + UINT32 DctSelIntLvAddr_1_0_:2 ; ///< + UINT32 Reserved_10_8:3 ; ///< + UINT32 DctSelBaseAddr_39_27_:13; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2854_STRUCT; + +// **** GMMx2858 Register Definition **** +// Address +#define GMMx2858_ADDRESS 0x2858 + +// Type +#define GMMx2858_TYPE TYPE_GMM +// Field Data +#define GMMx2858_Reserved_8_0_OFFSET 0 +#define GMMx2858_Reserved_8_0_WIDTH 9 +#define GMMx2858_Reserved_8_0_MASK 0x1ff +#define GMMx2858_DctSelIntLvAddr_2__OFFSET 9 +#define GMMx2858_DctSelIntLvAddr_2__WIDTH 1 +#define GMMx2858_DctSelIntLvAddr_2__MASK 0x200 +#define GMMx2858_DctSelBaseOffset_39_26__OFFSET 10 +#define GMMx2858_DctSelBaseOffset_39_26__WIDTH 14 +#define GMMx2858_DctSelBaseOffset_39_26__MASK 0xfffc00 +#define GMMx2858_Reserved_31_24_OFFSET 24 +#define GMMx2858_Reserved_31_24_WIDTH 8 +#define GMMx2858_Reserved_31_24_MASK 0xff000000 + +/// GMMx2858 +typedef union { + struct { ///< + UINT32 Reserved_8_0:9 ; ///< + UINT32 DctSelIntLvAddr_2_:1 ; ///< + UINT32 DctSelBaseOffset_39_26_:14; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2858_STRUCT; + +// **** GMMx285C Register Definition **** +// Address +#define GMMx285C_ADDRESS 0x285c + +// Type +#define GMMx285C_TYPE TYPE_GMM +// Field Data +#define GMMx285C_DramHoleValid_OFFSET 0 +#define GMMx285C_DramHoleValid_WIDTH 1 +#define GMMx285C_DramHoleValid_MASK 0x1 +#define GMMx285C_Reserved_6_1_OFFSET 1 +#define GMMx285C_Reserved_6_1_WIDTH 6 +#define GMMx285C_Reserved_6_1_MASK 0x7e +#define GMMx285C_DramHoleOffset_31_23__OFFSET 7 +#define GMMx285C_DramHoleOffset_31_23__WIDTH 9 +#define GMMx285C_DramHoleOffset_31_23__MASK 0xff80 +#define GMMx285C_Reserved_23_16_OFFSET 16 +#define GMMx285C_Reserved_23_16_WIDTH 8 +#define GMMx285C_Reserved_23_16_MASK 0xff0000 +#define GMMx285C_DramHoleBase_31_24__OFFSET 24 +#define GMMx285C_DramHoleBase_31_24__WIDTH 8 +#define GMMx285C_DramHoleBase_31_24__MASK 0xff000000 + +/// GMMx285C +typedef union { + struct { ///< + UINT32 DramHoleValid:1 ; ///< + UINT32 Reserved_6_1:6 ; ///< + UINT32 DramHoleOffset_31_23_:9 ; ///< + UINT32 Reserved_23_16:8 ; ///< + UINT32 DramHoleBase_31_24_:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx285C_STRUCT; + + + + + +// **** GMMx2870 Register Definition **** +// Address +#define GMMx2870_ADDRESS 0x2870 + +// Type +#define GMMx2870_TYPE TYPE_GMM +// Field Data +#define GMMx2870_Base_OFFSET 0 +#define GMMx2870_Base_WIDTH 20 +#define GMMx2870_Base_MASK 0xfffff +#define GMMx2870_Reserved_31_20_OFFSET 20 +#define GMMx2870_Reserved_31_20_WIDTH 12 +#define GMMx2870_Reserved_31_20_MASK 0xfff00000 + +/// GMMx2870 +typedef union { + struct { ///< + UINT32 Base:20; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2870_STRUCT; + +// **** GMMx2874 Register Definition **** +// Address +#define GMMx2874_ADDRESS 0x2874 + +// Type +#define GMMx2874_TYPE TYPE_GMM +// Field Data +#define GMMx2874_Base_OFFSET 0 +#define GMMx2874_Base_WIDTH 20 +#define GMMx2874_Base_MASK 0xfffff +#define GMMx2874_Reserved_31_20_OFFSET 20 +#define GMMx2874_Reserved_31_20_WIDTH 12 +#define GMMx2874_Reserved_31_20_MASK 0xfff00000 + +/// GMMx2874 +typedef union { + struct { ///< + UINT32 Base:20; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2874_STRUCT; + + +// **** GMMx287C Register Definition **** +// Address +#define GMMx287C_ADDRESS 0x287c + +// Type +#define GMMx287C_TYPE TYPE_GMM +// Field Data +#define GMMx287C_Top_OFFSET 0 +#define GMMx287C_Top_WIDTH 20 +#define GMMx287C_Top_MASK 0xfffff +#define GMMx287C_Reserved_31_20_OFFSET 20 +#define GMMx287C_Reserved_31_20_WIDTH 12 +#define GMMx287C_Reserved_31_20_MASK 0xfff00000 + +/// GMMx287C +typedef union { + struct { ///< + UINT32 Top:20; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx287C_STRUCT; + + + +// **** GMMx2888 Register Definition **** +// Address +#define GMMx2888_ADDRESS 0x2888 + +// Type +#define GMMx2888_TYPE TYPE_GMM +// Field Data +#define GMMx2888_Top_OFFSET 0 +#define GMMx2888_Top_WIDTH 20 +#define GMMx2888_Top_MASK 0xfffff +#define GMMx2888_Reserved_31_20_OFFSET 20 +#define GMMx2888_Reserved_31_20_WIDTH 12 +#define GMMx2888_Reserved_31_20_MASK 0xfff00000 + +/// GMMx2888 +typedef union { + struct { ///< + UINT32 Top:20; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2888_STRUCT; + + + + + + +// **** GMMx28D8 Register Definition **** +// Address +#define GMMx28D8_ADDRESS 0x28d8 + +// Type +#define GMMx28D8_TYPE TYPE_GMM +// Field Data +#define GMMx28D8_ActRd_OFFSET 0 +#define GMMx28D8_ActRd_WIDTH 8 +#define GMMx28D8_ActRd_MASK 0xff +#define GMMx28D8_ActWr_OFFSET 8 +#define GMMx28D8_ActWr_WIDTH 8 +#define GMMx28D8_ActWr_MASK 0xff00 +#define GMMx28D8_RasMActRd_OFFSET 16 +#define GMMx28D8_RasMActRd_WIDTH 8 +#define GMMx28D8_RasMActRd_MASK 0xff0000 +#define GMMx28D8_RasMActWr_OFFSET 24 +#define GMMx28D8_RasMActWr_WIDTH 8 +#define GMMx28D8_RasMActWr_MASK 0xff000000 + +/// GMMx28D8 +typedef union { + struct { ///< + UINT32 ActRd:8 ; ///< + UINT32 ActWr:8 ; ///< + UINT32 RasMActRd:8 ; ///< + UINT32 RasMActWr:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx28D8_STRUCT; + + + + + + + +// **** GMMx2C04 Register Definition **** +// Address +#define GMMx2C04_ADDRESS 0x2c04 + +// Type +#define GMMx2C04_TYPE TYPE_GMM +// Field Data +#define GMMx2C04_NonsurfBase_OFFSET 0 +#define GMMx2C04_NonsurfBase_WIDTH 28 +#define GMMx2C04_NonsurfBase_MASK 0xfffffff +#define GMMx2C04_Reserved_31_28_OFFSET 28 +#define GMMx2C04_Reserved_31_28_WIDTH 4 +#define GMMx2C04_Reserved_31_28_MASK 0xf0000000 + +/// GMMx2C04 +typedef union { + struct { ///< + UINT32 NonsurfBase:28; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2C04_STRUCT; + +// **** GMMx5428 Register Definition **** +// Address +#define GMMx5428_ADDRESS 0x5428 + +// Type +#define GMMx5428_TYPE TYPE_GMM +// Field Data +#define GMMx5428_ConfigMemsize_OFFSET 0 +#define GMMx5428_ConfigMemsize_WIDTH 32 +#define GMMx5428_ConfigMemsize_MASK 0xffffffff + +/// GMMx5428 +typedef union { + struct { ///< + UINT32 ConfigMemsize:32; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx5428_STRUCT; + +// **** GMMx5490 Register Definition **** +// Address +#define GMMx5490_ADDRESS 0x5490 + +// Type +#define GMMx5490_TYPE TYPE_GMM +// Field Data +#define GMMx5490_FbReadEn_OFFSET 0 +#define GMMx5490_FbReadEn_WIDTH 1 +#define GMMx5490_FbReadEn_MASK 0x1 +#define GMMx5490_FbWriteEn_OFFSET 1 +#define GMMx5490_FbWriteEn_WIDTH 1 +#define GMMx5490_FbWriteEn_MASK 0x2 +#define GMMx5490_Reserved_31_2_OFFSET 2 +#define GMMx5490_Reserved_31_2_WIDTH 30 +#define GMMx5490_Reserved_31_2_MASK 0xfffffffc + +/// GMMx5490 +typedef union { + struct { ///< + UINT32 FbReadEn:1 ; ///< + UINT32 FbWriteEn:1 ; ///< + UINT32 Reserved_31_2:30; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx5490_STRUCT; + + +/// SMUx73 +typedef union { + struct { ///< + UINT32 DisLclkGating:1 ; ///< + UINT32 DisSclkGating:1 ; ///< + UINT32 Reserved_15_2:14; ///< + } Field; ///< + UINT32 Value; ///< +} SMUx73_STRUCT; + +// **** MSRC001_001A Register Definition **** +// Address +#define MSRC001_001A_ADDRESS 0xc001001a + +// Type +#define MSRC001_001A_TYPE TYPE_MSR +// Field Data +#define MSRC001_001A_RAZ_22_0_OFFSET 0 +#define MSRC001_001A_RAZ_22_0_WIDTH 23 +#define MSRC001_001A_RAZ_22_0_MASK 0x7fffff +#define MSRC001_001A_TOM_39_23__OFFSET 23 +#define MSRC001_001A_TOM_39_23__WIDTH 17 +#define MSRC001_001A_TOM_39_23__MASK 0xffff800000 +#define MSRC001_001A_MBZ_47_40_OFFSET 40 +#define MSRC001_001A_MBZ_47_40_WIDTH 8 +#define MSRC001_001A_MBZ_47_40_MASK 0xff0000000000 +#define MSRC001_001A_RAZ_63_48_OFFSET 48 +#define MSRC001_001A_RAZ_63_48_WIDTH 16 +#define MSRC001_001A_RAZ_63_48_MASK 0xffff000000000000 + +/// MSRC001_001A +typedef union { + struct { ///< + UINT64 RAZ_22_0:23; ///< + UINT64 TOM_39_23_:17; ///< + UINT64 MBZ_47_40:8 ; ///< + UINT64 RAZ_63_48:16; ///< + } Field; ///< + UINT64 Value; ///< +} MSRC001_001A_STRUCT; + + + + + + + +// **** D0F0xE4_WRAP_8013 Register Definition **** +// Address +#define D0F0xE4_WRAP_8013_ADDRESS 0x8013 + +// Field Data +#define D0F0xE4_WRAP_8013_MasterPciePllA_OFFSET 0 +#define D0F0xE4_WRAP_8013_MasterPciePllA_WIDTH 1 +#define D0F0xE4_WRAP_8013_MasterPciePllA_MASK 0x1 +#define D0F0xE4_WRAP_8013_Reserved_1_1_OFFSET 1 +#define D0F0xE4_WRAP_8013_Reserved_1_1_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_1_1_MASK 0x2 +#define D0F0xE4_WRAP_8013_Reserved_2_2_OFFSET 2 +#define D0F0xE4_WRAP_8013_Reserved_2_2_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_2_2_MASK 0x4 +#define D0F0xE4_WRAP_8013_Reserved_3_3_OFFSET 3 +#define D0F0xE4_WRAP_8013_Reserved_3_3_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_3_3_MASK 0x8 +#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_OFFSET 4 +#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_WIDTH 1 +#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_MASK 0x10 +#define D0F0xE4_WRAP_8013_Reserved_5_5_OFFSET 5 +#define D0F0xE4_WRAP_8013_Reserved_5_5_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_5_5_MASK 0x20 +#define D0F0xE4_WRAP_8013_Reserved_6_6_OFFSET 6 +#define D0F0xE4_WRAP_8013_Reserved_6_6_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_6_6_MASK 0x40 +#define D0F0xE4_WRAP_8013_Reserved_7_7_OFFSET 7 +#define D0F0xE4_WRAP_8013_Reserved_7_7_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_7_7_MASK 0x80 +#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_OFFSET 8 +#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_WIDTH 1 +#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_MASK 0x100 +#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_OFFSET 9 +#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_WIDTH 1 +#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_MASK 0x200 +#define D0F0xE4_WRAP_8013_Reserved_10_10_OFFSET 10 +#define D0F0xE4_WRAP_8013_Reserved_10_10_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_10_10_MASK 0x400 +#define D0F0xE4_WRAP_8013_Reserved_11_11_OFFSET 11 +#define D0F0xE4_WRAP_8013_Reserved_11_11_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_11_11_MASK 0x800 +#define D0F0xE4_WRAP_8013_Reserved_12_12_OFFSET 12 +#define D0F0xE4_WRAP_8013_Reserved_12_12_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_12_12_MASK 0x1000 +#define D0F0xE4_WRAP_8013_Reserved_15_13_OFFSET 13 +#define D0F0xE4_WRAP_8013_Reserved_15_13_WIDTH 3 +#define D0F0xE4_WRAP_8013_Reserved_15_13_MASK 0xe000 +#define D0F0xE4_WRAP_8013_Reserved_16_16_OFFSET 16 +#define D0F0xE4_WRAP_8013_Reserved_16_16_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_16_16_MASK 0x10000 +#define D0F0xE4_WRAP_8013_Reserved_19_17_OFFSET 17 +#define D0F0xE4_WRAP_8013_Reserved_19_17_WIDTH 3 +#define D0F0xE4_WRAP_8013_Reserved_19_17_MASK 0xe0000 +#define D0F0xE4_WRAP_8013_Reserved_20_20_OFFSET 20 +#define D0F0xE4_WRAP_8013_Reserved_20_20_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_20_20_MASK 0x100000 +#define D0F0xE4_WRAP_8013_Reserved_31_21_OFFSET 21 +#define D0F0xE4_WRAP_8013_Reserved_31_21_WIDTH 11 +#define D0F0xE4_WRAP_8013_Reserved_31_21_MASK 0xffe00000 + +/// D0F0xE4_WRAP_8013 +typedef union { + struct { ///< + UINT32 MasterPciePllA:1 ; ///< + UINT32 MasterPciePllB:1 ; ///< + UINT32 MasterPciePllC:1 ; ///< + UINT32 MasterPciePllD:1 ; ///< + UINT32 ClkDividerResetOverrideA:1 ; ///< + UINT32 Reserved_5_5:1 ; ///< + UINT32 Reserved_6_6:1 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 TxclkSelCoreOverride:1 ; ///< + UINT32 TxclkSelPifAOverride:1 ; ///< + UINT32 Reserved_10_10:1 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 Reserved_12_12:1 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 Reserved_16_16:1 ; ///< + UINT32 Reserved_19_17:3 ; ///< + UINT32 Reserved_20_20:1 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8013_STRUCT; + +// **** D0F0xE4_WRAP_8014 Register Definition **** +// Address +#define D0F0xE4_WRAP_8014_ADDRESS 0x8014 + +// Field Data +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_OFFSET 0 +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_MASK 0x1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_OFFSET 1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_MASK 0x2 +#define D0F0xE4_WRAP_8014_Reserved_2_2_OFFSET 2 +#define D0F0xE4_WRAP_8014_Reserved_2_2_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_2_2_MASK 0x4 +#define D0F0xE4_WRAP_8014_Reserved_3_3_OFFSET 3 +#define D0F0xE4_WRAP_8014_Reserved_3_3_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_3_3_MASK 0x8 +#define D0F0xE4_WRAP_8014_Reserved_4_4_OFFSET 4 +#define D0F0xE4_WRAP_8014_Reserved_4_4_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_4_4_MASK 0x10 +#define D0F0xE4_WRAP_8014_Reserved_5_5_OFFSET 5 +#define D0F0xE4_WRAP_8014_Reserved_5_5_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_5_5_MASK 0x20 +#define D0F0xE4_WRAP_8014_Reserved_6_6_OFFSET 6 +#define D0F0xE4_WRAP_8014_Reserved_6_6_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_6_6_MASK 0x40 +#define D0F0xE4_WRAP_8014_Reserved_7_7_OFFSET 7 +#define D0F0xE4_WRAP_8014_Reserved_7_7_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_7_7_MASK 0x80 +#define D0F0xE4_WRAP_8014_Reserved_8_8_OFFSET 8 +#define D0F0xE4_WRAP_8014_Reserved_8_8_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_8_8_MASK 0x100 +#define D0F0xE4_WRAP_8014_Reserved_9_9_OFFSET 9 +#define D0F0xE4_WRAP_8014_Reserved_9_9_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_9_9_MASK 0x200 +#define D0F0xE4_WRAP_8014_Reserved_10_10_OFFSET 10 +#define D0F0xE4_WRAP_8014_Reserved_10_10_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_10_10_MASK 0x400 +#define D0F0xE4_WRAP_8014_Reserved_11_11_OFFSET 11 +#define D0F0xE4_WRAP_8014_Reserved_11_11_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_11_11_MASK 0x800 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_OFFSET 12 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_MASK 0x1000 +#define D0F0xE4_WRAP_8014_Reserved_13_13_OFFSET 13 +#define D0F0xE4_WRAP_8014_Reserved_13_13_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_13_13_MASK 0x2000 +#define D0F0xE4_WRAP_8014_Reserved_14_14_OFFSET 14 +#define D0F0xE4_WRAP_8014_Reserved_14_14_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_14_14_MASK 0x4000 +#define D0F0xE4_WRAP_8014_Reserved_15_15_OFFSET 15 +#define D0F0xE4_WRAP_8014_Reserved_15_15_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_15_15_MASK 0x8000 +#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_OFFSET 16 +#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_MASK 0x10000 +#define D0F0xE4_WRAP_8014_Reserved_17_17_OFFSET 17 +#define D0F0xE4_WRAP_8014_Reserved_17_17_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_17_17_MASK 0x20000 +#define D0F0xE4_WRAP_8014_Reserved_18_18_OFFSET 18 +#define D0F0xE4_WRAP_8014_Reserved_18_18_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_18_18_MASK 0x40000 +#define D0F0xE4_WRAP_8014_Reserved_19_19_OFFSET 19 +#define D0F0xE4_WRAP_8014_Reserved_19_19_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_19_19_MASK 0x80000 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_OFFSET 20 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_MASK 0x100000 +#define D0F0xE4_WRAP_8014_Reserved_31_21_OFFSET 21 +#define D0F0xE4_WRAP_8014_Reserved_31_21_WIDTH 11 +#define D0F0xE4_WRAP_8014_Reserved_31_21_MASK 0xffe00000 + +/// D0F0xE4_WRAP_8014 +typedef union { + struct { + UINT32 TxclkPermGateEnable:1 ; ///< + UINT32 TxclkPrbsGateEnable:1 ; ///< + UINT32 DdiGatePifA1xEnable:1 ; ///< + UINT32 DdiGatePifB1xEnable:1 ; ///< + UINT32 DdiGatePifC1xEnable:1 ; ///< + UINT32 DdiGatePifD1xEnable:1 ; ///< + UINT32 DdiGateDigAEnable:1 ; ///< + UINT32 DdiGateDigBEnable:1 ; ///< + UINT32 DdiGatePifA2p5xEnable:1 ; ///< + UINT32 DdiGatePifB2p5xEnable:1 ; ///< + UINT32 DdiGatePifC2p5xEnable:1 ; ///< + UINT32 DdiGatePifD2p5xEnable:1 ; ///< + UINT32 PcieGatePifA1xEnable:1 ; ///< + UINT32 PcieGatePifB1xEnable:1 ; ///< + UINT32 PcieGatePifC1xEnable:1 ; ///< + UINT32 PcieGatePifD1xEnable:1 ; ///< + UINT32 PcieGatePifA2p5xEnable:1 ; ///< + UINT32 PcieGatePifB2p5xEnable:1 ; ///< + UINT32 PcieGatePifC2p5xEnable:1 ; ///< + UINT32 PcieGatePifD2p5xEnable:1 ; ///< + UINT32 TxclkPermGateOnlyWhenPllPwrDn:1 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8014_STRUCT; + + + + + +// **** GMMx6124 Register Definition **** +// Address +#define GMMx6124_ADDRESS 0x6124 + +// **** GMMx6124 Register Definition **** +// Address +#define GMMx6124_ADDRESS 0x6124 + +// Type +#define GMMx6124_TYPE TYPE_GMM +// Field Data +#define GMMx6124_DoutScratch_OFFSET 0 +#define GMMx6124_DoutScratch_WIDTH 32 +#define GMMx6124_DoutScratch_MASK 0xffffffff + + + + + + + + +// **** D0F0xE4_CORE_0020 Register Definition **** +// Address +#define D0F0xE4_CORE_0020_ADDRESS 0x20 + +// Type +#define D0F0xE4_CORE_0020_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_0020_Reserved_1_0_OFFSET 0 +#define D0F0xE4_CORE_0020_Reserved_1_0_WIDTH 2 +#define D0F0xE4_CORE_0020_Reserved_1_0_MASK 0x3 +#define D0F0xE4_CORE_0020_Reserved_31_12_OFFSET 12 +#define D0F0xE4_CORE_0020_Reserved_31_12_WIDTH 20 +#define D0F0xE4_CORE_0020_Reserved_31_12_MASK 0xfffff000 + +/// D0F0xE4_CORE_0020 +typedef union { + struct { ///< + UINT32 Reserved_1_0:2 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :2 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_0020_STRUCT; + +// **** D0F0xE4_CORE_0010 Register Definition **** +// Address +#define D0F0xE4_CORE_0010_ADDRESS 0x10 + +// Type +#define D0F0xE4_CORE_0010_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_0010_HwInitWrLock_OFFSET 0 +#define D0F0xE4_CORE_0010_HwInitWrLock_WIDTH 1 +#define D0F0xE4_CORE_0010_HwInitWrLock_MASK 0x1 +#define D0F0xE4_CORE_0010_LcHotPlugDelSel_OFFSET 1 +#define D0F0xE4_CORE_0010_LcHotPlugDelSel_WIDTH 3 +#define D0F0xE4_CORE_0010_LcHotPlugDelSel_MASK 0xe +#define D0F0xE4_CORE_0010_Reserved_6_4_OFFSET 4 +#define D0F0xE4_CORE_0010_Reserved_6_4_WIDTH 3 +#define D0F0xE4_CORE_0010_Reserved_6_4_MASK 0x70 + +/// D0F0xE4_CORE_0010 +typedef union { + struct { ///< + UINT32 HwInitWrLock:1 ; ///< + UINT32 LcHotPlugDelSel:3 ; ///< + UINT32 Reserved_6_4:3 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :3 ; ///< + UINT32 :3 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :6 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_0010_STRUCT; + + +// **** D0F0x98_x0C Register Definition **** +// Address +#define D0F0x98_x0C_ADDRESS 0xc + +// Type +#define D0F0x98_x0C_TYPE TYPE_D0F0x98 +// Field Data +#define D0F0x98_x0C_GcmWrrLenA_OFFSET 0 +#define D0F0x98_x0C_GcmWrrLenA_WIDTH 8 +#define D0F0x98_x0C_GcmWrrLenA_MASK 0xff +#define D0F0x98_x0C_GcmWrrLenB_OFFSET 8 +#define D0F0x98_x0C_GcmWrrLenB_WIDTH 8 +#define D0F0x98_x0C_GcmWrrLenB_MASK 0xff00 +#define D0F0x98_x0C_Reserved_29_16_OFFSET 16 +#define D0F0x98_x0C_Reserved_29_16_WIDTH 14 +#define D0F0x98_x0C_Reserved_29_16_MASK 0x3fff0000 +#define D0F0x98_x0C_StrictSelWinnerEn_OFFSET 30 +#define D0F0x98_x0C_StrictSelWinnerEn_WIDTH 1 +#define D0F0x98_x0C_StrictSelWinnerEn_MASK 0x40000000 + +/// D0F0x98_x0C +typedef union { + struct { ///< + UINT32 GcmWrrLenA:8 ; ///< + UINT32 GcmWrrLenB:8 ; ///< + UINT32 Reserved_29_16:14; ///< + UINT32 StrictSelWinnerEn:1 ; ///< + UINT32 :1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_x0C_STRUCT; + + + + + + + + + + + + + + + + + + + + + +// **** D0F0xE4_WRAP_8063 Register Definition **** +// Address +#define D0F0xE4_WRAP_8063_ADDRESS 0x8063 + +// Type +#define D0F0xE4_WRAP_8063_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8063_Reserved_0_0_OFFSET 0 +#define D0F0xE4_WRAP_8063_Reserved_0_0_WIDTH 1 +#define D0F0xE4_WRAP_8063_Reserved_0_0_MASK 0x1 +#define D0F0xE4_WRAP_8063_Reserved_25_25_OFFSET 25 +#define D0F0xE4_WRAP_8063_Reserved_25_25_WIDTH 1 +#define D0F0xE4_WRAP_8063_Reserved_25_25_MASK 0x2000000 +#define D0F0xE4_WRAP_8063_Reserved_27_26_OFFSET 26 +#define D0F0xE4_WRAP_8063_Reserved_27_26_WIDTH 2 +#define D0F0xE4_WRAP_8063_Reserved_27_26_MASK 0xc000000 +#define D0F0xE4_WRAP_8063_Reserved_31_28_OFFSET 28 +#define D0F0xE4_WRAP_8063_Reserved_31_28_WIDTH 4 +#define D0F0xE4_WRAP_8063_Reserved_31_28_MASK 0xf0000000 + +/// D0F0xE4_WRAP_8063 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 line331:1 ; ///< + UINT32 line332:1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :2 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 line338:1 ; ///< + UINT32 line339:1 ; ///< + UINT32 line340:1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :2 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :2 ; ///< + UINT32 :1 ; ///< + UINT32 Reserved_25_25:1 ; ///< + UINT32 Reserved_27_26:2 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8063_STRUCT; + +// **** D0F0xE4_WRAP_8015 Register Definition **** +// Address +#define D0F0xE4_WRAP_8015_ADDRESS 0x8015 + +// Type +#define D0F0xE4_WRAP_8015_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8015_EnableD0StateReport_OFFSET 0 +#define D0F0xE4_WRAP_8015_EnableD0StateReport_WIDTH 1 +#define D0F0xE4_WRAP_8015_EnableD0StateReport_MASK 0x1 +#define D0F0xE4_WRAP_8015_Reserved_1_1_OFFSET 1 +#define D0F0xE4_WRAP_8015_Reserved_1_1_WIDTH 1 +#define D0F0xE4_WRAP_8015_Reserved_1_1_MASK 0x2 +#define D0F0xE4_WRAP_8015_SlowRefclkThroughTxclk2p5x_OFFSET 2 +#define D0F0xE4_WRAP_8015_SlowRefclkThroughTxclk2p5x_WIDTH 1 +#define D0F0xE4_WRAP_8015_SlowRefclkThroughTxclk2p5x_MASK 0x4 +#define D0F0xE4_WRAP_8015_SlowRefclkEnableTxclk2p5x_OFFSET 3 +#define D0F0xE4_WRAP_8015_SlowRefclkEnableTxclk2p5x_WIDTH 1 +#define D0F0xE4_WRAP_8015_SlowRefclkEnableTxclk2p5x_MASK 0x8 +#define D0F0xE4_WRAP_8015_SlowRefclkDivideTxclk2p5x_OFFSET 4 +#define D0F0xE4_WRAP_8015_SlowRefclkDivideTxclk2p5x_WIDTH 2 +#define D0F0xE4_WRAP_8015_SlowRefclkDivideTxclk2p5x_MASK 0x30 +#define D0F0xE4_WRAP_8015_SlowRefclkBurstTxclk2p5x_OFFSET 6 +#define D0F0xE4_WRAP_8015_SlowRefclkBurstTxclk2p5x_WIDTH 2 +#define D0F0xE4_WRAP_8015_SlowRefclkBurstTxclk2p5x_MASK 0xc0 +#define D0F0xE4_WRAP_8015_Reserved_8_8_OFFSET 8 +#define D0F0xE4_WRAP_8015_Reserved_8_8_WIDTH 1 +#define D0F0xE4_WRAP_8015_Reserved_8_8_MASK 0x100 +#define D0F0xE4_WRAP_8015_SlowRefclkLcntGateForce_OFFSET 9 +#define D0F0xE4_WRAP_8015_SlowRefclkLcntGateForce_WIDTH 1 +#define D0F0xE4_WRAP_8015_SlowRefclkLcntGateForce_MASK 0x200 +#define D0F0xE4_WRAP_8015_SlowRefclkThroughTxclk1x_OFFSET 10 +#define D0F0xE4_WRAP_8015_SlowRefclkThroughTxclk1x_WIDTH 1 +#define D0F0xE4_WRAP_8015_SlowRefclkThroughTxclk1x_MASK 0x400 +#define D0F0xE4_WRAP_8015_SlowRefclkEnableTxclk1x_OFFSET 11 +#define D0F0xE4_WRAP_8015_SlowRefclkEnableTxclk1x_WIDTH 1 +#define D0F0xE4_WRAP_8015_SlowRefclkEnableTxclk1x_MASK 0x800 +#define D0F0xE4_WRAP_8015_SlowRefclkDivideTxclk1x_OFFSET 12 +#define D0F0xE4_WRAP_8015_SlowRefclkDivideTxclk1x_WIDTH 2 +#define D0F0xE4_WRAP_8015_SlowRefclkDivideTxclk1x_MASK 0x3000 +#define D0F0xE4_WRAP_8015_SlowRefclkBurstTxclk1x_OFFSET 14 +#define D0F0xE4_WRAP_8015_SlowRefclkBurstTxclk1x_WIDTH 2 +#define D0F0xE4_WRAP_8015_SlowRefclkBurstTxclk1x_MASK 0xc000 +#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_OFFSET 16 +#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_MASK 0x3f0000 +#define D0F0xE4_WRAP_8015_Reserved_22_22_OFFSET 22 +#define D0F0xE4_WRAP_8015_Reserved_22_22_WIDTH 1 +#define D0F0xE4_WRAP_8015_Reserved_22_22_MASK 0x400000 +#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_OFFSET 23 +#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_MASK 0x800000 +#define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_OFFSET 24 +#define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_MASK 0x3f000000 +#define D0F0xE4_WRAP_8015_Reserved_30_30_OFFSET 30 +#define D0F0xE4_WRAP_8015_Reserved_30_30_WIDTH 1 +#define D0F0xE4_WRAP_8015_Reserved_30_30_MASK 0x40000000 +#define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_OFFSET 31 +#define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_MASK 0x80000000 + +/// D0F0xE4_WRAP_8015 +typedef union { + struct { ///< + UINT32 EnableD0StateReport:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 SlowRefclkThroughTxclk2p5x:1 ; ///< + UINT32 SlowRefclkEnableTxclk2p5x:1 ; ///< + UINT32 SlowRefclkDivideTxclk2p5x:2 ; ///< + UINT32 SlowRefclkBurstTxclk2p5x:2 ; ///< + UINT32 Reserved_8_8:1 ; ///< + UINT32 SlowRefclkLcntGateForce:1 ; ///< + UINT32 SlowRefclkThroughTxclk1x:1 ; ///< + UINT32 SlowRefclkEnableTxclk1x:1 ; ///< + UINT32 SlowRefclkDivideTxclk1x:2 ; ///< + UINT32 SlowRefclkBurstTxclk1x:2 ; ///< + UINT32 RefclkRegsGateLatency:6 ; ///< + UINT32 Reserved_22_22:1 ; ///< + UINT32 RefclkRegsGateEnable:1 ; ///< + UINT32 RefclkBphyGateLatency:6 ; ///< + UINT32 Reserved_30_30:1 ; ///< + UINT32 RefclkBphyGateEnable:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8015_STRUCT; + +// **** DxF0xE4_xB5 Register Definition **** +// Address +#define DxF0xE4_xB5_ADDRESS 0xb5 + +// Type +#define DxF0xE4_xB5_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_xB5_LcSelectDeemphasis_OFFSET 0 +#define DxF0xE4_xB5_LcSelectDeemphasis_WIDTH 1 +#define DxF0xE4_xB5_LcSelectDeemphasis_MASK 0x1 +#define DxF0xE4_xB5_LcSelectDeemphasisCntl_OFFSET 1 +#define DxF0xE4_xB5_LcSelectDeemphasisCntl_WIDTH 2 +#define DxF0xE4_xB5_LcSelectDeemphasisCntl_MASK 0x6 +#define DxF0xE4_xB5_LcRcvdDeemphasis_OFFSET 3 +#define DxF0xE4_xB5_LcRcvdDeemphasis_WIDTH 1 +#define DxF0xE4_xB5_LcRcvdDeemphasis_MASK 0x8 +#define DxF0xE4_xB5_Reserved_31_23_OFFSET 23 +#define DxF0xE4_xB5_Reserved_31_23_WIDTH 9 +#define DxF0xE4_xB5_Reserved_31_23_MASK 0xff800000 + +/// DxF0xE4_xB5 +typedef union { + struct { ///< + UINT32 LcSelectDeemphasis:1 ; ///< + UINT32 LcSelectDeemphasisCntl:2 ; ///< + UINT32 LcRcvdDeemphasis:1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :2 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 line519:1 ; ///< + UINT32 :1 ; ///< + UINT32 line521:2 ; ///< + UINT32 line522:2 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :2 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 Reserved_31_23:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_xB5_STRUCT; + + +// **** D0F0xE4_PHY_6006 Register Definition **** +// Address +#define D0F0xE4_PHY_6006_ADDRESS 0x6006 + +// Type +#define D0F0xE4_PHY_6006_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_6006_TxMarginNom_OFFSET 0 +#define D0F0xE4_PHY_6006_TxMarginNom_WIDTH 8 +#define D0F0xE4_PHY_6006_TxMarginNom_MASK 0xff +#define D0F0xE4_PHY_6006_DeemphGen1Nom_OFFSET 8 +#define D0F0xE4_PHY_6006_DeemphGen1Nom_WIDTH 8 +#define D0F0xE4_PHY_6006_DeemphGen1Nom_MASK 0xff00 +#define D0F0xE4_PHY_6006_Deemph35Gen2Nom_OFFSET 16 +#define D0F0xE4_PHY_6006_Deemph35Gen2Nom_WIDTH 8 +#define D0F0xE4_PHY_6006_Deemph35Gen2Nom_MASK 0xff0000 +#define D0F0xE4_PHY_6006_Deemph60Gen2Nom_OFFSET 24 +#define D0F0xE4_PHY_6006_Deemph60Gen2Nom_WIDTH 8 +#define D0F0xE4_PHY_6006_Deemph60Gen2Nom_MASK 0xff000000 + +/// D0F0xE4_PHY_6006 +typedef union { + struct { ///< + UINT32 TxMarginNom:8 ; ///< + UINT32 DeemphGen1Nom:8 ; ///< + UINT32 Deemph35Gen2Nom:8 ; ///< + UINT32 Deemph60Gen2Nom:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_6006_STRUCT; + + + +// **** D0F0x64_x1C Register Definition **** +// Address +#define D0F0x64_x1C_ADDRESS 0x1c + +// Type +#define D0F0x64_x1C_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x1C_WriteDis_OFFSET 0 +#define D0F0x64_x1C_WriteDis_WIDTH 1 +#define D0F0x64_x1C_WriteDis_MASK 0x1 +#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_OFFSET 1 +#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_WIDTH 1 +#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_MASK 0x2 +#define D0F0x64_x1C_F064BarEn_OFFSET 2 +#define D0F0x64_x1C_F064BarEn_WIDTH 1 +#define D0F0x64_x1C_F064BarEn_MASK 0x4 +#define D0F0x64_x1C_MemApSize_OFFSET 3 +#define D0F0x64_x1C_MemApSize_WIDTH 3 +#define D0F0x64_x1C_MemApSize_MASK 0x38 +#define D0F0x64_x1C_RegApSize_OFFSET 6 +#define D0F0x64_x1C_RegApSize_WIDTH 1 +#define D0F0x64_x1C_RegApSize_MASK 0x40 + +/// D0F0x64_x1C +typedef union { + struct { ///< + UINT32 WriteDis:1 ; ///< + UINT32 F0NonlegacyDeviceTypeEn:1 ; ///< + UINT32 F064BarEn:1 ; ///< + UINT32 MemApSize:3 ; ///< + UINT32 RegApSize:1 ; ///< + UINT32 /* DualfuncDisplayEn*/:1 ; ///< + UINT32 /* AudioEn*/:1 ; ///< + UINT32 /* MsiDis*/:1 ; ///< + UINT32 /* AudioNonlegacyDeviceTypeEn*/:1 ; ///< + UINT32 /* Audio64BarEn*/:1 ; ///< + UINT32 /* VgaDis*/:1 ; ///< + UINT32 /* FbAlwaysOn*/:1 ; ///< + UINT32 /* FbCplTypeSel*/:2 ; ///< + UINT32 /* IoBarDis*/:1 ; ///< + UINT32 /* F0En*/:1 ; ///< + UINT32 /* F0BarEn*/:1 ; ///< + UINT32 /* F1BarEn*/:1 ; ///< + UINT32 /* F2BarEn*/:1 ; ///< + UINT32 /* PcieDis*/:1 ; ///< + UINT32 /* BifBxcntlSpare0*/:1 ; ///< + UINT32 /* RcieEn*/:1 ; ///< + UINT32 /* BifBxcntlSpare*/:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x1C_STRUCT; + +// **** GMMx00 Register Definition **** +// Address +#define GMMx00_ADDRESS 0x0 + +// Type +#define GMMx00_TYPE TYPE_GMM +// Field Data +#define GMMx00_Offset_OFFSET 0 +#define GMMx00_Offset_WIDTH 31 +#define GMMx00_Offset_MASK 0x7fffffff +#define GMMx00_Aper_OFFSET 31 +#define GMMx00_Aper_WIDTH 1 +#define GMMx00_Aper_MASK 0x80000000 + +/// GMMx00 +typedef union { + struct { ///< + UINT32 Offset:31; ///< + UINT32 Aper:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx00_STRUCT; + +// **** GMMx04 Register Definition **** +// Address +#define GMMx04_ADDRESS 0x4 + +// Type +#define GMMx04_TYPE TYPE_GMM +// Field Data +#define GMMx04_Data_OFFSET 0 +#define GMMx04_Data_WIDTH 32 +#define GMMx04_Data_MASK 0xffffffff + +/// GMMx04 +typedef union { + struct { ///< + UINT32 Data:32; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx04_STRUCT; + + + +// **** D18F2x09C_x0D0FE00A Register Definition **** +// Address +#define D18F2x09C_x0D0FE00A_ADDRESS 0x0D0FE00A + +// Type +#define D18F2x09C_x0D0FE00A_TYPE TYPE_D18F2x9C +// Field Data +#define D18F2x09C_x0D0FE00A_Reserved_3_0_OFFSET 0 +#define D18F2x09C_x0D0FE00A_Reserved_3_0_WIDTH 4 +#define D18F2x09C_x0D0FE00A_Reserved_3_0_MASK 0xF +#define D18F2x09C_x0D0FE00A_SkewMemClk_OFFSET 4 +#define D18F2x09C_x0D0FE00A_SkewMemClk_WIDTH 1 +#define D18F2x09C_x0D0FE00A_SkewMemClk_MASK 0x10 +#define D18F2x09C_x0D0FE00A_Reserved_11_5_OFFSET 5 +#define D18F2x09C_x0D0FE00A_Reserved_11_5_WIDTH 7 +#define D18F2x09C_x0D0FE00A_Reserved_11_5_MASK 0xFE0 +#define D18F2x09C_x0D0FE00A_Reserved_31_15_OFFSET 15 +#define D18F2x09C_x0D0FE00A_Reserved_31_15_WIDTH 17 +#define D18F2x09C_x0D0FE00A_Reserved_31_15_MASK 0xFFFF8000 + +/// D18F2x09C_x0D0FE00A +typedef union { + struct { ///< + UINT32 Reserved_3_0:4; ///< + UINT32 SkewMemClk:1; ///< + UINT32 Reserved_11_5:7; ///< + UINT32 :2; ///< + UINT32 :1; ///< + UINT32 Reserved_31_15:17; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0FE00A_STRUCT; + +/// D0F0xE4_WRAP_8016 +typedef union { + struct { ///< + UINT32 CalibAckLatency:6 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 CalibDoneSelPifA:1 ; ///< + UINT32 Reserved_9_9:1 ; ///< + UINT32 Reserved_10_10:1 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 Gen1OnlyEngage:1 ; ///< + UINT32 Gen1OnlyEngaged:1 ; ///< + UINT32 Reserved_15_14:2 ; ///< + UINT32 LclkDynGateLatency:6 ; ///< + UINT32 LclkGateFree:1 ; ///< + UINT32 LclkDynGateEnable:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} ex688_STRUCT; + + + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbRegistersTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbRegistersTN.h new file mode 100644 index 0000000..fc9f9d6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbRegistersTN.h @@ -0,0 +1,41005 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Register definitions + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 64732 $ @e $Date: 2012-01-30 02:16:26 -0600 (Mon, 30 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _GNBREGISTERSTN_H_ +#define _GNBREGISTERSTN_H_ +#define TYPE_D0F0 0x1 +#define TYPE_D0F0x64 0x2 +#define TYPE_D0F0x98 0x3 +#define TYPE_D0F0xBC 0x4 +#define TYPE_D0F0xE4 0x5 +#define TYPE_DxF0 0x6 +#define TYPE_DxF0xE4 0x7 +#define TYPE_D0F2 0x8 +#define TYPE_D0F2xF4 0x9 +#define TYPE_D0F2xFC 0xa +#define TYPE_D18F1 0xb +#define TYPE_D18F2 0xc +#define TYPE_D18F3 0xd +#define TYPE_D18F4 0xe +#define TYPE_D18F5 0xf +#define TYPE_MSR 0x10 +#define TYPE_D1F0 0x11 +#define TYPE_GMM 0x12 +#define TYPE_D18F2x9C_dct0 0x13 +#define TYPE_D18F2x9C_dct0_mp0 0x14 +#define TYPE_D18F2x9C_dct0_mp1 0x15 +#define TYPE_D18F2x9C_dct1 0x16 +#define TYPE_D18F2x9C_dct1_mp0 0x17 +#define TYPE_D18F2x9C_dct1_mp1 0x18 +#define TYPE_D18F2_dct0 0x19 +#define TYPE_D18F2_dct1 0x1a +#define TYPE_D18F2_dct0_mp0 0x1b +#define TYPE_D18F2_dct0_mp1 0x1c +#define TYPE_D1F1 0x1d +#define TYPE_D18F2_dct1_mp0 0x1e +#define TYPE_D18F2_dct1_mp1 0x1f +#define TYPE_CGIND 0x20 +#define TYPE_SMU_MSG 0x21 + +#ifndef WRAP_SPACE + #define WRAP_SPACE(w, x) (0x01300000 | (w << 16) | (x)) +#endif +#ifndef CORE_SPACE + #define CORE_SPACE(c, x) (0x00010000 | (c << 24) | (x)) +#endif +#ifndef PHY_SPACE + #define PHY_SPACE(w, p, x) (0x00200000 | ((p + 1) << 24) | (w << 16) | (x)) +#endif +#ifndef PIF_SPACE + #define PIF_SPACE(w, p, x) (0x00100000 | ((p + 1) << 24) | (w << 16) | (x)) +#endif + +#define L1_SEL_GFX 0 +#define L1_SEL_GPPSB 1 +#define L1_SEL_GBIF 2 +#define L1_SEL_INTGEN 3 + +#define SMU_MSG_TYPE TYPE_SMU_MSG +#define SMC_MSG_FIRMWARE_AUTH 0 +#define SMC_MSG_HALT 1 +#define SMC_MSG_PHY_LN_OFF 2 +#define SMC_MSG_PHY_LN_ON 3 +#define SMC_MSG_DDI_PHY_OFF 4 +#define SMC_MSG_DDI_PHY_ON 5 +#define SMC_MSG_CASCADE_PLL_OFF 6 +#define SMC_MSG_CASCADE_PLL_ON 7 +#define SMC_MSG_PWR_OFF_x16 8 +#define SMC_MSG_CONFIG_LCLK_DPM 9 +#define SMC_MSG_FLUSH_DATA_CACHE 10 +#define SMC_MSG_FLUSH_INSTRUCTION_CACHE 11 +#define SMC_MSG_CONFIG_VPC_ACCUMULATOR 12 +#define SMC_MSG_CONFIG_BAPM 13 +#define SMC_MSG_CONFIG_TDC_LIMIT 14 +#define SMC_MSG_CONFIG_LPMx 15 +#define SMC_MSG_CONFIG_HTC_LIMIT 16 +#define SMC_MSG_CONFIG_THERMAL_CNTL 17 +#define SMC_MSG_CONFIG_VOLTAGE_CNTL 18 +#define SMC_MSG_CONFIG_TDP_CNTL 19 +#define SMC_MSG_EN_PM_CNTL 20 +#define SMC_MSG_DIS_PM_CNTL 21 +#define SMC_MSG_CONFIG_NBDPM 22 +#define SMC_MSG_CONFIG_LOADLINE 23 +#define SMC_MSG_ADJUST_LOADLINE 24 +#define SMC_MSG_RECONFIGURE 25 +#define SMC_MSG_PCIE_PLLSWITCH 27 +#define SMC_MSG_ENABLE_BAPM 32 +#define SMC_MSG_DISABLE_BAPM 33 + +// **** D0F0x00 Register Definition **** +// Address +#define D0F0x00_ADDRESS 0x0 + +// Type +#define D0F0x00_TYPE TYPE_D0F0 +// Field Data +#define D0F0x00_VendorID_OFFSET 0 +#define D0F0x00_VendorID_WIDTH 16 +#define D0F0x00_VendorID_MASK 0xffff +#define D0F0x00_DeviceID_OFFSET 16 +#define D0F0x00_DeviceID_WIDTH 16 +#define D0F0x00_DeviceID_MASK 0xffff0000 + +/// D0F0x00 +typedef union { + struct { ///< + UINT32 VendorID:16; ///< + UINT32 DeviceID:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x00_STRUCT; + +// **** D0F0x04 Register Definition **** +// Address +#define D0F0x04_ADDRESS 0x4 + +// Type +#define D0F0x04_TYPE TYPE_D0F0 +// Field Data +#define D0F0x04_IoAccessEn_OFFSET 0 +#define D0F0x04_IoAccessEn_WIDTH 1 +#define D0F0x04_IoAccessEn_MASK 0x1 +#define D0F0x04_MemAccessEn_OFFSET 1 +#define D0F0x04_MemAccessEn_WIDTH 1 +#define D0F0x04_MemAccessEn_MASK 0x2 +#define D0F0x04_BusMasterEn_OFFSET 2 +#define D0F0x04_BusMasterEn_WIDTH 1 +#define D0F0x04_BusMasterEn_MASK 0x4 +#define D0F0x04_SpecialCycleEn_OFFSET 3 +#define D0F0x04_SpecialCycleEn_WIDTH 1 +#define D0F0x04_SpecialCycleEn_MASK 0x8 +#define D0F0x04_MemWriteInvalidateEn_OFFSET 4 +#define D0F0x04_MemWriteInvalidateEn_WIDTH 1 +#define D0F0x04_MemWriteInvalidateEn_MASK 0x10 +#define D0F0x04_PalSnoopEn_OFFSET 5 +#define D0F0x04_PalSnoopEn_WIDTH 1 +#define D0F0x04_PalSnoopEn_MASK 0x20 +#define D0F0x04_ParityErrorEn_OFFSET 6 +#define D0F0x04_ParityErrorEn_WIDTH 1 +#define D0F0x04_ParityErrorEn_MASK 0x40 +#define D0F0x04_Reserved_7_7_OFFSET 7 +#define D0F0x04_Reserved_7_7_WIDTH 1 +#define D0F0x04_Reserved_7_7_MASK 0x80 +#define D0F0x04_SerrEn_OFFSET 8 +#define D0F0x04_SerrEn_WIDTH 1 +#define D0F0x04_SerrEn_MASK 0x100 +#define D0F0x04_FastB2BEn_OFFSET 9 +#define D0F0x04_FastB2BEn_WIDTH 1 +#define D0F0x04_FastB2BEn_MASK 0x200 +#define D0F0x04_Reserved_19_10_OFFSET 10 +#define D0F0x04_Reserved_19_10_WIDTH 10 +#define D0F0x04_Reserved_19_10_MASK 0xffc00 +#define D0F0x04_CapList_OFFSET 20 +#define D0F0x04_CapList_WIDTH 1 +#define D0F0x04_CapList_MASK 0x100000 +#define D0F0x04_PCI66En_OFFSET 21 +#define D0F0x04_PCI66En_WIDTH 1 +#define D0F0x04_PCI66En_MASK 0x200000 +#define D0F0x04_Reserved_22_22_OFFSET 22 +#define D0F0x04_Reserved_22_22_WIDTH 1 +#define D0F0x04_Reserved_22_22_MASK 0x400000 +#define D0F0x04_FastBackCapable_OFFSET 23 +#define D0F0x04_FastBackCapable_WIDTH 1 +#define D0F0x04_FastBackCapable_MASK 0x800000 +#define D0F0x04_Reserved_24_24_OFFSET 24 +#define D0F0x04_Reserved_24_24_WIDTH 1 +#define D0F0x04_Reserved_24_24_MASK 0x1000000 +#define D0F0x04_DevselTiming_OFFSET 25 +#define D0F0x04_DevselTiming_WIDTH 2 +#define D0F0x04_DevselTiming_MASK 0x6000000 +#define D0F0x04_SignalTargetAbort_OFFSET 27 +#define D0F0x04_SignalTargetAbort_WIDTH 1 +#define D0F0x04_SignalTargetAbort_MASK 0x8000000 +#define D0F0x04_ReceivedTargetAbort_OFFSET 28 +#define D0F0x04_ReceivedTargetAbort_WIDTH 1 +#define D0F0x04_ReceivedTargetAbort_MASK 0x10000000 +#define D0F0x04_ReceivedMasterAbort_OFFSET 29 +#define D0F0x04_ReceivedMasterAbort_WIDTH 1 +#define D0F0x04_ReceivedMasterAbort_MASK 0x20000000 +#define D0F0x04_SignaledSystemError_OFFSET 30 +#define D0F0x04_SignaledSystemError_WIDTH 1 +#define D0F0x04_SignaledSystemError_MASK 0x40000000 +#define D0F0x04_ParityErrorDetected_OFFSET 31 +#define D0F0x04_ParityErrorDetected_WIDTH 1 +#define D0F0x04_ParityErrorDetected_MASK 0x80000000 + +/// D0F0x04 +typedef union { + struct { ///< + UINT32 IoAccessEn:1 ; ///< + UINT32 MemAccessEn:1 ; ///< + UINT32 BusMasterEn:1 ; ///< + UINT32 SpecialCycleEn:1 ; ///< + UINT32 MemWriteInvalidateEn:1 ; ///< + UINT32 PalSnoopEn:1 ; ///< + UINT32 ParityErrorEn:1 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 SerrEn:1 ; ///< + UINT32 FastB2BEn:1 ; ///< + UINT32 Reserved_19_10:10; ///< + UINT32 CapList:1 ; ///< + UINT32 PCI66En:1 ; ///< + UINT32 Reserved_22_22:1 ; ///< + UINT32 FastBackCapable:1 ; ///< + UINT32 Reserved_24_24:1 ; ///< + UINT32 DevselTiming:2 ; ///< + UINT32 SignalTargetAbort:1 ; ///< + UINT32 ReceivedTargetAbort:1 ; ///< + UINT32 ReceivedMasterAbort:1 ; ///< + UINT32 SignaledSystemError:1 ; ///< + UINT32 ParityErrorDetected:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x04_STRUCT; + +// **** D0F0x08 Register Definition **** +// Address +#define D0F0x08_ADDRESS 0x8 + +// Type +#define D0F0x08_TYPE TYPE_D0F0 +// Field Data +#define D0F0x08_RevID_OFFSET 0 +#define D0F0x08_RevID_WIDTH 8 +#define D0F0x08_RevID_MASK 0xff +#define D0F0x08_ClassCode_OFFSET 8 +#define D0F0x08_ClassCode_WIDTH 24 +#define D0F0x08_ClassCode_MASK 0xffffff00 + +/// D0F0x08 +typedef union { + struct { ///< + UINT32 RevID:8 ; ///< + UINT32 ClassCode:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x08_STRUCT; + +// **** D0F0x0C Register Definition **** +// Address +#define D0F0x0C_ADDRESS 0xc + +// Type +#define D0F0x0C_TYPE TYPE_D0F0 +// Field Data +#define D0F0x0C_CacheLineSize_OFFSET 0 +#define D0F0x0C_CacheLineSize_WIDTH 8 +#define D0F0x0C_CacheLineSize_MASK 0xff +#define D0F0x0C_LatencyTimer_OFFSET 8 +#define D0F0x0C_LatencyTimer_WIDTH 8 +#define D0F0x0C_LatencyTimer_MASK 0xff00 +#define D0F0x0C_HeaderTypeReg_OFFSET 16 +#define D0F0x0C_HeaderTypeReg_WIDTH 8 +#define D0F0x0C_HeaderTypeReg_MASK 0xff0000 +#define D0F0x0C_BIST_OFFSET 24 +#define D0F0x0C_BIST_WIDTH 8 +#define D0F0x0C_BIST_MASK 0xff000000 + +/// D0F0x0C +typedef union { + struct { ///< + UINT32 CacheLineSize:8 ; ///< + UINT32 LatencyTimer:8 ; ///< + UINT32 HeaderTypeReg:8 ; ///< + UINT32 BIST:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x0C_STRUCT; + +// **** D0F0x2C Register Definition **** +// Address +#define D0F0x2C_ADDRESS 0x2c + +// Type +#define D0F0x2C_TYPE TYPE_D0F0 +// Field Data +#define D0F0x2C_SubsystemVendorID_OFFSET 0 +#define D0F0x2C_SubsystemVendorID_WIDTH 16 +#define D0F0x2C_SubsystemVendorID_MASK 0xffff +#define D0F0x2C_SubsystemID_OFFSET 16 +#define D0F0x2C_SubsystemID_WIDTH 16 +#define D0F0x2C_SubsystemID_MASK 0xffff0000 + +/// D0F0x2C +typedef union { + struct { ///< + UINT32 SubsystemVendorID:16; ///< + UINT32 SubsystemID:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x2C_STRUCT; + +// **** D0F0x34 Register Definition **** +// Address +#define D0F0x34_ADDRESS 0x34 + +// Type +#define D0F0x34_TYPE TYPE_D0F0 +// Field Data +#define D0F0x34_CapPtr_OFFSET 0 +#define D0F0x34_CapPtr_WIDTH 8 +#define D0F0x34_CapPtr_MASK 0xff +#define D0F0x34_Reserved_31_8_OFFSET 8 +#define D0F0x34_Reserved_31_8_WIDTH 24 +#define D0F0x34_Reserved_31_8_MASK 0xffffff00 + +/// D0F0x34 +typedef union { + struct { ///< + UINT32 CapPtr:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x34_STRUCT; + +// **** D0F0x4C Register Definition **** +// Address +#define D0F0x4C_ADDRESS 0x4c + +// Type +#define D0F0x4C_TYPE TYPE_D0F0 +// Field Data +#define D0F0x4C_Function1Enable_OFFSET 0 +#define D0F0x4C_Function1Enable_WIDTH 1 +#define D0F0x4C_Function1Enable_MASK 0x1 +#define D0F0x4C_ApicEnable_OFFSET 1 +#define D0F0x4C_ApicEnable_WIDTH 1 +#define D0F0x4C_ApicEnable_MASK 0x2 +#define D0F0x4C_Reserved_2_2_OFFSET 2 +#define D0F0x4C_Reserved_2_2_WIDTH 1 +#define D0F0x4C_Reserved_2_2_MASK 0x4 +#define D0F0x4C_Cf8Dis_OFFSET 3 +#define D0F0x4C_Cf8Dis_WIDTH 1 +#define D0F0x4C_Cf8Dis_MASK 0x8 +#define D0F0x4C_PMEDis_OFFSET 4 +#define D0F0x4C_PMEDis_WIDTH 1 +#define D0F0x4C_PMEDis_MASK 0x10 +#define D0F0x4C_SerrDis_OFFSET 5 +#define D0F0x4C_SerrDis_WIDTH 1 +#define D0F0x4C_SerrDis_MASK 0x20 +#define D0F0x4C_Reserved_10_6_OFFSET 6 +#define D0F0x4C_Reserved_10_6_WIDTH 5 +#define D0F0x4C_Reserved_10_6_MASK 0x7c0 +#define D0F0x4C_CRS_OFFSET 11 +#define D0F0x4C_CRS_WIDTH 1 +#define D0F0x4C_CRS_MASK 0x800 +#define D0F0x4C_CfgRdTime_OFFSET 12 +#define D0F0x4C_CfgRdTime_WIDTH 3 +#define D0F0x4C_CfgRdTime_MASK 0x7000 +#define D0F0x4C_Reserved_22_15_OFFSET 15 +#define D0F0x4C_Reserved_22_15_WIDTH 8 +#define D0F0x4C_Reserved_22_15_MASK 0x7f8000 +#define D0F0x4C_MMIOEnable_OFFSET 23 +#define D0F0x4C_MMIOEnable_WIDTH 1 +#define D0F0x4C_MMIOEnable_MASK 0x800000 +#define D0F0x4C_Reserved_25_24_OFFSET 24 +#define D0F0x4C_Reserved_25_24_WIDTH 2 +#define D0F0x4C_Reserved_25_24_MASK 0x3000000 +#define D0F0x4C_HPDis_OFFSET 26 +#define D0F0x4C_HPDis_WIDTH 1 +#define D0F0x4C_HPDis_MASK 0x4000000 +#define D0F0x4C_Reserved_31_27_OFFSET 27 +#define D0F0x4C_Reserved_31_27_WIDTH 5 +#define D0F0x4C_Reserved_31_27_MASK 0xf8000000 + +/// D0F0x4C +typedef union { + struct { ///< + UINT32 Function1Enable:1 ; ///< + UINT32 ApicEnable:1 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 Cf8Dis:1 ; ///< + UINT32 PMEDis:1 ; ///< + UINT32 SerrDis:1 ; ///< + UINT32 Reserved_10_6:5 ; ///< + UINT32 CRS:1 ; ///< + UINT32 CfgRdTime:3 ; ///< + UINT32 Reserved_22_15:8 ; ///< + UINT32 MMIOEnable:1 ; ///< + UINT32 Reserved_25_24:2 ; ///< + UINT32 HPDis:1 ; ///< + UINT32 Reserved_31_27:5 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x4C_STRUCT; + +// **** D0F0x60 Register Definition **** +// Address +#define D0F0x60_ADDRESS 0x60 + +// Type +#define D0F0x60_TYPE TYPE_D0F0 +// Field Data +#define D0F0x60_MiscIndAddr_OFFSET 0 +#define D0F0x60_MiscIndAddr_WIDTH 7 +#define D0F0x60_MiscIndAddr_MASK 0x7f +#define D0F0x60_MiscIndWrEn_OFFSET 7 +#define D0F0x60_MiscIndWrEn_WIDTH 1 +#define D0F0x60_MiscIndWrEn_MASK 0x80 +#define D0F0x60_Reserved_31_8_OFFSET 8 +#define D0F0x60_Reserved_31_8_WIDTH 24 +#define D0F0x60_Reserved_31_8_MASK 0xffffff00 + +/// D0F0x60 +typedef union { + struct { ///< + UINT32 MiscIndAddr:7 ; ///< + UINT32 MiscIndWrEn:1 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x60_STRUCT; + +// **** D0F0x64 Register Definition **** +// Address +#define D0F0x64_ADDRESS 0x64 + +// Type +#define D0F0x64_TYPE TYPE_D0F0 +// Field Data +#define D0F0x64_MiscIndData_OFFSET 0 +#define D0F0x64_MiscIndData_WIDTH 32 +#define D0F0x64_MiscIndData_MASK 0xffffffff + +/// D0F0x64 +typedef union { + struct { ///< + UINT32 MiscIndData:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_STRUCT; + +// **** D0F0x7C Register Definition **** +// Address +#define D0F0x7C_ADDRESS 0x7c + +// Type +#define D0F0x7C_TYPE TYPE_D0F0 +// Field Data +#define D0F0x7C_ForceIntGFXDisable_OFFSET 0 +#define D0F0x7C_ForceIntGFXDisable_WIDTH 1 +#define D0F0x7C_ForceIntGFXDisable_MASK 0x1 +#define D0F0x7C_Reserved_31_1_OFFSET 1 +#define D0F0x7C_Reserved_31_1_WIDTH 31 +#define D0F0x7C_Reserved_31_1_MASK 0xfffffffe + +/// D0F0x7C +typedef union { + struct { ///< + UINT32 ForceIntGFXDisable:1 ; ///< + UINT32 Reserved_31_1:31; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x7C_STRUCT; + +// **** D0F0x84 Register Definition **** +// Address +#define D0F0x84_ADDRESS 0x84 + +// Type +#define D0F0x84_TYPE TYPE_D0F0 +// Field Data +#define D0F0x84_Reserved_2_0_OFFSET 0 +#define D0F0x84_Reserved_2_0_WIDTH 3 +#define D0F0x84_Reserved_2_0_MASK 0x7 +#define D0F0x84_VgaHole_OFFSET 3 +#define D0F0x84_VgaHole_WIDTH 1 +#define D0F0x84_VgaHole_MASK 0x8 +#define D0F0x84_Ev6Mode_OFFSET 4 +#define D0F0x84_Ev6Mode_WIDTH 1 +#define D0F0x84_Ev6Mode_MASK 0x10 +#define D0F0x84_Reserved_7_5_OFFSET 5 +#define D0F0x84_Reserved_7_5_WIDTH 3 +#define D0F0x84_Reserved_7_5_MASK 0xe0 +#define D0F0x84_PmeMode_OFFSET 8 +#define D0F0x84_PmeMode_WIDTH 1 +#define D0F0x84_PmeMode_MASK 0x100 +#define D0F0x84_PmeTurnOff_OFFSET 9 +#define D0F0x84_PmeTurnOff_WIDTH 1 +#define D0F0x84_PmeTurnOff_MASK 0x200 +#define D0F0x84_Reserved_31_10_OFFSET 10 +#define D0F0x84_Reserved_31_10_WIDTH 22 +#define D0F0x84_Reserved_31_10_MASK 0xfffffc00 + +/// D0F0x84 +typedef union { + struct { ///< + UINT32 Reserved_2_0:3 ; ///< + UINT32 VgaHole:1 ; ///< + UINT32 Ev6Mode:1 ; ///< + UINT32 Reserved_7_5:3 ; ///< + UINT32 PmeMode:1 ; ///< + UINT32 PmeTurnOff:1 ; ///< + UINT32 Reserved_31_10:22; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x84_STRUCT; + +// **** D0F0x90 Register Definition **** +// Address +#define D0F0x90_ADDRESS 0x90 + +// Type +#define D0F0x90_TYPE TYPE_D0F0 +// Field Data +#define D0F0x90_Reserved_22_0_OFFSET 0 +#define D0F0x90_Reserved_22_0_WIDTH 23 +#define D0F0x90_Reserved_22_0_MASK 0x7fffff +#define D0F0x90_TopOfDram_OFFSET 23 +#define D0F0x90_TopOfDram_WIDTH 9 +#define D0F0x90_TopOfDram_MASK 0xff800000 + +/// D0F0x90 +typedef union { + struct { ///< + UINT32 Reserved_22_0:23; ///< + UINT32 TopOfDram:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x90_STRUCT; + +// **** D0F0x94 Register Definition **** +// Address +#define D0F0x94_ADDRESS 0x94 + +// Type +#define D0F0x94_TYPE TYPE_D0F0 +// Field Data +#define D0F0x94_OrbIndAddr_OFFSET 0 +#define D0F0x94_OrbIndAddr_WIDTH 7 +#define D0F0x94_OrbIndAddr_MASK 0x7f +#define D0F0x94_Reserved_7_7_OFFSET 7 +#define D0F0x94_Reserved_7_7_WIDTH 1 +#define D0F0x94_Reserved_7_7_MASK 0x80 +#define D0F0x94_OrbIndWrEn_OFFSET 8 +#define D0F0x94_OrbIndWrEn_WIDTH 1 +#define D0F0x94_OrbIndWrEn_MASK 0x100 +#define D0F0x94_Reserved_31_9_OFFSET 9 +#define D0F0x94_Reserved_31_9_WIDTH 23 +#define D0F0x94_Reserved_31_9_MASK 0xfffffe00 + +/// D0F0x94 +typedef union { + struct { ///< + UINT32 OrbIndAddr:7 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 OrbIndWrEn:1 ; ///< + UINT32 Reserved_31_9:23; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x94_STRUCT; + +// **** D0F0x98 Register Definition **** +// Address +#define D0F0x98_ADDRESS 0x98 + +// Type +#define D0F0x98_TYPE TYPE_D0F0 +// Field Data +#define D0F0x98_OrbIndData_OFFSET 0 +#define D0F0x98_OrbIndData_WIDTH 32 +#define D0F0x98_OrbIndData_MASK 0xffffffff + +/// D0F0x98 +typedef union { + struct { ///< + UINT32 OrbIndData:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_STRUCT; + +// **** D0F0xB8 Register Definition **** +// Address +#define D0F0xB8_ADDRESS 0xb8 + +// Type +#define D0F0xB8_TYPE TYPE_D0F0 +// Field Data +#define D0F0xB8_NbSmuIndAddr_OFFSET 0 +#define D0F0xB8_NbSmuIndAddr_WIDTH 32 +#define D0F0xB8_NbSmuIndAddr_MASK 0xffffffff + +/// D0F0xB8 +typedef union { + struct { ///< + UINT32 NbSmuIndAddr:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xB8_STRUCT; + +// **** D0F0xBC Register Definition **** +// Address +#define D0F0xBC_ADDRESS 0xbc + +// Type +#define D0F0xBC_TYPE TYPE_D0F0 +// Field Data +#define D0F0xBC_NbSmuIndData_OFFSET 0 +#define D0F0xBC_NbSmuIndData_WIDTH 32 +#define D0F0xBC_NbSmuIndData_MASK 0xffffffff + +/// D0F0xBC +typedef union { + struct { ///< + UINT32 NbSmuIndData:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_STRUCT; + +// **** D0F0xE0 Register Definition **** +// Address +#define D0F0xE0_ADDRESS 0xe0 + +// Type +#define D0F0xE0_TYPE TYPE_D0F0 +// Field Data +#define D0F0xE0_PcieIndxAddr_OFFSET 0 +#define D0F0xE0_PcieIndxAddr_WIDTH 16 +#define D0F0xE0_PcieIndxAddr_MASK 0xffff +#define D0F0xE0_FrameType_OFFSET 16 +#define D0F0xE0_FrameType_WIDTH 8 +#define D0F0xE0_FrameType_MASK 0xff0000 +#define D0F0xE0_BlockSelect_OFFSET 24 +#define D0F0xE0_BlockSelect_WIDTH 8 +#define D0F0xE0_BlockSelect_MASK 0xff000000 + +/// D0F0xE0 +typedef union { + struct { ///< + UINT32 PcieIndxAddr:16; ///< + UINT32 FrameType:8 ; ///< + UINT32 BlockSelect:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE0_STRUCT; + +// **** D0F0xE4 Register Definition **** +// Address +#define D0F0xE4_ADDRESS 0xe4 + +// Type +#define D0F0xE4_TYPE TYPE_D0F0 +// Field Data +#define D0F0xE4_PcieIndxData_OFFSET 0 +#define D0F0xE4_PcieIndxData_WIDTH 32 +#define D0F0xE4_PcieIndxData_MASK 0xffffffff + +/// D0F0xE4 +typedef union { + struct { ///< + UINT32 PcieIndxData:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_STRUCT; + +// **** D0F2x00 Register Definition **** +// Address +#define D0F2x00_ADDRESS 0x0 + +// Type +#define D0F2x00_TYPE TYPE_D0F2 +// Field Data +#define D0F2x00_VendorId_OFFSET 0 +#define D0F2x00_VendorId_WIDTH 16 +#define D0F2x00_VendorId_MASK 0xffff +#define D0F2x00_DeviceId_OFFSET 16 +#define D0F2x00_DeviceId_WIDTH 16 +#define D0F2x00_DeviceId_MASK 0xffff0000 + +/// D0F2x00 +typedef union { + struct { ///< + UINT32 VendorId:16; ///< + UINT32 DeviceId:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2x00_STRUCT; + +// **** D0F2x04 Register Definition **** +// Address +#define D0F2x04_ADDRESS 0x4 + +// Type +#define D0F2x04_TYPE TYPE_D0F2 +// Field Data +#define D0F2x04_IoAccessEn_OFFSET 0 +#define D0F2x04_IoAccessEn_WIDTH 1 +#define D0F2x04_IoAccessEn_MASK 0x1 +#define D0F2x04_MemAccessEn_OFFSET 1 +#define D0F2x04_MemAccessEn_WIDTH 1 +#define D0F2x04_MemAccessEn_MASK 0x2 +#define D0F2x04_BusMasterEn_OFFSET 2 +#define D0F2x04_BusMasterEn_WIDTH 1 +#define D0F2x04_BusMasterEn_MASK 0x4 +#define D0F2x04_Reserved_5_3_OFFSET 3 +#define D0F2x04_Reserved_5_3_WIDTH 3 +#define D0F2x04_Reserved_5_3_MASK 0x38 +#define D0F2x04_ParityErrorEn_OFFSET 6 +#define D0F2x04_ParityErrorEn_WIDTH 1 +#define D0F2x04_ParityErrorEn_MASK 0x40 +#define D0F2x04_Reserved_7_7_OFFSET 7 +#define D0F2x04_Reserved_7_7_WIDTH 1 +#define D0F2x04_Reserved_7_7_MASK 0x80 +#define D0F2x04_SerrEn_OFFSET 8 +#define D0F2x04_SerrEn_WIDTH 1 +#define D0F2x04_SerrEn_MASK 0x100 +#define D0F2x04_Reserved_9_9_OFFSET 9 +#define D0F2x04_Reserved_9_9_WIDTH 1 +#define D0F2x04_Reserved_9_9_MASK 0x200 +#define D0F2x04_InterruptDis_OFFSET 10 +#define D0F2x04_InterruptDis_WIDTH 1 +#define D0F2x04_InterruptDis_MASK 0x400 +#define D0F2x04_Reserved_18_11_OFFSET 11 +#define D0F2x04_Reserved_18_11_WIDTH 8 +#define D0F2x04_Reserved_18_11_MASK 0x7f800 +#define D0F2x04_IntStatus_OFFSET 19 +#define D0F2x04_IntStatus_WIDTH 1 +#define D0F2x04_IntStatus_MASK 0x80000 +#define D0F2x04_CapList_OFFSET 20 +#define D0F2x04_CapList_WIDTH 1 +#define D0F2x04_CapList_MASK 0x100000 +#define D0F2x04_Reserved_23_21_OFFSET 21 +#define D0F2x04_Reserved_23_21_WIDTH 3 +#define D0F2x04_Reserved_23_21_MASK 0xe00000 +#define D0F2x04_MasterDataError_OFFSET 24 +#define D0F2x04_MasterDataError_WIDTH 1 +#define D0F2x04_MasterDataError_MASK 0x1000000 +#define D0F2x04_Reserved_26_25_OFFSET 25 +#define D0F2x04_Reserved_26_25_WIDTH 2 +#define D0F2x04_Reserved_26_25_MASK 0x6000000 +#define D0F2x04_SignalTargetAbort_OFFSET 27 +#define D0F2x04_SignalTargetAbort_WIDTH 1 +#define D0F2x04_SignalTargetAbort_MASK 0x8000000 +#define D0F2x04_ReceivedTargetAbort_OFFSET 28 +#define D0F2x04_ReceivedTargetAbort_WIDTH 1 +#define D0F2x04_ReceivedTargetAbort_MASK 0x10000000 +#define D0F2x04_ReceivedMasterAbort_OFFSET 29 +#define D0F2x04_ReceivedMasterAbort_WIDTH 1 +#define D0F2x04_ReceivedMasterAbort_MASK 0x20000000 +#define D0F2x04_SignaledSystemError_OFFSET 30 +#define D0F2x04_SignaledSystemError_WIDTH 1 +#define D0F2x04_SignaledSystemError_MASK 0x40000000 +#define D0F2x04_ParityErrorDetected_OFFSET 31 +#define D0F2x04_ParityErrorDetected_WIDTH 1 +#define D0F2x04_ParityErrorDetected_MASK 0x80000000 + +/// D0F2x04 +typedef union { + struct { ///< + UINT32 IoAccessEn:1 ; ///< + UINT32 MemAccessEn:1 ; ///< + UINT32 BusMasterEn:1 ; ///< + UINT32 Reserved_5_3:3 ; ///< + UINT32 ParityErrorEn:1 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 SerrEn:1 ; ///< + UINT32 Reserved_9_9:1 ; ///< + UINT32 InterruptDis:1 ; ///< + UINT32 Reserved_18_11:8 ; ///< + UINT32 IntStatus:1 ; ///< + UINT32 CapList:1 ; ///< + UINT32 Reserved_23_21:3 ; ///< + UINT32 MasterDataError:1 ; ///< + UINT32 Reserved_26_25:2 ; ///< + UINT32 SignalTargetAbort:1 ; ///< + UINT32 ReceivedTargetAbort:1 ; ///< + UINT32 ReceivedMasterAbort:1 ; ///< + UINT32 SignaledSystemError:1 ; ///< + UINT32 ParityErrorDetected:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2x04_STRUCT; + +// **** D0F2x08 Register Definition **** +// Address +#define D0F2x08_ADDRESS 0x8 + +// Type +#define D0F2x08_TYPE TYPE_D0F2 +// Field Data +#define D0F2x08_RevID_OFFSET 0 +#define D0F2x08_RevID_WIDTH 8 +#define D0F2x08_RevID_MASK 0xff +#define D0F2x08_ClassCode_OFFSET 8 +#define D0F2x08_ClassCode_WIDTH 24 +#define D0F2x08_ClassCode_MASK 0xffffff00 + +/// D0F2x08 +typedef union { + struct { ///< + UINT32 RevID:8 ; ///< + UINT32 ClassCode:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2x08_STRUCT; + +// **** D0F2x0C Register Definition **** +// Address +#define D0F2x0C_ADDRESS 0xc + +// Type +#define D0F2x0C_TYPE TYPE_D0F2 +// Field Data +#define D0F2x0C_CacheLineSize_OFFSET 0 +#define D0F2x0C_CacheLineSize_WIDTH 8 +#define D0F2x0C_CacheLineSize_MASK 0xff +#define D0F2x0C_LatencyTimer_OFFSET 8 +#define D0F2x0C_LatencyTimer_WIDTH 8 +#define D0F2x0C_LatencyTimer_MASK 0xff00 +#define D0F2x0C_HeaderTypeReg_OFFSET 16 +#define D0F2x0C_HeaderTypeReg_WIDTH 8 +#define D0F2x0C_HeaderTypeReg_MASK 0xff0000 +#define D0F2x0C_BIST_OFFSET 24 +#define D0F2x0C_BIST_WIDTH 8 +#define D0F2x0C_BIST_MASK 0xff000000 + +/// D0F2x0C +typedef union { + struct { ///< + UINT32 CacheLineSize:8 ; ///< + UINT32 LatencyTimer:8 ; ///< + UINT32 HeaderTypeReg:8 ; ///< + UINT32 BIST:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2x0C_STRUCT; + +// **** D0F2x2C Register Definition **** +// Address +#define D0F2x2C_ADDRESS 0x2c + +// Type +#define D0F2x2C_TYPE TYPE_D0F2 +// Field Data +#define D0F2x2C_SubsystemVendorId_OFFSET 0 +#define D0F2x2C_SubsystemVendorId_WIDTH 16 +#define D0F2x2C_SubsystemVendorId_MASK 0xffff +#define D0F2x2C_SubsystemId_OFFSET 16 +#define D0F2x2C_SubsystemId_WIDTH 16 +#define D0F2x2C_SubsystemId_MASK 0xffff0000 + +/// D0F2x2C +typedef union { + struct { ///< + UINT32 SubsystemVendorId:16; ///< + UINT32 SubsystemId:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2x2C_STRUCT; + +// **** D0F2x34 Register Definition **** +// Address +#define D0F2x34_ADDRESS 0x34 + +// Type +#define D0F2x34_TYPE TYPE_D0F2 +// Field Data +#define D0F2x34_CapPtr_OFFSET 0 +#define D0F2x34_CapPtr_WIDTH 8 +#define D0F2x34_CapPtr_MASK 0xff +#define D0F2x34_Reserved_31_8_OFFSET 8 +#define D0F2x34_Reserved_31_8_WIDTH 24 +#define D0F2x34_Reserved_31_8_MASK 0xffffff00 + +/// D0F2x34 +typedef union { + struct { ///< + UINT32 CapPtr:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2x34_STRUCT; + +// **** D0F2x3C Register Definition **** +// Address +#define D0F2x3C_ADDRESS 0x3c + +// Type +#define D0F2x3C_TYPE TYPE_D0F2 +// Field Data +#define D0F2x3C_InterruptLine_OFFSET 0 +#define D0F2x3C_InterruptLine_WIDTH 8 +#define D0F2x3C_InterruptLine_MASK 0xff +#define D0F2x3C_InterruptPin_OFFSET 8 +#define D0F2x3C_InterruptPin_WIDTH 8 +#define D0F2x3C_InterruptPin_MASK 0xff00 +#define D0F2x3C_Reserved_31_16_OFFSET 16 +#define D0F2x3C_Reserved_31_16_WIDTH 16 +#define D0F2x3C_Reserved_31_16_MASK 0xffff0000 + +/// D0F2x3C +typedef union { + struct { ///< + UINT32 InterruptLine:8 ; ///< + UINT32 InterruptPin:8 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2x3C_STRUCT; + +// **** D0F2x40 Register Definition **** +// Address +#define D0F2x40_ADDRESS 0x40 + +// Type +#define D0F2x40_TYPE TYPE_D0F2 +// Field Data +#define D0F2x40_IommuCapId_OFFSET 0 +#define D0F2x40_IommuCapId_WIDTH 8 +#define D0F2x40_IommuCapId_MASK 0xff +#define D0F2x40_IommuCapPtr_OFFSET 8 +#define D0F2x40_IommuCapPtr_WIDTH 8 +#define D0F2x40_IommuCapPtr_MASK 0xff00 +#define D0F2x40_IommuCapType_OFFSET 16 +#define D0F2x40_IommuCapType_WIDTH 3 +#define D0F2x40_IommuCapType_MASK 0x70000 +#define D0F2x40_IommuCapRev_OFFSET 19 +#define D0F2x40_IommuCapRev_WIDTH 5 +#define D0F2x40_IommuCapRev_MASK 0xf80000 +#define D0F2x40_IommuIoTlbsup_OFFSET 24 +#define D0F2x40_IommuIoTlbsup_WIDTH 1 +#define D0F2x40_IommuIoTlbsup_MASK 0x1000000 +#define D0F2x40_IommuHtTunnelSup_OFFSET 25 +#define D0F2x40_IommuHtTunnelSup_WIDTH 1 +#define D0F2x40_IommuHtTunnelSup_MASK 0x2000000 +#define D0F2x40_IommuNpCache_OFFSET 26 +#define D0F2x40_IommuNpCache_WIDTH 1 +#define D0F2x40_IommuNpCache_MASK 0x4000000 +#define D0F2x40_IommuEfrSup_OFFSET 27 +#define D0F2x40_IommuEfrSup_WIDTH 1 +#define D0F2x40_IommuEfrSup_MASK 0x8000000 +#define D0F2x40_Reserved_31_28_OFFSET 28 +#define D0F2x40_Reserved_31_28_WIDTH 4 +#define D0F2x40_Reserved_31_28_MASK 0xf0000000 + +/// D0F2x40 +typedef union { + struct { ///< + UINT32 IommuCapId:8 ; ///< + UINT32 IommuCapPtr:8 ; ///< + UINT32 IommuCapType:3 ; ///< + UINT32 IommuCapRev:5 ; ///< + UINT32 IommuIoTlbsup:1 ; ///< + UINT32 IommuHtTunnelSup:1 ; ///< + UINT32 IommuNpCache:1 ; ///< + UINT32 IommuEfrSup:1 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2x40_STRUCT; + +// **** D0F2x44 Register Definition **** +// Address +#define D0F2x44_ADDRESS 0x44 + +// Type +#define D0F2x44_TYPE TYPE_D0F2 +// Field Data +#define D0F2x44_IommuEnable_OFFSET 0 +#define D0F2x44_IommuEnable_WIDTH 1 +#define D0F2x44_IommuEnable_MASK 0x1 +#define D0F2x44_Reserved_13_1_OFFSET 1 +#define D0F2x44_Reserved_13_1_WIDTH 13 +#define D0F2x44_Reserved_13_1_MASK 0x3ffe +#define D0F2x44_IommuBaseAddr_31_14__OFFSET 14 +#define D0F2x44_IommuBaseAddr_31_14__WIDTH 18 +#define D0F2x44_IommuBaseAddr_31_14__MASK 0xffffc000 + +/// D0F2x44 +typedef union { + struct { ///< + UINT32 IommuEnable:1 ; ///< + UINT32 Reserved_13_1:13; ///< + UINT32 IommuBaseAddr_31_14_:18; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2x44_STRUCT; + +// **** D0F2x48 Register Definition **** +// Address +#define D0F2x48_ADDRESS 0x48 + +// Type +#define D0F2x48_TYPE TYPE_D0F2 +// Field Data +#define D0F2x48_IommuBaseAddr_63_32__OFFSET 0 +#define D0F2x48_IommuBaseAddr_63_32__WIDTH 32 +#define D0F2x48_IommuBaseAddr_63_32__MASK 0xffffffff + +/// D0F2x48 +typedef union { + struct { ///< + UINT32 IommuBaseAddr_63_32_:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2x48_STRUCT; + +// **** D0F2x4C Register Definition **** +// Address +#define D0F2x4C_ADDRESS 0x4c + +// Type +#define D0F2x4C_TYPE TYPE_D0F2 +// Field Data +#define D0F2x4C_IommuUnitId_OFFSET 0 +#define D0F2x4C_IommuUnitId_WIDTH 5 +#define D0F2x4C_IommuUnitId_MASK 0x1f +#define D0F2x4C_Reserved_6_5_OFFSET 5 +#define D0F2x4C_Reserved_6_5_WIDTH 2 +#define D0F2x4C_Reserved_6_5_MASK 0x60 +#define D0F2x4C_IommuRngValid_OFFSET 7 +#define D0F2x4C_IommuRngValid_WIDTH 1 +#define D0F2x4C_IommuRngValid_MASK 0x80 +#define D0F2x4C_IommuBusNumber_OFFSET 8 +#define D0F2x4C_IommuBusNumber_WIDTH 8 +#define D0F2x4C_IommuBusNumber_MASK 0xff00 +#define D0F2x4C_IommuFirstDevice_OFFSET 16 +#define D0F2x4C_IommuFirstDevice_WIDTH 8 +#define D0F2x4C_IommuFirstDevice_MASK 0xff0000 +#define D0F2x4C_IommuLastDevice_OFFSET 24 +#define D0F2x4C_IommuLastDevice_WIDTH 8 +#define D0F2x4C_IommuLastDevice_MASK 0xff000000 + +/// D0F2x4C +typedef union { + struct { ///< + UINT32 IommuUnitId:5 ; ///< + UINT32 Reserved_6_5:2 ; ///< + UINT32 IommuRngValid:1 ; ///< + UINT32 IommuBusNumber:8 ; ///< + UINT32 IommuFirstDevice:8 ; ///< + UINT32 IommuLastDevice:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2x4C_STRUCT; + +// **** D0F2x50 Register Definition **** +// Address +#define D0F2x50_ADDRESS 0x50 + +// Type +#define D0F2x50_TYPE TYPE_D0F2 +// Field Data +#define D0F2x50_IommuMsiNum_OFFSET 0 +#define D0F2x50_IommuMsiNum_WIDTH 5 +#define D0F2x50_IommuMsiNum_MASK 0x1f +#define D0F2x50_IommuGvaSize_OFFSET 5 +#define D0F2x50_IommuGvaSize_WIDTH 3 +#define D0F2x50_IommuGvaSize_MASK 0xe0 +#define D0F2x50_IommuPaSize_OFFSET 8 +#define D0F2x50_IommuPaSize_WIDTH 7 +#define D0F2x50_IommuPaSize_MASK 0x7f00 +#define D0F2x50_IommuVaSize_OFFSET 15 +#define D0F2x50_IommuVaSize_WIDTH 7 +#define D0F2x50_IommuVaSize_MASK 0x3f8000 +#define D0F2x50_IommuHtAtsResv_OFFSET 22 +#define D0F2x50_IommuHtAtsResv_WIDTH 1 +#define D0F2x50_IommuHtAtsResv_MASK 0x400000 +#define D0F2x50_Reserved_26_23_OFFSET 23 +#define D0F2x50_Reserved_26_23_WIDTH 4 +#define D0F2x50_Reserved_26_23_MASK 0x7800000 +#define D0F2x50_IommuMsiNumPpr_OFFSET 27 +#define D0F2x50_IommuMsiNumPpr_WIDTH 5 +#define D0F2x50_IommuMsiNumPpr_MASK 0xf8000000 + +/// D0F2x50 +typedef union { + struct { ///< + UINT32 IommuMsiNum:5 ; ///< + UINT32 IommuGvaSize:3 ; ///< + UINT32 IommuPaSize:7 ; ///< + UINT32 IommuVaSize:7 ; ///< + UINT32 IommuHtAtsResv:1 ; ///< + UINT32 Reserved_26_23:4 ; ///< + UINT32 IommuMsiNumPpr:5 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2x50_STRUCT; + +// **** D0F2x54 Register Definition **** +// Address +#define D0F2x54_ADDRESS 0x54 + +// Type +#define D0F2x54_TYPE TYPE_D0F2 +// Field Data +#define D0F2x54_MsiCapId_OFFSET 0 +#define D0F2x54_MsiCapId_WIDTH 8 +#define D0F2x54_MsiCapId_MASK 0xff +#define D0F2x54_MsiCapPtr_OFFSET 8 +#define D0F2x54_MsiCapPtr_WIDTH 8 +#define D0F2x54_MsiCapPtr_MASK 0xff00 +#define D0F2x54_MsiEn_OFFSET 16 +#define D0F2x54_MsiEn_WIDTH 1 +#define D0F2x54_MsiEn_MASK 0x10000 +#define D0F2x54_MsiMultMessCap_OFFSET 17 +#define D0F2x54_MsiMultMessCap_WIDTH 3 +#define D0F2x54_MsiMultMessCap_MASK 0xe0000 +#define D0F2x54_MsiMultMessEn_OFFSET 20 +#define D0F2x54_MsiMultMessEn_WIDTH 3 +#define D0F2x54_MsiMultMessEn_MASK 0x700000 +#define D0F2x54_Msi64En_OFFSET 23 +#define D0F2x54_Msi64En_WIDTH 1 +#define D0F2x54_Msi64En_MASK 0x800000 +#define D0F2x54_Reserved_31_24_OFFSET 24 +#define D0F2x54_Reserved_31_24_WIDTH 8 +#define D0F2x54_Reserved_31_24_MASK 0xff000000 + +/// D0F2x54 +typedef union { + struct { ///< + UINT32 MsiCapId:8 ; ///< + UINT32 MsiCapPtr:8 ; ///< + UINT32 MsiEn:1 ; ///< + UINT32 MsiMultMessCap:3 ; ///< + UINT32 MsiMultMessEn:3 ; ///< + UINT32 Msi64En:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2x54_STRUCT; + +// **** D0F2x58 Register Definition **** +// Address +#define D0F2x58_ADDRESS 0x58 + +// Type +#define D0F2x58_TYPE TYPE_D0F2 +// Field Data +#define D0F2x58_Reserved_1_0_OFFSET 0 +#define D0F2x58_Reserved_1_0_WIDTH 2 +#define D0F2x58_Reserved_1_0_MASK 0x3 +#define D0F2x58_MsiAddr_31_2__OFFSET 2 +#define D0F2x58_MsiAddr_31_2__WIDTH 30 +#define D0F2x58_MsiAddr_31_2__MASK 0xfffffffc + +/// D0F2x58 +typedef union { + struct { ///< + UINT32 Reserved_1_0:2 ; ///< + UINT32 MsiAddr_31_2_:30; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2x58_STRUCT; + +// **** D0F2x5C Register Definition **** +// Address +#define D0F2x5C_ADDRESS 0x5c + +// Type +#define D0F2x5C_TYPE TYPE_D0F2 +// Field Data +#define D0F2x5C_MsiAddr_63_32__OFFSET 0 +#define D0F2x5C_MsiAddr_63_32__WIDTH 32 +#define D0F2x5C_MsiAddr_63_32__MASK 0xffffffff + +/// D0F2x5C +typedef union { + struct { ///< + UINT32 MsiAddr_63_32_:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2x5C_STRUCT; + +// **** D0F2x60 Register Definition **** +// Address +#define D0F2x60_ADDRESS 0x60 + +// Type +#define D0F2x60_TYPE TYPE_D0F2 +// Field Data +#define D0F2x60_MsiData_OFFSET 0 +#define D0F2x60_MsiData_WIDTH 16 +#define D0F2x60_MsiData_MASK 0xffff +#define D0F2x60_Reserved_31_16_OFFSET 16 +#define D0F2x60_Reserved_31_16_WIDTH 16 +#define D0F2x60_Reserved_31_16_MASK 0xffff0000 + +/// D0F2x60 +typedef union { + struct { ///< + UINT32 MsiData:16; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2x60_STRUCT; + +// **** D0F2x64 Register Definition **** +// Address +#define D0F2x64_ADDRESS 0x64 + +// Type +#define D0F2x64_TYPE TYPE_D0F2 +// Field Data +#define D0F2x64_MsiMapCapId_OFFSET 0 +#define D0F2x64_MsiMapCapId_WIDTH 8 +#define D0F2x64_MsiMapCapId_MASK 0xff +#define D0F2x64_MsiMapCapPtr_OFFSET 8 +#define D0F2x64_MsiMapCapPtr_WIDTH 8 +#define D0F2x64_MsiMapCapPtr_MASK 0xff00 +#define D0F2x64_MsiMapEn_OFFSET 16 +#define D0F2x64_MsiMapEn_WIDTH 1 +#define D0F2x64_MsiMapEn_MASK 0x10000 +#define D0F2x64_MsiMapFixd_OFFSET 17 +#define D0F2x64_MsiMapFixd_WIDTH 1 +#define D0F2x64_MsiMapFixd_MASK 0x20000 +#define D0F2x64_Reserved_26_18_OFFSET 18 +#define D0F2x64_Reserved_26_18_WIDTH 9 +#define D0F2x64_Reserved_26_18_MASK 0x7fc0000 +#define D0F2x64_MsiMapCapType_OFFSET 27 +#define D0F2x64_MsiMapCapType_WIDTH 5 +#define D0F2x64_MsiMapCapType_MASK 0xf8000000 + +/// D0F2x64 +typedef union { + struct { ///< + UINT32 MsiMapCapId:8 ; ///< + UINT32 MsiMapCapPtr:8 ; ///< + UINT32 MsiMapEn:1 ; ///< + UINT32 MsiMapFixd:1 ; ///< + UINT32 Reserved_26_18:9 ; ///< + UINT32 MsiMapCapType:5 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2x64_STRUCT; + +// **** D0F2x6C Register Definition **** +// Address +#define D0F2x6C_ADDRESS 0x6c + +// Type +#define D0F2x6C_TYPE TYPE_D0F2 +// Field Data +#define D0F2x6C_InterruptPinW_OFFSET 0 +#define D0F2x6C_InterruptPinW_WIDTH 3 +#define D0F2x6C_InterruptPinW_MASK 0x7 +#define D0F2x6C_Reserved_3_3_OFFSET 3 +#define D0F2x6C_Reserved_3_3_WIDTH 1 +#define D0F2x6C_Reserved_3_3_MASK 0x8 +#define D0F2x6C_MinorRevIdW_OFFSET 4 +#define D0F2x6C_MinorRevIdW_WIDTH 4 +#define D0F2x6C_MinorRevIdW_MASK 0xf0 +#define D0F2x6C_IoTlbsupW_OFFSET 8 +#define D0F2x6C_IoTlbsupW_WIDTH 1 +#define D0F2x6C_IoTlbsupW_MASK 0x100 +#define D0F2x6C_EfrSupW_OFFSET 9 +#define D0F2x6C_EfrSupW_WIDTH 1 +#define D0F2x6C_EfrSupW_MASK 0x200 +#define D0F2x6C_Reserved_31_10_OFFSET 10 +#define D0F2x6C_Reserved_31_10_WIDTH 22 +#define D0F2x6C_Reserved_31_10_MASK 0xfffffc00 + +/// D0F2x6C +typedef union { + struct { ///< + UINT32 InterruptPinW:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 MinorRevIdW:4 ; ///< + UINT32 IoTlbsupW:1 ; ///< + UINT32 EfrSupW:1 ; ///< + UINT32 Reserved_31_10:22; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2x6C_STRUCT; + +// **** D0F2x70 Register Definition **** +// Address +#define D0F2x70_ADDRESS 0x70 + +// Type +#define D0F2x70_TYPE TYPE_D0F2 +// Field Data +#define D0F2x70_PrefSupW_OFFSET 0 +#define D0F2x70_PrefSupW_WIDTH 1 +#define D0F2x70_PrefSupW_MASK 0x1 +#define D0F2x70_PprSupW_OFFSET 1 +#define D0F2x70_PprSupW_WIDTH 1 +#define D0F2x70_PprSupW_MASK 0x2 +#define D0F2x70_Reserved_2_2_OFFSET 2 +#define D0F2x70_Reserved_2_2_WIDTH 1 +#define D0F2x70_Reserved_2_2_MASK 0x4 +#define D0F2x70_NxSupW_OFFSET 3 +#define D0F2x70_NxSupW_WIDTH 1 +#define D0F2x70_NxSupW_MASK 0x8 +#define D0F2x70_GtSupW_OFFSET 4 +#define D0F2x70_GtSupW_WIDTH 1 +#define D0F2x70_GtSupW_MASK 0x10 +#define D0F2x70_Reserved_5_5_OFFSET 5 +#define D0F2x70_Reserved_5_5_WIDTH 1 +#define D0F2x70_Reserved_5_5_MASK 0x20 +#define D0F2x70_IaSupW_OFFSET 6 +#define D0F2x70_IaSupW_WIDTH 1 +#define D0F2x70_IaSupW_MASK 0x40 +#define D0F2x70_Reserved_7_7_OFFSET 7 +#define D0F2x70_Reserved_7_7_WIDTH 1 +#define D0F2x70_Reserved_7_7_MASK 0x80 +#define D0F2x70_Reserved_8_8_OFFSET 8 +#define D0F2x70_Reserved_8_8_WIDTH 1 +#define D0F2x70_Reserved_8_8_MASK 0x100 +#define D0F2x70_PcSupW_OFFSET 9 +#define D0F2x70_PcSupW_WIDTH 1 +#define D0F2x70_PcSupW_MASK 0x200 +#define D0F2x70_HatsW_OFFSET 10 +#define D0F2x70_HatsW_WIDTH 2 +#define D0F2x70_HatsW_MASK 0xc00 +#define D0F2x70_Reserved_31_12_OFFSET 12 +#define D0F2x70_Reserved_31_12_WIDTH 20 +#define D0F2x70_Reserved_31_12_MASK 0xfffff000 + +/// D0F2x70 +typedef union { + struct { ///< + UINT32 PrefSupW:1 ; ///< + UINT32 PprSupW:1 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 NxSupW:1 ; ///< + UINT32 GtSupW:1 ; ///< + UINT32 Reserved_5_5:1 ; ///< + UINT32 IaSupW:1 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 Reserved_8_8:1 ; ///< + UINT32 PcSupW:1 ; ///< + UINT32 HatsW:2 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2x70_STRUCT; + +// **** D0F2x74 Register Definition **** +// Address +#define D0F2x74_ADDRESS 0x74 + +// Type +#define D0F2x74_TYPE TYPE_D0F2 +// Field Data +#define D0F2x74_PasMaxW_OFFSET 0 +#define D0F2x74_PasMaxW_WIDTH 4 +#define D0F2x74_PasMaxW_MASK 0xf +#define D0F2x74_Reserved_31_4_OFFSET 4 +#define D0F2x74_Reserved_31_4_WIDTH 28 +#define D0F2x74_Reserved_31_4_MASK 0xfffffff0 + +/// D0F2x74 +typedef union { + struct { ///< + UINT32 PasMaxW:4 ; ///< + UINT32 Reserved_31_4:28; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2x74_STRUCT; + +// **** D0F2x78 Register Definition **** +// Address +#define D0F2x78_ADDRESS 0x78 + +// Type +#define D0F2x78_TYPE TYPE_D0F2 +// Field Data +#define D0F2x78_Reserved_6_0_OFFSET 0 +#define D0F2x78_Reserved_6_0_WIDTH 7 +#define D0F2x78_Reserved_6_0_MASK 0x7f +#define D0F2x78_RngValidW_OFFSET 7 +#define D0F2x78_RngValidW_WIDTH 1 +#define D0F2x78_RngValidW_MASK 0x80 +#define D0F2x78_BusNumberW_OFFSET 8 +#define D0F2x78_BusNumberW_WIDTH 8 +#define D0F2x78_BusNumberW_MASK 0xff00 +#define D0F2x78_FirstDeviceW_OFFSET 16 +#define D0F2x78_FirstDeviceW_WIDTH 8 +#define D0F2x78_FirstDeviceW_MASK 0xff0000 +#define D0F2x78_LastDeviceW_OFFSET 24 +#define D0F2x78_LastDeviceW_WIDTH 8 +#define D0F2x78_LastDeviceW_MASK 0xff000000 + +/// D0F2x78 +typedef union { + struct { ///< + UINT32 Reserved_6_0:7 ; ///< + UINT32 RngValidW:1 ; ///< + UINT32 BusNumberW:8 ; ///< + UINT32 FirstDeviceW:8 ; ///< + UINT32 LastDeviceW:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2x78_STRUCT; + +// **** D0F2xF0 Register Definition **** +// Address +#define D0F2xF0_ADDRESS 0xf0 + +// Type +#define D0F2xF0_TYPE TYPE_D0F2 +// Field Data +#define D0F2xF0_L2cfgIndex_OFFSET 0 +#define D0F2xF0_L2cfgIndex_WIDTH 8 +#define D0F2xF0_L2cfgIndex_MASK 0xff +#define D0F2xF0_L2cfgWrEn_OFFSET 8 +#define D0F2xF0_L2cfgWrEn_WIDTH 1 +#define D0F2xF0_L2cfgWrEn_MASK 0x100 +#define D0F2xF0_Reserved_31_9_OFFSET 9 +#define D0F2xF0_Reserved_31_9_WIDTH 23 +#define D0F2xF0_Reserved_31_9_MASK 0xfffffe00 + +/// D0F2xF0 +typedef union { + struct { ///< + UINT32 L2cfgIndex:8 ; ///< + UINT32 L2cfgWrEn:1 ; ///< + UINT32 Reserved_31_9:23; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF0_STRUCT; + +// **** D0F2xF4 Register Definition **** +// Address +#define D0F2xF4_ADDRESS 0xf4 + +// Type +#define D0F2xF4_TYPE TYPE_D0F2 +// Field Data +#define D0F2xF4_L2cfgData_OFFSET 0 +#define D0F2xF4_L2cfgData_WIDTH 32 +#define D0F2xF4_L2cfgData_MASK 0xffffffff + +/// D0F2xF4 +typedef union { + struct { ///< + UINT32 L2cfgData:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_STRUCT; + +// **** D0F2xF8 Register Definition **** +// Address +#define D0F2xF8_ADDRESS 0xf8 + +// Type +#define D0F2xF8_TYPE TYPE_D0F2 +// Field Data +#define D0F2xF8_L1cfgIndex_OFFSET 0 +#define D0F2xF8_L1cfgIndex_WIDTH 16 +#define D0F2xF8_L1cfgIndex_MASK 0xffff +#define D0F2xF8_L1cfgSel_OFFSET 16 +#define D0F2xF8_L1cfgSel_WIDTH 4 +#define D0F2xF8_L1cfgSel_MASK 0xf0000 +#define D0F2xF8_Reserved_30_20_OFFSET 20 +#define D0F2xF8_Reserved_30_20_WIDTH 11 +#define D0F2xF8_Reserved_30_20_MASK 0x7ff00000 +#define D0F2xF8_L1cfgEn_OFFSET 31 +#define D0F2xF8_L1cfgEn_WIDTH 1 +#define D0F2xF8_L1cfgEn_MASK 0x80000000 + +/// D0F2xF8 +typedef union { + struct { ///< + UINT32 L1cfgIndex:16; ///< + UINT32 L1cfgSel:4 ; ///< + UINT32 Reserved_30_20:11; ///< + UINT32 L1cfgEn:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF8_STRUCT; + +// **** D0F2xFC Register Definition **** +// Address +#define D0F2xFC_ADDRESS 0xfc + +// Type +#define D0F2xFC_TYPE TYPE_D0F2 +// Field Data +#define D0F2xFC_L1cfgData_OFFSET 0 +#define D0F2xFC_L1cfgData_WIDTH 32 +#define D0F2xFC_L1cfgData_MASK 0xffffffff + +/// D0F2xFC +typedef union { + struct { ///< + UINT32 L1cfgData:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xFC_STRUCT; + +// **** D18F0x00 Register Definition **** +// Address +#define D18F0x00_ADDRESS 0x0 + +// Type +#define D18F0x00_TYPE TYPE_D18F0 +// Field Data +#define D18F0x00_VendorID_OFFSET 0 +#define D18F0x00_VendorID_WIDTH 16 +#define D18F0x00_VendorID_MASK 0xffff +#define D18F0x00_DeviceID_OFFSET 16 +#define D18F0x00_DeviceID_WIDTH 16 +#define D18F0x00_DeviceID_MASK 0xffff0000 + +/// D18F0x00 +typedef union { + struct { ///< + UINT32 VendorID:16; ///< + UINT32 DeviceID:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F0x00_STRUCT; + +// **** D18F0x04 Register Definition **** +// Address +#define D18F0x04_ADDRESS 0x4 + +// Type +#define D18F0x04_TYPE TYPE_D18F0 +// Field Data +#define D18F0x04_Command_OFFSET 0 +#define D18F0x04_Command_WIDTH 16 +#define D18F0x04_Command_MASK 0xffff +#define D18F0x04_Status_OFFSET 16 +#define D18F0x04_Status_WIDTH 16 +#define D18F0x04_Status_MASK 0xffff0000 + +/// D18F0x04 +typedef union { + struct { ///< + UINT32 Command:16; ///< + UINT32 Status:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F0x04_STRUCT; + +// **** D18F0x08 Register Definition **** +// Address +#define D18F0x08_ADDRESS 0x8 + +// Type +#define D18F0x08_TYPE TYPE_D18F0 +// Field Data +#define D18F0x08_RevID_OFFSET 0 +#define D18F0x08_RevID_WIDTH 8 +#define D18F0x08_RevID_MASK 0xff +#define D18F0x08_ClassCode_OFFSET 8 +#define D18F0x08_ClassCode_WIDTH 24 +#define D18F0x08_ClassCode_MASK 0xffffff00 + +/// D18F0x08 +typedef union { + struct { ///< + UINT32 RevID:8 ; ///< + UINT32 ClassCode:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F0x08_STRUCT; + +// **** D18F0x0C Register Definition **** +// Address +#define D18F0x0C_ADDRESS 0xc + +// Type +#define D18F0x0C_TYPE TYPE_D18F0 +// Field Data +#define D18F0x0C_HeaderTypeReg_OFFSET 0 +#define D18F0x0C_HeaderTypeReg_WIDTH 32 +#define D18F0x0C_HeaderTypeReg_MASK 0xffffffff + +/// D18F0x0C +typedef union { + struct { ///< + UINT32 HeaderTypeReg:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F0x0C_STRUCT; + +// **** D18F0x34 Register Definition **** +// Address +#define D18F0x34_ADDRESS 0x34 + +// Type +#define D18F0x34_TYPE TYPE_D18F0 +// Field Data +#define D18F0x34_CapPtr_OFFSET 0 +#define D18F0x34_CapPtr_WIDTH 8 +#define D18F0x34_CapPtr_MASK 0xff +#define D18F0x34_Reserved_31_8_OFFSET 8 +#define D18F0x34_Reserved_31_8_WIDTH 24 +#define D18F0x34_Reserved_31_8_MASK 0xffffff00 + +/// D18F0x34 +typedef union { + struct { ///< + UINT32 CapPtr:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F0x34_STRUCT; + +// **** D18F0x40 Register Definition **** +// Address +#define D18F0x40_ADDRESS 0x40 + +// Type +#define D18F0x40_TYPE TYPE_D18F0 +// Field Data +#define D18F0x40_Reserved_31_0_OFFSET 0 +#define D18F0x40_Reserved_31_0_WIDTH 32 +#define D18F0x40_Reserved_31_0_MASK 0xffffffff + +/// D18F0x40 +typedef union { + struct { ///< + UINT32 Reserved_31_0:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F0x40_STRUCT; + +// **** D18F0x60 Register Definition **** +// Address +#define D18F0x60_ADDRESS 0x60 + +// Type +#define D18F0x60_TYPE TYPE_D18F0 +// Field Data +#define D18F0x60_Reserved_15_0_OFFSET 0 +#define D18F0x60_Reserved_15_0_WIDTH 16 +#define D18F0x60_Reserved_15_0_MASK 0xffff +#define D18F0x60_CpuCnt_4_0__OFFSET 16 +#define D18F0x60_CpuCnt_4_0__WIDTH 5 +#define D18F0x60_CpuCnt_4_0__MASK 0x1f0000 +#define D18F0x60_Reserved_31_21_OFFSET 21 +#define D18F0x60_Reserved_31_21_WIDTH 11 +#define D18F0x60_Reserved_31_21_MASK 0xffe00000 + +/// D18F0x60 +typedef union { + struct { ///< + UINT32 Reserved_15_0:16; ///< + UINT32 CpuCnt_4_0_:5 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D18F0x60_STRUCT; + +// **** D18F0x64 Register Definition **** +// Address +#define D18F0x64_ADDRESS 0x64 + +// Type +#define D18F0x64_TYPE TYPE_D18F0 +// Field Data +#define D18F0x64_MctUnit_OFFSET 4 +#define D18F0x64_MctUnit_WIDTH 2 +#define D18F0x64_MctUnit_MASK 0x30 +#define D18F0x64_HbUnit_OFFSET 6 +#define D18F0x64_HbUnit_WIDTH 2 +#define D18F0x64_HbUnit_MASK 0xc0 +#define D18F0x64_Reserved_31_8_OFFSET 8 +#define D18F0x64_Reserved_31_8_WIDTH 24 +#define D18F0x64_Reserved_31_8_MASK 0xffffff00 + +/// D18F0x64 +typedef union { + struct { ///< + UINT32 CpuUnit:2 ; ///< + UINT32 ExtCpuUnit:2 ; ///< + UINT32 MctUnit:2 ; ///< + UINT32 HbUnit:2 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F0x64_STRUCT; + +// **** D18F0x68 Register Definition **** +// Address +#define D18F0x68_ADDRESS 0x68 + +// Type +#define D18F0x68_TYPE TYPE_D18F0 +// Field Data +#define D18F0x68_Reserved_3_0_OFFSET 0 +#define D18F0x68_Reserved_3_0_WIDTH 4 +#define D18F0x68_Reserved_3_0_MASK 0xf +#define D18F0x68_DisMTS_OFFSET 4 +#define D18F0x68_DisMTS_WIDTH 1 +#define D18F0x68_DisMTS_MASK 0x10 +#define D18F0x68_Reserved_5_5_OFFSET 5 +#define D18F0x68_Reserved_5_5_WIDTH 1 +#define D18F0x68_Reserved_5_5_MASK 0x20 +#define D18F0x68_CPUReqPassPW_OFFSET 6 +#define D18F0x68_CPUReqPassPW_WIDTH 1 +#define D18F0x68_CPUReqPassPW_MASK 0x40 +#define D18F0x68_CPURdRspPassPW_OFFSET 7 +#define D18F0x68_CPURdRspPassPW_WIDTH 1 +#define D18F0x68_CPURdRspPassPW_MASK 0x80 +#define D18F0x68_DisPMemC_OFFSET 8 +#define D18F0x68_DisPMemC_WIDTH 1 +#define D18F0x68_DisPMemC_MASK 0x100 +#define D18F0x68_DisRmtPMemC_OFFSET 9 +#define D18F0x68_DisRmtPMemC_WIDTH 1 +#define D18F0x68_DisRmtPMemC_MASK 0x200 +#define D18F0x68_DisFillP_OFFSET 10 +#define D18F0x68_DisFillP_WIDTH 1 +#define D18F0x68_DisFillP_MASK 0x400 +#define D18F0x68_RespPassPW_OFFSET 11 +#define D18F0x68_RespPassPW_WIDTH 1 +#define D18F0x68_RespPassPW_MASK 0x800 +#define D18F0x68_Reserved_14_12_OFFSET 12 +#define D18F0x68_Reserved_14_12_WIDTH 3 +#define D18F0x68_Reserved_14_12_MASK 0x7000 +#define D18F0x68_LimitCldtCfg_OFFSET 15 +#define D18F0x68_LimitCldtCfg_WIDTH 1 +#define D18F0x68_LimitCldtCfg_MASK 0x8000 +#define D18F0x68_LintEn_OFFSET 16 +#define D18F0x68_LintEn_WIDTH 1 +#define D18F0x68_LintEn_MASK 0x10000 +#define D18F0x68_ApicExtBrdCst_OFFSET 17 +#define D18F0x68_ApicExtBrdCst_WIDTH 1 +#define D18F0x68_ApicExtBrdCst_MASK 0x20000 +#define D18F0x68_ApicExtId_OFFSET 18 +#define D18F0x68_ApicExtId_WIDTH 1 +#define D18F0x68_ApicExtId_MASK 0x40000 +#define D18F0x68_ApicExtSpur_OFFSET 19 +#define D18F0x68_ApicExtSpur_WIDTH 1 +#define D18F0x68_ApicExtSpur_MASK 0x80000 +#define D18F0x68_SeqIdSrcNodeEn_OFFSET 20 +#define D18F0x68_SeqIdSrcNodeEn_WIDTH 1 +#define D18F0x68_SeqIdSrcNodeEn_MASK 0x100000 +#define D18F0x68_DsNpReqLmt_OFFSET 21 +#define D18F0x68_DsNpReqLmt_WIDTH 2 +#define D18F0x68_DsNpReqLmt_MASK 0x600000 +#define D18F0x68_Reserved_31_23_OFFSET 23 +#define D18F0x68_Reserved_31_23_WIDTH 9 +#define D18F0x68_Reserved_31_23_MASK 0xff800000 + +/// D18F0x68 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 DisMTS:1 ; ///< + UINT32 Reserved_5_5:1 ; ///< + UINT32 CPUReqPassPW:1 ; ///< + UINT32 CPURdRspPassPW:1 ; ///< + UINT32 DisPMemC:1 ; ///< + UINT32 DisRmtPMemC:1 ; ///< + UINT32 DisFillP:1 ; ///< + UINT32 RespPassPW:1 ; ///< + UINT32 Reserved_14_12:3 ; ///< + UINT32 LimitCldtCfg:1 ; ///< + UINT32 LintEn:1 ; ///< + UINT32 ApicExtBrdCst:1 ; ///< + UINT32 ApicExtId:1 ; ///< + UINT32 ApicExtSpur:1 ; ///< + UINT32 SeqIdSrcNodeEn:1 ; ///< + UINT32 DsNpReqLmt:2 ; ///< + UINT32 Reserved_31_23:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F0x68_STRUCT; + +// **** D18F0x6C Register Definition **** +// Address +#define D18F0x6C_ADDRESS 0x6c + +// Type +#define D18F0x6C_TYPE TYPE_D18F0 +// Field Data +#define D18F0x6C_RouteTblDis_OFFSET 0 +#define D18F0x6C_RouteTblDis_WIDTH 1 +#define D18F0x6C_RouteTblDis_MASK 0x1 +#define D18F0x6C_Reserved_3_1_OFFSET 1 +#define D18F0x6C_Reserved_3_1_WIDTH 3 +#define D18F0x6C_Reserved_3_1_MASK 0xe +#define D18F0x6C_ColdRstDet_OFFSET 4 +#define D18F0x6C_ColdRstDet_WIDTH 1 +#define D18F0x6C_ColdRstDet_MASK 0x10 +#define D18F0x6C_BiosRstDet_0__OFFSET 5 +#define D18F0x6C_BiosRstDet_0__WIDTH 1 +#define D18F0x6C_BiosRstDet_0__MASK 0x20 +#define D18F0x6C_InitDet_OFFSET 6 +#define D18F0x6C_InitDet_WIDTH 1 +#define D18F0x6C_InitDet_MASK 0x40 +#define D18F0x6C_Reserved_8_7_OFFSET 7 +#define D18F0x6C_Reserved_8_7_WIDTH 2 +#define D18F0x6C_Reserved_8_7_MASK 0x180 +#define D18F0x6C_BiosRstDet_2_1__OFFSET 9 +#define D18F0x6C_BiosRstDet_2_1__WIDTH 2 +#define D18F0x6C_BiosRstDet_2_1__MASK 0x600 +#define D18F0x6C_Reserved_26_11_OFFSET 11 +#define D18F0x6C_Reserved_26_11_WIDTH 16 +#define D18F0x6C_Reserved_26_11_MASK 0x7fff800 +#define D18F0x6C_ApplyIsocModeEnNow_OFFSET 27 +#define D18F0x6C_ApplyIsocModeEnNow_WIDTH 1 +#define D18F0x6C_ApplyIsocModeEnNow_MASK 0x8000000 +#define D18F0x6C_RlsIntFullTokCntImm_OFFSET 28 +#define D18F0x6C_RlsIntFullTokCntImm_WIDTH 1 +#define D18F0x6C_RlsIntFullTokCntImm_MASK 0x10000000 +#define D18F0x6C_Reserved_29_29_OFFSET 29 +#define D18F0x6C_Reserved_29_29_WIDTH 1 +#define D18F0x6C_Reserved_29_29_MASK 0x20000000 +#define D18F0x6C_RlsLnkFullTokCntImm_OFFSET 30 +#define D18F0x6C_RlsLnkFullTokCntImm_WIDTH 1 +#define D18F0x6C_RlsLnkFullTokCntImm_MASK 0x40000000 +#define D18F0x6C_Reserved_31_31_OFFSET 31 +#define D18F0x6C_Reserved_31_31_WIDTH 1 +#define D18F0x6C_Reserved_31_31_MASK 0x80000000 + +/// D18F0x6C +typedef union { + struct { ///< + UINT32 RouteTblDis:1 ; ///< + UINT32 Reserved_3_1:3 ; ///< + UINT32 ColdRstDet:1 ; ///< + UINT32 BiosRstDet_0_:1 ; ///< + UINT32 InitDet:1 ; ///< + UINT32 Reserved_8_7:2 ; ///< + UINT32 BiosRstDet_2_1_:2 ; ///< + UINT32 Reserved_26_11:16; ///< + UINT32 ApplyIsocModeEnNow:1 ; ///< + UINT32 RlsIntFullTokCntImm:1 ; ///< + UINT32 Reserved_29_29:1 ; ///< + UINT32 RlsLnkFullTokCntImm:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F0x6C_STRUCT; + +// **** D18F0x84 Register Definition **** +// Address +#define D18F0x84_ADDRESS 0x84 + +// Type +#define D18F0x84_TYPE TYPE_D18F0 +// Field Data +#define D18F0x84_Reserved_3_0_OFFSET 0 +#define D18F0x84_Reserved_3_0_WIDTH 4 +#define D18F0x84_Reserved_3_0_MASK 0xf +#define D18F0x84_LinkFail_OFFSET 4 +#define D18F0x84_LinkFail_WIDTH 1 +#define D18F0x84_LinkFail_MASK 0x10 +#define D18F0x84_Reserved_5_5_OFFSET 5 +#define D18F0x84_Reserved_5_5_WIDTH 1 +#define D18F0x84_Reserved_5_5_MASK 0x20 +#define D18F0x84_Reserved_11_6_OFFSET 6 +#define D18F0x84_Reserved_11_6_WIDTH 6 +#define D18F0x84_Reserved_11_6_MASK 0xfc0 +#define D18F0x84_IsocEn_OFFSET 12 +#define D18F0x84_IsocEn_WIDTH 1 +#define D18F0x84_IsocEn_MASK 0x1000 +#define D18F0x84_Reserved_31_13_OFFSET 13 +#define D18F0x84_Reserved_31_13_WIDTH 19 +#define D18F0x84_Reserved_31_13_MASK 0xffffe000 + +/// D18F0x84 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 LinkFail:1 ; ///< + UINT32 Reserved_5_5:1 ; ///< + UINT32 Reserved_11_6:6 ; ///< + UINT32 IsocEn:1 ; ///< + UINT32 Reserved_31_13:19; ///< + } Field; ///< + UINT32 Value; ///< +} D18F0x84_STRUCT; + +// **** D18F0x90 Register Definition **** +// Address +#define D18F0x90_ADDRESS 0x90 + +// Type +#define D18F0x90_TYPE TYPE_D18F0 +// Field Data +#define D18F0x90_NpReqCmd_OFFSET 0 +#define D18F0x90_NpReqCmd_WIDTH 5 +#define D18F0x90_NpReqCmd_MASK 0x1f +#define D18F0x90_PReq_OFFSET 5 +#define D18F0x90_PReq_WIDTH 3 +#define D18F0x90_PReq_MASK 0xe0 +#define D18F0x90_RspCmd_OFFSET 8 +#define D18F0x90_RspCmd_WIDTH 4 +#define D18F0x90_RspCmd_MASK 0xf00 +#define D18F0x90_ProbeCmd_OFFSET 12 +#define D18F0x90_ProbeCmd_WIDTH 4 +#define D18F0x90_ProbeCmd_MASK 0xf000 +#define D18F0x90_NpReqData_OFFSET 16 +#define D18F0x90_NpReqData_WIDTH 2 +#define D18F0x90_NpReqData_MASK 0x30000 +#define D18F0x90_RspData_OFFSET 18 +#define D18F0x90_RspData_WIDTH 2 +#define D18F0x90_RspData_MASK 0xc0000 +#define D18F0x90_FreeCmd_OFFSET 20 +#define D18F0x90_FreeCmd_WIDTH 5 +#define D18F0x90_FreeCmd_MASK 0x1f00000 +#define D18F0x90_FreeData_OFFSET 25 +#define D18F0x90_FreeData_WIDTH 3 +#define D18F0x90_FreeData_MASK 0xe000000 +#define D18F0x90_Reserved_30_28_OFFSET 28 +#define D18F0x90_Reserved_30_28_WIDTH 3 +#define D18F0x90_Reserved_30_28_MASK 0x70000000 +#define D18F0x90_LockBc_OFFSET 31 +#define D18F0x90_LockBc_WIDTH 1 +#define D18F0x90_LockBc_MASK 0x80000000 + +/// D18F0x90 +typedef union { + struct { ///< + UINT32 NpReqCmd:5 ; ///< + UINT32 PReq:3 ; ///< + UINT32 RspCmd:4 ; ///< + UINT32 ProbeCmd:4 ; ///< + UINT32 NpReqData:2 ; ///< + UINT32 RspData:2 ; ///< + UINT32 FreeCmd:5 ; ///< + UINT32 FreeData:3 ; ///< + UINT32 Reserved_30_28:3 ; ///< + UINT32 LockBc:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F0x90_STRUCT; + +// **** D18F0x94 Register Definition **** +// Address +#define D18F0x94_ADDRESS 0x94 + +// Type +#define D18F0x94_TYPE TYPE_D18F0 +// Field Data +#define D18F0x94_Reserved_7_0_OFFSET 0 +#define D18F0x94_Reserved_7_0_WIDTH 8 +#define D18F0x94_Reserved_7_0_MASK 0xff +#define D18F0x94_SecBusNum_OFFSET 8 +#define D18F0x94_SecBusNum_WIDTH 8 +#define D18F0x94_SecBusNum_MASK 0xff00 +#define D18F0x94_IsocNpReqCmd_OFFSET 16 +#define D18F0x94_IsocNpReqCmd_WIDTH 3 +#define D18F0x94_IsocNpReqCmd_MASK 0x70000 +#define D18F0x94_IsocPReq_OFFSET 19 +#define D18F0x94_IsocPReq_WIDTH 3 +#define D18F0x94_IsocPReq_MASK 0x380000 +#define D18F0x94_IsocRspCmd_OFFSET 22 +#define D18F0x94_IsocRspCmd_WIDTH 3 +#define D18F0x94_IsocRspCmd_MASK 0x1c00000 +#define D18F0x94_IsocNpReqData_OFFSET 25 +#define D18F0x94_IsocNpReqData_WIDTH 2 +#define D18F0x94_IsocNpReqData_MASK 0x6000000 +#define D18F0x94_IsocRspData_OFFSET 27 +#define D18F0x94_IsocRspData_WIDTH 2 +#define D18F0x94_IsocRspData_MASK 0x18000000 +#define D18F0x94_Reserved_31_29_OFFSET 29 +#define D18F0x94_Reserved_31_29_WIDTH 3 +#define D18F0x94_Reserved_31_29_MASK 0xe0000000 + +/// D18F0x94 +typedef union { + struct { ///< + UINT32 Reserved_7_0:8 ; ///< + UINT32 SecBusNum:8 ; ///< + UINT32 IsocNpReqCmd:3 ; ///< + UINT32 IsocPReq:3 ; ///< + UINT32 IsocRspCmd:3 ; ///< + UINT32 IsocNpReqData:2 ; ///< + UINT32 IsocRspData:2 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F0x94_STRUCT; + +// **** D18F0x98 Register Definition **** +// Address +#define D18F0x98_ADDRESS 0x98 + +// Type +#define D18F0x98_TYPE TYPE_D18F0 +// Field Data +#define D18F0x98_Reserved_0_0_OFFSET 0 +#define D18F0x98_Reserved_0_0_WIDTH 1 +#define D18F0x98_Reserved_0_0_MASK 0x1 +#define D18F0x98_Reserved_1_1_OFFSET 1 +#define D18F0x98_Reserved_1_1_WIDTH 1 +#define D18F0x98_Reserved_1_1_MASK 0x2 +#define D18F0x98_Reserved_2_2_OFFSET 2 +#define D18F0x98_Reserved_2_2_WIDTH 1 +#define D18F0x98_Reserved_2_2_MASK 0x4 +#define D18F0x98_Reserved_4_3_OFFSET 3 +#define D18F0x98_Reserved_4_3_WIDTH 2 +#define D18F0x98_Reserved_4_3_MASK 0x18 +#define D18F0x98_PciEligible_OFFSET 5 +#define D18F0x98_PciEligible_WIDTH 1 +#define D18F0x98_PciEligible_MASK 0x20 +#define D18F0x98_Reserved_31_6_OFFSET 6 +#define D18F0x98_Reserved_31_6_WIDTH 26 +#define D18F0x98_Reserved_31_6_MASK 0xffffffc0 + +/// D18F0x98 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 Reserved_4_3:2 ; ///< + UINT32 PciEligible:1 ; ///< + UINT32 Reserved_31_6:26; ///< + } Field; ///< + UINT32 Value; ///< +} D18F0x98_STRUCT; + +// **** D18F0x9C Register Definition **** +// Address +#define D18F0x9C_ADDRESS 0x9c + +// Type +#define D18F0x9C_TYPE TYPE_D18F0 +// Field Data +#define D18F0x9C_Reserved_0_0_OFFSET 0 +#define D18F0x9C_Reserved_0_0_WIDTH 1 +#define D18F0x9C_Reserved_0_0_MASK 0x1 +#define D18F0x9C_Reserved_15_1_OFFSET 1 +#define D18F0x9C_Reserved_15_1_WIDTH 15 +#define D18F0x9C_Reserved_15_1_MASK 0xfffe +#define D18F0x9C_Reserved_31_16_OFFSET 16 +#define D18F0x9C_Reserved_31_16_WIDTH 16 +#define D18F0x9C_Reserved_31_16_MASK 0xffff0000 + +/// D18F0x9C +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 Reserved_15_1:15; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F0x9C_STRUCT; + +// **** D18F0x110 Register Definition **** +// Address +#define D18F0x110_ADDRESS 0x110 + +// Type +#define D18F0x110_TYPE TYPE_D18F0 +// Field Data +#define D18F0x110_Reserved_0_0_OFFSET 0 +#define D18F0x110_Reserved_0_0_WIDTH 1 +#define D18F0x110_Reserved_0_0_MASK 0x1 +#define D18F0x110_Reserved_1_1_OFFSET 1 +#define D18F0x110_Reserved_1_1_WIDTH 1 +#define D18F0x110_Reserved_1_1_MASK 0x2 +#define D18F0x110_ClumpEn_OFFSET 2 +#define D18F0x110_ClumpEn_WIDTH 30 +#define D18F0x110_ClumpEn_MASK 0xfffffffc + +/// D18F0x110 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 ClumpEn:30; ///< + } Field; ///< + UINT32 Value; ///< +} D18F0x110_STRUCT; + +// **** D18F0x16C Register Definition **** +// Address +#define D18F0x16C_ADDRESS 0x16c + +// Type +#define D18F0x16C_TYPE TYPE_D18F0 +// Field Data +#define D18F0x16C_Reserved_31_0_OFFSET 0 +#define D18F0x16C_Reserved_31_0_WIDTH 32 +#define D18F0x16C_Reserved_31_0_MASK 0xffffffff + +/// D18F0x16C +typedef union { + struct { ///< + UINT32 Reserved_31_0:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F0x16C_STRUCT; + +// **** D18F0x170 Register Definition **** +// Address +#define D18F0x170_ADDRESS 0x170 + +// Type +#define D18F0x170_TYPE TYPE_D18F0 +// Field Data +#define D18F0x170_Reserved_31_0_OFFSET 0 +#define D18F0x170_Reserved_31_0_WIDTH 32 +#define D18F0x170_Reserved_31_0_MASK 0xffffffff + +/// D18F0x170 +typedef union { + struct { ///< + UINT32 Reserved_31_0:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F0x170_STRUCT; + +// **** D18F0x1A0 Register Definition **** +// Address +#define D18F0x1A0_ADDRESS 0x1a0 + +// Type +#define D18F0x1A0_TYPE TYPE_D18F0 +// Field Data +#define D18F0x1A0_InitComplete_OFFSET 0 +#define D18F0x1A0_InitComplete_WIDTH 2 +#define D18F0x1A0_InitComplete_MASK 0x3 +#define D18F0x1A0_Reserved_30_2_OFFSET 2 +#define D18F0x1A0_Reserved_30_2_WIDTH 29 +#define D18F0x1A0_Reserved_30_2_MASK 0x7ffffffc +#define D18F0x1A0_InitStatusValid_OFFSET 31 +#define D18F0x1A0_InitStatusValid_WIDTH 1 +#define D18F0x1A0_InitStatusValid_MASK 0x80000000 + +/// D18F0x1A0 +typedef union { + struct { ///< + UINT32 InitComplete:2 ; ///< + UINT32 Reserved_30_2:29; ///< + UINT32 InitStatusValid:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F0x1A0_STRUCT; + +// **** D18F0x1DC Register Definition **** +// Address +#define D18F0x1DC_ADDRESS 0x1dc + +// Type +#define D18F0x1DC_TYPE TYPE_D18F0 +// Field Data +#define D18F0x1DC_Reserved_0_0_OFFSET 0 +#define D18F0x1DC_Reserved_0_0_WIDTH 1 +#define D18F0x1DC_Reserved_0_0_MASK 0x1 +#define D18F0x1DC_CpuEn_OFFSET 1 +#define D18F0x1DC_CpuEn_WIDTH 7 +#define D18F0x1DC_CpuEn_MASK 0xfe +#define D18F0x1DC_Reserved_31_8_OFFSET 8 +#define D18F0x1DC_Reserved_31_8_WIDTH 24 +#define D18F0x1DC_Reserved_31_8_MASK 0xffffff00 + +/// D18F0x1DC +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 CpuEn:7 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F0x1DC_STRUCT; + +// **** D18F1x00 Register Definition **** +// Address +#define D18F1x00_ADDRESS 0x0 + +// Type +#define D18F1x00_TYPE TYPE_D18F1 +// Field Data +#define D18F1x00_VendorID_OFFSET 0 +#define D18F1x00_VendorID_WIDTH 16 +#define D18F1x00_VendorID_MASK 0xffff +#define D18F1x00_DeviceID_OFFSET 16 +#define D18F1x00_DeviceID_WIDTH 16 +#define D18F1x00_DeviceID_MASK 0xffff0000 + +/// D18F1x00 +typedef union { + struct { ///< + UINT32 VendorID:16; ///< + UINT32 DeviceID:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x00_STRUCT; + +// **** D18F1x08 Register Definition **** +// Address +#define D18F1x08_ADDRESS 0x8 + +// Type +#define D18F1x08_TYPE TYPE_D18F1 +// Field Data +#define D18F1x08_RevID_OFFSET 0 +#define D18F1x08_RevID_WIDTH 8 +#define D18F1x08_RevID_MASK 0xff +#define D18F1x08_ClassCode_OFFSET 8 +#define D18F1x08_ClassCode_WIDTH 24 +#define D18F1x08_ClassCode_MASK 0xffffff00 + +/// D18F1x08 +typedef union { + struct { ///< + UINT32 RevID:8 ; ///< + UINT32 ClassCode:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x08_STRUCT; + +// **** D18F1x0C Register Definition **** +// Address +#define D18F1x0C_ADDRESS 0xc + +// Type +#define D18F1x0C_TYPE TYPE_D18F1 +// Field Data +#define D18F1x0C_HeaderTypeReg_OFFSET 0 +#define D18F1x0C_HeaderTypeReg_WIDTH 32 +#define D18F1x0C_HeaderTypeReg_MASK 0xffffffff + +/// D18F1x0C +typedef union { + struct { ///< + UINT32 HeaderTypeReg:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x0C_STRUCT; + +// **** D18F1x40 Register Definition **** +// Address +#define D18F1x40_ADDRESS 0x40 + +// Type +#define D18F1x40_TYPE TYPE_D18F1 +// Field Data +#define D18F1x40_RE_OFFSET 0 +#define D18F1x40_RE_WIDTH 1 +#define D18F1x40_RE_MASK 0x1 +#define D18F1x40_WE_OFFSET 1 +#define D18F1x40_WE_WIDTH 1 +#define D18F1x40_WE_MASK 0x2 +#define D18F1x40_Reserved_15_2_OFFSET 2 +#define D18F1x40_Reserved_15_2_WIDTH 14 +#define D18F1x40_Reserved_15_2_MASK 0xfffc +#define D18F1x40_DramBase_39_24__OFFSET 16 +#define D18F1x40_DramBase_39_24__WIDTH 16 +#define D18F1x40_DramBase_39_24__MASK 0xffff0000 + +/// D18F1x40 +typedef union { + struct { ///< + UINT32 RE:1 ; ///< + UINT32 WE:1 ; ///< + UINT32 Reserved_15_2:14; ///< + UINT32 DramBase_39_24_:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x40_STRUCT; + +// **** D18F1x44 Register Definition **** +// Address +#define D18F1x44_ADDRESS 0x44 + +// Type +#define D18F1x44_TYPE TYPE_D18F1 +// Field Data +#define D18F1x44_DstNode_OFFSET 0 +#define D18F1x44_DstNode_WIDTH 3 +#define D18F1x44_DstNode_MASK 0x7 +#define D18F1x44_Reserved_7_3_OFFSET 3 +#define D18F1x44_Reserved_7_3_WIDTH 5 +#define D18F1x44_Reserved_7_3_MASK 0xf8 +#define D18F1x44_Reserved_10_8_OFFSET 8 +#define D18F1x44_Reserved_10_8_WIDTH 3 +#define D18F1x44_Reserved_10_8_MASK 0x700 +#define D18F1x44_Reserved_15_11_OFFSET 11 +#define D18F1x44_Reserved_15_11_WIDTH 5 +#define D18F1x44_Reserved_15_11_MASK 0xf800 +#define D18F1x44_DramLimit_39_24__OFFSET 16 +#define D18F1x44_DramLimit_39_24__WIDTH 16 +#define D18F1x44_DramLimit_39_24__MASK 0xffff0000 + +/// D18F1x44 +typedef union { + struct { ///< + UINT32 DstNode:3 ; ///< + UINT32 Reserved_7_3:5 ; ///< + UINT32 Reserved_10_8:3 ; ///< + UINT32 Reserved_15_11:5 ; ///< + UINT32 DramLimit_39_24_:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x44_STRUCT; + +// **** D18F1x80 Register Definition **** +// Address +#define D18F1x80_ADDRESS 0x80 + +// Type +#define D18F1x80_TYPE TYPE_D18F1 +// Field Data +#define D18F1x80_RE_OFFSET 0 +#define D18F1x80_RE_WIDTH 1 +#define D18F1x80_RE_MASK 0x1 +#define D18F1x80_WE_OFFSET 1 +#define D18F1x80_WE_WIDTH 1 +#define D18F1x80_WE_MASK 0x2 +#define D18F1x80_Reserved_2_2_OFFSET 2 +#define D18F1x80_Reserved_2_2_WIDTH 1 +#define D18F1x80_Reserved_2_2_MASK 0x4 +#define D18F1x80_Lock_OFFSET 3 +#define D18F1x80_Lock_WIDTH 1 +#define D18F1x80_Lock_MASK 0x8 +#define D18F1x80_Reserved_7_4_OFFSET 4 +#define D18F1x80_Reserved_7_4_WIDTH 4 +#define D18F1x80_Reserved_7_4_MASK 0xf0 +#define D18F1x80_MMIOBase_39_16__OFFSET 8 +#define D18F1x80_MMIOBase_39_16__WIDTH 24 +#define D18F1x80_MMIOBase_39_16__MASK 0xffffff00 + +/// D18F1x80 +typedef union { + struct { ///< + UINT32 RE:1 ; ///< + UINT32 WE:1 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 Lock:1 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 MMIOBase_39_16_:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x80_STRUCT; + +// **** D18F1x84 Register Definition **** +// Address +#define D18F1x84_ADDRESS 0x84 + +// Type +#define D18F1x84_TYPE TYPE_D18F1 +// Field Data +#define D18F1x84_DstNode_OFFSET 0 +#define D18F1x84_DstNode_WIDTH 3 +#define D18F1x84_DstNode_MASK 0x7 +#define D18F1x84_Reserved_3_3_OFFSET 3 +#define D18F1x84_Reserved_3_3_WIDTH 1 +#define D18F1x84_Reserved_3_3_MASK 0x8 +#define D18F1x84_DstLink_OFFSET 4 +#define D18F1x84_DstLink_WIDTH 2 +#define D18F1x84_DstLink_MASK 0x30 +#define D18F1x84_DstSubLink_OFFSET 6 +#define D18F1x84_DstSubLink_WIDTH 1 +#define D18F1x84_DstSubLink_MASK 0x40 +#define D18F1x84_NP_OFFSET 7 +#define D18F1x84_NP_WIDTH 1 +#define D18F1x84_NP_MASK 0x80 +#define D18F1x84_MMIOLimit_39_16__OFFSET 8 +#define D18F1x84_MMIOLimit_39_16__WIDTH 24 +#define D18F1x84_MMIOLimit_39_16__MASK 0xffffff00 + +/// D18F1x84 +typedef union { + struct { ///< + UINT32 DstNode:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 DstLink:2 ; ///< + UINT32 DstSubLink:1 ; ///< + UINT32 NP:1 ; ///< + UINT32 MMIOLimit_39_16_:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x84_STRUCT; + +// **** D18F1x88 Register Definition **** +// Address +#define D18F1x88_ADDRESS 0x88 + +// Type +#define D18F1x88_TYPE TYPE_D18F1 +// Field Data +#define D18F1x88_RE_OFFSET 0 +#define D18F1x88_RE_WIDTH 1 +#define D18F1x88_RE_MASK 0x1 +#define D18F1x88_WE_OFFSET 1 +#define D18F1x88_WE_WIDTH 1 +#define D18F1x88_WE_MASK 0x2 +#define D18F1x88_Reserved_2_2_OFFSET 2 +#define D18F1x88_Reserved_2_2_WIDTH 1 +#define D18F1x88_Reserved_2_2_MASK 0x4 +#define D18F1x88_Lock_OFFSET 3 +#define D18F1x88_Lock_WIDTH 1 +#define D18F1x88_Lock_MASK 0x8 +#define D18F1x88_Reserved_7_4_OFFSET 4 +#define D18F1x88_Reserved_7_4_WIDTH 4 +#define D18F1x88_Reserved_7_4_MASK 0xf0 +#define D18F1x88_MMIOBase_39_16__OFFSET 8 +#define D18F1x88_MMIOBase_39_16__WIDTH 24 +#define D18F1x88_MMIOBase_39_16__MASK 0xffffff00 + +/// D18F1x88 +typedef union { + struct { ///< + UINT32 RE:1 ; ///< + UINT32 WE:1 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 Lock:1 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 MMIOBase_39_16_:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x88_STRUCT; + +// **** D18F1x8C Register Definition **** +// Address +#define D18F1x8C_ADDRESS 0x8c + +// Type +#define D18F1x8C_TYPE TYPE_D18F1 +// Field Data +#define D18F1x8C_DstNode_OFFSET 0 +#define D18F1x8C_DstNode_WIDTH 3 +#define D18F1x8C_DstNode_MASK 0x7 +#define D18F1x8C_Reserved_3_3_OFFSET 3 +#define D18F1x8C_Reserved_3_3_WIDTH 1 +#define D18F1x8C_Reserved_3_3_MASK 0x8 +#define D18F1x8C_DstLink_OFFSET 4 +#define D18F1x8C_DstLink_WIDTH 2 +#define D18F1x8C_DstLink_MASK 0x30 +#define D18F1x8C_DstSubLink_OFFSET 6 +#define D18F1x8C_DstSubLink_WIDTH 1 +#define D18F1x8C_DstSubLink_MASK 0x40 +#define D18F1x8C_NP_OFFSET 7 +#define D18F1x8C_NP_WIDTH 1 +#define D18F1x8C_NP_MASK 0x80 +#define D18F1x8C_MMIOLimit_39_16__OFFSET 8 +#define D18F1x8C_MMIOLimit_39_16__WIDTH 24 +#define D18F1x8C_MMIOLimit_39_16__MASK 0xffffff00 + +/// D18F1x8C +typedef union { + struct { ///< + UINT32 DstNode:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 DstLink:2 ; ///< + UINT32 DstSubLink:1 ; ///< + UINT32 NP:1 ; ///< + UINT32 MMIOLimit_39_16_:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x8C_STRUCT; + +// **** D18F1x90 Register Definition **** +// Address +#define D18F1x90_ADDRESS 0x90 + +// Type +#define D18F1x90_TYPE TYPE_D18F1 +// Field Data +#define D18F1x90_RE_OFFSET 0 +#define D18F1x90_RE_WIDTH 1 +#define D18F1x90_RE_MASK 0x1 +#define D18F1x90_WE_OFFSET 1 +#define D18F1x90_WE_WIDTH 1 +#define D18F1x90_WE_MASK 0x2 +#define D18F1x90_Reserved_2_2_OFFSET 2 +#define D18F1x90_Reserved_2_2_WIDTH 1 +#define D18F1x90_Reserved_2_2_MASK 0x4 +#define D18F1x90_Lock_OFFSET 3 +#define D18F1x90_Lock_WIDTH 1 +#define D18F1x90_Lock_MASK 0x8 +#define D18F1x90_Reserved_7_4_OFFSET 4 +#define D18F1x90_Reserved_7_4_WIDTH 4 +#define D18F1x90_Reserved_7_4_MASK 0xf0 +#define D18F1x90_MMIOBase_39_16__OFFSET 8 +#define D18F1x90_MMIOBase_39_16__WIDTH 24 +#define D18F1x90_MMIOBase_39_16__MASK 0xffffff00 + +/// D18F1x90 +typedef union { + struct { ///< + UINT32 RE:1 ; ///< + UINT32 WE:1 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 Lock:1 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 MMIOBase_39_16_:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x90_STRUCT; + +// **** D18F1x94 Register Definition **** +// Address +#define D18F1x94_ADDRESS 0x94 + +// Type +#define D18F1x94_TYPE TYPE_D18F1 +// Field Data +#define D18F1x94_DstNode_OFFSET 0 +#define D18F1x94_DstNode_WIDTH 3 +#define D18F1x94_DstNode_MASK 0x7 +#define D18F1x94_Reserved_3_3_OFFSET 3 +#define D18F1x94_Reserved_3_3_WIDTH 1 +#define D18F1x94_Reserved_3_3_MASK 0x8 +#define D18F1x94_DstLink_OFFSET 4 +#define D18F1x94_DstLink_WIDTH 2 +#define D18F1x94_DstLink_MASK 0x30 +#define D18F1x94_DstSubLink_OFFSET 6 +#define D18F1x94_DstSubLink_WIDTH 1 +#define D18F1x94_DstSubLink_MASK 0x40 +#define D18F1x94_NP_OFFSET 7 +#define D18F1x94_NP_WIDTH 1 +#define D18F1x94_NP_MASK 0x80 +#define D18F1x94_MMIOLimit_39_16__OFFSET 8 +#define D18F1x94_MMIOLimit_39_16__WIDTH 24 +#define D18F1x94_MMIOLimit_39_16__MASK 0xffffff00 + +/// D18F1x94 +typedef union { + struct { ///< + UINT32 DstNode:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 DstLink:2 ; ///< + UINT32 DstSubLink:1 ; ///< + UINT32 NP:1 ; ///< + UINT32 MMIOLimit_39_16_:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x94_STRUCT; + +// **** D18F1x98 Register Definition **** +// Address +#define D18F1x98_ADDRESS 0x98 + +// Type +#define D18F1x98_TYPE TYPE_D18F1 +// Field Data +#define D18F1x98_RE_OFFSET 0 +#define D18F1x98_RE_WIDTH 1 +#define D18F1x98_RE_MASK 0x1 +#define D18F1x98_WE_OFFSET 1 +#define D18F1x98_WE_WIDTH 1 +#define D18F1x98_WE_MASK 0x2 +#define D18F1x98_Reserved_2_2_OFFSET 2 +#define D18F1x98_Reserved_2_2_WIDTH 1 +#define D18F1x98_Reserved_2_2_MASK 0x4 +#define D18F1x98_Lock_OFFSET 3 +#define D18F1x98_Lock_WIDTH 1 +#define D18F1x98_Lock_MASK 0x8 +#define D18F1x98_Reserved_7_4_OFFSET 4 +#define D18F1x98_Reserved_7_4_WIDTH 4 +#define D18F1x98_Reserved_7_4_MASK 0xf0 +#define D18F1x98_MMIOBase_39_16__OFFSET 8 +#define D18F1x98_MMIOBase_39_16__WIDTH 24 +#define D18F1x98_MMIOBase_39_16__MASK 0xffffff00 + +/// D18F1x98 +typedef union { + struct { ///< + UINT32 RE:1 ; ///< + UINT32 WE:1 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 Lock:1 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 MMIOBase_39_16_:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x98_STRUCT; + +// **** D18F1x9C Register Definition **** +// Address +#define D18F1x9C_ADDRESS 0x9c + +// Type +#define D18F1x9C_TYPE TYPE_D18F1 +// Field Data +#define D18F1x9C_DstNode_OFFSET 0 +#define D18F1x9C_DstNode_WIDTH 3 +#define D18F1x9C_DstNode_MASK 0x7 +#define D18F1x9C_Reserved_3_3_OFFSET 3 +#define D18F1x9C_Reserved_3_3_WIDTH 1 +#define D18F1x9C_Reserved_3_3_MASK 0x8 +#define D18F1x9C_DstLink_OFFSET 4 +#define D18F1x9C_DstLink_WIDTH 2 +#define D18F1x9C_DstLink_MASK 0x30 +#define D18F1x9C_DstSubLink_OFFSET 6 +#define D18F1x9C_DstSubLink_WIDTH 1 +#define D18F1x9C_DstSubLink_MASK 0x40 +#define D18F1x9C_NP_OFFSET 7 +#define D18F1x9C_NP_WIDTH 1 +#define D18F1x9C_NP_MASK 0x80 +#define D18F1x9C_MMIOLimit_39_16__OFFSET 8 +#define D18F1x9C_MMIOLimit_39_16__WIDTH 24 +#define D18F1x9C_MMIOLimit_39_16__MASK 0xffffff00 + +/// D18F1x9C +typedef union { + struct { ///< + UINT32 DstNode:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 DstLink:2 ; ///< + UINT32 DstSubLink:1 ; ///< + UINT32 NP:1 ; ///< + UINT32 MMIOLimit_39_16_:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x9C_STRUCT; + +// **** D18F1xA0 Register Definition **** +// Address +#define D18F1xA0_ADDRESS 0xa0 + +// Type +#define D18F1xA0_TYPE TYPE_D18F1 +// Field Data +#define D18F1xA0_RE_OFFSET 0 +#define D18F1xA0_RE_WIDTH 1 +#define D18F1xA0_RE_MASK 0x1 +#define D18F1xA0_WE_OFFSET 1 +#define D18F1xA0_WE_WIDTH 1 +#define D18F1xA0_WE_MASK 0x2 +#define D18F1xA0_Reserved_2_2_OFFSET 2 +#define D18F1xA0_Reserved_2_2_WIDTH 1 +#define D18F1xA0_Reserved_2_2_MASK 0x4 +#define D18F1xA0_Lock_OFFSET 3 +#define D18F1xA0_Lock_WIDTH 1 +#define D18F1xA0_Lock_MASK 0x8 +#define D18F1xA0_Reserved_7_4_OFFSET 4 +#define D18F1xA0_Reserved_7_4_WIDTH 4 +#define D18F1xA0_Reserved_7_4_MASK 0xf0 +#define D18F1xA0_MMIOBase_39_16__OFFSET 8 +#define D18F1xA0_MMIOBase_39_16__WIDTH 24 +#define D18F1xA0_MMIOBase_39_16__MASK 0xffffff00 + +/// D18F1xA0 +typedef union { + struct { ///< + UINT32 RE:1 ; ///< + UINT32 WE:1 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 Lock:1 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 MMIOBase_39_16_:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1xA0_STRUCT; + +// **** D18F1xA4 Register Definition **** +// Address +#define D18F1xA4_ADDRESS 0xa4 + +// Type +#define D18F1xA4_TYPE TYPE_D18F1 +// Field Data +#define D18F1xA4_DstNode_OFFSET 0 +#define D18F1xA4_DstNode_WIDTH 3 +#define D18F1xA4_DstNode_MASK 0x7 +#define D18F1xA4_Reserved_3_3_OFFSET 3 +#define D18F1xA4_Reserved_3_3_WIDTH 1 +#define D18F1xA4_Reserved_3_3_MASK 0x8 +#define D18F1xA4_DstLink_OFFSET 4 +#define D18F1xA4_DstLink_WIDTH 2 +#define D18F1xA4_DstLink_MASK 0x30 +#define D18F1xA4_DstSubLink_OFFSET 6 +#define D18F1xA4_DstSubLink_WIDTH 1 +#define D18F1xA4_DstSubLink_MASK 0x40 +#define D18F1xA4_NP_OFFSET 7 +#define D18F1xA4_NP_WIDTH 1 +#define D18F1xA4_NP_MASK 0x80 +#define D18F1xA4_MMIOLimit_39_16__OFFSET 8 +#define D18F1xA4_MMIOLimit_39_16__WIDTH 24 +#define D18F1xA4_MMIOLimit_39_16__MASK 0xffffff00 + +/// D18F1xA4 +typedef union { + struct { ///< + UINT32 DstNode:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 DstLink:2 ; ///< + UINT32 DstSubLink:1 ; ///< + UINT32 NP:1 ; ///< + UINT32 MMIOLimit_39_16_:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1xA4_STRUCT; + +// **** D18F1xA8 Register Definition **** +// Address +#define D18F1xA8_ADDRESS 0xa8 + +// Type +#define D18F1xA8_TYPE TYPE_D18F1 +// Field Data +#define D18F1xA8_RE_OFFSET 0 +#define D18F1xA8_RE_WIDTH 1 +#define D18F1xA8_RE_MASK 0x1 +#define D18F1xA8_WE_OFFSET 1 +#define D18F1xA8_WE_WIDTH 1 +#define D18F1xA8_WE_MASK 0x2 +#define D18F1xA8_Reserved_2_2_OFFSET 2 +#define D18F1xA8_Reserved_2_2_WIDTH 1 +#define D18F1xA8_Reserved_2_2_MASK 0x4 +#define D18F1xA8_Lock_OFFSET 3 +#define D18F1xA8_Lock_WIDTH 1 +#define D18F1xA8_Lock_MASK 0x8 +#define D18F1xA8_Reserved_7_4_OFFSET 4 +#define D18F1xA8_Reserved_7_4_WIDTH 4 +#define D18F1xA8_Reserved_7_4_MASK 0xf0 +#define D18F1xA8_MMIOBase_39_16__OFFSET 8 +#define D18F1xA8_MMIOBase_39_16__WIDTH 24 +#define D18F1xA8_MMIOBase_39_16__MASK 0xffffff00 + +/// D18F1xA8 +typedef union { + struct { ///< + UINT32 RE:1 ; ///< + UINT32 WE:1 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 Lock:1 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 MMIOBase_39_16_:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1xA8_STRUCT; + +// **** D18F1xAC Register Definition **** +// Address +#define D18F1xAC_ADDRESS 0xac + +// Type +#define D18F1xAC_TYPE TYPE_D18F1 +// Field Data +#define D18F1xAC_DstNode_OFFSET 0 +#define D18F1xAC_DstNode_WIDTH 3 +#define D18F1xAC_DstNode_MASK 0x7 +#define D18F1xAC_Reserved_3_3_OFFSET 3 +#define D18F1xAC_Reserved_3_3_WIDTH 1 +#define D18F1xAC_Reserved_3_3_MASK 0x8 +#define D18F1xAC_DstLink_OFFSET 4 +#define D18F1xAC_DstLink_WIDTH 2 +#define D18F1xAC_DstLink_MASK 0x30 +#define D18F1xAC_DstSubLink_OFFSET 6 +#define D18F1xAC_DstSubLink_WIDTH 1 +#define D18F1xAC_DstSubLink_MASK 0x40 +#define D18F1xAC_NP_OFFSET 7 +#define D18F1xAC_NP_WIDTH 1 +#define D18F1xAC_NP_MASK 0x80 +#define D18F1xAC_MMIOLimit_39_16__OFFSET 8 +#define D18F1xAC_MMIOLimit_39_16__WIDTH 24 +#define D18F1xAC_MMIOLimit_39_16__MASK 0xffffff00 + +/// D18F1xAC +typedef union { + struct { ///< + UINT32 DstNode:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 DstLink:2 ; ///< + UINT32 DstSubLink:1 ; ///< + UINT32 NP:1 ; ///< + UINT32 MMIOLimit_39_16_:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1xAC_STRUCT; + +// **** D18F1xB0 Register Definition **** +// Address +#define D18F1xB0_ADDRESS 0xb0 + +// Type +#define D18F1xB0_TYPE TYPE_D18F1 +// Field Data +#define D18F1xB0_RE_OFFSET 0 +#define D18F1xB0_RE_WIDTH 1 +#define D18F1xB0_RE_MASK 0x1 +#define D18F1xB0_WE_OFFSET 1 +#define D18F1xB0_WE_WIDTH 1 +#define D18F1xB0_WE_MASK 0x2 +#define D18F1xB0_Reserved_2_2_OFFSET 2 +#define D18F1xB0_Reserved_2_2_WIDTH 1 +#define D18F1xB0_Reserved_2_2_MASK 0x4 +#define D18F1xB0_Lock_OFFSET 3 +#define D18F1xB0_Lock_WIDTH 1 +#define D18F1xB0_Lock_MASK 0x8 +#define D18F1xB0_Reserved_7_4_OFFSET 4 +#define D18F1xB0_Reserved_7_4_WIDTH 4 +#define D18F1xB0_Reserved_7_4_MASK 0xf0 +#define D18F1xB0_MMIOBase_39_16__OFFSET 8 +#define D18F1xB0_MMIOBase_39_16__WIDTH 24 +#define D18F1xB0_MMIOBase_39_16__MASK 0xffffff00 + +/// D18F1xB0 +typedef union { + struct { ///< + UINT32 RE:1 ; ///< + UINT32 WE:1 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 Lock:1 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 MMIOBase_39_16_:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1xB0_STRUCT; + +// **** D18F1xB4 Register Definition **** +// Address +#define D18F1xB4_ADDRESS 0xb4 + +// Type +#define D18F1xB4_TYPE TYPE_D18F1 +// Field Data +#define D18F1xB4_DstNode_OFFSET 0 +#define D18F1xB4_DstNode_WIDTH 3 +#define D18F1xB4_DstNode_MASK 0x7 +#define D18F1xB4_Reserved_3_3_OFFSET 3 +#define D18F1xB4_Reserved_3_3_WIDTH 1 +#define D18F1xB4_Reserved_3_3_MASK 0x8 +#define D18F1xB4_DstLink_OFFSET 4 +#define D18F1xB4_DstLink_WIDTH 2 +#define D18F1xB4_DstLink_MASK 0x30 +#define D18F1xB4_DstSubLink_OFFSET 6 +#define D18F1xB4_DstSubLink_WIDTH 1 +#define D18F1xB4_DstSubLink_MASK 0x40 +#define D18F1xB4_NP_OFFSET 7 +#define D18F1xB4_NP_WIDTH 1 +#define D18F1xB4_NP_MASK 0x80 +#define D18F1xB4_MMIOLimit_39_16__OFFSET 8 +#define D18F1xB4_MMIOLimit_39_16__WIDTH 24 +#define D18F1xB4_MMIOLimit_39_16__MASK 0xffffff00 + +/// D18F1xB4 +typedef union { + struct { ///< + UINT32 DstNode:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 DstLink:2 ; ///< + UINT32 DstSubLink:1 ; ///< + UINT32 NP:1 ; ///< + UINT32 MMIOLimit_39_16_:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1xB4_STRUCT; + +// **** D18F1xB8 Register Definition **** +// Address +#define D18F1xB8_ADDRESS 0xb8 + +// Type +#define D18F1xB8_TYPE TYPE_D18F1 +// Field Data +#define D18F1xB8_RE_OFFSET 0 +#define D18F1xB8_RE_WIDTH 1 +#define D18F1xB8_RE_MASK 0x1 +#define D18F1xB8_WE_OFFSET 1 +#define D18F1xB8_WE_WIDTH 1 +#define D18F1xB8_WE_MASK 0x2 +#define D18F1xB8_Reserved_2_2_OFFSET 2 +#define D18F1xB8_Reserved_2_2_WIDTH 1 +#define D18F1xB8_Reserved_2_2_MASK 0x4 +#define D18F1xB8_Lock_OFFSET 3 +#define D18F1xB8_Lock_WIDTH 1 +#define D18F1xB8_Lock_MASK 0x8 +#define D18F1xB8_Reserved_7_4_OFFSET 4 +#define D18F1xB8_Reserved_7_4_WIDTH 4 +#define D18F1xB8_Reserved_7_4_MASK 0xf0 +#define D18F1xB8_MMIOBase_39_16__OFFSET 8 +#define D18F1xB8_MMIOBase_39_16__WIDTH 24 +#define D18F1xB8_MMIOBase_39_16__MASK 0xffffff00 + +/// D18F1xB8 +typedef union { + struct { ///< + UINT32 RE:1 ; ///< + UINT32 WE:1 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 Lock:1 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 MMIOBase_39_16_:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1xB8_STRUCT; + +// **** D18F1xBC Register Definition **** +// Address +#define D18F1xBC_ADDRESS 0xbc + +// Type +#define D18F1xBC_TYPE TYPE_D18F1 +// Field Data +#define D18F1xBC_DstNode_OFFSET 0 +#define D18F1xBC_DstNode_WIDTH 3 +#define D18F1xBC_DstNode_MASK 0x7 +#define D18F1xBC_Reserved_3_3_OFFSET 3 +#define D18F1xBC_Reserved_3_3_WIDTH 1 +#define D18F1xBC_Reserved_3_3_MASK 0x8 +#define D18F1xBC_DstLink_OFFSET 4 +#define D18F1xBC_DstLink_WIDTH 2 +#define D18F1xBC_DstLink_MASK 0x30 +#define D18F1xBC_DstSubLink_OFFSET 6 +#define D18F1xBC_DstSubLink_WIDTH 1 +#define D18F1xBC_DstSubLink_MASK 0x40 +#define D18F1xBC_NP_OFFSET 7 +#define D18F1xBC_NP_WIDTH 1 +#define D18F1xBC_NP_MASK 0x80 +#define D18F1xBC_MMIOLimit_39_16__OFFSET 8 +#define D18F1xBC_MMIOLimit_39_16__WIDTH 24 +#define D18F1xBC_MMIOLimit_39_16__MASK 0xffffff00 + +/// D18F1xBC +typedef union { + struct { ///< + UINT32 DstNode:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 DstLink:2 ; ///< + UINT32 DstSubLink:1 ; ///< + UINT32 NP:1 ; ///< + UINT32 MMIOLimit_39_16_:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1xBC_STRUCT; + +// **** D18F1xC0 Register Definition **** +// Address +#define D18F1xC0_ADDRESS 0xc0 + +// Type +#define D18F1xC0_TYPE TYPE_D18F1 +// Field Data +#define D18F1xC0_RE_OFFSET 0 +#define D18F1xC0_RE_WIDTH 1 +#define D18F1xC0_RE_MASK 0x1 +#define D18F1xC0_WE_OFFSET 1 +#define D18F1xC0_WE_WIDTH 1 +#define D18F1xC0_WE_MASK 0x2 +#define D18F1xC0_Reserved_3_2_OFFSET 2 +#define D18F1xC0_Reserved_3_2_WIDTH 2 +#define D18F1xC0_Reserved_3_2_MASK 0xc +#define D18F1xC0_VE_OFFSET 4 +#define D18F1xC0_VE_WIDTH 1 +#define D18F1xC0_VE_MASK 0x10 +#define D18F1xC0_IE_OFFSET 5 +#define D18F1xC0_IE_WIDTH 1 +#define D18F1xC0_IE_MASK 0x20 +#define D18F1xC0_Reserved_11_6_OFFSET 6 +#define D18F1xC0_Reserved_11_6_WIDTH 6 +#define D18F1xC0_Reserved_11_6_MASK 0xfc0 +#define D18F1xC0_IOBase_24_12__OFFSET 12 +#define D18F1xC0_IOBase_24_12__WIDTH 13 +#define D18F1xC0_IOBase_24_12__MASK 0x1fff000 +#define D18F1xC0_Reserved_31_25_OFFSET 25 +#define D18F1xC0_Reserved_31_25_WIDTH 7 +#define D18F1xC0_Reserved_31_25_MASK 0xfe000000 + +/// D18F1xC0 +typedef union { + struct { ///< + UINT32 RE:1 ; ///< + UINT32 WE:1 ; ///< + UINT32 Reserved_3_2:2 ; ///< + UINT32 VE:1 ; ///< + UINT32 IE:1 ; ///< + UINT32 Reserved_11_6:6 ; ///< + UINT32 IOBase_24_12_:13; ///< + UINT32 Reserved_31_25:7 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1xC0_STRUCT; + +// **** D18F1xC4 Register Definition **** +// Address +#define D18F1xC4_ADDRESS 0xc4 + +// Type +#define D18F1xC4_TYPE TYPE_D18F1 +// Field Data +#define D18F1xC4_DstNode_OFFSET 0 +#define D18F1xC4_DstNode_WIDTH 3 +#define D18F1xC4_DstNode_MASK 0x7 +#define D18F1xC4_Reserved_3_3_OFFSET 3 +#define D18F1xC4_Reserved_3_3_WIDTH 1 +#define D18F1xC4_Reserved_3_3_MASK 0x8 +#define D18F1xC4_DstLink_OFFSET 4 +#define D18F1xC4_DstLink_WIDTH 2 +#define D18F1xC4_DstLink_MASK 0x30 +#define D18F1xC4_DstSubLink_OFFSET 6 +#define D18F1xC4_DstSubLink_WIDTH 1 +#define D18F1xC4_DstSubLink_MASK 0x40 +#define D18F1xC4_Reserved_11_7_OFFSET 7 +#define D18F1xC4_Reserved_11_7_WIDTH 5 +#define D18F1xC4_Reserved_11_7_MASK 0xf80 +#define D18F1xC4_IOLimit_24_12__OFFSET 12 +#define D18F1xC4_IOLimit_24_12__WIDTH 13 +#define D18F1xC4_IOLimit_24_12__MASK 0x1fff000 +#define D18F1xC4_Reserved_31_25_OFFSET 25 +#define D18F1xC4_Reserved_31_25_WIDTH 7 +#define D18F1xC4_Reserved_31_25_MASK 0xfe000000 + +/// D18F1xC4 +typedef union { + struct { ///< + UINT32 DstNode:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 DstLink:2 ; ///< + UINT32 DstSubLink:1 ; ///< + UINT32 Reserved_11_7:5 ; ///< + UINT32 IOLimit_24_12_:13; ///< + UINT32 Reserved_31_25:7 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1xC4_STRUCT; + +// **** D18F1xC8 Register Definition **** +// Address +#define D18F1xC8_ADDRESS 0xc8 + +// Type +#define D18F1xC8_TYPE TYPE_D18F1 +// Field Data +#define D18F1xC8_RE_OFFSET 0 +#define D18F1xC8_RE_WIDTH 1 +#define D18F1xC8_RE_MASK 0x1 +#define D18F1xC8_WE_OFFSET 1 +#define D18F1xC8_WE_WIDTH 1 +#define D18F1xC8_WE_MASK 0x2 +#define D18F1xC8_Reserved_3_2_OFFSET 2 +#define D18F1xC8_Reserved_3_2_WIDTH 2 +#define D18F1xC8_Reserved_3_2_MASK 0xc +#define D18F1xC8_VE_OFFSET 4 +#define D18F1xC8_VE_WIDTH 1 +#define D18F1xC8_VE_MASK 0x10 +#define D18F1xC8_IE_OFFSET 5 +#define D18F1xC8_IE_WIDTH 1 +#define D18F1xC8_IE_MASK 0x20 +#define D18F1xC8_Reserved_11_6_OFFSET 6 +#define D18F1xC8_Reserved_11_6_WIDTH 6 +#define D18F1xC8_Reserved_11_6_MASK 0xfc0 +#define D18F1xC8_IOBase_24_12__OFFSET 12 +#define D18F1xC8_IOBase_24_12__WIDTH 13 +#define D18F1xC8_IOBase_24_12__MASK 0x1fff000 +#define D18F1xC8_Reserved_31_25_OFFSET 25 +#define D18F1xC8_Reserved_31_25_WIDTH 7 +#define D18F1xC8_Reserved_31_25_MASK 0xfe000000 + +/// D18F1xC8 +typedef union { + struct { ///< + UINT32 RE:1 ; ///< + UINT32 WE:1 ; ///< + UINT32 Reserved_3_2:2 ; ///< + UINT32 VE:1 ; ///< + UINT32 IE:1 ; ///< + UINT32 Reserved_11_6:6 ; ///< + UINT32 IOBase_24_12_:13; ///< + UINT32 Reserved_31_25:7 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1xC8_STRUCT; + +// **** D18F1xCC Register Definition **** +// Address +#define D18F1xCC_ADDRESS 0xcc + +// Type +#define D18F1xCC_TYPE TYPE_D18F1 +// Field Data +#define D18F1xCC_DstNode_OFFSET 0 +#define D18F1xCC_DstNode_WIDTH 3 +#define D18F1xCC_DstNode_MASK 0x7 +#define D18F1xCC_Reserved_3_3_OFFSET 3 +#define D18F1xCC_Reserved_3_3_WIDTH 1 +#define D18F1xCC_Reserved_3_3_MASK 0x8 +#define D18F1xCC_DstLink_OFFSET 4 +#define D18F1xCC_DstLink_WIDTH 2 +#define D18F1xCC_DstLink_MASK 0x30 +#define D18F1xCC_DstSubLink_OFFSET 6 +#define D18F1xCC_DstSubLink_WIDTH 1 +#define D18F1xCC_DstSubLink_MASK 0x40 +#define D18F1xCC_Reserved_11_7_OFFSET 7 +#define D18F1xCC_Reserved_11_7_WIDTH 5 +#define D18F1xCC_Reserved_11_7_MASK 0xf80 +#define D18F1xCC_IOLimit_24_12__OFFSET 12 +#define D18F1xCC_IOLimit_24_12__WIDTH 13 +#define D18F1xCC_IOLimit_24_12__MASK 0x1fff000 +#define D18F1xCC_Reserved_31_25_OFFSET 25 +#define D18F1xCC_Reserved_31_25_WIDTH 7 +#define D18F1xCC_Reserved_31_25_MASK 0xfe000000 + +/// D18F1xCC +typedef union { + struct { ///< + UINT32 DstNode:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 DstLink:2 ; ///< + UINT32 DstSubLink:1 ; ///< + UINT32 Reserved_11_7:5 ; ///< + UINT32 IOLimit_24_12_:13; ///< + UINT32 Reserved_31_25:7 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1xCC_STRUCT; + +// **** D18F1xD0 Register Definition **** +// Address +#define D18F1xD0_ADDRESS 0xd0 + +// Type +#define D18F1xD0_TYPE TYPE_D18F1 +// Field Data +#define D18F1xD0_RE_OFFSET 0 +#define D18F1xD0_RE_WIDTH 1 +#define D18F1xD0_RE_MASK 0x1 +#define D18F1xD0_WE_OFFSET 1 +#define D18F1xD0_WE_WIDTH 1 +#define D18F1xD0_WE_MASK 0x2 +#define D18F1xD0_Reserved_3_2_OFFSET 2 +#define D18F1xD0_Reserved_3_2_WIDTH 2 +#define D18F1xD0_Reserved_3_2_MASK 0xc +#define D18F1xD0_VE_OFFSET 4 +#define D18F1xD0_VE_WIDTH 1 +#define D18F1xD0_VE_MASK 0x10 +#define D18F1xD0_IE_OFFSET 5 +#define D18F1xD0_IE_WIDTH 1 +#define D18F1xD0_IE_MASK 0x20 +#define D18F1xD0_Reserved_11_6_OFFSET 6 +#define D18F1xD0_Reserved_11_6_WIDTH 6 +#define D18F1xD0_Reserved_11_6_MASK 0xfc0 +#define D18F1xD0_IOBase_24_12__OFFSET 12 +#define D18F1xD0_IOBase_24_12__WIDTH 13 +#define D18F1xD0_IOBase_24_12__MASK 0x1fff000 +#define D18F1xD0_Reserved_31_25_OFFSET 25 +#define D18F1xD0_Reserved_31_25_WIDTH 7 +#define D18F1xD0_Reserved_31_25_MASK 0xfe000000 + +/// D18F1xD0 +typedef union { + struct { ///< + UINT32 RE:1 ; ///< + UINT32 WE:1 ; ///< + UINT32 Reserved_3_2:2 ; ///< + UINT32 VE:1 ; ///< + UINT32 IE:1 ; ///< + UINT32 Reserved_11_6:6 ; ///< + UINT32 IOBase_24_12_:13; ///< + UINT32 Reserved_31_25:7 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1xD0_STRUCT; + +// **** D18F1xD4 Register Definition **** +// Address +#define D18F1xD4_ADDRESS 0xd4 + +// Type +#define D18F1xD4_TYPE TYPE_D18F1 +// Field Data +#define D18F1xD4_DstNode_OFFSET 0 +#define D18F1xD4_DstNode_WIDTH 3 +#define D18F1xD4_DstNode_MASK 0x7 +#define D18F1xD4_Reserved_3_3_OFFSET 3 +#define D18F1xD4_Reserved_3_3_WIDTH 1 +#define D18F1xD4_Reserved_3_3_MASK 0x8 +#define D18F1xD4_DstLink_OFFSET 4 +#define D18F1xD4_DstLink_WIDTH 2 +#define D18F1xD4_DstLink_MASK 0x30 +#define D18F1xD4_DstSubLink_OFFSET 6 +#define D18F1xD4_DstSubLink_WIDTH 1 +#define D18F1xD4_DstSubLink_MASK 0x40 +#define D18F1xD4_Reserved_11_7_OFFSET 7 +#define D18F1xD4_Reserved_11_7_WIDTH 5 +#define D18F1xD4_Reserved_11_7_MASK 0xf80 +#define D18F1xD4_IOLimit_24_12__OFFSET 12 +#define D18F1xD4_IOLimit_24_12__WIDTH 13 +#define D18F1xD4_IOLimit_24_12__MASK 0x1fff000 +#define D18F1xD4_Reserved_31_25_OFFSET 25 +#define D18F1xD4_Reserved_31_25_WIDTH 7 +#define D18F1xD4_Reserved_31_25_MASK 0xfe000000 + +/// D18F1xD4 +typedef union { + struct { ///< + UINT32 DstNode:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 DstLink:2 ; ///< + UINT32 DstSubLink:1 ; ///< + UINT32 Reserved_11_7:5 ; ///< + UINT32 IOLimit_24_12_:13; ///< + UINT32 Reserved_31_25:7 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1xD4_STRUCT; + +// **** D18F1xD8 Register Definition **** +// Address +#define D18F1xD8_ADDRESS 0xd8 + +// Type +#define D18F1xD8_TYPE TYPE_D18F1 +// Field Data +#define D18F1xD8_RE_OFFSET 0 +#define D18F1xD8_RE_WIDTH 1 +#define D18F1xD8_RE_MASK 0x1 +#define D18F1xD8_WE_OFFSET 1 +#define D18F1xD8_WE_WIDTH 1 +#define D18F1xD8_WE_MASK 0x2 +#define D18F1xD8_Reserved_3_2_OFFSET 2 +#define D18F1xD8_Reserved_3_2_WIDTH 2 +#define D18F1xD8_Reserved_3_2_MASK 0xc +#define D18F1xD8_VE_OFFSET 4 +#define D18F1xD8_VE_WIDTH 1 +#define D18F1xD8_VE_MASK 0x10 +#define D18F1xD8_IE_OFFSET 5 +#define D18F1xD8_IE_WIDTH 1 +#define D18F1xD8_IE_MASK 0x20 +#define D18F1xD8_Reserved_11_6_OFFSET 6 +#define D18F1xD8_Reserved_11_6_WIDTH 6 +#define D18F1xD8_Reserved_11_6_MASK 0xfc0 +#define D18F1xD8_IOBase_24_12__OFFSET 12 +#define D18F1xD8_IOBase_24_12__WIDTH 13 +#define D18F1xD8_IOBase_24_12__MASK 0x1fff000 +#define D18F1xD8_Reserved_31_25_OFFSET 25 +#define D18F1xD8_Reserved_31_25_WIDTH 7 +#define D18F1xD8_Reserved_31_25_MASK 0xfe000000 + +/// D18F1xD8 +typedef union { + struct { ///< + UINT32 RE:1 ; ///< + UINT32 WE:1 ; ///< + UINT32 Reserved_3_2:2 ; ///< + UINT32 VE:1 ; ///< + UINT32 IE:1 ; ///< + UINT32 Reserved_11_6:6 ; ///< + UINT32 IOBase_24_12_:13; ///< + UINT32 Reserved_31_25:7 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1xD8_STRUCT; + +// **** D18F1xDC Register Definition **** +// Address +#define D18F1xDC_ADDRESS 0xdc + +// Type +#define D18F1xDC_TYPE TYPE_D18F1 +// Field Data +#define D18F1xDC_DstNode_OFFSET 0 +#define D18F1xDC_DstNode_WIDTH 3 +#define D18F1xDC_DstNode_MASK 0x7 +#define D18F1xDC_Reserved_3_3_OFFSET 3 +#define D18F1xDC_Reserved_3_3_WIDTH 1 +#define D18F1xDC_Reserved_3_3_MASK 0x8 +#define D18F1xDC_DstLink_OFFSET 4 +#define D18F1xDC_DstLink_WIDTH 2 +#define D18F1xDC_DstLink_MASK 0x30 +#define D18F1xDC_DstSubLink_OFFSET 6 +#define D18F1xDC_DstSubLink_WIDTH 1 +#define D18F1xDC_DstSubLink_MASK 0x40 +#define D18F1xDC_Reserved_11_7_OFFSET 7 +#define D18F1xDC_Reserved_11_7_WIDTH 5 +#define D18F1xDC_Reserved_11_7_MASK 0xf80 +#define D18F1xDC_IOLimit_24_12__OFFSET 12 +#define D18F1xDC_IOLimit_24_12__WIDTH 13 +#define D18F1xDC_IOLimit_24_12__MASK 0x1fff000 +#define D18F1xDC_Reserved_31_25_OFFSET 25 +#define D18F1xDC_Reserved_31_25_WIDTH 7 +#define D18F1xDC_Reserved_31_25_MASK 0xfe000000 + +/// D18F1xDC +typedef union { + struct { ///< + UINT32 DstNode:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 DstLink:2 ; ///< + UINT32 DstSubLink:1 ; ///< + UINT32 Reserved_11_7:5 ; ///< + UINT32 IOLimit_24_12_:13; ///< + UINT32 Reserved_31_25:7 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1xDC_STRUCT; + +// **** D18F1xE0 Register Definition **** +// Address +#define D18F1xE0_ADDRESS 0xe0 + +// Type +#define D18F1xE0_TYPE TYPE_D18F1 +// Field Data +#define D18F1xE0_RE_OFFSET 0 +#define D18F1xE0_RE_WIDTH 1 +#define D18F1xE0_RE_MASK 0x1 +#define D18F1xE0_WE_OFFSET 1 +#define D18F1xE0_WE_WIDTH 1 +#define D18F1xE0_WE_MASK 0x2 +#define D18F1xE0_DevCmpEn_OFFSET 2 +#define D18F1xE0_DevCmpEn_WIDTH 1 +#define D18F1xE0_DevCmpEn_MASK 0x4 +#define D18F1xE0_Reserved_15_3_OFFSET 3 +#define D18F1xE0_Reserved_15_3_WIDTH 13 +#define D18F1xE0_Reserved_15_3_MASK 0xfff8 +#define D18F1xE0_BusNumBase_7_0__OFFSET 16 +#define D18F1xE0_BusNumBase_7_0__WIDTH 8 +#define D18F1xE0_BusNumBase_7_0__MASK 0xff0000 +#define D18F1xE0_BusNumLimit_7_0__OFFSET 24 +#define D18F1xE0_BusNumLimit_7_0__WIDTH 8 +#define D18F1xE0_BusNumLimit_7_0__MASK 0xff000000 + +/// D18F1xE0 +typedef union { + struct { ///< + UINT32 RE:1 ; ///< + UINT32 WE:1 ; ///< + UINT32 DevCmpEn:1 ; ///< + UINT32 Reserved_15_3:13; ///< + UINT32 BusNumBase_7_0_:8 ; ///< + UINT32 BusNumLimit_7_0_:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1xE0_STRUCT; + +// **** D18F1xE4 Register Definition **** +// Address +#define D18F1xE4_ADDRESS 0xe4 + +// Type +#define D18F1xE4_TYPE TYPE_D18F1 +// Field Data +#define D18F1xE4_RE_OFFSET 0 +#define D18F1xE4_RE_WIDTH 1 +#define D18F1xE4_RE_MASK 0x1 +#define D18F1xE4_WE_OFFSET 1 +#define D18F1xE4_WE_WIDTH 1 +#define D18F1xE4_WE_MASK 0x2 +#define D18F1xE4_DevCmpEn_OFFSET 2 +#define D18F1xE4_DevCmpEn_WIDTH 1 +#define D18F1xE4_DevCmpEn_MASK 0x4 +#define D18F1xE4_Reserved_15_3_OFFSET 3 +#define D18F1xE4_Reserved_15_3_WIDTH 13 +#define D18F1xE4_Reserved_15_3_MASK 0xfff8 +#define D18F1xE4_BusNumBase_7_0__OFFSET 16 +#define D18F1xE4_BusNumBase_7_0__WIDTH 8 +#define D18F1xE4_BusNumBase_7_0__MASK 0xff0000 +#define D18F1xE4_BusNumLimit_7_0__OFFSET 24 +#define D18F1xE4_BusNumLimit_7_0__WIDTH 8 +#define D18F1xE4_BusNumLimit_7_0__MASK 0xff000000 + +/// D18F1xE4 +typedef union { + struct { ///< + UINT32 RE:1 ; ///< + UINT32 WE:1 ; ///< + UINT32 DevCmpEn:1 ; ///< + UINT32 Reserved_15_3:13; ///< + UINT32 BusNumBase_7_0_:8 ; ///< + UINT32 BusNumLimit_7_0_:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1xE4_STRUCT; + +// **** D18F1xE8 Register Definition **** +// Address +#define D18F1xE8_ADDRESS 0xe8 + +// Type +#define D18F1xE8_TYPE TYPE_D18F1 +// Field Data +#define D18F1xE8_RE_OFFSET 0 +#define D18F1xE8_RE_WIDTH 1 +#define D18F1xE8_RE_MASK 0x1 +#define D18F1xE8_WE_OFFSET 1 +#define D18F1xE8_WE_WIDTH 1 +#define D18F1xE8_WE_MASK 0x2 +#define D18F1xE8_DevCmpEn_OFFSET 2 +#define D18F1xE8_DevCmpEn_WIDTH 1 +#define D18F1xE8_DevCmpEn_MASK 0x4 +#define D18F1xE8_Reserved_15_3_OFFSET 3 +#define D18F1xE8_Reserved_15_3_WIDTH 13 +#define D18F1xE8_Reserved_15_3_MASK 0xfff8 +#define D18F1xE8_BusNumBase_7_0__OFFSET 16 +#define D18F1xE8_BusNumBase_7_0__WIDTH 8 +#define D18F1xE8_BusNumBase_7_0__MASK 0xff0000 +#define D18F1xE8_BusNumLimit_7_0__OFFSET 24 +#define D18F1xE8_BusNumLimit_7_0__WIDTH 8 +#define D18F1xE8_BusNumLimit_7_0__MASK 0xff000000 + +/// D18F1xE8 +typedef union { + struct { ///< + UINT32 RE:1 ; ///< + UINT32 WE:1 ; ///< + UINT32 DevCmpEn:1 ; ///< + UINT32 Reserved_15_3:13; ///< + UINT32 BusNumBase_7_0_:8 ; ///< + UINT32 BusNumLimit_7_0_:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1xE8_STRUCT; + +// **** D18F1xEC Register Definition **** +// Address +#define D18F1xEC_ADDRESS 0xec + +// Type +#define D18F1xEC_TYPE TYPE_D18F1 +// Field Data +#define D18F1xEC_RE_OFFSET 0 +#define D18F1xEC_RE_WIDTH 1 +#define D18F1xEC_RE_MASK 0x1 +#define D18F1xEC_WE_OFFSET 1 +#define D18F1xEC_WE_WIDTH 1 +#define D18F1xEC_WE_MASK 0x2 +#define D18F1xEC_DevCmpEn_OFFSET 2 +#define D18F1xEC_DevCmpEn_WIDTH 1 +#define D18F1xEC_DevCmpEn_MASK 0x4 +#define D18F1xEC_Reserved_15_3_OFFSET 3 +#define D18F1xEC_Reserved_15_3_WIDTH 13 +#define D18F1xEC_Reserved_15_3_MASK 0xfff8 +#define D18F1xEC_BusNumBase_7_0__OFFSET 16 +#define D18F1xEC_BusNumBase_7_0__WIDTH 8 +#define D18F1xEC_BusNumBase_7_0__MASK 0xff0000 +#define D18F1xEC_BusNumLimit_7_0__OFFSET 24 +#define D18F1xEC_BusNumLimit_7_0__WIDTH 8 +#define D18F1xEC_BusNumLimit_7_0__MASK 0xff000000 + +/// D18F1xEC +typedef union { + struct { ///< + UINT32 RE:1 ; ///< + UINT32 WE:1 ; ///< + UINT32 DevCmpEn:1 ; ///< + UINT32 Reserved_15_3:13; ///< + UINT32 BusNumBase_7_0_:8 ; ///< + UINT32 BusNumLimit_7_0_:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1xEC_STRUCT; + +// **** D18F1xF0 Register Definition **** +// Address +#define D18F1xF0_ADDRESS 0xf0 + +// Type +#define D18F1xF0_TYPE TYPE_D18F1 +// Field Data +#define D18F1xF0_DramHoleValid_OFFSET 0 +#define D18F1xF0_DramHoleValid_WIDTH 1 +#define D18F1xF0_DramHoleValid_MASK 0x1 +#define D18F1xF0_DramMemHoistValid_OFFSET 1 +#define D18F1xF0_DramMemHoistValid_WIDTH 1 +#define D18F1xF0_DramMemHoistValid_MASK 0x2 +#define D18F1xF0_Reserved_2_2_OFFSET 2 +#define D18F1xF0_Reserved_2_2_WIDTH 1 +#define D18F1xF0_Reserved_2_2_MASK 0x4 +#define D18F1xF0_Reserved_6_3_OFFSET 3 +#define D18F1xF0_Reserved_6_3_WIDTH 4 +#define D18F1xF0_Reserved_6_3_MASK 0x78 +#define D18F1xF0_DramHoleOffset_31_23__OFFSET 7 +#define D18F1xF0_DramHoleOffset_31_23__WIDTH 9 +#define D18F1xF0_DramHoleOffset_31_23__MASK 0xff80 +#define D18F1xF0_Reserved_23_16_OFFSET 16 +#define D18F1xF0_Reserved_23_16_WIDTH 8 +#define D18F1xF0_Reserved_23_16_MASK 0xff0000 +#define D18F1xF0_DramHoleBase_31_24__OFFSET 24 +#define D18F1xF0_DramHoleBase_31_24__WIDTH 8 +#define D18F1xF0_DramHoleBase_31_24__MASK 0xff000000 + +/// D18F1xF0 +typedef union { + struct { ///< + UINT32 DramHoleValid:1 ; ///< + UINT32 DramMemHoistValid:1 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 Reserved_6_3:4 ; ///< + UINT32 DramHoleOffset_31_23_:9 ; ///< + UINT32 Reserved_23_16:8 ; ///< + UINT32 DramHoleBase_31_24_:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1xF0_STRUCT; + +// **** D18F1xF4 Register Definition **** +// Address +#define D18F1xF4_ADDRESS 0xf4 + +// Type +#define D18F1xF4_TYPE TYPE_D18F1 +// Field Data +#define D18F1xF4_VE_OFFSET 0 +#define D18F1xF4_VE_WIDTH 1 +#define D18F1xF4_VE_MASK 0x1 +#define D18F1xF4_NP_OFFSET 1 +#define D18F1xF4_NP_WIDTH 1 +#define D18F1xF4_NP_MASK 0x2 +#define D18F1xF4_Reserved_2_2_OFFSET 2 +#define D18F1xF4_Reserved_2_2_WIDTH 1 +#define D18F1xF4_Reserved_2_2_MASK 0x4 +#define D18F1xF4_Lock_OFFSET 3 +#define D18F1xF4_Lock_WIDTH 1 +#define D18F1xF4_Lock_MASK 0x8 +#define D18F1xF4_DstNode_OFFSET 4 +#define D18F1xF4_DstNode_WIDTH 3 +#define D18F1xF4_DstNode_MASK 0x70 +#define D18F1xF4_Reserved_11_7_OFFSET 7 +#define D18F1xF4_Reserved_11_7_WIDTH 5 +#define D18F1xF4_Reserved_11_7_MASK 0xf80 +#define D18F1xF4_DstLink_OFFSET 12 +#define D18F1xF4_DstLink_WIDTH 2 +#define D18F1xF4_DstLink_MASK 0x3000 +#define D18F1xF4_DstSubLink_OFFSET 14 +#define D18F1xF4_DstSubLink_WIDTH 1 +#define D18F1xF4_DstSubLink_MASK 0x4000 +#define D18F1xF4_Reserved_31_15_OFFSET 15 +#define D18F1xF4_Reserved_31_15_WIDTH 17 +#define D18F1xF4_Reserved_31_15_MASK 0xffff8000 + +/// D18F1xF4 +typedef union { + struct { ///< + UINT32 VE:1 ; ///< + UINT32 NP:1 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 Lock:1 ; ///< + UINT32 DstNode:3 ; ///< + UINT32 Reserved_11_7:5 ; ///< + UINT32 DstLink:2 ; ///< + UINT32 DstSubLink:1 ; ///< + UINT32 Reserved_31_15:17; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1xF4_STRUCT; + +// **** D18F1x10C Register Definition **** +// Address +#define D18F1x10C_ADDRESS 0x10c + +// Type +#define D18F1x10C_TYPE TYPE_D18F1 +// Field Data +#define D18F1x10C_DctCfgSel_OFFSET 0 +#define D18F1x10C_DctCfgSel_WIDTH 1 +#define D18F1x10C_DctCfgSel_MASK 0x1 +#define D18F1x10C_Reserved_2_1_OFFSET 1 +#define D18F1x10C_Reserved_2_1_WIDTH 2 +#define D18F1x10C_Reserved_2_1_MASK 0x6 +#define D18F1x10C_MemPsSel_OFFSET 3 +#define D18F1x10C_MemPsSel_WIDTH 1 +#define D18F1x10C_MemPsSel_MASK 0x8 +#define D18F1x10C_NbPsSel_OFFSET 4 +#define D18F1x10C_NbPsSel_WIDTH 2 +#define D18F1x10C_NbPsSel_MASK 0x30 +#define D18F1x10C_Unused_31_6_OFFSET 6 +#define D18F1x10C_Unused_31_6_WIDTH 26 +#define D18F1x10C_Unused_31_6_MASK 0xffffffc0 + +/// D18F1x10C +typedef union { + struct { ///< + UINT32 DctCfgSel:1 ; ///< + UINT32 Reserved_2_1:2 ; ///< + UINT32 MemPsSel:1 ; ///< + UINT32 NbPsSel:2 ; ///< + UINT32 Unused_31_6:26; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x10C_STRUCT; + +// **** D18F1x120 Register Definition **** +// Address +#define D18F1x120_ADDRESS 0x120 + +// Type +#define D18F1x120_TYPE TYPE_D18F1 +// Field Data +#define D18F1x120_DramBaseAddr_47_27__OFFSET 0 +#define D18F1x120_DramBaseAddr_47_27__WIDTH 21 +#define D18F1x120_DramBaseAddr_47_27__MASK 0x1fffff +#define D18F1x120_Reserved_31_21_OFFSET 21 +#define D18F1x120_Reserved_31_21_WIDTH 11 +#define D18F1x120_Reserved_31_21_MASK 0xffe00000 + +/// D18F1x120 +typedef union { + struct { ///< + UINT32 DramBaseAddr_47_27_:21; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x120_STRUCT; + +// **** D18F1x124 Register Definition **** +// Address +#define D18F1x124_ADDRESS 0x124 + +// Type +#define D18F1x124_TYPE TYPE_D18F1 +// Field Data +#define D18F1x124_DramLimitAddr_47_27__OFFSET 0 +#define D18F1x124_DramLimitAddr_47_27__WIDTH 21 +#define D18F1x124_DramLimitAddr_47_27__MASK 0x1fffff +#define D18F1x124_Reserved_31_21_OFFSET 21 +#define D18F1x124_Reserved_31_21_WIDTH 11 +#define D18F1x124_Reserved_31_21_MASK 0xffe00000 + +/// D18F1x124 +typedef union { + struct { ///< + UINT32 DramLimitAddr_47_27_:21; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x124_STRUCT; + +// **** D18F1x140 Register Definition **** +// Address +#define D18F1x140_ADDRESS 0x140 + +// Type +#define D18F1x140_TYPE TYPE_D18F1 +// Field Data +#define D18F1x140_DramBase_47_40__OFFSET 0 +#define D18F1x140_DramBase_47_40__WIDTH 8 +#define D18F1x140_DramBase_47_40__MASK 0xff +#define D18F1x140_Reserved_31_8_OFFSET 8 +#define D18F1x140_Reserved_31_8_WIDTH 24 +#define D18F1x140_Reserved_31_8_MASK 0xffffff00 + +/// D18F1x140 +typedef union { + struct { ///< + UINT32 DramBase_47_40_:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x140_STRUCT; + +// **** D18F1x144 Register Definition **** +// Address +#define D18F1x144_ADDRESS 0x144 + +// Type +#define D18F1x144_TYPE TYPE_D18F1 +// Field Data +#define D18F1x144_DramLimit_47_40__OFFSET 0 +#define D18F1x144_DramLimit_47_40__WIDTH 8 +#define D18F1x144_DramLimit_47_40__MASK 0xff +#define D18F1x144_Reserved_31_8_OFFSET 8 +#define D18F1x144_Reserved_31_8_WIDTH 24 +#define D18F1x144_Reserved_31_8_MASK 0xffffff00 + +/// D18F1x144 +typedef union { + struct { ///< + UINT32 DramLimit_47_40_:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x144_STRUCT; + +// **** D18F1x180 Register Definition **** +// Address +#define D18F1x180_ADDRESS 0x180 + +// Type +#define D18F1x180_TYPE TYPE_D18F1 +// Field Data +#define D18F1x180_MMIOBase_47_40__OFFSET 0 +#define D18F1x180_MMIOBase_47_40__WIDTH 8 +#define D18F1x180_MMIOBase_47_40__MASK 0xff +#define D18F1x180_Reserved_15_8_OFFSET 8 +#define D18F1x180_Reserved_15_8_WIDTH 8 +#define D18F1x180_Reserved_15_8_MASK 0xff00 +#define D18F1x180_MMIOLimit_47_40__OFFSET 16 +#define D18F1x180_MMIOLimit_47_40__WIDTH 8 +#define D18F1x180_MMIOLimit_47_40__MASK 0xff0000 +#define D18F1x180_Reserved_31_24_OFFSET 24 +#define D18F1x180_Reserved_31_24_WIDTH 8 +#define D18F1x180_Reserved_31_24_MASK 0xff000000 + +/// D18F1x180 +typedef union { + struct { ///< + UINT32 MMIOBase_47_40_:8 ; ///< + UINT32 Reserved_15_8:8 ; ///< + UINT32 MMIOLimit_47_40_:8 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x180_STRUCT; + +// **** D18F1x184 Register Definition **** +// Address +#define D18F1x184_ADDRESS 0x184 + +// Type +#define D18F1x184_TYPE TYPE_D18F1 +// Field Data +#define D18F1x184_MMIOBase_47_40__OFFSET 0 +#define D18F1x184_MMIOBase_47_40__WIDTH 8 +#define D18F1x184_MMIOBase_47_40__MASK 0xff +#define D18F1x184_Reserved_15_8_OFFSET 8 +#define D18F1x184_Reserved_15_8_WIDTH 8 +#define D18F1x184_Reserved_15_8_MASK 0xff00 +#define D18F1x184_MMIOLimit_47_40__OFFSET 16 +#define D18F1x184_MMIOLimit_47_40__WIDTH 8 +#define D18F1x184_MMIOLimit_47_40__MASK 0xff0000 +#define D18F1x184_Reserved_31_24_OFFSET 24 +#define D18F1x184_Reserved_31_24_WIDTH 8 +#define D18F1x184_Reserved_31_24_MASK 0xff000000 + +/// D18F1x184 +typedef union { + struct { ///< + UINT32 MMIOBase_47_40_:8 ; ///< + UINT32 Reserved_15_8:8 ; ///< + UINT32 MMIOLimit_47_40_:8 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x184_STRUCT; + +// **** D18F1x188 Register Definition **** +// Address +#define D18F1x188_ADDRESS 0x188 + +// Type +#define D18F1x188_TYPE TYPE_D18F1 +// Field Data +#define D18F1x188_MMIOBase_47_40__OFFSET 0 +#define D18F1x188_MMIOBase_47_40__WIDTH 8 +#define D18F1x188_MMIOBase_47_40__MASK 0xff +#define D18F1x188_Reserved_15_8_OFFSET 8 +#define D18F1x188_Reserved_15_8_WIDTH 8 +#define D18F1x188_Reserved_15_8_MASK 0xff00 +#define D18F1x188_MMIOLimit_47_40__OFFSET 16 +#define D18F1x188_MMIOLimit_47_40__WIDTH 8 +#define D18F1x188_MMIOLimit_47_40__MASK 0xff0000 +#define D18F1x188_Reserved_31_24_OFFSET 24 +#define D18F1x188_Reserved_31_24_WIDTH 8 +#define D18F1x188_Reserved_31_24_MASK 0xff000000 + +/// D18F1x188 +typedef union { + struct { ///< + UINT32 MMIOBase_47_40_:8 ; ///< + UINT32 Reserved_15_8:8 ; ///< + UINT32 MMIOLimit_47_40_:8 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x188_STRUCT; + +// **** D18F1x18C Register Definition **** +// Address +#define D18F1x18C_ADDRESS 0x18c + +// Type +#define D18F1x18C_TYPE TYPE_D18F1 +// Field Data +#define D18F1x18C_MMIOBase_47_40__OFFSET 0 +#define D18F1x18C_MMIOBase_47_40__WIDTH 8 +#define D18F1x18C_MMIOBase_47_40__MASK 0xff +#define D18F1x18C_Reserved_15_8_OFFSET 8 +#define D18F1x18C_Reserved_15_8_WIDTH 8 +#define D18F1x18C_Reserved_15_8_MASK 0xff00 +#define D18F1x18C_MMIOLimit_47_40__OFFSET 16 +#define D18F1x18C_MMIOLimit_47_40__WIDTH 8 +#define D18F1x18C_MMIOLimit_47_40__MASK 0xff0000 +#define D18F1x18C_Reserved_31_24_OFFSET 24 +#define D18F1x18C_Reserved_31_24_WIDTH 8 +#define D18F1x18C_Reserved_31_24_MASK 0xff000000 + +/// D18F1x18C +typedef union { + struct { ///< + UINT32 MMIOBase_47_40_:8 ; ///< + UINT32 Reserved_15_8:8 ; ///< + UINT32 MMIOLimit_47_40_:8 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x18C_STRUCT; + +// **** D18F1x190 Register Definition **** +// Address +#define D18F1x190_ADDRESS 0x190 + +// Type +#define D18F1x190_TYPE TYPE_D18F1 +// Field Data +#define D18F1x190_MMIOBase_47_40__OFFSET 0 +#define D18F1x190_MMIOBase_47_40__WIDTH 8 +#define D18F1x190_MMIOBase_47_40__MASK 0xff +#define D18F1x190_Reserved_15_8_OFFSET 8 +#define D18F1x190_Reserved_15_8_WIDTH 8 +#define D18F1x190_Reserved_15_8_MASK 0xff00 +#define D18F1x190_MMIOLimit_47_40__OFFSET 16 +#define D18F1x190_MMIOLimit_47_40__WIDTH 8 +#define D18F1x190_MMIOLimit_47_40__MASK 0xff0000 +#define D18F1x190_Reserved_31_24_OFFSET 24 +#define D18F1x190_Reserved_31_24_WIDTH 8 +#define D18F1x190_Reserved_31_24_MASK 0xff000000 + +/// D18F1x190 +typedef union { + struct { ///< + UINT32 MMIOBase_47_40_:8 ; ///< + UINT32 Reserved_15_8:8 ; ///< + UINT32 MMIOLimit_47_40_:8 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x190_STRUCT; + +// **** D18F1x194 Register Definition **** +// Address +#define D18F1x194_ADDRESS 0x194 + +// Type +#define D18F1x194_TYPE TYPE_D18F1 +// Field Data +#define D18F1x194_MMIOBase_47_40__OFFSET 0 +#define D18F1x194_MMIOBase_47_40__WIDTH 8 +#define D18F1x194_MMIOBase_47_40__MASK 0xff +#define D18F1x194_Reserved_15_8_OFFSET 8 +#define D18F1x194_Reserved_15_8_WIDTH 8 +#define D18F1x194_Reserved_15_8_MASK 0xff00 +#define D18F1x194_MMIOLimit_47_40__OFFSET 16 +#define D18F1x194_MMIOLimit_47_40__WIDTH 8 +#define D18F1x194_MMIOLimit_47_40__MASK 0xff0000 +#define D18F1x194_Reserved_31_24_OFFSET 24 +#define D18F1x194_Reserved_31_24_WIDTH 8 +#define D18F1x194_Reserved_31_24_MASK 0xff000000 + +/// D18F1x194 +typedef union { + struct { ///< + UINT32 MMIOBase_47_40_:8 ; ///< + UINT32 Reserved_15_8:8 ; ///< + UINT32 MMIOLimit_47_40_:8 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x194_STRUCT; + +// **** D18F1x198 Register Definition **** +// Address +#define D18F1x198_ADDRESS 0x198 + +// Type +#define D18F1x198_TYPE TYPE_D18F1 +// Field Data +#define D18F1x198_MMIOBase_47_40__OFFSET 0 +#define D18F1x198_MMIOBase_47_40__WIDTH 8 +#define D18F1x198_MMIOBase_47_40__MASK 0xff +#define D18F1x198_Reserved_15_8_OFFSET 8 +#define D18F1x198_Reserved_15_8_WIDTH 8 +#define D18F1x198_Reserved_15_8_MASK 0xff00 +#define D18F1x198_MMIOLimit_47_40__OFFSET 16 +#define D18F1x198_MMIOLimit_47_40__WIDTH 8 +#define D18F1x198_MMIOLimit_47_40__MASK 0xff0000 +#define D18F1x198_Reserved_31_24_OFFSET 24 +#define D18F1x198_Reserved_31_24_WIDTH 8 +#define D18F1x198_Reserved_31_24_MASK 0xff000000 + +/// D18F1x198 +typedef union { + struct { ///< + UINT32 MMIOBase_47_40_:8 ; ///< + UINT32 Reserved_15_8:8 ; ///< + UINT32 MMIOLimit_47_40_:8 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x198_STRUCT; + +// **** D18F1x19C Register Definition **** +// Address +#define D18F1x19C_ADDRESS 0x19c + +// Type +#define D18F1x19C_TYPE TYPE_D18F1 +// Field Data +#define D18F1x19C_MMIOBase_47_40__OFFSET 0 +#define D18F1x19C_MMIOBase_47_40__WIDTH 8 +#define D18F1x19C_MMIOBase_47_40__MASK 0xff +#define D18F1x19C_Reserved_15_8_OFFSET 8 +#define D18F1x19C_Reserved_15_8_WIDTH 8 +#define D18F1x19C_Reserved_15_8_MASK 0xff00 +#define D18F1x19C_MMIOLimit_47_40__OFFSET 16 +#define D18F1x19C_MMIOLimit_47_40__WIDTH 8 +#define D18F1x19C_MMIOLimit_47_40__MASK 0xff0000 +#define D18F1x19C_Reserved_31_24_OFFSET 24 +#define D18F1x19C_Reserved_31_24_WIDTH 8 +#define D18F1x19C_Reserved_31_24_MASK 0xff000000 + +/// D18F1x19C +typedef union { + struct { ///< + UINT32 MMIOBase_47_40_:8 ; ///< + UINT32 Reserved_15_8:8 ; ///< + UINT32 MMIOLimit_47_40_:8 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x19C_STRUCT; + +// **** D18F1x1A0 Register Definition **** +// Address +#define D18F1x1A0_ADDRESS 0x1a0 + +// Type +#define D18F1x1A0_TYPE TYPE_D18F1 +// Field Data +#define D18F1x1A0_RE_OFFSET 0 +#define D18F1x1A0_RE_WIDTH 1 +#define D18F1x1A0_RE_MASK 0x1 +#define D18F1x1A0_WE_OFFSET 1 +#define D18F1x1A0_WE_WIDTH 1 +#define D18F1x1A0_WE_MASK 0x2 +#define D18F1x1A0_Reserved_2_2_OFFSET 2 +#define D18F1x1A0_Reserved_2_2_WIDTH 1 +#define D18F1x1A0_Reserved_2_2_MASK 0x4 +#define D18F1x1A0_Lock_OFFSET 3 +#define D18F1x1A0_Lock_WIDTH 1 +#define D18F1x1A0_Lock_MASK 0x8 +#define D18F1x1A0_Reserved_7_4_OFFSET 4 +#define D18F1x1A0_Reserved_7_4_WIDTH 4 +#define D18F1x1A0_Reserved_7_4_MASK 0xf0 +#define D18F1x1A0_MMIOBase_39_16__OFFSET 8 +#define D18F1x1A0_MMIOBase_39_16__WIDTH 24 +#define D18F1x1A0_MMIOBase_39_16__MASK 0xffffff00 + +/// D18F1x1A0 +typedef union { + struct { ///< + UINT32 RE:1 ; ///< + UINT32 WE:1 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 Lock:1 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 MMIOBase_39_16_:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x1A0_STRUCT; + +// **** D18F1x1A4 Register Definition **** +// Address +#define D18F1x1A4_ADDRESS 0x1a4 + +// Type +#define D18F1x1A4_TYPE TYPE_D18F1 +// Field Data +#define D18F1x1A4_DstNode_OFFSET 0 +#define D18F1x1A4_DstNode_WIDTH 3 +#define D18F1x1A4_DstNode_MASK 0x7 +#define D18F1x1A4_Reserved_3_3_OFFSET 3 +#define D18F1x1A4_Reserved_3_3_WIDTH 1 +#define D18F1x1A4_Reserved_3_3_MASK 0x8 +#define D18F1x1A4_DstLink_OFFSET 4 +#define D18F1x1A4_DstLink_WIDTH 2 +#define D18F1x1A4_DstLink_MASK 0x30 +#define D18F1x1A4_DstSubLink_OFFSET 6 +#define D18F1x1A4_DstSubLink_WIDTH 1 +#define D18F1x1A4_DstSubLink_MASK 0x40 +#define D18F1x1A4_NP_OFFSET 7 +#define D18F1x1A4_NP_WIDTH 1 +#define D18F1x1A4_NP_MASK 0x80 +#define D18F1x1A4_MMIOLimit_39_16__OFFSET 8 +#define D18F1x1A4_MMIOLimit_39_16__WIDTH 24 +#define D18F1x1A4_MMIOLimit_39_16__MASK 0xffffff00 + +/// D18F1x1A4 +typedef union { + struct { ///< + UINT32 DstNode:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 DstLink:2 ; ///< + UINT32 DstSubLink:1 ; ///< + UINT32 NP:1 ; ///< + UINT32 MMIOLimit_39_16_:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x1A4_STRUCT; + +// **** D18F1x1A8 Register Definition **** +// Address +#define D18F1x1A8_ADDRESS 0x1a8 + +// Type +#define D18F1x1A8_TYPE TYPE_D18F1 +// Field Data +#define D18F1x1A8_RE_OFFSET 0 +#define D18F1x1A8_RE_WIDTH 1 +#define D18F1x1A8_RE_MASK 0x1 +#define D18F1x1A8_WE_OFFSET 1 +#define D18F1x1A8_WE_WIDTH 1 +#define D18F1x1A8_WE_MASK 0x2 +#define D18F1x1A8_Reserved_2_2_OFFSET 2 +#define D18F1x1A8_Reserved_2_2_WIDTH 1 +#define D18F1x1A8_Reserved_2_2_MASK 0x4 +#define D18F1x1A8_Lock_OFFSET 3 +#define D18F1x1A8_Lock_WIDTH 1 +#define D18F1x1A8_Lock_MASK 0x8 +#define D18F1x1A8_Reserved_7_4_OFFSET 4 +#define D18F1x1A8_Reserved_7_4_WIDTH 4 +#define D18F1x1A8_Reserved_7_4_MASK 0xf0 +#define D18F1x1A8_MMIOBase_39_16__OFFSET 8 +#define D18F1x1A8_MMIOBase_39_16__WIDTH 24 +#define D18F1x1A8_MMIOBase_39_16__MASK 0xffffff00 + +/// D18F1x1A8 +typedef union { + struct { ///< + UINT32 RE:1 ; ///< + UINT32 WE:1 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 Lock:1 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 MMIOBase_39_16_:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x1A8_STRUCT; + +// **** D18F1x1AC Register Definition **** +// Address +#define D18F1x1AC_ADDRESS 0x1ac + +// Type +#define D18F1x1AC_TYPE TYPE_D18F1 +// Field Data +#define D18F1x1AC_DstNode_OFFSET 0 +#define D18F1x1AC_DstNode_WIDTH 3 +#define D18F1x1AC_DstNode_MASK 0x7 +#define D18F1x1AC_Reserved_3_3_OFFSET 3 +#define D18F1x1AC_Reserved_3_3_WIDTH 1 +#define D18F1x1AC_Reserved_3_3_MASK 0x8 +#define D18F1x1AC_DstLink_OFFSET 4 +#define D18F1x1AC_DstLink_WIDTH 2 +#define D18F1x1AC_DstLink_MASK 0x30 +#define D18F1x1AC_DstSubLink_OFFSET 6 +#define D18F1x1AC_DstSubLink_WIDTH 1 +#define D18F1x1AC_DstSubLink_MASK 0x40 +#define D18F1x1AC_NP_OFFSET 7 +#define D18F1x1AC_NP_WIDTH 1 +#define D18F1x1AC_NP_MASK 0x80 +#define D18F1x1AC_MMIOLimit_39_16__OFFSET 8 +#define D18F1x1AC_MMIOLimit_39_16__WIDTH 24 +#define D18F1x1AC_MMIOLimit_39_16__MASK 0xffffff00 + +/// D18F1x1AC +typedef union { + struct { ///< + UINT32 DstNode:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 DstLink:2 ; ///< + UINT32 DstSubLink:1 ; ///< + UINT32 NP:1 ; ///< + UINT32 MMIOLimit_39_16_:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x1AC_STRUCT; + +// **** D18F1x1B0 Register Definition **** +// Address +#define D18F1x1B0_ADDRESS 0x1b0 + +// Type +#define D18F1x1B0_TYPE TYPE_D18F1 +// Field Data +#define D18F1x1B0_RE_OFFSET 0 +#define D18F1x1B0_RE_WIDTH 1 +#define D18F1x1B0_RE_MASK 0x1 +#define D18F1x1B0_WE_OFFSET 1 +#define D18F1x1B0_WE_WIDTH 1 +#define D18F1x1B0_WE_MASK 0x2 +#define D18F1x1B0_Reserved_2_2_OFFSET 2 +#define D18F1x1B0_Reserved_2_2_WIDTH 1 +#define D18F1x1B0_Reserved_2_2_MASK 0x4 +#define D18F1x1B0_Lock_OFFSET 3 +#define D18F1x1B0_Lock_WIDTH 1 +#define D18F1x1B0_Lock_MASK 0x8 +#define D18F1x1B0_Reserved_7_4_OFFSET 4 +#define D18F1x1B0_Reserved_7_4_WIDTH 4 +#define D18F1x1B0_Reserved_7_4_MASK 0xf0 +#define D18F1x1B0_MMIOBase_39_16__OFFSET 8 +#define D18F1x1B0_MMIOBase_39_16__WIDTH 24 +#define D18F1x1B0_MMIOBase_39_16__MASK 0xffffff00 + +/// D18F1x1B0 +typedef union { + struct { ///< + UINT32 RE:1 ; ///< + UINT32 WE:1 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 Lock:1 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 MMIOBase_39_16_:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x1B0_STRUCT; + +// **** D18F1x1B4 Register Definition **** +// Address +#define D18F1x1B4_ADDRESS 0x1b4 + +// Type +#define D18F1x1B4_TYPE TYPE_D18F1 +// Field Data +#define D18F1x1B4_DstNode_OFFSET 0 +#define D18F1x1B4_DstNode_WIDTH 3 +#define D18F1x1B4_DstNode_MASK 0x7 +#define D18F1x1B4_Reserved_3_3_OFFSET 3 +#define D18F1x1B4_Reserved_3_3_WIDTH 1 +#define D18F1x1B4_Reserved_3_3_MASK 0x8 +#define D18F1x1B4_DstLink_OFFSET 4 +#define D18F1x1B4_DstLink_WIDTH 2 +#define D18F1x1B4_DstLink_MASK 0x30 +#define D18F1x1B4_DstSubLink_OFFSET 6 +#define D18F1x1B4_DstSubLink_WIDTH 1 +#define D18F1x1B4_DstSubLink_MASK 0x40 +#define D18F1x1B4_NP_OFFSET 7 +#define D18F1x1B4_NP_WIDTH 1 +#define D18F1x1B4_NP_MASK 0x80 +#define D18F1x1B4_MMIOLimit_39_16__OFFSET 8 +#define D18F1x1B4_MMIOLimit_39_16__WIDTH 24 +#define D18F1x1B4_MMIOLimit_39_16__MASK 0xffffff00 + +/// D18F1x1B4 +typedef union { + struct { ///< + UINT32 DstNode:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 DstLink:2 ; ///< + UINT32 DstSubLink:1 ; ///< + UINT32 NP:1 ; ///< + UINT32 MMIOLimit_39_16_:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x1B4_STRUCT; + +// **** D18F1x1B8 Register Definition **** +// Address +#define D18F1x1B8_ADDRESS 0x1b8 + +// Type +#define D18F1x1B8_TYPE TYPE_D18F1 +// Field Data +#define D18F1x1B8_RE_OFFSET 0 +#define D18F1x1B8_RE_WIDTH 1 +#define D18F1x1B8_RE_MASK 0x1 +#define D18F1x1B8_WE_OFFSET 1 +#define D18F1x1B8_WE_WIDTH 1 +#define D18F1x1B8_WE_MASK 0x2 +#define D18F1x1B8_Reserved_2_2_OFFSET 2 +#define D18F1x1B8_Reserved_2_2_WIDTH 1 +#define D18F1x1B8_Reserved_2_2_MASK 0x4 +#define D18F1x1B8_Lock_OFFSET 3 +#define D18F1x1B8_Lock_WIDTH 1 +#define D18F1x1B8_Lock_MASK 0x8 +#define D18F1x1B8_Reserved_7_4_OFFSET 4 +#define D18F1x1B8_Reserved_7_4_WIDTH 4 +#define D18F1x1B8_Reserved_7_4_MASK 0xf0 +#define D18F1x1B8_MMIOBase_39_16__OFFSET 8 +#define D18F1x1B8_MMIOBase_39_16__WIDTH 24 +#define D18F1x1B8_MMIOBase_39_16__MASK 0xffffff00 + +/// D18F1x1B8 +typedef union { + struct { ///< + UINT32 RE:1 ; ///< + UINT32 WE:1 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 Lock:1 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 MMIOBase_39_16_:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x1B8_STRUCT; + +// **** D18F1x1BC Register Definition **** +// Address +#define D18F1x1BC_ADDRESS 0x1bc + +// Type +#define D18F1x1BC_TYPE TYPE_D18F1 +// Field Data +#define D18F1x1BC_DstNode_OFFSET 0 +#define D18F1x1BC_DstNode_WIDTH 3 +#define D18F1x1BC_DstNode_MASK 0x7 +#define D18F1x1BC_Reserved_3_3_OFFSET 3 +#define D18F1x1BC_Reserved_3_3_WIDTH 1 +#define D18F1x1BC_Reserved_3_3_MASK 0x8 +#define D18F1x1BC_DstLink_OFFSET 4 +#define D18F1x1BC_DstLink_WIDTH 2 +#define D18F1x1BC_DstLink_MASK 0x30 +#define D18F1x1BC_DstSubLink_OFFSET 6 +#define D18F1x1BC_DstSubLink_WIDTH 1 +#define D18F1x1BC_DstSubLink_MASK 0x40 +#define D18F1x1BC_NP_OFFSET 7 +#define D18F1x1BC_NP_WIDTH 1 +#define D18F1x1BC_NP_MASK 0x80 +#define D18F1x1BC_MMIOLimit_39_16__OFFSET 8 +#define D18F1x1BC_MMIOLimit_39_16__WIDTH 24 +#define D18F1x1BC_MMIOLimit_39_16__MASK 0xffffff00 + +/// D18F1x1BC +typedef union { + struct { ///< + UINT32 DstNode:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 DstLink:2 ; ///< + UINT32 DstSubLink:1 ; ///< + UINT32 NP:1 ; ///< + UINT32 MMIOLimit_39_16_:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x1BC_STRUCT; + +// **** D18F1x1C0 Register Definition **** +// Address +#define D18F1x1C0_ADDRESS 0x1c0 + +// Type +#define D18F1x1C0_TYPE TYPE_D18F1 +// Field Data +#define D18F1x1C0_MMIOBase_47_40__OFFSET 0 +#define D18F1x1C0_MMIOBase_47_40__WIDTH 8 +#define D18F1x1C0_MMIOBase_47_40__MASK 0xff +#define D18F1x1C0_Reserved_15_8_OFFSET 8 +#define D18F1x1C0_Reserved_15_8_WIDTH 8 +#define D18F1x1C0_Reserved_15_8_MASK 0xff00 +#define D18F1x1C0_MMIOLimit_47_40__OFFSET 16 +#define D18F1x1C0_MMIOLimit_47_40__WIDTH 8 +#define D18F1x1C0_MMIOLimit_47_40__MASK 0xff0000 +#define D18F1x1C0_Reserved_31_24_OFFSET 24 +#define D18F1x1C0_Reserved_31_24_WIDTH 8 +#define D18F1x1C0_Reserved_31_24_MASK 0xff000000 + +/// D18F1x1C0 +typedef union { + struct { ///< + UINT32 MMIOBase_47_40_:8 ; ///< + UINT32 Reserved_15_8:8 ; ///< + UINT32 MMIOLimit_47_40_:8 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x1C0_STRUCT; + +// **** D18F1x1C4 Register Definition **** +// Address +#define D18F1x1C4_ADDRESS 0x1c4 + +// Type +#define D18F1x1C4_TYPE TYPE_D18F1 +// Field Data +#define D18F1x1C4_MMIOBase_47_40__OFFSET 0 +#define D18F1x1C4_MMIOBase_47_40__WIDTH 8 +#define D18F1x1C4_MMIOBase_47_40__MASK 0xff +#define D18F1x1C4_Reserved_15_8_OFFSET 8 +#define D18F1x1C4_Reserved_15_8_WIDTH 8 +#define D18F1x1C4_Reserved_15_8_MASK 0xff00 +#define D18F1x1C4_MMIOLimit_47_40__OFFSET 16 +#define D18F1x1C4_MMIOLimit_47_40__WIDTH 8 +#define D18F1x1C4_MMIOLimit_47_40__MASK 0xff0000 +#define D18F1x1C4_Reserved_31_24_OFFSET 24 +#define D18F1x1C4_Reserved_31_24_WIDTH 8 +#define D18F1x1C4_Reserved_31_24_MASK 0xff000000 + +/// D18F1x1C4 +typedef union { + struct { ///< + UINT32 MMIOBase_47_40_:8 ; ///< + UINT32 Reserved_15_8:8 ; ///< + UINT32 MMIOLimit_47_40_:8 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x1C4_STRUCT; + +// **** D18F1x1C8 Register Definition **** +// Address +#define D18F1x1C8_ADDRESS 0x1c8 + +// Type +#define D18F1x1C8_TYPE TYPE_D18F1 +// Field Data +#define D18F1x1C8_MMIOBase_47_40__OFFSET 0 +#define D18F1x1C8_MMIOBase_47_40__WIDTH 8 +#define D18F1x1C8_MMIOBase_47_40__MASK 0xff +#define D18F1x1C8_Reserved_15_8_OFFSET 8 +#define D18F1x1C8_Reserved_15_8_WIDTH 8 +#define D18F1x1C8_Reserved_15_8_MASK 0xff00 +#define D18F1x1C8_MMIOLimit_47_40__OFFSET 16 +#define D18F1x1C8_MMIOLimit_47_40__WIDTH 8 +#define D18F1x1C8_MMIOLimit_47_40__MASK 0xff0000 +#define D18F1x1C8_Reserved_31_24_OFFSET 24 +#define D18F1x1C8_Reserved_31_24_WIDTH 8 +#define D18F1x1C8_Reserved_31_24_MASK 0xff000000 + +/// D18F1x1C8 +typedef union { + struct { ///< + UINT32 MMIOBase_47_40_:8 ; ///< + UINT32 Reserved_15_8:8 ; ///< + UINT32 MMIOLimit_47_40_:8 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x1C8_STRUCT; + +// **** D18F1x1CC Register Definition **** +// Address +#define D18F1x1CC_ADDRESS 0x1cc + +// Type +#define D18F1x1CC_TYPE TYPE_D18F1 +// Field Data +#define D18F1x1CC_MMIOBase_47_40__OFFSET 0 +#define D18F1x1CC_MMIOBase_47_40__WIDTH 8 +#define D18F1x1CC_MMIOBase_47_40__MASK 0xff +#define D18F1x1CC_Reserved_15_8_OFFSET 8 +#define D18F1x1CC_Reserved_15_8_WIDTH 8 +#define D18F1x1CC_Reserved_15_8_MASK 0xff00 +#define D18F1x1CC_MMIOLimit_47_40__OFFSET 16 +#define D18F1x1CC_MMIOLimit_47_40__WIDTH 8 +#define D18F1x1CC_MMIOLimit_47_40__MASK 0xff0000 +#define D18F1x1CC_Reserved_31_24_OFFSET 24 +#define D18F1x1CC_Reserved_31_24_WIDTH 8 +#define D18F1x1CC_Reserved_31_24_MASK 0xff000000 + +/// D18F1x1CC +typedef union { + struct { ///< + UINT32 MMIOBase_47_40_:8 ; ///< + UINT32 Reserved_15_8:8 ; ///< + UINT32 MMIOLimit_47_40_:8 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F1x1CC_STRUCT; + +// **** D18F2x00 Register Definition **** +// Address +#define D18F2x00_ADDRESS 0x0 + +// Type +#define D18F2x00_TYPE TYPE_D18F2 +// Field Data +#define D18F2x00_VendorID_OFFSET 0 +#define D18F2x00_VendorID_WIDTH 16 +#define D18F2x00_VendorID_MASK 0xffff +#define D18F2x00_DeviceID_OFFSET 16 +#define D18F2x00_DeviceID_WIDTH 16 +#define D18F2x00_DeviceID_MASK 0xffff0000 + +/// D18F2x00 +typedef union { + struct { ///< + UINT32 VendorID:16; ///< + UINT32 DeviceID:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x00_STRUCT; + +// **** D18F2x08 Register Definition **** +// Address +#define D18F2x08_ADDRESS 0x8 + +// Type +#define D18F2x08_TYPE TYPE_D18F2 +// Field Data +#define D18F2x08_RevID_OFFSET 0 +#define D18F2x08_RevID_WIDTH 8 +#define D18F2x08_RevID_MASK 0xff +#define D18F2x08_ClassCode_OFFSET 8 +#define D18F2x08_ClassCode_WIDTH 24 +#define D18F2x08_ClassCode_MASK 0xffffff00 + +/// D18F2x08 +typedef union { + struct { ///< + UINT32 RevID:8 ; ///< + UINT32 ClassCode:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x08_STRUCT; + +// **** D18F2x0C Register Definition **** +// Address +#define D18F2x0C_ADDRESS 0xc + +// Type +#define D18F2x0C_TYPE TYPE_D18F2 +// Field Data +#define D18F2x0C_HeaderTypeReg_OFFSET 0 +#define D18F2x0C_HeaderTypeReg_WIDTH 32 +#define D18F2x0C_HeaderTypeReg_MASK 0xffffffff + +/// D18F2x0C +typedef union { + struct { ///< + UINT32 HeaderTypeReg:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x0C_STRUCT; + +// **** D18F2x40_dct1 Register Definition **** +// Address +#define D18F2x40_dct1_ADDRESS 0x40 + +// Type +#define D18F2x40_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x40_dct1_CSEnable_OFFSET 0 +#define D18F2x40_dct1_CSEnable_WIDTH 1 +#define D18F2x40_dct1_CSEnable_MASK 0x1 +#define D18F2x40_dct1_Reserved_1_1_OFFSET 1 +#define D18F2x40_dct1_Reserved_1_1_WIDTH 1 +#define D18F2x40_dct1_Reserved_1_1_MASK 0x2 +#define D18F2x40_dct1_TestFail_OFFSET 2 +#define D18F2x40_dct1_TestFail_WIDTH 1 +#define D18F2x40_dct1_TestFail_MASK 0x4 +#define D18F2x40_dct1_OnDimmMirror_OFFSET 3 +#define D18F2x40_dct1_OnDimmMirror_WIDTH 1 +#define D18F2x40_dct1_OnDimmMirror_MASK 0x8 +#define D18F2x40_dct1_Reserved_4_4_OFFSET 4 +#define D18F2x40_dct1_Reserved_4_4_WIDTH 1 +#define D18F2x40_dct1_Reserved_4_4_MASK 0x10 +#define D18F2x40_dct1_BaseAddr_21_11__OFFSET 5 +#define D18F2x40_dct1_BaseAddr_21_11__WIDTH 11 +#define D18F2x40_dct1_BaseAddr_21_11__MASK 0xffe0 +#define D18F2x40_dct1_Reserved_18_16_OFFSET 16 +#define D18F2x40_dct1_Reserved_18_16_WIDTH 3 +#define D18F2x40_dct1_Reserved_18_16_MASK 0x70000 +#define D18F2x40_dct1_BaseAddr_38_27__OFFSET 19 +#define D18F2x40_dct1_BaseAddr_38_27__WIDTH 12 +#define D18F2x40_dct1_BaseAddr_38_27__MASK 0x7ff80000 +#define D18F2x40_dct1_Reserved_31_31_OFFSET 31 +#define D18F2x40_dct1_Reserved_31_31_WIDTH 1 +#define D18F2x40_dct1_Reserved_31_31_MASK 0x80000000 + +/// D18F2x40_dct1 +typedef union { + struct { ///< + UINT32 CSEnable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 TestFail:1 ; ///< + UINT32 OnDimmMirror:1 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 BaseAddr_21_11_:11; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 BaseAddr_38_27_:12; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x40_dct1_STRUCT; + +// **** D18F2x40_dct0 Register Definition **** +// Address +#define D18F2x40_dct0_ADDRESS 0x40 + +// Type +#define D18F2x40_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x40_dct0_CSEnable_OFFSET 0 +#define D18F2x40_dct0_CSEnable_WIDTH 1 +#define D18F2x40_dct0_CSEnable_MASK 0x1 +#define D18F2x40_dct0_Reserved_1_1_OFFSET 1 +#define D18F2x40_dct0_Reserved_1_1_WIDTH 1 +#define D18F2x40_dct0_Reserved_1_1_MASK 0x2 +#define D18F2x40_dct0_TestFail_OFFSET 2 +#define D18F2x40_dct0_TestFail_WIDTH 1 +#define D18F2x40_dct0_TestFail_MASK 0x4 +#define D18F2x40_dct0_OnDimmMirror_OFFSET 3 +#define D18F2x40_dct0_OnDimmMirror_WIDTH 1 +#define D18F2x40_dct0_OnDimmMirror_MASK 0x8 +#define D18F2x40_dct0_Reserved_4_4_OFFSET 4 +#define D18F2x40_dct0_Reserved_4_4_WIDTH 1 +#define D18F2x40_dct0_Reserved_4_4_MASK 0x10 +#define D18F2x40_dct0_BaseAddr_21_11__OFFSET 5 +#define D18F2x40_dct0_BaseAddr_21_11__WIDTH 11 +#define D18F2x40_dct0_BaseAddr_21_11__MASK 0xffe0 +#define D18F2x40_dct0_Reserved_18_16_OFFSET 16 +#define D18F2x40_dct0_Reserved_18_16_WIDTH 3 +#define D18F2x40_dct0_Reserved_18_16_MASK 0x70000 +#define D18F2x40_dct0_BaseAddr_38_27__OFFSET 19 +#define D18F2x40_dct0_BaseAddr_38_27__WIDTH 12 +#define D18F2x40_dct0_BaseAddr_38_27__MASK 0x7ff80000 +#define D18F2x40_dct0_Reserved_31_31_OFFSET 31 +#define D18F2x40_dct0_Reserved_31_31_WIDTH 1 +#define D18F2x40_dct0_Reserved_31_31_MASK 0x80000000 + +/// D18F2x40_dct0 +typedef union { + struct { ///< + UINT32 CSEnable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 TestFail:1 ; ///< + UINT32 OnDimmMirror:1 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 BaseAddr_21_11_:11; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 BaseAddr_38_27_:12; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x40_dct0_STRUCT; + +// **** D18F2x44_dct1 Register Definition **** +// Address +#define D18F2x44_dct1_ADDRESS 0x44 + +// Type +#define D18F2x44_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x44_dct1_CSEnable_OFFSET 0 +#define D18F2x44_dct1_CSEnable_WIDTH 1 +#define D18F2x44_dct1_CSEnable_MASK 0x1 +#define D18F2x44_dct1_Reserved_1_1_OFFSET 1 +#define D18F2x44_dct1_Reserved_1_1_WIDTH 1 +#define D18F2x44_dct1_Reserved_1_1_MASK 0x2 +#define D18F2x44_dct1_TestFail_OFFSET 2 +#define D18F2x44_dct1_TestFail_WIDTH 1 +#define D18F2x44_dct1_TestFail_MASK 0x4 +#define D18F2x44_dct1_OnDimmMirror_OFFSET 3 +#define D18F2x44_dct1_OnDimmMirror_WIDTH 1 +#define D18F2x44_dct1_OnDimmMirror_MASK 0x8 +#define D18F2x44_dct1_Reserved_4_4_OFFSET 4 +#define D18F2x44_dct1_Reserved_4_4_WIDTH 1 +#define D18F2x44_dct1_Reserved_4_4_MASK 0x10 +#define D18F2x44_dct1_BaseAddr_21_11__OFFSET 5 +#define D18F2x44_dct1_BaseAddr_21_11__WIDTH 11 +#define D18F2x44_dct1_BaseAddr_21_11__MASK 0xffe0 +#define D18F2x44_dct1_Reserved_18_16_OFFSET 16 +#define D18F2x44_dct1_Reserved_18_16_WIDTH 3 +#define D18F2x44_dct1_Reserved_18_16_MASK 0x70000 +#define D18F2x44_dct1_BaseAddr_38_27__OFFSET 19 +#define D18F2x44_dct1_BaseAddr_38_27__WIDTH 12 +#define D18F2x44_dct1_BaseAddr_38_27__MASK 0x7ff80000 +#define D18F2x44_dct1_Reserved_31_31_OFFSET 31 +#define D18F2x44_dct1_Reserved_31_31_WIDTH 1 +#define D18F2x44_dct1_Reserved_31_31_MASK 0x80000000 + +/// D18F2x44_dct1 +typedef union { + struct { ///< + UINT32 CSEnable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 TestFail:1 ; ///< + UINT32 OnDimmMirror:1 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 BaseAddr_21_11_:11; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 BaseAddr_38_27_:12; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x44_dct1_STRUCT; + +// **** D18F2x44_dct0 Register Definition **** +// Address +#define D18F2x44_dct0_ADDRESS 0x44 + +// Type +#define D18F2x44_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x44_dct0_CSEnable_OFFSET 0 +#define D18F2x44_dct0_CSEnable_WIDTH 1 +#define D18F2x44_dct0_CSEnable_MASK 0x1 +#define D18F2x44_dct0_Reserved_1_1_OFFSET 1 +#define D18F2x44_dct0_Reserved_1_1_WIDTH 1 +#define D18F2x44_dct0_Reserved_1_1_MASK 0x2 +#define D18F2x44_dct0_TestFail_OFFSET 2 +#define D18F2x44_dct0_TestFail_WIDTH 1 +#define D18F2x44_dct0_TestFail_MASK 0x4 +#define D18F2x44_dct0_OnDimmMirror_OFFSET 3 +#define D18F2x44_dct0_OnDimmMirror_WIDTH 1 +#define D18F2x44_dct0_OnDimmMirror_MASK 0x8 +#define D18F2x44_dct0_Reserved_4_4_OFFSET 4 +#define D18F2x44_dct0_Reserved_4_4_WIDTH 1 +#define D18F2x44_dct0_Reserved_4_4_MASK 0x10 +#define D18F2x44_dct0_BaseAddr_21_11__OFFSET 5 +#define D18F2x44_dct0_BaseAddr_21_11__WIDTH 11 +#define D18F2x44_dct0_BaseAddr_21_11__MASK 0xffe0 +#define D18F2x44_dct0_Reserved_18_16_OFFSET 16 +#define D18F2x44_dct0_Reserved_18_16_WIDTH 3 +#define D18F2x44_dct0_Reserved_18_16_MASK 0x70000 +#define D18F2x44_dct0_BaseAddr_38_27__OFFSET 19 +#define D18F2x44_dct0_BaseAddr_38_27__WIDTH 12 +#define D18F2x44_dct0_BaseAddr_38_27__MASK 0x7ff80000 +#define D18F2x44_dct0_Reserved_31_31_OFFSET 31 +#define D18F2x44_dct0_Reserved_31_31_WIDTH 1 +#define D18F2x44_dct0_Reserved_31_31_MASK 0x80000000 + +/// D18F2x44_dct0 +typedef union { + struct { ///< + UINT32 CSEnable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 TestFail:1 ; ///< + UINT32 OnDimmMirror:1 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 BaseAddr_21_11_:11; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 BaseAddr_38_27_:12; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x44_dct0_STRUCT; + +// **** D18F2x48_dct1 Register Definition **** +// Address +#define D18F2x48_dct1_ADDRESS 0x48 + +// Type +#define D18F2x48_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x48_dct1_CSEnable_OFFSET 0 +#define D18F2x48_dct1_CSEnable_WIDTH 1 +#define D18F2x48_dct1_CSEnable_MASK 0x1 +#define D18F2x48_dct1_Reserved_1_1_OFFSET 1 +#define D18F2x48_dct1_Reserved_1_1_WIDTH 1 +#define D18F2x48_dct1_Reserved_1_1_MASK 0x2 +#define D18F2x48_dct1_TestFail_OFFSET 2 +#define D18F2x48_dct1_TestFail_WIDTH 1 +#define D18F2x48_dct1_TestFail_MASK 0x4 +#define D18F2x48_dct1_OnDimmMirror_OFFSET 3 +#define D18F2x48_dct1_OnDimmMirror_WIDTH 1 +#define D18F2x48_dct1_OnDimmMirror_MASK 0x8 +#define D18F2x48_dct1_Reserved_4_4_OFFSET 4 +#define D18F2x48_dct1_Reserved_4_4_WIDTH 1 +#define D18F2x48_dct1_Reserved_4_4_MASK 0x10 +#define D18F2x48_dct1_BaseAddr_21_11__OFFSET 5 +#define D18F2x48_dct1_BaseAddr_21_11__WIDTH 11 +#define D18F2x48_dct1_BaseAddr_21_11__MASK 0xffe0 +#define D18F2x48_dct1_Reserved_18_16_OFFSET 16 +#define D18F2x48_dct1_Reserved_18_16_WIDTH 3 +#define D18F2x48_dct1_Reserved_18_16_MASK 0x70000 +#define D18F2x48_dct1_BaseAddr_38_27__OFFSET 19 +#define D18F2x48_dct1_BaseAddr_38_27__WIDTH 12 +#define D18F2x48_dct1_BaseAddr_38_27__MASK 0x7ff80000 +#define D18F2x48_dct1_Reserved_31_31_OFFSET 31 +#define D18F2x48_dct1_Reserved_31_31_WIDTH 1 +#define D18F2x48_dct1_Reserved_31_31_MASK 0x80000000 + +/// D18F2x48_dct1 +typedef union { + struct { ///< + UINT32 CSEnable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 TestFail:1 ; ///< + UINT32 OnDimmMirror:1 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 BaseAddr_21_11_:11; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 BaseAddr_38_27_:12; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x48_dct1_STRUCT; + +// **** D18F2x48_dct0 Register Definition **** +// Address +#define D18F2x48_dct0_ADDRESS 0x48 + +// Type +#define D18F2x48_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x48_dct0_CSEnable_OFFSET 0 +#define D18F2x48_dct0_CSEnable_WIDTH 1 +#define D18F2x48_dct0_CSEnable_MASK 0x1 +#define D18F2x48_dct0_Reserved_1_1_OFFSET 1 +#define D18F2x48_dct0_Reserved_1_1_WIDTH 1 +#define D18F2x48_dct0_Reserved_1_1_MASK 0x2 +#define D18F2x48_dct0_TestFail_OFFSET 2 +#define D18F2x48_dct0_TestFail_WIDTH 1 +#define D18F2x48_dct0_TestFail_MASK 0x4 +#define D18F2x48_dct0_OnDimmMirror_OFFSET 3 +#define D18F2x48_dct0_OnDimmMirror_WIDTH 1 +#define D18F2x48_dct0_OnDimmMirror_MASK 0x8 +#define D18F2x48_dct0_Reserved_4_4_OFFSET 4 +#define D18F2x48_dct0_Reserved_4_4_WIDTH 1 +#define D18F2x48_dct0_Reserved_4_4_MASK 0x10 +#define D18F2x48_dct0_BaseAddr_21_11__OFFSET 5 +#define D18F2x48_dct0_BaseAddr_21_11__WIDTH 11 +#define D18F2x48_dct0_BaseAddr_21_11__MASK 0xffe0 +#define D18F2x48_dct0_Reserved_18_16_OFFSET 16 +#define D18F2x48_dct0_Reserved_18_16_WIDTH 3 +#define D18F2x48_dct0_Reserved_18_16_MASK 0x70000 +#define D18F2x48_dct0_BaseAddr_38_27__OFFSET 19 +#define D18F2x48_dct0_BaseAddr_38_27__WIDTH 12 +#define D18F2x48_dct0_BaseAddr_38_27__MASK 0x7ff80000 +#define D18F2x48_dct0_Reserved_31_31_OFFSET 31 +#define D18F2x48_dct0_Reserved_31_31_WIDTH 1 +#define D18F2x48_dct0_Reserved_31_31_MASK 0x80000000 + +/// D18F2x48_dct0 +typedef union { + struct { ///< + UINT32 CSEnable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 TestFail:1 ; ///< + UINT32 OnDimmMirror:1 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 BaseAddr_21_11_:11; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 BaseAddr_38_27_:12; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x48_dct0_STRUCT; + +// **** D18F2x4C_dct1 Register Definition **** +// Address +#define D18F2x4C_dct1_ADDRESS 0x4c + +// Type +#define D18F2x4C_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x4C_dct1_CSEnable_OFFSET 0 +#define D18F2x4C_dct1_CSEnable_WIDTH 1 +#define D18F2x4C_dct1_CSEnable_MASK 0x1 +#define D18F2x4C_dct1_Reserved_1_1_OFFSET 1 +#define D18F2x4C_dct1_Reserved_1_1_WIDTH 1 +#define D18F2x4C_dct1_Reserved_1_1_MASK 0x2 +#define D18F2x4C_dct1_TestFail_OFFSET 2 +#define D18F2x4C_dct1_TestFail_WIDTH 1 +#define D18F2x4C_dct1_TestFail_MASK 0x4 +#define D18F2x4C_dct1_OnDimmMirror_OFFSET 3 +#define D18F2x4C_dct1_OnDimmMirror_WIDTH 1 +#define D18F2x4C_dct1_OnDimmMirror_MASK 0x8 +#define D18F2x4C_dct1_Reserved_4_4_OFFSET 4 +#define D18F2x4C_dct1_Reserved_4_4_WIDTH 1 +#define D18F2x4C_dct1_Reserved_4_4_MASK 0x10 +#define D18F2x4C_dct1_BaseAddr_21_11__OFFSET 5 +#define D18F2x4C_dct1_BaseAddr_21_11__WIDTH 11 +#define D18F2x4C_dct1_BaseAddr_21_11__MASK 0xffe0 +#define D18F2x4C_dct1_Reserved_18_16_OFFSET 16 +#define D18F2x4C_dct1_Reserved_18_16_WIDTH 3 +#define D18F2x4C_dct1_Reserved_18_16_MASK 0x70000 +#define D18F2x4C_dct1_BaseAddr_38_27__OFFSET 19 +#define D18F2x4C_dct1_BaseAddr_38_27__WIDTH 12 +#define D18F2x4C_dct1_BaseAddr_38_27__MASK 0x7ff80000 +#define D18F2x4C_dct1_Reserved_31_31_OFFSET 31 +#define D18F2x4C_dct1_Reserved_31_31_WIDTH 1 +#define D18F2x4C_dct1_Reserved_31_31_MASK 0x80000000 + +/// D18F2x4C_dct1 +typedef union { + struct { ///< + UINT32 CSEnable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 TestFail:1 ; ///< + UINT32 OnDimmMirror:1 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 BaseAddr_21_11_:11; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 BaseAddr_38_27_:12; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x4C_dct1_STRUCT; + +// **** D18F2x4C_dct0 Register Definition **** +// Address +#define D18F2x4C_dct0_ADDRESS 0x4c + +// Type +#define D18F2x4C_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x4C_dct0_CSEnable_OFFSET 0 +#define D18F2x4C_dct0_CSEnable_WIDTH 1 +#define D18F2x4C_dct0_CSEnable_MASK 0x1 +#define D18F2x4C_dct0_Reserved_1_1_OFFSET 1 +#define D18F2x4C_dct0_Reserved_1_1_WIDTH 1 +#define D18F2x4C_dct0_Reserved_1_1_MASK 0x2 +#define D18F2x4C_dct0_TestFail_OFFSET 2 +#define D18F2x4C_dct0_TestFail_WIDTH 1 +#define D18F2x4C_dct0_TestFail_MASK 0x4 +#define D18F2x4C_dct0_OnDimmMirror_OFFSET 3 +#define D18F2x4C_dct0_OnDimmMirror_WIDTH 1 +#define D18F2x4C_dct0_OnDimmMirror_MASK 0x8 +#define D18F2x4C_dct0_Reserved_4_4_OFFSET 4 +#define D18F2x4C_dct0_Reserved_4_4_WIDTH 1 +#define D18F2x4C_dct0_Reserved_4_4_MASK 0x10 +#define D18F2x4C_dct0_BaseAddr_21_11__OFFSET 5 +#define D18F2x4C_dct0_BaseAddr_21_11__WIDTH 11 +#define D18F2x4C_dct0_BaseAddr_21_11__MASK 0xffe0 +#define D18F2x4C_dct0_Reserved_18_16_OFFSET 16 +#define D18F2x4C_dct0_Reserved_18_16_WIDTH 3 +#define D18F2x4C_dct0_Reserved_18_16_MASK 0x70000 +#define D18F2x4C_dct0_BaseAddr_38_27__OFFSET 19 +#define D18F2x4C_dct0_BaseAddr_38_27__WIDTH 12 +#define D18F2x4C_dct0_BaseAddr_38_27__MASK 0x7ff80000 +#define D18F2x4C_dct0_Reserved_31_31_OFFSET 31 +#define D18F2x4C_dct0_Reserved_31_31_WIDTH 1 +#define D18F2x4C_dct0_Reserved_31_31_MASK 0x80000000 + +/// D18F2x4C_dct0 +typedef union { + struct { ///< + UINT32 CSEnable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 TestFail:1 ; ///< + UINT32 OnDimmMirror:1 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 BaseAddr_21_11_:11; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 BaseAddr_38_27_:12; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x4C_dct0_STRUCT; + +// **** D18F2x50_dct1 Register Definition **** +// Address +#define D18F2x50_dct1_ADDRESS 0x50 + +// Type +#define D18F2x50_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x50_dct1_CSEnable_OFFSET 0 +#define D18F2x50_dct1_CSEnable_WIDTH 1 +#define D18F2x50_dct1_CSEnable_MASK 0x1 +#define D18F2x50_dct1_Reserved_1_1_OFFSET 1 +#define D18F2x50_dct1_Reserved_1_1_WIDTH 1 +#define D18F2x50_dct1_Reserved_1_1_MASK 0x2 +#define D18F2x50_dct1_TestFail_OFFSET 2 +#define D18F2x50_dct1_TestFail_WIDTH 1 +#define D18F2x50_dct1_TestFail_MASK 0x4 +#define D18F2x50_dct1_OnDimmMirror_OFFSET 3 +#define D18F2x50_dct1_OnDimmMirror_WIDTH 1 +#define D18F2x50_dct1_OnDimmMirror_MASK 0x8 +#define D18F2x50_dct1_Reserved_4_4_OFFSET 4 +#define D18F2x50_dct1_Reserved_4_4_WIDTH 1 +#define D18F2x50_dct1_Reserved_4_4_MASK 0x10 +#define D18F2x50_dct1_BaseAddr_21_11__OFFSET 5 +#define D18F2x50_dct1_BaseAddr_21_11__WIDTH 11 +#define D18F2x50_dct1_BaseAddr_21_11__MASK 0xffe0 +#define D18F2x50_dct1_Reserved_18_16_OFFSET 16 +#define D18F2x50_dct1_Reserved_18_16_WIDTH 3 +#define D18F2x50_dct1_Reserved_18_16_MASK 0x70000 +#define D18F2x50_dct1_BaseAddr_38_27__OFFSET 19 +#define D18F2x50_dct1_BaseAddr_38_27__WIDTH 12 +#define D18F2x50_dct1_BaseAddr_38_27__MASK 0x7ff80000 +#define D18F2x50_dct1_Reserved_31_31_OFFSET 31 +#define D18F2x50_dct1_Reserved_31_31_WIDTH 1 +#define D18F2x50_dct1_Reserved_31_31_MASK 0x80000000 + +/// D18F2x50_dct1 +typedef union { + struct { ///< + UINT32 CSEnable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 TestFail:1 ; ///< + UINT32 OnDimmMirror:1 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 BaseAddr_21_11_:11; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 BaseAddr_38_27_:12; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x50_dct1_STRUCT; + +// **** D18F2x50_dct0 Register Definition **** +// Address +#define D18F2x50_dct0_ADDRESS 0x50 + +// Type +#define D18F2x50_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x50_dct0_CSEnable_OFFSET 0 +#define D18F2x50_dct0_CSEnable_WIDTH 1 +#define D18F2x50_dct0_CSEnable_MASK 0x1 +#define D18F2x50_dct0_Reserved_1_1_OFFSET 1 +#define D18F2x50_dct0_Reserved_1_1_WIDTH 1 +#define D18F2x50_dct0_Reserved_1_1_MASK 0x2 +#define D18F2x50_dct0_TestFail_OFFSET 2 +#define D18F2x50_dct0_TestFail_WIDTH 1 +#define D18F2x50_dct0_TestFail_MASK 0x4 +#define D18F2x50_dct0_OnDimmMirror_OFFSET 3 +#define D18F2x50_dct0_OnDimmMirror_WIDTH 1 +#define D18F2x50_dct0_OnDimmMirror_MASK 0x8 +#define D18F2x50_dct0_Reserved_4_4_OFFSET 4 +#define D18F2x50_dct0_Reserved_4_4_WIDTH 1 +#define D18F2x50_dct0_Reserved_4_4_MASK 0x10 +#define D18F2x50_dct0_BaseAddr_21_11__OFFSET 5 +#define D18F2x50_dct0_BaseAddr_21_11__WIDTH 11 +#define D18F2x50_dct0_BaseAddr_21_11__MASK 0xffe0 +#define D18F2x50_dct0_Reserved_18_16_OFFSET 16 +#define D18F2x50_dct0_Reserved_18_16_WIDTH 3 +#define D18F2x50_dct0_Reserved_18_16_MASK 0x70000 +#define D18F2x50_dct0_BaseAddr_38_27__OFFSET 19 +#define D18F2x50_dct0_BaseAddr_38_27__WIDTH 12 +#define D18F2x50_dct0_BaseAddr_38_27__MASK 0x7ff80000 +#define D18F2x50_dct0_Reserved_31_31_OFFSET 31 +#define D18F2x50_dct0_Reserved_31_31_WIDTH 1 +#define D18F2x50_dct0_Reserved_31_31_MASK 0x80000000 + +/// D18F2x50_dct0 +typedef union { + struct { ///< + UINT32 CSEnable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 TestFail:1 ; ///< + UINT32 OnDimmMirror:1 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 BaseAddr_21_11_:11; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 BaseAddr_38_27_:12; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x50_dct0_STRUCT; + +// **** D18F2x54_dct0 Register Definition **** +// Address +#define D18F2x54_dct0_ADDRESS 0x54 + +// Type +#define D18F2x54_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x54_dct0_CSEnable_OFFSET 0 +#define D18F2x54_dct0_CSEnable_WIDTH 1 +#define D18F2x54_dct0_CSEnable_MASK 0x1 +#define D18F2x54_dct0_Reserved_1_1_OFFSET 1 +#define D18F2x54_dct0_Reserved_1_1_WIDTH 1 +#define D18F2x54_dct0_Reserved_1_1_MASK 0x2 +#define D18F2x54_dct0_TestFail_OFFSET 2 +#define D18F2x54_dct0_TestFail_WIDTH 1 +#define D18F2x54_dct0_TestFail_MASK 0x4 +#define D18F2x54_dct0_OnDimmMirror_OFFSET 3 +#define D18F2x54_dct0_OnDimmMirror_WIDTH 1 +#define D18F2x54_dct0_OnDimmMirror_MASK 0x8 +#define D18F2x54_dct0_Reserved_4_4_OFFSET 4 +#define D18F2x54_dct0_Reserved_4_4_WIDTH 1 +#define D18F2x54_dct0_Reserved_4_4_MASK 0x10 +#define D18F2x54_dct0_BaseAddr_21_11__OFFSET 5 +#define D18F2x54_dct0_BaseAddr_21_11__WIDTH 11 +#define D18F2x54_dct0_BaseAddr_21_11__MASK 0xffe0 +#define D18F2x54_dct0_Reserved_18_16_OFFSET 16 +#define D18F2x54_dct0_Reserved_18_16_WIDTH 3 +#define D18F2x54_dct0_Reserved_18_16_MASK 0x70000 +#define D18F2x54_dct0_BaseAddr_38_27__OFFSET 19 +#define D18F2x54_dct0_BaseAddr_38_27__WIDTH 12 +#define D18F2x54_dct0_BaseAddr_38_27__MASK 0x7ff80000 +#define D18F2x54_dct0_Reserved_31_31_OFFSET 31 +#define D18F2x54_dct0_Reserved_31_31_WIDTH 1 +#define D18F2x54_dct0_Reserved_31_31_MASK 0x80000000 + +/// D18F2x54_dct0 +typedef union { + struct { ///< + UINT32 CSEnable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 TestFail:1 ; ///< + UINT32 OnDimmMirror:1 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 BaseAddr_21_11_:11; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 BaseAddr_38_27_:12; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x54_dct0_STRUCT; + +// **** D18F2x54_dct1 Register Definition **** +// Address +#define D18F2x54_dct1_ADDRESS 0x54 + +// Type +#define D18F2x54_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x54_dct1_CSEnable_OFFSET 0 +#define D18F2x54_dct1_CSEnable_WIDTH 1 +#define D18F2x54_dct1_CSEnable_MASK 0x1 +#define D18F2x54_dct1_Reserved_1_1_OFFSET 1 +#define D18F2x54_dct1_Reserved_1_1_WIDTH 1 +#define D18F2x54_dct1_Reserved_1_1_MASK 0x2 +#define D18F2x54_dct1_TestFail_OFFSET 2 +#define D18F2x54_dct1_TestFail_WIDTH 1 +#define D18F2x54_dct1_TestFail_MASK 0x4 +#define D18F2x54_dct1_OnDimmMirror_OFFSET 3 +#define D18F2x54_dct1_OnDimmMirror_WIDTH 1 +#define D18F2x54_dct1_OnDimmMirror_MASK 0x8 +#define D18F2x54_dct1_Reserved_4_4_OFFSET 4 +#define D18F2x54_dct1_Reserved_4_4_WIDTH 1 +#define D18F2x54_dct1_Reserved_4_4_MASK 0x10 +#define D18F2x54_dct1_BaseAddr_21_11__OFFSET 5 +#define D18F2x54_dct1_BaseAddr_21_11__WIDTH 11 +#define D18F2x54_dct1_BaseAddr_21_11__MASK 0xffe0 +#define D18F2x54_dct1_Reserved_18_16_OFFSET 16 +#define D18F2x54_dct1_Reserved_18_16_WIDTH 3 +#define D18F2x54_dct1_Reserved_18_16_MASK 0x70000 +#define D18F2x54_dct1_BaseAddr_38_27__OFFSET 19 +#define D18F2x54_dct1_BaseAddr_38_27__WIDTH 12 +#define D18F2x54_dct1_BaseAddr_38_27__MASK 0x7ff80000 +#define D18F2x54_dct1_Reserved_31_31_OFFSET 31 +#define D18F2x54_dct1_Reserved_31_31_WIDTH 1 +#define D18F2x54_dct1_Reserved_31_31_MASK 0x80000000 + +/// D18F2x54_dct1 +typedef union { + struct { ///< + UINT32 CSEnable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 TestFail:1 ; ///< + UINT32 OnDimmMirror:1 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 BaseAddr_21_11_:11; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 BaseAddr_38_27_:12; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x54_dct1_STRUCT; + +// **** D18F2x58_dct1 Register Definition **** +// Address +#define D18F2x58_dct1_ADDRESS 0x58 + +// Type +#define D18F2x58_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x58_dct1_CSEnable_OFFSET 0 +#define D18F2x58_dct1_CSEnable_WIDTH 1 +#define D18F2x58_dct1_CSEnable_MASK 0x1 +#define D18F2x58_dct1_Reserved_1_1_OFFSET 1 +#define D18F2x58_dct1_Reserved_1_1_WIDTH 1 +#define D18F2x58_dct1_Reserved_1_1_MASK 0x2 +#define D18F2x58_dct1_TestFail_OFFSET 2 +#define D18F2x58_dct1_TestFail_WIDTH 1 +#define D18F2x58_dct1_TestFail_MASK 0x4 +#define D18F2x58_dct1_OnDimmMirror_OFFSET 3 +#define D18F2x58_dct1_OnDimmMirror_WIDTH 1 +#define D18F2x58_dct1_OnDimmMirror_MASK 0x8 +#define D18F2x58_dct1_Reserved_4_4_OFFSET 4 +#define D18F2x58_dct1_Reserved_4_4_WIDTH 1 +#define D18F2x58_dct1_Reserved_4_4_MASK 0x10 +#define D18F2x58_dct1_BaseAddr_21_11__OFFSET 5 +#define D18F2x58_dct1_BaseAddr_21_11__WIDTH 11 +#define D18F2x58_dct1_BaseAddr_21_11__MASK 0xffe0 +#define D18F2x58_dct1_Reserved_18_16_OFFSET 16 +#define D18F2x58_dct1_Reserved_18_16_WIDTH 3 +#define D18F2x58_dct1_Reserved_18_16_MASK 0x70000 +#define D18F2x58_dct1_BaseAddr_38_27__OFFSET 19 +#define D18F2x58_dct1_BaseAddr_38_27__WIDTH 12 +#define D18F2x58_dct1_BaseAddr_38_27__MASK 0x7ff80000 +#define D18F2x58_dct1_Reserved_31_31_OFFSET 31 +#define D18F2x58_dct1_Reserved_31_31_WIDTH 1 +#define D18F2x58_dct1_Reserved_31_31_MASK 0x80000000 + +/// D18F2x58_dct1 +typedef union { + struct { ///< + UINT32 CSEnable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 TestFail:1 ; ///< + UINT32 OnDimmMirror:1 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 BaseAddr_21_11_:11; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 BaseAddr_38_27_:12; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x58_dct1_STRUCT; + +// **** D18F2x58_dct0 Register Definition **** +// Address +#define D18F2x58_dct0_ADDRESS 0x58 + +// Type +#define D18F2x58_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x58_dct0_CSEnable_OFFSET 0 +#define D18F2x58_dct0_CSEnable_WIDTH 1 +#define D18F2x58_dct0_CSEnable_MASK 0x1 +#define D18F2x58_dct0_Reserved_1_1_OFFSET 1 +#define D18F2x58_dct0_Reserved_1_1_WIDTH 1 +#define D18F2x58_dct0_Reserved_1_1_MASK 0x2 +#define D18F2x58_dct0_TestFail_OFFSET 2 +#define D18F2x58_dct0_TestFail_WIDTH 1 +#define D18F2x58_dct0_TestFail_MASK 0x4 +#define D18F2x58_dct0_OnDimmMirror_OFFSET 3 +#define D18F2x58_dct0_OnDimmMirror_WIDTH 1 +#define D18F2x58_dct0_OnDimmMirror_MASK 0x8 +#define D18F2x58_dct0_Reserved_4_4_OFFSET 4 +#define D18F2x58_dct0_Reserved_4_4_WIDTH 1 +#define D18F2x58_dct0_Reserved_4_4_MASK 0x10 +#define D18F2x58_dct0_BaseAddr_21_11__OFFSET 5 +#define D18F2x58_dct0_BaseAddr_21_11__WIDTH 11 +#define D18F2x58_dct0_BaseAddr_21_11__MASK 0xffe0 +#define D18F2x58_dct0_Reserved_18_16_OFFSET 16 +#define D18F2x58_dct0_Reserved_18_16_WIDTH 3 +#define D18F2x58_dct0_Reserved_18_16_MASK 0x70000 +#define D18F2x58_dct0_BaseAddr_38_27__OFFSET 19 +#define D18F2x58_dct0_BaseAddr_38_27__WIDTH 12 +#define D18F2x58_dct0_BaseAddr_38_27__MASK 0x7ff80000 +#define D18F2x58_dct0_Reserved_31_31_OFFSET 31 +#define D18F2x58_dct0_Reserved_31_31_WIDTH 1 +#define D18F2x58_dct0_Reserved_31_31_MASK 0x80000000 + +/// D18F2x58_dct0 +typedef union { + struct { ///< + UINT32 CSEnable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 TestFail:1 ; ///< + UINT32 OnDimmMirror:1 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 BaseAddr_21_11_:11; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 BaseAddr_38_27_:12; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x58_dct0_STRUCT; + +// **** D18F2x5C_dct1 Register Definition **** +// Address +#define D18F2x5C_dct1_ADDRESS 0x5c + +// Type +#define D18F2x5C_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x5C_dct1_CSEnable_OFFSET 0 +#define D18F2x5C_dct1_CSEnable_WIDTH 1 +#define D18F2x5C_dct1_CSEnable_MASK 0x1 +#define D18F2x5C_dct1_Reserved_1_1_OFFSET 1 +#define D18F2x5C_dct1_Reserved_1_1_WIDTH 1 +#define D18F2x5C_dct1_Reserved_1_1_MASK 0x2 +#define D18F2x5C_dct1_TestFail_OFFSET 2 +#define D18F2x5C_dct1_TestFail_WIDTH 1 +#define D18F2x5C_dct1_TestFail_MASK 0x4 +#define D18F2x5C_dct1_OnDimmMirror_OFFSET 3 +#define D18F2x5C_dct1_OnDimmMirror_WIDTH 1 +#define D18F2x5C_dct1_OnDimmMirror_MASK 0x8 +#define D18F2x5C_dct1_Reserved_4_4_OFFSET 4 +#define D18F2x5C_dct1_Reserved_4_4_WIDTH 1 +#define D18F2x5C_dct1_Reserved_4_4_MASK 0x10 +#define D18F2x5C_dct1_BaseAddr_21_11__OFFSET 5 +#define D18F2x5C_dct1_BaseAddr_21_11__WIDTH 11 +#define D18F2x5C_dct1_BaseAddr_21_11__MASK 0xffe0 +#define D18F2x5C_dct1_Reserved_18_16_OFFSET 16 +#define D18F2x5C_dct1_Reserved_18_16_WIDTH 3 +#define D18F2x5C_dct1_Reserved_18_16_MASK 0x70000 +#define D18F2x5C_dct1_BaseAddr_38_27__OFFSET 19 +#define D18F2x5C_dct1_BaseAddr_38_27__WIDTH 12 +#define D18F2x5C_dct1_BaseAddr_38_27__MASK 0x7ff80000 +#define D18F2x5C_dct1_Reserved_31_31_OFFSET 31 +#define D18F2x5C_dct1_Reserved_31_31_WIDTH 1 +#define D18F2x5C_dct1_Reserved_31_31_MASK 0x80000000 + +/// D18F2x5C_dct1 +typedef union { + struct { ///< + UINT32 CSEnable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 TestFail:1 ; ///< + UINT32 OnDimmMirror:1 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 BaseAddr_21_11_:11; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 BaseAddr_38_27_:12; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x5C_dct1_STRUCT; + +// **** D18F2x5C_dct0 Register Definition **** +// Address +#define D18F2x5C_dct0_ADDRESS 0x5c + +// Type +#define D18F2x5C_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x5C_dct0_CSEnable_OFFSET 0 +#define D18F2x5C_dct0_CSEnable_WIDTH 1 +#define D18F2x5C_dct0_CSEnable_MASK 0x1 +#define D18F2x5C_dct0_Reserved_1_1_OFFSET 1 +#define D18F2x5C_dct0_Reserved_1_1_WIDTH 1 +#define D18F2x5C_dct0_Reserved_1_1_MASK 0x2 +#define D18F2x5C_dct0_TestFail_OFFSET 2 +#define D18F2x5C_dct0_TestFail_WIDTH 1 +#define D18F2x5C_dct0_TestFail_MASK 0x4 +#define D18F2x5C_dct0_OnDimmMirror_OFFSET 3 +#define D18F2x5C_dct0_OnDimmMirror_WIDTH 1 +#define D18F2x5C_dct0_OnDimmMirror_MASK 0x8 +#define D18F2x5C_dct0_Reserved_4_4_OFFSET 4 +#define D18F2x5C_dct0_Reserved_4_4_WIDTH 1 +#define D18F2x5C_dct0_Reserved_4_4_MASK 0x10 +#define D18F2x5C_dct0_BaseAddr_21_11__OFFSET 5 +#define D18F2x5C_dct0_BaseAddr_21_11__WIDTH 11 +#define D18F2x5C_dct0_BaseAddr_21_11__MASK 0xffe0 +#define D18F2x5C_dct0_Reserved_18_16_OFFSET 16 +#define D18F2x5C_dct0_Reserved_18_16_WIDTH 3 +#define D18F2x5C_dct0_Reserved_18_16_MASK 0x70000 +#define D18F2x5C_dct0_BaseAddr_38_27__OFFSET 19 +#define D18F2x5C_dct0_BaseAddr_38_27__WIDTH 12 +#define D18F2x5C_dct0_BaseAddr_38_27__MASK 0x7ff80000 +#define D18F2x5C_dct0_Reserved_31_31_OFFSET 31 +#define D18F2x5C_dct0_Reserved_31_31_WIDTH 1 +#define D18F2x5C_dct0_Reserved_31_31_MASK 0x80000000 + +/// D18F2x5C_dct0 +typedef union { + struct { ///< + UINT32 CSEnable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 TestFail:1 ; ///< + UINT32 OnDimmMirror:1 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 BaseAddr_21_11_:11; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 BaseAddr_38_27_:12; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x5C_dct0_STRUCT; + +// **** D18F2x60_dct1 Register Definition **** +// Address +#define D18F2x60_dct1_ADDRESS 0x60 + +// Type +#define D18F2x60_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x60_dct1_Reserved_4_0_OFFSET 0 +#define D18F2x60_dct1_Reserved_4_0_WIDTH 5 +#define D18F2x60_dct1_Reserved_4_0_MASK 0x1f +#define D18F2x60_dct1_AddrMask_21_11__OFFSET 5 +#define D18F2x60_dct1_AddrMask_21_11__WIDTH 11 +#define D18F2x60_dct1_AddrMask_21_11__MASK 0xffe0 +#define D18F2x60_dct1_Reserved_18_16_OFFSET 16 +#define D18F2x60_dct1_Reserved_18_16_WIDTH 3 +#define D18F2x60_dct1_Reserved_18_16_MASK 0x70000 +#define D18F2x60_dct1_AddrMask_38_27__OFFSET 19 +#define D18F2x60_dct1_AddrMask_38_27__WIDTH 12 +#define D18F2x60_dct1_AddrMask_38_27__MASK 0x7ff80000 +#define D18F2x60_dct1_Reserved_31_31_OFFSET 31 +#define D18F2x60_dct1_Reserved_31_31_WIDTH 1 +#define D18F2x60_dct1_Reserved_31_31_MASK 0x80000000 + +/// D18F2x60_dct1 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 AddrMask_21_11_:11; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 AddrMask_38_27_:12; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x60_dct1_STRUCT; + +// **** D18F2x60_dct0 Register Definition **** +// Address +#define D18F2x60_dct0_ADDRESS 0x60 + +// Type +#define D18F2x60_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x60_dct0_Reserved_4_0_OFFSET 0 +#define D18F2x60_dct0_Reserved_4_0_WIDTH 5 +#define D18F2x60_dct0_Reserved_4_0_MASK 0x1f +#define D18F2x60_dct0_AddrMask_21_11__OFFSET 5 +#define D18F2x60_dct0_AddrMask_21_11__WIDTH 11 +#define D18F2x60_dct0_AddrMask_21_11__MASK 0xffe0 +#define D18F2x60_dct0_Reserved_18_16_OFFSET 16 +#define D18F2x60_dct0_Reserved_18_16_WIDTH 3 +#define D18F2x60_dct0_Reserved_18_16_MASK 0x70000 +#define D18F2x60_dct0_AddrMask_38_27__OFFSET 19 +#define D18F2x60_dct0_AddrMask_38_27__WIDTH 12 +#define D18F2x60_dct0_AddrMask_38_27__MASK 0x7ff80000 +#define D18F2x60_dct0_Reserved_31_31_OFFSET 31 +#define D18F2x60_dct0_Reserved_31_31_WIDTH 1 +#define D18F2x60_dct0_Reserved_31_31_MASK 0x80000000 + +/// D18F2x60_dct0 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 AddrMask_21_11_:11; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 AddrMask_38_27_:12; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x60_dct0_STRUCT; + +// **** D18F2x64_dct0 Register Definition **** +// Address +#define D18F2x64_dct0_ADDRESS 0x64 + +// Type +#define D18F2x64_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x64_dct0_Reserved_4_0_OFFSET 0 +#define D18F2x64_dct0_Reserved_4_0_WIDTH 5 +#define D18F2x64_dct0_Reserved_4_0_MASK 0x1f +#define D18F2x64_dct0_AddrMask_21_11__OFFSET 5 +#define D18F2x64_dct0_AddrMask_21_11__WIDTH 11 +#define D18F2x64_dct0_AddrMask_21_11__MASK 0xffe0 +#define D18F2x64_dct0_Reserved_18_16_OFFSET 16 +#define D18F2x64_dct0_Reserved_18_16_WIDTH 3 +#define D18F2x64_dct0_Reserved_18_16_MASK 0x70000 +#define D18F2x64_dct0_AddrMask_38_27__OFFSET 19 +#define D18F2x64_dct0_AddrMask_38_27__WIDTH 12 +#define D18F2x64_dct0_AddrMask_38_27__MASK 0x7ff80000 +#define D18F2x64_dct0_Reserved_31_31_OFFSET 31 +#define D18F2x64_dct0_Reserved_31_31_WIDTH 1 +#define D18F2x64_dct0_Reserved_31_31_MASK 0x80000000 + +/// D18F2x64_dct0 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 AddrMask_21_11_:11; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 AddrMask_38_27_:12; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x64_dct0_STRUCT; + +// **** D18F2x64_dct1 Register Definition **** +// Address +#define D18F2x64_dct1_ADDRESS 0x64 + +// Type +#define D18F2x64_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x64_dct1_Reserved_4_0_OFFSET 0 +#define D18F2x64_dct1_Reserved_4_0_WIDTH 5 +#define D18F2x64_dct1_Reserved_4_0_MASK 0x1f +#define D18F2x64_dct1_AddrMask_21_11__OFFSET 5 +#define D18F2x64_dct1_AddrMask_21_11__WIDTH 11 +#define D18F2x64_dct1_AddrMask_21_11__MASK 0xffe0 +#define D18F2x64_dct1_Reserved_18_16_OFFSET 16 +#define D18F2x64_dct1_Reserved_18_16_WIDTH 3 +#define D18F2x64_dct1_Reserved_18_16_MASK 0x70000 +#define D18F2x64_dct1_AddrMask_38_27__OFFSET 19 +#define D18F2x64_dct1_AddrMask_38_27__WIDTH 12 +#define D18F2x64_dct1_AddrMask_38_27__MASK 0x7ff80000 +#define D18F2x64_dct1_Reserved_31_31_OFFSET 31 +#define D18F2x64_dct1_Reserved_31_31_WIDTH 1 +#define D18F2x64_dct1_Reserved_31_31_MASK 0x80000000 + +/// D18F2x64_dct1 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 AddrMask_21_11_:11; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 AddrMask_38_27_:12; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x64_dct1_STRUCT; + +// **** D18F2x68_dct1 Register Definition **** +// Address +#define D18F2x68_dct1_ADDRESS 0x68 + +// Type +#define D18F2x68_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x68_dct1_Reserved_4_0_OFFSET 0 +#define D18F2x68_dct1_Reserved_4_0_WIDTH 5 +#define D18F2x68_dct1_Reserved_4_0_MASK 0x1f +#define D18F2x68_dct1_AddrMask_21_11__OFFSET 5 +#define D18F2x68_dct1_AddrMask_21_11__WIDTH 11 +#define D18F2x68_dct1_AddrMask_21_11__MASK 0xffe0 +#define D18F2x68_dct1_Reserved_18_16_OFFSET 16 +#define D18F2x68_dct1_Reserved_18_16_WIDTH 3 +#define D18F2x68_dct1_Reserved_18_16_MASK 0x70000 +#define D18F2x68_dct1_AddrMask_38_27__OFFSET 19 +#define D18F2x68_dct1_AddrMask_38_27__WIDTH 12 +#define D18F2x68_dct1_AddrMask_38_27__MASK 0x7ff80000 +#define D18F2x68_dct1_Reserved_31_31_OFFSET 31 +#define D18F2x68_dct1_Reserved_31_31_WIDTH 1 +#define D18F2x68_dct1_Reserved_31_31_MASK 0x80000000 + +/// D18F2x68_dct1 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 AddrMask_21_11_:11; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 AddrMask_38_27_:12; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x68_dct1_STRUCT; + +// **** D18F2x68_dct0 Register Definition **** +// Address +#define D18F2x68_dct0_ADDRESS 0x68 + +// Type +#define D18F2x68_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x68_dct0_Reserved_4_0_OFFSET 0 +#define D18F2x68_dct0_Reserved_4_0_WIDTH 5 +#define D18F2x68_dct0_Reserved_4_0_MASK 0x1f +#define D18F2x68_dct0_AddrMask_21_11__OFFSET 5 +#define D18F2x68_dct0_AddrMask_21_11__WIDTH 11 +#define D18F2x68_dct0_AddrMask_21_11__MASK 0xffe0 +#define D18F2x68_dct0_Reserved_18_16_OFFSET 16 +#define D18F2x68_dct0_Reserved_18_16_WIDTH 3 +#define D18F2x68_dct0_Reserved_18_16_MASK 0x70000 +#define D18F2x68_dct0_AddrMask_38_27__OFFSET 19 +#define D18F2x68_dct0_AddrMask_38_27__WIDTH 12 +#define D18F2x68_dct0_AddrMask_38_27__MASK 0x7ff80000 +#define D18F2x68_dct0_Reserved_31_31_OFFSET 31 +#define D18F2x68_dct0_Reserved_31_31_WIDTH 1 +#define D18F2x68_dct0_Reserved_31_31_MASK 0x80000000 + +/// D18F2x68_dct0 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 AddrMask_21_11_:11; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 AddrMask_38_27_:12; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x68_dct0_STRUCT; + +// **** D18F2x6C_dct1 Register Definition **** +// Address +#define D18F2x6C_dct1_ADDRESS 0x6c + +// Type +#define D18F2x6C_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x6C_dct1_Reserved_4_0_OFFSET 0 +#define D18F2x6C_dct1_Reserved_4_0_WIDTH 5 +#define D18F2x6C_dct1_Reserved_4_0_MASK 0x1f +#define D18F2x6C_dct1_AddrMask_21_11__OFFSET 5 +#define D18F2x6C_dct1_AddrMask_21_11__WIDTH 11 +#define D18F2x6C_dct1_AddrMask_21_11__MASK 0xffe0 +#define D18F2x6C_dct1_Reserved_18_16_OFFSET 16 +#define D18F2x6C_dct1_Reserved_18_16_WIDTH 3 +#define D18F2x6C_dct1_Reserved_18_16_MASK 0x70000 +#define D18F2x6C_dct1_AddrMask_38_27__OFFSET 19 +#define D18F2x6C_dct1_AddrMask_38_27__WIDTH 12 +#define D18F2x6C_dct1_AddrMask_38_27__MASK 0x7ff80000 +#define D18F2x6C_dct1_Reserved_31_31_OFFSET 31 +#define D18F2x6C_dct1_Reserved_31_31_WIDTH 1 +#define D18F2x6C_dct1_Reserved_31_31_MASK 0x80000000 + +/// D18F2x6C_dct1 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 AddrMask_21_11_:11; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 AddrMask_38_27_:12; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x6C_dct1_STRUCT; + +// **** D18F2x6C_dct0 Register Definition **** +// Address +#define D18F2x6C_dct0_ADDRESS 0x6c + +// Type +#define D18F2x6C_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x6C_dct0_Reserved_4_0_OFFSET 0 +#define D18F2x6C_dct0_Reserved_4_0_WIDTH 5 +#define D18F2x6C_dct0_Reserved_4_0_MASK 0x1f +#define D18F2x6C_dct0_AddrMask_21_11__OFFSET 5 +#define D18F2x6C_dct0_AddrMask_21_11__WIDTH 11 +#define D18F2x6C_dct0_AddrMask_21_11__MASK 0xffe0 +#define D18F2x6C_dct0_Reserved_18_16_OFFSET 16 +#define D18F2x6C_dct0_Reserved_18_16_WIDTH 3 +#define D18F2x6C_dct0_Reserved_18_16_MASK 0x70000 +#define D18F2x6C_dct0_AddrMask_38_27__OFFSET 19 +#define D18F2x6C_dct0_AddrMask_38_27__WIDTH 12 +#define D18F2x6C_dct0_AddrMask_38_27__MASK 0x7ff80000 +#define D18F2x6C_dct0_Reserved_31_31_OFFSET 31 +#define D18F2x6C_dct0_Reserved_31_31_WIDTH 1 +#define D18F2x6C_dct0_Reserved_31_31_MASK 0x80000000 + +/// D18F2x6C_dct0 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 AddrMask_21_11_:11; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 AddrMask_38_27_:12; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x6C_dct0_STRUCT; + +// **** D18F2x78_dct0 Register Definition **** +// Address +#define D18F2x78_dct0_ADDRESS 0x78 + +// Type +#define D18F2x78_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x78_dct0_Reserved_16_0_OFFSET 0 +#define D18F2x78_dct0_Reserved_16_0_WIDTH 17 +#define D18F2x78_dct0_Reserved_16_0_MASK 0x1ffff +#define D18F2x78_dct0_AddrCmdTriEn_OFFSET 17 +#define D18F2x78_dct0_AddrCmdTriEn_WIDTH 1 +#define D18F2x78_dct0_AddrCmdTriEn_MASK 0x20000 +#define D18F2x78_dct0_Reserved_31_18_OFFSET 18 +#define D18F2x78_dct0_Reserved_31_18_WIDTH 14 +#define D18F2x78_dct0_Reserved_31_18_MASK 0xfffc0000 + +/// D18F2x78_dct0 +typedef union { + struct { ///< + UINT32 Reserved_16_0:17; ///< + UINT32 AddrCmdTriEn:1 ; ///< + UINT32 Reserved_31_18:14; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x78_dct0_STRUCT; + +// **** D18F2x78_dct1 Register Definition **** +// Address +#define D18F2x78_dct1_ADDRESS 0x78 + +// Type +#define D18F2x78_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x78_dct1_Reserved_16_0_OFFSET 0 +#define D18F2x78_dct1_Reserved_16_0_WIDTH 17 +#define D18F2x78_dct1_Reserved_16_0_MASK 0x1ffff +#define D18F2x78_dct1_AddrCmdTriEn_OFFSET 17 +#define D18F2x78_dct1_AddrCmdTriEn_WIDTH 1 +#define D18F2x78_dct1_AddrCmdTriEn_MASK 0x20000 +#define D18F2x78_dct1_Reserved_31_18_OFFSET 18 +#define D18F2x78_dct1_Reserved_31_18_WIDTH 14 +#define D18F2x78_dct1_Reserved_31_18_MASK 0xfffc0000 + +/// D18F2x78_dct1 +typedef union { + struct { ///< + UINT32 Reserved_16_0:17; ///< + UINT32 AddrCmdTriEn:1 ; ///< + UINT32 Reserved_31_18:14; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x78_dct1_STRUCT; + +// **** D18F2x7C_dct1 Register Definition **** +// Address +#define D18F2x7C_dct1_ADDRESS 0x7c + +// Type +#define D18F2x7C_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x7C_dct1_MrsAddress_17_0__OFFSET 0 +#define D18F2x7C_dct1_MrsAddress_17_0__WIDTH 18 +#define D18F2x7C_dct1_MrsAddress_17_0__MASK 0x3ffff +#define D18F2x7C_dct1_MrsBank_2_0__OFFSET 18 +#define D18F2x7C_dct1_MrsBank_2_0__WIDTH 3 +#define D18F2x7C_dct1_MrsBank_2_0__MASK 0x1c0000 +#define D18F2x7C_dct1_MrsChipSel_OFFSET 21 +#define D18F2x7C_dct1_MrsChipSel_WIDTH 3 +#define D18F2x7C_dct1_MrsChipSel_MASK 0xe00000 +#define D18F2x7C_dct1_Reserved_24_24_OFFSET 24 +#define D18F2x7C_dct1_Reserved_24_24_WIDTH 1 +#define D18F2x7C_dct1_Reserved_24_24_MASK 0x1000000 +#define D18F2x7C_dct1_SendAutoRefresh_OFFSET 25 +#define D18F2x7C_dct1_SendAutoRefresh_WIDTH 1 +#define D18F2x7C_dct1_SendAutoRefresh_MASK 0x2000000 +#define D18F2x7C_dct1_SendMrsCmd_OFFSET 26 +#define D18F2x7C_dct1_SendMrsCmd_WIDTH 1 +#define D18F2x7C_dct1_SendMrsCmd_MASK 0x4000000 +#define D18F2x7C_dct1_DeassertMemRstX_OFFSET 27 +#define D18F2x7C_dct1_DeassertMemRstX_WIDTH 1 +#define D18F2x7C_dct1_DeassertMemRstX_MASK 0x8000000 +#define D18F2x7C_dct1_AssertCke_OFFSET 28 +#define D18F2x7C_dct1_AssertCke_WIDTH 1 +#define D18F2x7C_dct1_AssertCke_MASK 0x10000000 +#define D18F2x7C_dct1_SendZQCmd_OFFSET 29 +#define D18F2x7C_dct1_SendZQCmd_WIDTH 1 +#define D18F2x7C_dct1_SendZQCmd_MASK 0x20000000 +#define D18F2x7C_dct1_SendControlWord_OFFSET 30 +#define D18F2x7C_dct1_SendControlWord_WIDTH 1 +#define D18F2x7C_dct1_SendControlWord_MASK 0x40000000 +#define D18F2x7C_dct1_EnDramInit_OFFSET 31 +#define D18F2x7C_dct1_EnDramInit_WIDTH 1 +#define D18F2x7C_dct1_EnDramInit_MASK 0x80000000 + +/// D18F2x7C_dct1 +typedef union { + struct { ///< + UINT32 MrsAddress_17_0_:18; ///< + UINT32 MrsBank_2_0_:3 ; ///< + UINT32 MrsChipSel:3 ; ///< + UINT32 Reserved_24_24:1 ; ///< + UINT32 SendAutoRefresh:1 ; ///< + UINT32 SendMrsCmd:1 ; ///< + UINT32 DeassertMemRstX:1 ; ///< + UINT32 AssertCke:1 ; ///< + UINT32 SendZQCmd:1 ; ///< + UINT32 SendControlWord:1 ; ///< + UINT32 EnDramInit:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x7C_dct1_STRUCT; + +// **** D18F2x7C_dct0 Register Definition **** +// Address +#define D18F2x7C_dct0_ADDRESS 0x7c + +// Type +#define D18F2x7C_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x7C_dct0_MrsAddress_17_0__OFFSET 0 +#define D18F2x7C_dct0_MrsAddress_17_0__WIDTH 18 +#define D18F2x7C_dct0_MrsAddress_17_0__MASK 0x3ffff +#define D18F2x7C_dct0_MrsBank_2_0__OFFSET 18 +#define D18F2x7C_dct0_MrsBank_2_0__WIDTH 3 +#define D18F2x7C_dct0_MrsBank_2_0__MASK 0x1c0000 +#define D18F2x7C_dct0_MrsChipSel_OFFSET 21 +#define D18F2x7C_dct0_MrsChipSel_WIDTH 3 +#define D18F2x7C_dct0_MrsChipSel_MASK 0xe00000 +#define D18F2x7C_dct0_Reserved_24_24_OFFSET 24 +#define D18F2x7C_dct0_Reserved_24_24_WIDTH 1 +#define D18F2x7C_dct0_Reserved_24_24_MASK 0x1000000 +#define D18F2x7C_dct0_SendAutoRefresh_OFFSET 25 +#define D18F2x7C_dct0_SendAutoRefresh_WIDTH 1 +#define D18F2x7C_dct0_SendAutoRefresh_MASK 0x2000000 +#define D18F2x7C_dct0_SendMrsCmd_OFFSET 26 +#define D18F2x7C_dct0_SendMrsCmd_WIDTH 1 +#define D18F2x7C_dct0_SendMrsCmd_MASK 0x4000000 +#define D18F2x7C_dct0_DeassertMemRstX_OFFSET 27 +#define D18F2x7C_dct0_DeassertMemRstX_WIDTH 1 +#define D18F2x7C_dct0_DeassertMemRstX_MASK 0x8000000 +#define D18F2x7C_dct0_AssertCke_OFFSET 28 +#define D18F2x7C_dct0_AssertCke_WIDTH 1 +#define D18F2x7C_dct0_AssertCke_MASK 0x10000000 +#define D18F2x7C_dct0_SendZQCmd_OFFSET 29 +#define D18F2x7C_dct0_SendZQCmd_WIDTH 1 +#define D18F2x7C_dct0_SendZQCmd_MASK 0x20000000 +#define D18F2x7C_dct0_SendControlWord_OFFSET 30 +#define D18F2x7C_dct0_SendControlWord_WIDTH 1 +#define D18F2x7C_dct0_SendControlWord_MASK 0x40000000 +#define D18F2x7C_dct0_EnDramInit_OFFSET 31 +#define D18F2x7C_dct0_EnDramInit_WIDTH 1 +#define D18F2x7C_dct0_EnDramInit_MASK 0x80000000 + +/// D18F2x7C_dct0 +typedef union { + struct { ///< + UINT32 MrsAddress_17_0_:18; ///< + UINT32 MrsBank_2_0_:3 ; ///< + UINT32 MrsChipSel:3 ; ///< + UINT32 Reserved_24_24:1 ; ///< + UINT32 SendAutoRefresh:1 ; ///< + UINT32 SendMrsCmd:1 ; ///< + UINT32 DeassertMemRstX:1 ; ///< + UINT32 AssertCke:1 ; ///< + UINT32 SendZQCmd:1 ; ///< + UINT32 SendControlWord:1 ; ///< + UINT32 EnDramInit:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x7C_dct0_STRUCT; + +// **** D18F2x80_dct1 Register Definition **** +// Address +#define D18F2x80_dct1_ADDRESS 0x80 + +// Type +#define D18F2x80_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x80_dct1_DimmAddrMap0_OFFSET 0 +#define D18F2x80_dct1_DimmAddrMap0_WIDTH 4 +#define D18F2x80_dct1_DimmAddrMap0_MASK 0xf +#define D18F2x80_dct1_DimmAddrMap1_OFFSET 4 +#define D18F2x80_dct1_DimmAddrMap1_WIDTH 4 +#define D18F2x80_dct1_DimmAddrMap1_MASK 0xf0 +#define D18F2x80_dct1_DimmAddrMap2_OFFSET 8 +#define D18F2x80_dct1_DimmAddrMap2_WIDTH 4 +#define D18F2x80_dct1_DimmAddrMap2_MASK 0xf00 +#define D18F2x80_dct1_DimmAddrMap3_OFFSET 12 +#define D18F2x80_dct1_DimmAddrMap3_WIDTH 4 +#define D18F2x80_dct1_DimmAddrMap3_MASK 0xf000 +#define D18F2x80_dct1_Reserved_31_16_OFFSET 16 +#define D18F2x80_dct1_Reserved_31_16_WIDTH 16 +#define D18F2x80_dct1_Reserved_31_16_MASK 0xffff0000 + +/// D18F2x80_dct1 +typedef union { + struct { ///< + UINT32 DimmAddrMap0:4 ; ///< + UINT32 DimmAddrMap1:4 ; ///< + UINT32 DimmAddrMap2:4 ; ///< + UINT32 DimmAddrMap3:4 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x80_dct1_STRUCT; + +// **** D18F2x80_dct0 Register Definition **** +// Address +#define D18F2x80_dct0_ADDRESS 0x80 + +// Type +#define D18F2x80_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x80_dct0_DimmAddrMap0_OFFSET 0 +#define D18F2x80_dct0_DimmAddrMap0_WIDTH 4 +#define D18F2x80_dct0_DimmAddrMap0_MASK 0xf +#define D18F2x80_dct0_DimmAddrMap1_OFFSET 4 +#define D18F2x80_dct0_DimmAddrMap1_WIDTH 4 +#define D18F2x80_dct0_DimmAddrMap1_MASK 0xf0 +#define D18F2x80_dct0_DimmAddrMap2_OFFSET 8 +#define D18F2x80_dct0_DimmAddrMap2_WIDTH 4 +#define D18F2x80_dct0_DimmAddrMap2_MASK 0xf00 +#define D18F2x80_dct0_DimmAddrMap3_OFFSET 12 +#define D18F2x80_dct0_DimmAddrMap3_WIDTH 4 +#define D18F2x80_dct0_DimmAddrMap3_MASK 0xf000 +#define D18F2x80_dct0_Reserved_31_16_OFFSET 16 +#define D18F2x80_dct0_Reserved_31_16_WIDTH 16 +#define D18F2x80_dct0_Reserved_31_16_MASK 0xffff0000 + +/// D18F2x80_dct0 +typedef union { + struct { ///< + UINT32 DimmAddrMap0:4 ; ///< + UINT32 DimmAddrMap1:4 ; ///< + UINT32 DimmAddrMap2:4 ; ///< + UINT32 DimmAddrMap3:4 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x80_dct0_STRUCT; + +// **** D18F2x84_dct1 Register Definition **** +// Address +#define D18F2x84_dct1_ADDRESS 0x84 + +// Type +#define D18F2x84_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x84_dct1_BurstCtrl_OFFSET 0 +#define D18F2x84_dct1_BurstCtrl_WIDTH 2 +#define D18F2x84_dct1_BurstCtrl_MASK 0x3 +#define D18F2x84_dct1_Reserved_22_2_OFFSET 2 +#define D18F2x84_dct1_Reserved_22_2_WIDTH 21 +#define D18F2x84_dct1_Reserved_22_2_MASK 0x7ffffc +#define D18F2x84_dct1_PchgPDModeSel_OFFSET 23 +#define D18F2x84_dct1_PchgPDModeSel_WIDTH 1 +#define D18F2x84_dct1_PchgPDModeSel_MASK 0x800000 +#define D18F2x84_dct1_Reserved_31_24_OFFSET 24 +#define D18F2x84_dct1_Reserved_31_24_WIDTH 8 +#define D18F2x84_dct1_Reserved_31_24_MASK 0xff000000 + +/// D18F2x84_dct1 +typedef union { + struct { ///< + UINT32 BurstCtrl:2 ; ///< + UINT32 Reserved_22_2:21; ///< + UINT32 PchgPDModeSel:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x84_dct1_STRUCT; + +// **** D18F2x84_dct0 Register Definition **** +// Address +#define D18F2x84_dct0_ADDRESS 0x84 + +// Type +#define D18F2x84_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x84_dct0_BurstCtrl_OFFSET 0 +#define D18F2x84_dct0_BurstCtrl_WIDTH 2 +#define D18F2x84_dct0_BurstCtrl_MASK 0x3 +#define D18F2x84_dct0_Reserved_22_2_OFFSET 2 +#define D18F2x84_dct0_Reserved_22_2_WIDTH 21 +#define D18F2x84_dct0_Reserved_22_2_MASK 0x7ffffc +#define D18F2x84_dct0_PchgPDModeSel_OFFSET 23 +#define D18F2x84_dct0_PchgPDModeSel_WIDTH 1 +#define D18F2x84_dct0_PchgPDModeSel_MASK 0x800000 +#define D18F2x84_dct0_Reserved_31_24_OFFSET 24 +#define D18F2x84_dct0_Reserved_31_24_WIDTH 8 +#define D18F2x84_dct0_Reserved_31_24_MASK 0xff000000 + +/// D18F2x84_dct0 +typedef union { + struct { ///< + UINT32 BurstCtrl:2 ; ///< + UINT32 Reserved_22_2:21; ///< + UINT32 PchgPDModeSel:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x84_dct0_STRUCT; + +// **** D18F2x88_dct1 Register Definition **** +// Address +#define D18F2x88_dct1_ADDRESS 0x88 + +// Type +#define D18F2x88_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x88_dct1_Reserved_23_0_OFFSET 0 +#define D18F2x88_dct1_Reserved_23_0_WIDTH 24 +#define D18F2x88_dct1_Reserved_23_0_MASK 0xffffff +#define D18F2x88_dct1_MemClkDis_OFFSET 24 +#define D18F2x88_dct1_MemClkDis_WIDTH 6 +#define D18F2x88_dct1_MemClkDis_MASK 0x3f000000 +#define D18F2x88_dct1_Reserved_31_30_OFFSET 30 +#define D18F2x88_dct1_Reserved_31_30_WIDTH 2 +#define D18F2x88_dct1_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x88_dct1 +typedef union { + struct { ///< + UINT32 Reserved_23_0:24; ///< + UINT32 MemClkDis:6 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x88_dct1_STRUCT; + +// **** D18F2x88_dct0 Register Definition **** +// Address +#define D18F2x88_dct0_ADDRESS 0x88 + +// Type +#define D18F2x88_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x88_dct0_Reserved_23_0_OFFSET 0 +#define D18F2x88_dct0_Reserved_23_0_WIDTH 24 +#define D18F2x88_dct0_Reserved_23_0_MASK 0xffffff +#define D18F2x88_dct0_MemClkDis_OFFSET 24 +#define D18F2x88_dct0_MemClkDis_WIDTH 6 +#define D18F2x88_dct0_MemClkDis_MASK 0x3f000000 +#define D18F2x88_dct0_Reserved_31_30_OFFSET 30 +#define D18F2x88_dct0_Reserved_31_30_WIDTH 2 +#define D18F2x88_dct0_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x88_dct0 +typedef union { + struct { ///< + UINT32 Reserved_23_0:24; ///< + UINT32 MemClkDis:6 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x88_dct0_STRUCT; + +// **** D18F2x8C_dct1 Register Definition **** +// Address +#define D18F2x8C_dct1_ADDRESS 0x8c + +// Type +#define D18F2x8C_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x8C_dct1_Reserved_15_0_OFFSET 0 +#define D18F2x8C_dct1_Reserved_15_0_WIDTH 16 +#define D18F2x8C_dct1_Reserved_15_0_MASK 0xffff +#define D18F2x8C_dct1_Tref_OFFSET 16 +#define D18F2x8C_dct1_Tref_WIDTH 2 +#define D18F2x8C_dct1_Tref_MASK 0x30000 +#define D18F2x8C_dct1_DisAutoRefresh_OFFSET 18 +#define D18F2x8C_dct1_DisAutoRefresh_WIDTH 1 +#define D18F2x8C_dct1_DisAutoRefresh_MASK 0x40000 +#define D18F2x8C_dct1_Reserved_31_19_OFFSET 19 +#define D18F2x8C_dct1_Reserved_31_19_WIDTH 13 +#define D18F2x8C_dct1_Reserved_31_19_MASK 0xfff80000 + +/// D18F2x8C_dct1 +typedef union { + struct { ///< + UINT32 Reserved_15_0:16; ///< + UINT32 Tref:2 ; ///< + UINT32 DisAutoRefresh:1 ; ///< + UINT32 Reserved_31_19:13; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x8C_dct1_STRUCT; + +// **** D18F2x8C_dct0 Register Definition **** +// Address +#define D18F2x8C_dct0_ADDRESS 0x8c + +// Type +#define D18F2x8C_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x8C_dct0_Reserved_15_0_OFFSET 0 +#define D18F2x8C_dct0_Reserved_15_0_WIDTH 16 +#define D18F2x8C_dct0_Reserved_15_0_MASK 0xffff +#define D18F2x8C_dct0_Tref_OFFSET 16 +#define D18F2x8C_dct0_Tref_WIDTH 2 +#define D18F2x8C_dct0_Tref_MASK 0x30000 +#define D18F2x8C_dct0_DisAutoRefresh_OFFSET 18 +#define D18F2x8C_dct0_DisAutoRefresh_WIDTH 1 +#define D18F2x8C_dct0_DisAutoRefresh_MASK 0x40000 +#define D18F2x8C_dct0_Reserved_31_19_OFFSET 19 +#define D18F2x8C_dct0_Reserved_31_19_WIDTH 13 +#define D18F2x8C_dct0_Reserved_31_19_MASK 0xfff80000 + +/// D18F2x8C_dct0 +typedef union { + struct { ///< + UINT32 Reserved_15_0:16; ///< + UINT32 Tref:2 ; ///< + UINT32 DisAutoRefresh:1 ; ///< + UINT32 Reserved_31_19:13; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x8C_dct0_STRUCT; + +// **** D18F2x90_dct0 Register Definition **** +// Address +#define D18F2x90_dct0_ADDRESS 0x90 + +// Type +#define D18F2x90_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x90_dct0_Reserved_0_0_OFFSET 0 +#define D18F2x90_dct0_Reserved_0_0_WIDTH 1 +#define D18F2x90_dct0_Reserved_0_0_MASK 0x1 +#define D18F2x90_dct0_ExitSelfRef_OFFSET 1 +#define D18F2x90_dct0_ExitSelfRef_WIDTH 1 +#define D18F2x90_dct0_ExitSelfRef_MASK 0x2 +#define D18F2x90_dct0_Reserved_7_2_OFFSET 2 +#define D18F2x90_dct0_Reserved_7_2_WIDTH 6 +#define D18F2x90_dct0_Reserved_7_2_MASK 0xfc +#define D18F2x90_dct0_Reserved_8_8_OFFSET 8 +#define D18F2x90_dct0_Reserved_8_8_WIDTH 1 +#define D18F2x90_dct0_Reserved_8_8_MASK 0x100 +#define D18F2x90_dct0_Reserved_11_9_OFFSET 9 +#define D18F2x90_dct0_Reserved_11_9_WIDTH 3 +#define D18F2x90_dct0_Reserved_11_9_MASK 0xe00 +#define D18F2x90_dct0_Reserved_15_12_OFFSET 12 +#define D18F2x90_dct0_Reserved_15_12_WIDTH 4 +#define D18F2x90_dct0_Reserved_15_12_MASK 0xf000 +#define D18F2x90_dct0_UnbuffDimm_OFFSET 16 +#define D18F2x90_dct0_UnbuffDimm_WIDTH 1 +#define D18F2x90_dct0_UnbuffDimm_MASK 0x10000 +#define D18F2x90_dct0_EnterSelfRef_OFFSET 17 +#define D18F2x90_dct0_EnterSelfRef_WIDTH 1 +#define D18F2x90_dct0_EnterSelfRef_MASK 0x20000 +#define D18F2x90_dct0_PendRefPayback_OFFSET 18 +#define D18F2x90_dct0_PendRefPayback_WIDTH 1 +#define D18F2x90_dct0_PendRefPayback_MASK 0x40000 +#define D18F2x90_dct0_Reserved_19_19_OFFSET 19 +#define D18F2x90_dct0_Reserved_19_19_WIDTH 1 +#define D18F2x90_dct0_Reserved_19_19_MASK 0x80000 +#define D18F2x90_dct0_DynPageCloseEn_OFFSET 20 +#define D18F2x90_dct0_DynPageCloseEn_WIDTH 1 +#define D18F2x90_dct0_DynPageCloseEn_MASK 0x100000 +#define D18F2x90_dct0_IdleCycLowLimit_OFFSET 21 +#define D18F2x90_dct0_IdleCycLowLimit_WIDTH 2 +#define D18F2x90_dct0_IdleCycLowLimit_MASK 0x600000 +#define D18F2x90_dct0_ForceAutoPchg_OFFSET 23 +#define D18F2x90_dct0_ForceAutoPchg_WIDTH 1 +#define D18F2x90_dct0_ForceAutoPchg_MASK 0x800000 +#define D18F2x90_dct0_StagRefEn_OFFSET 24 +#define D18F2x90_dct0_StagRefEn_WIDTH 1 +#define D18F2x90_dct0_StagRefEn_MASK 0x1000000 +#define D18F2x90_dct0_PendRefPaybackS3En_OFFSET 25 +#define D18F2x90_dct0_PendRefPaybackS3En_WIDTH 1 +#define D18F2x90_dct0_PendRefPaybackS3En_MASK 0x2000000 +#define D18F2x90_dct0_Reserved_26_26_OFFSET 26 +#define D18F2x90_dct0_Reserved_26_26_WIDTH 1 +#define D18F2x90_dct0_Reserved_26_26_MASK 0x4000000 +#define D18F2x90_dct0_DisDllShutdownSR_OFFSET 27 +#define D18F2x90_dct0_DisDllShutdownSR_WIDTH 1 +#define D18F2x90_dct0_DisDllShutdownSR_MASK 0x8000000 +#define D18F2x90_dct0_Reserved_31_28_OFFSET 28 +#define D18F2x90_dct0_Reserved_31_28_WIDTH 4 +#define D18F2x90_dct0_Reserved_31_28_MASK 0xf0000000 + +/// D18F2x90_dct0 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 ExitSelfRef:1 ; ///< + UINT32 Reserved_7_2:6 ; ///< + UINT32 Reserved_8_8:1 ; ///< + UINT32 Reserved_11_9:3 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 UnbuffDimm:1 ; ///< + UINT32 EnterSelfRef:1 ; ///< + UINT32 PendRefPayback:1 ; ///< + UINT32 Reserved_19_19:1 ; ///< + UINT32 DynPageCloseEn:1 ; ///< + UINT32 IdleCycLowLimit:2 ; ///< + UINT32 ForceAutoPchg:1 ; ///< + UINT32 StagRefEn:1 ; ///< + UINT32 PendRefPaybackS3En:1 ; ///< + UINT32 Reserved_26_26:1 ; ///< + UINT32 DisDllShutdownSR:1 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x90_dct0_STRUCT; + +// **** D18F2x90_dct1 Register Definition **** +// Address +#define D18F2x90_dct1_ADDRESS 0x90 + +// Type +#define D18F2x90_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x90_dct1_Reserved_0_0_OFFSET 0 +#define D18F2x90_dct1_Reserved_0_0_WIDTH 1 +#define D18F2x90_dct1_Reserved_0_0_MASK 0x1 +#define D18F2x90_dct1_ExitSelfRef_OFFSET 1 +#define D18F2x90_dct1_ExitSelfRef_WIDTH 1 +#define D18F2x90_dct1_ExitSelfRef_MASK 0x2 +#define D18F2x90_dct1_Reserved_7_2_OFFSET 2 +#define D18F2x90_dct1_Reserved_7_2_WIDTH 6 +#define D18F2x90_dct1_Reserved_7_2_MASK 0xfc +#define D18F2x90_dct1_Reserved_8_8_OFFSET 8 +#define D18F2x90_dct1_Reserved_8_8_WIDTH 1 +#define D18F2x90_dct1_Reserved_8_8_MASK 0x100 +#define D18F2x90_dct1_Reserved_11_9_OFFSET 9 +#define D18F2x90_dct1_Reserved_11_9_WIDTH 3 +#define D18F2x90_dct1_Reserved_11_9_MASK 0xe00 +#define D18F2x90_dct1_Reserved_15_12_OFFSET 12 +#define D18F2x90_dct1_Reserved_15_12_WIDTH 4 +#define D18F2x90_dct1_Reserved_15_12_MASK 0xf000 +#define D18F2x90_dct1_UnbuffDimm_OFFSET 16 +#define D18F2x90_dct1_UnbuffDimm_WIDTH 1 +#define D18F2x90_dct1_UnbuffDimm_MASK 0x10000 +#define D18F2x90_dct1_EnterSelfRef_OFFSET 17 +#define D18F2x90_dct1_EnterSelfRef_WIDTH 1 +#define D18F2x90_dct1_EnterSelfRef_MASK 0x20000 +#define D18F2x90_dct1_PendRefPayback_OFFSET 18 +#define D18F2x90_dct1_PendRefPayback_WIDTH 1 +#define D18F2x90_dct1_PendRefPayback_MASK 0x40000 +#define D18F2x90_dct1_Reserved_19_19_OFFSET 19 +#define D18F2x90_dct1_Reserved_19_19_WIDTH 1 +#define D18F2x90_dct1_Reserved_19_19_MASK 0x80000 +#define D18F2x90_dct1_DynPageCloseEn_OFFSET 20 +#define D18F2x90_dct1_DynPageCloseEn_WIDTH 1 +#define D18F2x90_dct1_DynPageCloseEn_MASK 0x100000 +#define D18F2x90_dct1_IdleCycLowLimit_OFFSET 21 +#define D18F2x90_dct1_IdleCycLowLimit_WIDTH 2 +#define D18F2x90_dct1_IdleCycLowLimit_MASK 0x600000 +#define D18F2x90_dct1_ForceAutoPchg_OFFSET 23 +#define D18F2x90_dct1_ForceAutoPchg_WIDTH 1 +#define D18F2x90_dct1_ForceAutoPchg_MASK 0x800000 +#define D18F2x90_dct1_StagRefEn_OFFSET 24 +#define D18F2x90_dct1_StagRefEn_WIDTH 1 +#define D18F2x90_dct1_StagRefEn_MASK 0x1000000 +#define D18F2x90_dct1_PendRefPaybackS3En_OFFSET 25 +#define D18F2x90_dct1_PendRefPaybackS3En_WIDTH 1 +#define D18F2x90_dct1_PendRefPaybackS3En_MASK 0x2000000 +#define D18F2x90_dct1_Reserved_26_26_OFFSET 26 +#define D18F2x90_dct1_Reserved_26_26_WIDTH 1 +#define D18F2x90_dct1_Reserved_26_26_MASK 0x4000000 +#define D18F2x90_dct1_DisDllShutdownSR_OFFSET 27 +#define D18F2x90_dct1_DisDllShutdownSR_WIDTH 1 +#define D18F2x90_dct1_DisDllShutdownSR_MASK 0x8000000 +#define D18F2x90_dct1_Reserved_31_28_OFFSET 28 +#define D18F2x90_dct1_Reserved_31_28_WIDTH 4 +#define D18F2x90_dct1_Reserved_31_28_MASK 0xf0000000 + +/// D18F2x90_dct1 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 ExitSelfRef:1 ; ///< + UINT32 Reserved_7_2:6 ; ///< + UINT32 Reserved_8_8:1 ; ///< + UINT32 Reserved_11_9:3 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 UnbuffDimm:1 ; ///< + UINT32 EnterSelfRef:1 ; ///< + UINT32 PendRefPayback:1 ; ///< + UINT32 Reserved_19_19:1 ; ///< + UINT32 DynPageCloseEn:1 ; ///< + UINT32 IdleCycLowLimit:2 ; ///< + UINT32 ForceAutoPchg:1 ; ///< + UINT32 StagRefEn:1 ; ///< + UINT32 PendRefPaybackS3En:1 ; ///< + UINT32 Reserved_26_26:1 ; ///< + UINT32 DisDllShutdownSR:1 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x90_dct1_STRUCT; + +// **** D18F2x94_dct1 Register Definition **** +// Address +#define D18F2x94_dct1_ADDRESS 0x94 + +// Type +#define D18F2x94_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x94_dct1_MemClkFreq_OFFSET 0 +#define D18F2x94_dct1_MemClkFreq_WIDTH 5 +#define D18F2x94_dct1_MemClkFreq_MASK 0x1f +#define D18F2x94_dct1_Reserved_6_5_OFFSET 5 +#define D18F2x94_dct1_Reserved_6_5_WIDTH 2 +#define D18F2x94_dct1_Reserved_6_5_MASK 0x60 +#define D18F2x94_dct1_MemClkFreqVal_OFFSET 7 +#define D18F2x94_dct1_MemClkFreqVal_WIDTH 1 +#define D18F2x94_dct1_MemClkFreqVal_MASK 0x80 +#define D18F2x94_dct1_Reserved_9_8_OFFSET 8 +#define D18F2x94_dct1_Reserved_9_8_WIDTH 2 +#define D18F2x94_dct1_Reserved_9_8_MASK 0x300 +#define D18F2x94_dct1_ZqcsInterval_OFFSET 10 +#define D18F2x94_dct1_ZqcsInterval_WIDTH 2 +#define D18F2x94_dct1_ZqcsInterval_MASK 0xc00 +#define D18F2x94_dct1_Reserved_12_12_OFFSET 12 +#define D18F2x94_dct1_Reserved_12_12_WIDTH 1 +#define D18F2x94_dct1_Reserved_12_12_MASK 0x1000 +#define D18F2x94_dct1_Reserved_13_13_OFFSET 13 +#define D18F2x94_dct1_Reserved_13_13_WIDTH 1 +#define D18F2x94_dct1_Reserved_13_13_MASK 0x2000 +#define D18F2x94_dct1_DisDramInterface_OFFSET 14 +#define D18F2x94_dct1_DisDramInterface_WIDTH 1 +#define D18F2x94_dct1_DisDramInterface_MASK 0x4000 +#define D18F2x94_dct1_PowerDownEn_OFFSET 15 +#define D18F2x94_dct1_PowerDownEn_WIDTH 1 +#define D18F2x94_dct1_PowerDownEn_MASK 0x8000 +#define D18F2x94_dct1_PowerDownMode_OFFSET 16 +#define D18F2x94_dct1_PowerDownMode_WIDTH 1 +#define D18F2x94_dct1_PowerDownMode_MASK 0x10000 +#define D18F2x94_dct1_Reserved_18_17_OFFSET 17 +#define D18F2x94_dct1_Reserved_18_17_WIDTH 2 +#define D18F2x94_dct1_Reserved_18_17_MASK 0x60000 +#define D18F2x94_dct1_SlowAccessMode_OFFSET 20 +#define D18F2x94_dct1_SlowAccessMode_WIDTH 1 +#define D18F2x94_dct1_SlowAccessMode_MASK 0x100000 +#define D18F2x94_dct1_FreqChgInProg_OFFSET 21 +#define D18F2x94_dct1_FreqChgInProg_WIDTH 1 +#define D18F2x94_dct1_FreqChgInProg_MASK 0x200000 +#define D18F2x94_dct1_BankSwizzleMode_OFFSET 22 +#define D18F2x94_dct1_BankSwizzleMode_WIDTH 1 +#define D18F2x94_dct1_BankSwizzleMode_MASK 0x400000 +#define D18F2x94_dct1_ProcOdtDis_OFFSET 23 +#define D18F2x94_dct1_ProcOdtDis_WIDTH 1 +#define D18F2x94_dct1_ProcOdtDis_MASK 0x800000 +#define D18F2x94_dct1_DcqBypassMax_OFFSET 24 +#define D18F2x94_dct1_DcqBypassMax_WIDTH 5 +#define D18F2x94_dct1_DcqBypassMax_MASK 0x1f000000 +#define D18F2x94_dct1_Reserved_30_29_OFFSET 29 +#define D18F2x94_dct1_Reserved_30_29_WIDTH 2 +#define D18F2x94_dct1_Reserved_30_29_MASK 0x60000000 +#define D18F2x94_dct1_DphyMemPsSelEn_OFFSET 31 +#define D18F2x94_dct1_DphyMemPsSelEn_WIDTH 1 +#define D18F2x94_dct1_DphyMemPsSelEn_MASK 0x80000000 + +/// D18F2x94_dct1 +typedef union { + struct { ///< + UINT32 MemClkFreq:5 ; ///< + UINT32 Reserved_6_5:2 ; ///< + UINT32 MemClkFreqVal:1 ; ///< + UINT32 Reserved_9_8:2 ; ///< + UINT32 ZqcsInterval:2 ; ///< + UINT32 Reserved_12_12:1 ; ///< + UINT32 Reserved_13_13:1 ; ///< + UINT32 DisDramInterface:1 ; ///< + UINT32 PowerDownEn:1 ; ///< + UINT32 PowerDownMode:1 ; ///< + UINT32 Reserved_18_17:2 ; ///< + UINT32 DcqArbBypassEn:1 ; ///< + UINT32 SlowAccessMode:1 ; ///< + UINT32 FreqChgInProg:1 ; ///< + UINT32 BankSwizzleMode:1 ; ///< + UINT32 ProcOdtDis:1 ; ///< + UINT32 DcqBypassMax:5 ; ///< + UINT32 Reserved_30_29:2 ; ///< + UINT32 DphyMemPsSelEn:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x94_dct1_STRUCT; + +// **** D18F2x94_dct0 Register Definition **** +// Address +#define D18F2x94_dct0_ADDRESS 0x94 + +// Type +#define D18F2x94_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x94_dct0_MemClkFreq_OFFSET 0 +#define D18F2x94_dct0_MemClkFreq_WIDTH 5 +#define D18F2x94_dct0_MemClkFreq_MASK 0x1f +#define D18F2x94_dct0_Reserved_6_5_OFFSET 5 +#define D18F2x94_dct0_Reserved_6_5_WIDTH 2 +#define D18F2x94_dct0_Reserved_6_5_MASK 0x60 +#define D18F2x94_dct0_MemClkFreqVal_OFFSET 7 +#define D18F2x94_dct0_MemClkFreqVal_WIDTH 1 +#define D18F2x94_dct0_MemClkFreqVal_MASK 0x80 +#define D18F2x94_dct0_Reserved_9_8_OFFSET 8 +#define D18F2x94_dct0_Reserved_9_8_WIDTH 2 +#define D18F2x94_dct0_Reserved_9_8_MASK 0x300 +#define D18F2x94_dct0_ZqcsInterval_OFFSET 10 +#define D18F2x94_dct0_ZqcsInterval_WIDTH 2 +#define D18F2x94_dct0_ZqcsInterval_MASK 0xc00 +#define D18F2x94_dct0_Reserved_12_12_OFFSET 12 +#define D18F2x94_dct0_Reserved_12_12_WIDTH 1 +#define D18F2x94_dct0_Reserved_12_12_MASK 0x1000 +#define D18F2x94_dct0_Reserved_13_13_OFFSET 13 +#define D18F2x94_dct0_Reserved_13_13_WIDTH 1 +#define D18F2x94_dct0_Reserved_13_13_MASK 0x2000 +#define D18F2x94_dct0_DisDramInterface_OFFSET 14 +#define D18F2x94_dct0_DisDramInterface_WIDTH 1 +#define D18F2x94_dct0_DisDramInterface_MASK 0x4000 +#define D18F2x94_dct0_PowerDownEn_OFFSET 15 +#define D18F2x94_dct0_PowerDownEn_WIDTH 1 +#define D18F2x94_dct0_PowerDownEn_MASK 0x8000 +#define D18F2x94_dct0_PowerDownMode_OFFSET 16 +#define D18F2x94_dct0_PowerDownMode_WIDTH 1 +#define D18F2x94_dct0_PowerDownMode_MASK 0x10000 +#define D18F2x94_dct0_Reserved_18_17_OFFSET 17 +#define D18F2x94_dct0_Reserved_18_17_WIDTH 2 +#define D18F2x94_dct0_Reserved_18_17_MASK 0x60000 +#define D18F2x94_dct0_SlowAccessMode_OFFSET 20 +#define D18F2x94_dct0_SlowAccessMode_WIDTH 1 +#define D18F2x94_dct0_SlowAccessMode_MASK 0x100000 +#define D18F2x94_dct0_FreqChgInProg_OFFSET 21 +#define D18F2x94_dct0_FreqChgInProg_WIDTH 1 +#define D18F2x94_dct0_FreqChgInProg_MASK 0x200000 +#define D18F2x94_dct0_BankSwizzleMode_OFFSET 22 +#define D18F2x94_dct0_BankSwizzleMode_WIDTH 1 +#define D18F2x94_dct0_BankSwizzleMode_MASK 0x400000 +#define D18F2x94_dct0_ProcOdtDis_OFFSET 23 +#define D18F2x94_dct0_ProcOdtDis_WIDTH 1 +#define D18F2x94_dct0_ProcOdtDis_MASK 0x800000 +#define D18F2x94_dct0_DcqBypassMax_OFFSET 24 +#define D18F2x94_dct0_DcqBypassMax_WIDTH 5 +#define D18F2x94_dct0_DcqBypassMax_MASK 0x1f000000 +#define D18F2x94_dct0_Reserved_30_29_OFFSET 29 +#define D18F2x94_dct0_Reserved_30_29_WIDTH 2 +#define D18F2x94_dct0_Reserved_30_29_MASK 0x60000000 +#define D18F2x94_dct0_DphyMemPsSelEn_OFFSET 31 +#define D18F2x94_dct0_DphyMemPsSelEn_WIDTH 1 +#define D18F2x94_dct0_DphyMemPsSelEn_MASK 0x80000000 + +/// D18F2x94_dct0 +typedef union { + struct { ///< + UINT32 MemClkFreq:5 ; ///< + UINT32 Reserved_6_5:2 ; ///< + UINT32 MemClkFreqVal:1 ; ///< + UINT32 Reserved_9_8:2 ; ///< + UINT32 ZqcsInterval:2 ; ///< + UINT32 Reserved_12_12:1 ; ///< + UINT32 Reserved_13_13:1 ; ///< + UINT32 DisDramInterface:1 ; ///< + UINT32 PowerDownEn:1 ; ///< + UINT32 PowerDownMode:1 ; ///< + UINT32 Reserved_18_17:2 ; ///< + UINT32 DcqArbBypassEn:1 ; ///< + UINT32 SlowAccessMode:1 ; ///< + UINT32 FreqChgInProg:1 ; ///< + UINT32 BankSwizzleMode:1 ; ///< + UINT32 ProcOdtDis:1 ; ///< + UINT32 DcqBypassMax:5 ; ///< + UINT32 Reserved_30_29:2 ; ///< + UINT32 DphyMemPsSelEn:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x94_dct0_STRUCT; + +// **** D18F2x98_dct0 Register Definition **** +// Address +#define D18F2x98_dct0_ADDRESS 0x98 + +// Type +#define D18F2x98_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x98_dct0_DctOffset_OFFSET 0 +#define D18F2x98_dct0_DctOffset_WIDTH 30 +#define D18F2x98_dct0_DctOffset_MASK 0x3fffffff +#define D18F2x98_dct0_DctAccessWrite_OFFSET 30 +#define D18F2x98_dct0_DctAccessWrite_WIDTH 1 +#define D18F2x98_dct0_DctAccessWrite_MASK 0x40000000 +#define D18F2x98_dct0_Reserved_31_31_OFFSET 31 +#define D18F2x98_dct0_Reserved_31_31_WIDTH 1 +#define D18F2x98_dct0_Reserved_31_31_MASK 0x80000000 + +/// D18F2x98_dct0 +typedef union { + struct { ///< + UINT32 DctOffset:30; ///< + UINT32 DctAccessWrite:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x98_dct0_STRUCT; + +// **** D18F2x98_dct1 Register Definition **** +// Address +#define D18F2x98_dct1_ADDRESS 0x98 + +// Type +#define D18F2x98_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x98_dct1_DctOffset_OFFSET 0 +#define D18F2x98_dct1_DctOffset_WIDTH 30 +#define D18F2x98_dct1_DctOffset_MASK 0x3fffffff +#define D18F2x98_dct1_DctAccessWrite_OFFSET 30 +#define D18F2x98_dct1_DctAccessWrite_WIDTH 1 +#define D18F2x98_dct1_DctAccessWrite_MASK 0x40000000 +#define D18F2x98_dct1_Reserved_31_31_OFFSET 31 +#define D18F2x98_dct1_Reserved_31_31_WIDTH 1 +#define D18F2x98_dct1_Reserved_31_31_MASK 0x80000000 + +/// D18F2x98_dct1 +typedef union { + struct { ///< + UINT32 DctOffset:30; ///< + UINT32 DctAccessWrite:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x98_dct1_STRUCT; + +// **** D18F2x9C_dct1 Register Definition **** +// Address +#define D18F2x9C_dct1_ADDRESS 0x9c + +// Type +#define D18F2x9C_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x9C_dct1_Data_OFFSET 0 +#define D18F2x9C_dct1_Data_WIDTH 32 +#define D18F2x9C_dct1_Data_MASK 0xffffffff + +/// D18F2x9C_dct1 +typedef union { + struct { ///< + UINT32 Data:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_dct1_STRUCT; + +// **** D18F2x9C_dct0 Register Definition **** +// Address +#define D18F2x9C_dct0_ADDRESS 0x9c + +// Type +#define D18F2x9C_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x9C_dct0_Data_OFFSET 0 +#define D18F2x9C_dct0_Data_WIDTH 32 +#define D18F2x9C_dct0_Data_MASK 0xffffffff + +/// D18F2x9C_dct0 +typedef union { + struct { ///< + UINT32 Data:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_dct0_STRUCT; + +// **** D18F2xA4 Register Definition **** +// Address +#define D18F2xA4_ADDRESS 0xa4 + +// Type +#define D18F2xA4_TYPE TYPE_D18F2 +// Field Data +#define D18F2xA4_Reserved_7_0_OFFSET 0 +#define D18F2xA4_Reserved_7_0_WIDTH 8 +#define D18F2xA4_Reserved_7_0_MASK 0xff +#define D18F2xA4_ODTSEn_OFFSET 8 +#define D18F2xA4_ODTSEn_WIDTH 1 +#define D18F2xA4_ODTSEn_MASK 0x100 +#define D18F2xA4_Reserved_10_9_OFFSET 9 +#define D18F2xA4_Reserved_10_9_WIDTH 2 +#define D18F2xA4_Reserved_10_9_MASK 0x600 +#define D18F2xA4_BwCapEn_OFFSET 11 +#define D18F2xA4_BwCapEn_WIDTH 1 +#define D18F2xA4_BwCapEn_MASK 0x800 +#define D18F2xA4_CmdThrottleMode_OFFSET 12 +#define D18F2xA4_CmdThrottleMode_WIDTH 3 +#define D18F2xA4_CmdThrottleMode_MASK 0x7000 +#define D18F2xA4_Reserved_19_15_OFFSET 15 +#define D18F2xA4_Reserved_19_15_WIDTH 5 +#define D18F2xA4_Reserved_19_15_MASK 0xf8000 +#define D18F2xA4_BwCapCmdThrottleMode_OFFSET 20 +#define D18F2xA4_BwCapCmdThrottleMode_WIDTH 4 +#define D18F2xA4_BwCapCmdThrottleMode_MASK 0xf00000 +#define D18F2xA4_Reserved_31_24_OFFSET 24 +#define D18F2xA4_Reserved_31_24_WIDTH 8 +#define D18F2xA4_Reserved_31_24_MASK 0xff000000 + +/// D18F2xA4 +typedef union { + struct { ///< + UINT32 Reserved_7_0:8 ; ///< + UINT32 ODTSEn:1 ; ///< + UINT32 Reserved_10_9:2 ; ///< + UINT32 BwCapEn:1 ; ///< + UINT32 CmdThrottleMode:3 ; ///< + UINT32 Reserved_19_15:5 ; ///< + UINT32 BwCapCmdThrottleMode:4 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xA4_STRUCT; + +// **** D18F2xA8_dct0 Register Definition **** +// Address +#define D18F2xA8_dct0_ADDRESS 0xa8 + +// Type +#define D18F2xA8_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2xA8_dct0_Reserved_1_0_OFFSET 0 +#define D18F2xA8_dct0_Reserved_1_0_WIDTH 2 +#define D18F2xA8_dct0_Reserved_1_0_MASK 0x3 +#define D18F2xA8_dct0_CSTimingMux67_OFFSET 2 +#define D18F2xA8_dct0_CSTimingMux67_WIDTH 1 +#define D18F2xA8_dct0_CSTimingMux67_MASK 0x4 +#define D18F2xA8_dct0_Reserved_3_3_OFFSET 3 +#define D18F2xA8_dct0_Reserved_3_3_WIDTH 1 +#define D18F2xA8_dct0_Reserved_3_3_MASK 0x8 +#define D18F2xA8_dct0_Reserved_4_4_OFFSET 4 +#define D18F2xA8_dct0_Reserved_4_4_WIDTH 1 +#define D18F2xA8_dct0_Reserved_4_4_MASK 0x10 +#define D18F2xA8_dct0_SubMemclkRegDly_OFFSET 5 +#define D18F2xA8_dct0_SubMemclkRegDly_WIDTH 1 +#define D18F2xA8_dct0_SubMemclkRegDly_MASK 0x20 +#define D18F2xA8_dct0_Reserved_7_6_OFFSET 6 +#define D18F2xA8_dct0_Reserved_7_6_WIDTH 2 +#define D18F2xA8_dct0_Reserved_7_6_MASK 0xc0 +#define D18F2xA8_dct0_CtrlWordCS_7_0__OFFSET 8 +#define D18F2xA8_dct0_CtrlWordCS_7_0__WIDTH 8 +#define D18F2xA8_dct0_CtrlWordCS_7_0__MASK 0xff00 +#define D18F2xA8_dct0_MemPhyPllPdMode_OFFSET 16 +#define D18F2xA8_dct0_MemPhyPllPdMode_WIDTH 2 +#define D18F2xA8_dct0_MemPhyPllPdMode_MASK 0x30000 +#define D18F2xA8_dct0_Reserved_19_18_OFFSET 18 +#define D18F2xA8_dct0_Reserved_19_18_WIDTH 2 +#define D18F2xA8_dct0_Reserved_19_18_MASK 0xc0000 +#define D18F2xA8_dct0_BankSwap_OFFSET 20 +#define D18F2xA8_dct0_BankSwap_WIDTH 1 +#define D18F2xA8_dct0_BankSwap_MASK 0x100000 +#define D18F2xA8_dct0_AggrPDEn_OFFSET 21 +#define D18F2xA8_dct0_AggrPDEn_WIDTH 1 +#define D18F2xA8_dct0_AggrPDEn_MASK 0x200000 +#define D18F2xA8_dct0_PrtlChPDEnhEn_OFFSET 22 +#define D18F2xA8_dct0_PrtlChPDEnhEn_WIDTH 1 +#define D18F2xA8_dct0_PrtlChPDEnhEn_MASK 0x400000 +#define D18F2xA8_dct0_Reserved_23_23_OFFSET 23 +#define D18F2xA8_dct0_Reserved_23_23_WIDTH 1 +#define D18F2xA8_dct0_Reserved_23_23_MASK 0x800000 +#define D18F2xA8_dct0_Reserved_25_24_OFFSET 24 +#define D18F2xA8_dct0_Reserved_25_24_WIDTH 2 +#define D18F2xA8_dct0_Reserved_25_24_MASK 0x3000000 +#define D18F2xA8_dct0_CsMux45_OFFSET 26 +#define D18F2xA8_dct0_CsMux45_WIDTH 1 +#define D18F2xA8_dct0_CsMux45_MASK 0x4000000 +#define D18F2xA8_dct0_CsMux67_OFFSET 27 +#define D18F2xA8_dct0_CsMux67_WIDTH 1 +#define D18F2xA8_dct0_CsMux67_MASK 0x8000000 +#define D18F2xA8_dct0_FastSelfRefEntryDis_OFFSET 28 +#define D18F2xA8_dct0_FastSelfRefEntryDis_WIDTH 1 +#define D18F2xA8_dct0_FastSelfRefEntryDis_MASK 0x10000000 +#define D18F2xA8_dct0_RefChCmdMgtDis_OFFSET 29 +#define D18F2xA8_dct0_RefChCmdMgtDis_WIDTH 1 +#define D18F2xA8_dct0_RefChCmdMgtDis_MASK 0x20000000 +#define D18F2xA8_dct0_Reserved_30_30_OFFSET 30 +#define D18F2xA8_dct0_Reserved_30_30_WIDTH 1 +#define D18F2xA8_dct0_Reserved_30_30_MASK 0x40000000 +#define D18F2xA8_dct0_PerRankTimingEn_OFFSET 31 +#define D18F2xA8_dct0_PerRankTimingEn_WIDTH 1 +#define D18F2xA8_dct0_PerRankTimingEn_MASK 0x80000000 + +/// D18F2xA8_dct0 +typedef union { + struct { ///< + UINT32 Reserved_1_0:2 ; ///< + UINT32 CSTimingMux67:1 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 SubMemclkRegDly:1 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 CtrlWordCS_7_0_:8 ; ///< + UINT32 MemPhyPllPdMode:2 ; ///< + UINT32 Reserved_19_18:2 ; ///< + UINT32 BankSwap:1 ; ///< + UINT32 AggrPDEn:1 ; ///< + UINT32 PrtlChPDEnhEn:1 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 Reserved_25_24:2 ; ///< + UINT32 CsMux45:1 ; ///< + UINT32 CsMux67:1 ; ///< + UINT32 FastSelfRefEntryDis:1 ; ///< + UINT32 RefChCmdMgtDis:1 ; ///< + UINT32 Reserved_30_30:1 ; ///< + UINT32 PerRankTimingEn:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xA8_dct0_STRUCT; + +// **** D18F2xA8_dct1 Register Definition **** +// Address +#define D18F2xA8_dct1_ADDRESS 0xa8 + +// Type +#define D18F2xA8_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2xA8_dct1_Reserved_1_0_OFFSET 0 +#define D18F2xA8_dct1_Reserved_1_0_WIDTH 2 +#define D18F2xA8_dct1_Reserved_1_0_MASK 0x3 +#define D18F2xA8_dct1_CSTimingMux67_OFFSET 2 +#define D18F2xA8_dct1_CSTimingMux67_WIDTH 1 +#define D18F2xA8_dct1_CSTimingMux67_MASK 0x4 +#define D18F2xA8_dct1_Reserved_3_3_OFFSET 3 +#define D18F2xA8_dct1_Reserved_3_3_WIDTH 1 +#define D18F2xA8_dct1_Reserved_3_3_MASK 0x8 +#define D18F2xA8_dct1_Reserved_4_4_OFFSET 4 +#define D18F2xA8_dct1_Reserved_4_4_WIDTH 1 +#define D18F2xA8_dct1_Reserved_4_4_MASK 0x10 +#define D18F2xA8_dct1_SubMemclkRegDly_OFFSET 5 +#define D18F2xA8_dct1_SubMemclkRegDly_WIDTH 1 +#define D18F2xA8_dct1_SubMemclkRegDly_MASK 0x20 +#define D18F2xA8_dct1_Reserved_7_6_OFFSET 6 +#define D18F2xA8_dct1_Reserved_7_6_WIDTH 2 +#define D18F2xA8_dct1_Reserved_7_6_MASK 0xc0 +#define D18F2xA8_dct1_CtrlWordCS_7_0__OFFSET 8 +#define D18F2xA8_dct1_CtrlWordCS_7_0__WIDTH 8 +#define D18F2xA8_dct1_CtrlWordCS_7_0__MASK 0xff00 +#define D18F2xA8_dct1_MemPhyPllPdMode_OFFSET 16 +#define D18F2xA8_dct1_MemPhyPllPdMode_WIDTH 2 +#define D18F2xA8_dct1_MemPhyPllPdMode_MASK 0x30000 +#define D18F2xA8_dct1_Reserved_19_18_OFFSET 18 +#define D18F2xA8_dct1_Reserved_19_18_WIDTH 2 +#define D18F2xA8_dct1_Reserved_19_18_MASK 0xc0000 +#define D18F2xA8_dct1_BankSwap_OFFSET 20 +#define D18F2xA8_dct1_BankSwap_WIDTH 1 +#define D18F2xA8_dct1_BankSwap_MASK 0x100000 +#define D18F2xA8_dct1_AggrPDEn_OFFSET 21 +#define D18F2xA8_dct1_AggrPDEn_WIDTH 1 +#define D18F2xA8_dct1_AggrPDEn_MASK 0x200000 +#define D18F2xA8_dct1_PrtlChPDEnhEn_OFFSET 22 +#define D18F2xA8_dct1_PrtlChPDEnhEn_WIDTH 1 +#define D18F2xA8_dct1_PrtlChPDEnhEn_MASK 0x400000 +#define D18F2xA8_dct1_Reserved_23_23_OFFSET 23 +#define D18F2xA8_dct1_Reserved_23_23_WIDTH 1 +#define D18F2xA8_dct1_Reserved_23_23_MASK 0x800000 +#define D18F2xA8_dct1_Reserved_25_24_OFFSET 24 +#define D18F2xA8_dct1_Reserved_25_24_WIDTH 2 +#define D18F2xA8_dct1_Reserved_25_24_MASK 0x3000000 +#define D18F2xA8_dct1_CsMux45_OFFSET 26 +#define D18F2xA8_dct1_CsMux45_WIDTH 1 +#define D18F2xA8_dct1_CsMux45_MASK 0x4000000 +#define D18F2xA8_dct1_CsMux67_OFFSET 27 +#define D18F2xA8_dct1_CsMux67_WIDTH 1 +#define D18F2xA8_dct1_CsMux67_MASK 0x8000000 +#define D18F2xA8_dct1_FastSelfRefEntryDis_OFFSET 28 +#define D18F2xA8_dct1_FastSelfRefEntryDis_WIDTH 1 +#define D18F2xA8_dct1_FastSelfRefEntryDis_MASK 0x10000000 +#define D18F2xA8_dct1_RefChCmdMgtDis_OFFSET 29 +#define D18F2xA8_dct1_RefChCmdMgtDis_WIDTH 1 +#define D18F2xA8_dct1_RefChCmdMgtDis_MASK 0x20000000 +#define D18F2xA8_dct1_Reserved_30_30_OFFSET 30 +#define D18F2xA8_dct1_Reserved_30_30_WIDTH 1 +#define D18F2xA8_dct1_Reserved_30_30_MASK 0x40000000 +#define D18F2xA8_dct1_PerRankTimingEn_OFFSET 31 +#define D18F2xA8_dct1_PerRankTimingEn_WIDTH 1 +#define D18F2xA8_dct1_PerRankTimingEn_MASK 0x80000000 + +/// D18F2xA8_dct1 +typedef union { + struct { ///< + UINT32 Reserved_1_0:2 ; ///< + UINT32 CSTimingMux67:1 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 SubMemclkRegDly:1 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 CtrlWordCS_7_0_:8 ; ///< + UINT32 MemPhyPllPdMode:2 ; ///< + UINT32 Reserved_19_18:2 ; ///< + UINT32 BankSwap:1 ; ///< + UINT32 AggrPDEn:1 ; ///< + UINT32 PrtlChPDEnhEn:1 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 Reserved_25_24:2 ; ///< + UINT32 CsMux45:1 ; ///< + UINT32 CsMux67:1 ; ///< + UINT32 FastSelfRefEntryDis:1 ; ///< + UINT32 RefChCmdMgtDis:1 ; ///< + UINT32 Reserved_30_30:1 ; ///< + UINT32 PerRankTimingEn:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xA8_dct1_STRUCT; + +// **** D18F2xAC Register Definition **** +// Address +#define D18F2xAC_ADDRESS 0xac + +// Type +#define D18F2xAC_TYPE TYPE_D18F2 +// Field Data +#define D18F2xAC_MemTempHot0_OFFSET 0 +#define D18F2xAC_MemTempHot0_WIDTH 1 +#define D18F2xAC_MemTempHot0_MASK 0x1 +#define D18F2xAC_Reserved_1_1_OFFSET 1 +#define D18F2xAC_Reserved_1_1_WIDTH 1 +#define D18F2xAC_Reserved_1_1_MASK 0x2 +#define D18F2xAC_MemTempHot1_OFFSET 2 +#define D18F2xAC_MemTempHot1_WIDTH 1 +#define D18F2xAC_MemTempHot1_MASK 0x4 +#define D18F2xAC_Reserved_31_3_OFFSET 3 +#define D18F2xAC_Reserved_31_3_WIDTH 29 +#define D18F2xAC_Reserved_31_3_MASK 0xfffffff8 + +/// D18F2xAC +typedef union { + struct { ///< + UINT32 MemTempHot0:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 MemTempHot1:1 ; ///< + UINT32 Reserved_31_3:29; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xAC_STRUCT; + + + +// **** D18F2xC4 Register Definition **** +// Address + + + + + + + + + + + +// **** D18F2xF8 Register Definition **** +// Address +#define D18F2xF8_ADDRESS 0xf8 + +// Type +#define D18F2xF8_TYPE TYPE_D18F2 +// Field Data +#define D18F2xF8_PwrValue0_OFFSET 0 +#define D18F2xF8_PwrValue0_WIDTH 8 +#define D18F2xF8_PwrValue0_MASK 0xff +#define D18F2xF8_PwrValue1_OFFSET 8 +#define D18F2xF8_PwrValue1_WIDTH 8 +#define D18F2xF8_PwrValue1_MASK 0xff00 +#define D18F2xF8_PwrValue2_OFFSET 16 +#define D18F2xF8_PwrValue2_WIDTH 8 +#define D18F2xF8_PwrValue2_MASK 0xff0000 +#define D18F2xF8_PwrValue3_OFFSET 24 +#define D18F2xF8_PwrValue3_WIDTH 8 +#define D18F2xF8_PwrValue3_MASK 0xff000000 + +/// D18F2xF8 +typedef union { + struct { ///< + UINT32 PwrValue0:8 ; ///< + UINT32 PwrValue1:8 ; ///< + UINT32 PwrValue2:8 ; ///< + UINT32 PwrValue3:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xF8_STRUCT; + + +// **** D18F2x104 Register Definition **** +// Address +#define D18F2x104_ADDRESS 0x104 + +// Type +#define D18F2x104_TYPE TYPE_D18F2 +// Field Data +#define D18F2x104_PwrValue5_OFFSET 0 +#define D18F2x104_PwrValue5_WIDTH 8 +#define D18F2x104_PwrValue5_MASK 0xff +#define D18F2x104_PwrValue6_OFFSET 8 +#define D18F2x104_PwrValue6_WIDTH 8 +#define D18F2x104_PwrValue6_MASK 0xff00 +#define D18F2x104_PwrValue7_OFFSET 16 +#define D18F2x104_PwrValue7_WIDTH 8 +#define D18F2x104_PwrValue7_MASK 0xff0000 +#define D18F2x104_Reserved_31_24_OFFSET 24 +#define D18F2x104_Reserved_31_24_WIDTH 8 +#define D18F2x104_Reserved_31_24_MASK 0xff000000 + +/// D18F2x104 +typedef union { + struct { ///< + UINT32 PwrValue5:8 ; ///< + UINT32 PwrValue6:8 ; ///< + UINT32 PwrValue7:8 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x104_STRUCT; + +// **** D18F2x10C Register Definition **** +// Address +#define D18F2x10C_ADDRESS 0x10c + +// Type +#define D18F2x10C_TYPE TYPE_D18F2 +// Field Data +#define D18F2x10C_IntLvRgnSwapEn_OFFSET 0 +#define D18F2x10C_IntLvRgnSwapEn_WIDTH 1 +#define D18F2x10C_IntLvRgnSwapEn_MASK 0x1 +#define D18F2x10C_Reserved_2_1_OFFSET 1 +#define D18F2x10C_Reserved_2_1_WIDTH 2 +#define D18F2x10C_Reserved_2_1_MASK 0x6 +#define D18F2x10C_IntLvRgnBaseAddr_33_27__OFFSET 3 +#define D18F2x10C_IntLvRgnBaseAddr_33_27__WIDTH 7 +#define D18F2x10C_IntLvRgnBaseAddr_33_27__MASK 0x3f8 +#define D18F2x10C_Reserved_10_10_OFFSET 10 +#define D18F2x10C_Reserved_10_10_WIDTH 1 +#define D18F2x10C_Reserved_10_10_MASK 0x400 +#define D18F2x10C_IntLvRgnLmtAddr_33_27__OFFSET 11 +#define D18F2x10C_IntLvRgnLmtAddr_33_27__WIDTH 7 +#define D18F2x10C_IntLvRgnLmtAddr_33_27__MASK 0x3f800 +#define D18F2x10C_Reserved_19_18_OFFSET 18 +#define D18F2x10C_Reserved_19_18_WIDTH 2 +#define D18F2x10C_Reserved_19_18_MASK 0xc0000 +#define D18F2x10C_IntLvRgnSize_33_27__OFFSET 20 +#define D18F2x10C_IntLvRgnSize_33_27__WIDTH 7 +#define D18F2x10C_IntLvRgnSize_33_27__MASK 0x7f00000 +#define D18F2x10C_Reserved_31_27_OFFSET 27 +#define D18F2x10C_Reserved_31_27_WIDTH 5 +#define D18F2x10C_Reserved_31_27_MASK 0xf8000000 + +/// D18F2x10C +typedef union { + struct { ///< + UINT32 IntLvRgnSwapEn:1 ; ///< + UINT32 Reserved_2_1:2 ; ///< + UINT32 IntLvRgnBaseAddr_33_27_:7 ; ///< + UINT32 Reserved_10_10:1 ; ///< + UINT32 IntLvRgnLmtAddr_33_27_:7 ; ///< + UINT32 Reserved_19_18:2 ; ///< + UINT32 IntLvRgnSize_33_27_:7 ; ///< + UINT32 Reserved_31_27:5 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x10C_STRUCT; + +// **** D18F2x110 Register Definition **** +// Address +#define D18F2x110_ADDRESS 0x110 + +// Type +#define D18F2x110_TYPE TYPE_D18F2 +// Field Data +#define D18F2x110_DctSelHiRngEn_OFFSET 0 +#define D18F2x110_DctSelHiRngEn_WIDTH 1 +#define D18F2x110_DctSelHiRngEn_MASK 0x1 +#define D18F2x110_DctSelHi_OFFSET 1 +#define D18F2x110_DctSelHi_WIDTH 1 +#define D18F2x110_DctSelHi_MASK 0x2 +#define D18F2x110_DctSelIntLvEn_OFFSET 2 +#define D18F2x110_DctSelIntLvEn_WIDTH 1 +#define D18F2x110_DctSelIntLvEn_MASK 0x4 +#define D18F2x110_MemClrInit_OFFSET 3 +#define D18F2x110_MemClrInit_WIDTH 1 +#define D18F2x110_MemClrInit_MASK 0x8 +#define D18F2x110_Reserved_4_4_OFFSET 4 +#define D18F2x110_Reserved_4_4_WIDTH 1 +#define D18F2x110_Reserved_4_4_MASK 0x10 +#define D18F2x110_DctDatIntLv_OFFSET 5 +#define D18F2x110_DctDatIntLv_WIDTH 1 +#define D18F2x110_DctDatIntLv_MASK 0x20 +#define D18F2x110_DctSelIntLvAddr_1_0__OFFSET 6 +#define D18F2x110_DctSelIntLvAddr_1_0__WIDTH 2 +#define D18F2x110_DctSelIntLvAddr_1_0__MASK 0xc0 +#define D18F2x110_DramEnable_OFFSET 8 +#define D18F2x110_DramEnable_WIDTH 1 +#define D18F2x110_DramEnable_MASK 0x100 +#define D18F2x110_MemClrBusy_OFFSET 9 +#define D18F2x110_MemClrBusy_WIDTH 1 +#define D18F2x110_MemClrBusy_MASK 0x200 +#define D18F2x110_MemCleared_OFFSET 10 +#define D18F2x110_MemCleared_WIDTH 1 +#define D18F2x110_MemCleared_MASK 0x400 +#define D18F2x110_DctSelBaseAddr_47_27__OFFSET 11 +#define D18F2x110_DctSelBaseAddr_47_27__WIDTH 21 +#define D18F2x110_DctSelBaseAddr_47_27__MASK 0xfffff800 + +/// D18F2x110 +typedef union { + struct { ///< + UINT32 DctSelHiRngEn:1 ; ///< + UINT32 DctSelHi:1 ; ///< + UINT32 DctSelIntLvEn:1 ; ///< + UINT32 MemClrInit:1 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 DctDatIntLv:1 ; ///< + UINT32 DctSelIntLvAddr_1_0_:2 ; ///< + UINT32 DramEnable:1 ; ///< + UINT32 MemClrBusy:1 ; ///< + UINT32 MemCleared:1 ; ///< + UINT32 DctSelBaseAddr_47_27_:21; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x110_STRUCT; + +// **** D18F2x114 Register Definition **** +// Address +#define D18F2x114_ADDRESS 0x114 + +// Type +#define D18F2x114_TYPE TYPE_D18F2 +// Field Data +#define D18F2x114_Reserved_8_0_OFFSET 0 +#define D18F2x114_Reserved_8_0_WIDTH 9 +#define D18F2x114_Reserved_8_0_MASK 0x1ff +#define D18F2x114_DctSelIntLvAddr_2__OFFSET 9 +#define D18F2x114_DctSelIntLvAddr_2__WIDTH 1 +#define D18F2x114_DctSelIntLvAddr_2__MASK 0x200 +#define D18F2x114_DctSelBaseOffset_47_26__OFFSET 10 +#define D18F2x114_DctSelBaseOffset_47_26__WIDTH 22 +#define D18F2x114_DctSelBaseOffset_47_26__MASK 0xfffffc00 + +/// D18F2x114 +typedef union { + struct { ///< + UINT32 Reserved_8_0:9 ; ///< + UINT32 DctSelIntLvAddr_2_:1 ; ///< + UINT32 DctSelBaseOffset_47_26_:22; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x114_STRUCT; + +// **** D18F2x118 Register Definition **** +// Address +#define D18F2x118_ADDRESS 0x118 + +// Type +#define D18F2x118_TYPE TYPE_D18F2 +// Field Data +#define D18F2x118_MctPriCpuRd_OFFSET 0 +#define D18F2x118_MctPriCpuRd_WIDTH 2 +#define D18F2x118_MctPriCpuRd_MASK 0x3 +#define D18F2x118_MctPriCpuWr_OFFSET 2 +#define D18F2x118_MctPriCpuWr_WIDTH 2 +#define D18F2x118_MctPriCpuWr_MASK 0xc +#define D18F2x118_MctPriIsocRd_OFFSET 4 +#define D18F2x118_MctPriIsocRd_WIDTH 2 +#define D18F2x118_MctPriIsocRd_MASK 0x30 +#define D18F2x118_MctPriIsocWr_OFFSET 6 +#define D18F2x118_MctPriIsocWr_WIDTH 2 +#define D18F2x118_MctPriIsocWr_MASK 0xc0 +#define D18F2x118_MctPriDefault_OFFSET 8 +#define D18F2x118_MctPriDefault_WIDTH 2 +#define D18F2x118_MctPriDefault_MASK 0x300 +#define D18F2x118_MctPriWr_OFFSET 10 +#define D18F2x118_MctPriWr_WIDTH 2 +#define D18F2x118_MctPriWr_MASK 0xc00 +#define D18F2x118_MctPriIsoc_OFFSET 12 +#define D18F2x118_MctPriIsoc_WIDTH 2 +#define D18F2x118_MctPriIsoc_MASK 0x3000 +#define D18F2x118_MctPriTrace_OFFSET 14 +#define D18F2x118_MctPriTrace_WIDTH 2 +#define D18F2x118_MctPriTrace_MASK 0xc000 +#define D18F2x118_MctPriScrub_OFFSET 16 +#define D18F2x118_MctPriScrub_WIDTH 2 +#define D18F2x118_MctPriScrub_MASK 0x30000 +#define D18F2x118_CC6SaveEn_OFFSET 18 +#define D18F2x118_CC6SaveEn_WIDTH 1 +#define D18F2x118_CC6SaveEn_MASK 0x40000 +#define D18F2x118_LockDramCfg_OFFSET 19 +#define D18F2x118_LockDramCfg_WIDTH 1 +#define D18F2x118_LockDramCfg_MASK 0x80000 +#define D18F2x118_McqMedPriByPassMax_OFFSET 20 +#define D18F2x118_McqMedPriByPassMax_WIDTH 3 +#define D18F2x118_McqMedPriByPassMax_MASK 0x700000 +#define D18F2x118_Reserved_23_23_OFFSET 23 +#define D18F2x118_Reserved_23_23_WIDTH 1 +#define D18F2x118_Reserved_23_23_MASK 0x800000 +#define D18F2x118_McqHiPriByPassMax_OFFSET 24 +#define D18F2x118_McqHiPriByPassMax_WIDTH 3 +#define D18F2x118_McqHiPriByPassMax_MASK 0x7000000 +#define D18F2x118_MctEccDisLatOptEn_OFFSET 27 +#define D18F2x118_MctEccDisLatOptEn_WIDTH 1 +#define D18F2x118_MctEccDisLatOptEn_MASK 0x8000000 +#define D18F2x118_MctVarPriCntLmt_OFFSET 28 +#define D18F2x118_MctVarPriCntLmt_WIDTH 4 +#define D18F2x118_MctVarPriCntLmt_MASK 0xf0000000 + +/// D18F2x118 +typedef union { + struct { ///< + UINT32 MctPriCpuRd:2 ; ///< + UINT32 MctPriCpuWr:2 ; ///< + UINT32 MctPriIsocRd:2 ; ///< + UINT32 MctPriIsocWr:2 ; ///< + UINT32 MctPriDefault:2 ; ///< + UINT32 MctPriWr:2 ; ///< + UINT32 MctPriIsoc:2 ; ///< + UINT32 MctPriTrace:2 ; ///< + UINT32 MctPriScrub:2 ; ///< + UINT32 CC6SaveEn:1 ; ///< + UINT32 LockDramCfg:1 ; ///< + UINT32 McqMedPriByPassMax:3 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 McqHiPriByPassMax:3 ; ///< + UINT32 MctEccDisLatOptEn:1 ; ///< + UINT32 MctVarPriCntLmt:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x118_STRUCT; + +// **** D18F2x11C Register Definition **** +// Address +#define D18F2x11C_ADDRESS 0x11c + +// Type +#define D18F2x11C_TYPE TYPE_D18F2 +// Field Data +#define D18F2x11C_DctWrLimit_OFFSET 0 +#define D18F2x11C_DctWrLimit_WIDTH 2 +#define D18F2x11C_DctWrLimit_MASK 0x3 +#define D18F2x11C_MctWrLimit_OFFSET 2 +#define D18F2x11C_MctWrLimit_WIDTH 5 +#define D18F2x11C_MctWrLimit_MASK 0x7c +#define D18F2x11C_MctPrefReqLimit_OFFSET 7 +#define D18F2x11C_MctPrefReqLimit_WIDTH 5 +#define D18F2x11C_MctPrefReqLimit_MASK 0xf80 +#define D18F2x11C_PrefCpuDis_OFFSET 12 +#define D18F2x11C_PrefCpuDis_WIDTH 1 +#define D18F2x11C_PrefCpuDis_MASK 0x1000 +#define D18F2x11C_PrefIoDis_OFFSET 13 +#define D18F2x11C_PrefIoDis_WIDTH 1 +#define D18F2x11C_PrefIoDis_MASK 0x2000 +#define D18F2x11C_PrefIoFixStrideEn_OFFSET 14 +#define D18F2x11C_PrefIoFixStrideEn_WIDTH 1 +#define D18F2x11C_PrefIoFixStrideEn_MASK 0x4000 +#define D18F2x11C_PrefFixStrideEn_OFFSET 15 +#define D18F2x11C_PrefFixStrideEn_WIDTH 1 +#define D18F2x11C_PrefFixStrideEn_MASK 0x8000 +#define D18F2x11C_PrefFixDist_OFFSET 16 +#define D18F2x11C_PrefFixDist_WIDTH 2 +#define D18F2x11C_PrefFixDist_MASK 0x30000 +#define D18F2x11C_PrefConfSat_OFFSET 18 +#define D18F2x11C_PrefConfSat_WIDTH 2 +#define D18F2x11C_PrefConfSat_MASK 0xc0000 +#define D18F2x11C_PrefOneConf_OFFSET 20 +#define D18F2x11C_PrefOneConf_WIDTH 2 +#define D18F2x11C_PrefOneConf_MASK 0x300000 +#define D18F2x11C_PrefTwoConf_OFFSET 22 +#define D18F2x11C_PrefTwoConf_WIDTH 3 +#define D18F2x11C_PrefTwoConf_MASK 0x1c00000 +#define D18F2x11C_PrefThreeConf_OFFSET 25 +#define D18F2x11C_PrefThreeConf_WIDTH 3 +#define D18F2x11C_PrefThreeConf_MASK 0xe000000 +#define D18F2x11C_PrefDramTrainMode_OFFSET 28 +#define D18F2x11C_PrefDramTrainMode_WIDTH 1 +#define D18F2x11C_PrefDramTrainMode_MASK 0x10000000 +#define D18F2x11C_FlushWrOnStpGnt_OFFSET 29 +#define D18F2x11C_FlushWrOnStpGnt_WIDTH 1 +#define D18F2x11C_FlushWrOnStpGnt_MASK 0x20000000 +#define D18F2x11C_FlushWr_OFFSET 30 +#define D18F2x11C_FlushWr_WIDTH 1 +#define D18F2x11C_FlushWr_MASK 0x40000000 +#define D18F2x11C_Reserved_31_31_OFFSET 31 +#define D18F2x11C_Reserved_31_31_WIDTH 1 +#define D18F2x11C_Reserved_31_31_MASK 0x80000000 + +/// D18F2x11C +typedef union { + struct { ///< + UINT32 DctWrLimit:2 ; ///< + UINT32 MctWrLimit:5 ; ///< + UINT32 MctPrefReqLimit:5 ; ///< + UINT32 PrefCpuDis:1 ; ///< + UINT32 PrefIoDis:1 ; ///< + UINT32 PrefIoFixStrideEn:1 ; ///< + UINT32 PrefFixStrideEn:1 ; ///< + UINT32 PrefFixDist:2 ; ///< + UINT32 PrefConfSat:2 ; ///< + UINT32 PrefOneConf:2 ; ///< + UINT32 PrefTwoConf:3 ; ///< + UINT32 PrefThreeConf:3 ; ///< + UINT32 PrefDramTrainMode:1 ; ///< + UINT32 FlushWrOnStpGnt:1 ; ///< + UINT32 FlushWr:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x11C_STRUCT; + + + + + + +// **** D18F2x1B0 Register Definition **** +// Address +#define D18F2x1B0_ADDRESS 0x1b0 + +// Type +#define D18F2x1B0_TYPE TYPE_D18F2 +// Field Data +#define D18F2x1B0_AdapPrefMissRatio_OFFSET 0 +#define D18F2x1B0_AdapPrefMissRatio_WIDTH 2 +#define D18F2x1B0_AdapPrefMissRatio_MASK 0x3 +#define D18F2x1B0_AdapPrefPositiveStep_OFFSET 2 +#define D18F2x1B0_AdapPrefPositiveStep_WIDTH 2 +#define D18F2x1B0_AdapPrefPositiveStep_MASK 0xc +#define D18F2x1B0_AdapPrefNegativeStep_OFFSET 4 +#define D18F2x1B0_AdapPrefNegativeStep_WIDTH 2 +#define D18F2x1B0_AdapPrefNegativeStep_MASK 0x30 +#define D18F2x1B0_Reserved_7_6_OFFSET 6 +#define D18F2x1B0_Reserved_7_6_WIDTH 2 +#define D18F2x1B0_Reserved_7_6_MASK 0xc0 +#define D18F2x1B0_CohPrefPrbLmt_OFFSET 8 +#define D18F2x1B0_CohPrefPrbLmt_WIDTH 3 +#define D18F2x1B0_CohPrefPrbLmt_MASK 0x700 +#define D18F2x1B0_DisIoCohPref_OFFSET 11 +#define D18F2x1B0_DisIoCohPref_WIDTH 1 +#define D18F2x1B0_DisIoCohPref_MASK 0x800 +#define D18F2x1B0_EnSplitDctLimits_OFFSET 12 +#define D18F2x1B0_EnSplitDctLimits_WIDTH 1 +#define D18F2x1B0_EnSplitDctLimits_MASK 0x1000 +#define D18F2x1B0_Reserved_17_13_OFFSET 13 +#define D18F2x1B0_Reserved_17_13_WIDTH 5 +#define D18F2x1B0_Reserved_17_13_MASK 0x3e000 +#define D18F2x1B0_Reserved_19_18_OFFSET 18 +#define D18F2x1B0_Reserved_19_18_WIDTH 2 +#define D18F2x1B0_Reserved_19_18_MASK 0xc0000 +#define D18F2x1B0_DblPrefEn_OFFSET 20 +#define D18F2x1B0_DblPrefEn_WIDTH 1 +#define D18F2x1B0_DblPrefEn_MASK 0x100000 +#define D18F2x1B0_Reserved_21_21_OFFSET 21 +#define D18F2x1B0_Reserved_21_21_WIDTH 1 +#define D18F2x1B0_Reserved_21_21_MASK 0x200000 +#define D18F2x1B0_PrefFourConf_OFFSET 22 +#define D18F2x1B0_PrefFourConf_WIDTH 3 +#define D18F2x1B0_PrefFourConf_MASK 0x1c00000 +#define D18F2x1B0_PrefFiveConf_OFFSET 25 +#define D18F2x1B0_PrefFiveConf_WIDTH 3 +#define D18F2x1B0_PrefFiveConf_MASK 0xe000000 +#define D18F2x1B0_DcqBwThrotWm_OFFSET 28 +#define D18F2x1B0_DcqBwThrotWm_WIDTH 4 +#define D18F2x1B0_DcqBwThrotWm_MASK 0xf0000000 + +/// D18F2x1B0 +typedef union { + struct { ///< + UINT32 AdapPrefMissRatio:2 ; ///< + UINT32 AdapPrefPositiveStep:2 ; ///< + UINT32 AdapPrefNegativeStep:2 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 CohPrefPrbLmt:3 ; ///< + UINT32 DisIoCohPref:1 ; ///< + UINT32 EnSplitDctLimits:1 ; ///< + UINT32 Reserved_17_13:5 ; ///< + UINT32 Reserved_19_18:2 ; ///< + UINT32 DblPrefEn:1 ; ///< + UINT32 Reserved_21_21:1 ; ///< + UINT32 PrefFourConf:3 ; ///< + UINT32 PrefFiveConf:3 ; ///< + UINT32 DcqBwThrotWm:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x1B0_STRUCT; + +// **** D18F2x1B4 Register Definition **** +// Address +#define D18F2x1B4_ADDRESS 0x1b4 + +// Type +#define D18F2x1B4_TYPE TYPE_D18F2 +// Field Data +#define D18F2x1B4_DcqBwThrotWm1_OFFSET 0 +#define D18F2x1B4_DcqBwThrotWm1_WIDTH 5 +#define D18F2x1B4_DcqBwThrotWm1_MASK 0x1f +#define D18F2x1B4_DcqBwThrotWm2_OFFSET 5 +#define D18F2x1B4_DcqBwThrotWm2_WIDTH 5 +#define D18F2x1B4_DcqBwThrotWm2_MASK 0x3e0 +#define D18F2x1B4_DemandPropWm1_OFFSET 10 +#define D18F2x1B4_DemandPropWm1_WIDTH 1 +#define D18F2x1B4_DemandPropWm1_MASK 0x400 +#define D18F2x1B4_DemandAlloWm1_OFFSET 11 +#define D18F2x1B4_DemandAlloWm1_WIDTH 1 +#define D18F2x1B4_DemandAlloWm1_MASK 0x800 +#define D18F2x1B4_StridePropWm1_OFFSET 12 +#define D18F2x1B4_StridePropWm1_WIDTH 1 +#define D18F2x1B4_StridePropWm1_MASK 0x1000 +#define D18F2x1B4_StrideAlloWm1_OFFSET 13 +#define D18F2x1B4_StrideAlloWm1_WIDTH 1 +#define D18F2x1B4_StrideAlloWm1_MASK 0x2000 +#define D18F2x1B4_RegionPropWm1_OFFSET 14 +#define D18F2x1B4_RegionPropWm1_WIDTH 1 +#define D18F2x1B4_RegionPropWm1_MASK 0x4000 +#define D18F2x1B4_RegionAlloWm1_OFFSET 15 +#define D18F2x1B4_RegionAlloWm1_WIDTH 1 +#define D18F2x1B4_RegionAlloWm1_MASK 0x8000 +#define D18F2x1B4_DemandPropWm2_OFFSET 16 +#define D18F2x1B4_DemandPropWm2_WIDTH 1 +#define D18F2x1B4_DemandPropWm2_MASK 0x10000 +#define D18F2x1B4_DemandAlloWm2_OFFSET 17 +#define D18F2x1B4_DemandAlloWm2_WIDTH 1 +#define D18F2x1B4_DemandAlloWm2_MASK 0x20000 +#define D18F2x1B4_StridePropWm2_OFFSET 18 +#define D18F2x1B4_StridePropWm2_WIDTH 1 +#define D18F2x1B4_StridePropWm2_MASK 0x40000 +#define D18F2x1B4_StrideAlloWm2_OFFSET 19 +#define D18F2x1B4_StrideAlloWm2_WIDTH 1 +#define D18F2x1B4_StrideAlloWm2_MASK 0x80000 +#define D18F2x1B4_RegionPropWm2_OFFSET 20 +#define D18F2x1B4_RegionPropWm2_WIDTH 1 +#define D18F2x1B4_RegionPropWm2_MASK 0x100000 +#define D18F2x1B4_RegionAlloWm2_OFFSET 21 +#define D18F2x1B4_RegionAlloWm2_WIDTH 1 +#define D18F2x1B4_RegionAlloWm2_MASK 0x200000 +#define D18F2x1B4_SpecPrefDisWm1_OFFSET 22 +#define D18F2x1B4_SpecPrefDisWm1_WIDTH 1 +#define D18F2x1B4_SpecPrefDisWm1_MASK 0x400000 +#define D18F2x1B4_Reserved_25_23_OFFSET 23 +#define D18F2x1B4_Reserved_25_23_WIDTH 3 +#define D18F2x1B4_Reserved_25_23_MASK 0x3800000 +#define D18F2x1B4_EnSplitMctDatBuffers_OFFSET 26 +#define D18F2x1B4_EnSplitMctDatBuffers_WIDTH 1 +#define D18F2x1B4_EnSplitMctDatBuffers_MASK 0x4000000 +#define D18F2x1B4_FlushWrOnS3StpGnt_OFFSET 27 +#define D18F2x1B4_FlushWrOnS3StpGnt_WIDTH 1 +#define D18F2x1B4_FlushWrOnS3StpGnt_MASK 0x8000000 +#define D18F2x1B4_S3SmafId_OFFSET 28 +#define D18F2x1B4_S3SmafId_WIDTH 3 +#define D18F2x1B4_S3SmafId_MASK 0x70000000 +#define D18F2x1B4_FlushOnMmioWrEn_OFFSET 31 +#define D18F2x1B4_FlushOnMmioWrEn_WIDTH 1 +#define D18F2x1B4_FlushOnMmioWrEn_MASK 0x80000000 + +/// D18F2x1B4 +typedef union { + struct { ///< + UINT32 DcqBwThrotWm1:5 ; ///< + UINT32 DcqBwThrotWm2:5 ; ///< + UINT32 DemandPropWm1:1 ; ///< + UINT32 DemandAlloWm1:1 ; ///< + UINT32 StridePropWm1:1 ; ///< + UINT32 StrideAlloWm1:1 ; ///< + UINT32 RegionPropWm1:1 ; ///< + UINT32 RegionAlloWm1:1 ; ///< + UINT32 DemandPropWm2:1 ; ///< + UINT32 DemandAlloWm2:1 ; ///< + UINT32 StridePropWm2:1 ; ///< + UINT32 StrideAlloWm2:1 ; ///< + UINT32 RegionPropWm2:1 ; ///< + UINT32 RegionAlloWm2:1 ; ///< + UINT32 SpecPrefDisWm1:1 ; ///< + UINT32 Reserved_25_23:3 ; ///< + UINT32 EnSplitMctDatBuffers:1 ; ///< + UINT32 FlushWrOnS3StpGnt:1 ; ///< + UINT32 S3SmafId:3 ; ///< + UINT32 FlushOnMmioWrEn:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x1B4_STRUCT; + +// **** D18F2x200_dct0_mp1 Register Definition **** +// Address +#define D18F2x200_dct0_mp1_ADDRESS 0x200 + +// Type +#define D18F2x200_dct0_mp1_TYPE TYPE_D18F2_dct0_mp1 +// Field Data +#define D18F2x200_dct0_mp1_Tcl_OFFSET 0 +#define D18F2x200_dct0_mp1_Tcl_WIDTH 5 +#define D18F2x200_dct0_mp1_Tcl_MASK 0x1f +#define D18F2x200_dct0_mp1_Reserved_7_5_OFFSET 5 +#define D18F2x200_dct0_mp1_Reserved_7_5_WIDTH 3 +#define D18F2x200_dct0_mp1_Reserved_7_5_MASK 0xe0 +#define D18F2x200_dct0_mp1_Trcd_OFFSET 8 +#define D18F2x200_dct0_mp1_Trcd_WIDTH 5 +#define D18F2x200_dct0_mp1_Trcd_MASK 0x1f00 +#define D18F2x200_dct0_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x200_dct0_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x200_dct0_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x200_dct0_mp1_Trp_OFFSET 16 +#define D18F2x200_dct0_mp1_Trp_WIDTH 5 +#define D18F2x200_dct0_mp1_Trp_MASK 0x1f0000 +#define D18F2x200_dct0_mp1_Reserved_23_21_OFFSET 21 +#define D18F2x200_dct0_mp1_Reserved_23_21_WIDTH 3 +#define D18F2x200_dct0_mp1_Reserved_23_21_MASK 0xe00000 +#define D18F2x200_dct0_mp1_Tras_OFFSET 24 +#define D18F2x200_dct0_mp1_Tras_WIDTH 6 +#define D18F2x200_dct0_mp1_Tras_MASK 0x3f000000 +#define D18F2x200_dct0_mp1_Reserved_31_30_OFFSET 30 +#define D18F2x200_dct0_mp1_Reserved_31_30_WIDTH 2 +#define D18F2x200_dct0_mp1_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x200_dct0_mp1 +typedef union { + struct { ///< + UINT32 Tcl:5 ; ///< + UINT32 Reserved_7_5:3 ; ///< + UINT32 Trcd:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 Trp:5 ; ///< + UINT32 Reserved_23_21:3 ; ///< + UINT32 Tras:6 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x200_dct0_mp1_STRUCT; + +// **** D18F2x200_dct0_mp0 Register Definition **** +// Address +#define D18F2x200_dct0_mp0_ADDRESS 0x200 + +// Type +#define D18F2x200_dct0_mp0_TYPE TYPE_D18F2_dct0_mp0 +// Field Data +#define D18F2x200_dct0_mp0_Tcl_OFFSET 0 +#define D18F2x200_dct0_mp0_Tcl_WIDTH 5 +#define D18F2x200_dct0_mp0_Tcl_MASK 0x1f +#define D18F2x200_dct0_mp0_Reserved_7_5_OFFSET 5 +#define D18F2x200_dct0_mp0_Reserved_7_5_WIDTH 3 +#define D18F2x200_dct0_mp0_Reserved_7_5_MASK 0xe0 +#define D18F2x200_dct0_mp0_Trcd_OFFSET 8 +#define D18F2x200_dct0_mp0_Trcd_WIDTH 5 +#define D18F2x200_dct0_mp0_Trcd_MASK 0x1f00 +#define D18F2x200_dct0_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x200_dct0_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x200_dct0_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x200_dct0_mp0_Trp_OFFSET 16 +#define D18F2x200_dct0_mp0_Trp_WIDTH 5 +#define D18F2x200_dct0_mp0_Trp_MASK 0x1f0000 +#define D18F2x200_dct0_mp0_Reserved_23_21_OFFSET 21 +#define D18F2x200_dct0_mp0_Reserved_23_21_WIDTH 3 +#define D18F2x200_dct0_mp0_Reserved_23_21_MASK 0xe00000 +#define D18F2x200_dct0_mp0_Tras_OFFSET 24 +#define D18F2x200_dct0_mp0_Tras_WIDTH 6 +#define D18F2x200_dct0_mp0_Tras_MASK 0x3f000000 +#define D18F2x200_dct0_mp0_Reserved_31_30_OFFSET 30 +#define D18F2x200_dct0_mp0_Reserved_31_30_WIDTH 2 +#define D18F2x200_dct0_mp0_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x200_dct0_mp0 +typedef union { + struct { ///< + UINT32 Tcl:5 ; ///< + UINT32 Reserved_7_5:3 ; ///< + UINT32 Trcd:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 Trp:5 ; ///< + UINT32 Reserved_23_21:3 ; ///< + UINT32 Tras:6 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x200_dct0_mp0_STRUCT; + +// **** D18F2x200_dct1_mp1 Register Definition **** +// Address +#define D18F2x200_dct1_mp1_ADDRESS 0x200 + +// Type +#define D18F2x200_dct1_mp1_TYPE TYPE_D18F2_dct1_mp1 +// Field Data +#define D18F2x200_dct1_mp1_Tcl_OFFSET 0 +#define D18F2x200_dct1_mp1_Tcl_WIDTH 5 +#define D18F2x200_dct1_mp1_Tcl_MASK 0x1f +#define D18F2x200_dct1_mp1_Reserved_7_5_OFFSET 5 +#define D18F2x200_dct1_mp1_Reserved_7_5_WIDTH 3 +#define D18F2x200_dct1_mp1_Reserved_7_5_MASK 0xe0 +#define D18F2x200_dct1_mp1_Trcd_OFFSET 8 +#define D18F2x200_dct1_mp1_Trcd_WIDTH 5 +#define D18F2x200_dct1_mp1_Trcd_MASK 0x1f00 +#define D18F2x200_dct1_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x200_dct1_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x200_dct1_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x200_dct1_mp1_Trp_OFFSET 16 +#define D18F2x200_dct1_mp1_Trp_WIDTH 5 +#define D18F2x200_dct1_mp1_Trp_MASK 0x1f0000 +#define D18F2x200_dct1_mp1_Reserved_23_21_OFFSET 21 +#define D18F2x200_dct1_mp1_Reserved_23_21_WIDTH 3 +#define D18F2x200_dct1_mp1_Reserved_23_21_MASK 0xe00000 +#define D18F2x200_dct1_mp1_Tras_OFFSET 24 +#define D18F2x200_dct1_mp1_Tras_WIDTH 6 +#define D18F2x200_dct1_mp1_Tras_MASK 0x3f000000 +#define D18F2x200_dct1_mp1_Reserved_31_30_OFFSET 30 +#define D18F2x200_dct1_mp1_Reserved_31_30_WIDTH 2 +#define D18F2x200_dct1_mp1_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x200_dct1_mp1 +typedef union { + struct { ///< + UINT32 Tcl:5 ; ///< + UINT32 Reserved_7_5:3 ; ///< + UINT32 Trcd:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 Trp:5 ; ///< + UINT32 Reserved_23_21:3 ; ///< + UINT32 Tras:6 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x200_dct1_mp1_STRUCT; + +// **** D18F2x200_dct1_mp0 Register Definition **** +// Address +#define D18F2x200_dct1_mp0_ADDRESS 0x200 + +// Type +#define D18F2x200_dct1_mp0_TYPE TYPE_D18F2_dct1_mp0 +// Field Data +#define D18F2x200_dct1_mp0_Tcl_OFFSET 0 +#define D18F2x200_dct1_mp0_Tcl_WIDTH 5 +#define D18F2x200_dct1_mp0_Tcl_MASK 0x1f +#define D18F2x200_dct1_mp0_Reserved_7_5_OFFSET 5 +#define D18F2x200_dct1_mp0_Reserved_7_5_WIDTH 3 +#define D18F2x200_dct1_mp0_Reserved_7_5_MASK 0xe0 +#define D18F2x200_dct1_mp0_Trcd_OFFSET 8 +#define D18F2x200_dct1_mp0_Trcd_WIDTH 5 +#define D18F2x200_dct1_mp0_Trcd_MASK 0x1f00 +#define D18F2x200_dct1_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x200_dct1_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x200_dct1_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x200_dct1_mp0_Trp_OFFSET 16 +#define D18F2x200_dct1_mp0_Trp_WIDTH 5 +#define D18F2x200_dct1_mp0_Trp_MASK 0x1f0000 +#define D18F2x200_dct1_mp0_Reserved_23_21_OFFSET 21 +#define D18F2x200_dct1_mp0_Reserved_23_21_WIDTH 3 +#define D18F2x200_dct1_mp0_Reserved_23_21_MASK 0xe00000 +#define D18F2x200_dct1_mp0_Tras_OFFSET 24 +#define D18F2x200_dct1_mp0_Tras_WIDTH 6 +#define D18F2x200_dct1_mp0_Tras_MASK 0x3f000000 +#define D18F2x200_dct1_mp0_Reserved_31_30_OFFSET 30 +#define D18F2x200_dct1_mp0_Reserved_31_30_WIDTH 2 +#define D18F2x200_dct1_mp0_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x200_dct1_mp0 +typedef union { + struct { ///< + UINT32 Tcl:5 ; ///< + UINT32 Reserved_7_5:3 ; ///< + UINT32 Trcd:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 Trp:5 ; ///< + UINT32 Reserved_23_21:3 ; ///< + UINT32 Tras:6 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x200_dct1_mp0_STRUCT; + +// **** D18F2x204_dct0_mp0 Register Definition **** +// Address +#define D18F2x204_dct0_mp0_ADDRESS 0x204 + +// Type +#define D18F2x204_dct0_mp0_TYPE TYPE_D18F2_dct0_mp0 +// Field Data +#define D18F2x204_dct0_mp0_Trc_OFFSET 0 +#define D18F2x204_dct0_mp0_Trc_WIDTH 6 +#define D18F2x204_dct0_mp0_Trc_MASK 0x3f +#define D18F2x204_dct0_mp0_Reserved_7_6_OFFSET 6 +#define D18F2x204_dct0_mp0_Reserved_7_6_WIDTH 2 +#define D18F2x204_dct0_mp0_Reserved_7_6_MASK 0xc0 +#define D18F2x204_dct0_mp0_Trrd_OFFSET 8 +#define D18F2x204_dct0_mp0_Trrd_WIDTH 4 +#define D18F2x204_dct0_mp0_Trrd_MASK 0xf00 +#define D18F2x204_dct0_mp0_Reserved_15_12_OFFSET 12 +#define D18F2x204_dct0_mp0_Reserved_15_12_WIDTH 4 +#define D18F2x204_dct0_mp0_Reserved_15_12_MASK 0xf000 +#define D18F2x204_dct0_mp0_FourActWindow_OFFSET 16 +#define D18F2x204_dct0_mp0_FourActWindow_WIDTH 6 +#define D18F2x204_dct0_mp0_FourActWindow_MASK 0x3f0000 +#define D18F2x204_dct0_mp0_Reserved_23_22_OFFSET 22 +#define D18F2x204_dct0_mp0_Reserved_23_22_WIDTH 2 +#define D18F2x204_dct0_mp0_Reserved_23_22_MASK 0xc00000 +#define D18F2x204_dct0_mp0_Trtp_OFFSET 24 +#define D18F2x204_dct0_mp0_Trtp_WIDTH 4 +#define D18F2x204_dct0_mp0_Trtp_MASK 0xf000000 +#define D18F2x204_dct0_mp0_Reserved_31_28_OFFSET 28 +#define D18F2x204_dct0_mp0_Reserved_31_28_WIDTH 4 +#define D18F2x204_dct0_mp0_Reserved_31_28_MASK 0xf0000000 + +/// D18F2x204_dct0_mp0 +typedef union { + struct { ///< + UINT32 Trc:6 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 Trrd:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 FourActWindow:6 ; ///< + UINT32 Reserved_23_22:2 ; ///< + UINT32 Trtp:4 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x204_dct0_mp0_STRUCT; + +// **** D18F2x204_dct1_mp0 Register Definition **** +// Address +#define D18F2x204_dct1_mp0_ADDRESS 0x204 + +// Type +#define D18F2x204_dct1_mp0_TYPE TYPE_D18F2_dct1_mp0 +// Field Data +#define D18F2x204_dct1_mp0_Trc_OFFSET 0 +#define D18F2x204_dct1_mp0_Trc_WIDTH 6 +#define D18F2x204_dct1_mp0_Trc_MASK 0x3f +#define D18F2x204_dct1_mp0_Reserved_7_6_OFFSET 6 +#define D18F2x204_dct1_mp0_Reserved_7_6_WIDTH 2 +#define D18F2x204_dct1_mp0_Reserved_7_6_MASK 0xc0 +#define D18F2x204_dct1_mp0_Trrd_OFFSET 8 +#define D18F2x204_dct1_mp0_Trrd_WIDTH 4 +#define D18F2x204_dct1_mp0_Trrd_MASK 0xf00 +#define D18F2x204_dct1_mp0_Reserved_15_12_OFFSET 12 +#define D18F2x204_dct1_mp0_Reserved_15_12_WIDTH 4 +#define D18F2x204_dct1_mp0_Reserved_15_12_MASK 0xf000 +#define D18F2x204_dct1_mp0_FourActWindow_OFFSET 16 +#define D18F2x204_dct1_mp0_FourActWindow_WIDTH 6 +#define D18F2x204_dct1_mp0_FourActWindow_MASK 0x3f0000 +#define D18F2x204_dct1_mp0_Reserved_23_22_OFFSET 22 +#define D18F2x204_dct1_mp0_Reserved_23_22_WIDTH 2 +#define D18F2x204_dct1_mp0_Reserved_23_22_MASK 0xc00000 +#define D18F2x204_dct1_mp0_Trtp_OFFSET 24 +#define D18F2x204_dct1_mp0_Trtp_WIDTH 4 +#define D18F2x204_dct1_mp0_Trtp_MASK 0xf000000 +#define D18F2x204_dct1_mp0_Reserved_31_28_OFFSET 28 +#define D18F2x204_dct1_mp0_Reserved_31_28_WIDTH 4 +#define D18F2x204_dct1_mp0_Reserved_31_28_MASK 0xf0000000 + +/// D18F2x204_dct1_mp0 +typedef union { + struct { ///< + UINT32 Trc:6 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 Trrd:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 FourActWindow:6 ; ///< + UINT32 Reserved_23_22:2 ; ///< + UINT32 Trtp:4 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x204_dct1_mp0_STRUCT; + +// **** D18F2x204_dct0_mp1 Register Definition **** +// Address +#define D18F2x204_dct0_mp1_ADDRESS 0x204 + +// Type +#define D18F2x204_dct0_mp1_TYPE TYPE_D18F2_dct0_mp1 +// Field Data +#define D18F2x204_dct0_mp1_Trc_OFFSET 0 +#define D18F2x204_dct0_mp1_Trc_WIDTH 6 +#define D18F2x204_dct0_mp1_Trc_MASK 0x3f +#define D18F2x204_dct0_mp1_Reserved_7_6_OFFSET 6 +#define D18F2x204_dct0_mp1_Reserved_7_6_WIDTH 2 +#define D18F2x204_dct0_mp1_Reserved_7_6_MASK 0xc0 +#define D18F2x204_dct0_mp1_Trrd_OFFSET 8 +#define D18F2x204_dct0_mp1_Trrd_WIDTH 4 +#define D18F2x204_dct0_mp1_Trrd_MASK 0xf00 +#define D18F2x204_dct0_mp1_Reserved_15_12_OFFSET 12 +#define D18F2x204_dct0_mp1_Reserved_15_12_WIDTH 4 +#define D18F2x204_dct0_mp1_Reserved_15_12_MASK 0xf000 +#define D18F2x204_dct0_mp1_FourActWindow_OFFSET 16 +#define D18F2x204_dct0_mp1_FourActWindow_WIDTH 6 +#define D18F2x204_dct0_mp1_FourActWindow_MASK 0x3f0000 +#define D18F2x204_dct0_mp1_Reserved_23_22_OFFSET 22 +#define D18F2x204_dct0_mp1_Reserved_23_22_WIDTH 2 +#define D18F2x204_dct0_mp1_Reserved_23_22_MASK 0xc00000 +#define D18F2x204_dct0_mp1_Trtp_OFFSET 24 +#define D18F2x204_dct0_mp1_Trtp_WIDTH 4 +#define D18F2x204_dct0_mp1_Trtp_MASK 0xf000000 +#define D18F2x204_dct0_mp1_Reserved_31_28_OFFSET 28 +#define D18F2x204_dct0_mp1_Reserved_31_28_WIDTH 4 +#define D18F2x204_dct0_mp1_Reserved_31_28_MASK 0xf0000000 + +/// D18F2x204_dct0_mp1 +typedef union { + struct { ///< + UINT32 Trc:6 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 Trrd:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 FourActWindow:6 ; ///< + UINT32 Reserved_23_22:2 ; ///< + UINT32 Trtp:4 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x204_dct0_mp1_STRUCT; + +// **** D18F2x204_dct1_mp1 Register Definition **** +// Address +#define D18F2x204_dct1_mp1_ADDRESS 0x204 + +// Type +#define D18F2x204_dct1_mp1_TYPE TYPE_D18F2_dct1_mp1 +// Field Data +#define D18F2x204_dct1_mp1_Trc_OFFSET 0 +#define D18F2x204_dct1_mp1_Trc_WIDTH 6 +#define D18F2x204_dct1_mp1_Trc_MASK 0x3f +#define D18F2x204_dct1_mp1_Reserved_7_6_OFFSET 6 +#define D18F2x204_dct1_mp1_Reserved_7_6_WIDTH 2 +#define D18F2x204_dct1_mp1_Reserved_7_6_MASK 0xc0 +#define D18F2x204_dct1_mp1_Trrd_OFFSET 8 +#define D18F2x204_dct1_mp1_Trrd_WIDTH 4 +#define D18F2x204_dct1_mp1_Trrd_MASK 0xf00 +#define D18F2x204_dct1_mp1_Reserved_15_12_OFFSET 12 +#define D18F2x204_dct1_mp1_Reserved_15_12_WIDTH 4 +#define D18F2x204_dct1_mp1_Reserved_15_12_MASK 0xf000 +#define D18F2x204_dct1_mp1_FourActWindow_OFFSET 16 +#define D18F2x204_dct1_mp1_FourActWindow_WIDTH 6 +#define D18F2x204_dct1_mp1_FourActWindow_MASK 0x3f0000 +#define D18F2x204_dct1_mp1_Reserved_23_22_OFFSET 22 +#define D18F2x204_dct1_mp1_Reserved_23_22_WIDTH 2 +#define D18F2x204_dct1_mp1_Reserved_23_22_MASK 0xc00000 +#define D18F2x204_dct1_mp1_Trtp_OFFSET 24 +#define D18F2x204_dct1_mp1_Trtp_WIDTH 4 +#define D18F2x204_dct1_mp1_Trtp_MASK 0xf000000 +#define D18F2x204_dct1_mp1_Reserved_31_28_OFFSET 28 +#define D18F2x204_dct1_mp1_Reserved_31_28_WIDTH 4 +#define D18F2x204_dct1_mp1_Reserved_31_28_MASK 0xf0000000 + +/// D18F2x204_dct1_mp1 +typedef union { + struct { ///< + UINT32 Trc:6 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 Trrd:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 FourActWindow:6 ; ///< + UINT32 Reserved_23_22:2 ; ///< + UINT32 Trtp:4 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x204_dct1_mp1_STRUCT; + +// **** D18F2x208_dct0 Register Definition **** +// Address +#define D18F2x208_dct0_ADDRESS 0x208 + +// Type +#define D18F2x208_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x208_dct0_Trfc0_OFFSET 0 +#define D18F2x208_dct0_Trfc0_WIDTH 3 +#define D18F2x208_dct0_Trfc0_MASK 0x7 +#define D18F2x208_dct0_Reserved_7_3_OFFSET 3 +#define D18F2x208_dct0_Reserved_7_3_WIDTH 5 +#define D18F2x208_dct0_Reserved_7_3_MASK 0xf8 +#define D18F2x208_dct0_Trfc1_OFFSET 8 +#define D18F2x208_dct0_Trfc1_WIDTH 3 +#define D18F2x208_dct0_Trfc1_MASK 0x700 +#define D18F2x208_dct0_Reserved_15_11_OFFSET 11 +#define D18F2x208_dct0_Reserved_15_11_WIDTH 5 +#define D18F2x208_dct0_Reserved_15_11_MASK 0xf800 +#define D18F2x208_dct0_Trfc2_OFFSET 16 +#define D18F2x208_dct0_Trfc2_WIDTH 3 +#define D18F2x208_dct0_Trfc2_MASK 0x70000 +#define D18F2x208_dct0_Reserved_23_19_OFFSET 19 +#define D18F2x208_dct0_Reserved_23_19_WIDTH 5 +#define D18F2x208_dct0_Reserved_23_19_MASK 0xf80000 +#define D18F2x208_dct0_Trfc3_OFFSET 24 +#define D18F2x208_dct0_Trfc3_WIDTH 3 +#define D18F2x208_dct0_Trfc3_MASK 0x7000000 +#define D18F2x208_dct0_Reserved_31_27_OFFSET 27 +#define D18F2x208_dct0_Reserved_31_27_WIDTH 5 +#define D18F2x208_dct0_Reserved_31_27_MASK 0xf8000000 + +/// D18F2x208_dct0 +typedef union { + struct { ///< + UINT32 Trfc0:3 ; ///< + UINT32 Reserved_7_3:5 ; ///< + UINT32 Trfc1:3 ; ///< + UINT32 Reserved_15_11:5 ; ///< + UINT32 Trfc2:3 ; ///< + UINT32 Reserved_23_19:5 ; ///< + UINT32 Trfc3:3 ; ///< + UINT32 Reserved_31_27:5 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x208_dct0_STRUCT; + +// **** D18F2x208_dct1 Register Definition **** +// Address +#define D18F2x208_dct1_ADDRESS 0x208 + +// Type +#define D18F2x208_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x208_dct1_Trfc0_OFFSET 0 +#define D18F2x208_dct1_Trfc0_WIDTH 3 +#define D18F2x208_dct1_Trfc0_MASK 0x7 +#define D18F2x208_dct1_Reserved_7_3_OFFSET 3 +#define D18F2x208_dct1_Reserved_7_3_WIDTH 5 +#define D18F2x208_dct1_Reserved_7_3_MASK 0xf8 +#define D18F2x208_dct1_Trfc1_OFFSET 8 +#define D18F2x208_dct1_Trfc1_WIDTH 3 +#define D18F2x208_dct1_Trfc1_MASK 0x700 +#define D18F2x208_dct1_Reserved_15_11_OFFSET 11 +#define D18F2x208_dct1_Reserved_15_11_WIDTH 5 +#define D18F2x208_dct1_Reserved_15_11_MASK 0xf800 +#define D18F2x208_dct1_Trfc2_OFFSET 16 +#define D18F2x208_dct1_Trfc2_WIDTH 3 +#define D18F2x208_dct1_Trfc2_MASK 0x70000 +#define D18F2x208_dct1_Reserved_23_19_OFFSET 19 +#define D18F2x208_dct1_Reserved_23_19_WIDTH 5 +#define D18F2x208_dct1_Reserved_23_19_MASK 0xf80000 +#define D18F2x208_dct1_Trfc3_OFFSET 24 +#define D18F2x208_dct1_Trfc3_WIDTH 3 +#define D18F2x208_dct1_Trfc3_MASK 0x7000000 +#define D18F2x208_dct1_Reserved_31_27_OFFSET 27 +#define D18F2x208_dct1_Reserved_31_27_WIDTH 5 +#define D18F2x208_dct1_Reserved_31_27_MASK 0xf8000000 + +/// D18F2x208_dct1 +typedef union { + struct { ///< + UINT32 Trfc0:3 ; ///< + UINT32 Reserved_7_3:5 ; ///< + UINT32 Trfc1:3 ; ///< + UINT32 Reserved_15_11:5 ; ///< + UINT32 Trfc2:3 ; ///< + UINT32 Reserved_23_19:5 ; ///< + UINT32 Trfc3:3 ; ///< + UINT32 Reserved_31_27:5 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x208_dct1_STRUCT; + +// **** D18F2x20C_dct0_mp1 Register Definition **** +// Address +#define D18F2x20C_dct0_mp1_ADDRESS 0x20c + +// Type +#define D18F2x20C_dct0_mp1_TYPE TYPE_D18F2_dct0_mp1 +// Field Data +#define D18F2x20C_dct0_mp1_Tcwl_OFFSET 0 +#define D18F2x20C_dct0_mp1_Tcwl_WIDTH 5 +#define D18F2x20C_dct0_mp1_Tcwl_MASK 0x1f +#define D18F2x20C_dct0_mp1_Reserved_7_5_OFFSET 5 +#define D18F2x20C_dct0_mp1_Reserved_7_5_WIDTH 3 +#define D18F2x20C_dct0_mp1_Reserved_7_5_MASK 0xe0 +#define D18F2x20C_dct0_mp1_Twtr_OFFSET 8 +#define D18F2x20C_dct0_mp1_Twtr_WIDTH 4 +#define D18F2x20C_dct0_mp1_Twtr_MASK 0xf00 +#define D18F2x20C_dct0_mp1_Reserved_15_12_OFFSET 12 +#define D18F2x20C_dct0_mp1_Reserved_15_12_WIDTH 4 +#define D18F2x20C_dct0_mp1_Reserved_15_12_MASK 0xf000 +#define D18F2x20C_dct0_mp1_WrDqDqsEarly_OFFSET 16 +#define D18F2x20C_dct0_mp1_WrDqDqsEarly_WIDTH 2 +#define D18F2x20C_dct0_mp1_WrDqDqsEarly_MASK 0x30000 +#define D18F2x20C_dct0_mp1_Reserved_31_18_OFFSET 18 +#define D18F2x20C_dct0_mp1_Reserved_31_18_WIDTH 14 +#define D18F2x20C_dct0_mp1_Reserved_31_18_MASK 0xfffc0000 + +/// D18F2x20C_dct0_mp1 +typedef union { + struct { ///< + UINT32 Tcwl:5 ; ///< + UINT32 Reserved_7_5:3 ; ///< + UINT32 Twtr:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 WrDqDqsEarly:2 ; ///< + UINT32 Reserved_31_18:14; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x20C_dct0_mp1_STRUCT; + +// **** D18F2x20C_dct1_mp1 Register Definition **** +// Address +#define D18F2x20C_dct1_mp1_ADDRESS 0x20c + +// Type +#define D18F2x20C_dct1_mp1_TYPE TYPE_D18F2_dct1_mp1 +// Field Data +#define D18F2x20C_dct1_mp1_Tcwl_OFFSET 0 +#define D18F2x20C_dct1_mp1_Tcwl_WIDTH 5 +#define D18F2x20C_dct1_mp1_Tcwl_MASK 0x1f +#define D18F2x20C_dct1_mp1_Reserved_7_5_OFFSET 5 +#define D18F2x20C_dct1_mp1_Reserved_7_5_WIDTH 3 +#define D18F2x20C_dct1_mp1_Reserved_7_5_MASK 0xe0 +#define D18F2x20C_dct1_mp1_Twtr_OFFSET 8 +#define D18F2x20C_dct1_mp1_Twtr_WIDTH 4 +#define D18F2x20C_dct1_mp1_Twtr_MASK 0xf00 +#define D18F2x20C_dct1_mp1_Reserved_15_12_OFFSET 12 +#define D18F2x20C_dct1_mp1_Reserved_15_12_WIDTH 4 +#define D18F2x20C_dct1_mp1_Reserved_15_12_MASK 0xf000 +#define D18F2x20C_dct1_mp1_WrDqDqsEarly_OFFSET 16 +#define D18F2x20C_dct1_mp1_WrDqDqsEarly_WIDTH 2 +#define D18F2x20C_dct1_mp1_WrDqDqsEarly_MASK 0x30000 +#define D18F2x20C_dct1_mp1_Reserved_31_18_OFFSET 18 +#define D18F2x20C_dct1_mp1_Reserved_31_18_WIDTH 14 +#define D18F2x20C_dct1_mp1_Reserved_31_18_MASK 0xfffc0000 + +/// D18F2x20C_dct1_mp1 +typedef union { + struct { ///< + UINT32 Tcwl:5 ; ///< + UINT32 Reserved_7_5:3 ; ///< + UINT32 Twtr:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 WrDqDqsEarly:2 ; ///< + UINT32 Reserved_31_18:14; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x20C_dct1_mp1_STRUCT; + +// **** D18F2x20C_dct1_mp0 Register Definition **** +// Address +#define D18F2x20C_dct1_mp0_ADDRESS 0x20c + +// Type +#define D18F2x20C_dct1_mp0_TYPE TYPE_D18F2_dct1_mp0 +// Field Data +#define D18F2x20C_dct1_mp0_Tcwl_OFFSET 0 +#define D18F2x20C_dct1_mp0_Tcwl_WIDTH 5 +#define D18F2x20C_dct1_mp0_Tcwl_MASK 0x1f +#define D18F2x20C_dct1_mp0_Reserved_7_5_OFFSET 5 +#define D18F2x20C_dct1_mp0_Reserved_7_5_WIDTH 3 +#define D18F2x20C_dct1_mp0_Reserved_7_5_MASK 0xe0 +#define D18F2x20C_dct1_mp0_Twtr_OFFSET 8 +#define D18F2x20C_dct1_mp0_Twtr_WIDTH 4 +#define D18F2x20C_dct1_mp0_Twtr_MASK 0xf00 +#define D18F2x20C_dct1_mp0_Reserved_15_12_OFFSET 12 +#define D18F2x20C_dct1_mp0_Reserved_15_12_WIDTH 4 +#define D18F2x20C_dct1_mp0_Reserved_15_12_MASK 0xf000 +#define D18F2x20C_dct1_mp0_WrDqDqsEarly_OFFSET 16 +#define D18F2x20C_dct1_mp0_WrDqDqsEarly_WIDTH 2 +#define D18F2x20C_dct1_mp0_WrDqDqsEarly_MASK 0x30000 +#define D18F2x20C_dct1_mp0_Reserved_31_18_OFFSET 18 +#define D18F2x20C_dct1_mp0_Reserved_31_18_WIDTH 14 +#define D18F2x20C_dct1_mp0_Reserved_31_18_MASK 0xfffc0000 + +/// D18F2x20C_dct1_mp0 +typedef union { + struct { ///< + UINT32 Tcwl:5 ; ///< + UINT32 Reserved_7_5:3 ; ///< + UINT32 Twtr:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 WrDqDqsEarly:2 ; ///< + UINT32 Reserved_31_18:14; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x20C_dct1_mp0_STRUCT; + +// **** D18F2x20C_dct0_mp0 Register Definition **** +// Address +#define D18F2x20C_dct0_mp0_ADDRESS 0x20c + +// Type +#define D18F2x20C_dct0_mp0_TYPE TYPE_D18F2_dct0_mp0 +// Field Data +#define D18F2x20C_dct0_mp0_Tcwl_OFFSET 0 +#define D18F2x20C_dct0_mp0_Tcwl_WIDTH 5 +#define D18F2x20C_dct0_mp0_Tcwl_MASK 0x1f +#define D18F2x20C_dct0_mp0_Reserved_7_5_OFFSET 5 +#define D18F2x20C_dct0_mp0_Reserved_7_5_WIDTH 3 +#define D18F2x20C_dct0_mp0_Reserved_7_5_MASK 0xe0 +#define D18F2x20C_dct0_mp0_Twtr_OFFSET 8 +#define D18F2x20C_dct0_mp0_Twtr_WIDTH 4 +#define D18F2x20C_dct0_mp0_Twtr_MASK 0xf00 +#define D18F2x20C_dct0_mp0_Reserved_15_12_OFFSET 12 +#define D18F2x20C_dct0_mp0_Reserved_15_12_WIDTH 4 +#define D18F2x20C_dct0_mp0_Reserved_15_12_MASK 0xf000 +#define D18F2x20C_dct0_mp0_WrDqDqsEarly_OFFSET 16 +#define D18F2x20C_dct0_mp0_WrDqDqsEarly_WIDTH 2 +#define D18F2x20C_dct0_mp0_WrDqDqsEarly_MASK 0x30000 +#define D18F2x20C_dct0_mp0_Reserved_31_18_OFFSET 18 +#define D18F2x20C_dct0_mp0_Reserved_31_18_WIDTH 14 +#define D18F2x20C_dct0_mp0_Reserved_31_18_MASK 0xfffc0000 + +/// D18F2x20C_dct0_mp0 +typedef union { + struct { ///< + UINT32 Tcwl:5 ; ///< + UINT32 Reserved_7_5:3 ; ///< + UINT32 Twtr:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 WrDqDqsEarly:2 ; ///< + UINT32 Reserved_31_18:14; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x20C_dct0_mp0_STRUCT; + +// **** D18F2x210_dct1_nbp0 Register Definition **** +// Address +#define D18F2x210_dct1_nbp0_ADDRESS 0x210 + +// Type +#define D18F2x210_dct1_nbp0_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x210_dct1_nbp0_RdPtrInit_OFFSET 0 +#define D18F2x210_dct1_nbp0_RdPtrInit_WIDTH 4 +#define D18F2x210_dct1_nbp0_RdPtrInit_MASK 0xf +#define D18F2x210_dct1_nbp0_Reserved_15_4_OFFSET 4 +#define D18F2x210_dct1_nbp0_Reserved_15_4_WIDTH 12 +#define D18F2x210_dct1_nbp0_Reserved_15_4_MASK 0xfff0 +#define D18F2x210_dct1_nbp0_DataTxFifoWrDly_OFFSET 16 +#define D18F2x210_dct1_nbp0_DataTxFifoWrDly_WIDTH 3 +#define D18F2x210_dct1_nbp0_DataTxFifoWrDly_MASK 0x70000 +#define D18F2x210_dct1_nbp0_Reserved_21_19_OFFSET 19 +#define D18F2x210_dct1_nbp0_Reserved_21_19_WIDTH 3 +#define D18F2x210_dct1_nbp0_Reserved_21_19_MASK 0x380000 +#define D18F2x210_dct1_nbp0_MaxRdLatency_OFFSET 22 +#define D18F2x210_dct1_nbp0_MaxRdLatency_WIDTH 10 +#define D18F2x210_dct1_nbp0_MaxRdLatency_MASK 0xffc00000 + +/// D18F2x210_dct1_nbp0 +typedef union { + struct { ///< + UINT32 RdPtrInit:4 ; ///< + UINT32 Reserved_15_4:12; ///< + UINT32 DataTxFifoWrDly:3 ; ///< + UINT32 Reserved_21_19:3 ; ///< + UINT32 MaxRdLatency:10; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x210_dct1_nbp0_STRUCT; + +// **** D18F2x210_dct0_nbp2 Register Definition **** +// Address +#define D18F2x210_dct0_nbp2_ADDRESS 0x210 + +// Type +#define D18F2x210_dct0_nbp2_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x210_dct0_nbp2_RdPtrInit_OFFSET 0 +#define D18F2x210_dct0_nbp2_RdPtrInit_WIDTH 4 +#define D18F2x210_dct0_nbp2_RdPtrInit_MASK 0xf +#define D18F2x210_dct0_nbp2_Reserved_15_4_OFFSET 4 +#define D18F2x210_dct0_nbp2_Reserved_15_4_WIDTH 12 +#define D18F2x210_dct0_nbp2_Reserved_15_4_MASK 0xfff0 +#define D18F2x210_dct0_nbp2_DataTxFifoWrDly_OFFSET 16 +#define D18F2x210_dct0_nbp2_DataTxFifoWrDly_WIDTH 3 +#define D18F2x210_dct0_nbp2_DataTxFifoWrDly_MASK 0x70000 +#define D18F2x210_dct0_nbp2_Reserved_21_19_OFFSET 19 +#define D18F2x210_dct0_nbp2_Reserved_21_19_WIDTH 3 +#define D18F2x210_dct0_nbp2_Reserved_21_19_MASK 0x380000 +#define D18F2x210_dct0_nbp2_MaxRdLatency_OFFSET 22 +#define D18F2x210_dct0_nbp2_MaxRdLatency_WIDTH 10 +#define D18F2x210_dct0_nbp2_MaxRdLatency_MASK 0xffc00000 + +/// D18F2x210_dct0_nbp2 +typedef union { + struct { ///< + UINT32 RdPtrInit:4 ; ///< + UINT32 Reserved_15_4:12; ///< + UINT32 DataTxFifoWrDly:3 ; ///< + UINT32 Reserved_21_19:3 ; ///< + UINT32 MaxRdLatency:10; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x210_dct0_nbp2_STRUCT; + +// **** D18F2x210_dct1_nbp1 Register Definition **** +// Address +#define D18F2x210_dct1_nbp1_ADDRESS 0x210 + +// Type +#define D18F2x210_dct1_nbp1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x210_dct1_nbp1_RdPtrInit_OFFSET 0 +#define D18F2x210_dct1_nbp1_RdPtrInit_WIDTH 4 +#define D18F2x210_dct1_nbp1_RdPtrInit_MASK 0xf +#define D18F2x210_dct1_nbp1_Reserved_15_4_OFFSET 4 +#define D18F2x210_dct1_nbp1_Reserved_15_4_WIDTH 12 +#define D18F2x210_dct1_nbp1_Reserved_15_4_MASK 0xfff0 +#define D18F2x210_dct1_nbp1_DataTxFifoWrDly_OFFSET 16 +#define D18F2x210_dct1_nbp1_DataTxFifoWrDly_WIDTH 3 +#define D18F2x210_dct1_nbp1_DataTxFifoWrDly_MASK 0x70000 +#define D18F2x210_dct1_nbp1_Reserved_21_19_OFFSET 19 +#define D18F2x210_dct1_nbp1_Reserved_21_19_WIDTH 3 +#define D18F2x210_dct1_nbp1_Reserved_21_19_MASK 0x380000 +#define D18F2x210_dct1_nbp1_MaxRdLatency_OFFSET 22 +#define D18F2x210_dct1_nbp1_MaxRdLatency_WIDTH 10 +#define D18F2x210_dct1_nbp1_MaxRdLatency_MASK 0xffc00000 + +/// D18F2x210_dct1_nbp1 +typedef union { + struct { ///< + UINT32 RdPtrInit:4 ; ///< + UINT32 Reserved_15_4:12; ///< + UINT32 DataTxFifoWrDly:3 ; ///< + UINT32 Reserved_21_19:3 ; ///< + UINT32 MaxRdLatency:10; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x210_dct1_nbp1_STRUCT; + +// **** D18F2x210_dct1_nbp3 Register Definition **** +// Address +#define D18F2x210_dct1_nbp3_ADDRESS 0x210 + +// Type +#define D18F2x210_dct1_nbp3_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x210_dct1_nbp3_RdPtrInit_OFFSET 0 +#define D18F2x210_dct1_nbp3_RdPtrInit_WIDTH 4 +#define D18F2x210_dct1_nbp3_RdPtrInit_MASK 0xf +#define D18F2x210_dct1_nbp3_Reserved_15_4_OFFSET 4 +#define D18F2x210_dct1_nbp3_Reserved_15_4_WIDTH 12 +#define D18F2x210_dct1_nbp3_Reserved_15_4_MASK 0xfff0 +#define D18F2x210_dct1_nbp3_DataTxFifoWrDly_OFFSET 16 +#define D18F2x210_dct1_nbp3_DataTxFifoWrDly_WIDTH 3 +#define D18F2x210_dct1_nbp3_DataTxFifoWrDly_MASK 0x70000 +#define D18F2x210_dct1_nbp3_Reserved_21_19_OFFSET 19 +#define D18F2x210_dct1_nbp3_Reserved_21_19_WIDTH 3 +#define D18F2x210_dct1_nbp3_Reserved_21_19_MASK 0x380000 +#define D18F2x210_dct1_nbp3_MaxRdLatency_OFFSET 22 +#define D18F2x210_dct1_nbp3_MaxRdLatency_WIDTH 10 +#define D18F2x210_dct1_nbp3_MaxRdLatency_MASK 0xffc00000 + +/// D18F2x210_dct1_nbp3 +typedef union { + struct { ///< + UINT32 RdPtrInit:4 ; ///< + UINT32 Reserved_15_4:12; ///< + UINT32 DataTxFifoWrDly:3 ; ///< + UINT32 Reserved_21_19:3 ; ///< + UINT32 MaxRdLatency:10; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x210_dct1_nbp3_STRUCT; + +// **** D18F2x210_dct0_nbp0 Register Definition **** +// Address +#define D18F2x210_dct0_nbp0_ADDRESS 0x210 + +// Type +#define D18F2x210_dct0_nbp0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x210_dct0_nbp0_RdPtrInit_OFFSET 0 +#define D18F2x210_dct0_nbp0_RdPtrInit_WIDTH 4 +#define D18F2x210_dct0_nbp0_RdPtrInit_MASK 0xf +#define D18F2x210_dct0_nbp0_Reserved_15_4_OFFSET 4 +#define D18F2x210_dct0_nbp0_Reserved_15_4_WIDTH 12 +#define D18F2x210_dct0_nbp0_Reserved_15_4_MASK 0xfff0 +#define D18F2x210_dct0_nbp0_DataTxFifoWrDly_OFFSET 16 +#define D18F2x210_dct0_nbp0_DataTxFifoWrDly_WIDTH 3 +#define D18F2x210_dct0_nbp0_DataTxFifoWrDly_MASK 0x70000 +#define D18F2x210_dct0_nbp0_Reserved_21_19_OFFSET 19 +#define D18F2x210_dct0_nbp0_Reserved_21_19_WIDTH 3 +#define D18F2x210_dct0_nbp0_Reserved_21_19_MASK 0x380000 +#define D18F2x210_dct0_nbp0_MaxRdLatency_OFFSET 22 +#define D18F2x210_dct0_nbp0_MaxRdLatency_WIDTH 10 +#define D18F2x210_dct0_nbp0_MaxRdLatency_MASK 0xffc00000 + +/// D18F2x210_dct0_nbp0 +typedef union { + struct { ///< + UINT32 RdPtrInit:4 ; ///< + UINT32 Reserved_15_4:12; ///< + UINT32 DataTxFifoWrDly:3 ; ///< + UINT32 Reserved_21_19:3 ; ///< + UINT32 MaxRdLatency:10; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x210_dct0_nbp0_STRUCT; + +// **** D18F2x210_dct0_nbp3 Register Definition **** +// Address +#define D18F2x210_dct0_nbp3_ADDRESS 0x210 + +// Type +#define D18F2x210_dct0_nbp3_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x210_dct0_nbp3_RdPtrInit_OFFSET 0 +#define D18F2x210_dct0_nbp3_RdPtrInit_WIDTH 4 +#define D18F2x210_dct0_nbp3_RdPtrInit_MASK 0xf +#define D18F2x210_dct0_nbp3_Reserved_15_4_OFFSET 4 +#define D18F2x210_dct0_nbp3_Reserved_15_4_WIDTH 12 +#define D18F2x210_dct0_nbp3_Reserved_15_4_MASK 0xfff0 +#define D18F2x210_dct0_nbp3_DataTxFifoWrDly_OFFSET 16 +#define D18F2x210_dct0_nbp3_DataTxFifoWrDly_WIDTH 3 +#define D18F2x210_dct0_nbp3_DataTxFifoWrDly_MASK 0x70000 +#define D18F2x210_dct0_nbp3_Reserved_21_19_OFFSET 19 +#define D18F2x210_dct0_nbp3_Reserved_21_19_WIDTH 3 +#define D18F2x210_dct0_nbp3_Reserved_21_19_MASK 0x380000 +#define D18F2x210_dct0_nbp3_MaxRdLatency_OFFSET 22 +#define D18F2x210_dct0_nbp3_MaxRdLatency_WIDTH 10 +#define D18F2x210_dct0_nbp3_MaxRdLatency_MASK 0xffc00000 + +/// D18F2x210_dct0_nbp3 +typedef union { + struct { ///< + UINT32 RdPtrInit:4 ; ///< + UINT32 Reserved_15_4:12; ///< + UINT32 DataTxFifoWrDly:3 ; ///< + UINT32 Reserved_21_19:3 ; ///< + UINT32 MaxRdLatency:10; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x210_dct0_nbp3_STRUCT; + +// **** D18F2x210_dct1_nbp2 Register Definition **** +// Address +#define D18F2x210_dct1_nbp2_ADDRESS 0x210 + +// Type +#define D18F2x210_dct1_nbp2_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x210_dct1_nbp2_RdPtrInit_OFFSET 0 +#define D18F2x210_dct1_nbp2_RdPtrInit_WIDTH 4 +#define D18F2x210_dct1_nbp2_RdPtrInit_MASK 0xf +#define D18F2x210_dct1_nbp2_Reserved_15_4_OFFSET 4 +#define D18F2x210_dct1_nbp2_Reserved_15_4_WIDTH 12 +#define D18F2x210_dct1_nbp2_Reserved_15_4_MASK 0xfff0 +#define D18F2x210_dct1_nbp2_DataTxFifoWrDly_OFFSET 16 +#define D18F2x210_dct1_nbp2_DataTxFifoWrDly_WIDTH 3 +#define D18F2x210_dct1_nbp2_DataTxFifoWrDly_MASK 0x70000 +#define D18F2x210_dct1_nbp2_Reserved_21_19_OFFSET 19 +#define D18F2x210_dct1_nbp2_Reserved_21_19_WIDTH 3 +#define D18F2x210_dct1_nbp2_Reserved_21_19_MASK 0x380000 +#define D18F2x210_dct1_nbp2_MaxRdLatency_OFFSET 22 +#define D18F2x210_dct1_nbp2_MaxRdLatency_WIDTH 10 +#define D18F2x210_dct1_nbp2_MaxRdLatency_MASK 0xffc00000 + +/// D18F2x210_dct1_nbp2 +typedef union { + struct { ///< + UINT32 RdPtrInit:4 ; ///< + UINT32 Reserved_15_4:12; ///< + UINT32 DataTxFifoWrDly:3 ; ///< + UINT32 Reserved_21_19:3 ; ///< + UINT32 MaxRdLatency:10; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x210_dct1_nbp2_STRUCT; + +// **** D18F2x210_dct0_nbp1 Register Definition **** +// Address +#define D18F2x210_dct0_nbp1_ADDRESS 0x210 + +// Type +#define D18F2x210_dct0_nbp1_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x210_dct0_nbp1_RdPtrInit_OFFSET 0 +#define D18F2x210_dct0_nbp1_RdPtrInit_WIDTH 4 +#define D18F2x210_dct0_nbp1_RdPtrInit_MASK 0xf +#define D18F2x210_dct0_nbp1_Reserved_15_4_OFFSET 4 +#define D18F2x210_dct0_nbp1_Reserved_15_4_WIDTH 12 +#define D18F2x210_dct0_nbp1_Reserved_15_4_MASK 0xfff0 +#define D18F2x210_dct0_nbp1_DataTxFifoWrDly_OFFSET 16 +#define D18F2x210_dct0_nbp1_DataTxFifoWrDly_WIDTH 3 +#define D18F2x210_dct0_nbp1_DataTxFifoWrDly_MASK 0x70000 +#define D18F2x210_dct0_nbp1_Reserved_21_19_OFFSET 19 +#define D18F2x210_dct0_nbp1_Reserved_21_19_WIDTH 3 +#define D18F2x210_dct0_nbp1_Reserved_21_19_MASK 0x380000 +#define D18F2x210_dct0_nbp1_MaxRdLatency_OFFSET 22 +#define D18F2x210_dct0_nbp1_MaxRdLatency_WIDTH 10 +#define D18F2x210_dct0_nbp1_MaxRdLatency_MASK 0xffc00000 + +/// D18F2x210_dct0_nbp1 +typedef union { + struct { ///< + UINT32 RdPtrInit:4 ; ///< + UINT32 Reserved_15_4:12; ///< + UINT32 DataTxFifoWrDly:3 ; ///< + UINT32 Reserved_21_19:3 ; ///< + UINT32 MaxRdLatency:10; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x210_dct0_nbp1_STRUCT; + +// **** D18F2x214_dct1_mp1 Register Definition **** +// Address +#define D18F2x214_dct1_mp1_ADDRESS 0x214 + +// Type +#define D18F2x214_dct1_mp1_TYPE TYPE_D18F2_dct1_mp1 +// Field Data +#define D18F2x214_dct1_mp1_TwrwrDd_OFFSET 0 +#define D18F2x214_dct1_mp1_TwrwrDd_WIDTH 4 +#define D18F2x214_dct1_mp1_TwrwrDd_MASK 0xf +#define D18F2x214_dct1_mp1_Reserved_7_4_OFFSET 4 +#define D18F2x214_dct1_mp1_Reserved_7_4_WIDTH 4 +#define D18F2x214_dct1_mp1_Reserved_7_4_MASK 0xf0 +#define D18F2x214_dct1_mp1_TwrwrSdDc_OFFSET 8 +#define D18F2x214_dct1_mp1_TwrwrSdDc_WIDTH 4 +#define D18F2x214_dct1_mp1_TwrwrSdDc_MASK 0xf00 +#define D18F2x214_dct1_mp1_Reserved_15_12_OFFSET 12 +#define D18F2x214_dct1_mp1_Reserved_15_12_WIDTH 4 +#define D18F2x214_dct1_mp1_Reserved_15_12_MASK 0xf000 +#define D18F2x214_dct1_mp1_TwrwrSdSc_OFFSET 16 +#define D18F2x214_dct1_mp1_TwrwrSdSc_WIDTH 4 +#define D18F2x214_dct1_mp1_TwrwrSdSc_MASK 0xf0000 +#define D18F2x214_dct1_mp1_Reserved_31_20_OFFSET 20 +#define D18F2x214_dct1_mp1_Reserved_31_20_WIDTH 12 +#define D18F2x214_dct1_mp1_Reserved_31_20_MASK 0xfff00000 + +/// D18F2x214_dct1_mp1 +typedef union { + struct { ///< + UINT32 TwrwrDd:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 TwrwrSdDc:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 TwrwrSdSc:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x214_dct1_mp1_STRUCT; + +// **** D18F2x214_dct0_mp0 Register Definition **** +// Address +#define D18F2x214_dct0_mp0_ADDRESS 0x214 + +// Type +#define D18F2x214_dct0_mp0_TYPE TYPE_D18F2_dct0_mp0 +// Field Data +#define D18F2x214_dct0_mp0_TwrwrDd_OFFSET 0 +#define D18F2x214_dct0_mp0_TwrwrDd_WIDTH 4 +#define D18F2x214_dct0_mp0_TwrwrDd_MASK 0xf +#define D18F2x214_dct0_mp0_Reserved_7_4_OFFSET 4 +#define D18F2x214_dct0_mp0_Reserved_7_4_WIDTH 4 +#define D18F2x214_dct0_mp0_Reserved_7_4_MASK 0xf0 +#define D18F2x214_dct0_mp0_TwrwrSdDc_OFFSET 8 +#define D18F2x214_dct0_mp0_TwrwrSdDc_WIDTH 4 +#define D18F2x214_dct0_mp0_TwrwrSdDc_MASK 0xf00 +#define D18F2x214_dct0_mp0_Reserved_15_12_OFFSET 12 +#define D18F2x214_dct0_mp0_Reserved_15_12_WIDTH 4 +#define D18F2x214_dct0_mp0_Reserved_15_12_MASK 0xf000 +#define D18F2x214_dct0_mp0_TwrwrSdSc_OFFSET 16 +#define D18F2x214_dct0_mp0_TwrwrSdSc_WIDTH 4 +#define D18F2x214_dct0_mp0_TwrwrSdSc_MASK 0xf0000 +#define D18F2x214_dct0_mp0_Reserved_31_20_OFFSET 20 +#define D18F2x214_dct0_mp0_Reserved_31_20_WIDTH 12 +#define D18F2x214_dct0_mp0_Reserved_31_20_MASK 0xfff00000 + +/// D18F2x214_dct0_mp0 +typedef union { + struct { ///< + UINT32 TwrwrDd:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 TwrwrSdDc:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 TwrwrSdSc:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x214_dct0_mp0_STRUCT; + +// **** D18F2x214_dct1_mp0 Register Definition **** +// Address +#define D18F2x214_dct1_mp0_ADDRESS 0x214 + +// Type +#define D18F2x214_dct1_mp0_TYPE TYPE_D18F2_dct1_mp0 +// Field Data +#define D18F2x214_dct1_mp0_TwrwrDd_OFFSET 0 +#define D18F2x214_dct1_mp0_TwrwrDd_WIDTH 4 +#define D18F2x214_dct1_mp0_TwrwrDd_MASK 0xf +#define D18F2x214_dct1_mp0_Reserved_7_4_OFFSET 4 +#define D18F2x214_dct1_mp0_Reserved_7_4_WIDTH 4 +#define D18F2x214_dct1_mp0_Reserved_7_4_MASK 0xf0 +#define D18F2x214_dct1_mp0_TwrwrSdDc_OFFSET 8 +#define D18F2x214_dct1_mp0_TwrwrSdDc_WIDTH 4 +#define D18F2x214_dct1_mp0_TwrwrSdDc_MASK 0xf00 +#define D18F2x214_dct1_mp0_Reserved_15_12_OFFSET 12 +#define D18F2x214_dct1_mp0_Reserved_15_12_WIDTH 4 +#define D18F2x214_dct1_mp0_Reserved_15_12_MASK 0xf000 +#define D18F2x214_dct1_mp0_TwrwrSdSc_OFFSET 16 +#define D18F2x214_dct1_mp0_TwrwrSdSc_WIDTH 4 +#define D18F2x214_dct1_mp0_TwrwrSdSc_MASK 0xf0000 +#define D18F2x214_dct1_mp0_Reserved_31_20_OFFSET 20 +#define D18F2x214_dct1_mp0_Reserved_31_20_WIDTH 12 +#define D18F2x214_dct1_mp0_Reserved_31_20_MASK 0xfff00000 + +/// D18F2x214_dct1_mp0 +typedef union { + struct { ///< + UINT32 TwrwrDd:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 TwrwrSdDc:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 TwrwrSdSc:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x214_dct1_mp0_STRUCT; + +// **** D18F2x214_dct0_mp1 Register Definition **** +// Address +#define D18F2x214_dct0_mp1_ADDRESS 0x214 + +// Type +#define D18F2x214_dct0_mp1_TYPE TYPE_D18F2_dct0_mp1 +// Field Data +#define D18F2x214_dct0_mp1_TwrwrDd_OFFSET 0 +#define D18F2x214_dct0_mp1_TwrwrDd_WIDTH 4 +#define D18F2x214_dct0_mp1_TwrwrDd_MASK 0xf +#define D18F2x214_dct0_mp1_Reserved_7_4_OFFSET 4 +#define D18F2x214_dct0_mp1_Reserved_7_4_WIDTH 4 +#define D18F2x214_dct0_mp1_Reserved_7_4_MASK 0xf0 +#define D18F2x214_dct0_mp1_TwrwrSdDc_OFFSET 8 +#define D18F2x214_dct0_mp1_TwrwrSdDc_WIDTH 4 +#define D18F2x214_dct0_mp1_TwrwrSdDc_MASK 0xf00 +#define D18F2x214_dct0_mp1_Reserved_15_12_OFFSET 12 +#define D18F2x214_dct0_mp1_Reserved_15_12_WIDTH 4 +#define D18F2x214_dct0_mp1_Reserved_15_12_MASK 0xf000 +#define D18F2x214_dct0_mp1_TwrwrSdSc_OFFSET 16 +#define D18F2x214_dct0_mp1_TwrwrSdSc_WIDTH 4 +#define D18F2x214_dct0_mp1_TwrwrSdSc_MASK 0xf0000 +#define D18F2x214_dct0_mp1_Reserved_31_20_OFFSET 20 +#define D18F2x214_dct0_mp1_Reserved_31_20_WIDTH 12 +#define D18F2x214_dct0_mp1_Reserved_31_20_MASK 0xfff00000 + +/// D18F2x214_dct0_mp1 +typedef union { + struct { ///< + UINT32 TwrwrDd:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 TwrwrSdDc:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 TwrwrSdSc:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x214_dct0_mp1_STRUCT; + +// **** D18F2x218_dct0_mp1 Register Definition **** +// Address +#define D18F2x218_dct0_mp1_ADDRESS 0x218 + +// Type +#define D18F2x218_dct0_mp1_TYPE TYPE_D18F2_dct0_mp1 +// Field Data +#define D18F2x218_dct0_mp1_TrdrdDd_OFFSET 0 +#define D18F2x218_dct0_mp1_TrdrdDd_WIDTH 4 +#define D18F2x218_dct0_mp1_TrdrdDd_MASK 0xf +#define D18F2x218_dct0_mp1_Reserved_7_4_OFFSET 4 +#define D18F2x218_dct0_mp1_Reserved_7_4_WIDTH 4 +#define D18F2x218_dct0_mp1_Reserved_7_4_MASK 0xf0 +#define D18F2x218_dct0_mp1_Twrrd_OFFSET 8 +#define D18F2x218_dct0_mp1_Twrrd_WIDTH 4 +#define D18F2x218_dct0_mp1_Twrrd_MASK 0xf00 +#define D18F2x218_dct0_mp1_Reserved_15_12_OFFSET 12 +#define D18F2x218_dct0_mp1_Reserved_15_12_WIDTH 4 +#define D18F2x218_dct0_mp1_Reserved_15_12_MASK 0xf000 +#define D18F2x218_dct0_mp1_TrdrdSdDc_OFFSET 16 +#define D18F2x218_dct0_mp1_TrdrdSdDc_WIDTH 4 +#define D18F2x218_dct0_mp1_TrdrdSdDc_MASK 0xf0000 +#define D18F2x218_dct0_mp1_Reserved_23_20_OFFSET 20 +#define D18F2x218_dct0_mp1_Reserved_23_20_WIDTH 4 +#define D18F2x218_dct0_mp1_Reserved_23_20_MASK 0xf00000 +#define D18F2x218_dct0_mp1_TrdrdSdSc_OFFSET 24 +#define D18F2x218_dct0_mp1_TrdrdSdSc_WIDTH 4 +#define D18F2x218_dct0_mp1_TrdrdSdSc_MASK 0xf000000 +#define D18F2x218_dct0_mp1_Reserved_31_28_OFFSET 28 +#define D18F2x218_dct0_mp1_Reserved_31_28_WIDTH 4 +#define D18F2x218_dct0_mp1_Reserved_31_28_MASK 0xf0000000 + +/// D18F2x218_dct0_mp1 +typedef union { + struct { ///< + UINT32 TrdrdDd:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 Twrrd:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 TrdrdSdDc:4 ; ///< + UINT32 Reserved_23_20:4 ; ///< + UINT32 TrdrdSdSc:4 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x218_dct0_mp1_STRUCT; + +// **** D18F2x218_dct1_mp1 Register Definition **** +// Address +#define D18F2x218_dct1_mp1_ADDRESS 0x218 + +// Type +#define D18F2x218_dct1_mp1_TYPE TYPE_D18F2_dct1_mp1 +// Field Data +#define D18F2x218_dct1_mp1_TrdrdDd_OFFSET 0 +#define D18F2x218_dct1_mp1_TrdrdDd_WIDTH 4 +#define D18F2x218_dct1_mp1_TrdrdDd_MASK 0xf +#define D18F2x218_dct1_mp1_Reserved_7_4_OFFSET 4 +#define D18F2x218_dct1_mp1_Reserved_7_4_WIDTH 4 +#define D18F2x218_dct1_mp1_Reserved_7_4_MASK 0xf0 +#define D18F2x218_dct1_mp1_Twrrd_OFFSET 8 +#define D18F2x218_dct1_mp1_Twrrd_WIDTH 4 +#define D18F2x218_dct1_mp1_Twrrd_MASK 0xf00 +#define D18F2x218_dct1_mp1_Reserved_15_12_OFFSET 12 +#define D18F2x218_dct1_mp1_Reserved_15_12_WIDTH 4 +#define D18F2x218_dct1_mp1_Reserved_15_12_MASK 0xf000 +#define D18F2x218_dct1_mp1_TrdrdSdDc_OFFSET 16 +#define D18F2x218_dct1_mp1_TrdrdSdDc_WIDTH 4 +#define D18F2x218_dct1_mp1_TrdrdSdDc_MASK 0xf0000 +#define D18F2x218_dct1_mp1_Reserved_23_20_OFFSET 20 +#define D18F2x218_dct1_mp1_Reserved_23_20_WIDTH 4 +#define D18F2x218_dct1_mp1_Reserved_23_20_MASK 0xf00000 +#define D18F2x218_dct1_mp1_TrdrdSdSc_OFFSET 24 +#define D18F2x218_dct1_mp1_TrdrdSdSc_WIDTH 4 +#define D18F2x218_dct1_mp1_TrdrdSdSc_MASK 0xf000000 +#define D18F2x218_dct1_mp1_Reserved_31_28_OFFSET 28 +#define D18F2x218_dct1_mp1_Reserved_31_28_WIDTH 4 +#define D18F2x218_dct1_mp1_Reserved_31_28_MASK 0xf0000000 + +/// D18F2x218_dct1_mp1 +typedef union { + struct { ///< + UINT32 TrdrdDd:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 Twrrd:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 TrdrdSdDc:4 ; ///< + UINT32 Reserved_23_20:4 ; ///< + UINT32 TrdrdSdSc:4 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x218_dct1_mp1_STRUCT; + +// **** D18F2x218_dct0_mp0 Register Definition **** +// Address +#define D18F2x218_dct0_mp0_ADDRESS 0x218 + +// Type +#define D18F2x218_dct0_mp0_TYPE TYPE_D18F2_dct0_mp0 +// Field Data +#define D18F2x218_dct0_mp0_TrdrdDd_OFFSET 0 +#define D18F2x218_dct0_mp0_TrdrdDd_WIDTH 4 +#define D18F2x218_dct0_mp0_TrdrdDd_MASK 0xf +#define D18F2x218_dct0_mp0_Reserved_7_4_OFFSET 4 +#define D18F2x218_dct0_mp0_Reserved_7_4_WIDTH 4 +#define D18F2x218_dct0_mp0_Reserved_7_4_MASK 0xf0 +#define D18F2x218_dct0_mp0_Twrrd_OFFSET 8 +#define D18F2x218_dct0_mp0_Twrrd_WIDTH 4 +#define D18F2x218_dct0_mp0_Twrrd_MASK 0xf00 +#define D18F2x218_dct0_mp0_Reserved_15_12_OFFSET 12 +#define D18F2x218_dct0_mp0_Reserved_15_12_WIDTH 4 +#define D18F2x218_dct0_mp0_Reserved_15_12_MASK 0xf000 +#define D18F2x218_dct0_mp0_TrdrdSdDc_OFFSET 16 +#define D18F2x218_dct0_mp0_TrdrdSdDc_WIDTH 4 +#define D18F2x218_dct0_mp0_TrdrdSdDc_MASK 0xf0000 +#define D18F2x218_dct0_mp0_Reserved_23_20_OFFSET 20 +#define D18F2x218_dct0_mp0_Reserved_23_20_WIDTH 4 +#define D18F2x218_dct0_mp0_Reserved_23_20_MASK 0xf00000 +#define D18F2x218_dct0_mp0_TrdrdSdSc_OFFSET 24 +#define D18F2x218_dct0_mp0_TrdrdSdSc_WIDTH 4 +#define D18F2x218_dct0_mp0_TrdrdSdSc_MASK 0xf000000 +#define D18F2x218_dct0_mp0_Reserved_31_28_OFFSET 28 +#define D18F2x218_dct0_mp0_Reserved_31_28_WIDTH 4 +#define D18F2x218_dct0_mp0_Reserved_31_28_MASK 0xf0000000 + +/// D18F2x218_dct0_mp0 +typedef union { + struct { ///< + UINT32 TrdrdDd:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 Twrrd:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 TrdrdSdDc:4 ; ///< + UINT32 Reserved_23_20:4 ; ///< + UINT32 TrdrdSdSc:4 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x218_dct0_mp0_STRUCT; + +// **** D18F2x218_dct1_mp0 Register Definition **** +// Address +#define D18F2x218_dct1_mp0_ADDRESS 0x218 + +// Type +#define D18F2x218_dct1_mp0_TYPE TYPE_D18F2_dct1_mp0 +// Field Data +#define D18F2x218_dct1_mp0_TrdrdDd_OFFSET 0 +#define D18F2x218_dct1_mp0_TrdrdDd_WIDTH 4 +#define D18F2x218_dct1_mp0_TrdrdDd_MASK 0xf +#define D18F2x218_dct1_mp0_Reserved_7_4_OFFSET 4 +#define D18F2x218_dct1_mp0_Reserved_7_4_WIDTH 4 +#define D18F2x218_dct1_mp0_Reserved_7_4_MASK 0xf0 +#define D18F2x218_dct1_mp0_Twrrd_OFFSET 8 +#define D18F2x218_dct1_mp0_Twrrd_WIDTH 4 +#define D18F2x218_dct1_mp0_Twrrd_MASK 0xf00 +#define D18F2x218_dct1_mp0_Reserved_15_12_OFFSET 12 +#define D18F2x218_dct1_mp0_Reserved_15_12_WIDTH 4 +#define D18F2x218_dct1_mp0_Reserved_15_12_MASK 0xf000 +#define D18F2x218_dct1_mp0_TrdrdSdDc_OFFSET 16 +#define D18F2x218_dct1_mp0_TrdrdSdDc_WIDTH 4 +#define D18F2x218_dct1_mp0_TrdrdSdDc_MASK 0xf0000 +#define D18F2x218_dct1_mp0_Reserved_23_20_OFFSET 20 +#define D18F2x218_dct1_mp0_Reserved_23_20_WIDTH 4 +#define D18F2x218_dct1_mp0_Reserved_23_20_MASK 0xf00000 +#define D18F2x218_dct1_mp0_TrdrdSdSc_OFFSET 24 +#define D18F2x218_dct1_mp0_TrdrdSdSc_WIDTH 4 +#define D18F2x218_dct1_mp0_TrdrdSdSc_MASK 0xf000000 +#define D18F2x218_dct1_mp0_Reserved_31_28_OFFSET 28 +#define D18F2x218_dct1_mp0_Reserved_31_28_WIDTH 4 +#define D18F2x218_dct1_mp0_Reserved_31_28_MASK 0xf0000000 + +/// D18F2x218_dct1_mp0 +typedef union { + struct { ///< + UINT32 TrdrdDd:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 Twrrd:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 TrdrdSdDc:4 ; ///< + UINT32 Reserved_23_20:4 ; ///< + UINT32 TrdrdSdSc:4 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x218_dct1_mp0_STRUCT; + +// **** D18F2x21C_dct1_mp1 Register Definition **** +// Address +#define D18F2x21C_dct1_mp1_ADDRESS 0x21c + +// Type +#define D18F2x21C_dct1_mp1_TYPE TYPE_D18F2_dct1_mp1 +// Field Data +#define D18F2x21C_dct1_mp1_Reserved_7_0_OFFSET 0 +#define D18F2x21C_dct1_mp1_Reserved_7_0_WIDTH 8 +#define D18F2x21C_dct1_mp1_Reserved_7_0_MASK 0xff +#define D18F2x21C_dct1_mp1_TrwtTO_OFFSET 8 +#define D18F2x21C_dct1_mp1_TrwtTO_WIDTH 5 +#define D18F2x21C_dct1_mp1_TrwtTO_MASK 0x1f00 +#define D18F2x21C_dct1_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x21C_dct1_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x21C_dct1_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x21C_dct1_mp1_TrwtWB_OFFSET 16 +#define D18F2x21C_dct1_mp1_TrwtWB_WIDTH 5 +#define D18F2x21C_dct1_mp1_TrwtWB_MASK 0x1f0000 +#define D18F2x21C_dct1_mp1_Reserved_31_21_OFFSET 21 +#define D18F2x21C_dct1_mp1_Reserved_31_21_WIDTH 11 +#define D18F2x21C_dct1_mp1_Reserved_31_21_MASK 0xffe00000 + +/// D18F2x21C_dct1_mp1 +typedef union { + struct { ///< + UINT32 Reserved_7_0:8 ; ///< + UINT32 TrwtTO:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 TrwtWB:5 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x21C_dct1_mp1_STRUCT; + +// **** D18F2x21C_dct1_mp0 Register Definition **** +// Address +#define D18F2x21C_dct1_mp0_ADDRESS 0x21c + +// Type +#define D18F2x21C_dct1_mp0_TYPE TYPE_D18F2_dct1_mp0 +// Field Data +#define D18F2x21C_dct1_mp0_Reserved_7_0_OFFSET 0 +#define D18F2x21C_dct1_mp0_Reserved_7_0_WIDTH 8 +#define D18F2x21C_dct1_mp0_Reserved_7_0_MASK 0xff +#define D18F2x21C_dct1_mp0_TrwtTO_OFFSET 8 +#define D18F2x21C_dct1_mp0_TrwtTO_WIDTH 5 +#define D18F2x21C_dct1_mp0_TrwtTO_MASK 0x1f00 +#define D18F2x21C_dct1_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x21C_dct1_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x21C_dct1_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x21C_dct1_mp0_TrwtWB_OFFSET 16 +#define D18F2x21C_dct1_mp0_TrwtWB_WIDTH 5 +#define D18F2x21C_dct1_mp0_TrwtWB_MASK 0x1f0000 +#define D18F2x21C_dct1_mp0_Reserved_31_21_OFFSET 21 +#define D18F2x21C_dct1_mp0_Reserved_31_21_WIDTH 11 +#define D18F2x21C_dct1_mp0_Reserved_31_21_MASK 0xffe00000 + +/// D18F2x21C_dct1_mp0 +typedef union { + struct { ///< + UINT32 Reserved_7_0:8 ; ///< + UINT32 TrwtTO:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 TrwtWB:5 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x21C_dct1_mp0_STRUCT; + +// **** D18F2x21C_dct0_mp0 Register Definition **** +// Address +#define D18F2x21C_dct0_mp0_ADDRESS 0x21c + +// Type +#define D18F2x21C_dct0_mp0_TYPE TYPE_D18F2_dct0_mp0 +// Field Data +#define D18F2x21C_dct0_mp0_Reserved_7_0_OFFSET 0 +#define D18F2x21C_dct0_mp0_Reserved_7_0_WIDTH 8 +#define D18F2x21C_dct0_mp0_Reserved_7_0_MASK 0xff +#define D18F2x21C_dct0_mp0_TrwtTO_OFFSET 8 +#define D18F2x21C_dct0_mp0_TrwtTO_WIDTH 5 +#define D18F2x21C_dct0_mp0_TrwtTO_MASK 0x1f00 +#define D18F2x21C_dct0_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x21C_dct0_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x21C_dct0_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x21C_dct0_mp0_TrwtWB_OFFSET 16 +#define D18F2x21C_dct0_mp0_TrwtWB_WIDTH 5 +#define D18F2x21C_dct0_mp0_TrwtWB_MASK 0x1f0000 +#define D18F2x21C_dct0_mp0_Reserved_31_21_OFFSET 21 +#define D18F2x21C_dct0_mp0_Reserved_31_21_WIDTH 11 +#define D18F2x21C_dct0_mp0_Reserved_31_21_MASK 0xffe00000 + +/// D18F2x21C_dct0_mp0 +typedef union { + struct { ///< + UINT32 Reserved_7_0:8 ; ///< + UINT32 TrwtTO:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 TrwtWB:5 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x21C_dct0_mp0_STRUCT; + +// **** D18F2x21C_dct0_mp1 Register Definition **** +// Address +#define D18F2x21C_dct0_mp1_ADDRESS 0x21c + +// Type +#define D18F2x21C_dct0_mp1_TYPE TYPE_D18F2_dct0_mp1 +// Field Data +#define D18F2x21C_dct0_mp1_Reserved_7_0_OFFSET 0 +#define D18F2x21C_dct0_mp1_Reserved_7_0_WIDTH 8 +#define D18F2x21C_dct0_mp1_Reserved_7_0_MASK 0xff +#define D18F2x21C_dct0_mp1_TrwtTO_OFFSET 8 +#define D18F2x21C_dct0_mp1_TrwtTO_WIDTH 5 +#define D18F2x21C_dct0_mp1_TrwtTO_MASK 0x1f00 +#define D18F2x21C_dct0_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x21C_dct0_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x21C_dct0_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x21C_dct0_mp1_TrwtWB_OFFSET 16 +#define D18F2x21C_dct0_mp1_TrwtWB_WIDTH 5 +#define D18F2x21C_dct0_mp1_TrwtWB_MASK 0x1f0000 +#define D18F2x21C_dct0_mp1_Reserved_31_21_OFFSET 21 +#define D18F2x21C_dct0_mp1_Reserved_31_21_WIDTH 11 +#define D18F2x21C_dct0_mp1_Reserved_31_21_MASK 0xffe00000 + +/// D18F2x21C_dct0_mp1 +typedef union { + struct { ///< + UINT32 Reserved_7_0:8 ; ///< + UINT32 TrwtTO:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 TrwtWB:5 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x21C_dct0_mp1_STRUCT; + +// **** D18F2x220_dct1 Register Definition **** +// Address +#define D18F2x220_dct1_ADDRESS 0x220 + +// Type +#define D18F2x220_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x220_dct1_Tmrd_OFFSET 0 +#define D18F2x220_dct1_Tmrd_WIDTH 4 +#define D18F2x220_dct1_Tmrd_MASK 0xf +#define D18F2x220_dct1_Reserved_7_4_OFFSET 4 +#define D18F2x220_dct1_Reserved_7_4_WIDTH 4 +#define D18F2x220_dct1_Reserved_7_4_MASK 0xf0 +#define D18F2x220_dct1_Tmod_OFFSET 8 +#define D18F2x220_dct1_Tmod_WIDTH 5 +#define D18F2x220_dct1_Tmod_MASK 0x1f00 +#define D18F2x220_dct1_Reserved_31_13_OFFSET 13 +#define D18F2x220_dct1_Reserved_31_13_WIDTH 19 +#define D18F2x220_dct1_Reserved_31_13_MASK 0xffffe000 + +/// D18F2x220_dct1 +typedef union { + struct { ///< + UINT32 Tmrd:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 Tmod:5 ; ///< + UINT32 Reserved_31_13:19; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x220_dct1_STRUCT; + +// **** D18F2x220_dct0 Register Definition **** +// Address +#define D18F2x220_dct0_ADDRESS 0x220 + +// Type +#define D18F2x220_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x220_dct0_Tmrd_OFFSET 0 +#define D18F2x220_dct0_Tmrd_WIDTH 4 +#define D18F2x220_dct0_Tmrd_MASK 0xf +#define D18F2x220_dct0_Reserved_7_4_OFFSET 4 +#define D18F2x220_dct0_Reserved_7_4_WIDTH 4 +#define D18F2x220_dct0_Reserved_7_4_MASK 0xf0 +#define D18F2x220_dct0_Tmod_OFFSET 8 +#define D18F2x220_dct0_Tmod_WIDTH 5 +#define D18F2x220_dct0_Tmod_MASK 0x1f00 +#define D18F2x220_dct0_Reserved_31_13_OFFSET 13 +#define D18F2x220_dct0_Reserved_31_13_WIDTH 19 +#define D18F2x220_dct0_Reserved_31_13_MASK 0xffffe000 + +/// D18F2x220_dct0 +typedef union { + struct { ///< + UINT32 Tmrd:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 Tmod:5 ; ///< + UINT32 Reserved_31_13:19; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x220_dct0_STRUCT; + +// **** D18F2x224_dct0 Register Definition **** +// Address +#define D18F2x224_dct0_ADDRESS 0x224 + +// Type +#define D18F2x224_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x224_dct0_Tzqoper_OFFSET 0 +#define D18F2x224_dct0_Tzqoper_WIDTH 4 +#define D18F2x224_dct0_Tzqoper_MASK 0xf +#define D18F2x224_dct0_Reserved_7_4_OFFSET 4 +#define D18F2x224_dct0_Reserved_7_4_WIDTH 4 +#define D18F2x224_dct0_Reserved_7_4_MASK 0xf0 +#define D18F2x224_dct0_Tzqcs_OFFSET 8 +#define D18F2x224_dct0_Tzqcs_WIDTH 3 +#define D18F2x224_dct0_Tzqcs_MASK 0x700 +#define D18F2x224_dct0_Reserved_31_11_OFFSET 11 +#define D18F2x224_dct0_Reserved_31_11_WIDTH 21 +#define D18F2x224_dct0_Reserved_31_11_MASK 0xfffff800 + +/// D18F2x224_dct0 +typedef union { + struct { ///< + UINT32 Tzqoper:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 Tzqcs:3 ; ///< + UINT32 Reserved_31_11:21; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x224_dct0_STRUCT; + +// **** D18F2x224_dct1 Register Definition **** +// Address +#define D18F2x224_dct1_ADDRESS 0x224 + +// Type +#define D18F2x224_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x224_dct1_Tzqoper_OFFSET 0 +#define D18F2x224_dct1_Tzqoper_WIDTH 4 +#define D18F2x224_dct1_Tzqoper_MASK 0xf +#define D18F2x224_dct1_Reserved_7_4_OFFSET 4 +#define D18F2x224_dct1_Reserved_7_4_WIDTH 4 +#define D18F2x224_dct1_Reserved_7_4_MASK 0xf0 +#define D18F2x224_dct1_Tzqcs_OFFSET 8 +#define D18F2x224_dct1_Tzqcs_WIDTH 3 +#define D18F2x224_dct1_Tzqcs_MASK 0x700 +#define D18F2x224_dct1_Reserved_31_11_OFFSET 11 +#define D18F2x224_dct1_Reserved_31_11_WIDTH 21 +#define D18F2x224_dct1_Reserved_31_11_MASK 0xfffff800 + +/// D18F2x224_dct1 +typedef union { + struct { ///< + UINT32 Tzqoper:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 Tzqcs:3 ; ///< + UINT32 Reserved_31_11:21; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x224_dct1_STRUCT; + +// **** D18F2x228_dct1 Register Definition **** +// Address +#define D18F2x228_dct1_ADDRESS 0x228 + +// Type +#define D18F2x228_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x228_dct1_Tstag0_OFFSET 0 +#define D18F2x228_dct1_Tstag0_WIDTH 8 +#define D18F2x228_dct1_Tstag0_MASK 0xff +#define D18F2x228_dct1_Tstag1_OFFSET 8 +#define D18F2x228_dct1_Tstag1_WIDTH 8 +#define D18F2x228_dct1_Tstag1_MASK 0xff00 +#define D18F2x228_dct1_Tstag2_OFFSET 16 +#define D18F2x228_dct1_Tstag2_WIDTH 8 +#define D18F2x228_dct1_Tstag2_MASK 0xff0000 +#define D18F2x228_dct1_Tstag3_OFFSET 24 +#define D18F2x228_dct1_Tstag3_WIDTH 8 +#define D18F2x228_dct1_Tstag3_MASK 0xff000000 + +/// D18F2x228_dct1 +typedef union { + struct { ///< + UINT32 Tstag0:8 ; ///< + UINT32 Tstag1:8 ; ///< + UINT32 Tstag2:8 ; ///< + UINT32 Tstag3:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x228_dct1_STRUCT; + +// **** D18F2x228_dct0 Register Definition **** +// Address +#define D18F2x228_dct0_ADDRESS 0x228 + +// Type +#define D18F2x228_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x228_dct0_Tstag0_OFFSET 0 +#define D18F2x228_dct0_Tstag0_WIDTH 8 +#define D18F2x228_dct0_Tstag0_MASK 0xff +#define D18F2x228_dct0_Tstag1_OFFSET 8 +#define D18F2x228_dct0_Tstag1_WIDTH 8 +#define D18F2x228_dct0_Tstag1_MASK 0xff00 +#define D18F2x228_dct0_Tstag2_OFFSET 16 +#define D18F2x228_dct0_Tstag2_WIDTH 8 +#define D18F2x228_dct0_Tstag2_MASK 0xff0000 +#define D18F2x228_dct0_Tstag3_OFFSET 24 +#define D18F2x228_dct0_Tstag3_WIDTH 8 +#define D18F2x228_dct0_Tstag3_MASK 0xff000000 + +/// D18F2x228_dct0 +typedef union { + struct { ///< + UINT32 Tstag0:8 ; ///< + UINT32 Tstag1:8 ; ///< + UINT32 Tstag2:8 ; ///< + UINT32 Tstag3:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x228_dct0_STRUCT; + +// **** D18F2x22C_dct1_mp1 Register Definition **** +// Address +#define D18F2x22C_dct1_mp1_ADDRESS 0x22c + +// Type +#define D18F2x22C_dct1_mp1_TYPE TYPE_D18F2_dct1_mp1 +// Field Data +#define D18F2x22C_dct1_mp1_Twr_OFFSET 0 +#define D18F2x22C_dct1_mp1_Twr_WIDTH 5 +#define D18F2x22C_dct1_mp1_Twr_MASK 0x1f +#define D18F2x22C_dct1_mp1_Reserved_31_5_OFFSET 5 +#define D18F2x22C_dct1_mp1_Reserved_31_5_WIDTH 27 +#define D18F2x22C_dct1_mp1_Reserved_31_5_MASK 0xffffffe0 + +/// D18F2x22C_dct1_mp1 +typedef union { + struct { ///< + UINT32 Twr:5 ; ///< + UINT32 Reserved_31_5:27; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x22C_dct1_mp1_STRUCT; + +// **** D18F2x22C_dct1_mp0 Register Definition **** +// Address +#define D18F2x22C_dct1_mp0_ADDRESS 0x22c + +// Type +#define D18F2x22C_dct1_mp0_TYPE TYPE_D18F2_dct1_mp0 +// Field Data +#define D18F2x22C_dct1_mp0_Twr_OFFSET 0 +#define D18F2x22C_dct1_mp0_Twr_WIDTH 5 +#define D18F2x22C_dct1_mp0_Twr_MASK 0x1f +#define D18F2x22C_dct1_mp0_Reserved_31_5_OFFSET 5 +#define D18F2x22C_dct1_mp0_Reserved_31_5_WIDTH 27 +#define D18F2x22C_dct1_mp0_Reserved_31_5_MASK 0xffffffe0 + +/// D18F2x22C_dct1_mp0 +typedef union { + struct { ///< + UINT32 Twr:5 ; ///< + UINT32 Reserved_31_5:27; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x22C_dct1_mp0_STRUCT; + +// **** D18F2x22C_dct0_mp0 Register Definition **** +// Address +#define D18F2x22C_dct0_mp0_ADDRESS 0x22c + +// Type +#define D18F2x22C_dct0_mp0_TYPE TYPE_D18F2_dct0_mp0 +// Field Data +#define D18F2x22C_dct0_mp0_Twr_OFFSET 0 +#define D18F2x22C_dct0_mp0_Twr_WIDTH 5 +#define D18F2x22C_dct0_mp0_Twr_MASK 0x1f +#define D18F2x22C_dct0_mp0_Reserved_31_5_OFFSET 5 +#define D18F2x22C_dct0_mp0_Reserved_31_5_WIDTH 27 +#define D18F2x22C_dct0_mp0_Reserved_31_5_MASK 0xffffffe0 + +/// D18F2x22C_dct0_mp0 +typedef union { + struct { ///< + UINT32 Twr:5 ; ///< + UINT32 Reserved_31_5:27; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x22C_dct0_mp0_STRUCT; + +// **** D18F2x22C_dct0_mp1 Register Definition **** +// Address +#define D18F2x22C_dct0_mp1_ADDRESS 0x22c + +// Type +#define D18F2x22C_dct0_mp1_TYPE TYPE_D18F2_dct0_mp1 +// Field Data +#define D18F2x22C_dct0_mp1_Twr_OFFSET 0 +#define D18F2x22C_dct0_mp1_Twr_WIDTH 5 +#define D18F2x22C_dct0_mp1_Twr_MASK 0x1f +#define D18F2x22C_dct0_mp1_Reserved_31_5_OFFSET 5 +#define D18F2x22C_dct0_mp1_Reserved_31_5_WIDTH 27 +#define D18F2x22C_dct0_mp1_Reserved_31_5_MASK 0xffffffe0 + +/// D18F2x22C_dct0_mp1 +typedef union { + struct { ///< + UINT32 Twr:5 ; ///< + UINT32 Reserved_31_5:27; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x22C_dct0_mp1_STRUCT; + +// **** D18F2x230_dct0 Register Definition **** +// Address +#define D18F2x230_dct0_ADDRESS 0x230 + +// Type +#define D18F2x230_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x230_dct0_RdOdtPatCs40_OFFSET 0 +#define D18F2x230_dct0_RdOdtPatCs40_WIDTH 4 +#define D18F2x230_dct0_RdOdtPatCs40_MASK 0xf +#define D18F2x230_dct0_Reserved_7_4_OFFSET 4 +#define D18F2x230_dct0_Reserved_7_4_WIDTH 4 +#define D18F2x230_dct0_Reserved_7_4_MASK 0xf0 +#define D18F2x230_dct0_RdOdtPatCs51_OFFSET 8 +#define D18F2x230_dct0_RdOdtPatCs51_WIDTH 4 +#define D18F2x230_dct0_RdOdtPatCs51_MASK 0xf00 +#define D18F2x230_dct0_Reserved_15_12_OFFSET 12 +#define D18F2x230_dct0_Reserved_15_12_WIDTH 4 +#define D18F2x230_dct0_Reserved_15_12_MASK 0xf000 +#define D18F2x230_dct0_RdOdtPatCs62_OFFSET 16 +#define D18F2x230_dct0_RdOdtPatCs62_WIDTH 4 +#define D18F2x230_dct0_RdOdtPatCs62_MASK 0xf0000 +#define D18F2x230_dct0_Reserved_23_20_OFFSET 20 +#define D18F2x230_dct0_Reserved_23_20_WIDTH 4 +#define D18F2x230_dct0_Reserved_23_20_MASK 0xf00000 +#define D18F2x230_dct0_RdOdtPatCs73_OFFSET 24 +#define D18F2x230_dct0_RdOdtPatCs73_WIDTH 4 +#define D18F2x230_dct0_RdOdtPatCs73_MASK 0xf000000 +#define D18F2x230_dct0_Reserved_31_28_OFFSET 28 +#define D18F2x230_dct0_Reserved_31_28_WIDTH 4 +#define D18F2x230_dct0_Reserved_31_28_MASK 0xf0000000 + +/// D18F2x230_dct0 +typedef union { + struct { ///< + UINT32 RdOdtPatCs40:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 RdOdtPatCs51:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 RdOdtPatCs62:4 ; ///< + UINT32 Reserved_23_20:4 ; ///< + UINT32 RdOdtPatCs73:4 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x230_dct0_STRUCT; + +// **** D18F2x230_dct1 Register Definition **** +// Address +#define D18F2x230_dct1_ADDRESS 0x230 + +// Type +#define D18F2x230_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x230_dct1_RdOdtPatCs40_OFFSET 0 +#define D18F2x230_dct1_RdOdtPatCs40_WIDTH 4 +#define D18F2x230_dct1_RdOdtPatCs40_MASK 0xf +#define D18F2x230_dct1_Reserved_7_4_OFFSET 4 +#define D18F2x230_dct1_Reserved_7_4_WIDTH 4 +#define D18F2x230_dct1_Reserved_7_4_MASK 0xf0 +#define D18F2x230_dct1_RdOdtPatCs51_OFFSET 8 +#define D18F2x230_dct1_RdOdtPatCs51_WIDTH 4 +#define D18F2x230_dct1_RdOdtPatCs51_MASK 0xf00 +#define D18F2x230_dct1_Reserved_15_12_OFFSET 12 +#define D18F2x230_dct1_Reserved_15_12_WIDTH 4 +#define D18F2x230_dct1_Reserved_15_12_MASK 0xf000 +#define D18F2x230_dct1_RdOdtPatCs62_OFFSET 16 +#define D18F2x230_dct1_RdOdtPatCs62_WIDTH 4 +#define D18F2x230_dct1_RdOdtPatCs62_MASK 0xf0000 +#define D18F2x230_dct1_Reserved_23_20_OFFSET 20 +#define D18F2x230_dct1_Reserved_23_20_WIDTH 4 +#define D18F2x230_dct1_Reserved_23_20_MASK 0xf00000 +#define D18F2x230_dct1_RdOdtPatCs73_OFFSET 24 +#define D18F2x230_dct1_RdOdtPatCs73_WIDTH 4 +#define D18F2x230_dct1_RdOdtPatCs73_MASK 0xf000000 +#define D18F2x230_dct1_Reserved_31_28_OFFSET 28 +#define D18F2x230_dct1_Reserved_31_28_WIDTH 4 +#define D18F2x230_dct1_Reserved_31_28_MASK 0xf0000000 + +/// D18F2x230_dct1 +typedef union { + struct { ///< + UINT32 RdOdtPatCs40:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 RdOdtPatCs51:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 RdOdtPatCs62:4 ; ///< + UINT32 Reserved_23_20:4 ; ///< + UINT32 RdOdtPatCs73:4 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x230_dct1_STRUCT; + +// **** D18F2x234_dct1 Register Definition **** +// Address +#define D18F2x234_dct1_ADDRESS 0x234 + +// Type +#define D18F2x234_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x234_dct1_RdOdtPatCs40_OFFSET 0 +#define D18F2x234_dct1_RdOdtPatCs40_WIDTH 4 +#define D18F2x234_dct1_RdOdtPatCs40_MASK 0xf +#define D18F2x234_dct1_Reserved_7_4_OFFSET 4 +#define D18F2x234_dct1_Reserved_7_4_WIDTH 4 +#define D18F2x234_dct1_Reserved_7_4_MASK 0xf0 +#define D18F2x234_dct1_RdOdtPatCs51_OFFSET 8 +#define D18F2x234_dct1_RdOdtPatCs51_WIDTH 4 +#define D18F2x234_dct1_RdOdtPatCs51_MASK 0xf00 +#define D18F2x234_dct1_Reserved_15_12_OFFSET 12 +#define D18F2x234_dct1_Reserved_15_12_WIDTH 4 +#define D18F2x234_dct1_Reserved_15_12_MASK 0xf000 +#define D18F2x234_dct1_RdOdtPatCs62_OFFSET 16 +#define D18F2x234_dct1_RdOdtPatCs62_WIDTH 4 +#define D18F2x234_dct1_RdOdtPatCs62_MASK 0xf0000 +#define D18F2x234_dct1_Reserved_23_20_OFFSET 20 +#define D18F2x234_dct1_Reserved_23_20_WIDTH 4 +#define D18F2x234_dct1_Reserved_23_20_MASK 0xf00000 +#define D18F2x234_dct1_RdOdtPatCs73_OFFSET 24 +#define D18F2x234_dct1_RdOdtPatCs73_WIDTH 4 +#define D18F2x234_dct1_RdOdtPatCs73_MASK 0xf000000 +#define D18F2x234_dct1_Reserved_31_28_OFFSET 28 +#define D18F2x234_dct1_Reserved_31_28_WIDTH 4 +#define D18F2x234_dct1_Reserved_31_28_MASK 0xf0000000 + +/// D18F2x234_dct1 +typedef union { + struct { ///< + UINT32 RdOdtPatCs40:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 RdOdtPatCs51:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 RdOdtPatCs62:4 ; ///< + UINT32 Reserved_23_20:4 ; ///< + UINT32 RdOdtPatCs73:4 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x234_dct1_STRUCT; + +// **** D18F2x234_dct0 Register Definition **** +// Address +#define D18F2x234_dct0_ADDRESS 0x234 + +// Type +#define D18F2x234_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x234_dct0_RdOdtPatCs40_OFFSET 0 +#define D18F2x234_dct0_RdOdtPatCs40_WIDTH 4 +#define D18F2x234_dct0_RdOdtPatCs40_MASK 0xf +#define D18F2x234_dct0_Reserved_7_4_OFFSET 4 +#define D18F2x234_dct0_Reserved_7_4_WIDTH 4 +#define D18F2x234_dct0_Reserved_7_4_MASK 0xf0 +#define D18F2x234_dct0_RdOdtPatCs51_OFFSET 8 +#define D18F2x234_dct0_RdOdtPatCs51_WIDTH 4 +#define D18F2x234_dct0_RdOdtPatCs51_MASK 0xf00 +#define D18F2x234_dct0_Reserved_15_12_OFFSET 12 +#define D18F2x234_dct0_Reserved_15_12_WIDTH 4 +#define D18F2x234_dct0_Reserved_15_12_MASK 0xf000 +#define D18F2x234_dct0_RdOdtPatCs62_OFFSET 16 +#define D18F2x234_dct0_RdOdtPatCs62_WIDTH 4 +#define D18F2x234_dct0_RdOdtPatCs62_MASK 0xf0000 +#define D18F2x234_dct0_Reserved_23_20_OFFSET 20 +#define D18F2x234_dct0_Reserved_23_20_WIDTH 4 +#define D18F2x234_dct0_Reserved_23_20_MASK 0xf00000 +#define D18F2x234_dct0_RdOdtPatCs73_OFFSET 24 +#define D18F2x234_dct0_RdOdtPatCs73_WIDTH 4 +#define D18F2x234_dct0_RdOdtPatCs73_MASK 0xf000000 +#define D18F2x234_dct0_Reserved_31_28_OFFSET 28 +#define D18F2x234_dct0_Reserved_31_28_WIDTH 4 +#define D18F2x234_dct0_Reserved_31_28_MASK 0xf0000000 + +/// D18F2x234_dct0 +typedef union { + struct { ///< + UINT32 RdOdtPatCs40:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 RdOdtPatCs51:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 RdOdtPatCs62:4 ; ///< + UINT32 Reserved_23_20:4 ; ///< + UINT32 RdOdtPatCs73:4 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x234_dct0_STRUCT; + +// **** D18F2x238_dct1 Register Definition **** +// Address +#define D18F2x238_dct1_ADDRESS 0x238 + +// Type +#define D18F2x238_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x238_dct1_WrOdtPatCs40_OFFSET 0 +#define D18F2x238_dct1_WrOdtPatCs40_WIDTH 4 +#define D18F2x238_dct1_WrOdtPatCs40_MASK 0xf +#define D18F2x238_dct1_Reserved_7_4_OFFSET 4 +#define D18F2x238_dct1_Reserved_7_4_WIDTH 4 +#define D18F2x238_dct1_Reserved_7_4_MASK 0xf0 +#define D18F2x238_dct1_WrOdtPatCs51_OFFSET 8 +#define D18F2x238_dct1_WrOdtPatCs51_WIDTH 4 +#define D18F2x238_dct1_WrOdtPatCs51_MASK 0xf00 +#define D18F2x238_dct1_Reserved_15_12_OFFSET 12 +#define D18F2x238_dct1_Reserved_15_12_WIDTH 4 +#define D18F2x238_dct1_Reserved_15_12_MASK 0xf000 +#define D18F2x238_dct1_WrOdtPatCs62_OFFSET 16 +#define D18F2x238_dct1_WrOdtPatCs62_WIDTH 4 +#define D18F2x238_dct1_WrOdtPatCs62_MASK 0xf0000 +#define D18F2x238_dct1_Reserved_23_20_OFFSET 20 +#define D18F2x238_dct1_Reserved_23_20_WIDTH 4 +#define D18F2x238_dct1_Reserved_23_20_MASK 0xf00000 +#define D18F2x238_dct1_WrOdtPatCs73_OFFSET 24 +#define D18F2x238_dct1_WrOdtPatCs73_WIDTH 4 +#define D18F2x238_dct1_WrOdtPatCs73_MASK 0xf000000 +#define D18F2x238_dct1_Reserved_31_28_OFFSET 28 +#define D18F2x238_dct1_Reserved_31_28_WIDTH 4 +#define D18F2x238_dct1_Reserved_31_28_MASK 0xf0000000 + +/// D18F2x238_dct1 +typedef union { + struct { ///< + UINT32 WrOdtPatCs40:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 WrOdtPatCs51:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 WrOdtPatCs62:4 ; ///< + UINT32 Reserved_23_20:4 ; ///< + UINT32 WrOdtPatCs73:4 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x238_dct1_STRUCT; + +// **** D18F2x238_dct0 Register Definition **** +// Address +#define D18F2x238_dct0_ADDRESS 0x238 + +// Type +#define D18F2x238_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x238_dct0_WrOdtPatCs40_OFFSET 0 +#define D18F2x238_dct0_WrOdtPatCs40_WIDTH 4 +#define D18F2x238_dct0_WrOdtPatCs40_MASK 0xf +#define D18F2x238_dct0_Reserved_7_4_OFFSET 4 +#define D18F2x238_dct0_Reserved_7_4_WIDTH 4 +#define D18F2x238_dct0_Reserved_7_4_MASK 0xf0 +#define D18F2x238_dct0_WrOdtPatCs51_OFFSET 8 +#define D18F2x238_dct0_WrOdtPatCs51_WIDTH 4 +#define D18F2x238_dct0_WrOdtPatCs51_MASK 0xf00 +#define D18F2x238_dct0_Reserved_15_12_OFFSET 12 +#define D18F2x238_dct0_Reserved_15_12_WIDTH 4 +#define D18F2x238_dct0_Reserved_15_12_MASK 0xf000 +#define D18F2x238_dct0_WrOdtPatCs62_OFFSET 16 +#define D18F2x238_dct0_WrOdtPatCs62_WIDTH 4 +#define D18F2x238_dct0_WrOdtPatCs62_MASK 0xf0000 +#define D18F2x238_dct0_Reserved_23_20_OFFSET 20 +#define D18F2x238_dct0_Reserved_23_20_WIDTH 4 +#define D18F2x238_dct0_Reserved_23_20_MASK 0xf00000 +#define D18F2x238_dct0_WrOdtPatCs73_OFFSET 24 +#define D18F2x238_dct0_WrOdtPatCs73_WIDTH 4 +#define D18F2x238_dct0_WrOdtPatCs73_MASK 0xf000000 +#define D18F2x238_dct0_Reserved_31_28_OFFSET 28 +#define D18F2x238_dct0_Reserved_31_28_WIDTH 4 +#define D18F2x238_dct0_Reserved_31_28_MASK 0xf0000000 + +/// D18F2x238_dct0 +typedef union { + struct { ///< + UINT32 WrOdtPatCs40:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 WrOdtPatCs51:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 WrOdtPatCs62:4 ; ///< + UINT32 Reserved_23_20:4 ; ///< + UINT32 WrOdtPatCs73:4 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x238_dct0_STRUCT; + +// **** D18F2x23C_dct0 Register Definition **** +// Address +#define D18F2x23C_dct0_ADDRESS 0x23c + +// Type +#define D18F2x23C_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x23C_dct0_WrOdtPatCs40_OFFSET 0 +#define D18F2x23C_dct0_WrOdtPatCs40_WIDTH 4 +#define D18F2x23C_dct0_WrOdtPatCs40_MASK 0xf +#define D18F2x23C_dct0_Reserved_7_4_OFFSET 4 +#define D18F2x23C_dct0_Reserved_7_4_WIDTH 4 +#define D18F2x23C_dct0_Reserved_7_4_MASK 0xf0 +#define D18F2x23C_dct0_WrOdtPatCs51_OFFSET 8 +#define D18F2x23C_dct0_WrOdtPatCs51_WIDTH 4 +#define D18F2x23C_dct0_WrOdtPatCs51_MASK 0xf00 +#define D18F2x23C_dct0_Reserved_15_12_OFFSET 12 +#define D18F2x23C_dct0_Reserved_15_12_WIDTH 4 +#define D18F2x23C_dct0_Reserved_15_12_MASK 0xf000 +#define D18F2x23C_dct0_WrOdtPatCs62_OFFSET 16 +#define D18F2x23C_dct0_WrOdtPatCs62_WIDTH 4 +#define D18F2x23C_dct0_WrOdtPatCs62_MASK 0xf0000 +#define D18F2x23C_dct0_Reserved_23_20_OFFSET 20 +#define D18F2x23C_dct0_Reserved_23_20_WIDTH 4 +#define D18F2x23C_dct0_Reserved_23_20_MASK 0xf00000 +#define D18F2x23C_dct0_WrOdtPatCs73_OFFSET 24 +#define D18F2x23C_dct0_WrOdtPatCs73_WIDTH 4 +#define D18F2x23C_dct0_WrOdtPatCs73_MASK 0xf000000 +#define D18F2x23C_dct0_Reserved_31_28_OFFSET 28 +#define D18F2x23C_dct0_Reserved_31_28_WIDTH 4 +#define D18F2x23C_dct0_Reserved_31_28_MASK 0xf0000000 + +/// D18F2x23C_dct0 +typedef union { + struct { ///< + UINT32 WrOdtPatCs40:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 WrOdtPatCs51:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 WrOdtPatCs62:4 ; ///< + UINT32 Reserved_23_20:4 ; ///< + UINT32 WrOdtPatCs73:4 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x23C_dct0_STRUCT; + +// **** D18F2x23C_dct1 Register Definition **** +// Address +#define D18F2x23C_dct1_ADDRESS 0x23c + +// Type +#define D18F2x23C_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x23C_dct1_WrOdtPatCs40_OFFSET 0 +#define D18F2x23C_dct1_WrOdtPatCs40_WIDTH 4 +#define D18F2x23C_dct1_WrOdtPatCs40_MASK 0xf +#define D18F2x23C_dct1_Reserved_7_4_OFFSET 4 +#define D18F2x23C_dct1_Reserved_7_4_WIDTH 4 +#define D18F2x23C_dct1_Reserved_7_4_MASK 0xf0 +#define D18F2x23C_dct1_WrOdtPatCs51_OFFSET 8 +#define D18F2x23C_dct1_WrOdtPatCs51_WIDTH 4 +#define D18F2x23C_dct1_WrOdtPatCs51_MASK 0xf00 +#define D18F2x23C_dct1_Reserved_15_12_OFFSET 12 +#define D18F2x23C_dct1_Reserved_15_12_WIDTH 4 +#define D18F2x23C_dct1_Reserved_15_12_MASK 0xf000 +#define D18F2x23C_dct1_WrOdtPatCs62_OFFSET 16 +#define D18F2x23C_dct1_WrOdtPatCs62_WIDTH 4 +#define D18F2x23C_dct1_WrOdtPatCs62_MASK 0xf0000 +#define D18F2x23C_dct1_Reserved_23_20_OFFSET 20 +#define D18F2x23C_dct1_Reserved_23_20_WIDTH 4 +#define D18F2x23C_dct1_Reserved_23_20_MASK 0xf00000 +#define D18F2x23C_dct1_WrOdtPatCs73_OFFSET 24 +#define D18F2x23C_dct1_WrOdtPatCs73_WIDTH 4 +#define D18F2x23C_dct1_WrOdtPatCs73_MASK 0xf000000 +#define D18F2x23C_dct1_Reserved_31_28_OFFSET 28 +#define D18F2x23C_dct1_Reserved_31_28_WIDTH 4 +#define D18F2x23C_dct1_Reserved_31_28_MASK 0xf0000000 + +/// D18F2x23C_dct1 +typedef union { + struct { ///< + UINT32 WrOdtPatCs40:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 WrOdtPatCs51:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 WrOdtPatCs62:4 ; ///< + UINT32 Reserved_23_20:4 ; ///< + UINT32 WrOdtPatCs73:4 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x23C_dct1_STRUCT; + +// **** D18F2x240_dct0_mp1 Register Definition **** +// Address +#define D18F2x240_dct0_mp1_ADDRESS 0x240 + +// Type +#define D18F2x240_dct0_mp1_TYPE TYPE_D18F2_dct0_mp1 +// Field Data +#define D18F2x240_dct0_mp1_RdOdtTrnOnDly_OFFSET 0 +#define D18F2x240_dct0_mp1_RdOdtTrnOnDly_WIDTH 4 +#define D18F2x240_dct0_mp1_RdOdtTrnOnDly_MASK 0xf +#define D18F2x240_dct0_mp1_RdOdtOnDuration_OFFSET 4 +#define D18F2x240_dct0_mp1_RdOdtOnDuration_WIDTH 3 +#define D18F2x240_dct0_mp1_RdOdtOnDuration_MASK 0x70 +#define D18F2x240_dct0_mp1_Reserved_7_7_OFFSET 7 +#define D18F2x240_dct0_mp1_Reserved_7_7_WIDTH 1 +#define D18F2x240_dct0_mp1_Reserved_7_7_MASK 0x80 +#define D18F2x240_dct0_mp1_WrOdtTrnOnDly_OFFSET 8 +#define D18F2x240_dct0_mp1_WrOdtTrnOnDly_WIDTH 3 +#define D18F2x240_dct0_mp1_WrOdtTrnOnDly_MASK 0x700 +#define D18F2x240_dct0_mp1_Reserved_11_11_OFFSET 11 +#define D18F2x240_dct0_mp1_Reserved_11_11_WIDTH 1 +#define D18F2x240_dct0_mp1_Reserved_11_11_MASK 0x800 +#define D18F2x240_dct0_mp1_WrOdtOnDuration_OFFSET 12 +#define D18F2x240_dct0_mp1_WrOdtOnDuration_WIDTH 3 +#define D18F2x240_dct0_mp1_WrOdtOnDuration_MASK 0x7000 +#define D18F2x240_dct0_mp1_Reserved_31_15_OFFSET 15 +#define D18F2x240_dct0_mp1_Reserved_31_15_WIDTH 17 +#define D18F2x240_dct0_mp1_Reserved_31_15_MASK 0xffff8000 + +/// D18F2x240_dct0_mp1 +typedef union { + struct { ///< + UINT32 RdOdtTrnOnDly:4 ; ///< + UINT32 RdOdtOnDuration:3 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 WrOdtTrnOnDly:3 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 WrOdtOnDuration:3 ; ///< + UINT32 Reserved_31_15:17; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x240_dct0_mp1_STRUCT; + +// **** D18F2x240_dct1_mp0 Register Definition **** +// Address +#define D18F2x240_dct1_mp0_ADDRESS 0x240 + +// Type +#define D18F2x240_dct1_mp0_TYPE TYPE_D18F2_dct1_mp0 +// Field Data +#define D18F2x240_dct1_mp0_RdOdtTrnOnDly_OFFSET 0 +#define D18F2x240_dct1_mp0_RdOdtTrnOnDly_WIDTH 4 +#define D18F2x240_dct1_mp0_RdOdtTrnOnDly_MASK 0xf +#define D18F2x240_dct1_mp0_RdOdtOnDuration_OFFSET 4 +#define D18F2x240_dct1_mp0_RdOdtOnDuration_WIDTH 3 +#define D18F2x240_dct1_mp0_RdOdtOnDuration_MASK 0x70 +#define D18F2x240_dct1_mp0_Reserved_7_7_OFFSET 7 +#define D18F2x240_dct1_mp0_Reserved_7_7_WIDTH 1 +#define D18F2x240_dct1_mp0_Reserved_7_7_MASK 0x80 +#define D18F2x240_dct1_mp0_WrOdtTrnOnDly_OFFSET 8 +#define D18F2x240_dct1_mp0_WrOdtTrnOnDly_WIDTH 3 +#define D18F2x240_dct1_mp0_WrOdtTrnOnDly_MASK 0x700 +#define D18F2x240_dct1_mp0_Reserved_11_11_OFFSET 11 +#define D18F2x240_dct1_mp0_Reserved_11_11_WIDTH 1 +#define D18F2x240_dct1_mp0_Reserved_11_11_MASK 0x800 +#define D18F2x240_dct1_mp0_WrOdtOnDuration_OFFSET 12 +#define D18F2x240_dct1_mp0_WrOdtOnDuration_WIDTH 3 +#define D18F2x240_dct1_mp0_WrOdtOnDuration_MASK 0x7000 +#define D18F2x240_dct1_mp0_Reserved_31_15_OFFSET 15 +#define D18F2x240_dct1_mp0_Reserved_31_15_WIDTH 17 +#define D18F2x240_dct1_mp0_Reserved_31_15_MASK 0xffff8000 + +/// D18F2x240_dct1_mp0 +typedef union { + struct { ///< + UINT32 RdOdtTrnOnDly:4 ; ///< + UINT32 RdOdtOnDuration:3 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 WrOdtTrnOnDly:3 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 WrOdtOnDuration:3 ; ///< + UINT32 Reserved_31_15:17; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x240_dct1_mp0_STRUCT; + +// **** D18F2x240_dct0_mp0 Register Definition **** +// Address +#define D18F2x240_dct0_mp0_ADDRESS 0x240 + +// Type +#define D18F2x240_dct0_mp0_TYPE TYPE_D18F2_dct0_mp0 +// Field Data +#define D18F2x240_dct0_mp0_RdOdtTrnOnDly_OFFSET 0 +#define D18F2x240_dct0_mp0_RdOdtTrnOnDly_WIDTH 4 +#define D18F2x240_dct0_mp0_RdOdtTrnOnDly_MASK 0xf +#define D18F2x240_dct0_mp0_RdOdtOnDuration_OFFSET 4 +#define D18F2x240_dct0_mp0_RdOdtOnDuration_WIDTH 3 +#define D18F2x240_dct0_mp0_RdOdtOnDuration_MASK 0x70 +#define D18F2x240_dct0_mp0_Reserved_7_7_OFFSET 7 +#define D18F2x240_dct0_mp0_Reserved_7_7_WIDTH 1 +#define D18F2x240_dct0_mp0_Reserved_7_7_MASK 0x80 +#define D18F2x240_dct0_mp0_WrOdtTrnOnDly_OFFSET 8 +#define D18F2x240_dct0_mp0_WrOdtTrnOnDly_WIDTH 3 +#define D18F2x240_dct0_mp0_WrOdtTrnOnDly_MASK 0x700 +#define D18F2x240_dct0_mp0_Reserved_11_11_OFFSET 11 +#define D18F2x240_dct0_mp0_Reserved_11_11_WIDTH 1 +#define D18F2x240_dct0_mp0_Reserved_11_11_MASK 0x800 +#define D18F2x240_dct0_mp0_WrOdtOnDuration_OFFSET 12 +#define D18F2x240_dct0_mp0_WrOdtOnDuration_WIDTH 3 +#define D18F2x240_dct0_mp0_WrOdtOnDuration_MASK 0x7000 +#define D18F2x240_dct0_mp0_Reserved_31_15_OFFSET 15 +#define D18F2x240_dct0_mp0_Reserved_31_15_WIDTH 17 +#define D18F2x240_dct0_mp0_Reserved_31_15_MASK 0xffff8000 + +/// D18F2x240_dct0_mp0 +typedef union { + struct { ///< + UINT32 RdOdtTrnOnDly:4 ; ///< + UINT32 RdOdtOnDuration:3 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 WrOdtTrnOnDly:3 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 WrOdtOnDuration:3 ; ///< + UINT32 Reserved_31_15:17; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x240_dct0_mp0_STRUCT; + +// **** D18F2x240_dct1_mp1 Register Definition **** +// Address +#define D18F2x240_dct1_mp1_ADDRESS 0x240 + +// Type +#define D18F2x240_dct1_mp1_TYPE TYPE_D18F2_dct1_mp1 +// Field Data +#define D18F2x240_dct1_mp1_RdOdtTrnOnDly_OFFSET 0 +#define D18F2x240_dct1_mp1_RdOdtTrnOnDly_WIDTH 4 +#define D18F2x240_dct1_mp1_RdOdtTrnOnDly_MASK 0xf +#define D18F2x240_dct1_mp1_RdOdtOnDuration_OFFSET 4 +#define D18F2x240_dct1_mp1_RdOdtOnDuration_WIDTH 3 +#define D18F2x240_dct1_mp1_RdOdtOnDuration_MASK 0x70 +#define D18F2x240_dct1_mp1_Reserved_7_7_OFFSET 7 +#define D18F2x240_dct1_mp1_Reserved_7_7_WIDTH 1 +#define D18F2x240_dct1_mp1_Reserved_7_7_MASK 0x80 +#define D18F2x240_dct1_mp1_WrOdtTrnOnDly_OFFSET 8 +#define D18F2x240_dct1_mp1_WrOdtTrnOnDly_WIDTH 3 +#define D18F2x240_dct1_mp1_WrOdtTrnOnDly_MASK 0x700 +#define D18F2x240_dct1_mp1_Reserved_11_11_OFFSET 11 +#define D18F2x240_dct1_mp1_Reserved_11_11_WIDTH 1 +#define D18F2x240_dct1_mp1_Reserved_11_11_MASK 0x800 +#define D18F2x240_dct1_mp1_WrOdtOnDuration_OFFSET 12 +#define D18F2x240_dct1_mp1_WrOdtOnDuration_WIDTH 3 +#define D18F2x240_dct1_mp1_WrOdtOnDuration_MASK 0x7000 +#define D18F2x240_dct1_mp1_Reserved_31_15_OFFSET 15 +#define D18F2x240_dct1_mp1_Reserved_31_15_WIDTH 17 +#define D18F2x240_dct1_mp1_Reserved_31_15_MASK 0xffff8000 + +/// D18F2x240_dct1_mp1 +typedef union { + struct { ///< + UINT32 RdOdtTrnOnDly:4 ; ///< + UINT32 RdOdtOnDuration:3 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 WrOdtTrnOnDly:3 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 WrOdtOnDuration:3 ; ///< + UINT32 Reserved_31_15:17; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x240_dct1_mp1_STRUCT; + +// **** D18F2x244_dct1 Register Definition **** +// Address +#define D18F2x244_dct1_ADDRESS 0x244 + +// Type +#define D18F2x244_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x244_dct1_PrtlChPDDynDly_OFFSET 0 +#define D18F2x244_dct1_PrtlChPDDynDly_WIDTH 4 +#define D18F2x244_dct1_PrtlChPDDynDly_MASK 0xf +#define D18F2x244_dct1_Reserved_31_4_OFFSET 4 +#define D18F2x244_dct1_Reserved_31_4_WIDTH 28 +#define D18F2x244_dct1_Reserved_31_4_MASK 0xfffffff0 + +/// D18F2x244_dct1 +typedef union { + struct { ///< + UINT32 PrtlChPDDynDly:4 ; ///< + UINT32 Reserved_31_4:28; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x244_dct1_STRUCT; + +// **** D18F2x244_dct0 Register Definition **** +// Address +#define D18F2x244_dct0_ADDRESS 0x244 + +// Type +#define D18F2x244_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x244_dct0_PrtlChPDDynDly_OFFSET 0 +#define D18F2x244_dct0_PrtlChPDDynDly_WIDTH 4 +#define D18F2x244_dct0_PrtlChPDDynDly_MASK 0xf +#define D18F2x244_dct0_Reserved_31_4_OFFSET 4 +#define D18F2x244_dct0_Reserved_31_4_WIDTH 28 +#define D18F2x244_dct0_Reserved_31_4_MASK 0xfffffff0 + +/// D18F2x244_dct0 +typedef union { + struct { ///< + UINT32 PrtlChPDDynDly:4 ; ///< + UINT32 Reserved_31_4:28; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x244_dct0_STRUCT; + +// **** D18F2x248_dct1_mp1 Register Definition **** +// Address +#define D18F2x248_dct1_mp1_ADDRESS 0x248 + +// Type +#define D18F2x248_dct1_mp1_TYPE TYPE_D18F2_dct1_mp1 +// Field Data +#define D18F2x248_dct1_mp1_Txp_OFFSET 0 +#define D18F2x248_dct1_mp1_Txp_WIDTH 4 +#define D18F2x248_dct1_mp1_Txp_MASK 0xf +#define D18F2x248_dct1_mp1_Reserved_7_4_OFFSET 4 +#define D18F2x248_dct1_mp1_Reserved_7_4_WIDTH 4 +#define D18F2x248_dct1_mp1_Reserved_7_4_MASK 0xf0 +#define D18F2x248_dct1_mp1_Txpdll_OFFSET 8 +#define D18F2x248_dct1_mp1_Txpdll_WIDTH 5 +#define D18F2x248_dct1_mp1_Txpdll_MASK 0x1f00 +#define D18F2x248_dct1_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x248_dct1_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x248_dct1_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x248_dct1_mp1_PchgPDEnDelay_OFFSET 16 +#define D18F2x248_dct1_mp1_PchgPDEnDelay_WIDTH 6 +#define D18F2x248_dct1_mp1_PchgPDEnDelay_MASK 0x3f0000 +#define D18F2x248_dct1_mp1_Reserved_23_22_OFFSET 22 +#define D18F2x248_dct1_mp1_Reserved_23_22_WIDTH 2 +#define D18F2x248_dct1_mp1_Reserved_23_22_MASK 0xc00000 +#define D18F2x248_dct1_mp1_AggrPDDelay_OFFSET 24 +#define D18F2x248_dct1_mp1_AggrPDDelay_WIDTH 6 +#define D18F2x248_dct1_mp1_AggrPDDelay_MASK 0x3f000000 +#define D18F2x248_dct1_mp1_Reserved_30_30_OFFSET 30 +#define D18F2x248_dct1_mp1_Reserved_30_30_WIDTH 1 +#define D18F2x248_dct1_mp1_Reserved_30_30_MASK 0x40000000 +#define D18F2x248_dct1_mp1_RxChMntClkEn_OFFSET 31 +#define D18F2x248_dct1_mp1_RxChMntClkEn_WIDTH 1 +#define D18F2x248_dct1_mp1_RxChMntClkEn_MASK 0x80000000 + +/// D18F2x248_dct1_mp1 +typedef union { + struct { ///< + UINT32 Txp:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 Txpdll:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 PchgPDEnDelay:6 ; ///< + UINT32 Reserved_23_22:2 ; ///< + UINT32 AggrPDDelay:6 ; ///< + UINT32 Reserved_30_30:1 ; ///< + UINT32 RxChMntClkEn:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x248_dct1_mp1_STRUCT; + +// **** D18F2x248_dct0_mp1 Register Definition **** +// Address +#define D18F2x248_dct0_mp1_ADDRESS 0x248 + +// Type +#define D18F2x248_dct0_mp1_TYPE TYPE_D18F2_dct0_mp1 +// Field Data +#define D18F2x248_dct0_mp1_Txp_OFFSET 0 +#define D18F2x248_dct0_mp1_Txp_WIDTH 4 +#define D18F2x248_dct0_mp1_Txp_MASK 0xf +#define D18F2x248_dct0_mp1_Reserved_7_4_OFFSET 4 +#define D18F2x248_dct0_mp1_Reserved_7_4_WIDTH 4 +#define D18F2x248_dct0_mp1_Reserved_7_4_MASK 0xf0 +#define D18F2x248_dct0_mp1_Txpdll_OFFSET 8 +#define D18F2x248_dct0_mp1_Txpdll_WIDTH 5 +#define D18F2x248_dct0_mp1_Txpdll_MASK 0x1f00 +#define D18F2x248_dct0_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x248_dct0_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x248_dct0_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x248_dct0_mp1_PchgPDEnDelay_OFFSET 16 +#define D18F2x248_dct0_mp1_PchgPDEnDelay_WIDTH 6 +#define D18F2x248_dct0_mp1_PchgPDEnDelay_MASK 0x3f0000 +#define D18F2x248_dct0_mp1_Reserved_23_22_OFFSET 22 +#define D18F2x248_dct0_mp1_Reserved_23_22_WIDTH 2 +#define D18F2x248_dct0_mp1_Reserved_23_22_MASK 0xc00000 +#define D18F2x248_dct0_mp1_AggrPDDelay_OFFSET 24 +#define D18F2x248_dct0_mp1_AggrPDDelay_WIDTH 6 +#define D18F2x248_dct0_mp1_AggrPDDelay_MASK 0x3f000000 +#define D18F2x248_dct0_mp1_Reserved_30_30_OFFSET 30 +#define D18F2x248_dct0_mp1_Reserved_30_30_WIDTH 1 +#define D18F2x248_dct0_mp1_Reserved_30_30_MASK 0x40000000 +#define D18F2x248_dct0_mp1_RxChMntClkEn_OFFSET 31 +#define D18F2x248_dct0_mp1_RxChMntClkEn_WIDTH 1 +#define D18F2x248_dct0_mp1_RxChMntClkEn_MASK 0x80000000 + +/// D18F2x248_dct0_mp1 +typedef union { + struct { ///< + UINT32 Txp:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 Txpdll:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 PchgPDEnDelay:6 ; ///< + UINT32 Reserved_23_22:2 ; ///< + UINT32 AggrPDDelay:6 ; ///< + UINT32 Reserved_30_30:1 ; ///< + UINT32 RxChMntClkEn:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x248_dct0_mp1_STRUCT; + +// **** D18F2x248_dct1_mp0 Register Definition **** +// Address +#define D18F2x248_dct1_mp0_ADDRESS 0x248 + +// Type +#define D18F2x248_dct1_mp0_TYPE TYPE_D18F2_dct1_mp0 +// Field Data +#define D18F2x248_dct1_mp0_Txp_OFFSET 0 +#define D18F2x248_dct1_mp0_Txp_WIDTH 4 +#define D18F2x248_dct1_mp0_Txp_MASK 0xf +#define D18F2x248_dct1_mp0_Reserved_7_4_OFFSET 4 +#define D18F2x248_dct1_mp0_Reserved_7_4_WIDTH 4 +#define D18F2x248_dct1_mp0_Reserved_7_4_MASK 0xf0 +#define D18F2x248_dct1_mp0_Txpdll_OFFSET 8 +#define D18F2x248_dct1_mp0_Txpdll_WIDTH 5 +#define D18F2x248_dct1_mp0_Txpdll_MASK 0x1f00 +#define D18F2x248_dct1_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x248_dct1_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x248_dct1_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x248_dct1_mp0_PchgPDEnDelay_OFFSET 16 +#define D18F2x248_dct1_mp0_PchgPDEnDelay_WIDTH 6 +#define D18F2x248_dct1_mp0_PchgPDEnDelay_MASK 0x3f0000 +#define D18F2x248_dct1_mp0_Reserved_23_22_OFFSET 22 +#define D18F2x248_dct1_mp0_Reserved_23_22_WIDTH 2 +#define D18F2x248_dct1_mp0_Reserved_23_22_MASK 0xc00000 +#define D18F2x248_dct1_mp0_AggrPDDelay_OFFSET 24 +#define D18F2x248_dct1_mp0_AggrPDDelay_WIDTH 6 +#define D18F2x248_dct1_mp0_AggrPDDelay_MASK 0x3f000000 +#define D18F2x248_dct1_mp0_Reserved_30_30_OFFSET 30 +#define D18F2x248_dct1_mp0_Reserved_30_30_WIDTH 1 +#define D18F2x248_dct1_mp0_Reserved_30_30_MASK 0x40000000 +#define D18F2x248_dct1_mp0_RxChMntClkEn_OFFSET 31 +#define D18F2x248_dct1_mp0_RxChMntClkEn_WIDTH 1 +#define D18F2x248_dct1_mp0_RxChMntClkEn_MASK 0x80000000 + +/// D18F2x248_dct1_mp0 +typedef union { + struct { ///< + UINT32 Txp:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 Txpdll:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 PchgPDEnDelay:6 ; ///< + UINT32 Reserved_23_22:2 ; ///< + UINT32 AggrPDDelay:6 ; ///< + UINT32 Reserved_30_30:1 ; ///< + UINT32 RxChMntClkEn:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x248_dct1_mp0_STRUCT; + +// **** D18F2x248_dct0_mp0 Register Definition **** +// Address +#define D18F2x248_dct0_mp0_ADDRESS 0x248 + +// Type +#define D18F2x248_dct0_mp0_TYPE TYPE_D18F2_dct0_mp0 +// Field Data +#define D18F2x248_dct0_mp0_Txp_OFFSET 0 +#define D18F2x248_dct0_mp0_Txp_WIDTH 4 +#define D18F2x248_dct0_mp0_Txp_MASK 0xf +#define D18F2x248_dct0_mp0_Reserved_7_4_OFFSET 4 +#define D18F2x248_dct0_mp0_Reserved_7_4_WIDTH 4 +#define D18F2x248_dct0_mp0_Reserved_7_4_MASK 0xf0 +#define D18F2x248_dct0_mp0_Txpdll_OFFSET 8 +#define D18F2x248_dct0_mp0_Txpdll_WIDTH 5 +#define D18F2x248_dct0_mp0_Txpdll_MASK 0x1f00 +#define D18F2x248_dct0_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x248_dct0_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x248_dct0_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x248_dct0_mp0_PchgPDEnDelay_OFFSET 16 +#define D18F2x248_dct0_mp0_PchgPDEnDelay_WIDTH 6 +#define D18F2x248_dct0_mp0_PchgPDEnDelay_MASK 0x3f0000 +#define D18F2x248_dct0_mp0_Reserved_23_22_OFFSET 22 +#define D18F2x248_dct0_mp0_Reserved_23_22_WIDTH 2 +#define D18F2x248_dct0_mp0_Reserved_23_22_MASK 0xc00000 +#define D18F2x248_dct0_mp0_AggrPDDelay_OFFSET 24 +#define D18F2x248_dct0_mp0_AggrPDDelay_WIDTH 6 +#define D18F2x248_dct0_mp0_AggrPDDelay_MASK 0x3f000000 +#define D18F2x248_dct0_mp0_Reserved_30_30_OFFSET 30 +#define D18F2x248_dct0_mp0_Reserved_30_30_WIDTH 1 +#define D18F2x248_dct0_mp0_Reserved_30_30_MASK 0x40000000 +#define D18F2x248_dct0_mp0_RxChMntClkEn_OFFSET 31 +#define D18F2x248_dct0_mp0_RxChMntClkEn_WIDTH 1 +#define D18F2x248_dct0_mp0_RxChMntClkEn_MASK 0x80000000 + +/// D18F2x248_dct0_mp0 +typedef union { + struct { ///< + UINT32 Txp:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 Txpdll:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 PchgPDEnDelay:6 ; ///< + UINT32 Reserved_23_22:2 ; ///< + UINT32 AggrPDDelay:6 ; ///< + UINT32 Reserved_30_30:1 ; ///< + UINT32 RxChMntClkEn:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x248_dct0_mp0_STRUCT; + +// **** D18F2x24C_dct0 Register Definition **** +// Address +#define D18F2x24C_dct0_ADDRESS 0x24c + +// Type +#define D18F2x24C_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x24C_dct0_Tpd_OFFSET 0 +#define D18F2x24C_dct0_Tpd_WIDTH 4 +#define D18F2x24C_dct0_Tpd_MASK 0xf +#define D18F2x24C_dct0_Reserved_7_4_OFFSET 4 +#define D18F2x24C_dct0_Reserved_7_4_WIDTH 4 +#define D18F2x24C_dct0_Reserved_7_4_MASK 0xf0 +#define D18F2x24C_dct0_Tckesr_OFFSET 8 +#define D18F2x24C_dct0_Tckesr_WIDTH 6 +#define D18F2x24C_dct0_Tckesr_MASK 0x3f00 +#define D18F2x24C_dct0_Reserved_15_14_OFFSET 14 +#define D18F2x24C_dct0_Reserved_15_14_WIDTH 2 +#define D18F2x24C_dct0_Reserved_15_14_MASK 0xc000 +#define D18F2x24C_dct0_Tcksre_OFFSET 16 +#define D18F2x24C_dct0_Tcksre_WIDTH 6 +#define D18F2x24C_dct0_Tcksre_MASK 0x3f0000 +#define D18F2x24C_dct0_Reserved_23_22_OFFSET 22 +#define D18F2x24C_dct0_Reserved_23_22_WIDTH 2 +#define D18F2x24C_dct0_Reserved_23_22_MASK 0xc00000 +#define D18F2x24C_dct0_Tcksrx_OFFSET 24 +#define D18F2x24C_dct0_Tcksrx_WIDTH 6 +#define D18F2x24C_dct0_Tcksrx_MASK 0x3f000000 +#define D18F2x24C_dct0_Reserved_31_30_OFFSET 30 +#define D18F2x24C_dct0_Reserved_31_30_WIDTH 2 +#define D18F2x24C_dct0_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x24C_dct0 +typedef union { + struct { ///< + UINT32 Tpd:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 Tckesr:6 ; ///< + UINT32 Reserved_15_14:2 ; ///< + UINT32 Tcksre:6 ; ///< + UINT32 Reserved_23_22:2 ; ///< + UINT32 Tcksrx:6 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x24C_dct0_STRUCT; + +// **** D18F2x24C_dct1 Register Definition **** +// Address +#define D18F2x24C_dct1_ADDRESS 0x24c + +// Type +#define D18F2x24C_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x24C_dct1_Tpd_OFFSET 0 +#define D18F2x24C_dct1_Tpd_WIDTH 4 +#define D18F2x24C_dct1_Tpd_MASK 0xf +#define D18F2x24C_dct1_Reserved_7_4_OFFSET 4 +#define D18F2x24C_dct1_Reserved_7_4_WIDTH 4 +#define D18F2x24C_dct1_Reserved_7_4_MASK 0xf0 +#define D18F2x24C_dct1_Tckesr_OFFSET 8 +#define D18F2x24C_dct1_Tckesr_WIDTH 6 +#define D18F2x24C_dct1_Tckesr_MASK 0x3f00 +#define D18F2x24C_dct1_Reserved_15_14_OFFSET 14 +#define D18F2x24C_dct1_Reserved_15_14_WIDTH 2 +#define D18F2x24C_dct1_Reserved_15_14_MASK 0xc000 +#define D18F2x24C_dct1_Tcksre_OFFSET 16 +#define D18F2x24C_dct1_Tcksre_WIDTH 6 +#define D18F2x24C_dct1_Tcksre_MASK 0x3f0000 +#define D18F2x24C_dct1_Reserved_23_22_OFFSET 22 +#define D18F2x24C_dct1_Reserved_23_22_WIDTH 2 +#define D18F2x24C_dct1_Reserved_23_22_MASK 0xc00000 +#define D18F2x24C_dct1_Tcksrx_OFFSET 24 +#define D18F2x24C_dct1_Tcksrx_WIDTH 6 +#define D18F2x24C_dct1_Tcksrx_MASK 0x3f000000 +#define D18F2x24C_dct1_Reserved_31_30_OFFSET 30 +#define D18F2x24C_dct1_Reserved_31_30_WIDTH 2 +#define D18F2x24C_dct1_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x24C_dct1 +typedef union { + struct { ///< + UINT32 Tpd:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 Tckesr:6 ; ///< + UINT32 Reserved_15_14:2 ; ///< + UINT32 Tcksre:6 ; ///< + UINT32 Reserved_23_22:2 ; ///< + UINT32 Tcksrx:6 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x24C_dct1_STRUCT; + +// **** D18F2x250_dct0 Register Definition **** +// Address +#define D18F2x250_dct0_ADDRESS 0x250 + +// Type +#define D18F2x250_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x250_dct0_Reserved_1_0_OFFSET 0 +#define D18F2x250_dct0_Reserved_1_0_WIDTH 2 +#define D18F2x250_dct0_Reserved_1_0_MASK 0x3 +#define D18F2x250_dct0_CmdTestEnable_OFFSET 2 +#define D18F2x250_dct0_CmdTestEnable_WIDTH 1 +#define D18F2x250_dct0_CmdTestEnable_MASK 0x4 +#define D18F2x250_dct0_ResetAllErr_OFFSET 3 +#define D18F2x250_dct0_ResetAllErr_WIDTH 1 +#define D18F2x250_dct0_ResetAllErr_MASK 0x8 +#define D18F2x250_dct0_StopOnErr_OFFSET 4 +#define D18F2x250_dct0_StopOnErr_WIDTH 1 +#define D18F2x250_dct0_StopOnErr_MASK 0x10 +#define D18F2x250_dct0_CmdType_OFFSET 5 +#define D18F2x250_dct0_CmdType_WIDTH 3 +#define D18F2x250_dct0_CmdType_MASK 0xe0 +#define D18F2x250_dct0_CmdTgt_OFFSET 8 +#define D18F2x250_dct0_CmdTgt_WIDTH 2 +#define D18F2x250_dct0_CmdTgt_MASK 0x300 +#define D18F2x250_dct0_TestStatus_OFFSET 10 +#define D18F2x250_dct0_TestStatus_WIDTH 1 +#define D18F2x250_dct0_TestStatus_MASK 0x400 +#define D18F2x250_dct0_SendCmd_OFFSET 11 +#define D18F2x250_dct0_SendCmd_WIDTH 1 +#define D18F2x250_dct0_SendCmd_MASK 0x800 +#define D18F2x250_dct0_CmdSendInProg_OFFSET 12 +#define D18F2x250_dct0_CmdSendInProg_WIDTH 1 +#define D18F2x250_dct0_CmdSendInProg_MASK 0x1000 +#define D18F2x250_dct0_Reserved_31_13_OFFSET 13 +#define D18F2x250_dct0_Reserved_31_13_WIDTH 19 +#define D18F2x250_dct0_Reserved_31_13_MASK 0xffffe000 + +/// D18F2x250_dct0 +typedef union { + struct { ///< + UINT32 Reserved_1_0:2 ; ///< + UINT32 CmdTestEnable:1 ; ///< + UINT32 ResetAllErr:1 ; ///< + UINT32 StopOnErr:1 ; ///< + UINT32 CmdType:3 ; ///< + UINT32 CmdTgt:2 ; ///< + UINT32 TestStatus:1 ; ///< + UINT32 SendCmd:1 ; ///< + UINT32 CmdSendInProg:1 ; ///< + UINT32 Reserved_31_13:19; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x250_dct0_STRUCT; + +// **** D18F2x250_dct1 Register Definition **** +// Address +#define D18F2x250_dct1_ADDRESS 0x250 + +// Type +#define D18F2x250_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x250_dct1_Reserved_1_0_OFFSET 0 +#define D18F2x250_dct1_Reserved_1_0_WIDTH 2 +#define D18F2x250_dct1_Reserved_1_0_MASK 0x3 +#define D18F2x250_dct1_CmdTestEnable_OFFSET 2 +#define D18F2x250_dct1_CmdTestEnable_WIDTH 1 +#define D18F2x250_dct1_CmdTestEnable_MASK 0x4 +#define D18F2x250_dct1_ResetAllErr_OFFSET 3 +#define D18F2x250_dct1_ResetAllErr_WIDTH 1 +#define D18F2x250_dct1_ResetAllErr_MASK 0x8 +#define D18F2x250_dct1_StopOnErr_OFFSET 4 +#define D18F2x250_dct1_StopOnErr_WIDTH 1 +#define D18F2x250_dct1_StopOnErr_MASK 0x10 +#define D18F2x250_dct1_CmdType_OFFSET 5 +#define D18F2x250_dct1_CmdType_WIDTH 3 +#define D18F2x250_dct1_CmdType_MASK 0xe0 +#define D18F2x250_dct1_CmdTgt_OFFSET 8 +#define D18F2x250_dct1_CmdTgt_WIDTH 2 +#define D18F2x250_dct1_CmdTgt_MASK 0x300 +#define D18F2x250_dct1_TestStatus_OFFSET 10 +#define D18F2x250_dct1_TestStatus_WIDTH 1 +#define D18F2x250_dct1_TestStatus_MASK 0x400 +#define D18F2x250_dct1_SendCmd_OFFSET 11 +#define D18F2x250_dct1_SendCmd_WIDTH 1 +#define D18F2x250_dct1_SendCmd_MASK 0x800 +#define D18F2x250_dct1_CmdSendInProg_OFFSET 12 +#define D18F2x250_dct1_CmdSendInProg_WIDTH 1 +#define D18F2x250_dct1_CmdSendInProg_MASK 0x1000 +#define D18F2x250_dct1_Reserved_31_13_OFFSET 13 +#define D18F2x250_dct1_Reserved_31_13_WIDTH 19 +#define D18F2x250_dct1_Reserved_31_13_MASK 0xffffe000 + +/// D18F2x250_dct1 +typedef union { + struct { ///< + UINT32 Reserved_1_0:2 ; ///< + UINT32 CmdTestEnable:1 ; ///< + UINT32 ResetAllErr:1 ; ///< + UINT32 StopOnErr:1 ; ///< + UINT32 CmdType:3 ; ///< + UINT32 CmdTgt:2 ; ///< + UINT32 TestStatus:1 ; ///< + UINT32 SendCmd:1 ; ///< + UINT32 CmdSendInProg:1 ; ///< + UINT32 Reserved_31_13:19; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x250_dct1_STRUCT; + +// **** D18F2x254_dct0 Register Definition **** +// Address +#define D18F2x254_dct0_ADDRESS 0x254 + +// Type +#define D18F2x254_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x254_dct0_TgtAddress_9_0__OFFSET 0 +#define D18F2x254_dct0_TgtAddress_9_0__WIDTH 10 +#define D18F2x254_dct0_TgtAddress_9_0__MASK 0x3ff +#define D18F2x254_dct0_Reserved_20_10_OFFSET 10 +#define D18F2x254_dct0_Reserved_20_10_WIDTH 11 +#define D18F2x254_dct0_Reserved_20_10_MASK 0x1ffc00 +#define D18F2x254_dct0_TgtBank_OFFSET 21 +#define D18F2x254_dct0_TgtBank_WIDTH 3 +#define D18F2x254_dct0_TgtBank_MASK 0xe00000 +#define D18F2x254_dct0_TgtChipSelect_OFFSET 24 +#define D18F2x254_dct0_TgtChipSelect_WIDTH 3 +#define D18F2x254_dct0_TgtChipSelect_MASK 0x7000000 +#define D18F2x254_dct0_Reserved_31_27_OFFSET 27 +#define D18F2x254_dct0_Reserved_31_27_WIDTH 5 +#define D18F2x254_dct0_Reserved_31_27_MASK 0xf8000000 + +/// D18F2x254_dct0 +typedef union { + struct { ///< + UINT32 TgtAddress_9_0_:10; ///< + UINT32 Reserved_20_10:11; ///< + UINT32 TgtBank:3 ; ///< + UINT32 TgtChipSelect:3 ; ///< + UINT32 Reserved_31_27:5 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x254_dct0_STRUCT; + +// **** D18F2x254_dct1 Register Definition **** +// Address +#define D18F2x254_dct1_ADDRESS 0x254 + +// Type +#define D18F2x254_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x254_dct1_TgtAddress_9_0__OFFSET 0 +#define D18F2x254_dct1_TgtAddress_9_0__WIDTH 10 +#define D18F2x254_dct1_TgtAddress_9_0__MASK 0x3ff +#define D18F2x254_dct1_Reserved_20_10_OFFSET 10 +#define D18F2x254_dct1_Reserved_20_10_WIDTH 11 +#define D18F2x254_dct1_Reserved_20_10_MASK 0x1ffc00 +#define D18F2x254_dct1_TgtBank_OFFSET 21 +#define D18F2x254_dct1_TgtBank_WIDTH 3 +#define D18F2x254_dct1_TgtBank_MASK 0xe00000 +#define D18F2x254_dct1_TgtChipSelect_OFFSET 24 +#define D18F2x254_dct1_TgtChipSelect_WIDTH 3 +#define D18F2x254_dct1_TgtChipSelect_MASK 0x7000000 +#define D18F2x254_dct1_Reserved_31_27_OFFSET 27 +#define D18F2x254_dct1_Reserved_31_27_WIDTH 5 +#define D18F2x254_dct1_Reserved_31_27_MASK 0xf8000000 + +/// D18F2x254_dct1 +typedef union { + struct { ///< + UINT32 TgtAddress_9_0_:10; ///< + UINT32 Reserved_20_10:11; ///< + UINT32 TgtBank:3 ; ///< + UINT32 TgtChipSelect:3 ; ///< + UINT32 Reserved_31_27:5 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x254_dct1_STRUCT; + +// **** D18F2x258_dct0 Register Definition **** +// Address +#define D18F2x258_dct0_ADDRESS 0x258 + +// Type +#define D18F2x258_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x258_dct0_TgtAddress_9_0__OFFSET 0 +#define D18F2x258_dct0_TgtAddress_9_0__WIDTH 10 +#define D18F2x258_dct0_TgtAddress_9_0__MASK 0x3ff +#define D18F2x258_dct0_Reserved_20_10_OFFSET 10 +#define D18F2x258_dct0_Reserved_20_10_WIDTH 11 +#define D18F2x258_dct0_Reserved_20_10_MASK 0x1ffc00 +#define D18F2x258_dct0_TgtBank_OFFSET 21 +#define D18F2x258_dct0_TgtBank_WIDTH 3 +#define D18F2x258_dct0_TgtBank_MASK 0xe00000 +#define D18F2x258_dct0_TgtChipSelect_OFFSET 24 +#define D18F2x258_dct0_TgtChipSelect_WIDTH 3 +#define D18F2x258_dct0_TgtChipSelect_MASK 0x7000000 +#define D18F2x258_dct0_Reserved_31_27_OFFSET 27 +#define D18F2x258_dct0_Reserved_31_27_WIDTH 5 +#define D18F2x258_dct0_Reserved_31_27_MASK 0xf8000000 + +/// D18F2x258_dct0 +typedef union { + struct { ///< + UINT32 TgtAddress_9_0_:10; ///< + UINT32 Reserved_20_10:11; ///< + UINT32 TgtBank:3 ; ///< + UINT32 TgtChipSelect:3 ; ///< + UINT32 Reserved_31_27:5 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x258_dct0_STRUCT; + +// **** D18F2x258_dct1 Register Definition **** +// Address +#define D18F2x258_dct1_ADDRESS 0x258 + +// Type +#define D18F2x258_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x258_dct1_TgtAddress_9_0__OFFSET 0 +#define D18F2x258_dct1_TgtAddress_9_0__WIDTH 10 +#define D18F2x258_dct1_TgtAddress_9_0__MASK 0x3ff +#define D18F2x258_dct1_Reserved_20_10_OFFSET 10 +#define D18F2x258_dct1_Reserved_20_10_WIDTH 11 +#define D18F2x258_dct1_Reserved_20_10_MASK 0x1ffc00 +#define D18F2x258_dct1_TgtBank_OFFSET 21 +#define D18F2x258_dct1_TgtBank_WIDTH 3 +#define D18F2x258_dct1_TgtBank_MASK 0xe00000 +#define D18F2x258_dct1_TgtChipSelect_OFFSET 24 +#define D18F2x258_dct1_TgtChipSelect_WIDTH 3 +#define D18F2x258_dct1_TgtChipSelect_MASK 0x7000000 +#define D18F2x258_dct1_Reserved_31_27_OFFSET 27 +#define D18F2x258_dct1_Reserved_31_27_WIDTH 5 +#define D18F2x258_dct1_Reserved_31_27_MASK 0xf8000000 + +/// D18F2x258_dct1 +typedef union { + struct { ///< + UINT32 TgtAddress_9_0_:10; ///< + UINT32 Reserved_20_10:11; ///< + UINT32 TgtBank:3 ; ///< + UINT32 TgtChipSelect:3 ; ///< + UINT32 Reserved_31_27:5 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x258_dct1_STRUCT; + + +// **** D18F2x260_dct1 Register Definition **** +// Address +#define D18F2x260_dct1_ADDRESS 0x260 + +// Type +#define D18F2x260_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x260_dct1_CmdCount_OFFSET 0 +#define D18F2x260_dct1_CmdCount_WIDTH 21 +#define D18F2x260_dct1_CmdCount_MASK 0x1fffff +#define D18F2x260_dct1_Reserved_31_21_OFFSET 21 +#define D18F2x260_dct1_Reserved_31_21_WIDTH 11 +#define D18F2x260_dct1_Reserved_31_21_MASK 0xffe00000 + +/// D18F2x260_dct1 +typedef union { + struct { ///< + UINT32 CmdCount:21; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x260_dct1_STRUCT; + +// **** D18F2x260_dct0 Register Definition **** +// Address +#define D18F2x260_dct0_ADDRESS 0x260 + +// Type +#define D18F2x260_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x260_dct0_CmdCount_OFFSET 0 +#define D18F2x260_dct0_CmdCount_WIDTH 21 +#define D18F2x260_dct0_CmdCount_MASK 0x1fffff +#define D18F2x260_dct0_Reserved_31_21_OFFSET 21 +#define D18F2x260_dct0_Reserved_31_21_WIDTH 11 +#define D18F2x260_dct0_Reserved_31_21_MASK 0xffe00000 + +/// D18F2x260_dct0 +typedef union { + struct { ///< + UINT32 CmdCount:21; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x260_dct0_STRUCT; + +// **** D18F2x264_dct1 Register Definition **** +// Address +#define D18F2x264_dct1_ADDRESS 0x264 + +// Type +#define D18F2x264_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x264_dct1_ErrCnt_OFFSET 0 +#define D18F2x264_dct1_ErrCnt_WIDTH 25 +#define D18F2x264_dct1_ErrCnt_MASK 0x1ffffff +#define D18F2x264_dct1_ErrDqNum_OFFSET 25 +#define D18F2x264_dct1_ErrDqNum_WIDTH 7 +#define D18F2x264_dct1_ErrDqNum_MASK 0xfe000000 + +/// D18F2x264_dct1 +typedef union { + struct { ///< + UINT32 ErrCnt:25; ///< + UINT32 ErrDqNum:7 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x264_dct1_STRUCT; + +// **** D18F2x264_dct0 Register Definition **** +// Address +#define D18F2x264_dct0_ADDRESS 0x264 + +// Type +#define D18F2x264_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x264_dct0_ErrCnt_OFFSET 0 +#define D18F2x264_dct0_ErrCnt_WIDTH 25 +#define D18F2x264_dct0_ErrCnt_MASK 0x1ffffff +#define D18F2x264_dct0_ErrDqNum_OFFSET 25 +#define D18F2x264_dct0_ErrDqNum_WIDTH 7 +#define D18F2x264_dct0_ErrDqNum_MASK 0xfe000000 + +/// D18F2x264_dct0 +typedef union { + struct { ///< + UINT32 ErrCnt:25; ///< + UINT32 ErrDqNum:7 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x264_dct0_STRUCT; + +// **** D18F2x268_dct1 Register Definition **** +// Address +#define D18F2x268_dct1_ADDRESS 0x268 + +// Type +#define D18F2x268_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x268_dct1_NibbleErrSts_OFFSET 0 +#define D18F2x268_dct1_NibbleErrSts_WIDTH 18 +#define D18F2x268_dct1_NibbleErrSts_MASK 0x3ffff +#define D18F2x268_dct1_Reserved_31_18_OFFSET 18 +#define D18F2x268_dct1_Reserved_31_18_WIDTH 14 +#define D18F2x268_dct1_Reserved_31_18_MASK 0xfffc0000 + +/// D18F2x268_dct1 +typedef union { + struct { ///< + UINT32 NibbleErrSts:18; ///< + UINT32 Reserved_31_18:14; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x268_dct1_STRUCT; + +// **** D18F2x268_dct0 Register Definition **** +// Address +#define D18F2x268_dct0_ADDRESS 0x268 + +// Type +#define D18F2x268_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x268_dct0_NibbleErrSts_OFFSET 0 +#define D18F2x268_dct0_NibbleErrSts_WIDTH 18 +#define D18F2x268_dct0_NibbleErrSts_MASK 0x3ffff +#define D18F2x268_dct0_Reserved_31_18_OFFSET 18 +#define D18F2x268_dct0_Reserved_31_18_WIDTH 14 +#define D18F2x268_dct0_Reserved_31_18_MASK 0xfffc0000 + +/// D18F2x268_dct0 +typedef union { + struct { ///< + UINT32 NibbleErrSts:18; ///< + UINT32 Reserved_31_18:14; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x268_dct0_STRUCT; + +// **** D18F2x26C_dct1 Register Definition **** +// Address +#define D18F2x26C_dct1_ADDRESS 0x26c + +// Type +#define D18F2x26C_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x26C_dct1_NibbleErr180Sts_OFFSET 0 +#define D18F2x26C_dct1_NibbleErr180Sts_WIDTH 18 +#define D18F2x26C_dct1_NibbleErr180Sts_MASK 0x3ffff +#define D18F2x26C_dct1_Reserved_31_18_OFFSET 18 +#define D18F2x26C_dct1_Reserved_31_18_WIDTH 14 +#define D18F2x26C_dct1_Reserved_31_18_MASK 0xfffc0000 + +/// D18F2x26C_dct1 +typedef union { + struct { ///< + UINT32 NibbleErr180Sts:18; ///< + UINT32 Reserved_31_18:14; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x26C_dct1_STRUCT; + +// **** D18F2x26C_dct0 Register Definition **** +// Address +#define D18F2x26C_dct0_ADDRESS 0x26c + +// Type +#define D18F2x26C_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x26C_dct0_NibbleErr180Sts_OFFSET 0 +#define D18F2x26C_dct0_NibbleErr180Sts_WIDTH 18 +#define D18F2x26C_dct0_NibbleErr180Sts_MASK 0x3ffff +#define D18F2x26C_dct0_Reserved_31_18_OFFSET 18 +#define D18F2x26C_dct0_Reserved_31_18_WIDTH 14 +#define D18F2x26C_dct0_Reserved_31_18_MASK 0xfffc0000 + +/// D18F2x26C_dct0 +typedef union { + struct { ///< + UINT32 NibbleErr180Sts:18; ///< + UINT32 Reserved_31_18:14; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x26C_dct0_STRUCT; + +// **** D18F2x270_dct0 Register Definition **** +// Address +#define D18F2x270_dct0_ADDRESS 0x270 + +// Type +#define D18F2x270_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x270_dct0_DataPrbsSeed_OFFSET 0 +#define D18F2x270_dct0_DataPrbsSeed_WIDTH 19 +#define D18F2x270_dct0_DataPrbsSeed_MASK 0x7ffff +#define D18F2x270_dct0_Reserved_23_19_OFFSET 19 +#define D18F2x270_dct0_Reserved_23_19_WIDTH 5 +#define D18F2x270_dct0_Reserved_23_19_MASK 0xf80000 +#define D18F2x270_dct0_Reserved_30_24_OFFSET 24 +#define D18F2x270_dct0_Reserved_30_24_WIDTH 7 +#define D18F2x270_dct0_Reserved_30_24_MASK 0x7f000000 +#define D18F2x270_dct0_Reserved_31_31_OFFSET 31 +#define D18F2x270_dct0_Reserved_31_31_WIDTH 1 +#define D18F2x270_dct0_Reserved_31_31_MASK 0x80000000 + +/// D18F2x270_dct0 +typedef union { + struct { ///< + UINT32 DataPrbsSeed:19; ///< + UINT32 Reserved_23_19:5 ; ///< + UINT32 Reserved_30_24:7 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x270_dct0_STRUCT; + +// **** D18F2x270_dct1 Register Definition **** +// Address +#define D18F2x270_dct1_ADDRESS 0x270 + +// Type +#define D18F2x270_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x270_dct1_DataPrbsSeed_OFFSET 0 +#define D18F2x270_dct1_DataPrbsSeed_WIDTH 19 +#define D18F2x270_dct1_DataPrbsSeed_MASK 0x7ffff +#define D18F2x270_dct1_Reserved_23_19_OFFSET 19 +#define D18F2x270_dct1_Reserved_23_19_WIDTH 5 +#define D18F2x270_dct1_Reserved_23_19_MASK 0xf80000 +#define D18F2x270_dct1_Reserved_30_24_OFFSET 24 +#define D18F2x270_dct1_Reserved_30_24_WIDTH 7 +#define D18F2x270_dct1_Reserved_30_24_MASK 0x7f000000 +#define D18F2x270_dct1_Reserved_31_31_OFFSET 31 +#define D18F2x270_dct1_Reserved_31_31_WIDTH 1 +#define D18F2x270_dct1_Reserved_31_31_MASK 0x80000000 + +/// D18F2x270_dct1 +typedef union { + struct { ///< + UINT32 DataPrbsSeed:19; ///< + UINT32 Reserved_23_19:5 ; ///< + UINT32 Reserved_30_24:7 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x270_dct1_STRUCT; + +// **** D18F2x274_dct0 Register Definition **** +// Address +#define D18F2x274_dct0_ADDRESS 0x274 + +// Type +#define D18F2x274_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x274_dct0_DQMask_31_0__OFFSET 0 +#define D18F2x274_dct0_DQMask_31_0__WIDTH 32 +#define D18F2x274_dct0_DQMask_31_0__MASK 0xffffffff + +/// D18F2x274_dct0 +typedef union { + struct { ///< + UINT32 DQMask_31_0_:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x274_dct0_STRUCT; + +// **** D18F2x274_dct1 Register Definition **** +// Address +#define D18F2x274_dct1_ADDRESS 0x274 + +// Type +#define D18F2x274_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x274_dct1_DQMask_31_0__OFFSET 0 +#define D18F2x274_dct1_DQMask_31_0__WIDTH 32 +#define D18F2x274_dct1_DQMask_31_0__MASK 0xffffffff + +/// D18F2x274_dct1 +typedef union { + struct { ///< + UINT32 DQMask_31_0_:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x274_dct1_STRUCT; + +// **** D18F2x278_dct0 Register Definition **** +// Address +#define D18F2x278_dct0_ADDRESS 0x278 + +// Type +#define D18F2x278_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x278_dct0_DQMask_63_32__OFFSET 0 +#define D18F2x278_dct0_DQMask_63_32__WIDTH 32 +#define D18F2x278_dct0_DQMask_63_32__MASK 0xffffffff + +/// D18F2x278_dct0 +typedef union { + struct { ///< + UINT32 DQMask_63_32_:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x278_dct0_STRUCT; + +// **** D18F2x278_dct1 Register Definition **** +// Address +#define D18F2x278_dct1_ADDRESS 0x278 + +// Type +#define D18F2x278_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x278_dct1_DQMask_63_32__OFFSET 0 +#define D18F2x278_dct1_DQMask_63_32__WIDTH 32 +#define D18F2x278_dct1_DQMask_63_32__MASK 0xffffffff + +/// D18F2x278_dct1 +typedef union { + struct { ///< + UINT32 DQMask_63_32_:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x278_dct1_STRUCT; + +// **** D18F2x28C_dct0 Register Definition **** +// Address +#define D18F2x28C_dct0_ADDRESS 0x28c + +// Type +#define D18F2x28C_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x28C_dct0_CmdAddress_17_0__OFFSET 0 +#define D18F2x28C_dct0_CmdAddress_17_0__WIDTH 18 +#define D18F2x28C_dct0_CmdAddress_17_0__MASK 0x3ffff +#define D18F2x28C_dct0_Reserved_18_18_OFFSET 18 +#define D18F2x28C_dct0_Reserved_18_18_WIDTH 1 +#define D18F2x28C_dct0_Reserved_18_18_MASK 0x40000 +#define D18F2x28C_dct0_CmdBank_2_0__OFFSET 19 +#define D18F2x28C_dct0_CmdBank_2_0__WIDTH 3 +#define D18F2x28C_dct0_CmdBank_2_0__MASK 0x380000 +#define D18F2x28C_dct0_CmdChipSelect_OFFSET 22 +#define D18F2x28C_dct0_CmdChipSelect_WIDTH 8 +#define D18F2x28C_dct0_CmdChipSelect_MASK 0x3fc00000 +#define D18F2x28C_dct0_SendPchgCmd_OFFSET 30 +#define D18F2x28C_dct0_SendPchgCmd_WIDTH 1 +#define D18F2x28C_dct0_SendPchgCmd_MASK 0x40000000 +#define D18F2x28C_dct0_SendActCmd_OFFSET 31 +#define D18F2x28C_dct0_SendActCmd_WIDTH 1 +#define D18F2x28C_dct0_SendActCmd_MASK 0x80000000 + +/// D18F2x28C_dct0 +typedef union { + struct { ///< + UINT32 CmdAddress_17_0_:18; ///< + UINT32 Reserved_18_18:1 ; ///< + UINT32 CmdBank_2_0_:3 ; ///< + UINT32 CmdChipSelect:8 ; ///< + UINT32 SendPchgCmd:1 ; ///< + UINT32 SendActCmd:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x28C_dct0_STRUCT; + +// **** D18F2x28C_dct1 Register Definition **** +// Address +#define D18F2x28C_dct1_ADDRESS 0x28c + +// Type +#define D18F2x28C_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x28C_dct1_CmdAddress_17_0__OFFSET 0 +#define D18F2x28C_dct1_CmdAddress_17_0__WIDTH 18 +#define D18F2x28C_dct1_CmdAddress_17_0__MASK 0x3ffff +#define D18F2x28C_dct1_Reserved_18_18_OFFSET 18 +#define D18F2x28C_dct1_Reserved_18_18_WIDTH 1 +#define D18F2x28C_dct1_Reserved_18_18_MASK 0x40000 +#define D18F2x28C_dct1_CmdBank_2_0__OFFSET 19 +#define D18F2x28C_dct1_CmdBank_2_0__WIDTH 3 +#define D18F2x28C_dct1_CmdBank_2_0__MASK 0x380000 +#define D18F2x28C_dct1_CmdChipSelect_OFFSET 22 +#define D18F2x28C_dct1_CmdChipSelect_WIDTH 8 +#define D18F2x28C_dct1_CmdChipSelect_MASK 0x3fc00000 +#define D18F2x28C_dct1_SendPchgCmd_OFFSET 30 +#define D18F2x28C_dct1_SendPchgCmd_WIDTH 1 +#define D18F2x28C_dct1_SendPchgCmd_MASK 0x40000000 +#define D18F2x28C_dct1_SendActCmd_OFFSET 31 +#define D18F2x28C_dct1_SendActCmd_WIDTH 1 +#define D18F2x28C_dct1_SendActCmd_MASK 0x80000000 + +/// D18F2x28C_dct1 +typedef union { + struct { ///< + UINT32 CmdAddress_17_0_:18; ///< + UINT32 Reserved_18_18:1 ; ///< + UINT32 CmdBank_2_0_:3 ; ///< + UINT32 CmdChipSelect:8 ; ///< + UINT32 SendPchgCmd:1 ; ///< + UINT32 SendActCmd:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x28C_dct1_STRUCT; + +// **** D18F2x290_dct1 Register Definition **** +// Address +#define D18F2x290_dct1_ADDRESS 0x290 + +// Type +#define D18F2x290_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x290_dct1_ErrCmdNum_OFFSET 0 +#define D18F2x290_dct1_ErrCmdNum_WIDTH 21 +#define D18F2x290_dct1_ErrCmdNum_MASK 0x1fffff +#define D18F2x290_dct1_Reserved_23_21_OFFSET 21 +#define D18F2x290_dct1_Reserved_23_21_WIDTH 3 +#define D18F2x290_dct1_Reserved_23_21_MASK 0xe00000 +#define D18F2x290_dct1_ErrBeatNum_OFFSET 24 +#define D18F2x290_dct1_ErrBeatNum_WIDTH 3 +#define D18F2x290_dct1_ErrBeatNum_MASK 0x7000000 +#define D18F2x290_dct1_Reserved_31_27_OFFSET 27 +#define D18F2x290_dct1_Reserved_31_27_WIDTH 5 +#define D18F2x290_dct1_Reserved_31_27_MASK 0xf8000000 + +/// D18F2x290_dct1 +typedef union { + struct { ///< + UINT32 ErrCmdNum:21; ///< + UINT32 Reserved_23_21:3 ; ///< + UINT32 ErrBeatNum:3 ; ///< + UINT32 Reserved_31_27:5 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x290_dct1_STRUCT; + +// **** D18F2x290_dct0 Register Definition **** +// Address +#define D18F2x290_dct0_ADDRESS 0x290 + +// Type +#define D18F2x290_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x290_dct0_ErrCmdNum_OFFSET 0 +#define D18F2x290_dct0_ErrCmdNum_WIDTH 21 +#define D18F2x290_dct0_ErrCmdNum_MASK 0x1fffff +#define D18F2x290_dct0_Reserved_23_21_OFFSET 21 +#define D18F2x290_dct0_Reserved_23_21_WIDTH 3 +#define D18F2x290_dct0_Reserved_23_21_MASK 0xe00000 +#define D18F2x290_dct0_ErrBeatNum_OFFSET 24 +#define D18F2x290_dct0_ErrBeatNum_WIDTH 3 +#define D18F2x290_dct0_ErrBeatNum_MASK 0x7000000 +#define D18F2x290_dct0_Reserved_31_27_OFFSET 27 +#define D18F2x290_dct0_Reserved_31_27_WIDTH 5 +#define D18F2x290_dct0_Reserved_31_27_MASK 0xf8000000 + +/// D18F2x290_dct0 +typedef union { + struct { ///< + UINT32 ErrCmdNum:21; ///< + UINT32 Reserved_23_21:3 ; ///< + UINT32 ErrBeatNum:3 ; ///< + UINT32 Reserved_31_27:5 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x290_dct0_STRUCT; + +// **** D18F2x294_dct1 Register Definition **** +// Address +#define D18F2x294_dct1_ADDRESS 0x294 + +// Type +#define D18F2x294_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x294_dct1_DQErr_31_0__OFFSET 0 +#define D18F2x294_dct1_DQErr_31_0__WIDTH 32 +#define D18F2x294_dct1_DQErr_31_0__MASK 0xffffffff + +/// D18F2x294_dct1 +typedef union { + struct { ///< + UINT32 DQErr_31_0_:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x294_dct1_STRUCT; + +// **** D18F2x294_dct0 Register Definition **** +// Address +#define D18F2x294_dct0_ADDRESS 0x294 + +// Type +#define D18F2x294_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x294_dct0_DQErr_31_0__OFFSET 0 +#define D18F2x294_dct0_DQErr_31_0__WIDTH 32 +#define D18F2x294_dct0_DQErr_31_0__MASK 0xffffffff + +/// D18F2x294_dct0 +typedef union { + struct { ///< + UINT32 DQErr_31_0_:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x294_dct0_STRUCT; + +// **** D18F2x298_dct0 Register Definition **** +// Address +#define D18F2x298_dct0_ADDRESS 0x298 + +// Type +#define D18F2x298_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x298_dct0_DQErr_63_32__OFFSET 0 +#define D18F2x298_dct0_DQErr_63_32__WIDTH 32 +#define D18F2x298_dct0_DQErr_63_32__MASK 0xffffffff + +/// D18F2x298_dct0 +typedef union { + struct { ///< + UINT32 DQErr_63_32_:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x298_dct0_STRUCT; + +// **** D18F2x298_dct1 Register Definition **** +// Address +#define D18F2x298_dct1_ADDRESS 0x298 + +// Type +#define D18F2x298_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x298_dct1_DQErr_63_32__OFFSET 0 +#define D18F2x298_dct1_DQErr_63_32__WIDTH 32 +#define D18F2x298_dct1_DQErr_63_32__MASK 0xffffffff + +/// D18F2x298_dct1 +typedef union { + struct { ///< + UINT32 DQErr_63_32_:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x298_dct1_STRUCT; + +// **** D18F2x2E0_dct1 Register Definition **** +// Address +#define D18F2x2E0_dct1_ADDRESS 0x2e0 + +// Type +#define D18F2x2E0_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x2E0_dct1_CurMemPstate_OFFSET 0 +#define D18F2x2E0_dct1_CurMemPstate_WIDTH 1 +#define D18F2x2E0_dct1_CurMemPstate_MASK 0x1 +#define D18F2x2E0_dct1_Reserved_19_1_OFFSET 1 +#define D18F2x2E0_dct1_Reserved_19_1_WIDTH 19 +#define D18F2x2E0_dct1_Reserved_19_1_MASK 0xffffe +#define D18F2x2E0_dct1_MxMrsEn_OFFSET 20 +#define D18F2x2E0_dct1_MxMrsEn_WIDTH 3 +#define D18F2x2E0_dct1_MxMrsEn_MASK 0x700000 +#define D18F2x2E0_dct1_Reserved_23_23_OFFSET 23 +#define D18F2x2E0_dct1_Reserved_23_23_WIDTH 1 +#define D18F2x2E0_dct1_Reserved_23_23_MASK 0x800000 +#define D18F2x2E0_dct1_M1MemClkFreq_OFFSET 24 +#define D18F2x2E0_dct1_M1MemClkFreq_WIDTH 5 +#define D18F2x2E0_dct1_M1MemClkFreq_MASK 0x1f000000 +#define D18F2x2E0_dct1_Reserved_29_29_OFFSET 29 +#define D18F2x2E0_dct1_Reserved_29_29_WIDTH 1 +#define D18F2x2E0_dct1_Reserved_29_29_MASK 0x20000000 +#define D18F2x2E0_dct1_FastMstateDis_OFFSET 30 +#define D18F2x2E0_dct1_FastMstateDis_WIDTH 1 +#define D18F2x2E0_dct1_FastMstateDis_MASK 0x40000000 +#define D18F2x2E0_dct1_Reserved_31_31_OFFSET 31 +#define D18F2x2E0_dct1_Reserved_31_31_WIDTH 1 +#define D18F2x2E0_dct1_Reserved_31_31_MASK 0x80000000 + +/// D18F2x2E0_dct1 +typedef union { + struct { ///< + UINT32 CurMemPstate:1 ; ///< + UINT32 Reserved_19_1:19; ///< + UINT32 MxMrsEn:3 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 M1MemClkFreq:5 ; ///< + UINT32 Reserved_29_29:1 ; ///< + UINT32 FastMstateDis:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x2E0_dct1_STRUCT; + +// **** D18F2x2E0_dct0 Register Definition **** +// Address +#define D18F2x2E0_dct0_ADDRESS 0x2e0 + +// Type +#define D18F2x2E0_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x2E0_dct0_CurMemPstate_OFFSET 0 +#define D18F2x2E0_dct0_CurMemPstate_WIDTH 1 +#define D18F2x2E0_dct0_CurMemPstate_MASK 0x1 +#define D18F2x2E0_dct0_Reserved_19_1_OFFSET 1 +#define D18F2x2E0_dct0_Reserved_19_1_WIDTH 19 +#define D18F2x2E0_dct0_Reserved_19_1_MASK 0xffffe +#define D18F2x2E0_dct0_MxMrsEn_OFFSET 20 +#define D18F2x2E0_dct0_MxMrsEn_WIDTH 3 +#define D18F2x2E0_dct0_MxMrsEn_MASK 0x700000 +#define D18F2x2E0_dct0_Reserved_23_23_OFFSET 23 +#define D18F2x2E0_dct0_Reserved_23_23_WIDTH 1 +#define D18F2x2E0_dct0_Reserved_23_23_MASK 0x800000 +#define D18F2x2E0_dct0_M1MemClkFreq_OFFSET 24 +#define D18F2x2E0_dct0_M1MemClkFreq_WIDTH 5 +#define D18F2x2E0_dct0_M1MemClkFreq_MASK 0x1f000000 +#define D18F2x2E0_dct0_Reserved_29_29_OFFSET 29 +#define D18F2x2E0_dct0_Reserved_29_29_WIDTH 1 +#define D18F2x2E0_dct0_Reserved_29_29_MASK 0x20000000 +#define D18F2x2E0_dct0_FastMstateDis_OFFSET 30 +#define D18F2x2E0_dct0_FastMstateDis_WIDTH 1 +#define D18F2x2E0_dct0_FastMstateDis_MASK 0x40000000 +#define D18F2x2E0_dct0_Reserved_31_31_OFFSET 31 +#define D18F2x2E0_dct0_Reserved_31_31_WIDTH 1 +#define D18F2x2E0_dct0_Reserved_31_31_MASK 0x80000000 + +/// D18F2x2E0_dct0 +typedef union { + struct { ///< + UINT32 CurMemPstate:1 ; ///< + UINT32 Reserved_19_1:19; ///< + UINT32 MxMrsEn:3 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 M1MemClkFreq:5 ; ///< + UINT32 Reserved_29_29:1 ; ///< + UINT32 FastMstateDis:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x2E0_dct0_STRUCT; + +// **** D18F2x2E8_dct0_mp1 Register Definition **** +// Address +#define D18F2x2E8_dct0_mp1_ADDRESS 0x2e8 + +// Type +#define D18F2x2E8_dct0_mp1_TYPE TYPE_D18F2_dct0_mp1 +// Field Data +#define D18F2x2E8_dct0_mp1_MxMr0_OFFSET 0 +#define D18F2x2E8_dct0_mp1_MxMr0_WIDTH 16 +#define D18F2x2E8_dct0_mp1_MxMr0_MASK 0xffff +#define D18F2x2E8_dct0_mp1_MxMr1_OFFSET 16 +#define D18F2x2E8_dct0_mp1_MxMr1_WIDTH 16 +#define D18F2x2E8_dct0_mp1_MxMr1_MASK 0xffff0000 + +/// D18F2x2E8_dct0_mp1 +typedef union { + struct { ///< + UINT32 MxMr0:16; ///< + UINT32 MxMr1:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x2E8_dct0_mp1_STRUCT; + +// **** D18F2x2E8_dct1_mp1 Register Definition **** +// Address +#define D18F2x2E8_dct1_mp1_ADDRESS 0x2e8 + +// Type +#define D18F2x2E8_dct1_mp1_TYPE TYPE_D18F2_dct1_mp1 +// Field Data +#define D18F2x2E8_dct1_mp1_MxMr0_OFFSET 0 +#define D18F2x2E8_dct1_mp1_MxMr0_WIDTH 16 +#define D18F2x2E8_dct1_mp1_MxMr0_MASK 0xffff +#define D18F2x2E8_dct1_mp1_MxMr1_OFFSET 16 +#define D18F2x2E8_dct1_mp1_MxMr1_WIDTH 16 +#define D18F2x2E8_dct1_mp1_MxMr1_MASK 0xffff0000 + +/// D18F2x2E8_dct1_mp1 +typedef union { + struct { ///< + UINT32 MxMr0:16; ///< + UINT32 MxMr1:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x2E8_dct1_mp1_STRUCT; + +// **** D18F2x2E8_dct1_mp0 Register Definition **** +// Address +#define D18F2x2E8_dct1_mp0_ADDRESS 0x2e8 + +// Type +#define D18F2x2E8_dct1_mp0_TYPE TYPE_D18F2_dct1_mp0 +// Field Data +#define D18F2x2E8_dct1_mp0_MxMr0_OFFSET 0 +#define D18F2x2E8_dct1_mp0_MxMr0_WIDTH 16 +#define D18F2x2E8_dct1_mp0_MxMr0_MASK 0xffff +#define D18F2x2E8_dct1_mp0_MxMr1_OFFSET 16 +#define D18F2x2E8_dct1_mp0_MxMr1_WIDTH 16 +#define D18F2x2E8_dct1_mp0_MxMr1_MASK 0xffff0000 + +/// D18F2x2E8_dct1_mp0 +typedef union { + struct { ///< + UINT32 MxMr0:16; ///< + UINT32 MxMr1:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x2E8_dct1_mp0_STRUCT; + +// **** D18F2x2E8_dct0_mp0 Register Definition **** +// Address +#define D18F2x2E8_dct0_mp0_ADDRESS 0x2e8 + +// Type +#define D18F2x2E8_dct0_mp0_TYPE TYPE_D18F2_dct0_mp0 +// Field Data +#define D18F2x2E8_dct0_mp0_MxMr0_OFFSET 0 +#define D18F2x2E8_dct0_mp0_MxMr0_WIDTH 16 +#define D18F2x2E8_dct0_mp0_MxMr0_MASK 0xffff +#define D18F2x2E8_dct0_mp0_MxMr1_OFFSET 16 +#define D18F2x2E8_dct0_mp0_MxMr1_WIDTH 16 +#define D18F2x2E8_dct0_mp0_MxMr1_MASK 0xffff0000 + +/// D18F2x2E8_dct0_mp0 +typedef union { + struct { ///< + UINT32 MxMr0:16; ///< + UINT32 MxMr1:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x2E8_dct0_mp0_STRUCT; + +// **** D18F2x2EC_dct0_mp0 Register Definition **** +// Address +#define D18F2x2EC_dct0_mp0_ADDRESS 0x2ec + +// Type +#define D18F2x2EC_dct0_mp0_TYPE TYPE_D18F2_dct0_mp0 +// Field Data +#define D18F2x2EC_dct0_mp0_MxMr2_OFFSET 0 +#define D18F2x2EC_dct0_mp0_MxMr2_WIDTH 16 +#define D18F2x2EC_dct0_mp0_MxMr2_MASK 0xffff +#define D18F2x2EC_dct0_mp0_Reserved_31_16_OFFSET 16 +#define D18F2x2EC_dct0_mp0_Reserved_31_16_WIDTH 16 +#define D18F2x2EC_dct0_mp0_Reserved_31_16_MASK 0xffff0000 + +/// D18F2x2EC_dct0_mp0 +typedef union { + struct { ///< + UINT32 MxMr2:16; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x2EC_dct0_mp0_STRUCT; + +// **** D18F2x2EC_dct0_mp1 Register Definition **** +// Address +#define D18F2x2EC_dct0_mp1_ADDRESS 0x2ec + +// Type +#define D18F2x2EC_dct0_mp1_TYPE TYPE_D18F2_dct0_mp1 +// Field Data +#define D18F2x2EC_dct0_mp1_MxMr2_OFFSET 0 +#define D18F2x2EC_dct0_mp1_MxMr2_WIDTH 16 +#define D18F2x2EC_dct0_mp1_MxMr2_MASK 0xffff +#define D18F2x2EC_dct0_mp1_Reserved_31_16_OFFSET 16 +#define D18F2x2EC_dct0_mp1_Reserved_31_16_WIDTH 16 +#define D18F2x2EC_dct0_mp1_Reserved_31_16_MASK 0xffff0000 + +/// D18F2x2EC_dct0_mp1 +typedef union { + struct { ///< + UINT32 MxMr2:16; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x2EC_dct0_mp1_STRUCT; + +// **** D18F2x2EC_dct1_mp1 Register Definition **** +// Address +#define D18F2x2EC_dct1_mp1_ADDRESS 0x2ec + +// Type +#define D18F2x2EC_dct1_mp1_TYPE TYPE_D18F2_dct1_mp1 +// Field Data +#define D18F2x2EC_dct1_mp1_MxMr2_OFFSET 0 +#define D18F2x2EC_dct1_mp1_MxMr2_WIDTH 16 +#define D18F2x2EC_dct1_mp1_MxMr2_MASK 0xffff +#define D18F2x2EC_dct1_mp1_Reserved_31_16_OFFSET 16 +#define D18F2x2EC_dct1_mp1_Reserved_31_16_WIDTH 16 +#define D18F2x2EC_dct1_mp1_Reserved_31_16_MASK 0xffff0000 + +/// D18F2x2EC_dct1_mp1 +typedef union { + struct { ///< + UINT32 MxMr2:16; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x2EC_dct1_mp1_STRUCT; + +// **** D18F2x2EC_dct1_mp0 Register Definition **** +// Address +#define D18F2x2EC_dct1_mp0_ADDRESS 0x2ec + +// Type +#define D18F2x2EC_dct1_mp0_TYPE TYPE_D18F2_dct1_mp0 +// Field Data +#define D18F2x2EC_dct1_mp0_MxMr2_OFFSET 0 +#define D18F2x2EC_dct1_mp0_MxMr2_WIDTH 16 +#define D18F2x2EC_dct1_mp0_MxMr2_MASK 0xffff +#define D18F2x2EC_dct1_mp0_Reserved_31_16_OFFSET 16 +#define D18F2x2EC_dct1_mp0_Reserved_31_16_WIDTH 16 +#define D18F2x2EC_dct1_mp0_Reserved_31_16_MASK 0xffff0000 + +/// D18F2x2EC_dct1_mp0 +typedef union { + struct { ///< + UINT32 MxMr2:16; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x2EC_dct1_mp0_STRUCT; + +// **** D18F2x2F0_dct1_mp1 Register Definition **** +// Address +#define D18F2x2F0_dct1_mp1_ADDRESS 0x2f0 + +// Type +#define D18F2x2F0_dct1_mp1_TYPE TYPE_D18F2_dct1_mp1 +// Field Data +#define D18F2x2F0_dct1_mp1_EffArbDis_OFFSET 0 +#define D18F2x2F0_dct1_mp1_EffArbDis_WIDTH 1 +#define D18F2x2F0_dct1_mp1_EffArbDis_MASK 0x1 +#define D18F2x2F0_dct1_mp1_Reserved_31_1_OFFSET 1 +#define D18F2x2F0_dct1_mp1_Reserved_31_1_WIDTH 31 +#define D18F2x2F0_dct1_mp1_Reserved_31_1_MASK 0xfffffffe + +/// D18F2x2F0_dct1_mp1 +typedef union { + struct { ///< + UINT32 EffArbDis:1 ; ///< + UINT32 Reserved_31_1:31; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x2F0_dct1_mp1_STRUCT; + +// **** D18F2x2F0_dct0_mp1 Register Definition **** +// Address +#define D18F2x2F0_dct0_mp1_ADDRESS 0x2f0 + +// Type +#define D18F2x2F0_dct0_mp1_TYPE TYPE_D18F2_dct0_mp1 +// Field Data +#define D18F2x2F0_dct0_mp1_EffArbDis_OFFSET 0 +#define D18F2x2F0_dct0_mp1_EffArbDis_WIDTH 1 +#define D18F2x2F0_dct0_mp1_EffArbDis_MASK 0x1 +#define D18F2x2F0_dct0_mp1_Reserved_31_1_OFFSET 1 +#define D18F2x2F0_dct0_mp1_Reserved_31_1_WIDTH 31 +#define D18F2x2F0_dct0_mp1_Reserved_31_1_MASK 0xfffffffe + +/// D18F2x2F0_dct0_mp1 +typedef union { + struct { ///< + UINT32 EffArbDis:1 ; ///< + UINT32 Reserved_31_1:31; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x2F0_dct0_mp1_STRUCT; + +// **** D18F2x2F0_dct1_mp0 Register Definition **** +// Address +#define D18F2x2F0_dct1_mp0_ADDRESS 0x2f0 + +// Type +#define D18F2x2F0_dct1_mp0_TYPE TYPE_D18F2_dct1_mp0 +// Field Data +#define D18F2x2F0_dct1_mp0_EffArbDis_OFFSET 0 +#define D18F2x2F0_dct1_mp0_EffArbDis_WIDTH 1 +#define D18F2x2F0_dct1_mp0_EffArbDis_MASK 0x1 +#define D18F2x2F0_dct1_mp0_Reserved_31_1_OFFSET 1 +#define D18F2x2F0_dct1_mp0_Reserved_31_1_WIDTH 31 +#define D18F2x2F0_dct1_mp0_Reserved_31_1_MASK 0xfffffffe + +/// D18F2x2F0_dct1_mp0 +typedef union { + struct { ///< + UINT32 EffArbDis:1 ; ///< + UINT32 Reserved_31_1:31; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x2F0_dct1_mp0_STRUCT; + +// **** D18F2x2F0_dct0_mp0 Register Definition **** +// Address +#define D18F2x2F0_dct0_mp0_ADDRESS 0x2f0 + +// Type +#define D18F2x2F0_dct0_mp0_TYPE TYPE_D18F2_dct0_mp0 +// Field Data +#define D18F2x2F0_dct0_mp0_EffArbDis_OFFSET 0 +#define D18F2x2F0_dct0_mp0_EffArbDis_WIDTH 1 +#define D18F2x2F0_dct0_mp0_EffArbDis_MASK 0x1 +#define D18F2x2F0_dct0_mp0_Reserved_31_1_OFFSET 1 +#define D18F2x2F0_dct0_mp0_Reserved_31_1_WIDTH 31 +#define D18F2x2F0_dct0_mp0_Reserved_31_1_MASK 0xfffffffe + +/// D18F2x2F0_dct0_mp0 +typedef union { + struct { ///< + UINT32 EffArbDis:1 ; ///< + UINT32 Reserved_31_1:31; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x2F0_dct0_mp0_STRUCT; + +// **** D18F2x400_dct1 Register Definition **** +// Address +#define D18F2x400_dct1_ADDRESS 0x400 + +// Type +#define D18F2x400_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x400_dct1_MctTokenLimit_OFFSET 0 +#define D18F2x400_dct1_MctTokenLimit_WIDTH 4 +#define D18F2x400_dct1_MctTokenLimit_MASK 0xf +#define D18F2x400_dct1_Reserved_7_4_OFFSET 4 +#define D18F2x400_dct1_Reserved_7_4_WIDTH 4 +#define D18F2x400_dct1_Reserved_7_4_MASK 0xf0 +#define D18F2x400_dct1_GmcTokenLimit_OFFSET 8 +#define D18F2x400_dct1_GmcTokenLimit_WIDTH 4 +#define D18F2x400_dct1_GmcTokenLimit_MASK 0xf00 +#define D18F2x400_dct1_Reserved_15_12_OFFSET 12 +#define D18F2x400_dct1_Reserved_15_12_WIDTH 4 +#define D18F2x400_dct1_Reserved_15_12_MASK 0xf000 +#define D18F2x400_dct1_Reserved_31_16_OFFSET 16 +#define D18F2x400_dct1_Reserved_31_16_WIDTH 16 +#define D18F2x400_dct1_Reserved_31_16_MASK 0xffff0000 + +/// D18F2x400_dct1 +typedef union { + struct { ///< + UINT32 MctTokenLimit:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 GmcTokenLimit:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x400_dct1_STRUCT; + +// **** D18F2x400_dct0 Register Definition **** +// Address +#define D18F2x400_dct0_ADDRESS 0x400 + +// Type +#define D18F2x400_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x400_dct0_MctTokenLimit_OFFSET 0 +#define D18F2x400_dct0_MctTokenLimit_WIDTH 4 +#define D18F2x400_dct0_MctTokenLimit_MASK 0xf +#define D18F2x400_dct0_Reserved_7_4_OFFSET 4 +#define D18F2x400_dct0_Reserved_7_4_WIDTH 4 +#define D18F2x400_dct0_Reserved_7_4_MASK 0xf0 +#define D18F2x400_dct0_GmcTokenLimit_OFFSET 8 +#define D18F2x400_dct0_GmcTokenLimit_WIDTH 4 +#define D18F2x400_dct0_GmcTokenLimit_MASK 0xf00 +#define D18F2x400_dct0_Reserved_15_12_OFFSET 12 +#define D18F2x400_dct0_Reserved_15_12_WIDTH 4 +#define D18F2x400_dct0_Reserved_15_12_MASK 0xf000 +#define D18F2x400_dct0_Reserved_31_16_OFFSET 16 +#define D18F2x400_dct0_Reserved_31_16_WIDTH 16 +#define D18F2x400_dct0_Reserved_31_16_MASK 0xffff0000 + +/// D18F2x400_dct0 +typedef union { + struct { ///< + UINT32 MctTokenLimit:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 GmcTokenLimit:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x400_dct0_STRUCT; + +// **** D18F2x404_dct0 Register Definition **** +// Address +#define D18F2x404_dct0_ADDRESS 0x404 + +// Type +#define D18F2x404_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x404_dct0_UrMctTokenLimit_OFFSET 0 +#define D18F2x404_dct0_UrMctTokenLimit_WIDTH 4 +#define D18F2x404_dct0_UrMctTokenLimit_MASK 0xf +#define D18F2x404_dct0_UrMctMinTokens_OFFSET 4 +#define D18F2x404_dct0_UrMctMinTokens_WIDTH 4 +#define D18F2x404_dct0_UrMctMinTokens_MASK 0xf0 +#define D18F2x404_dct0_UrGmcTokenLimit_OFFSET 8 +#define D18F2x404_dct0_UrGmcTokenLimit_WIDTH 4 +#define D18F2x404_dct0_UrGmcTokenLimit_MASK 0xf00 +#define D18F2x404_dct0_UrGmcMinTokens_OFFSET 12 +#define D18F2x404_dct0_UrGmcMinTokens_WIDTH 4 +#define D18F2x404_dct0_UrGmcMinTokens_MASK 0xf000 +#define D18F2x404_dct0_UrgentTknDis_OFFSET 16 +#define D18F2x404_dct0_UrgentTknDis_WIDTH 1 +#define D18F2x404_dct0_UrgentTknDis_MASK 0x10000 +#define D18F2x404_dct0_Reserved_31_17_OFFSET 17 +#define D18F2x404_dct0_Reserved_31_17_WIDTH 15 +#define D18F2x404_dct0_Reserved_31_17_MASK 0xfffe0000 + +/// D18F2x404_dct0 +typedef union { + struct { ///< + UINT32 UrMctTokenLimit:4 ; ///< + UINT32 UrMctMinTokens:4 ; ///< + UINT32 UrGmcTokenLimit:4 ; ///< + UINT32 UrGmcMinTokens:4 ; ///< + UINT32 UrgentTknDis:1 ; ///< + UINT32 Reserved_31_17:15; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x404_dct0_STRUCT; + +// **** D18F2x404_dct1 Register Definition **** +// Address +#define D18F2x404_dct1_ADDRESS 0x404 + +// Type +#define D18F2x404_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x404_dct1_UrMctTokenLimit_OFFSET 0 +#define D18F2x404_dct1_UrMctTokenLimit_WIDTH 4 +#define D18F2x404_dct1_UrMctTokenLimit_MASK 0xf +#define D18F2x404_dct1_UrMctMinTokens_OFFSET 4 +#define D18F2x404_dct1_UrMctMinTokens_WIDTH 4 +#define D18F2x404_dct1_UrMctMinTokens_MASK 0xf0 +#define D18F2x404_dct1_UrGmcTokenLimit_OFFSET 8 +#define D18F2x404_dct1_UrGmcTokenLimit_WIDTH 4 +#define D18F2x404_dct1_UrGmcTokenLimit_MASK 0xf00 +#define D18F2x404_dct1_UrGmcMinTokens_OFFSET 12 +#define D18F2x404_dct1_UrGmcMinTokens_WIDTH 4 +#define D18F2x404_dct1_UrGmcMinTokens_MASK 0xf000 +#define D18F2x404_dct1_UrgentTknDis_OFFSET 16 +#define D18F2x404_dct1_UrgentTknDis_WIDTH 1 +#define D18F2x404_dct1_UrgentTknDis_MASK 0x10000 +#define D18F2x404_dct1_Reserved_31_17_OFFSET 17 +#define D18F2x404_dct1_Reserved_31_17_WIDTH 15 +#define D18F2x404_dct1_Reserved_31_17_MASK 0xfffe0000 + +/// D18F2x404_dct1 +typedef union { + struct { ///< + UINT32 UrMctTokenLimit:4 ; ///< + UINT32 UrMctMinTokens:4 ; ///< + UINT32 UrGmcTokenLimit:4 ; ///< + UINT32 UrGmcMinTokens:4 ; ///< + UINT32 UrgentTknDis:1 ; ///< + UINT32 Reserved_31_17:15; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x404_dct1_STRUCT; + +// **** D18F2x408_dct1 Register Definition **** +// Address +#define D18F2x408_dct1_ADDRESS 0x408 + +// Type +#define D18F2x408_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x408_dct1_CpuElevPrioDis_OFFSET 0 +#define D18F2x408_dct1_CpuElevPrioDis_WIDTH 1 +#define D18F2x408_dct1_CpuElevPrioDis_MASK 0x1 +#define D18F2x408_dct1_TokenAllocSelect_OFFSET 1 +#define D18F2x408_dct1_TokenAllocSelect_WIDTH 1 +#define D18F2x408_dct1_TokenAllocSelect_MASK 0x2 +#define D18F2x408_dct1_Reserved_30_2_OFFSET 2 +#define D18F2x408_dct1_Reserved_30_2_WIDTH 29 +#define D18F2x408_dct1_Reserved_30_2_MASK 0x7ffffffc +#define D18F2x408_dct1_DisHalfNclkPwrGate_OFFSET 31 +#define D18F2x408_dct1_DisHalfNclkPwrGate_WIDTH 1 +#define D18F2x408_dct1_DisHalfNclkPwrGate_MASK 0x80000000 + +/// D18F2x408_dct1 +typedef union { + struct { ///< + UINT32 CpuElevPrioDis:1 ; ///< + UINT32 TokenAllocSelect:1 ; ///< + UINT32 Reserved_30_2:29; ///< + UINT32 DisHalfNclkPwrGate:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x408_dct1_STRUCT; + +// **** D18F2x408_dct0 Register Definition **** +// Address +#define D18F2x408_dct0_ADDRESS 0x408 + +// Type +#define D18F2x408_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x408_dct0_CpuElevPrioDis_OFFSET 0 +#define D18F2x408_dct0_CpuElevPrioDis_WIDTH 1 +#define D18F2x408_dct0_CpuElevPrioDis_MASK 0x1 +#define D18F2x408_dct0_TokenAllocSelect_OFFSET 1 +#define D18F2x408_dct0_TokenAllocSelect_WIDTH 1 +#define D18F2x408_dct0_TokenAllocSelect_MASK 0x2 +#define D18F2x408_dct0_Reserved_30_2_OFFSET 2 +#define D18F2x408_dct0_Reserved_30_2_WIDTH 29 +#define D18F2x408_dct0_Reserved_30_2_MASK 0x7ffffffc +#define D18F2x408_dct0_DisHalfNclkPwrGate_OFFSET 31 +#define D18F2x408_dct0_DisHalfNclkPwrGate_WIDTH 1 +#define D18F2x408_dct0_DisHalfNclkPwrGate_MASK 0x80000000 + +/// D18F2x408_dct0 +typedef union { + struct { ///< + UINT32 CpuElevPrioDis:1 ; ///< + UINT32 TokenAllocSelect:1 ; ///< + UINT32 Reserved_30_2:29; ///< + UINT32 DisHalfNclkPwrGate:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x408_dct0_STRUCT; + +// **** D18F2x420_dct0 Register Definition **** +// Address +#define D18F2x420_dct0_ADDRESS 0x420 + +// Type +#define D18F2x420_dct0_TYPE TYPE_D18F2_dct0 +// Field Data +#define D18F2x420_dct0_CmdRdPtrInit_OFFSET 0 +#define D18F2x420_dct0_CmdRdPtrInit_WIDTH 4 +#define D18F2x420_dct0_CmdRdPtrInit_MASK 0xf +#define D18F2x420_dct0_Reserved_7_4_OFFSET 4 +#define D18F2x420_dct0_Reserved_7_4_WIDTH 4 +#define D18F2x420_dct0_Reserved_7_4_MASK 0xf0 +#define D18F2x420_dct0_SbRdPtrInit_OFFSET 8 +#define D18F2x420_dct0_SbRdPtrInit_WIDTH 4 +#define D18F2x420_dct0_SbRdPtrInit_MASK 0xf00 +#define D18F2x420_dct0_Reserved_31_12_OFFSET 12 +#define D18F2x420_dct0_Reserved_31_12_WIDTH 20 +#define D18F2x420_dct0_Reserved_31_12_MASK 0xfffff000 + +/// D18F2x420_dct0 +typedef union { + struct { ///< + UINT32 CmdRdPtrInit:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 SbRdPtrInit:4 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x420_dct0_STRUCT; + +// **** D18F2x420_dct1 Register Definition **** +// Address +#define D18F2x420_dct1_ADDRESS 0x420 + +// Type +#define D18F2x420_dct1_TYPE TYPE_D18F2_dct1 +// Field Data +#define D18F2x420_dct1_CmdRdPtrInit_OFFSET 0 +#define D18F2x420_dct1_CmdRdPtrInit_WIDTH 4 +#define D18F2x420_dct1_CmdRdPtrInit_MASK 0xf +#define D18F2x420_dct1_Reserved_7_4_OFFSET 4 +#define D18F2x420_dct1_Reserved_7_4_WIDTH 4 +#define D18F2x420_dct1_Reserved_7_4_MASK 0xf0 +#define D18F2x420_dct1_SbRdPtrInit_OFFSET 8 +#define D18F2x420_dct1_SbRdPtrInit_WIDTH 4 +#define D18F2x420_dct1_SbRdPtrInit_MASK 0xf00 +#define D18F2x420_dct1_Reserved_31_12_OFFSET 12 +#define D18F2x420_dct1_Reserved_31_12_WIDTH 20 +#define D18F2x420_dct1_Reserved_31_12_MASK 0xfffff000 + +/// D18F2x420_dct1 +typedef union { + struct { ///< + UINT32 CmdRdPtrInit:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 SbRdPtrInit:4 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x420_dct1_STRUCT; + +// **** D18F3x00 Register Definition **** +// Address +#define D18F3x00_ADDRESS 0x0 + +// Type +#define D18F3x00_TYPE TYPE_D18F3 +// Field Data +#define D18F3x00_VendorID_OFFSET 0 +#define D18F3x00_VendorID_WIDTH 16 +#define D18F3x00_VendorID_MASK 0xffff +#define D18F3x00_DeviceID_OFFSET 16 +#define D18F3x00_DeviceID_WIDTH 16 +#define D18F3x00_DeviceID_MASK 0xffff0000 + +/// D18F3x00 +typedef union { + struct { ///< + UINT32 VendorID:16; ///< + UINT32 DeviceID:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x00_STRUCT; + +// **** D18F3x04 Register Definition **** +// Address +#define D18F3x04_ADDRESS 0x4 + +// Type +#define D18F3x04_TYPE TYPE_D18F3 +// Field Data +#define D18F3x04_Command_OFFSET 0 +#define D18F3x04_Command_WIDTH 16 +#define D18F3x04_Command_MASK 0xffff +#define D18F3x04_Status_OFFSET 16 +#define D18F3x04_Status_WIDTH 16 +#define D18F3x04_Status_MASK 0xffff0000 + +/// D18F3x04 +typedef union { + struct { ///< + UINT32 Command:16; ///< + UINT32 Status:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x04_STRUCT; + +// **** D18F3x08 Register Definition **** +// Address +#define D18F3x08_ADDRESS 0x8 + +// Type +#define D18F3x08_TYPE TYPE_D18F3 +// Field Data +#define D18F3x08_RevID_OFFSET 0 +#define D18F3x08_RevID_WIDTH 8 +#define D18F3x08_RevID_MASK 0xff +#define D18F3x08_ClassCode_OFFSET 8 +#define D18F3x08_ClassCode_WIDTH 24 +#define D18F3x08_ClassCode_MASK 0xffffff00 + +/// D18F3x08 +typedef union { + struct { ///< + UINT32 RevID:8 ; ///< + UINT32 ClassCode:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x08_STRUCT; + +// **** D18F3x0C Register Definition **** +// Address +#define D18F3x0C_ADDRESS 0xc + +// Type +#define D18F3x0C_TYPE TYPE_D18F3 +// Field Data +#define D18F3x0C_HeaderTypeReg_OFFSET 0 +#define D18F3x0C_HeaderTypeReg_WIDTH 32 +#define D18F3x0C_HeaderTypeReg_MASK 0xffffffff + +/// D18F3x0C +typedef union { + struct { ///< + UINT32 HeaderTypeReg:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x0C_STRUCT; + +// **** D18F3x34 Register Definition **** +// Address +#define D18F3x34_ADDRESS 0x34 + +// Type +#define D18F3x34_TYPE TYPE_D18F3 +// Field Data +#define D18F3x34_CapPtr_OFFSET 0 +#define D18F3x34_CapPtr_WIDTH 8 +#define D18F3x34_CapPtr_MASK 0xff +#define D18F3x34_Reserved_31_8_OFFSET 8 +#define D18F3x34_Reserved_31_8_WIDTH 24 +#define D18F3x34_Reserved_31_8_MASK 0xffffff00 + +/// D18F3x34 +typedef union { + struct { ///< + UINT32 CapPtr:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x34_STRUCT; + +// **** D18F3x40 Register Definition **** +// Address +#define D18F3x40_ADDRESS 0x40 + +// Type +#define D18F3x40_TYPE TYPE_D18F3 +// Field Data +#define D18F3x40_Unused_4_0_OFFSET 0 +#define D18F3x40_Unused_4_0_WIDTH 5 +#define D18F3x40_Unused_4_0_MASK 0x1f +#define D18F3x40_SyncPktEn_OFFSET 5 +#define D18F3x40_SyncPktEn_WIDTH 1 +#define D18F3x40_SyncPktEn_MASK 0x20 +#define D18F3x40_Unused_7_6_OFFSET 6 +#define D18F3x40_Unused_7_6_WIDTH 2 +#define D18F3x40_Unused_7_6_MASK 0xc0 +#define D18F3x40_MstrAbortEn_OFFSET 8 +#define D18F3x40_MstrAbortEn_WIDTH 1 +#define D18F3x40_MstrAbortEn_MASK 0x100 +#define D18F3x40_TgtAbortEn_OFFSET 9 +#define D18F3x40_TgtAbortEn_WIDTH 1 +#define D18F3x40_TgtAbortEn_MASK 0x200 +#define D18F3x40_Unused_10_10_OFFSET 10 +#define D18F3x40_Unused_10_10_WIDTH 1 +#define D18F3x40_Unused_10_10_MASK 0x400 +#define D18F3x40_AtomicRMWEn_OFFSET 11 +#define D18F3x40_AtomicRMWEn_WIDTH 1 +#define D18F3x40_AtomicRMWEn_MASK 0x800 +#define D18F3x40_WDTRptEn_OFFSET 12 +#define D18F3x40_WDTRptEn_WIDTH 1 +#define D18F3x40_WDTRptEn_MASK 0x1000 +#define D18F3x40_Unused_15_13_OFFSET 13 +#define D18F3x40_Unused_15_13_WIDTH 3 +#define D18F3x40_Unused_15_13_MASK 0xe000 +#define D18F3x40_NbIntProtEn_OFFSET 16 +#define D18F3x40_NbIntProtEn_WIDTH 1 +#define D18F3x40_NbIntProtEn_MASK 0x10000 +#define D18F3x40_CpPktDatEn_OFFSET 17 +#define D18F3x40_CpPktDatEn_WIDTH 1 +#define D18F3x40_CpPktDatEn_MASK 0x20000 +#define D18F3x40_Unused_24_18_OFFSET 18 +#define D18F3x40_Unused_24_18_WIDTH 7 +#define D18F3x40_Unused_24_18_MASK 0x1fc0000 +#define D18F3x40_UsPwDatErrEn_OFFSET 25 +#define D18F3x40_UsPwDatErrEn_WIDTH 1 +#define D18F3x40_UsPwDatErrEn_MASK 0x2000000 +#define D18F3x40_NbArrayParEn_OFFSET 26 +#define D18F3x40_NbArrayParEn_WIDTH 1 +#define D18F3x40_NbArrayParEn_MASK 0x4000000 +#define D18F3x40_Unused_29_27_OFFSET 27 +#define D18F3x40_Unused_29_27_WIDTH 3 +#define D18F3x40_Unused_29_27_MASK 0x38000000 +#define D18F3x40_Unused_30_30_OFFSET 30 +#define D18F3x40_Unused_30_30_WIDTH 1 +#define D18F3x40_Unused_30_30_MASK 0x40000000 +#define D18F3x40_McaCpuDatErrEn_OFFSET 31 +#define D18F3x40_McaCpuDatErrEn_WIDTH 1 +#define D18F3x40_McaCpuDatErrEn_MASK 0x80000000 + +/// D18F3x40 +typedef union { + struct { ///< + UINT32 Unused_4_0:5 ; ///< + UINT32 SyncPktEn:1 ; ///< + UINT32 Unused_7_6:2 ; ///< + UINT32 MstrAbortEn:1 ; ///< + UINT32 TgtAbortEn:1 ; ///< + UINT32 Unused_10_10:1 ; ///< + UINT32 AtomicRMWEn:1 ; ///< + UINT32 WDTRptEn:1 ; ///< + UINT32 Unused_15_13:3 ; ///< + UINT32 NbIntProtEn:1 ; ///< + UINT32 CpPktDatEn:1 ; ///< + UINT32 Unused_24_18:7 ; ///< + UINT32 UsPwDatErrEn:1 ; ///< + UINT32 NbArrayParEn:1 ; ///< + UINT32 Unused_29_27:3 ; ///< + UINT32 Unused_30_30:1 ; ///< + UINT32 McaCpuDatErrEn:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x40_STRUCT; + +// **** D18F3x44 Register Definition **** +// Address +#define D18F3x44_ADDRESS 0x44 + +// Type +#define D18F3x44_TYPE TYPE_D18F3 +// Field Data +#define D18F3x44_Reserved_0_0_OFFSET 0 +#define D18F3x44_Reserved_0_0_WIDTH 1 +#define D18F3x44_Reserved_0_0_MASK 0x1 +#define D18F3x44_CpuRdDatErrEn_OFFSET 1 +#define D18F3x44_CpuRdDatErrEn_WIDTH 1 +#define D18F3x44_CpuRdDatErrEn_MASK 0x2 +#define D18F3x44_SyncPktGenDis_OFFSET 3 +#define D18F3x44_SyncPktGenDis_WIDTH 1 +#define D18F3x44_SyncPktGenDis_MASK 0x8 +#define D18F3x44_SyncPktPropDis_OFFSET 4 +#define D18F3x44_SyncPktPropDis_WIDTH 1 +#define D18F3x44_SyncPktPropDis_MASK 0x10 +#define D18F3x44_IoMstAbortDis_OFFSET 5 +#define D18F3x44_IoMstAbortDis_WIDTH 1 +#define D18F3x44_IoMstAbortDis_MASK 0x20 +#define D18F3x44_CpuErrDis_OFFSET 6 +#define D18F3x44_CpuErrDis_WIDTH 1 +#define D18F3x44_CpuErrDis_MASK 0x40 +#define D18F3x44_IoErrDis_OFFSET 7 +#define D18F3x44_IoErrDis_WIDTH 1 +#define D18F3x44_IoErrDis_MASK 0x80 +#define D18F3x44_WDTDis_OFFSET 8 +#define D18F3x44_WDTDis_WIDTH 1 +#define D18F3x44_WDTDis_MASK 0x100 +#define D18F3x44_WDTCntSel_2_0__OFFSET 9 +#define D18F3x44_WDTCntSel_2_0__WIDTH 3 +#define D18F3x44_WDTCntSel_2_0__MASK 0xe00 +#define D18F3x44_WDTBaseSel_OFFSET 12 +#define D18F3x44_WDTBaseSel_WIDTH 2 +#define D18F3x44_WDTBaseSel_MASK 0x3000 +#define D18F3x44_GenCrcErrByte0_OFFSET 16 +#define D18F3x44_GenCrcErrByte0_WIDTH 1 +#define D18F3x44_GenCrcErrByte0_MASK 0x10000 +#define D18F3x44_GenCrcErrByte1_OFFSET 17 +#define D18F3x44_GenCrcErrByte1_WIDTH 1 +#define D18F3x44_GenCrcErrByte1_MASK 0x20000 +#define D18F3x44_GenSubLinkSel_OFFSET 18 +#define D18F3x44_GenSubLinkSel_WIDTH 2 +#define D18F3x44_GenSubLinkSel_MASK 0xc0000 +#define D18F3x44_Reserved_23_22_WIDTH 2 +#define D18F3x44_Reserved_23_22_MASK 0xc00000 +#define D18F3x44_IoRdDatErrEn_OFFSET 24 +#define D18F3x44_IoRdDatErrEn_WIDTH 1 +#define D18F3x44_IoRdDatErrEn_MASK 0x1000000 +#define D18F3x44_DisPciCfgCpuErrRsp_OFFSET 25 +#define D18F3x44_DisPciCfgCpuErrRsp_WIDTH 1 +#define D18F3x44_DisPciCfgCpuErrRsp_MASK 0x2000000 +#define D18F3x44_FlagMcaCorrErr_OFFSET 26 +#define D18F3x44_FlagMcaCorrErr_WIDTH 1 +#define D18F3x44_FlagMcaCorrErr_MASK 0x4000000 +#define D18F3x44_NbMcaToMstCpuEn_OFFSET 27 +#define D18F3x44_NbMcaToMstCpuEn_WIDTH 1 +#define D18F3x44_NbMcaToMstCpuEn_MASK 0x8000000 +#define D18F3x44_DisTgtAbortCpuErrRsp_OFFSET 28 +#define D18F3x44_DisTgtAbortCpuErrRsp_WIDTH 1 +#define D18F3x44_DisTgtAbortCpuErrRsp_MASK 0x10000000 +#define D18F3x44_DisMstAbortCpuErrRsp_OFFSET 29 +#define D18F3x44_DisMstAbortCpuErrRsp_WIDTH 1 +#define D18F3x44_DisMstAbortCpuErrRsp_MASK 0x20000000 +#define D18F3x44_SyncOnDramAdrParErrEn_OFFSET 30 +#define D18F3x44_SyncOnDramAdrParErrEn_WIDTH 1 +#define D18F3x44_SyncOnDramAdrParErrEn_MASK 0x40000000 +#define D18F3x44_NbMcaLogEn_OFFSET 31 +#define D18F3x44_NbMcaLogEn_WIDTH 1 +#define D18F3x44_NbMcaLogEn_MASK 0x80000000 + +/// D18F3x44 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 CpuRdDatErrEn:1 ; ///< + UINT32 SyncOnUcEccEn:1 ; ///< + UINT32 SyncPktGenDis:1 ; ///< + UINT32 SyncPktPropDis:1 ; ///< + UINT32 IoMstAbortDis:1 ; ///< + UINT32 CpuErrDis:1 ; ///< + UINT32 IoErrDis:1 ; ///< + UINT32 WDTDis:1 ; ///< + UINT32 WDTCntSel_2_0_:3 ; ///< + UINT32 WDTBaseSel:2 ; ///< + UINT32 :2 ; ///< + UINT32 GenCrcErrByte0:1 ; ///< + UINT32 GenCrcErrByte1:1 ; ///< + UINT32 GenSubLinkSel:2 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 Reserved_23_22:2 ; ///< + UINT32 IoRdDatErrEn:1 ; ///< + UINT32 DisPciCfgCpuErrRsp:1 ; ///< + UINT32 FlagMcaCorrErr:1 ; ///< + UINT32 NbMcaToMstCpuEn:1 ; ///< + UINT32 DisTgtAbortCpuErrRsp:1 ; ///< + UINT32 DisMstAbortCpuErrRsp:1 ; ///< + UINT32 SyncOnDramAdrParErrEn:1 ; ///< + UINT32 NbMcaLogEn:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x44_STRUCT; + +// **** D18F3x48 Register Definition **** +// Address +#define D18F3x48_ADDRESS 0x48 + +// Type +#define D18F3x48_TYPE TYPE_D18F3 +// Field Data +#define D18F3x48_ErrorCode_OFFSET 0 +#define D18F3x48_ErrorCode_WIDTH 16 +#define D18F3x48_ErrorCode_MASK 0xffff +#define D18F3x48_ErrorCodeExt_OFFSET 16 +#define D18F3x48_ErrorCodeExt_WIDTH 5 +#define D18F3x48_ErrorCodeExt_MASK 0x1f0000 +#define D18F3x48_Reserved_23_21_OFFSET 21 +#define D18F3x48_Reserved_23_21_WIDTH 3 +#define D18F3x48_Reserved_23_21_MASK 0xe00000 +#define D18F3x48_Reserved_31_24_OFFSET 24 +#define D18F3x48_Reserved_31_24_WIDTH 8 +#define D18F3x48_Reserved_31_24_MASK 0xff000000 + +/// D18F3x48 +typedef union { + struct { ///< + UINT32 ErrorCode:16; ///< + UINT32 ErrorCodeExt:5 ; ///< + UINT32 Reserved_23_21:3 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x48_STRUCT; + +// **** D18F3x4C Register Definition **** +// Address +#define D18F3x4C_ADDRESS 0x4c + +// Type +#define D18F3x4C_TYPE TYPE_D18F3 +// Field Data +#define D18F3x4C_ErrCoreId_OFFSET 0 +#define D18F3x4C_ErrCoreId_WIDTH 4 +#define D18F3x4C_ErrCoreId_MASK 0xf +#define D18F3x4C_Reserved_39_37_OFFSET 5 +#define D18F3x4C_Reserved_39_37_WIDTH 3 +#define D18F3x4C_Reserved_39_37_MASK 0xe0 +#define D18F3x4C_Reserved_40_40_OFFSET 8 +#define D18F3x4C_Reserved_40_40_WIDTH 1 +#define D18F3x4C_Reserved_40_40_MASK 0x100 +#define D18F3x4C_SubLink_OFFSET 9 +#define D18F3x4C_SubLink_WIDTH 1 +#define D18F3x4C_SubLink_MASK 0x200 +#define D18F3x4C_Reserved_43_42_OFFSET 10 +#define D18F3x4C_Reserved_43_42_WIDTH 2 +#define D18F3x4C_Reserved_43_42_MASK 0xc00 +#define D18F3x4C_Reserved_54_45_OFFSET 13 +#define D18F3x4C_Reserved_54_45_WIDTH 10 +#define D18F3x4C_Reserved_54_45_MASK 0x7fe000 +#define D18F3x4C_Reserved_55_55_OFFSET 23 +#define D18F3x4C_Reserved_55_55_WIDTH 1 +#define D18F3x4C_Reserved_55_55_MASK 0x800000 +#define D18F3x4C_ErrCoreIdVal_OFFSET 24 +#define D18F3x4C_ErrCoreIdVal_WIDTH 1 +#define D18F3x4C_ErrCoreIdVal_MASK 0x1000000 +#define D18F3x4C_PCC_OFFSET 25 +#define D18F3x4C_PCC_WIDTH 1 +#define D18F3x4C_PCC_MASK 0x2000000 +#define D18F3x4C_AddrV_OFFSET 26 +#define D18F3x4C_AddrV_WIDTH 1 +#define D18F3x4C_AddrV_MASK 0x4000000 +#define D18F3x4C_MiscV_OFFSET 27 +#define D18F3x4C_MiscV_WIDTH 1 +#define D18F3x4C_MiscV_MASK 0x8000000 +#define D18F3x4C_En_OFFSET 28 +#define D18F3x4C_En_WIDTH 1 +#define D18F3x4C_En_MASK 0x10000000 +#define D18F3x4C_UC_OFFSET 29 +#define D18F3x4C_UC_WIDTH 1 +#define D18F3x4C_UC_MASK 0x20000000 +#define D18F3x4C_Overflow_OFFSET 30 +#define D18F3x4C_Overflow_WIDTH 1 +#define D18F3x4C_Overflow_MASK 0x40000000 +#define D18F3x4C_Val_OFFSET 31 +#define D18F3x4C_Val_WIDTH 1 +#define D18F3x4C_Val_MASK 0x80000000 + +/// D18F3x4C +typedef union { + struct { ///< + UINT32 ErrCoreId:4 ; ///< + UINT32 Link:1 ; ///< + UINT32 Reserved_39_37:3 ; ///< + UINT32 Reserved_40_40:1 ; ///< + UINT32 SubLink:1 ; ///< + UINT32 Reserved_43_42:2 ; ///< + UINT32 Reserved_44_44:1 ; ///< + UINT32 Reserved_54_45:10; ///< + UINT32 Reserved_55_55:1 ; ///< + UINT32 ErrCoreIdVal:1 ; ///< + UINT32 PCC:1 ; ///< + UINT32 AddrV:1 ; ///< + UINT32 MiscV:1 ; ///< + UINT32 En:1 ; ///< + UINT32 UC:1 ; ///< + UINT32 Overflow:1 ; ///< + UINT32 Val:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x4C_STRUCT; + +// **** D18F3x50 Register Definition **** +// Address +#define D18F3x50_ADDRESS 0x50 + +// Type +#define D18F3x50_TYPE TYPE_D18F3 +// Field Data +#define D18F3x50_Reserved_0_0_OFFSET 0 +#define D18F3x50_Reserved_0_0_WIDTH 1 +#define D18F3x50_Reserved_0_0_MASK 0x1 +#define D18F3x50_ErrAddr_31_1__OFFSET 1 +#define D18F3x50_ErrAddr_31_1__WIDTH 31 +#define D18F3x50_ErrAddr_31_1__MASK 0xfffffffe + +/// D18F3x50 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 ErrAddr_31_1_:31; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x50_STRUCT; + +// **** D18F3x54 Register Definition **** +// Address +#define D18F3x54_ADDRESS 0x54 + +// Type +#define D18F3x54_TYPE TYPE_D18F3 +// Field Data +#define D18F3x54_ErrAddr_47_32__OFFSET 0 +#define D18F3x54_ErrAddr_47_32__WIDTH 16 +#define D18F3x54_ErrAddr_47_32__MASK 0xffff +#define D18F3x54_Reserved_63_48_OFFSET 16 +#define D18F3x54_Reserved_63_48_WIDTH 16 +#define D18F3x54_Reserved_63_48_MASK 0xffff0000 + +/// D18F3x54 +typedef union { + struct { ///< + UINT32 ErrAddr_47_32_:16; ///< + UINT32 Reserved_63_48:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x54_STRUCT; + +// **** D18F3x64 Register Definition **** +// Address +#define D18F3x64_ADDRESS 0x64 + +// Type +#define D18F3x64_TYPE TYPE_D18F3 +// Field Data +#define D18F3x64_HtcEn_OFFSET 0 +#define D18F3x64_HtcEn_WIDTH 1 +#define D18F3x64_HtcEn_MASK 0x1 +#define D18F3x64_Reserved_3_1_OFFSET 1 +#define D18F3x64_Reserved_3_1_WIDTH 3 +#define D18F3x64_Reserved_3_1_MASK 0xe +#define D18F3x64_HtcAct_OFFSET 4 +#define D18F3x64_HtcAct_WIDTH 1 +#define D18F3x64_HtcAct_MASK 0x10 +#define D18F3x64_HtcActSts_OFFSET 5 +#define D18F3x64_HtcActSts_WIDTH 1 +#define D18F3x64_HtcActSts_MASK 0x20 +#define D18F3x64_PslApicHiEn_OFFSET 6 +#define D18F3x64_PslApicHiEn_WIDTH 1 +#define D18F3x64_PslApicHiEn_MASK 0x40 +#define D18F3x64_PslApicLoEn_OFFSET 7 +#define D18F3x64_PslApicLoEn_WIDTH 1 +#define D18F3x64_PslApicLoEn_MASK 0x80 +#define D18F3x64_Reserved_15_8_OFFSET 8 +#define D18F3x64_Reserved_15_8_WIDTH 8 +#define D18F3x64_Reserved_15_8_MASK 0xff00 +#define D18F3x64_HtcTmpLmt_OFFSET 16 +#define D18F3x64_HtcTmpLmt_WIDTH 7 +#define D18F3x64_HtcTmpLmt_MASK 0x7f0000 +#define D18F3x64_HtcSlewSel_OFFSET 23 +#define D18F3x64_HtcSlewSel_WIDTH 1 +#define D18F3x64_HtcSlewSel_MASK 0x800000 +#define D18F3x64_HtcHystLmt_OFFSET 24 +#define D18F3x64_HtcHystLmt_WIDTH 4 +#define D18F3x64_HtcHystLmt_MASK 0xf000000 +#define D18F3x64_HtcPstateLimit_OFFSET 28 +#define D18F3x64_HtcPstateLimit_WIDTH 3 +#define D18F3x64_HtcPstateLimit_MASK 0x70000000 +#define D18F3x64_Reserved_31_31_OFFSET 31 +#define D18F3x64_Reserved_31_31_WIDTH 1 +#define D18F3x64_Reserved_31_31_MASK 0x80000000 + +/// D18F3x64 +typedef union { + struct { ///< + UINT32 HtcEn:1 ; ///< + UINT32 Reserved_3_1:3 ; ///< + UINT32 HtcAct:1 ; ///< + UINT32 HtcActSts:1 ; ///< + UINT32 PslApicHiEn:1 ; ///< + UINT32 PslApicLoEn:1 ; ///< + UINT32 Reserved_15_8:8 ; ///< + UINT32 HtcTmpLmt:7 ; ///< + UINT32 HtcSlewSel:1 ; ///< + UINT32 HtcHystLmt:4 ; ///< + UINT32 HtcPstateLimit:3 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x64_STRUCT; + +// **** D18F3x68 Register Definition **** +// Address +#define D18F3x68_ADDRESS 0x68 + +// Type +#define D18F3x68_TYPE TYPE_D18F3 +// Field Data +#define D18F3x68_Reserved_4_0_OFFSET 0 +#define D18F3x68_Reserved_4_0_WIDTH 5 +#define D18F3x68_Reserved_4_0_MASK 0x1f +#define D18F3x68_SwPstateLimitEn_OFFSET 5 +#define D18F3x68_SwPstateLimitEn_WIDTH 1 +#define D18F3x68_SwPstateLimitEn_MASK 0x20 +#define D18F3x68_Reserved_27_6_OFFSET 6 +#define D18F3x68_Reserved_27_6_WIDTH 22 +#define D18F3x68_Reserved_27_6_MASK 0xfffffc0 +#define D18F3x68_SwPstateLimit_OFFSET 28 +#define D18F3x68_SwPstateLimit_WIDTH 3 +#define D18F3x68_SwPstateLimit_MASK 0x70000000 +#define D18F3x68_Reserved_31_31_OFFSET 31 +#define D18F3x68_Reserved_31_31_WIDTH 1 +#define D18F3x68_Reserved_31_31_MASK 0x80000000 + +/// D18F3x68 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 SwPstateLimitEn:1 ; ///< + UINT32 Reserved_27_6:22; ///< + UINT32 SwPstateLimit:3 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x68_STRUCT; + +// **** D18F3x6C Register Definition **** +// Address +#define D18F3x6C_ADDRESS 0x6c + +// Type +#define D18F3x6C_TYPE TYPE_D18F3 +// Field Data +#define D18F3x6C_UpReqDBC_OFFSET 0 +#define D18F3x6C_UpReqDBC_WIDTH 3 +#define D18F3x6C_UpReqDBC_MASK 0x7 +#define D18F3x6C_Reserved_3_3_OFFSET 3 +#define D18F3x6C_Reserved_3_3_WIDTH 1 +#define D18F3x6C_Reserved_3_3_MASK 0x8 +#define D18F3x6C_DnReqDBC_OFFSET 4 +#define D18F3x6C_DnReqDBC_WIDTH 2 +#define D18F3x6C_DnReqDBC_MASK 0x30 +#define D18F3x6C_DnRspDBC_OFFSET 6 +#define D18F3x6C_DnRspDBC_WIDTH 2 +#define D18F3x6C_DnRspDBC_MASK 0xc0 +#define D18F3x6C_Reserved_15_8_OFFSET 8 +#define D18F3x6C_Reserved_15_8_WIDTH 8 +#define D18F3x6C_Reserved_15_8_MASK 0xff00 +#define D18F3x6C_UpRspDBC_OFFSET 16 +#define D18F3x6C_UpRspDBC_WIDTH 3 +#define D18F3x6C_UpRspDBC_MASK 0x70000 +#define D18F3x6C_Reserved_27_19_OFFSET 19 +#define D18F3x6C_Reserved_27_19_WIDTH 9 +#define D18F3x6C_Reserved_27_19_MASK 0xff80000 +#define D18F3x6C_IsocRspDBC_OFFSET 28 +#define D18F3x6C_IsocRspDBC_WIDTH 3 +#define D18F3x6C_IsocRspDBC_MASK 0x70000000 +#define D18F3x6C_Reserved_31_31_OFFSET 31 +#define D18F3x6C_Reserved_31_31_WIDTH 1 +#define D18F3x6C_Reserved_31_31_MASK 0x80000000 + +/// D18F3x6C +typedef union { + struct { ///< + UINT32 UpReqDBC:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 DnReqDBC:2 ; ///< + UINT32 DnRspDBC:2 ; ///< + UINT32 Reserved_15_8:8 ; ///< + UINT32 UpRspDBC:3 ; ///< + UINT32 Reserved_27_19:9 ; ///< + UINT32 IsocRspDBC:3 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x6C_STRUCT; + +// **** D18F3x70 Register Definition **** +// Address +#define D18F3x70_ADDRESS 0x70 + +// Type +#define D18F3x70_TYPE TYPE_D18F3 +// Field Data +#define D18F3x70_UpReqCBC_OFFSET 0 +#define D18F3x70_UpReqCBC_WIDTH 3 +#define D18F3x70_UpReqCBC_MASK 0x7 +#define D18F3x70_Reserved_3_3_OFFSET 3 +#define D18F3x70_Reserved_3_3_WIDTH 1 +#define D18F3x70_Reserved_3_3_MASK 0x8 +#define D18F3x70_DnReqCBC_OFFSET 4 +#define D18F3x70_DnReqCBC_WIDTH 2 +#define D18F3x70_DnReqCBC_MASK 0x30 +#define D18F3x70_DnRspCBC_OFFSET 6 +#define D18F3x70_DnRspCBC_WIDTH 2 +#define D18F3x70_DnRspCBC_MASK 0xc0 +#define D18F3x70_UpPreqCBC_OFFSET 8 +#define D18F3x70_UpPreqCBC_WIDTH 3 +#define D18F3x70_UpPreqCBC_MASK 0x700 +#define D18F3x70_Reserved_11_11_OFFSET 11 +#define D18F3x70_Reserved_11_11_WIDTH 1 +#define D18F3x70_Reserved_11_11_MASK 0x800 +#define D18F3x70_DnPreqCBC_OFFSET 12 +#define D18F3x70_DnPreqCBC_WIDTH 3 +#define D18F3x70_DnPreqCBC_MASK 0x7000 +#define D18F3x70_Reserved_15_15_OFFSET 15 +#define D18F3x70_Reserved_15_15_WIDTH 1 +#define D18F3x70_Reserved_15_15_MASK 0x8000 +#define D18F3x70_UpRspCBC_OFFSET 16 +#define D18F3x70_UpRspCBC_WIDTH 3 +#define D18F3x70_UpRspCBC_MASK 0x70000 +#define D18F3x70_Reserved_19_19_OFFSET 19 +#define D18F3x70_Reserved_19_19_WIDTH 1 +#define D18F3x70_Reserved_19_19_MASK 0x80000 +#define D18F3x70_IsocReqCBC_OFFSET 20 +#define D18F3x70_IsocReqCBC_WIDTH 3 +#define D18F3x70_IsocReqCBC_MASK 0x700000 +#define D18F3x70_Reserved_23_23_OFFSET 23 +#define D18F3x70_Reserved_23_23_WIDTH 1 +#define D18F3x70_Reserved_23_23_MASK 0x800000 +#define D18F3x70_IsocPreqCBC_OFFSET 24 +#define D18F3x70_IsocPreqCBC_WIDTH 3 +#define D18F3x70_IsocPreqCBC_MASK 0x7000000 +#define D18F3x70_Reserved_27_27_OFFSET 27 +#define D18F3x70_Reserved_27_27_WIDTH 1 +#define D18F3x70_Reserved_27_27_MASK 0x8000000 +#define D18F3x70_IsocRspCBC_OFFSET 28 +#define D18F3x70_IsocRspCBC_WIDTH 3 +#define D18F3x70_IsocRspCBC_MASK 0x70000000 +#define D18F3x70_Reserved_31_31_OFFSET 31 +#define D18F3x70_Reserved_31_31_WIDTH 1 +#define D18F3x70_Reserved_31_31_MASK 0x80000000 + +/// D18F3x70 +typedef union { + struct { ///< + UINT32 UpReqCBC:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 DnReqCBC:2 ; ///< + UINT32 DnRspCBC:2 ; ///< + UINT32 UpPreqCBC:3 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 DnPreqCBC:3 ; ///< + UINT32 Reserved_15_15:1 ; ///< + UINT32 UpRspCBC:3 ; ///< + UINT32 Reserved_19_19:1 ; ///< + UINT32 IsocReqCBC:3 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 IsocPreqCBC:3 ; ///< + UINT32 Reserved_27_27:1 ; ///< + UINT32 IsocRspCBC:3 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x70_STRUCT; + +// **** D18F3x74 Register Definition **** +// Address +#define D18F3x74_ADDRESS 0x74 + +// Type +#define D18F3x74_TYPE TYPE_D18F3 +// Field Data +#define D18F3x74_UpReqCBC_OFFSET 0 +#define D18F3x74_UpReqCBC_WIDTH 3 +#define D18F3x74_UpReqCBC_MASK 0x7 +#define D18F3x74_Reserved_3_3_OFFSET 3 +#define D18F3x74_Reserved_3_3_WIDTH 1 +#define D18F3x74_Reserved_3_3_MASK 0x8 +#define D18F3x74_DnReqCBC_OFFSET 4 +#define D18F3x74_DnReqCBC_WIDTH 3 +#define D18F3x74_DnReqCBC_MASK 0x70 +#define D18F3x74_Reserved_7_7_OFFSET 7 +#define D18F3x74_Reserved_7_7_WIDTH 1 +#define D18F3x74_Reserved_7_7_MASK 0x80 +#define D18F3x74_UpPreqCBC_OFFSET 8 +#define D18F3x74_UpPreqCBC_WIDTH 3 +#define D18F3x74_UpPreqCBC_MASK 0x700 +#define D18F3x74_Reserved_11_11_OFFSET 11 +#define D18F3x74_Reserved_11_11_WIDTH 1 +#define D18F3x74_Reserved_11_11_MASK 0x800 +#define D18F3x74_DnPreqCBC_OFFSET 12 +#define D18F3x74_DnPreqCBC_WIDTH 3 +#define D18F3x74_DnPreqCBC_MASK 0x7000 +#define D18F3x74_Reserved_15_15_OFFSET 15 +#define D18F3x74_Reserved_15_15_WIDTH 1 +#define D18F3x74_Reserved_15_15_MASK 0x8000 +#define D18F3x74_ProbeCBC_OFFSET 16 +#define D18F3x74_ProbeCBC_WIDTH 4 +#define D18F3x74_ProbeCBC_MASK 0xf0000 +#define D18F3x74_IsocReqCBC_OFFSET 20 +#define D18F3x74_IsocReqCBC_WIDTH 4 +#define D18F3x74_IsocReqCBC_MASK 0xf00000 +#define D18F3x74_IsocPreqCBC_OFFSET 24 +#define D18F3x74_IsocPreqCBC_WIDTH 3 +#define D18F3x74_IsocPreqCBC_MASK 0x7000000 +#define D18F3x74_Reserved_27_27_OFFSET 27 +#define D18F3x74_Reserved_27_27_WIDTH 1 +#define D18F3x74_Reserved_27_27_MASK 0x8000000 +#define D18F3x74_DRReqCBC_OFFSET 28 +#define D18F3x74_DRReqCBC_WIDTH 4 +#define D18F3x74_DRReqCBC_MASK 0xf0000000 + +/// D18F3x74 +typedef union { + struct { ///< + UINT32 UpReqCBC:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 DnReqCBC:3 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 UpPreqCBC:3 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 DnPreqCBC:3 ; ///< + UINT32 Reserved_15_15:1 ; ///< + UINT32 ProbeCBC:4 ; ///< + UINT32 IsocReqCBC:4 ; ///< + UINT32 IsocPreqCBC:3 ; ///< + UINT32 Reserved_27_27:1 ; ///< + UINT32 DRReqCBC:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x74_STRUCT; + +// **** D18F3x78 Register Definition **** +// Address +#define D18F3x78_ADDRESS 0x78 + +// Type +#define D18F3x78_TYPE TYPE_D18F3 +// Field Data +#define D18F3x78_RspCBC_OFFSET 0 +#define D18F3x78_RspCBC_WIDTH 5 +#define D18F3x78_RspCBC_MASK 0x1f +#define D18F3x78_Reserved_7_5_OFFSET 5 +#define D18F3x78_Reserved_7_5_WIDTH 3 +#define D18F3x78_Reserved_7_5_MASK 0xe0 +#define D18F3x78_ProbeCBC_OFFSET 8 +#define D18F3x78_ProbeCBC_WIDTH 5 +#define D18F3x78_ProbeCBC_MASK 0x1f00 +#define D18F3x78_Reserved_15_13_OFFSET 13 +#define D18F3x78_Reserved_15_13_WIDTH 3 +#define D18F3x78_Reserved_15_13_MASK 0xe000 +#define D18F3x78_RspDBC_OFFSET 16 +#define D18F3x78_RspDBC_WIDTH 6 +#define D18F3x78_RspDBC_MASK 0x3f0000 +#define D18F3x78_Reserved_31_22_OFFSET 22 +#define D18F3x78_Reserved_31_22_WIDTH 10 +#define D18F3x78_Reserved_31_22_MASK 0xffc00000 + +/// D18F3x78 +typedef union { + struct { ///< + UINT32 RspCBC:5 ; ///< + UINT32 Reserved_7_5:3 ; ///< + UINT32 ProbeCBC:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 RspDBC:6 ; ///< + UINT32 Reserved_31_22:10; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x78_STRUCT; + +// **** D18F3x7C Register Definition **** +// Address +#define D18F3x7C_ADDRESS 0x7c + +// Type +#define D18F3x7C_TYPE TYPE_D18F3 +// Field Data +#define D18F3x7C_Xbar2SriFreeListCBC_OFFSET 0 +#define D18F3x7C_Xbar2SriFreeListCBC_WIDTH 5 +#define D18F3x7C_Xbar2SriFreeListCBC_MASK 0x1f +#define D18F3x7C_Reserved_7_5_OFFSET 5 +#define D18F3x7C_Reserved_7_5_WIDTH 3 +#define D18F3x7C_Reserved_7_5_MASK 0xe0 +#define D18F3x7C_Sri2XbarFreeXreqCBC_OFFSET 8 +#define D18F3x7C_Sri2XbarFreeXreqCBC_WIDTH 4 +#define D18F3x7C_Sri2XbarFreeXreqCBC_MASK 0xf00 +#define D18F3x7C_Sri2XbarFreeRspCBC_OFFSET 12 +#define D18F3x7C_Sri2XbarFreeRspCBC_WIDTH 4 +#define D18F3x7C_Sri2XbarFreeRspCBC_MASK 0xf000 +#define D18F3x7C_Sri2XbarFreeXreqDBC_OFFSET 16 +#define D18F3x7C_Sri2XbarFreeXreqDBC_WIDTH 4 +#define D18F3x7C_Sri2XbarFreeXreqDBC_MASK 0xf0000 +#define D18F3x7C_Sri2XbarFreeRspDBC_OFFSET 20 +#define D18F3x7C_Sri2XbarFreeRspDBC_WIDTH 3 +#define D18F3x7C_Sri2XbarFreeRspDBC_MASK 0x700000 +#define D18F3x7C_ExtSrqFreeList_OFFSET 23 +#define D18F3x7C_ExtSrqFreeList_WIDTH 4 +#define D18F3x7C_ExtSrqFreeList_MASK 0x7800000 +#define D18F3x7C_Reserved_27_27_OFFSET 27 +#define D18F3x7C_Reserved_27_27_WIDTH 1 +#define D18F3x7C_Reserved_27_27_MASK 0x8000000 +#define D18F3x7C_Xbar2SriFreeListCBInc_OFFSET 28 +#define D18F3x7C_Xbar2SriFreeListCBInc_WIDTH 3 +#define D18F3x7C_Xbar2SriFreeListCBInc_MASK 0x70000000 +#define D18F3x7C_Reserved_31_31_OFFSET 31 +#define D18F3x7C_Reserved_31_31_WIDTH 1 +#define D18F3x7C_Reserved_31_31_MASK 0x80000000 + +/// D18F3x7C +typedef union { + struct { ///< + UINT32 Xbar2SriFreeListCBC:5 ; ///< + UINT32 Reserved_7_5:3 ; ///< + UINT32 Sri2XbarFreeXreqCBC:4 ; ///< + UINT32 Sri2XbarFreeRspCBC:4 ; ///< + UINT32 Sri2XbarFreeXreqDBC:4 ; ///< + UINT32 Sri2XbarFreeRspDBC:3 ; ///< + UINT32 ExtSrqFreeList:4 ; ///< + UINT32 Reserved_27_27:1 ; ///< + UINT32 Xbar2SriFreeListCBInc:3 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x7C_STRUCT; + +// **** D18F3x80 Register Definition **** +// Address +#define D18F3x80_ADDRESS 0x80 + +// Type +#define D18F3x80_TYPE TYPE_D18F3 +// Field Data +#define D18F3x80_CpuPrbEnSmafAct0_OFFSET 0 +#define D18F3x80_CpuPrbEnSmafAct0_WIDTH 1 +#define D18F3x80_CpuPrbEnSmafAct0_MASK 0x1 +#define D18F3x80_NbLowPwrEnSmafAct0_OFFSET 1 +#define D18F3x80_NbLowPwrEnSmafAct0_WIDTH 1 +#define D18F3x80_NbLowPwrEnSmafAct0_MASK 0x2 +#define D18F3x80_NbGateEnSmafAct0_OFFSET 2 +#define D18F3x80_NbGateEnSmafAct0_WIDTH 1 +#define D18F3x80_NbGateEnSmafAct0_MASK 0x4 +#define D18F3x80_Reserved_4_3_OFFSET 3 +#define D18F3x80_Reserved_4_3_WIDTH 2 +#define D18F3x80_Reserved_4_3_MASK 0x18 +#define D18F3x80_ClkDivisorSmafAct0_OFFSET 5 +#define D18F3x80_ClkDivisorSmafAct0_WIDTH 3 +#define D18F3x80_ClkDivisorSmafAct0_MASK 0xe0 +#define D18F3x80_CpuPrbEnSmafAct1_OFFSET 8 +#define D18F3x80_CpuPrbEnSmafAct1_WIDTH 1 +#define D18F3x80_CpuPrbEnSmafAct1_MASK 0x100 +#define D18F3x80_NbLowPwrEnSmafAct1_OFFSET 9 +#define D18F3x80_NbLowPwrEnSmafAct1_WIDTH 1 +#define D18F3x80_NbLowPwrEnSmafAct1_MASK 0x200 +#define D18F3x80_NbGateEnSmafAct1_OFFSET 10 +#define D18F3x80_NbGateEnSmafAct1_WIDTH 1 +#define D18F3x80_NbGateEnSmafAct1_MASK 0x400 +#define D18F3x80_Reserved_12_11_OFFSET 11 +#define D18F3x80_Reserved_12_11_WIDTH 2 +#define D18F3x80_Reserved_12_11_MASK 0x1800 +#define D18F3x80_ClkDivisorSmafAct1_OFFSET 13 +#define D18F3x80_ClkDivisorSmafAct1_WIDTH 3 +#define D18F3x80_ClkDivisorSmafAct1_MASK 0xe000 +#define D18F3x80_CpuPrbEnSmafAct2_OFFSET 16 +#define D18F3x80_CpuPrbEnSmafAct2_WIDTH 1 +#define D18F3x80_CpuPrbEnSmafAct2_MASK 0x10000 +#define D18F3x80_NbLowPwrEnSmafAct2_OFFSET 17 +#define D18F3x80_NbLowPwrEnSmafAct2_WIDTH 1 +#define D18F3x80_NbLowPwrEnSmafAct2_MASK 0x20000 +#define D18F3x80_NbGateEnSmafAct2_OFFSET 18 +#define D18F3x80_NbGateEnSmafAct2_WIDTH 1 +#define D18F3x80_NbGateEnSmafAct2_MASK 0x40000 +#define D18F3x80_Reserved_20_19_OFFSET 19 +#define D18F3x80_Reserved_20_19_WIDTH 2 +#define D18F3x80_Reserved_20_19_MASK 0x180000 +#define D18F3x80_ClkDivisorSmafAct2_OFFSET 21 +#define D18F3x80_ClkDivisorSmafAct2_WIDTH 3 +#define D18F3x80_ClkDivisorSmafAct2_MASK 0xe00000 +#define D18F3x80_CpuPrbEnSmafAct3_OFFSET 24 +#define D18F3x80_CpuPrbEnSmafAct3_WIDTH 1 +#define D18F3x80_CpuPrbEnSmafAct3_MASK 0x1000000 +#define D18F3x80_NbLowPwrEnSmafAct3_OFFSET 25 +#define D18F3x80_NbLowPwrEnSmafAct3_WIDTH 1 +#define D18F3x80_NbLowPwrEnSmafAct3_MASK 0x2000000 +#define D18F3x80_NbGateEnSmafAct3_OFFSET 26 +#define D18F3x80_NbGateEnSmafAct3_WIDTH 1 +#define D18F3x80_NbGateEnSmafAct3_MASK 0x4000000 +#define D18F3x80_Reserved_28_27_OFFSET 27 +#define D18F3x80_Reserved_28_27_WIDTH 2 +#define D18F3x80_Reserved_28_27_MASK 0x18000000 +#define D18F3x80_ClkDivisorSmafAct3_OFFSET 29 +#define D18F3x80_ClkDivisorSmafAct3_WIDTH 3 +#define D18F3x80_ClkDivisorSmafAct3_MASK 0xe0000000 + +/// D18F3x80 +typedef union { + struct { ///< + UINT32 CpuPrbEnSmafAct0:1 ; ///< + UINT32 NbLowPwrEnSmafAct0:1 ; ///< + UINT32 NbGateEnSmafAct0:1 ; ///< + UINT32 Reserved_4_3:2 ; ///< + UINT32 ClkDivisorSmafAct0:3 ; ///< + UINT32 CpuPrbEnSmafAct1:1 ; ///< + UINT32 NbLowPwrEnSmafAct1:1 ; ///< + UINT32 NbGateEnSmafAct1:1 ; ///< + UINT32 Reserved_12_11:2 ; ///< + UINT32 ClkDivisorSmafAct1:3 ; ///< + UINT32 CpuPrbEnSmafAct2:1 ; ///< + UINT32 NbLowPwrEnSmafAct2:1 ; ///< + UINT32 NbGateEnSmafAct2:1 ; ///< + UINT32 Reserved_20_19:2 ; ///< + UINT32 ClkDivisorSmafAct2:3 ; ///< + UINT32 CpuPrbEnSmafAct3:1 ; ///< + UINT32 NbLowPwrEnSmafAct3:1 ; ///< + UINT32 NbGateEnSmafAct3:1 ; ///< + UINT32 Reserved_28_27:2 ; ///< + UINT32 ClkDivisorSmafAct3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x80_STRUCT; + +// **** D18F3x84 Register Definition **** +// Address +#define D18F3x84_ADDRESS 0x84 + +// Type +#define D18F3x84_TYPE TYPE_D18F3 +// Field Data +#define D18F3x84_CpuPrbEnSmafAct4_OFFSET 0 +#define D18F3x84_CpuPrbEnSmafAct4_WIDTH 1 +#define D18F3x84_CpuPrbEnSmafAct4_MASK 0x1 +#define D18F3x84_NbLowPwrEnSmafAct4_OFFSET 1 +#define D18F3x84_NbLowPwrEnSmafAct4_WIDTH 1 +#define D18F3x84_NbLowPwrEnSmafAct4_MASK 0x2 +#define D18F3x84_NbGateEnSmafAct4_OFFSET 2 +#define D18F3x84_NbGateEnSmafAct4_WIDTH 1 +#define D18F3x84_NbGateEnSmafAct4_MASK 0x4 +#define D18F3x84_Reserved_4_3_OFFSET 3 +#define D18F3x84_Reserved_4_3_WIDTH 2 +#define D18F3x84_Reserved_4_3_MASK 0x18 +#define D18F3x84_ClkDivisorSmafAct4_OFFSET 5 +#define D18F3x84_ClkDivisorSmafAct4_WIDTH 3 +#define D18F3x84_ClkDivisorSmafAct4_MASK 0xe0 +#define D18F3x84_CpuPrbEnSmafAct5_OFFSET 8 +#define D18F3x84_CpuPrbEnSmafAct5_WIDTH 1 +#define D18F3x84_CpuPrbEnSmafAct5_MASK 0x100 +#define D18F3x84_NbLowPwrEnSmafAct5_OFFSET 9 +#define D18F3x84_NbLowPwrEnSmafAct5_WIDTH 1 +#define D18F3x84_NbLowPwrEnSmafAct5_MASK 0x200 +#define D18F3x84_NbGateEnSmafAct5_OFFSET 10 +#define D18F3x84_NbGateEnSmafAct5_WIDTH 1 +#define D18F3x84_NbGateEnSmafAct5_MASK 0x400 +#define D18F3x84_Reserved_12_11_OFFSET 11 +#define D18F3x84_Reserved_12_11_WIDTH 2 +#define D18F3x84_Reserved_12_11_MASK 0x1800 +#define D18F3x84_ClkDivisorSmafAct5_OFFSET 13 +#define D18F3x84_ClkDivisorSmafAct5_WIDTH 3 +#define D18F3x84_ClkDivisorSmafAct5_MASK 0xe000 +#define D18F3x84_CpuPrbEnSmafAct6_OFFSET 16 +#define D18F3x84_CpuPrbEnSmafAct6_WIDTH 1 +#define D18F3x84_CpuPrbEnSmafAct6_MASK 0x10000 +#define D18F3x84_NbLowPwrEnSmafAct6_OFFSET 17 +#define D18F3x84_NbLowPwrEnSmafAct6_WIDTH 1 +#define D18F3x84_NbLowPwrEnSmafAct6_MASK 0x20000 +#define D18F3x84_NbGateEnSmafAct6_OFFSET 18 +#define D18F3x84_NbGateEnSmafAct6_WIDTH 1 +#define D18F3x84_NbGateEnSmafAct6_MASK 0x40000 +#define D18F3x84_Reserved_20_19_OFFSET 19 +#define D18F3x84_Reserved_20_19_WIDTH 2 +#define D18F3x84_Reserved_20_19_MASK 0x180000 +#define D18F3x84_ClkDivisorSmafAct6_OFFSET 21 +#define D18F3x84_ClkDivisorSmafAct6_WIDTH 3 +#define D18F3x84_ClkDivisorSmafAct6_MASK 0xe00000 +#define D18F3x84_CpuPrbEnSmafAct7_OFFSET 24 +#define D18F3x84_CpuPrbEnSmafAct7_WIDTH 1 +#define D18F3x84_CpuPrbEnSmafAct7_MASK 0x1000000 +#define D18F3x84_NbLowPwrEnSmafAct7_OFFSET 25 +#define D18F3x84_NbLowPwrEnSmafAct7_WIDTH 1 +#define D18F3x84_NbLowPwrEnSmafAct7_MASK 0x2000000 +#define D18F3x84_NbGateEnSmafAct7_OFFSET 26 +#define D18F3x84_NbGateEnSmafAct7_WIDTH 1 +#define D18F3x84_NbGateEnSmafAct7_MASK 0x4000000 +#define D18F3x84_Reserved_28_27_OFFSET 27 +#define D18F3x84_Reserved_28_27_WIDTH 2 +#define D18F3x84_Reserved_28_27_MASK 0x18000000 +#define D18F3x84_ClkDivisorSmafAct7_OFFSET 29 +#define D18F3x84_ClkDivisorSmafAct7_WIDTH 3 +#define D18F3x84_ClkDivisorSmafAct7_MASK 0xe0000000 + +/// D18F3x84 +typedef union { + struct { ///< + UINT32 CpuPrbEnSmafAct4:1 ; ///< + UINT32 NbLowPwrEnSmafAct4:1 ; ///< + UINT32 NbGateEnSmafAct4:1 ; ///< + UINT32 Reserved_4_3:2 ; ///< + UINT32 ClkDivisorSmafAct4:3 ; ///< + UINT32 CpuPrbEnSmafAct5:1 ; ///< + UINT32 NbLowPwrEnSmafAct5:1 ; ///< + UINT32 NbGateEnSmafAct5:1 ; ///< + UINT32 Reserved_12_11:2 ; ///< + UINT32 ClkDivisorSmafAct5:3 ; ///< + UINT32 CpuPrbEnSmafAct6:1 ; ///< + UINT32 NbLowPwrEnSmafAct6:1 ; ///< + UINT32 NbGateEnSmafAct6:1 ; ///< + UINT32 Reserved_20_19:2 ; ///< + UINT32 ClkDivisorSmafAct6:3 ; ///< + UINT32 CpuPrbEnSmafAct7:1 ; ///< + UINT32 NbLowPwrEnSmafAct7:1 ; ///< + UINT32 NbGateEnSmafAct7:1 ; ///< + UINT32 Reserved_28_27:2 ; ///< + UINT32 ClkDivisorSmafAct7:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x84_STRUCT; + +// **** D18F3x88 Register Definition **** +// Address +#define D18F3x88_ADDRESS 0x88 + +// Type +#define D18F3x88_TYPE TYPE_D18F3 +// Field Data +#define D18F3x88_Reserved_30_0_OFFSET 0 +#define D18F3x88_Reserved_30_0_WIDTH 31 +#define D18F3x88_Reserved_30_0_MASK 0x7fffffff +#define D18F3x88_DisCohLdtCfg_OFFSET 31 +#define D18F3x88_DisCohLdtCfg_WIDTH 1 +#define D18F3x88_DisCohLdtCfg_MASK 0x80000000 + +/// D18F3x88 +typedef union { + struct { ///< + UINT32 Reserved_30_0:31; ///< + UINT32 DisCohLdtCfg:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x88_STRUCT; + +// **** D18F3x8C Register Definition **** +// Address +#define D18F3x8C_ADDRESS 0x8c + +// Type +#define D18F3x8C_TYPE TYPE_D18F3 +// Field Data +#define D18F3x8C_Reserved_35_32_OFFSET 0 +#define D18F3x8C_Reserved_35_32_WIDTH 4 +#define D18F3x8C_Reserved_35_32_MASK 0xf +#define D18F3x8C_DisDatMsk_OFFSET 4 +#define D18F3x8C_DisDatMsk_WIDTH 1 +#define D18F3x8C_DisDatMsk_MASK 0x10 +#define D18F3x8C_Reserved_44_37_OFFSET 5 +#define D18F3x8C_Reserved_44_37_WIDTH 8 +#define D18F3x8C_Reserved_44_37_MASK 0x1fe0 +#define D18F3x8C_DisUsSysMgtReqToNcHt_OFFSET 13 +#define D18F3x8C_DisUsSysMgtReqToNcHt_WIDTH 1 +#define D18F3x8C_DisUsSysMgtReqToNcHt_MASK 0x2000 +#define D18F3x8C_EnableCf8ExtCfg_OFFSET 14 +#define D18F3x8C_EnableCf8ExtCfg_WIDTH 1 +#define D18F3x8C_EnableCf8ExtCfg_MASK 0x4000 +#define D18F3x8C_Reserved_49_47_OFFSET 15 +#define D18F3x8C_Reserved_49_47_WIDTH 3 +#define D18F3x8C_Reserved_49_47_MASK 0x38000 +#define D18F3x8C_DisOrderRdRsp_OFFSET 18 +#define D18F3x8C_DisOrderRdRsp_WIDTH 1 +#define D18F3x8C_DisOrderRdRsp_MASK 0x40000 +#define D18F3x8C_Reserved_53_51_OFFSET 19 +#define D18F3x8C_Reserved_53_51_WIDTH 3 +#define D18F3x8C_Reserved_53_51_MASK 0x380000 +#define D18F3x8C_InitApicIdCpuIdLo_OFFSET 22 +#define D18F3x8C_InitApicIdCpuIdLo_WIDTH 1 +#define D18F3x8C_InitApicIdCpuIdLo_MASK 0x400000 +#define D18F3x8C_Reserved_63_55_OFFSET 23 +#define D18F3x8C_Reserved_63_55_WIDTH 9 +#define D18F3x8C_Reserved_63_55_MASK 0xff800000 + +/// D18F3x8C +typedef union { + struct { ///< + UINT32 Reserved_35_32:4 ; ///< + UINT32 DisDatMsk:1 ; ///< + UINT32 Reserved_44_37:8 ; ///< + UINT32 DisUsSysMgtReqToNcHt:1 ; ///< + UINT32 EnableCf8ExtCfg:1 ; ///< + UINT32 Reserved_49_47:3 ; ///< + UINT32 DisOrderRdRsp:1 ; ///< + UINT32 Reserved_53_51:3 ; ///< + UINT32 InitApicIdCpuIdLo:1 ; ///< + UINT32 Reserved_63_55:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x8C_STRUCT; + +// **** D18F3xA0 Register Definition **** +// Address +#define D18F3xA0_ADDRESS 0xa0 + +// Type +#define D18F3xA0_TYPE TYPE_D18F3 +// Field Data +#define D18F3xA0_PsiVid_6_0__OFFSET 0 +#define D18F3xA0_PsiVid_6_0__WIDTH 7 +#define D18F3xA0_PsiVid_6_0__MASK 0x7f +#define D18F3xA0_PsiVidEn_OFFSET 7 +#define D18F3xA0_PsiVidEn_WIDTH 1 +#define D18F3xA0_PsiVidEn_MASK 0x80 +#define D18F3xA0_PsiVid_7__OFFSET 8 +#define D18F3xA0_PsiVid_7__WIDTH 1 +#define D18F3xA0_PsiVid_7__MASK 0x100 +#define D18F3xA0_Reserved_10_9_OFFSET 9 +#define D18F3xA0_Reserved_10_9_WIDTH 2 +#define D18F3xA0_Reserved_10_9_MASK 0x600 +#define D18F3xA0_PllLockTime_OFFSET 11 +#define D18F3xA0_PllLockTime_WIDTH 3 +#define D18F3xA0_PllLockTime_MASK 0x3800 +#define D18F3xA0_Svi2HighFreqSel_OFFSET 14 +#define D18F3xA0_Svi2HighFreqSel_WIDTH 1 +#define D18F3xA0_Svi2HighFreqSel_MASK 0x4000 +#define D18F3xA0_Reserved_15_15_OFFSET 15 +#define D18F3xA0_Reserved_15_15_WIDTH 1 +#define D18F3xA0_Reserved_15_15_MASK 0x8000 +#define D18F3xA0_ConfigId_OFFSET 16 +#define D18F3xA0_ConfigId_WIDTH 12 +#define D18F3xA0_ConfigId_MASK 0xfff0000 +#define D18F3xA0_Reserved_30_28_OFFSET 28 +#define D18F3xA0_Reserved_30_28_WIDTH 3 +#define D18F3xA0_Reserved_30_28_MASK 0x70000000 +#define D18F3xA0_CofVidProg_OFFSET 31 +#define D18F3xA0_CofVidProg_WIDTH 1 +#define D18F3xA0_CofVidProg_MASK 0x80000000 + +/// D18F3xA0 +typedef union { + struct { ///< + UINT32 PsiVid_6_0_:7 ; ///< + UINT32 PsiVidEn:1 ; ///< + UINT32 PsiVid_7_:1 ; ///< + UINT32 Reserved_10_9:2 ; ///< + UINT32 PllLockTime:3 ; ///< + UINT32 Svi2HighFreqSel:1 ; ///< + UINT32 Reserved_15_15:1 ; ///< + UINT32 ConfigId:12; ///< + UINT32 Reserved_30_28:3 ; ///< + UINT32 CofVidProg:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3xA0_STRUCT; + +// **** D18F3xA4 Register Definition **** +// Address +#define D18F3xA4_ADDRESS 0xa4 + +// Type +#define D18F3xA4_TYPE TYPE_D18F3 +// Field Data +#define D18F3xA4_PerStepTimeUp_OFFSET 0 +#define D18F3xA4_PerStepTimeUp_WIDTH 5 +#define D18F3xA4_PerStepTimeUp_MASK 0x1f +#define D18F3xA4_TmpMaxDiffUp_OFFSET 5 +#define D18F3xA4_TmpMaxDiffUp_WIDTH 2 +#define D18F3xA4_TmpMaxDiffUp_MASK 0x60 +#define D18F3xA4_TmpSlewDnEn_OFFSET 7 +#define D18F3xA4_TmpSlewDnEn_WIDTH 1 +#define D18F3xA4_TmpSlewDnEn_MASK 0x80 +#define D18F3xA4_PerStepTimeDn_OFFSET 8 +#define D18F3xA4_PerStepTimeDn_WIDTH 5 +#define D18F3xA4_PerStepTimeDn_MASK 0x1f00 +#define D18F3xA4_Reserved_15_13_OFFSET 13 +#define D18F3xA4_Reserved_15_13_WIDTH 3 +#define D18F3xA4_Reserved_15_13_MASK 0xe000 +#define D18F3xA4_CurTmpTjSel_OFFSET 16 +#define D18F3xA4_CurTmpTjSel_WIDTH 2 +#define D18F3xA4_CurTmpTjSel_MASK 0x30000 +#define D18F3xA4_Reserved_19_18_OFFSET 18 +#define D18F3xA4_Reserved_19_18_WIDTH 2 +#define D18F3xA4_Reserved_19_18_MASK 0xc0000 +#define D18F3xA4_TcenPwrDnCc6En_OFFSET 20 +#define D18F3xA4_TcenPwrDnCc6En_WIDTH 1 +#define D18F3xA4_TcenPwrDnCc6En_MASK 0x100000 +#define D18F3xA4_CurTmp_OFFSET 21 +#define D18F3xA4_CurTmp_WIDTH 11 +#define D18F3xA4_CurTmp_MASK 0xffe00000 + +/// D18F3xA4 +typedef union { + struct { ///< + UINT32 PerStepTimeUp:5 ; ///< + UINT32 TmpMaxDiffUp:2 ; ///< + UINT32 TmpSlewDnEn:1 ; ///< + UINT32 PerStepTimeDn:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 CurTmpTjSel:2 ; ///< + UINT32 Reserved_19_18:2 ; ///< + UINT32 TcenPwrDnCc6En:1 ; ///< + UINT32 CurTmp:11; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3xA4_STRUCT; + +// **** D18F3xA8 Register Definition **** +// Address +#define D18F3xA8_ADDRESS 0xa8 + +// Type +#define D18F3xA8_TYPE TYPE_D18F3 +// Field Data +#define D18F3xA8_Reserved_28_0_OFFSET 0 +#define D18F3xA8_Reserved_28_0_WIDTH 29 +#define D18F3xA8_Reserved_28_0_MASK 0x1fffffff +#define D18F3xA8_PopDownPstate_OFFSET 29 +#define D18F3xA8_PopDownPstate_WIDTH 3 +#define D18F3xA8_PopDownPstate_MASK 0xe0000000 + +/// D18F3xA8 +typedef union { + struct { ///< + UINT32 Reserved_28_0:29; ///< + UINT32 PopDownPstate:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3xA8_STRUCT; + + +// **** D18F3xD4 Register Definition **** +// Address +#define D18F3xD4_ADDRESS 0xd4 + +// Type +#define D18F3xD4_TYPE TYPE_D18F3 +// Field Data +#define D18F3xD4_MaxSwPstateCpuCof_OFFSET 0 +#define D18F3xD4_MaxSwPstateCpuCof_WIDTH 6 +#define D18F3xD4_MaxSwPstateCpuCof_MASK 0x3f +#define D18F3xD4_Reserved_7_6_OFFSET 6 +#define D18F3xD4_Reserved_7_6_WIDTH 2 +#define D18F3xD4_Reserved_7_6_MASK 0xc0 +#define D18F3xD4_ClkRampHystSel_OFFSET 8 +#define D18F3xD4_ClkRampHystSel_WIDTH 4 +#define D18F3xD4_ClkRampHystSel_MASK 0xf00 +#define D18F3xD4_ClkRampHystCtl_OFFSET 12 +#define D18F3xD4_ClkRampHystCtl_WIDTH 1 +#define D18F3xD4_ClkRampHystCtl_MASK 0x1000 +#define D18F3xD4_Reserved_13_13_OFFSET 13 +#define D18F3xD4_Reserved_13_13_WIDTH 1 +#define D18F3xD4_Reserved_13_13_MASK 0x2000 +#define D18F3xD4_CacheFlushImmOnAllHalt_OFFSET 14 +#define D18F3xD4_CacheFlushImmOnAllHalt_WIDTH 1 +#define D18F3xD4_CacheFlushImmOnAllHalt_MASK 0x4000 +#define D18F3xD4_Reserved_17_15_OFFSET 15 +#define D18F3xD4_Reserved_17_15_WIDTH 3 +#define D18F3xD4_Reserved_17_15_MASK 0x38000 +#define D18F3xD4_Reserved_19_18_OFFSET 18 +#define D18F3xD4_Reserved_19_18_WIDTH 2 +#define D18F3xD4_Reserved_19_18_MASK 0xc0000 +#define D18F3xD4_PowerStepDown_OFFSET 20 +#define D18F3xD4_PowerStepDown_WIDTH 4 +#define D18F3xD4_PowerStepDown_MASK 0xf00000 +#define D18F3xD4_PowerStepUp_OFFSET 24 +#define D18F3xD4_PowerStepUp_WIDTH 4 +#define D18F3xD4_PowerStepUp_MASK 0xf000000 +#define D18F3xD4_NbClkDiv_OFFSET 28 +#define D18F3xD4_NbClkDiv_WIDTH 3 +#define D18F3xD4_NbClkDiv_MASK 0x70000000 +#define D18F3xD4_NbClkDivApplyAll_OFFSET 31 +#define D18F3xD4_NbClkDivApplyAll_WIDTH 1 +#define D18F3xD4_NbClkDivApplyAll_MASK 0x80000000 + +/// D18F3xD4 +typedef union { + struct { ///< + UINT32 MaxSwPstateCpuCof:6 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 ClkRampHystSel:4 ; ///< + UINT32 ClkRampHystCtl:1 ; ///< + UINT32 Reserved_13_13:1 ; ///< + UINT32 CacheFlushImmOnAllHalt:1 ; ///< + UINT32 Reserved_17_15:3 ; ///< + UINT32 Reserved_19_18:2 ; ///< + UINT32 PowerStepDown:4 ; ///< + UINT32 PowerStepUp:4 ; ///< + UINT32 NbClkDiv:3 ; ///< + UINT32 NbClkDivApplyAll:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3xD4_STRUCT; + +// **** D18F3xD8 Register Definition **** +// Address +#define D18F3xD8_ADDRESS 0xd8 + +// Type +#define D18F3xD8_TYPE TYPE_D18F3 +// Field Data +#define D18F3xD8_Reserved_3_0_OFFSET 0 +#define D18F3xD8_Reserved_3_0_WIDTH 4 +#define D18F3xD8_Reserved_3_0_MASK 0xf +#define D18F3xD8_VSRampSlamTime_OFFSET 4 +#define D18F3xD8_VSRampSlamTime_WIDTH 3 +#define D18F3xD8_VSRampSlamTime_MASK 0x70 +#define D18F3xD8_Reserved_31_7_OFFSET 7 +#define D18F3xD8_Reserved_31_7_WIDTH 25 +#define D18F3xD8_Reserved_31_7_MASK 0xffffff80 + +/// D18F3xD8 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 VSRampSlamTime:3 ; ///< + UINT32 Reserved_31_7:25; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3xD8_STRUCT; + +// **** D18F3xDC Register Definition **** +// Address +#define D18F3xDC_ADDRESS 0xdc + +// Type +#define D18F3xDC_TYPE TYPE_D18F3 +// Field Data +#define D18F3xDC_Reserved_7_0_OFFSET 0 +#define D18F3xDC_Reserved_7_0_WIDTH 8 +#define D18F3xDC_Reserved_7_0_MASK 0xff +#define D18F3xDC_PstateMaxVal_OFFSET 8 +#define D18F3xDC_PstateMaxVal_WIDTH 3 +#define D18F3xDC_PstateMaxVal_MASK 0x700 +#define D18F3xDC_Reserved_11_11_OFFSET 11 +#define D18F3xDC_Reserved_11_11_WIDTH 1 +#define D18F3xDC_Reserved_11_11_MASK 0x800 +#define D18F3xDC_NbsynPtrAdj_OFFSET 12 +#define D18F3xDC_NbsynPtrAdj_WIDTH 3 +#define D18F3xDC_NbsynPtrAdj_MASK 0x7000 +#define D18F3xDC_Reserved_15_15_OFFSET 15 +#define D18F3xDC_Reserved_15_15_WIDTH 1 +#define D18F3xDC_Reserved_15_15_MASK 0x8000 +#define D18F3xDC_CacheFlushOnHaltCtl_OFFSET 16 +#define D18F3xDC_CacheFlushOnHaltCtl_WIDTH 3 +#define D18F3xDC_CacheFlushOnHaltCtl_MASK 0x70000 +#define D18F3xDC_CacheFlushOnHaltTmr_OFFSET 19 +#define D18F3xDC_CacheFlushOnHaltTmr_WIDTH 7 +#define D18F3xDC_CacheFlushOnHaltTmr_MASK 0x3f80000 +#define D18F3xDC_IgnCpuPrbEn_OFFSET 26 +#define D18F3xDC_IgnCpuPrbEn_WIDTH 1 +#define D18F3xDC_IgnCpuPrbEn_MASK 0x4000000 +#define D18F3xDC_Reserved_31_27_OFFSET 27 +#define D18F3xDC_Reserved_31_27_WIDTH 5 +#define D18F3xDC_Reserved_31_27_MASK 0xf8000000 + +/// D18F3xDC +typedef union { + struct { ///< + UINT32 Reserved_7_0:8 ; ///< + UINT32 PstateMaxVal:3 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 NbsynPtrAdj:3 ; ///< + UINT32 Reserved_15_15:1 ; ///< + UINT32 CacheFlushOnHaltCtl:3 ; ///< + UINT32 CacheFlushOnHaltTmr:7 ; ///< + UINT32 IgnCpuPrbEn:1 ; ///< + UINT32 Reserved_31_27:5 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3xDC_STRUCT; + +// **** D18F3xE4 Register Definition **** +// Address +#define D18F3xE4_ADDRESS 0xe4 + +// Type +#define D18F3xE4_TYPE TYPE_D18F3 +// Field Data +#define D18F3xE4_Reserved_0_0_OFFSET 0 +#define D18F3xE4_Reserved_0_0_WIDTH 1 +#define D18F3xE4_Reserved_0_0_MASK 0x1 +#define D18F3xE4_Thermtp_OFFSET 1 +#define D18F3xE4_Thermtp_WIDTH 1 +#define D18F3xE4_Thermtp_MASK 0x2 +#define D18F3xE4_Reserved_2_2_OFFSET 2 +#define D18F3xE4_Reserved_2_2_WIDTH 1 +#define D18F3xE4_Reserved_2_2_MASK 0x4 +#define D18F3xE4_ThermtpSense_OFFSET 3 +#define D18F3xE4_ThermtpSense_WIDTH 1 +#define D18F3xE4_ThermtpSense_MASK 0x8 +#define D18F3xE4_Reserved_4_4_OFFSET 4 +#define D18F3xE4_Reserved_4_4_WIDTH 1 +#define D18F3xE4_Reserved_4_4_MASK 0x10 +#define D18F3xE4_ThermtpEn_OFFSET 5 +#define D18F3xE4_ThermtpEn_WIDTH 1 +#define D18F3xE4_ThermtpEn_MASK 0x20 +#define D18F3xE4_Reserved_30_6_OFFSET 6 +#define D18F3xE4_Reserved_30_6_WIDTH 25 +#define D18F3xE4_Reserved_30_6_MASK 0x7fffffc0 +#define D18F3xE4_SwThermtp_OFFSET 31 +#define D18F3xE4_SwThermtp_WIDTH 1 +#define D18F3xE4_SwThermtp_MASK 0x80000000 + +/// D18F3xE4 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 Thermtp:1 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 ThermtpSense:1 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 ThermtpEn:1 ; ///< + UINT32 Reserved_30_6:25; ///< + UINT32 SwThermtp:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3xE4_STRUCT; + +// **** D18F3xE8 Register Definition **** +// Address +#define D18F3xE8_ADDRESS 0xe8 + +// Type +#define D18F3xE8_TYPE TYPE_D18F3 +// Field Data +#define D18F3xE8_Reserved_0_0_OFFSET 0 +#define D18F3xE8_Reserved_0_0_WIDTH 1 +#define D18F3xE8_Reserved_0_0_MASK 0x1 +#define D18F3xE8_DualNode_OFFSET 1 +#define D18F3xE8_DualNode_WIDTH 1 +#define D18F3xE8_DualNode_MASK 0x2 +#define D18F3xE8_EightNode_OFFSET 2 +#define D18F3xE8_EightNode_WIDTH 1 +#define D18F3xE8_EightNode_MASK 0x4 +#define D18F3xE8_ECC_OFFSET 3 +#define D18F3xE8_ECC_WIDTH 1 +#define D18F3xE8_ECC_MASK 0x8 +#define D18F3xE8_ChipKill_OFFSET 4 +#define D18F3xE8_ChipKill_WIDTH 1 +#define D18F3xE8_ChipKill_MASK 0x10 +#define D18F3xE8_Reserved_7_5_OFFSET 5 +#define D18F3xE8_Reserved_7_5_WIDTH 3 +#define D18F3xE8_Reserved_7_5_MASK 0xe0 +#define D18F3xE8_MctCap_OFFSET 8 +#define D18F3xE8_MctCap_WIDTH 1 +#define D18F3xE8_MctCap_MASK 0x100 +#define D18F3xE8_SvmCapable_OFFSET 9 +#define D18F3xE8_SvmCapable_WIDTH 1 +#define D18F3xE8_SvmCapable_MASK 0x200 +#define D18F3xE8_HtcCapable_OFFSET 10 +#define D18F3xE8_HtcCapable_WIDTH 1 +#define D18F3xE8_HtcCapable_MASK 0x400 +#define D18F3xE8_Reserved_11_11_OFFSET 11 +#define D18F3xE8_Reserved_11_11_WIDTH 1 +#define D18F3xE8_Reserved_11_11_MASK 0x800 +#define D18F3xE8_Reserved_13_12_OFFSET 12 +#define D18F3xE8_Reserved_13_12_WIDTH 2 +#define D18F3xE8_Reserved_13_12_MASK 0x3000 +#define D18F3xE8_MultVidPlane_OFFSET 14 +#define D18F3xE8_MultVidPlane_WIDTH 1 +#define D18F3xE8_MultVidPlane_MASK 0x4000 +#define D18F3xE8_Reserved_15_15_OFFSET 15 +#define D18F3xE8_Reserved_15_15_WIDTH 1 +#define D18F3xE8_Reserved_15_15_MASK 0x8000 +#define D18F3xE8_Reserved_18_16_OFFSET 16 +#define D18F3xE8_Reserved_18_16_WIDTH 3 +#define D18F3xE8_Reserved_18_16_MASK 0x70000 +#define D18F3xE8_x2Apic_OFFSET 19 +#define D18F3xE8_x2Apic_WIDTH 1 +#define D18F3xE8_x2Apic_MASK 0x80000 +#define D18F3xE8_Reserved_23_20_OFFSET 20 +#define D18F3xE8_Reserved_23_20_WIDTH 4 +#define D18F3xE8_Reserved_23_20_MASK 0xf00000 +#define D18F3xE8_MemPstateCap_OFFSET 24 +#define D18F3xE8_MemPstateCap_WIDTH 1 +#define D18F3xE8_MemPstateCap_MASK 0x1000000 +#define D18F3xE8_L3Capable_OFFSET 25 +#define D18F3xE8_L3Capable_WIDTH 1 +#define D18F3xE8_L3Capable_MASK 0x2000000 +#define D18F3xE8_Reserved_28_26_OFFSET 26 +#define D18F3xE8_Reserved_28_26_WIDTH 3 +#define D18F3xE8_Reserved_28_26_MASK 0x1c000000 +#define D18F3xE8_Reserved_31_29_OFFSET 29 +#define D18F3xE8_Reserved_31_29_WIDTH 3 +#define D18F3xE8_Reserved_31_29_MASK 0xe0000000 + +/// D18F3xE8 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 DualNode:1 ; ///< + UINT32 EightNode:1 ; ///< + UINT32 ECC:1 ; ///< + UINT32 ChipKill:1 ; ///< + UINT32 Reserved_7_5:3 ; ///< + UINT32 MctCap:1 ; ///< + UINT32 SvmCapable:1 ; ///< + UINT32 HtcCapable:1 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 Reserved_13_12:2 ; ///< + UINT32 MultVidPlane:1 ; ///< + UINT32 Reserved_15_15:1 ; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 x2Apic:1 ; ///< + UINT32 Reserved_23_20:4 ; ///< + UINT32 MemPstateCap:1 ; ///< + UINT32 L3Capable:1 ; ///< + UINT32 Reserved_28_26:3 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3xE8_STRUCT; + +// **** D18F3xFC Register Definition **** +// Address +#define D18F3xFC_ADDRESS 0xfc + +// Type +#define D18F3xFC_TYPE TYPE_D18F3 +// Field Data +#define D18F3xFC_Stepping_OFFSET 0 +#define D18F3xFC_Stepping_WIDTH 4 +#define D18F3xFC_Stepping_MASK 0xf +#define D18F3xFC_BaseModel_OFFSET 4 +#define D18F3xFC_BaseModel_WIDTH 4 +#define D18F3xFC_BaseModel_MASK 0xf0 +#define D18F3xFC_BaseFamily_OFFSET 8 +#define D18F3xFC_BaseFamily_WIDTH 4 +#define D18F3xFC_BaseFamily_MASK 0xf00 +#define D18F3xFC_Reserved_15_12_OFFSET 12 +#define D18F3xFC_Reserved_15_12_WIDTH 4 +#define D18F3xFC_Reserved_15_12_MASK 0xf000 +#define D18F3xFC_ExtModel_OFFSET 16 +#define D18F3xFC_ExtModel_WIDTH 4 +#define D18F3xFC_ExtModel_MASK 0xf0000 +#define D18F3xFC_ExtFamily_OFFSET 20 +#define D18F3xFC_ExtFamily_WIDTH 8 +#define D18F3xFC_ExtFamily_MASK 0xff00000 +#define D18F3xFC_Reserved_31_28_OFFSET 28 +#define D18F3xFC_Reserved_31_28_WIDTH 4 +#define D18F3xFC_Reserved_31_28_MASK 0xf0000000 + +/// D18F3xFC +typedef union { + struct { ///< + UINT32 Stepping:4 ; ///< + UINT32 BaseModel:4 ; ///< + UINT32 BaseFamily:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 ExtModel:4 ; ///< + UINT32 ExtFamily:8 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3xFC_STRUCT; + +// **** D18F3x140 Register Definition **** +// Address +#define D18F3x140_ADDRESS 0x140 + +// Type +#define D18F3x140_TYPE TYPE_D18F3 +// Field Data +#define D18F3x140_UpReqTok_OFFSET 0 +#define D18F3x140_UpReqTok_WIDTH 2 +#define D18F3x140_UpReqTok_MASK 0x3 +#define D18F3x140_DnReqTok_OFFSET 2 +#define D18F3x140_DnReqTok_WIDTH 2 +#define D18F3x140_DnReqTok_MASK 0xc +#define D18F3x140_UpPreqTok_OFFSET 4 +#define D18F3x140_UpPreqTok_WIDTH 2 +#define D18F3x140_UpPreqTok_MASK 0x30 +#define D18F3x140_DnPreqTok_OFFSET 6 +#define D18F3x140_DnPreqTok_WIDTH 2 +#define D18F3x140_DnPreqTok_MASK 0xc0 +#define D18F3x140_UpRspTok_OFFSET 8 +#define D18F3x140_UpRspTok_WIDTH 2 +#define D18F3x140_UpRspTok_MASK 0x300 +#define D18F3x140_DnRspTok_OFFSET 10 +#define D18F3x140_DnRspTok_WIDTH 2 +#define D18F3x140_DnRspTok_MASK 0xc00 +#define D18F3x140_IsocReqTok_OFFSET 12 +#define D18F3x140_IsocReqTok_WIDTH 2 +#define D18F3x140_IsocReqTok_MASK 0x3000 +#define D18F3x140_IsocPreqTok_OFFSET 14 +#define D18F3x140_IsocPreqTok_WIDTH 2 +#define D18F3x140_IsocPreqTok_MASK 0xc000 +#define D18F3x140_IsocRspTok_OFFSET 16 +#define D18F3x140_IsocRspTok_WIDTH 2 +#define D18F3x140_IsocRspTok_MASK 0x30000 +#define D18F3x140_Reserved_19_18_OFFSET 18 +#define D18F3x140_Reserved_19_18_WIDTH 2 +#define D18F3x140_Reserved_19_18_MASK 0xc0000 +#define D18F3x140_FreeTok_OFFSET 20 +#define D18F3x140_FreeTok_WIDTH 4 +#define D18F3x140_FreeTok_MASK 0xf00000 +#define D18F3x140_Reserved_31_24_OFFSET 24 +#define D18F3x140_Reserved_31_24_WIDTH 8 +#define D18F3x140_Reserved_31_24_MASK 0xff000000 + +/// D18F3x140 +typedef union { + struct { ///< + UINT32 UpReqTok:2 ; ///< + UINT32 DnReqTok:2 ; ///< + UINT32 UpPreqTok:2 ; ///< + UINT32 DnPreqTok:2 ; ///< + UINT32 UpRspTok:2 ; ///< + UINT32 DnRspTok:2 ; ///< + UINT32 IsocReqTok:2 ; ///< + UINT32 IsocPreqTok:2 ; ///< + UINT32 IsocRspTok:2 ; ///< + UINT32 Reserved_19_18:2 ; ///< + UINT32 FreeTok:4 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x140_STRUCT; + +// **** D18F3x144 Register Definition **** +// Address +#define D18F3x144_ADDRESS 0x144 + +// Type +#define D18F3x144_TYPE TYPE_D18F3 +// Field Data +#define D18F3x144_RspTok_OFFSET 0 +#define D18F3x144_RspTok_WIDTH 4 +#define D18F3x144_RspTok_MASK 0xf +#define D18F3x144_ProbeTok_OFFSET 4 +#define D18F3x144_ProbeTok_WIDTH 4 +#define D18F3x144_ProbeTok_MASK 0xf0 +#define D18F3x144_Reserved_31_8_OFFSET 8 +#define D18F3x144_Reserved_31_8_WIDTH 24 +#define D18F3x144_Reserved_31_8_MASK 0xffffff00 + +/// D18F3x144 +typedef union { + struct { ///< + UINT32 RspTok:4 ; ///< + UINT32 ProbeTok:4 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x144_STRUCT; + +// **** D18F3x148 Register Definition **** +// Address +#define D18F3x148_ADDRESS 0x148 + +// Type +#define D18F3x148_TYPE TYPE_D18F3 +// Field Data +#define D18F3x148_ReqTok0_OFFSET 0 +#define D18F3x148_ReqTok0_WIDTH 2 +#define D18F3x148_ReqTok0_MASK 0x3 +#define D18F3x148_PReqTok0_OFFSET 2 +#define D18F3x148_PReqTok0_WIDTH 2 +#define D18F3x148_PReqTok0_MASK 0xc +#define D18F3x148_RspTok0_OFFSET 4 +#define D18F3x148_RspTok0_WIDTH 2 +#define D18F3x148_RspTok0_MASK 0x30 +#define D18F3x148_ProbeTok0_OFFSET 6 +#define D18F3x148_ProbeTok0_WIDTH 2 +#define D18F3x148_ProbeTok0_MASK 0xc0 +#define D18F3x148_IsocReqTok0_OFFSET 8 +#define D18F3x148_IsocReqTok0_WIDTH 2 +#define D18F3x148_IsocReqTok0_MASK 0x300 +#define D18F3x148_IsocPreqTok0_OFFSET 10 +#define D18F3x148_IsocPreqTok0_WIDTH 2 +#define D18F3x148_IsocPreqTok0_MASK 0xc00 +#define D18F3x148_IsocRspTok0_OFFSET 12 +#define D18F3x148_IsocRspTok0_WIDTH 2 +#define D18F3x148_IsocRspTok0_MASK 0x3000 +#define D18F3x148_FreeTok_1_0__OFFSET 14 +#define D18F3x148_FreeTok_1_0__WIDTH 2 +#define D18F3x148_FreeTok_1_0__MASK 0xc000 +#define D18F3x148_ReqTok1_OFFSET 16 +#define D18F3x148_ReqTok1_WIDTH 2 +#define D18F3x148_ReqTok1_MASK 0x30000 +#define D18F3x148_PReqTok1_OFFSET 18 +#define D18F3x148_PReqTok1_WIDTH 2 +#define D18F3x148_PReqTok1_MASK 0xc0000 +#define D18F3x148_RspTok1_OFFSET 20 +#define D18F3x148_RspTok1_WIDTH 2 +#define D18F3x148_RspTok1_MASK 0x300000 +#define D18F3x148_ProbeTok1_OFFSET 22 +#define D18F3x148_ProbeTok1_WIDTH 2 +#define D18F3x148_ProbeTok1_MASK 0xc00000 +#define D18F3x148_IsocReqTok1_OFFSET 24 +#define D18F3x148_IsocReqTok1_WIDTH 1 +#define D18F3x148_IsocReqTok1_MASK 0x1000000 +#define D18F3x148_Reserved_25_25_OFFSET 25 +#define D18F3x148_Reserved_25_25_WIDTH 1 +#define D18F3x148_Reserved_25_25_MASK 0x2000000 +#define D18F3x148_IsocPreqTok1_OFFSET 26 +#define D18F3x148_IsocPreqTok1_WIDTH 1 +#define D18F3x148_IsocPreqTok1_MASK 0x4000000 +#define D18F3x148_Reserved_27_27_OFFSET 27 +#define D18F3x148_Reserved_27_27_WIDTH 1 +#define D18F3x148_Reserved_27_27_MASK 0x8000000 +#define D18F3x148_IsocRspTok1_OFFSET 28 +#define D18F3x148_IsocRspTok1_WIDTH 1 +#define D18F3x148_IsocRspTok1_MASK 0x10000000 +#define D18F3x148_Reserved_29_29_OFFSET 29 +#define D18F3x148_Reserved_29_29_WIDTH 1 +#define D18F3x148_Reserved_29_29_MASK 0x20000000 +#define D18F3x148_FreeTok_3_2__OFFSET 30 +#define D18F3x148_FreeTok_3_2__WIDTH 2 +#define D18F3x148_FreeTok_3_2__MASK 0xc0000000 + +/// D18F3x148 +typedef union { + struct { ///< + UINT32 ReqTok0:2 ; ///< + UINT32 PReqTok0:2 ; ///< + UINT32 RspTok0:2 ; ///< + UINT32 ProbeTok0:2 ; ///< + UINT32 IsocReqTok0:2 ; ///< + UINT32 IsocPreqTok0:2 ; ///< + UINT32 IsocRspTok0:2 ; ///< + UINT32 FreeTok_1_0_:2 ; ///< + UINT32 ReqTok1:2 ; ///< + UINT32 PReqTok1:2 ; ///< + UINT32 RspTok1:2 ; ///< + UINT32 ProbeTok1:2 ; ///< + UINT32 IsocReqTok1:1 ; ///< + UINT32 Reserved_25_25:1 ; ///< + UINT32 IsocPreqTok1:1 ; ///< + UINT32 Reserved_27_27:1 ; ///< + UINT32 IsocRspTok1:1 ; ///< + UINT32 Reserved_29_29:1 ; ///< + UINT32 FreeTok_3_2_:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x148_STRUCT; + +// **** D18F3x17C Register Definition **** +// Address +#define D18F3x17C_ADDRESS 0x17c + +// Type +#define D18F3x17C_TYPE TYPE_D18F3 +// Field Data +#define D18F3x17C_SPQPrbFreeCBC_OFFSET 0 +#define D18F3x17C_SPQPrbFreeCBC_WIDTH 4 +#define D18F3x17C_SPQPrbFreeCBC_MASK 0xf +#define D18F3x17C_Reserved_31_4_OFFSET 4 +#define D18F3x17C_Reserved_31_4_WIDTH 28 +#define D18F3x17C_Reserved_31_4_MASK 0xfffffff0 + +/// D18F3x17C +typedef union { + struct { ///< + UINT32 SPQPrbFreeCBC:4 ; ///< + UINT32 Reserved_31_4:28; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x17C_STRUCT; + +// **** D18F3x180 Register Definition **** +// Address +#define D18F3x180_ADDRESS 0x180 + +// Type +#define D18F3x180_TYPE TYPE_D18F3 +// Field Data +#define D18F3x180_Reserved_1_0_OFFSET 0 +#define D18F3x180_Reserved_1_0_WIDTH 2 +#define D18F3x180_Reserved_1_0_MASK 0x3 +#define D18F3x180_WDTCntSel_3__OFFSET 2 +#define D18F3x180_WDTCntSel_3__WIDTH 1 +#define D18F3x180_WDTCntSel_3__MASK 0x4 +#define D18F3x180_ChgDatErrToTgtAbort_OFFSET 3 +#define D18F3x180_ChgDatErrToTgtAbort_WIDTH 1 +#define D18F3x180_ChgDatErrToTgtAbort_MASK 0x8 +#define D18F3x180_ChgMstAbortToNoErr_OFFSET 4 +#define D18F3x180_ChgMstAbortToNoErr_WIDTH 1 +#define D18F3x180_ChgMstAbortToNoErr_MASK 0x10 +#define D18F3x180_DisPciCfgCpuMstAbortRsp_OFFSET 5 +#define D18F3x180_DisPciCfgCpuMstAbortRsp_WIDTH 1 +#define D18F3x180_DisPciCfgCpuMstAbortRsp_MASK 0x20 +#define D18F3x180_SyncFloodOnDatErr_OFFSET 6 +#define D18F3x180_SyncFloodOnDatErr_WIDTH 1 +#define D18F3x180_SyncFloodOnDatErr_MASK 0x40 +#define D18F3x180_SyncFloodOnTgtAbortErr_OFFSET 7 +#define D18F3x180_SyncFloodOnTgtAbortErr_WIDTH 1 +#define D18F3x180_SyncFloodOnTgtAbortErr_MASK 0x80 +#define D18F3x180_PwP2pDatErrLclPropDis_OFFSET 18 +#define D18F3x180_PwP2pDatErrLclPropDis_WIDTH 1 +#define D18F3x180_PwP2pDatErrLclPropDis_MASK 0x40000 +#define D18F3x180_PwP2pDatErrRmtPropDis_OFFSET 19 +#define D18F3x180_PwP2pDatErrRmtPropDis_WIDTH 1 +#define D18F3x180_PwP2pDatErrRmtPropDis_MASK 0x80000 +#define D18F3x180_SyncFloodOnL3LeakErr_OFFSET 20 +#define D18F3x180_SyncFloodOnL3LeakErr_WIDTH 1 +#define D18F3x180_SyncFloodOnL3LeakErr_MASK 0x100000 +#define D18F3x180_SyncFloodOnCpuLeakErr_OFFSET 21 +#define D18F3x180_SyncFloodOnCpuLeakErr_WIDTH 1 +#define D18F3x180_SyncFloodOnCpuLeakErr_MASK 0x200000 +#define D18F3x180_SyncFloodOnTblWalkErr_OFFSET 22 +#define D18F3x180_SyncFloodOnTblWalkErr_WIDTH 1 +#define D18F3x180_SyncFloodOnTblWalkErr_MASK 0x400000 +#define D18F3x180_Reserved_23_23_OFFSET 23 +#define D18F3x180_Reserved_23_23_WIDTH 1 +#define D18F3x180_Reserved_23_23_MASK 0x800000 +#define D18F3x180_McaLogErrAddrWdtErr_OFFSET 24 +#define D18F3x180_McaLogErrAddrWdtErr_WIDTH 1 +#define D18F3x180_McaLogErrAddrWdtErr_MASK 0x1000000 +#define D18F3x180_Reserved_25_25_OFFSET 25 +#define D18F3x180_Reserved_25_25_WIDTH 1 +#define D18F3x180_Reserved_25_25_MASK 0x2000000 +#define D18F3x180_ChgUcToCeEn_OFFSET 26 +#define D18F3x180_ChgUcToCeEn_WIDTH 1 +#define D18F3x180_ChgUcToCeEn_MASK 0x4000000 +#define D18F3x180_Reserved_31_27_OFFSET 27 +#define D18F3x180_Reserved_31_27_WIDTH 5 +#define D18F3x180_Reserved_31_27_MASK 0xf8000000 + +/// D18F3x180 +typedef union { + struct { ///< + UINT32 Reserved_1_0:2 ; ///< + UINT32 WDTCntSel_3_:1 ; ///< + UINT32 ChgDatErrToTgtAbort:1 ; ///< + UINT32 ChgMstAbortToNoErr:1 ; ///< + UINT32 DisPciCfgCpuMstAbortRsp:1 ; ///< + UINT32 SyncFloodOnDatErr:1 ; ///< + UINT32 SyncFloodOnTgtAbortErr:1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :7 ; ///< + UINT32 PwP2pDatErrLclPropDis:1 ; ///< + UINT32 PwP2pDatErrRmtPropDis:1 ; ///< + UINT32 SyncFloodOnL3LeakErr:1 ; ///< + UINT32 SyncFloodOnCpuLeakErr:1 ; ///< + UINT32 SyncFloodOnTblWalkErr:1 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 McaLogErrAddrWdtErr:1 ; ///< + UINT32 Reserved_25_25:1 ; ///< + UINT32 ChgUcToCeEn:1 ; ///< + UINT32 Reserved_31_27:5 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x180_STRUCT; + +// **** D18F3x190 Register Definition **** +// Address +#define D18F3x190_ADDRESS 0x190 + +// Type +#define D18F3x190_TYPE TYPE_D18F3 +// Field Data +#define D18F3x190_DisCore_OFFSET 0 +#define D18F3x190_DisCore_WIDTH 32 +#define D18F3x190_DisCore_MASK 0xffffffff + +/// D18F3x190 +typedef union { + struct { ///< + UINT32 DisCore:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x190_STRUCT; + +// **** D18F3x1A0 Register Definition **** +// Address +#define D18F3x1A0_ADDRESS 0x1a0 + +// Type +#define D18F3x1A0_TYPE TYPE_D18F3 +// Field Data +#define D18F3x1A0_CpuCmdBufCnt_OFFSET 0 +#define D18F3x1A0_CpuCmdBufCnt_WIDTH 3 +#define D18F3x1A0_CpuCmdBufCnt_MASK 0x7 +#define D18F3x1A0_Reserved_3_3_OFFSET 3 +#define D18F3x1A0_Reserved_3_3_WIDTH 1 +#define D18F3x1A0_Reserved_3_3_MASK 0x8 +#define D18F3x1A0_Reserved_8_4_OFFSET 4 +#define D18F3x1A0_Reserved_8_4_WIDTH 5 +#define D18F3x1A0_Reserved_8_4_MASK 0x1f0 +#define D18F3x1A0_Reserved_11_9_OFFSET 9 +#define D18F3x1A0_Reserved_11_9_WIDTH 3 +#define D18F3x1A0_Reserved_11_9_MASK 0xe00 +#define D18F3x1A0_Reserved_14_12_OFFSET 12 +#define D18F3x1A0_Reserved_14_12_WIDTH 3 +#define D18F3x1A0_Reserved_14_12_MASK 0x7000 +#define D18F3x1A0_Reserved_15_15_OFFSET 15 +#define D18F3x1A0_Reserved_15_15_WIDTH 1 +#define D18F3x1A0_Reserved_15_15_MASK 0x8000 +#define D18F3x1A0_CpuToNbFreeBufCnt_OFFSET 16 +#define D18F3x1A0_CpuToNbFreeBufCnt_WIDTH 2 +#define D18F3x1A0_CpuToNbFreeBufCnt_MASK 0x30000 +#define D18F3x1A0_Reserved_31_18_OFFSET 18 +#define D18F3x1A0_Reserved_31_18_WIDTH 14 +#define D18F3x1A0_Reserved_31_18_MASK 0xfffc0000 + +/// D18F3x1A0 +typedef union { + struct { ///< + UINT32 CpuCmdBufCnt:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 Reserved_8_4:5 ; ///< + UINT32 Reserved_11_9:3 ; ///< + UINT32 Reserved_14_12:3 ; ///< + UINT32 Reserved_15_15:1 ; ///< + UINT32 CpuToNbFreeBufCnt:2 ; ///< + UINT32 Reserved_31_18:14; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x1A0_STRUCT; + +// **** D18F3x1CC Register Definition **** +// Address +#define D18F3x1CC_ADDRESS 0x1cc + +// Type +#define D18F3x1CC_TYPE TYPE_D18F3 +// Field Data +#define D18F3x1CC_LvtOffset_OFFSET 0 +#define D18F3x1CC_LvtOffset_WIDTH 4 +#define D18F3x1CC_LvtOffset_MASK 0xf +#define D18F3x1CC_Reserved_7_4_OFFSET 4 +#define D18F3x1CC_Reserved_7_4_WIDTH 4 +#define D18F3x1CC_Reserved_7_4_MASK 0xf0 +#define D18F3x1CC_LvtOffsetVal_OFFSET 8 +#define D18F3x1CC_LvtOffsetVal_WIDTH 1 +#define D18F3x1CC_LvtOffsetVal_MASK 0x100 +#define D18F3x1CC_Reserved_31_9_OFFSET 9 +#define D18F3x1CC_Reserved_31_9_WIDTH 23 +#define D18F3x1CC_Reserved_31_9_MASK 0xfffffe00 + +/// D18F3x1CC +typedef union { + struct { ///< + UINT32 LvtOffset:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 LvtOffsetVal:1 ; ///< + UINT32 Reserved_31_9:23; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x1CC_STRUCT; + + +// **** D18F3x1FC Register Definition **** +// Address +#define D18F3x1FC_ADDRESS 0x1fc + +// Type +#define D18F3x1FC_TYPE TYPE_D18F3 +// Field Data +#define D18F3x1FC_DiDtMode_OFFSET 0 +#define D18F3x1FC_DiDtMode_WIDTH 1 +#define D18F3x1FC_DiDtMode_MASK 0x1 +#define D18F3x1FC_DiDtCfg0_OFFSET 1 +#define D18F3x1FC_DiDtCfg0_WIDTH 5 +#define D18F3x1FC_DiDtCfg0_MASK 0x3e +#define D18F3x1FC_DiDtCfg1_OFFSET 6 +#define D18F3x1FC_DiDtCfg1_WIDTH 8 +#define D18F3x1FC_DiDtCfg1_MASK 0x3fc0 +#define D18F3x1FC_DiDtCfg2_OFFSET 14 +#define D18F3x1FC_DiDtCfg2_WIDTH 2 +#define D18F3x1FC_DiDtCfg2_MASK 0xc000 +#define D18F3x1FC_Reserved_16_16_OFFSET 16 +#define D18F3x1FC_Reserved_16_16_WIDTH 1 +#define D18F3x1FC_Reserved_16_16_MASK 0x10000 +#define D18F3x1FC_DiDtCfg4_OFFSET 17 +#define D18F3x1FC_DiDtCfg4_WIDTH 3 +#define D18F3x1FC_DiDtCfg4_MASK 0xe0000 +#define D18F3x1FC_Reserved_23_20_OFFSET 20 +#define D18F3x1FC_Reserved_23_20_WIDTH 4 +#define D18F3x1FC_Reserved_23_20_MASK 0xf00000 +#define D18F3x1FC_SWDllCapTableEn_OFFSET 24 +#define D18F3x1FC_SWDllCapTableEn_WIDTH 1 +#define D18F3x1FC_SWDllCapTableEn_MASK 0x1000000 +#define D18F3x1FC_DllProcFreqCtlIndex2Rate50_OFFSET 25 +#define D18F3x1FC_DllProcFreqCtlIndex2Rate50_WIDTH 4 +#define D18F3x1FC_DllProcFreqCtlIndex2Rate50_MASK 0x1e000000 + +/// D18F3x1FC +typedef union { + struct { ///< + UINT32 DiDtMode:1 ; ///< + UINT32 DiDtCfg0:5 ; ///< + UINT32 DiDtCfg1:8 ; ///< + UINT32 DiDtCfg2:2 ; ///< + UINT32 Reserved_16_16:1 ; ///< + UINT32 DiDtCfg4:3 ; ///< + UINT32 Reserved_23_20:4 ; ///< + UINT32 SWDllCapTableEn:1 ; ///< + UINT32 DllProcFreqCtlIndex2Rate50:4 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3x1FC_STRUCT; + +// **** D18F4x00 Register Definition **** +// Address +#define D18F4x00_ADDRESS 0x0 + +// Type +#define D18F4x00_TYPE TYPE_D18F4 +// Field Data +#define D18F4x00_VendorID_OFFSET 0 +#define D18F4x00_VendorID_WIDTH 16 +#define D18F4x00_VendorID_MASK 0xffff +#define D18F4x00_DeviceID_OFFSET 16 +#define D18F4x00_DeviceID_WIDTH 16 +#define D18F4x00_DeviceID_MASK 0xffff0000 + +/// D18F4x00 +typedef union { + struct { ///< + UINT32 VendorID:16; ///< + UINT32 DeviceID:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F4x00_STRUCT; + +// **** D18F4x04 Register Definition **** +// Address +#define D18F4x04_ADDRESS 0x4 + +// Type +#define D18F4x04_TYPE TYPE_D18F4 +// Field Data +#define D18F4x04_Command_OFFSET 0 +#define D18F4x04_Command_WIDTH 16 +#define D18F4x04_Command_MASK 0xffff +#define D18F4x04_Status_OFFSET 16 +#define D18F4x04_Status_WIDTH 16 +#define D18F4x04_Status_MASK 0xffff0000 + +/// D18F4x04 +typedef union { + struct { ///< + UINT32 Command:16; ///< + UINT32 Status:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F4x04_STRUCT; + +// **** D18F4x08 Register Definition **** +// Address +#define D18F4x08_ADDRESS 0x8 + +// Type +#define D18F4x08_TYPE TYPE_D18F4 +// Field Data +#define D18F4x08_RevID_OFFSET 0 +#define D18F4x08_RevID_WIDTH 8 +#define D18F4x08_RevID_MASK 0xff +#define D18F4x08_ClassCode_OFFSET 8 +#define D18F4x08_ClassCode_WIDTH 24 +#define D18F4x08_ClassCode_MASK 0xffffff00 + +/// D18F4x08 +typedef union { + struct { ///< + UINT32 RevID:8 ; ///< + UINT32 ClassCode:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F4x08_STRUCT; + +// **** D18F4x0C Register Definition **** +// Address +#define D18F4x0C_ADDRESS 0xc + +// Type +#define D18F4x0C_TYPE TYPE_D18F4 +// Field Data +#define D18F4x0C_HeaderTypeReg_OFFSET 0 +#define D18F4x0C_HeaderTypeReg_WIDTH 32 +#define D18F4x0C_HeaderTypeReg_MASK 0xffffffff + +/// D18F4x0C +typedef union { + struct { ///< + UINT32 HeaderTypeReg:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F4x0C_STRUCT; + +// **** D18F4x34 Register Definition **** +// Address +#define D18F4x34_ADDRESS 0x34 + +// Type +#define D18F4x34_TYPE TYPE_D18F4 +// Field Data +#define D18F4x34_CapPtr_OFFSET 0 +#define D18F4x34_CapPtr_WIDTH 8 +#define D18F4x34_CapPtr_MASK 0xff +#define D18F4x34_Reserved_31_8_OFFSET 8 +#define D18F4x34_Reserved_31_8_WIDTH 24 +#define D18F4x34_Reserved_31_8_MASK 0xffffff00 + +/// D18F4x34 +typedef union { + struct { ///< + UINT32 CapPtr:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F4x34_STRUCT; + +// **** D18F4x108 Register Definition **** +// Address +#define D18F4x108_ADDRESS 0x108 + +// Type +#define D18F4x108_TYPE TYPE_D18F4 +// Field Data +#define D18F4x108_Reserved_31_0_OFFSET 0 +#define D18F4x108_Reserved_31_0_WIDTH 32 +#define D18F4x108_Reserved_31_0_MASK 0xffffffff + +/// D18F4x108 +typedef union { + struct { ///< + UINT32 Reserved_31_0:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F4x108_STRUCT; + +// **** D18F4x10C Register Definition **** +// Address +#define D18F4x10C_ADDRESS 0x10c + +// Type +#define D18F4x10C_TYPE TYPE_D18F4 +// Field Data +#define D18F4x10C_NodeTdpLimit_OFFSET 0 +#define D18F4x10C_NodeTdpLimit_WIDTH 12 +#define D18F4x10C_NodeTdpLimit_MASK 0xfff +#define D18F4x10C_Reserved_31_12_OFFSET 12 +#define D18F4x10C_Reserved_31_12_WIDTH 20 +#define D18F4x10C_Reserved_31_12_MASK 0xfffff000 + +/// D18F4x10C +typedef union { + struct { ///< + UINT32 NodeTdpLimit:12; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F4x10C_STRUCT; + +// **** D18F4x110 Register Definition **** +// Address +#define D18F4x110_ADDRESS 0x110 + +// Type +#define D18F4x110_TYPE TYPE_D18F4 +// Field Data +#define D18F4x110_CSampleTimer_OFFSET 0 +#define D18F4x110_CSampleTimer_WIDTH 12 +#define D18F4x110_CSampleTimer_MASK 0xfff +#define D18F4x110_Reserved_12_12_OFFSET 12 +#define D18F4x110_Reserved_12_12_WIDTH 1 +#define D18F4x110_Reserved_12_12_MASK 0x1000 +#define D18F4x110_MinResTmr_OFFSET 13 +#define D18F4x110_MinResTmr_WIDTH 8 +#define D18F4x110_MinResTmr_MASK 0x1fe000 +#define D18F4x110_Reserved_31_21_OFFSET 21 +#define D18F4x110_Reserved_31_21_WIDTH 11 +#define D18F4x110_Reserved_31_21_MASK 0xffe00000 + +/// D18F4x110 +typedef union { + struct { ///< + UINT32 CSampleTimer:12; ///< + UINT32 Reserved_12_12:1 ; ///< + UINT32 MinResTmr:8 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D18F4x110_STRUCT; + +// **** D18F4x118 Register Definition **** +// Address +#define D18F4x118_ADDRESS 0x118 + +// Type +#define D18F4x118_TYPE TYPE_D18F4 +// Field Data +#define D18F4x118_CpuPrbEnCstAct0_OFFSET 0 +#define D18F4x118_CpuPrbEnCstAct0_WIDTH 1 +#define D18F4x118_CpuPrbEnCstAct0_MASK 0x1 +#define D18F4x118_CacheFlushEnCstAct0_OFFSET 1 +#define D18F4x118_CacheFlushEnCstAct0_WIDTH 1 +#define D18F4x118_CacheFlushEnCstAct0_MASK 0x2 +#define D18F4x118_CacheFlushTmrSelCstAct0_OFFSET 2 +#define D18F4x118_CacheFlushTmrSelCstAct0_WIDTH 2 +#define D18F4x118_CacheFlushTmrSelCstAct0_MASK 0xc +#define D18F4x118_Reserved_4_4_OFFSET 4 +#define D18F4x118_Reserved_4_4_WIDTH 1 +#define D18F4x118_Reserved_4_4_MASK 0x10 +#define D18F4x118_ClkDivisorCstAct0_OFFSET 5 +#define D18F4x118_ClkDivisorCstAct0_WIDTH 3 +#define D18F4x118_ClkDivisorCstAct0_MASK 0xe0 +#define D18F4x118_PwrGateEnCstAct0_OFFSET 8 +#define D18F4x118_PwrGateEnCstAct0_WIDTH 1 +#define D18F4x118_PwrGateEnCstAct0_MASK 0x100 +#define D18F4x118_PwrOffEnCstAct0_OFFSET 9 +#define D18F4x118_PwrOffEnCstAct0_WIDTH 1 +#define D18F4x118_PwrOffEnCstAct0_MASK 0x200 +#define D18F4x118_NbPwrGate0_OFFSET 10 +#define D18F4x118_NbPwrGate0_WIDTH 1 +#define D18F4x118_NbPwrGate0_MASK 0x400 +#define D18F4x118_NbClkGate0_OFFSET 11 +#define D18F4x118_NbClkGate0_WIDTH 1 +#define D18F4x118_NbClkGate0_MASK 0x800 +#define D18F4x118_SelfRefr0_OFFSET 12 +#define D18F4x118_SelfRefr0_WIDTH 1 +#define D18F4x118_SelfRefr0_MASK 0x1000 +#define D18F4x118_SelfRefrEarly0_OFFSET 13 +#define D18F4x118_SelfRefrEarly0_WIDTH 1 +#define D18F4x118_SelfRefrEarly0_MASK 0x2000 +#define D18F4x118_Reserved_15_14_OFFSET 14 +#define D18F4x118_Reserved_15_14_WIDTH 2 +#define D18F4x118_Reserved_15_14_MASK 0xc000 +#define D18F4x118_CpuPrbEnCstAct1_OFFSET 16 +#define D18F4x118_CpuPrbEnCstAct1_WIDTH 1 +#define D18F4x118_CpuPrbEnCstAct1_MASK 0x10000 +#define D18F4x118_CacheFlushEnCstAct1_OFFSET 17 +#define D18F4x118_CacheFlushEnCstAct1_WIDTH 1 +#define D18F4x118_CacheFlushEnCstAct1_MASK 0x20000 +#define D18F4x118_CacheFlushTmrSelCstAct1_OFFSET 18 +#define D18F4x118_CacheFlushTmrSelCstAct1_WIDTH 2 +#define D18F4x118_CacheFlushTmrSelCstAct1_MASK 0xc0000 +#define D18F4x118_Reserved_20_20_OFFSET 20 +#define D18F4x118_Reserved_20_20_WIDTH 1 +#define D18F4x118_Reserved_20_20_MASK 0x100000 +#define D18F4x118_ClkDivisorCstAct1_OFFSET 21 +#define D18F4x118_ClkDivisorCstAct1_WIDTH 3 +#define D18F4x118_ClkDivisorCstAct1_MASK 0xe00000 +#define D18F4x118_PwrGateEnCstAct1_OFFSET 24 +#define D18F4x118_PwrGateEnCstAct1_WIDTH 1 +#define D18F4x118_PwrGateEnCstAct1_MASK 0x1000000 +#define D18F4x118_PwrOffEnCstAct1_OFFSET 25 +#define D18F4x118_PwrOffEnCstAct1_WIDTH 1 +#define D18F4x118_PwrOffEnCstAct1_MASK 0x2000000 +#define D18F4x118_NbPwrGate1_OFFSET 26 +#define D18F4x118_NbPwrGate1_WIDTH 1 +#define D18F4x118_NbPwrGate1_MASK 0x4000000 +#define D18F4x118_NbClkGate1_OFFSET 27 +#define D18F4x118_NbClkGate1_WIDTH 1 +#define D18F4x118_NbClkGate1_MASK 0x8000000 +#define D18F4x118_SelfRefr1_OFFSET 28 +#define D18F4x118_SelfRefr1_WIDTH 1 +#define D18F4x118_SelfRefr1_MASK 0x10000000 +#define D18F4x118_SelfRefrEarly1_OFFSET 29 +#define D18F4x118_SelfRefrEarly1_WIDTH 1 +#define D18F4x118_SelfRefrEarly1_MASK 0x20000000 +#define D18F4x118_Reserved_31_30_OFFSET 30 +#define D18F4x118_Reserved_31_30_WIDTH 2 +#define D18F4x118_Reserved_31_30_MASK 0xc0000000 + +/// D18F4x118 +typedef union { + struct { ///< + UINT32 CpuPrbEnCstAct0:1 ; ///< + UINT32 CacheFlushEnCstAct0:1 ; ///< + UINT32 CacheFlushTmrSelCstAct0:2 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 ClkDivisorCstAct0:3 ; ///< + UINT32 PwrGateEnCstAct0:1 ; ///< + UINT32 PwrOffEnCstAct0:1 ; ///< + UINT32 NbPwrGate0:1 ; ///< + UINT32 NbClkGate0:1 ; ///< + UINT32 SelfRefr0:1 ; ///< + UINT32 SelfRefrEarly0:1 ; ///< + UINT32 Reserved_15_14:2 ; ///< + UINT32 CpuPrbEnCstAct1:1 ; ///< + UINT32 CacheFlushEnCstAct1:1 ; ///< + UINT32 CacheFlushTmrSelCstAct1:2 ; ///< + UINT32 Reserved_20_20:1 ; ///< + UINT32 ClkDivisorCstAct1:3 ; ///< + UINT32 PwrGateEnCstAct1:1 ; ///< + UINT32 PwrOffEnCstAct1:1 ; ///< + UINT32 NbPwrGate1:1 ; ///< + UINT32 NbClkGate1:1 ; ///< + UINT32 SelfRefr1:1 ; ///< + UINT32 SelfRefrEarly1:1 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F4x118_STRUCT; + +// **** D18F4x11C Register Definition **** +// Address +#define D18F4x11C_ADDRESS 0x11c + +// Type +#define D18F4x11C_TYPE TYPE_D18F4 +// Field Data +#define D18F4x11C_CpuPrbEnCstAct2_OFFSET 0 +#define D18F4x11C_CpuPrbEnCstAct2_WIDTH 1 +#define D18F4x11C_CpuPrbEnCstAct2_MASK 0x1 +#define D18F4x11C_CacheFlushEnCstAct2_OFFSET 1 +#define D18F4x11C_CacheFlushEnCstAct2_WIDTH 1 +#define D18F4x11C_CacheFlushEnCstAct2_MASK 0x2 +#define D18F4x11C_CacheFlushTmrSelCstAct2_OFFSET 2 +#define D18F4x11C_CacheFlushTmrSelCstAct2_WIDTH 2 +#define D18F4x11C_CacheFlushTmrSelCstAct2_MASK 0xc +#define D18F4x11C_Reserved_4_4_OFFSET 4 +#define D18F4x11C_Reserved_4_4_WIDTH 1 +#define D18F4x11C_Reserved_4_4_MASK 0x10 +#define D18F4x11C_ClkDivisorCstAct2_OFFSET 5 +#define D18F4x11C_ClkDivisorCstAct2_WIDTH 3 +#define D18F4x11C_ClkDivisorCstAct2_MASK 0xe0 +#define D18F4x11C_PwrGateEnCstAct2_OFFSET 8 +#define D18F4x11C_PwrGateEnCstAct2_WIDTH 1 +#define D18F4x11C_PwrGateEnCstAct2_MASK 0x100 +#define D18F4x11C_PwrOffEnCstAct2_OFFSET 9 +#define D18F4x11C_PwrOffEnCstAct2_WIDTH 1 +#define D18F4x11C_PwrOffEnCstAct2_MASK 0x200 +#define D18F4x11C_NbPwrGate2_OFFSET 10 +#define D18F4x11C_NbPwrGate2_WIDTH 1 +#define D18F4x11C_NbPwrGate2_MASK 0x400 +#define D18F4x11C_NbClkGate2_OFFSET 11 +#define D18F4x11C_NbClkGate2_WIDTH 1 +#define D18F4x11C_NbClkGate2_MASK 0x800 +#define D18F4x11C_SelfRefr2_OFFSET 12 +#define D18F4x11C_SelfRefr2_WIDTH 1 +#define D18F4x11C_SelfRefr2_MASK 0x1000 +#define D18F4x11C_SelfRefrEarly2_OFFSET 13 +#define D18F4x11C_SelfRefrEarly2_WIDTH 1 +#define D18F4x11C_SelfRefrEarly2_MASK 0x2000 +#define D18F4x11C_Reserved_31_14_OFFSET 14 +#define D18F4x11C_Reserved_31_14_WIDTH 18 +#define D18F4x11C_Reserved_31_14_MASK 0xffffc000 + +/// D18F4x11C +typedef union { + struct { ///< + UINT32 CpuPrbEnCstAct2:1 ; ///< + UINT32 CacheFlushEnCstAct2:1 ; ///< + UINT32 CacheFlushTmrSelCstAct2:2 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 ClkDivisorCstAct2:3 ; ///< + UINT32 PwrGateEnCstAct2:1 ; ///< + UINT32 PwrOffEnCstAct2:1 ; ///< + UINT32 NbPwrGate2:1 ; ///< + UINT32 NbClkGate2:1 ; ///< + UINT32 SelfRefr2:1 ; ///< + UINT32 SelfRefrEarly2:1 ; ///< + UINT32 Reserved_31_14:18; ///< + } Field; ///< + UINT32 Value; ///< +} D18F4x11C_STRUCT; + +// **** D18F4x124 Register Definition **** +// Address +#define D18F4x124_ADDRESS 0x124 + +// Type +#define D18F4x124_TYPE TYPE_D18F4 +// Field Data +#define D18F4x124_Reserved_21_0_OFFSET 0 +#define D18F4x124_Reserved_21_0_WIDTH 22 +#define D18F4x124_Reserved_21_0_MASK 0x3fffff +#define D18F4x124_IntMonPC6En_OFFSET 22 +#define D18F4x124_IntMonPC6En_WIDTH 1 +#define D18F4x124_IntMonPC6En_MASK 0x400000 +#define D18F4x124_IntMonPC6Limit_OFFSET 23 +#define D18F4x124_IntMonPC6Limit_WIDTH 4 +#define D18F4x124_IntMonPC6Limit_MASK 0x7800000 +#define D18F4x124_Reserved_31_27_OFFSET 27 +#define D18F4x124_Reserved_31_27_WIDTH 5 +#define D18F4x124_Reserved_31_27_MASK 0xf8000000 + +/// D18F4x124 +typedef union { + struct { ///< + UINT32 Reserved_21_0:22; ///< + UINT32 IntMonPC6En:1 ; ///< + UINT32 IntMonPC6Limit:4 ; ///< + UINT32 Reserved_31_27:5 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F4x124_STRUCT; + +// **** D18F4x128 Register Definition **** +// Address +#define D18F4x128_ADDRESS 0x128 + +// Type +#define D18F4x128_TYPE TYPE_D18F4 +// Field Data +#define D18F4x128_Reserved_0_0_OFFSET 0 +#define D18F4x128_Reserved_0_0_WIDTH 1 +#define D18F4x128_Reserved_0_0_MASK 0x1 +#define D18F4x128_CoreCstatePolicy_OFFSET 1 +#define D18F4x128_CoreCstatePolicy_WIDTH 1 +#define D18F4x128_CoreCstatePolicy_MASK 0x2 +#define D18F4x128_HaltCstateIndex_OFFSET 2 +#define D18F4x128_HaltCstateIndex_WIDTH 3 +#define D18F4x128_HaltCstateIndex_MASK 0x1c +#define D18F4x128_CacheFlushTmr_OFFSET 5 +#define D18F4x128_CacheFlushTmr_WIDTH 7 +#define D18F4x128_CacheFlushTmr_MASK 0xfe0 +#define D18F4x128_Reserved_17_12_OFFSET 12 +#define D18F4x128_Reserved_17_12_WIDTH 6 +#define D18F4x128_Reserved_17_12_MASK 0x3f000 +#define D18F4x128_CacheFlushSucMonThreshold_OFFSET 18 +#define D18F4x128_CacheFlushSucMonThreshold_WIDTH 3 +#define D18F4x128_CacheFlushSucMonThreshold_MASK 0x1c0000 +#define D18F4x128_Reserved_30_21_OFFSET 21 +#define D18F4x128_Reserved_30_21_WIDTH 10 +#define D18F4x128_Reserved_30_21_MASK 0x7fe00000 +#define D18F4x128_CstateMsgDis_OFFSET 31 +#define D18F4x128_CstateMsgDis_WIDTH 1 +#define D18F4x128_CstateMsgDis_MASK 0x80000000 + +/// D18F4x128 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 CoreCstatePolicy:1 ; ///< + UINT32 HaltCstateIndex:3 ; ///< + UINT32 CacheFlushTmr:7 ; ///< + UINT32 Reserved_17_12:6 ; ///< + UINT32 CacheFlushSucMonThreshold:3 ; ///< + UINT32 Reserved_30_21:10; ///< + UINT32 CstateMsgDis:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F4x128_STRUCT; + +// **** D18F4x13C Register Definition **** +// Address +#define D18F4x13C_ADDRESS 0x13c + +// Type +#define D18F4x13C_TYPE TYPE_D18F4 +// Field Data +#define D18F4x13C_SmuPstateLimitEn_OFFSET 0 +#define D18F4x13C_SmuPstateLimitEn_WIDTH 1 +#define D18F4x13C_SmuPstateLimitEn_MASK 0x1 +#define D18F4x13C_SmuPstateLimit_OFFSET 1 +#define D18F4x13C_SmuPstateLimit_WIDTH 3 +#define D18F4x13C_SmuPstateLimit_MASK 0xe +#define D18F4x13C_Reserved_31_4_OFFSET 4 +#define D18F4x13C_Reserved_31_4_WIDTH 28 +#define D18F4x13C_Reserved_31_4_MASK 0xfffffff0 + +/// D18F4x13C +typedef union { + struct { ///< + UINT32 SmuPstateLimitEn:1 ; ///< + UINT32 SmuPstateLimit:3 ; ///< + UINT32 Reserved_31_4:28; ///< + } Field; ///< + UINT32 Value; ///< +} D18F4x13C_STRUCT; + +// **** D18F4x15C Register Definition **** +// Address +#define D18F4x15C_ADDRESS 0x15c + +// Type +#define D18F4x15C_TYPE TYPE_D18F4 +// Field Data +#define D18F4x15C_BoostSrc_OFFSET 0 +#define D18F4x15C_BoostSrc_WIDTH 2 +#define D18F4x15C_BoostSrc_MASK 0x3 +#define D18F4x15C_NumBoostStates_OFFSET 2 +#define D18F4x15C_NumBoostStates_WIDTH 3 +#define D18F4x15C_NumBoostStates_MASK 0x1c +#define D18F4x15C_Reserved_6_5_OFFSET 5 +#define D18F4x15C_Reserved_6_5_WIDTH 2 +#define D18F4x15C_Reserved_6_5_MASK 0x60 +#define D18F4x15C_ApmMasterEn_OFFSET 7 +#define D18F4x15C_ApmMasterEn_WIDTH 1 +#define D18F4x15C_ApmMasterEn_MASK 0x80 +#define D18F4x15C_Reserved_27_8_OFFSET 8 +#define D18F4x15C_Reserved_27_8_WIDTH 20 +#define D18F4x15C_Reserved_27_8_MASK 0xfffff00 +#define D18F4x15C_Reserved_30_28_OFFSET 28 +#define D18F4x15C_Reserved_30_28_WIDTH 3 +#define D18F4x15C_Reserved_30_28_MASK 0x70000000 +#define D18F4x15C_BoostLock_OFFSET 31 +#define D18F4x15C_BoostLock_WIDTH 1 +#define D18F4x15C_BoostLock_MASK 0x80000000 + +/// D18F4x15C +typedef union { + struct { ///< + UINT32 BoostSrc:2 ; ///< + UINT32 NumBoostStates:3 ; ///< + UINT32 Reserved_6_5:2 ; ///< + UINT32 ApmMasterEn:1 ; ///< + UINT32 Reserved_27_8:20; ///< + UINT32 Reserved_30_28:3 ; ///< + UINT32 BoostLock:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F4x15C_STRUCT; + + +// **** D18F4x164 Register Definition **** +// Address +#define D18F4x164_ADDRESS 0x164 + +// Type +#define D18F4x164_TYPE TYPE_D18F4 +// Field Data +#define D18F4x164_FixedErrata_OFFSET 0 +#define D18F4x164_FixedErrata_WIDTH 32 +#define D18F4x164_FixedErrata_MASK 0xffffffff + +/// D18F4x164 +typedef union { + struct { ///< + UINT32 FixedErrata:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F4x164_STRUCT; + +// **** D18F4x16C Register Definition **** +// Address +#define D18F4x16C_ADDRESS 0x16c + +// Type +#define D18F4x16C_TYPE TYPE_D18F4 +// Field Data +#define D18F4x16C_CstateBoost_OFFSET 6 +#define D18F4x16C_CstateBoost_WIDTH 3 +#define D18F4x16C_CstateBoost_MASK 0x1c0 +#define D18F4x16C_CstateCnt_OFFSET 9 +#define D18F4x16C_CstateCnt_WIDTH 3 +#define D18F4x16C_CstateCnt_MASK 0xe00 +#define D18F4x16C_Reserved_31_12_OFFSET 12 +#define D18F4x16C_Reserved_31_12_WIDTH 20 +#define D18F4x16C_Reserved_31_12_MASK 0xfffff000 + +/// D18F4x16C +typedef union { + struct { ///< + UINT32 :6 ; ///< + UINT32 CstateBoost:3 ; ///< + UINT32 CstateCnt:3 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D18F4x16C_STRUCT; + + +// **** D18F5x00 Register Definition **** +// Address +#define D18F5x00_ADDRESS 0x0 + +// Type +#define D18F5x00_TYPE TYPE_D18F5 +// Field Data +#define D18F5x00_VendorID_OFFSET 0 +#define D18F5x00_VendorID_WIDTH 16 +#define D18F5x00_VendorID_MASK 0xffff +#define D18F5x00_DeviceID_OFFSET 16 +#define D18F5x00_DeviceID_WIDTH 16 +#define D18F5x00_DeviceID_MASK 0xffff0000 + +/// D18F5x00 +typedef union { + struct { ///< + UINT32 VendorID:16; ///< + UINT32 DeviceID:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x00_STRUCT; + +// **** D18F5x04 Register Definition **** +// Address +#define D18F5x04_ADDRESS 0x4 + +// Type +#define D18F5x04_TYPE TYPE_D18F5 +// Field Data +#define D18F5x04_Command_OFFSET 0 +#define D18F5x04_Command_WIDTH 16 +#define D18F5x04_Command_MASK 0xffff +#define D18F5x04_Status_OFFSET 16 +#define D18F5x04_Status_WIDTH 16 +#define D18F5x04_Status_MASK 0xffff0000 + +/// D18F5x04 +typedef union { + struct { ///< + UINT32 Command:16; ///< + UINT32 Status:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x04_STRUCT; + +// **** D18F5x08 Register Definition **** +// Address +#define D18F5x08_ADDRESS 0x8 + +// Type +#define D18F5x08_TYPE TYPE_D18F5 +// Field Data +#define D18F5x08_RevID_OFFSET 0 +#define D18F5x08_RevID_WIDTH 8 +#define D18F5x08_RevID_MASK 0xff +#define D18F5x08_ClassCode_OFFSET 8 +#define D18F5x08_ClassCode_WIDTH 24 +#define D18F5x08_ClassCode_MASK 0xffffff00 + +/// D18F5x08 +typedef union { + struct { ///< + UINT32 RevID:8 ; ///< + UINT32 ClassCode:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x08_STRUCT; + +// **** D18F5x0C Register Definition **** +// Address +#define D18F5x0C_ADDRESS 0xc + +// Type +#define D18F5x0C_TYPE TYPE_D18F5 +// Field Data +#define D18F5x0C_HeaderTypeReg_OFFSET 0 +#define D18F5x0C_HeaderTypeReg_WIDTH 32 +#define D18F5x0C_HeaderTypeReg_MASK 0xffffffff + +/// D18F5x0C +typedef union { + struct { ///< + UINT32 HeaderTypeReg:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x0C_STRUCT; + +// **** D18F5x34 Register Definition **** +// Address +#define D18F5x34_ADDRESS 0x34 + +// Type +#define D18F5x34_TYPE TYPE_D18F5 +// Field Data +#define D18F5x34_CapPtr_OFFSET 0 +#define D18F5x34_CapPtr_WIDTH 8 +#define D18F5x34_CapPtr_MASK 0xff +#define D18F5x34_Reserved_31_8_OFFSET 8 +#define D18F5x34_Reserved_31_8_WIDTH 24 +#define D18F5x34_Reserved_31_8_MASK 0xffffff00 + +/// D18F5x34 +typedef union { + struct { ///< + UINT32 CapPtr:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x34_STRUCT; + +// **** D18F5x40 Register Definition **** +// Address +#define D18F5x40_ADDRESS 0x40 + +// Type +#define D18F5x40_TYPE TYPE_D18F5 +// Field Data +#define D18F5x40_EventSelect_7_0__OFFSET 0 +#define D18F5x40_EventSelect_7_0__WIDTH 8 +#define D18F5x40_EventSelect_7_0__MASK 0xff +#define D18F5x40_UnitMask_OFFSET 8 +#define D18F5x40_UnitMask_WIDTH 8 +#define D18F5x40_UnitMask_MASK 0xff00 +#define D18F5x40_Reserved_18_16_OFFSET 16 +#define D18F5x40_Reserved_18_16_WIDTH 3 +#define D18F5x40_Reserved_18_16_MASK 0x70000 +#define D18F5x40_Reserved_19_19_OFFSET 19 +#define D18F5x40_Reserved_19_19_WIDTH 1 +#define D18F5x40_Reserved_19_19_MASK 0x80000 +#define D18F5x40_Int_OFFSET 20 +#define D18F5x40_Int_WIDTH 1 +#define D18F5x40_Int_MASK 0x100000 +#define D18F5x40_Reserved_21_21_OFFSET 21 +#define D18F5x40_Reserved_21_21_WIDTH 1 +#define D18F5x40_Reserved_21_21_MASK 0x200000 +#define D18F5x40_En_OFFSET 22 +#define D18F5x40_En_WIDTH 1 +#define D18F5x40_En_MASK 0x400000 +#define D18F5x40_Reserved_31_23_OFFSET 23 +#define D18F5x40_Reserved_31_23_WIDTH 9 +#define D18F5x40_Reserved_31_23_MASK 0xff800000 + +/// D18F5x40 +typedef union { + struct { ///< + UINT32 EventSelect_7_0_:8 ; ///< + UINT32 UnitMask:8 ; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 Reserved_19_19:1 ; ///< + UINT32 Int:1 ; ///< + UINT32 Reserved_21_21:1 ; ///< + UINT32 En:1 ; ///< + UINT32 Reserved_31_23:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x40_STRUCT; + +// **** D18F5x44 Register Definition **** +// Address +#define D18F5x44_ADDRESS 0x44 + +// Type +#define D18F5x44_TYPE TYPE_D18F5 +// Field Data +#define D18F5x44_EventSelect_11_8__OFFSET 0 +#define D18F5x44_EventSelect_11_8__WIDTH 4 +#define D18F5x44_EventSelect_11_8__MASK 0xf +#define D18F5x44_Reserved_63_36_OFFSET 4 +#define D18F5x44_Reserved_63_36_WIDTH 28 +#define D18F5x44_Reserved_63_36_MASK 0xfffffff0 + +/// D18F5x44 +typedef union { + struct { ///< + UINT32 EventSelect_11_8_:4 ; ///< + UINT32 Reserved_63_36:28; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x44_STRUCT; + +// **** D18F5x48 Register Definition **** +// Address +#define D18F5x48_ADDRESS 0x48 + +// Type +#define D18F5x48_TYPE TYPE_D18F5 +// Field Data +#define D18F5x48_CTR_31_0__OFFSET 0 +#define D18F5x48_CTR_31_0__WIDTH 32 +#define D18F5x48_CTR_31_0__MASK 0xffffffff + +/// D18F5x48 +typedef union { + struct { ///< + UINT32 CTR_31_0_:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x48_STRUCT; + +// **** D18F5x4C Register Definition **** +// Address +#define D18F5x4C_ADDRESS 0x4c + +// Type +#define D18F5x4C_TYPE TYPE_D18F5 +// Field Data +#define D18F5x4C_CTR_47_32__OFFSET 0 +#define D18F5x4C_CTR_47_32__WIDTH 16 +#define D18F5x4C_CTR_47_32__MASK 0xffff +#define D18F5x4C_RAZ_63_48_OFFSET 16 +#define D18F5x4C_RAZ_63_48_WIDTH 16 +#define D18F5x4C_RAZ_63_48_MASK 0xffff0000 + +/// D18F5x4C +typedef union { + struct { ///< + UINT32 CTR_47_32_:16; ///< + UINT32 RAZ_63_48:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x4C_STRUCT; + +// **** D18F5x50 Register Definition **** +// Address +#define D18F5x50_ADDRESS 0x50 + +// Type +#define D18F5x50_TYPE TYPE_D18F5 +// Field Data +#define D18F5x50_EventSelect_7_0__OFFSET 0 +#define D18F5x50_EventSelect_7_0__WIDTH 8 +#define D18F5x50_EventSelect_7_0__MASK 0xff +#define D18F5x50_UnitMask_OFFSET 8 +#define D18F5x50_UnitMask_WIDTH 8 +#define D18F5x50_UnitMask_MASK 0xff00 +#define D18F5x50_Reserved_18_16_OFFSET 16 +#define D18F5x50_Reserved_18_16_WIDTH 3 +#define D18F5x50_Reserved_18_16_MASK 0x70000 +#define D18F5x50_Reserved_19_19_OFFSET 19 +#define D18F5x50_Reserved_19_19_WIDTH 1 +#define D18F5x50_Reserved_19_19_MASK 0x80000 +#define D18F5x50_Int_OFFSET 20 +#define D18F5x50_Int_WIDTH 1 +#define D18F5x50_Int_MASK 0x100000 +#define D18F5x50_Reserved_21_21_OFFSET 21 +#define D18F5x50_Reserved_21_21_WIDTH 1 +#define D18F5x50_Reserved_21_21_MASK 0x200000 +#define D18F5x50_En_OFFSET 22 +#define D18F5x50_En_WIDTH 1 +#define D18F5x50_En_MASK 0x400000 +#define D18F5x50_Reserved_31_23_OFFSET 23 +#define D18F5x50_Reserved_31_23_WIDTH 9 +#define D18F5x50_Reserved_31_23_MASK 0xff800000 + +/// D18F5x50 +typedef union { + struct { ///< + UINT32 EventSelect_7_0_:8 ; ///< + UINT32 UnitMask:8 ; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 Reserved_19_19:1 ; ///< + UINT32 Int:1 ; ///< + UINT32 Reserved_21_21:1 ; ///< + UINT32 En:1 ; ///< + UINT32 Reserved_31_23:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x50_STRUCT; + +// **** D18F5x54 Register Definition **** +// Address +#define D18F5x54_ADDRESS 0x54 + +// Type +#define D18F5x54_TYPE TYPE_D18F5 +// Field Data +#define D18F5x54_EventSelect_11_8__OFFSET 0 +#define D18F5x54_EventSelect_11_8__WIDTH 4 +#define D18F5x54_EventSelect_11_8__MASK 0xf +#define D18F5x54_Reserved_63_36_OFFSET 4 +#define D18F5x54_Reserved_63_36_WIDTH 28 +#define D18F5x54_Reserved_63_36_MASK 0xfffffff0 + +/// D18F5x54 +typedef union { + struct { ///< + UINT32 EventSelect_11_8_:4 ; ///< + UINT32 Reserved_63_36:28; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x54_STRUCT; + +// **** D18F5x58 Register Definition **** +// Address +#define D18F5x58_ADDRESS 0x58 + +// Type +#define D18F5x58_TYPE TYPE_D18F5 +// Field Data +#define D18F5x58_CTR_31_0__OFFSET 0 +#define D18F5x58_CTR_31_0__WIDTH 32 +#define D18F5x58_CTR_31_0__MASK 0xffffffff + +/// D18F5x58 +typedef union { + struct { ///< + UINT32 CTR_31_0_:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x58_STRUCT; + +// **** D18F5x5C Register Definition **** +// Address +#define D18F5x5C_ADDRESS 0x5c + +// Type +#define D18F5x5C_TYPE TYPE_D18F5 +// Field Data +#define D18F5x5C_CTR_47_32__OFFSET 0 +#define D18F5x5C_CTR_47_32__WIDTH 16 +#define D18F5x5C_CTR_47_32__MASK 0xffff +#define D18F5x5C_RAZ_63_48_OFFSET 16 +#define D18F5x5C_RAZ_63_48_WIDTH 16 +#define D18F5x5C_RAZ_63_48_MASK 0xffff0000 + +/// D18F5x5C +typedef union { + struct { ///< + UINT32 CTR_47_32_:16; ///< + UINT32 RAZ_63_48:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x5C_STRUCT; + +// **** D18F5x60 Register Definition **** +// Address +#define D18F5x60_ADDRESS 0x60 + +// Type +#define D18F5x60_TYPE TYPE_D18F5 +// Field Data +#define D18F5x60_EventSelect_7_0__OFFSET 0 +#define D18F5x60_EventSelect_7_0__WIDTH 8 +#define D18F5x60_EventSelect_7_0__MASK 0xff +#define D18F5x60_UnitMask_OFFSET 8 +#define D18F5x60_UnitMask_WIDTH 8 +#define D18F5x60_UnitMask_MASK 0xff00 +#define D18F5x60_Reserved_18_16_OFFSET 16 +#define D18F5x60_Reserved_18_16_WIDTH 3 +#define D18F5x60_Reserved_18_16_MASK 0x70000 +#define D18F5x60_Reserved_19_19_OFFSET 19 +#define D18F5x60_Reserved_19_19_WIDTH 1 +#define D18F5x60_Reserved_19_19_MASK 0x80000 +#define D18F5x60_Int_OFFSET 20 +#define D18F5x60_Int_WIDTH 1 +#define D18F5x60_Int_MASK 0x100000 +#define D18F5x60_Reserved_21_21_OFFSET 21 +#define D18F5x60_Reserved_21_21_WIDTH 1 +#define D18F5x60_Reserved_21_21_MASK 0x200000 +#define D18F5x60_En_OFFSET 22 +#define D18F5x60_En_WIDTH 1 +#define D18F5x60_En_MASK 0x400000 +#define D18F5x60_Reserved_31_23_OFFSET 23 +#define D18F5x60_Reserved_31_23_WIDTH 9 +#define D18F5x60_Reserved_31_23_MASK 0xff800000 + +/// D18F5x60 +typedef union { + struct { ///< + UINT32 EventSelect_7_0_:8 ; ///< + UINT32 UnitMask:8 ; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 Reserved_19_19:1 ; ///< + UINT32 Int:1 ; ///< + UINT32 Reserved_21_21:1 ; ///< + UINT32 En:1 ; ///< + UINT32 Reserved_31_23:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x60_STRUCT; + +// **** D18F5x64 Register Definition **** +// Address +#define D18F5x64_ADDRESS 0x64 + +// Type +#define D18F5x64_TYPE TYPE_D18F5 +// Field Data +#define D18F5x64_EventSelect_11_8__OFFSET 0 +#define D18F5x64_EventSelect_11_8__WIDTH 4 +#define D18F5x64_EventSelect_11_8__MASK 0xf +#define D18F5x64_Reserved_63_36_OFFSET 4 +#define D18F5x64_Reserved_63_36_WIDTH 28 +#define D18F5x64_Reserved_63_36_MASK 0xfffffff0 + +/// D18F5x64 +typedef union { + struct { ///< + UINT32 EventSelect_11_8_:4 ; ///< + UINT32 Reserved_63_36:28; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x64_STRUCT; + +// **** D18F5x68 Register Definition **** +// Address +#define D18F5x68_ADDRESS 0x68 + +// Type +#define D18F5x68_TYPE TYPE_D18F5 +// Field Data +#define D18F5x68_CTR_31_0__OFFSET 0 +#define D18F5x68_CTR_31_0__WIDTH 32 +#define D18F5x68_CTR_31_0__MASK 0xffffffff + +/// D18F5x68 +typedef union { + struct { ///< + UINT32 CTR_31_0_:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x68_STRUCT; + +// **** D18F5x6C Register Definition **** +// Address +#define D18F5x6C_ADDRESS 0x6c + +// Type +#define D18F5x6C_TYPE TYPE_D18F5 +// Field Data +#define D18F5x6C_CTR_47_32__OFFSET 0 +#define D18F5x6C_CTR_47_32__WIDTH 16 +#define D18F5x6C_CTR_47_32__MASK 0xffff +#define D18F5x6C_RAZ_63_48_OFFSET 16 +#define D18F5x6C_RAZ_63_48_WIDTH 16 +#define D18F5x6C_RAZ_63_48_MASK 0xffff0000 + +/// D18F5x6C +typedef union { + struct { ///< + UINT32 CTR_47_32_:16; ///< + UINT32 RAZ_63_48:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x6C_STRUCT; + +// **** D18F5x70 Register Definition **** +// Address +#define D18F5x70_ADDRESS 0x70 + +// Type +#define D18F5x70_TYPE TYPE_D18F5 +// Field Data +#define D18F5x70_EventSelect_7_0__OFFSET 0 +#define D18F5x70_EventSelect_7_0__WIDTH 8 +#define D18F5x70_EventSelect_7_0__MASK 0xff +#define D18F5x70_UnitMask_OFFSET 8 +#define D18F5x70_UnitMask_WIDTH 8 +#define D18F5x70_UnitMask_MASK 0xff00 +#define D18F5x70_Reserved_18_16_OFFSET 16 +#define D18F5x70_Reserved_18_16_WIDTH 3 +#define D18F5x70_Reserved_18_16_MASK 0x70000 +#define D18F5x70_Reserved_19_19_OFFSET 19 +#define D18F5x70_Reserved_19_19_WIDTH 1 +#define D18F5x70_Reserved_19_19_MASK 0x80000 +#define D18F5x70_Int_OFFSET 20 +#define D18F5x70_Int_WIDTH 1 +#define D18F5x70_Int_MASK 0x100000 +#define D18F5x70_Reserved_21_21_OFFSET 21 +#define D18F5x70_Reserved_21_21_WIDTH 1 +#define D18F5x70_Reserved_21_21_MASK 0x200000 +#define D18F5x70_En_OFFSET 22 +#define D18F5x70_En_WIDTH 1 +#define D18F5x70_En_MASK 0x400000 +#define D18F5x70_Reserved_31_23_OFFSET 23 +#define D18F5x70_Reserved_31_23_WIDTH 9 +#define D18F5x70_Reserved_31_23_MASK 0xff800000 + +/// D18F5x70 +typedef union { + struct { ///< + UINT32 EventSelect_7_0_:8 ; ///< + UINT32 UnitMask:8 ; ///< + UINT32 Reserved_18_16:3 ; ///< + UINT32 Reserved_19_19:1 ; ///< + UINT32 Int:1 ; ///< + UINT32 Reserved_21_21:1 ; ///< + UINT32 En:1 ; ///< + UINT32 Reserved_31_23:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x70_STRUCT; + +// **** D18F5x74 Register Definition **** +// Address +#define D18F5x74_ADDRESS 0x74 + +// Type +#define D18F5x74_TYPE TYPE_D18F5 +// Field Data +#define D18F5x74_EventSelect_11_8__OFFSET 0 +#define D18F5x74_EventSelect_11_8__WIDTH 4 +#define D18F5x74_EventSelect_11_8__MASK 0xf +#define D18F5x74_Reserved_63_36_OFFSET 4 +#define D18F5x74_Reserved_63_36_WIDTH 28 +#define D18F5x74_Reserved_63_36_MASK 0xfffffff0 + +/// D18F5x74 +typedef union { + struct { ///< + UINT32 EventSelect_11_8_:4 ; ///< + UINT32 Reserved_63_36:28; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x74_STRUCT; + +// **** D18F5x78 Register Definition **** +// Address +#define D18F5x78_ADDRESS 0x78 + +// Type +#define D18F5x78_TYPE TYPE_D18F5 +// Field Data +#define D18F5x78_CTR_31_0__OFFSET 0 +#define D18F5x78_CTR_31_0__WIDTH 32 +#define D18F5x78_CTR_31_0__MASK 0xffffffff + +/// D18F5x78 +typedef union { + struct { ///< + UINT32 CTR_31_0_:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x78_STRUCT; + +// **** D18F5x7C Register Definition **** +// Address +#define D18F5x7C_ADDRESS 0x7c + +// Type +#define D18F5x7C_TYPE TYPE_D18F5 +// Field Data +#define D18F5x7C_CTR_47_32__OFFSET 0 +#define D18F5x7C_CTR_47_32__WIDTH 16 +#define D18F5x7C_CTR_47_32__MASK 0xffff +#define D18F5x7C_RAZ_63_48_OFFSET 16 +#define D18F5x7C_RAZ_63_48_WIDTH 16 +#define D18F5x7C_RAZ_63_48_MASK 0xffff0000 + +/// D18F5x7C +typedef union { + struct { ///< + UINT32 CTR_47_32_:16; ///< + UINT32 RAZ_63_48:16; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x7C_STRUCT; + +// **** D18F5x80 Register Definition **** +// Address +#define D18F5x80_ADDRESS 0x80 + +// Type +#define D18F5x80_TYPE TYPE_D18F5 +// Field Data +#define D18F5x80_Enabled_OFFSET 0 +#define D18F5x80_Enabled_WIDTH 4 +#define D18F5x80_Enabled_MASK 0xf +#define D18F5x80_Reserved_15_4_OFFSET 4 +#define D18F5x80_Reserved_15_4_WIDTH 12 +#define D18F5x80_Reserved_15_4_MASK 0xfff0 +#define D18F5x80_DualCore_OFFSET 16 +#define D18F5x80_DualCore_WIDTH 4 +#define D18F5x80_DualCore_MASK 0xf0000 +#define D18F5x80_Reserved_31_20_OFFSET 20 +#define D18F5x80_Reserved_31_20_WIDTH 12 +#define D18F5x80_Reserved_31_20_MASK 0xfff00000 + +/// D18F5x80 +typedef union { + struct { ///< + UINT32 Enabled:4 ; ///< + UINT32 Reserved_15_4:12; ///< + UINT32 DualCore:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x80_STRUCT; + +// **** D18F5x84 Register Definition **** +// Address +#define D18F5x84_ADDRESS 0x84 + +// Type +#define D18F5x84_TYPE TYPE_D18F5 +// Field Data +#define D18F5x84_CmpCap_OFFSET 0 +#define D18F5x84_CmpCap_WIDTH 8 +#define D18F5x84_CmpCap_MASK 0xff +#define D18F5x84_Reserved_11_8_OFFSET 8 +#define D18F5x84_Reserved_11_8_WIDTH 4 +#define D18F5x84_Reserved_11_8_MASK 0xf00 +#define D18F5x84_DctEn_OFFSET 12 +#define D18F5x84_DctEn_WIDTH 2 +#define D18F5x84_DctEn_MASK 0x3000 +#define D18F5x84_Reserved_15_14_OFFSET 14 +#define D18F5x84_Reserved_15_14_WIDTH 2 +#define D18F5x84_Reserved_15_14_MASK 0xc000 +#define D18F5x84_DdrMaxRate_OFFSET 16 +#define D18F5x84_DdrMaxRate_WIDTH 5 +#define D18F5x84_DdrMaxRate_MASK 0x1f0000 +#define D18F5x84_Reserved_23_21_OFFSET 21 +#define D18F5x84_Reserved_23_21_WIDTH 3 +#define D18F5x84_Reserved_23_21_MASK 0xe00000 +#define D18F5x84_DdrMaxRateEnf_OFFSET 24 +#define D18F5x84_DdrMaxRateEnf_WIDTH 5 +#define D18F5x84_DdrMaxRateEnf_MASK 0x1f000000 +#define D18F5x84_Reserved_31_29_OFFSET 29 +#define D18F5x84_Reserved_31_29_WIDTH 3 +#define D18F5x84_Reserved_31_29_MASK 0xe0000000 + +/// D18F5x84 +typedef union { + struct { ///< + UINT32 CmpCap:8 ; ///< + UINT32 Reserved_11_8:4 ; ///< + UINT32 DctEn:2 ; ///< + UINT32 Reserved_15_14:2 ; ///< + UINT32 DdrMaxRate:5 ; ///< + UINT32 Reserved_23_21:3 ; ///< + UINT32 DdrMaxRateEnf:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x84_STRUCT; + +// **** D18F5x88 Register Definition **** +// Address +#define D18F5x88_ADDRESS 0x88 + +// Type +#define D18F5x88_TYPE TYPE_D18F5 +// Field Data +#define D18F5x88_Reserved_1_0_OFFSET 0 +#define D18F5x88_Reserved_1_0_WIDTH 2 +#define D18F5x88_Reserved_1_0_MASK 0x3 +#define D18F5x88_IntStpClkHaltExitEn_OFFSET 2 +#define D18F5x88_IntStpClkHaltExitEn_WIDTH 1 +#define D18F5x88_IntStpClkHaltExitEn_MASK 0x4 + +/// D18F5x88 +typedef union { + struct { ///< + UINT32 Reserved_1_0:2 ; ///< + UINT32 IntStpClkHaltExitEn:1 ; ///< + UINT32 :29; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x88_STRUCT; + +// **** D18F5xE0 Register Definition **** +// Address +#define D18F5xE0_ADDRESS 0xe0 + +// Type +#define D18F5xE0_TYPE TYPE_D18F5 +// Field Data +#define D18F5xE0_RunAvgRange_OFFSET 0 +#define D18F5xE0_RunAvgRange_WIDTH 4 +#define D18F5xE0_RunAvgRange_MASK 0xf +#define D18F5xE0_Reserved_31_4_OFFSET 4 +#define D18F5xE0_Reserved_31_4_WIDTH 28 +#define D18F5xE0_Reserved_31_4_MASK 0xfffffff0 + +/// D18F5xE0 +typedef union { + struct { ///< + UINT32 RunAvgRange:4 ; ///< + UINT32 Reserved_31_4:28; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5xE0_STRUCT; + + +// **** D18F5x128 Register Definition **** +// Address +#define D18F5x128_ADDRESS 0x128 + +// Type +#define D18F5x128_TYPE TYPE_D18F5 +// Field Data +#define D18F5x128_PC6Vid_6_0__OFFSET 0 +#define D18F5x128_PC6Vid_6_0__WIDTH 7 +#define D18F5x128_PC6Vid_6_0__MASK 0x7f +#define D18F5x128_PllRegTime_OFFSET 7 +#define D18F5x128_PllRegTime_WIDTH 2 +#define D18F5x128_PllRegTime_MASK 0x180 +#define D18F5x128_FastSlamTimeDown_OFFSET 9 +#define D18F5x128_FastSlamTimeDown_WIDTH 1 +#define D18F5x128_FastSlamTimeDown_MASK 0x200 +#define D18F5x128_PllVddOutUpTime_OFFSET 10 +#define D18F5x128_PllVddOutUpTime_WIDTH 2 +#define D18F5x128_PllVddOutUpTime_MASK 0xc00 +#define D18F5x128_PwrGateTmr_OFFSET 12 +#define D18F5x128_PwrGateTmr_WIDTH 2 +#define D18F5x128_PwrGateTmr_MASK 0x3000 +#define D18F5x128_PC6PwrDwnRegEn_OFFSET 14 +#define D18F5x128_PC6PwrDwnRegEn_WIDTH 1 +#define D18F5x128_PC6PwrDwnRegEn_MASK 0x4000 +#define D18F5x128_CC6PwrDwnRegEn_OFFSET 15 +#define D18F5x128_CC6PwrDwnRegEn_WIDTH 1 +#define D18F5x128_CC6PwrDwnRegEn_MASK 0x8000 +#define D18F5x128_Reserved_20_16_OFFSET 16 +#define D18F5x128_Reserved_20_16_WIDTH 5 +#define D18F5x128_Reserved_20_16_MASK 0x1f0000 +#define D18F5x128_PC6Vid_7__OFFSET 21 +#define D18F5x128_PC6Vid_7__WIDTH 1 +#define D18F5x128_PC6Vid_7__MASK 0x200000 +#define D18F5x128_NbPllPwrDwnRegEn_OFFSET 22 +#define D18F5x128_NbPllPwrDwnRegEn_WIDTH 1 +#define D18F5x128_NbPllPwrDwnRegEn_MASK 0x400000 +#define D18F5x128_Reserved_31_23_OFFSET 23 +#define D18F5x128_Reserved_31_23_WIDTH 9 +#define D18F5x128_Reserved_31_23_MASK 0xff800000 + +/// D18F5x128 +typedef union { + struct { ///< + UINT32 PC6Vid_6_0_:7 ; ///< + UINT32 PllRegTime:2 ; ///< + UINT32 FastSlamTimeDown:1 ; ///< + UINT32 PllVddOutUpTime:2 ; ///< + UINT32 PwrGateTmr:2 ; ///< + UINT32 PC6PwrDwnRegEn:1 ; ///< + UINT32 CC6PwrDwnRegEn:1 ; ///< + UINT32 Reserved_20_16:5 ; ///< + UINT32 PC6Vid_7_:1 ; ///< + UINT32 NbPllPwrDwnRegEn:1 ; ///< + UINT32 Reserved_31_23:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x128_STRUCT; + +// **** D18F5x12C Register Definition **** +// Address +#define D18F5x12C_ADDRESS 0x12c + +// Type +#define D18F5x12C_TYPE TYPE_D18F5 +// Field Data +#define D18F5x12C_CoreOffsetTrim_OFFSET 0 +#define D18F5x12C_CoreOffsetTrim_WIDTH 2 +#define D18F5x12C_CoreOffsetTrim_MASK 0x3 +#define D18F5x12C_CoreLoadLineTrim_OFFSET 2 +#define D18F5x12C_CoreLoadLineTrim_WIDTH 3 +#define D18F5x12C_CoreLoadLineTrim_MASK 0x1c +#define D18F5x12C_CorePsi1En_OFFSET 5 +#define D18F5x12C_CorePsi1En_WIDTH 1 +#define D18F5x12C_CorePsi1En_MASK 0x20 +#define D18F5x12C_Reserved_29_7_OFFSET 7 +#define D18F5x12C_Reserved_29_7_WIDTH 23 +#define D18F5x12C_Reserved_29_7_MASK 0x3fffff80 +#define D18F5x12C_WaitVidCompDis_OFFSET 30 +#define D18F5x12C_WaitVidCompDis_WIDTH 1 +#define D18F5x12C_WaitVidCompDis_MASK 0x40000000 +#define D18F5x12C_Svi2CmdBusy_OFFSET 31 +#define D18F5x12C_Svi2CmdBusy_WIDTH 1 +#define D18F5x12C_Svi2CmdBusy_MASK 0x80000000 + +/// D18F5x12C +typedef union { + struct { ///< + UINT32 CoreOffsetTrim:2 ; ///< + UINT32 CoreLoadLineTrim:3 ; ///< + UINT32 CorePsi1En:1 ; ///< + UINT32 :1 ; ///< + UINT32 Reserved_29_7:23; ///< + UINT32 WaitVidCompDis:1 ; ///< + UINT32 Svi2CmdBusy:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x12C_STRUCT; + + +// **** D18F5x160 Register Definition **** +// Address +#define D18F5x160_ADDRESS 0x160 + +// Type +#define D18F5x160_TYPE TYPE_D18F5 +// Field Data +#define D18F5x160_NbPstateEn_OFFSET 0 +#define D18F5x160_NbPstateEn_WIDTH 1 +#define D18F5x160_NbPstateEn_MASK 0x1 +#define D18F5x160_NbFid_OFFSET 1 +#define D18F5x160_NbFid_WIDTH 6 +#define D18F5x160_NbFid_MASK 0x7e +#define D18F5x160_NbDid_OFFSET 7 +#define D18F5x160_NbDid_WIDTH 1 +#define D18F5x160_NbDid_MASK 0x80 +#define D18F5x160_Reserved_9_8_OFFSET 8 +#define D18F5x160_Reserved_9_8_WIDTH 2 +#define D18F5x160_Reserved_9_8_MASK 0x300 +#define D18F5x160_NbVid_6_0__OFFSET 10 +#define D18F5x160_NbVid_6_0__WIDTH 7 +#define D18F5x160_NbVid_6_0__MASK 0x1fc00 +#define D18F5x160_Reserved_17_17_OFFSET 17 +#define D18F5x160_Reserved_17_17_WIDTH 1 +#define D18F5x160_Reserved_17_17_MASK 0x20000 +#define D18F5x160_MemPstate_OFFSET 18 +#define D18F5x160_MemPstate_WIDTH 1 +#define D18F5x160_MemPstate_MASK 0x40000 +#define D18F5x160_Reserved_20_19_OFFSET 19 +#define D18F5x160_Reserved_20_19_WIDTH 2 +#define D18F5x160_Reserved_20_19_MASK 0x180000 +#define D18F5x160_NbVid_7__OFFSET 21 +#define D18F5x160_NbVid_7__WIDTH 1 +#define D18F5x160_NbVid_7__MASK 0x200000 +#define D18F5x160_NbIddDiv_OFFSET 22 +#define D18F5x160_NbIddDiv_WIDTH 2 +#define D18F5x160_NbIddDiv_MASK 0xc00000 +#define D18F5x160_NbIddValue_OFFSET 24 +#define D18F5x160_NbIddValue_WIDTH 8 +#define D18F5x160_NbIddValue_MASK 0xff000000 + +/// D18F5x160 +typedef union { + struct { ///< + UINT32 NbPstateEn:1 ; ///< + UINT32 NbFid:6 ; ///< + UINT32 NbDid:1 ; ///< + UINT32 Reserved_9_8:2 ; ///< + UINT32 NbVid_6_0_:7 ; ///< + UINT32 Reserved_17_17:1 ; ///< + UINT32 MemPstate:1 ; ///< + UINT32 Reserved_20_19:2 ; ///< + UINT32 NbVid_7_:1 ; ///< + UINT32 NbIddDiv:2 ; ///< + UINT32 NbIddValue:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x160_STRUCT; + +// **** D18F5x164 Register Definition **** +// Address +#define D18F5x164_ADDRESS 0x164 + +// Type +#define D18F5x164_TYPE TYPE_D18F5 +// Field Data +#define D18F5x164_NbPstateEn_OFFSET 0 +#define D18F5x164_NbPstateEn_WIDTH 1 +#define D18F5x164_NbPstateEn_MASK 0x1 +#define D18F5x164_NbFid_OFFSET 1 +#define D18F5x164_NbFid_WIDTH 6 +#define D18F5x164_NbFid_MASK 0x7e +#define D18F5x164_NbDid_OFFSET 7 +#define D18F5x164_NbDid_WIDTH 1 +#define D18F5x164_NbDid_MASK 0x80 +#define D18F5x164_Reserved_9_8_OFFSET 8 +#define D18F5x164_Reserved_9_8_WIDTH 2 +#define D18F5x164_Reserved_9_8_MASK 0x300 +#define D18F5x164_NbVid_6_0__OFFSET 10 +#define D18F5x164_NbVid_6_0__WIDTH 7 +#define D18F5x164_NbVid_6_0__MASK 0x1fc00 +#define D18F5x164_Reserved_17_17_OFFSET 17 +#define D18F5x164_Reserved_17_17_WIDTH 1 +#define D18F5x164_Reserved_17_17_MASK 0x20000 +#define D18F5x164_MemPstate_OFFSET 18 +#define D18F5x164_MemPstate_WIDTH 1 +#define D18F5x164_MemPstate_MASK 0x40000 +#define D18F5x164_Reserved_20_19_OFFSET 19 +#define D18F5x164_Reserved_20_19_WIDTH 2 +#define D18F5x164_Reserved_20_19_MASK 0x180000 +#define D18F5x164_NbVid_7__OFFSET 21 +#define D18F5x164_NbVid_7__WIDTH 1 +#define D18F5x164_NbVid_7__MASK 0x200000 +#define D18F5x164_NbIddDiv_OFFSET 22 +#define D18F5x164_NbIddDiv_WIDTH 2 +#define D18F5x164_NbIddDiv_MASK 0xc00000 +#define D18F5x164_NbIddValue_OFFSET 24 +#define D18F5x164_NbIddValue_WIDTH 8 +#define D18F5x164_NbIddValue_MASK 0xff000000 + +/// D18F5x164 +typedef union { + struct { ///< + UINT32 NbPstateEn:1 ; ///< + UINT32 NbFid:6 ; ///< + UINT32 NbDid:1 ; ///< + UINT32 Reserved_9_8:2 ; ///< + UINT32 NbVid_6_0_:7 ; ///< + UINT32 Reserved_17_17:1 ; ///< + UINT32 MemPstate:1 ; ///< + UINT32 Reserved_20_19:2 ; ///< + UINT32 NbVid_7_:1 ; ///< + UINT32 NbIddDiv:2 ; ///< + UINT32 NbIddValue:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x164_STRUCT; + +// **** D18F5x168 Register Definition **** +// Address +#define D18F5x168_ADDRESS 0x168 + +// Type +#define D18F5x168_TYPE TYPE_D18F5 +// Field Data +#define D18F5x168_NbPstateEn_OFFSET 0 +#define D18F5x168_NbPstateEn_WIDTH 1 +#define D18F5x168_NbPstateEn_MASK 0x1 +#define D18F5x168_NbFid_OFFSET 1 +#define D18F5x168_NbFid_WIDTH 6 +#define D18F5x168_NbFid_MASK 0x7e +#define D18F5x168_NbDid_OFFSET 7 +#define D18F5x168_NbDid_WIDTH 1 +#define D18F5x168_NbDid_MASK 0x80 +#define D18F5x168_Reserved_9_8_OFFSET 8 +#define D18F5x168_Reserved_9_8_WIDTH 2 +#define D18F5x168_Reserved_9_8_MASK 0x300 +#define D18F5x168_NbVid_6_0__OFFSET 10 +#define D18F5x168_NbVid_6_0__WIDTH 7 +#define D18F5x168_NbVid_6_0__MASK 0x1fc00 +#define D18F5x168_Reserved_17_17_OFFSET 17 +#define D18F5x168_Reserved_17_17_WIDTH 1 +#define D18F5x168_Reserved_17_17_MASK 0x20000 +#define D18F5x168_MemPstate_OFFSET 18 +#define D18F5x168_MemPstate_WIDTH 1 +#define D18F5x168_MemPstate_MASK 0x40000 +#define D18F5x168_Reserved_20_19_OFFSET 19 +#define D18F5x168_Reserved_20_19_WIDTH 2 +#define D18F5x168_Reserved_20_19_MASK 0x180000 +#define D18F5x168_NbVid_7__OFFSET 21 +#define D18F5x168_NbVid_7__WIDTH 1 +#define D18F5x168_NbVid_7__MASK 0x200000 +#define D18F5x168_NbIddDiv_OFFSET 22 +#define D18F5x168_NbIddDiv_WIDTH 2 +#define D18F5x168_NbIddDiv_MASK 0xc00000 +#define D18F5x168_NbIddValue_OFFSET 24 +#define D18F5x168_NbIddValue_WIDTH 8 +#define D18F5x168_NbIddValue_MASK 0xff000000 + +/// D18F5x168 +typedef union { + struct { ///< + UINT32 NbPstateEn:1 ; ///< + UINT32 NbFid:6 ; ///< + UINT32 NbDid:1 ; ///< + UINT32 Reserved_9_8:2 ; ///< + UINT32 NbVid_6_0_:7 ; ///< + UINT32 Reserved_17_17:1 ; ///< + UINT32 MemPstate:1 ; ///< + UINT32 Reserved_20_19:2 ; ///< + UINT32 NbVid_7_:1 ; ///< + UINT32 NbIddDiv:2 ; ///< + UINT32 NbIddValue:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x168_STRUCT; + +// **** D18F5x16C Register Definition **** +// Address +#define D18F5x16C_ADDRESS 0x16c + +// Type +#define D18F5x16C_TYPE TYPE_D18F5 +// Field Data +#define D18F5x16C_NbPstateEn_OFFSET 0 +#define D18F5x16C_NbPstateEn_WIDTH 1 +#define D18F5x16C_NbPstateEn_MASK 0x1 +#define D18F5x16C_NbFid_OFFSET 1 +#define D18F5x16C_NbFid_WIDTH 6 +#define D18F5x16C_NbFid_MASK 0x7e +#define D18F5x16C_NbDid_OFFSET 7 +#define D18F5x16C_NbDid_WIDTH 1 +#define D18F5x16C_NbDid_MASK 0x80 +#define D18F5x16C_Reserved_9_8_OFFSET 8 +#define D18F5x16C_Reserved_9_8_WIDTH 2 +#define D18F5x16C_Reserved_9_8_MASK 0x300 +#define D18F5x16C_NbVid_6_0__OFFSET 10 +#define D18F5x16C_NbVid_6_0__WIDTH 7 +#define D18F5x16C_NbVid_6_0__MASK 0x1fc00 +#define D18F5x16C_Reserved_17_17_OFFSET 17 +#define D18F5x16C_Reserved_17_17_WIDTH 1 +#define D18F5x16C_Reserved_17_17_MASK 0x20000 +#define D18F5x16C_MemPstate_OFFSET 18 +#define D18F5x16C_MemPstate_WIDTH 1 +#define D18F5x16C_MemPstate_MASK 0x40000 +#define D18F5x16C_Reserved_20_19_OFFSET 19 +#define D18F5x16C_Reserved_20_19_WIDTH 2 +#define D18F5x16C_Reserved_20_19_MASK 0x180000 +#define D18F5x16C_NbVid_7__OFFSET 21 +#define D18F5x16C_NbVid_7__WIDTH 1 +#define D18F5x16C_NbVid_7__MASK 0x200000 +#define D18F5x16C_NbIddDiv_OFFSET 22 +#define D18F5x16C_NbIddDiv_WIDTH 2 +#define D18F5x16C_NbIddDiv_MASK 0xc00000 +#define D18F5x16C_NbIddValue_OFFSET 24 +#define D18F5x16C_NbIddValue_WIDTH 8 +#define D18F5x16C_NbIddValue_MASK 0xff000000 + +/// D18F5x16C +typedef union { + struct { ///< + UINT32 NbPstateEn:1 ; ///< + UINT32 NbFid:6 ; ///< + UINT32 NbDid:1 ; ///< + UINT32 Reserved_9_8:2 ; ///< + UINT32 NbVid_6_0_:7 ; ///< + UINT32 Reserved_17_17:1 ; ///< + UINT32 MemPstate:1 ; ///< + UINT32 Reserved_20_19:2 ; ///< + UINT32 NbVid_7_:1 ; ///< + UINT32 NbIddDiv:2 ; ///< + UINT32 NbIddValue:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x16C_STRUCT; + +// **** D18F5x170 Register Definition **** +// Address +#define D18F5x170_ADDRESS 0x170 + +// Type +#define D18F5x170_TYPE TYPE_D18F5 +// Field Data +#define D18F5x170_NbPstateMaxVal_OFFSET 0 +#define D18F5x170_NbPstateMaxVal_WIDTH 2 +#define D18F5x170_NbPstateMaxVal_MASK 0x3 +#define D18F5x170_Reserved_2_2_OFFSET 2 +#define D18F5x170_Reserved_2_2_WIDTH 1 +#define D18F5x170_Reserved_2_2_MASK 0x4 +#define D18F5x170_NbPstateLo_OFFSET 3 +#define D18F5x170_NbPstateLo_WIDTH 2 +#define D18F5x170_NbPstateLo_MASK 0x18 +#define D18F5x170_Reserved_5_5_OFFSET 5 +#define D18F5x170_Reserved_5_5_WIDTH 1 +#define D18F5x170_Reserved_5_5_MASK 0x20 +#define D18F5x170_NbPstateHi_OFFSET 6 +#define D18F5x170_NbPstateHi_WIDTH 2 +#define D18F5x170_NbPstateHi_MASK 0xc0 +#define D18F5x170_Reserved_8_8_OFFSET 8 +#define D18F5x170_Reserved_8_8_WIDTH 1 +#define D18F5x170_Reserved_8_8_MASK 0x100 +#define D18F5x170_NbPstateThreshold_OFFSET 9 +#define D18F5x170_NbPstateThreshold_WIDTH 3 +#define D18F5x170_NbPstateThreshold_MASK 0xe00 +#define D18F5x170_Reserved_12_12_OFFSET 12 +#define D18F5x170_Reserved_12_12_WIDTH 1 +#define D18F5x170_Reserved_12_12_MASK 0x1000 +#define D18F5x170_NbPstateDisOnP0_OFFSET 13 +#define D18F5x170_NbPstateDisOnP0_WIDTH 1 +#define D18F5x170_NbPstateDisOnP0_MASK 0x2000 +#define D18F5x170_SwNbPstateLoDis_OFFSET 14 +#define D18F5x170_SwNbPstateLoDis_WIDTH 1 +#define D18F5x170_SwNbPstateLoDis_MASK 0x4000 +#define D18F5x170_Reserved_22_15_OFFSET 15 +#define D18F5x170_Reserved_22_15_WIDTH 8 +#define D18F5x170_Reserved_22_15_MASK 0x7f8000 +#define D18F5x170_NbPstateGnbSlowDis_OFFSET 23 +#define D18F5x170_NbPstateGnbSlowDis_WIDTH 1 +#define D18F5x170_NbPstateGnbSlowDis_MASK 0x800000 +#define D18F5x170_NbPstateLoRes_OFFSET 24 +#define D18F5x170_NbPstateLoRes_WIDTH 3 +#define D18F5x170_NbPstateLoRes_MASK 0x7000000 +#define D18F5x170_NbPstateHiRes_OFFSET 27 +#define D18F5x170_NbPstateHiRes_WIDTH 3 +#define D18F5x170_NbPstateHiRes_MASK 0x38000000 +#define D18F5x170_Reserved_30_30_OFFSET 30 +#define D18F5x170_Reserved_30_30_WIDTH 1 +#define D18F5x170_Reserved_30_30_MASK 0x40000000 +#define D18F5x170_MemPstateDis_OFFSET 31 +#define D18F5x170_MemPstateDis_WIDTH 1 +#define D18F5x170_MemPstateDis_MASK 0x80000000 + +/// D18F5x170 +typedef union { + struct { ///< + UINT32 NbPstateMaxVal:2 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 NbPstateLo:2 ; ///< + UINT32 Reserved_5_5:1 ; ///< + UINT32 NbPstateHi:2 ; ///< + UINT32 Reserved_8_8:1 ; ///< + UINT32 NbPstateThreshold:3 ; ///< + UINT32 Reserved_12_12:1 ; ///< + UINT32 NbPstateDisOnP0:1 ; ///< + UINT32 SwNbPstateLoDis:1 ; ///< + UINT32 Reserved_22_15:8 ; ///< + UINT32 NbPstateGnbSlowDis:1 ; ///< + UINT32 NbPstateLoRes:3 ; ///< + UINT32 NbPstateHiRes:3 ; ///< + UINT32 Reserved_30_30:1 ; ///< + UINT32 MemPstateDis:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x170_STRUCT; + +// **** D18F5x174 Register Definition **** +// Address +#define D18F5x174_ADDRESS 0x174 + +// Type +#define D18F5x174_TYPE TYPE_D18F5 +// Field Data +#define D18F5x174_NbPstateDis_OFFSET 0 +#define D18F5x174_NbPstateDis_WIDTH 1 +#define D18F5x174_NbPstateDis_MASK 0x1 +#define D18F5x174_StartupNbPstate_OFFSET 1 +#define D18F5x174_StartupNbPstate_WIDTH 2 +#define D18F5x174_StartupNbPstate_MASK 0x6 +#define D18F5x174_CurNbFid_OFFSET 3 +#define D18F5x174_CurNbFid_WIDTH 6 +#define D18F5x174_CurNbFid_MASK 0x1f8 +#define D18F5x174_CurNbDid_OFFSET 9 +#define D18F5x174_CurNbDid_WIDTH 1 +#define D18F5x174_CurNbDid_MASK 0x200 +#define D18F5x174_Reserved_11_10_OFFSET 10 +#define D18F5x174_Reserved_11_10_WIDTH 2 +#define D18F5x174_Reserved_11_10_MASK 0xc00 +#define D18F5x174_CurNbVid_6_0__OFFSET 12 +#define D18F5x174_CurNbVid_6_0__WIDTH 7 +#define D18F5x174_CurNbVid_6_0__MASK 0x7f000 +#define D18F5x174_CurNbPstate_OFFSET 19 +#define D18F5x174_CurNbPstate_WIDTH 2 +#define D18F5x174_CurNbPstate_MASK 0x180000 +#define D18F5x174_Reserved_22_21_OFFSET 21 +#define D18F5x174_Reserved_22_21_WIDTH 2 +#define D18F5x174_Reserved_22_21_MASK 0x600000 +#define D18F5x174_CurNbVid_7__OFFSET 23 +#define D18F5x174_CurNbVid_7__WIDTH 1 +#define D18F5x174_CurNbVid_7__MASK 0x800000 +#define D18F5x174_CurMemPstate_OFFSET 24 +#define D18F5x174_CurMemPstate_WIDTH 1 +#define D18F5x174_CurMemPstate_MASK 0x1000000 +#define D18F5x174_Reserved_31_25_OFFSET 25 +#define D18F5x174_Reserved_31_25_WIDTH 7 +#define D18F5x174_Reserved_31_25_MASK 0xfe000000 + +/// D18F5x174 +typedef union { + struct { ///< + UINT32 NbPstateDis:1 ; ///< + UINT32 StartupNbPstate:2 ; ///< + UINT32 CurNbFid:6 ; ///< + UINT32 CurNbDid:1 ; ///< + UINT32 Reserved_11_10:2 ; ///< + UINT32 CurNbVid_6_0_:7 ; ///< + UINT32 CurNbPstate:2 ; ///< + UINT32 Reserved_22_21:2 ; ///< + UINT32 CurNbVid_7_:1 ; ///< + UINT32 CurMemPstate:1 ; ///< + UINT32 Reserved_31_25:7 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x174_STRUCT; + +// **** D18F5x178 Register Definition **** +// Address +#define D18F5x178_ADDRESS 0x178 + +// Type +#define D18F5x178_TYPE TYPE_D18F5 +// Field Data +#define D18F5x178_Reserved_1_0_OFFSET 0 +#define D18F5x178_Reserved_1_0_WIDTH 2 +#define D18F5x178_Reserved_1_0_MASK 0x3 +#define D18F5x178_CstateFusionDis_OFFSET 2 +#define D18F5x178_CstateFusionDis_WIDTH 1 +#define D18F5x178_CstateFusionDis_MASK 0x4 +#define D18F5x178_CstateThreeWayHsEn_OFFSET 3 +#define D18F5x178_CstateThreeWayHsEn_WIDTH 1 +#define D18F5x178_CstateThreeWayHsEn_MASK 0x8 +#define D18F5x178_Reserved_9_4_OFFSET 4 +#define D18F5x178_Reserved_9_4_WIDTH 6 +#define D18F5x178_Reserved_9_4_MASK 0x3f0 +#define D18F5x178_InbWakeS3Dis_OFFSET 10 +#define D18F5x178_InbWakeS3Dis_WIDTH 1 +#define D18F5x178_InbWakeS3Dis_MASK 0x400 +#define D18F5x178_AllowSelfRefrS3Dis_OFFSET 11 +#define D18F5x178_AllowSelfRefrS3Dis_WIDTH 1 +#define D18F5x178_AllowSelfRefrS3Dis_MASK 0x800 +#define D18F5x178_CstateFusionHsDis_OFFSET 18 +#define D18F5x178_CstateFusionHsDis_WIDTH 1 +#define D18F5x178_CstateFusionHsDis_MASK 0x40000 +#define D18F5x178_SwGfxDis_OFFSET 19 +#define D18F5x178_SwGfxDis_WIDTH 1 +#define D18F5x178_SwGfxDis_MASK 0x80000 +#define D18F5x178_Reserved_31_20_OFFSET 20 +#define D18F5x178_Reserved_31_20_WIDTH 12 +#define D18F5x178_Reserved_31_20_MASK 0xfff00000 + +/// D18F5x178 +typedef union { + struct { ///< + UINT32 Reserved_1_0:2 ; ///< + UINT32 CstateFusionDis:1 ; ///< + UINT32 CstateThreeWayHsEn:1 ; ///< + UINT32 Reserved_9_4:6 ; ///< + UINT32 InbWakeS3Dis:1 ; ///< + UINT32 AllowSelfRefrS3Dis:1 ; ///< + UINT32 :6 ; ///< + UINT32 CstateFusionHsDis:1 ; ///< + UINT32 SwGfxDis:1 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x178_STRUCT; + +// **** D18F5x17C Register Definition **** +// Address +#define D18F5x17C_ADDRESS 0x17c + +// Type +#define D18F5x17C_TYPE TYPE_D18F5 +// Field Data +#define D18F5x17C_MaxVid_OFFSET 0 +#define D18F5x17C_MaxVid_WIDTH 8 +#define D18F5x17C_MaxVid_MASK 0xff +#define D18F5x17C_Reserved_9_8_OFFSET 8 +#define D18F5x17C_Reserved_9_8_WIDTH 2 +#define D18F5x17C_Reserved_9_8_MASK 0x300 +#define D18F5x17C_MinVid_OFFSET 10 +#define D18F5x17C_MinVid_WIDTH 8 +#define D18F5x17C_MinVid_MASK 0x3fc00 +#define D18F5x17C_Reserved_22_18_OFFSET 18 +#define D18F5x17C_Reserved_22_18_WIDTH 5 +#define D18F5x17C_Reserved_22_18_MASK 0x7c0000 +#define D18F5x17C_NbPsi0Vid_7_0__OFFSET 23 +#define D18F5x17C_NbPsi0Vid_7_0__WIDTH 8 +#define D18F5x17C_NbPsi0Vid_7_0__MASK 0x7f800000 +#define D18F5x17C_NbPsi0VidEn_OFFSET 31 +#define D18F5x17C_NbPsi0VidEn_WIDTH 1 +#define D18F5x17C_NbPsi0VidEn_MASK 0x80000000 + +/// D18F5x17C +typedef union { + struct { ///< + UINT32 MaxVid:8 ; ///< + UINT32 Reserved_9_8:2 ; ///< + UINT32 MinVid:8 ; ///< + UINT32 Reserved_22_18:5 ; ///< + UINT32 NbPsi0Vid_7_0_:8 ; ///< + UINT32 NbPsi0VidEn:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x17C_STRUCT; + +// **** D18F5x188 Register Definition **** +// Address +#define D18F5x188_ADDRESS 0x188 + +// Type +#define D18F5x188_TYPE TYPE_D18F5 +// Field Data +#define D18F5x188_NbOffsetTrim_OFFSET 0 +#define D18F5x188_NbOffsetTrim_WIDTH 2 +#define D18F5x188_NbOffsetTrim_MASK 0x3 +#define D18F5x188_NbLoadLineTrim_OFFSET 2 +#define D18F5x188_NbLoadLineTrim_WIDTH 3 +#define D18F5x188_NbLoadLineTrim_MASK 0x1c +#define D18F5x188_NbPsi1_OFFSET 5 +#define D18F5x188_NbPsi1_WIDTH 1 +#define D18F5x188_NbPsi1_MASK 0x20 +#define D18F5x188_Reserved_31_7_OFFSET 7 +#define D18F5x188_Reserved_31_7_WIDTH 25 +#define D18F5x188_Reserved_31_7_MASK 0xffffff80 + +/// D18F5x188 +typedef union { + struct { ///< + UINT32 NbOffsetTrim:2 ; ///< + UINT32 NbLoadLineTrim:3 ; ///< + UINT32 NbPsi1:1 ; ///< + UINT32 NbTfn:1 ; ///< + UINT32 Reserved_31_7:25; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x188_STRUCT; + +// **** D18F5x194 Register Definition **** +// Address +#define D18F5x194_ADDRESS 0x194 + +// Type +#define D18F5x194_TYPE TYPE_D18F5 +// Field Data +#define D18F5x194_Index_OFFSET 0 +#define D18F5x194_Index_WIDTH 4 +#define D18F5x194_Index_MASK 0xf +#define D18F5x194_Reserved_31_4_OFFSET 4 +#define D18F5x194_Reserved_31_4_WIDTH 28 +#define D18F5x194_Reserved_31_4_MASK 0xfffffff0 + +/// D18F5x194 +typedef union { + struct { ///< + UINT32 Index:4 ; ///< + UINT32 Reserved_31_4:28; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x194_STRUCT; + +// **** D18F5x198 Register Definition **** +// Address +#define D18F5x198_ADDRESS 0x198 + +// Type +#define D18F5x198_TYPE TYPE_D18F5 +// Field Data +#define D18F5x198_Data_OFFSET 0 +#define D18F5x198_Data_WIDTH 32 +#define D18F5x198_Data_MASK 0xffffffff + +/// D18F5x198 +typedef union { + struct { ///< + UINT32 Data:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F5x198_STRUCT; + +// **** DxF0x00 Register Definition **** +// Address +#define DxF0x00_ADDRESS 0x0 + +// Type +#define DxF0x00_TYPE TYPE_D4F0 +// Field Data +#define DxF0x00_VendorID_OFFSET 0 +#define DxF0x00_VendorID_WIDTH 16 +#define DxF0x00_VendorID_MASK 0xffff +#define DxF0x00_DeviceID_OFFSET 16 +#define DxF0x00_DeviceID_WIDTH 16 +#define DxF0x00_DeviceID_MASK 0xffff0000 + +/// DxF0x00 +typedef union { + struct { ///< + UINT32 VendorID:16; ///< + UINT32 DeviceID:16; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x00_STRUCT; + +// **** DxF0x04 Register Definition **** +// Address +#define DxF0x04_ADDRESS 0x4 + +// Type +#define DxF0x04_TYPE TYPE_D4F0 +// Field Data +#define DxF0x04_IoAccessEn_OFFSET 0 +#define DxF0x04_IoAccessEn_WIDTH 1 +#define DxF0x04_IoAccessEn_MASK 0x1 +#define DxF0x04_MemAccessEn_OFFSET 1 +#define DxF0x04_MemAccessEn_WIDTH 1 +#define DxF0x04_MemAccessEn_MASK 0x2 +#define DxF0x04_BusMasterEn_OFFSET 2 +#define DxF0x04_BusMasterEn_WIDTH 1 +#define DxF0x04_BusMasterEn_MASK 0x4 +#define DxF0x04_SpecialCycleEn_OFFSET 3 +#define DxF0x04_SpecialCycleEn_WIDTH 1 +#define DxF0x04_SpecialCycleEn_MASK 0x8 +#define DxF0x04_MemWriteInvalidateEn_OFFSET 4 +#define DxF0x04_MemWriteInvalidateEn_WIDTH 1 +#define DxF0x04_MemWriteInvalidateEn_MASK 0x10 +#define DxF0x04_PalSnoopEn_OFFSET 5 +#define DxF0x04_PalSnoopEn_WIDTH 1 +#define DxF0x04_PalSnoopEn_MASK 0x20 +#define DxF0x04_ParityErrorEn_OFFSET 6 +#define DxF0x04_ParityErrorEn_WIDTH 1 +#define DxF0x04_ParityErrorEn_MASK 0x40 +#define DxF0x04_Stepping_OFFSET 7 +#define DxF0x04_Stepping_WIDTH 1 +#define DxF0x04_Stepping_MASK 0x80 +#define DxF0x04_SerrEn_OFFSET 8 +#define DxF0x04_SerrEn_WIDTH 1 +#define DxF0x04_SerrEn_MASK 0x100 +#define DxF0x04_FastB2BEn_OFFSET 9 +#define DxF0x04_FastB2BEn_WIDTH 1 +#define DxF0x04_FastB2BEn_MASK 0x200 +#define DxF0x04_IntDis_OFFSET 10 +#define DxF0x04_IntDis_WIDTH 1 +#define DxF0x04_IntDis_MASK 0x400 +#define DxF0x04_Reserved_18_11_OFFSET 11 +#define DxF0x04_Reserved_18_11_WIDTH 8 +#define DxF0x04_Reserved_18_11_MASK 0x7f800 +#define DxF0x04_IntStatus_OFFSET 19 +#define DxF0x04_IntStatus_WIDTH 1 +#define DxF0x04_IntStatus_MASK 0x80000 +#define DxF0x04_CapList_OFFSET 20 +#define DxF0x04_CapList_WIDTH 1 +#define DxF0x04_CapList_MASK 0x100000 +#define DxF0x04_PCI66En_OFFSET 21 +#define DxF0x04_PCI66En_WIDTH 1 +#define DxF0x04_PCI66En_MASK 0x200000 +#define DxF0x04_UDFEn_OFFSET 22 +#define DxF0x04_UDFEn_WIDTH 1 +#define DxF0x04_UDFEn_MASK 0x400000 +#define DxF0x04_FastBackCapable_OFFSET 23 +#define DxF0x04_FastBackCapable_WIDTH 1 +#define DxF0x04_FastBackCapable_MASK 0x800000 +#define DxF0x04_DataPerr_OFFSET 24 +#define DxF0x04_DataPerr_WIDTH 1 +#define DxF0x04_DataPerr_MASK 0x1000000 +#define DxF0x04_DevselTiming_OFFSET 25 +#define DxF0x04_DevselTiming_WIDTH 2 +#define DxF0x04_DevselTiming_MASK 0x6000000 +#define DxF0x04_SignalTargetAbort_OFFSET 27 +#define DxF0x04_SignalTargetAbort_WIDTH 1 +#define DxF0x04_SignalTargetAbort_MASK 0x8000000 +#define DxF0x04_ReceivedTargetAbort_OFFSET 28 +#define DxF0x04_ReceivedTargetAbort_WIDTH 1 +#define DxF0x04_ReceivedTargetAbort_MASK 0x10000000 +#define DxF0x04_ReceivedMasterAbort_OFFSET 29 +#define DxF0x04_ReceivedMasterAbort_WIDTH 1 +#define DxF0x04_ReceivedMasterAbort_MASK 0x20000000 +#define DxF0x04_SignaledSystemError_OFFSET 30 +#define DxF0x04_SignaledSystemError_WIDTH 1 +#define DxF0x04_SignaledSystemError_MASK 0x40000000 +#define DxF0x04_ParityErrorDetected_OFFSET 31 +#define DxF0x04_ParityErrorDetected_WIDTH 1 +#define DxF0x04_ParityErrorDetected_MASK 0x80000000 + +/// DxF0x04 +typedef union { + struct { ///< + UINT32 IoAccessEn:1 ; ///< + UINT32 MemAccessEn:1 ; ///< + UINT32 BusMasterEn:1 ; ///< + UINT32 SpecialCycleEn:1 ; ///< + UINT32 MemWriteInvalidateEn:1 ; ///< + UINT32 PalSnoopEn:1 ; ///< + UINT32 ParityErrorEn:1 ; ///< + UINT32 Stepping:1 ; ///< + UINT32 SerrEn:1 ; ///< + UINT32 FastB2BEn:1 ; ///< + UINT32 IntDis:1 ; ///< + UINT32 Reserved_18_11:8 ; ///< + UINT32 IntStatus:1 ; ///< + UINT32 CapList:1 ; ///< + UINT32 PCI66En:1 ; ///< + UINT32 UDFEn:1 ; ///< + UINT32 FastBackCapable:1 ; ///< + UINT32 DataPerr:1 ; ///< + UINT32 DevselTiming:2 ; ///< + UINT32 SignalTargetAbort:1 ; ///< + UINT32 ReceivedTargetAbort:1 ; ///< + UINT32 ReceivedMasterAbort:1 ; ///< + UINT32 SignaledSystemError:1 ; ///< + UINT32 ParityErrorDetected:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x04_STRUCT; + +// **** DxF0x08 Register Definition **** +// Address +#define DxF0x08_ADDRESS 0x8 + +// Type +#define DxF0x08_TYPE TYPE_D4F0 +// Field Data +#define DxF0x08_RevID_OFFSET 0 +#define DxF0x08_RevID_WIDTH 8 +#define DxF0x08_RevID_MASK 0xff +#define DxF0x08_ClassCode_OFFSET 8 +#define DxF0x08_ClassCode_WIDTH 24 +#define DxF0x08_ClassCode_MASK 0xffffff00 + +/// DxF0x08 +typedef union { + struct { ///< + UINT32 RevID:8 ; ///< + UINT32 ClassCode:24; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x08_STRUCT; + +// **** DxF0x0C Register Definition **** +// Address +#define DxF0x0C_ADDRESS 0xc + +// Type +#define DxF0x0C_TYPE TYPE_D4F0 +// Field Data +#define DxF0x0C_CacheLineSize_OFFSET 0 +#define DxF0x0C_CacheLineSize_WIDTH 8 +#define DxF0x0C_CacheLineSize_MASK 0xff +#define DxF0x0C_LatencyTimer_OFFSET 8 +#define DxF0x0C_LatencyTimer_WIDTH 8 +#define DxF0x0C_LatencyTimer_MASK 0xff00 +#define DxF0x0C_HeaderTypeReg_OFFSET 16 +#define DxF0x0C_HeaderTypeReg_WIDTH 8 +#define DxF0x0C_HeaderTypeReg_MASK 0xff0000 +#define DxF0x0C_BIST_OFFSET 24 +#define DxF0x0C_BIST_WIDTH 8 +#define DxF0x0C_BIST_MASK 0xff000000 + +/// DxF0x0C +typedef union { + struct { ///< + UINT32 CacheLineSize:8 ; ///< + UINT32 LatencyTimer:8 ; ///< + UINT32 HeaderTypeReg:8 ; ///< + UINT32 BIST:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x0C_STRUCT; + +// **** DxF0x18 Register Definition **** +// Address +#define DxF0x18_ADDRESS 0x18 + +// Type +#define DxF0x18_TYPE TYPE_D4F0 +// Field Data +#define DxF0x18_PrimaryBus_OFFSET 0 +#define DxF0x18_PrimaryBus_WIDTH 8 +#define DxF0x18_PrimaryBus_MASK 0xff +#define DxF0x18_SecondaryBus_OFFSET 8 +#define DxF0x18_SecondaryBus_WIDTH 8 +#define DxF0x18_SecondaryBus_MASK 0xff00 +#define DxF0x18_SubBusNumber_OFFSET 16 +#define DxF0x18_SubBusNumber_WIDTH 8 +#define DxF0x18_SubBusNumber_MASK 0xff0000 +#define DxF0x18_SecondaryLatencyTimer_OFFSET 24 +#define DxF0x18_SecondaryLatencyTimer_WIDTH 8 +#define DxF0x18_SecondaryLatencyTimer_MASK 0xff000000 + +/// DxF0x18 +typedef union { + struct { ///< + UINT32 PrimaryBus:8 ; ///< + UINT32 SecondaryBus:8 ; ///< + UINT32 SubBusNumber:8 ; ///< + UINT32 SecondaryLatencyTimer:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x18_STRUCT; + +// **** DxF0x1C Register Definition **** +// Address +#define DxF0x1C_ADDRESS 0x1c + +// Type +#define DxF0x1C_TYPE TYPE_D4F0 +// Field Data +#define DxF0x1C_Reserved_3_0_OFFSET 0 +#define DxF0x1C_Reserved_3_0_WIDTH 4 +#define DxF0x1C_Reserved_3_0_MASK 0xf +#define DxF0x1C_IOBase_15_12__OFFSET 4 +#define DxF0x1C_IOBase_15_12__WIDTH 4 +#define DxF0x1C_IOBase_15_12__MASK 0xf0 +#define DxF0x1C_Reserved_11_8_OFFSET 8 +#define DxF0x1C_Reserved_11_8_WIDTH 4 +#define DxF0x1C_Reserved_11_8_MASK 0xf00 +#define DxF0x1C_IOLimit_15_12__OFFSET 12 +#define DxF0x1C_IOLimit_15_12__WIDTH 4 +#define DxF0x1C_IOLimit_15_12__MASK 0xf000 +#define DxF0x1C_Reserved_19_16_OFFSET 16 +#define DxF0x1C_Reserved_19_16_WIDTH 4 +#define DxF0x1C_Reserved_19_16_MASK 0xf0000 +#define DxF0x1C_CapList_OFFSET 20 +#define DxF0x1C_CapList_WIDTH 1 +#define DxF0x1C_CapList_MASK 0x100000 +#define DxF0x1C_PCI66En_OFFSET 21 +#define DxF0x1C_PCI66En_WIDTH 1 +#define DxF0x1C_PCI66En_MASK 0x200000 +#define DxF0x1C_UDFEn_OFFSET 22 +#define DxF0x1C_UDFEn_WIDTH 1 +#define DxF0x1C_UDFEn_MASK 0x400000 +#define DxF0x1C_FastBackCapable_OFFSET 23 +#define DxF0x1C_FastBackCapable_WIDTH 1 +#define DxF0x1C_FastBackCapable_MASK 0x800000 +#define DxF0x1C_MasterDataPerr_OFFSET 24 +#define DxF0x1C_MasterDataPerr_WIDTH 1 +#define DxF0x1C_MasterDataPerr_MASK 0x1000000 +#define DxF0x1C_DevselTiming_OFFSET 25 +#define DxF0x1C_DevselTiming_WIDTH 2 +#define DxF0x1C_DevselTiming_MASK 0x6000000 +#define DxF0x1C_SignalTargetAbort_OFFSET 27 +#define DxF0x1C_SignalTargetAbort_WIDTH 1 +#define DxF0x1C_SignalTargetAbort_MASK 0x8000000 +#define DxF0x1C_ReceivedTargetAbort_OFFSET 28 +#define DxF0x1C_ReceivedTargetAbort_WIDTH 1 +#define DxF0x1C_ReceivedTargetAbort_MASK 0x10000000 +#define DxF0x1C_ReceivedMasterAbort_OFFSET 29 +#define DxF0x1C_ReceivedMasterAbort_WIDTH 1 +#define DxF0x1C_ReceivedMasterAbort_MASK 0x20000000 +#define DxF0x1C_ReceivedSystemError_OFFSET 30 +#define DxF0x1C_ReceivedSystemError_WIDTH 1 +#define DxF0x1C_ReceivedSystemError_MASK 0x40000000 +#define DxF0x1C_ParityErrorDetected_OFFSET 31 +#define DxF0x1C_ParityErrorDetected_WIDTH 1 +#define DxF0x1C_ParityErrorDetected_MASK 0x80000000 + +/// DxF0x1C +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 IOBase_15_12_:4 ; ///< + UINT32 Reserved_11_8:4 ; ///< + UINT32 IOLimit_15_12_:4 ; ///< + UINT32 Reserved_19_16:4 ; ///< + UINT32 CapList:1 ; ///< + UINT32 PCI66En:1 ; ///< + UINT32 UDFEn:1 ; ///< + UINT32 FastBackCapable:1 ; ///< + UINT32 MasterDataPerr:1 ; ///< + UINT32 DevselTiming:2 ; ///< + UINT32 SignalTargetAbort:1 ; ///< + UINT32 ReceivedTargetAbort:1 ; ///< + UINT32 ReceivedMasterAbort:1 ; ///< + UINT32 ReceivedSystemError:1 ; ///< + UINT32 ParityErrorDetected:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x1C_STRUCT; + +// **** DxF0x20 Register Definition **** +// Address +#define DxF0x20_ADDRESS 0x20 + +// Type +#define DxF0x20_TYPE TYPE_D4F0 +// Field Data +#define DxF0x20_Reserved_3_0_OFFSET 0 +#define DxF0x20_Reserved_3_0_WIDTH 4 +#define DxF0x20_Reserved_3_0_MASK 0xf +#define DxF0x20_MemBase_OFFSET 4 +#define DxF0x20_MemBase_WIDTH 12 +#define DxF0x20_MemBase_MASK 0xfff0 +#define DxF0x20_Reserved_19_16_OFFSET 16 +#define DxF0x20_Reserved_19_16_WIDTH 4 +#define DxF0x20_Reserved_19_16_MASK 0xf0000 +#define DxF0x20_MemLimit_OFFSET 20 +#define DxF0x20_MemLimit_WIDTH 12 +#define DxF0x20_MemLimit_MASK 0xfff00000 + +/// DxF0x20 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 MemBase:12; ///< + UINT32 Reserved_19_16:4 ; ///< + UINT32 MemLimit:12; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x20_STRUCT; + +// **** DxF0x24 Register Definition **** +// Address +#define DxF0x24_ADDRESS 0x24 + +// Type +#define DxF0x24_TYPE TYPE_D4F0 +// Field Data +#define DxF0x24_PrefMemBaseR_OFFSET 0 +#define DxF0x24_PrefMemBaseR_WIDTH 4 +#define DxF0x24_PrefMemBaseR_MASK 0xf +#define DxF0x24_PrefMemBase_31_20__OFFSET 4 +#define DxF0x24_PrefMemBase_31_20__WIDTH 12 +#define DxF0x24_PrefMemBase_31_20__MASK 0xfff0 +#define DxF0x24_PrefMemLimitR_OFFSET 16 +#define DxF0x24_PrefMemLimitR_WIDTH 4 +#define DxF0x24_PrefMemLimitR_MASK 0xf0000 +#define DxF0x24_PrefMemLimit_OFFSET 20 +#define DxF0x24_PrefMemLimit_WIDTH 12 +#define DxF0x24_PrefMemLimit_MASK 0xfff00000 + +/// DxF0x24 +typedef union { + struct { ///< + UINT32 PrefMemBaseR:4 ; ///< + UINT32 PrefMemBase_31_20_:12; ///< + UINT32 PrefMemLimitR:4 ; ///< + UINT32 PrefMemLimit:12; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x24_STRUCT; + +// **** DxF0x28 Register Definition **** +// Address +#define DxF0x28_ADDRESS 0x28 + +// Type +#define DxF0x28_TYPE TYPE_D4F0 +// Field Data +#define DxF0x28_PrefMemBase_63_32__OFFSET 0 +#define DxF0x28_PrefMemBase_63_32__WIDTH 32 +#define DxF0x28_PrefMemBase_63_32__MASK 0xffffffff + +/// DxF0x28 +typedef union { + struct { ///< + UINT32 PrefMemBase_63_32_:32; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x28_STRUCT; + +// **** DxF0x2C Register Definition **** +// Address +#define DxF0x2C_ADDRESS 0x2c + +// Type +#define DxF0x2C_TYPE TYPE_D4F0 +// Field Data +#define DxF0x2C_PrefMemLimit_63_32__OFFSET 0 +#define DxF0x2C_PrefMemLimit_63_32__WIDTH 32 +#define DxF0x2C_PrefMemLimit_63_32__MASK 0xffffffff + +/// DxF0x2C +typedef union { + struct { ///< + UINT32 PrefMemLimit_63_32_:32; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x2C_STRUCT; + +// **** DxF0x30 Register Definition **** +// Address +#define DxF0x30_ADDRESS 0x30 + +// Type +#define DxF0x30_TYPE TYPE_D4F0 +// Field Data +#define DxF0x30_IOBase_31_16__OFFSET 0 +#define DxF0x30_IOBase_31_16__WIDTH 16 +#define DxF0x30_IOBase_31_16__MASK 0xffff +#define DxF0x30_IOLimit_31_16__OFFSET 16 +#define DxF0x30_IOLimit_31_16__WIDTH 16 +#define DxF0x30_IOLimit_31_16__MASK 0xffff0000 + +/// DxF0x30 +typedef union { + struct { ///< + UINT32 IOBase_31_16_:16; ///< + UINT32 IOLimit_31_16_:16; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x30_STRUCT; + +// **** DxF0x34 Register Definition **** +// Address +#define DxF0x34_ADDRESS 0x34 + +// Type +#define DxF0x34_TYPE TYPE_D4F0 +// Field Data +#define DxF0x34_CapPtr_OFFSET 0 +#define DxF0x34_CapPtr_WIDTH 8 +#define DxF0x34_CapPtr_MASK 0xff +#define DxF0x34_Reserved_31_8_OFFSET 8 +#define DxF0x34_Reserved_31_8_WIDTH 24 +#define DxF0x34_Reserved_31_8_MASK 0xffffff00 + +/// DxF0x34 +typedef union { + struct { ///< + UINT32 CapPtr:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x34_STRUCT; + +// **** DxF0x3C Register Definition **** +// Address +#define DxF0x3C_ADDRESS 0x3c + +// Type +#define DxF0x3C_TYPE TYPE_D4F0 +// Field Data +#define DxF0x3C_IntLine_OFFSET 0 +#define DxF0x3C_IntLine_WIDTH 8 +#define DxF0x3C_IntLine_MASK 0xff +#define DxF0x3C_IntPin_OFFSET 8 +#define DxF0x3C_IntPin_WIDTH 3 +#define DxF0x3C_IntPin_MASK 0x700 +#define DxF0x3C_IntPinR_OFFSET 11 +#define DxF0x3C_IntPinR_WIDTH 5 +#define DxF0x3C_IntPinR_MASK 0xf800 +#define DxF0x3C_ParityResponseEn_OFFSET 16 +#define DxF0x3C_ParityResponseEn_WIDTH 1 +#define DxF0x3C_ParityResponseEn_MASK 0x10000 +#define DxF0x3C_SerrEn_OFFSET 17 +#define DxF0x3C_SerrEn_WIDTH 1 +#define DxF0x3C_SerrEn_MASK 0x20000 +#define DxF0x3C_IsaEn_OFFSET 18 +#define DxF0x3C_IsaEn_WIDTH 1 +#define DxF0x3C_IsaEn_MASK 0x40000 +#define DxF0x3C_VgaEn_OFFSET 19 +#define DxF0x3C_VgaEn_WIDTH 1 +#define DxF0x3C_VgaEn_MASK 0x80000 +#define DxF0x3C_Vga16En_OFFSET 20 +#define DxF0x3C_Vga16En_WIDTH 1 +#define DxF0x3C_Vga16En_MASK 0x100000 +#define DxF0x3C_MasterAbortMode_OFFSET 21 +#define DxF0x3C_MasterAbortMode_WIDTH 1 +#define DxF0x3C_MasterAbortMode_MASK 0x200000 +#define DxF0x3C_SecondaryBusReset_OFFSET 22 +#define DxF0x3C_SecondaryBusReset_WIDTH 1 +#define DxF0x3C_SecondaryBusReset_MASK 0x400000 +#define DxF0x3C_FastB2BCap_OFFSET 23 +#define DxF0x3C_FastB2BCap_WIDTH 1 +#define DxF0x3C_FastB2BCap_MASK 0x800000 +#define DxF0x3C_Reserved_31_24_OFFSET 24 +#define DxF0x3C_Reserved_31_24_WIDTH 8 +#define DxF0x3C_Reserved_31_24_MASK 0xff000000 + +/// DxF0x3C +typedef union { + struct { ///< + UINT32 IntLine:8 ; ///< + UINT32 IntPin:3 ; ///< + UINT32 IntPinR:5 ; ///< + UINT32 ParityResponseEn:1 ; ///< + UINT32 SerrEn:1 ; ///< + UINT32 IsaEn:1 ; ///< + UINT32 VgaEn:1 ; ///< + UINT32 Vga16En:1 ; ///< + UINT32 MasterAbortMode:1 ; ///< + UINT32 SecondaryBusReset:1 ; ///< + UINT32 FastB2BCap:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x3C_STRUCT; + +// **** DxF0x50 Register Definition **** +// Address +#define DxF0x50_ADDRESS 0x50 + +// Type +#define DxF0x50_TYPE TYPE_D4F0 +// Field Data +#define DxF0x50_CapID_OFFSET 0 +#define DxF0x50_CapID_WIDTH 8 +#define DxF0x50_CapID_MASK 0xff +#define DxF0x50_NextPtr_OFFSET 8 +#define DxF0x50_NextPtr_WIDTH 8 +#define DxF0x50_NextPtr_MASK 0xff00 +#define DxF0x50_Version_OFFSET 16 +#define DxF0x50_Version_WIDTH 3 +#define DxF0x50_Version_MASK 0x70000 +#define DxF0x50_PmeClock_OFFSET 19 +#define DxF0x50_PmeClock_WIDTH 1 +#define DxF0x50_PmeClock_MASK 0x80000 +#define DxF0x50_Reserved_20_20_OFFSET 20 +#define DxF0x50_Reserved_20_20_WIDTH 1 +#define DxF0x50_Reserved_20_20_MASK 0x100000 +#define DxF0x50_DevSpecificInit_OFFSET 21 +#define DxF0x50_DevSpecificInit_WIDTH 1 +#define DxF0x50_DevSpecificInit_MASK 0x200000 +#define DxF0x50_AuxCurrent_OFFSET 22 +#define DxF0x50_AuxCurrent_WIDTH 3 +#define DxF0x50_AuxCurrent_MASK 0x1c00000 +#define DxF0x50_D1Support_OFFSET 25 +#define DxF0x50_D1Support_WIDTH 1 +#define DxF0x50_D1Support_MASK 0x2000000 +#define DxF0x50_D2Support_OFFSET 26 +#define DxF0x50_D2Support_WIDTH 1 +#define DxF0x50_D2Support_MASK 0x4000000 +#define DxF0x50_PmeSupport_OFFSET 27 +#define DxF0x50_PmeSupport_WIDTH 5 +#define DxF0x50_PmeSupport_MASK 0xf8000000 + +/// DxF0x50 +typedef union { + struct { ///< + UINT32 CapID:8 ; ///< + UINT32 NextPtr:8 ; ///< + UINT32 Version:3 ; ///< + UINT32 PmeClock:1 ; ///< + UINT32 Reserved_20_20:1 ; ///< + UINT32 DevSpecificInit:1 ; ///< + UINT32 AuxCurrent:3 ; ///< + UINT32 D1Support:1 ; ///< + UINT32 D2Support:1 ; ///< + UINT32 PmeSupport:5 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x50_STRUCT; + +// **** DxF0x54 Register Definition **** +// Address +#define DxF0x54_ADDRESS 0x54 + +// Type +#define DxF0x54_TYPE TYPE_D4F0 +// Field Data +#define DxF0x54_PowerState_OFFSET 0 +#define DxF0x54_PowerState_WIDTH 2 +#define DxF0x54_PowerState_MASK 0x3 +#define DxF0x54_Reserved_2_2_OFFSET 2 +#define DxF0x54_Reserved_2_2_WIDTH 1 +#define DxF0x54_Reserved_2_2_MASK 0x4 +#define DxF0x54_NoSoftReset_OFFSET 3 +#define DxF0x54_NoSoftReset_WIDTH 1 +#define DxF0x54_NoSoftReset_MASK 0x8 +#define DxF0x54_Reserved_7_4_OFFSET 4 +#define DxF0x54_Reserved_7_4_WIDTH 4 +#define DxF0x54_Reserved_7_4_MASK 0xf0 +#define DxF0x54_PmeEn_OFFSET 8 +#define DxF0x54_PmeEn_WIDTH 1 +#define DxF0x54_PmeEn_MASK 0x100 +#define DxF0x54_DataSelect_OFFSET 9 +#define DxF0x54_DataSelect_WIDTH 4 +#define DxF0x54_DataSelect_MASK 0x1e00 +#define DxF0x54_DataScale_OFFSET 13 +#define DxF0x54_DataScale_WIDTH 2 +#define DxF0x54_DataScale_MASK 0x6000 +#define DxF0x54_PmeStatus_OFFSET 15 +#define DxF0x54_PmeStatus_WIDTH 1 +#define DxF0x54_PmeStatus_MASK 0x8000 +#define DxF0x54_Reserved_21_16_OFFSET 16 +#define DxF0x54_Reserved_21_16_WIDTH 6 +#define DxF0x54_Reserved_21_16_MASK 0x3f0000 +#define DxF0x54_B2B3Support_OFFSET 22 +#define DxF0x54_B2B3Support_WIDTH 1 +#define DxF0x54_B2B3Support_MASK 0x400000 +#define DxF0x54_BusPwrEn_OFFSET 23 +#define DxF0x54_BusPwrEn_WIDTH 1 +#define DxF0x54_BusPwrEn_MASK 0x800000 +#define DxF0x54_PmeData_OFFSET 24 +#define DxF0x54_PmeData_WIDTH 8 +#define DxF0x54_PmeData_MASK 0xff000000 + +/// DxF0x54 +typedef union { + struct { ///< + UINT32 PowerState:2 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 NoSoftReset:1 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 PmeEn:1 ; ///< + UINT32 DataSelect:4 ; ///< + UINT32 DataScale:2 ; ///< + UINT32 PmeStatus:1 ; ///< + UINT32 Reserved_21_16:6 ; ///< + UINT32 B2B3Support:1 ; ///< + UINT32 BusPwrEn:1 ; ///< + UINT32 PmeData:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x54_STRUCT; + +// **** DxF0x58 Register Definition **** +// Address +#define DxF0x58_ADDRESS 0x58 + +// Type +#define DxF0x58_TYPE TYPE_D4F0 +// Field Data +#define DxF0x58_CapID_OFFSET 0 +#define DxF0x58_CapID_WIDTH 8 +#define DxF0x58_CapID_MASK 0xff +#define DxF0x58_NextPtr_OFFSET 8 +#define DxF0x58_NextPtr_WIDTH 8 +#define DxF0x58_NextPtr_MASK 0xff00 +#define DxF0x58_Version_OFFSET 16 +#define DxF0x58_Version_WIDTH 4 +#define DxF0x58_Version_MASK 0xf0000 +#define DxF0x58_DeviceType_OFFSET 20 +#define DxF0x58_DeviceType_WIDTH 4 +#define DxF0x58_DeviceType_MASK 0xf00000 +#define DxF0x58_SlotImplemented_OFFSET 24 +#define DxF0x58_SlotImplemented_WIDTH 1 +#define DxF0x58_SlotImplemented_MASK 0x1000000 +#define DxF0x58_IntMessageNum_OFFSET 25 +#define DxF0x58_IntMessageNum_WIDTH 5 +#define DxF0x58_IntMessageNum_MASK 0x3e000000 +#define DxF0x58_Reserved_31_30_OFFSET 30 +#define DxF0x58_Reserved_31_30_WIDTH 2 +#define DxF0x58_Reserved_31_30_MASK 0xc0000000 + +/// DxF0x58 +typedef union { + struct { ///< + UINT32 CapID:8 ; ///< + UINT32 NextPtr:8 ; ///< + UINT32 Version:4 ; ///< + UINT32 DeviceType:4 ; ///< + UINT32 SlotImplemented:1 ; ///< + UINT32 IntMessageNum:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x58_STRUCT; + +// **** DxF0x5C Register Definition **** +// Address +#define DxF0x5C_ADDRESS 0x5c + +// Type +#define DxF0x5C_TYPE TYPE_D4F0 +// Field Data +#define DxF0x5C_MaxPayloadSupport_OFFSET 0 +#define DxF0x5C_MaxPayloadSupport_WIDTH 3 +#define DxF0x5C_MaxPayloadSupport_MASK 0x7 +#define DxF0x5C_PhantomFunc_OFFSET 3 +#define DxF0x5C_PhantomFunc_WIDTH 2 +#define DxF0x5C_PhantomFunc_MASK 0x18 +#define DxF0x5C_ExtendedTag_OFFSET 5 +#define DxF0x5C_ExtendedTag_WIDTH 1 +#define DxF0x5C_ExtendedTag_MASK 0x20 +#define DxF0x5C_L0SAcceptableLatency_OFFSET 6 +#define DxF0x5C_L0SAcceptableLatency_WIDTH 3 +#define DxF0x5C_L0SAcceptableLatency_MASK 0x1c0 +#define DxF0x5C_L1AcceptableLatency_OFFSET 9 +#define DxF0x5C_L1AcceptableLatency_WIDTH 3 +#define DxF0x5C_L1AcceptableLatency_MASK 0xe00 +#define DxF0x5C_Reserved_14_12_OFFSET 12 +#define DxF0x5C_Reserved_14_12_WIDTH 3 +#define DxF0x5C_Reserved_14_12_MASK 0x7000 +#define DxF0x5C_RoleBasedErrReporting_OFFSET 15 +#define DxF0x5C_RoleBasedErrReporting_WIDTH 1 +#define DxF0x5C_RoleBasedErrReporting_MASK 0x8000 +#define DxF0x5C_Reserved_17_16_OFFSET 16 +#define DxF0x5C_Reserved_17_16_WIDTH 2 +#define DxF0x5C_Reserved_17_16_MASK 0x30000 +#define DxF0x5C_CapturedSlotPowerLimit_OFFSET 18 +#define DxF0x5C_CapturedSlotPowerLimit_WIDTH 8 +#define DxF0x5C_CapturedSlotPowerLimit_MASK 0x3fc0000 +#define DxF0x5C_CapturedSlotPowerScale_OFFSET 26 +#define DxF0x5C_CapturedSlotPowerScale_WIDTH 2 +#define DxF0x5C_CapturedSlotPowerScale_MASK 0xc000000 +#define DxF0x5C_FlrCapable_OFFSET 28 +#define DxF0x5C_FlrCapable_WIDTH 1 +#define DxF0x5C_FlrCapable_MASK 0x10000000 +#define DxF0x5C_Reserved_31_29_OFFSET 29 +#define DxF0x5C_Reserved_31_29_WIDTH 3 +#define DxF0x5C_Reserved_31_29_MASK 0xe0000000 + +/// DxF0x5C +typedef union { + struct { ///< + UINT32 MaxPayloadSupport:3 ; ///< + UINT32 PhantomFunc:2 ; ///< + UINT32 ExtendedTag:1 ; ///< + UINT32 L0SAcceptableLatency:3 ; ///< + UINT32 L1AcceptableLatency:3 ; ///< + UINT32 Reserved_14_12:3 ; ///< + UINT32 RoleBasedErrReporting:1 ; ///< + UINT32 Reserved_17_16:2 ; ///< + UINT32 CapturedSlotPowerLimit:8 ; ///< + UINT32 CapturedSlotPowerScale:2 ; ///< + UINT32 FlrCapable:1 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x5C_STRUCT; + +// **** DxF0x60 Register Definition **** +// Address +#define DxF0x60_ADDRESS 0x60 + +// Type +#define DxF0x60_TYPE TYPE_D4F0 +// Field Data +#define DxF0x60_CorrErrEn_OFFSET 0 +#define DxF0x60_CorrErrEn_WIDTH 1 +#define DxF0x60_CorrErrEn_MASK 0x1 +#define DxF0x60_NonFatalErrEn_OFFSET 1 +#define DxF0x60_NonFatalErrEn_WIDTH 1 +#define DxF0x60_NonFatalErrEn_MASK 0x2 +#define DxF0x60_FatalErrEn_OFFSET 2 +#define DxF0x60_FatalErrEn_WIDTH 1 +#define DxF0x60_FatalErrEn_MASK 0x4 +#define DxF0x60_UsrReportEn_OFFSET 3 +#define DxF0x60_UsrReportEn_WIDTH 1 +#define DxF0x60_UsrReportEn_MASK 0x8 +#define DxF0x60_RelaxedOrdEn_OFFSET 4 +#define DxF0x60_RelaxedOrdEn_WIDTH 1 +#define DxF0x60_RelaxedOrdEn_MASK 0x10 +#define DxF0x60_MaxPayloadSize_OFFSET 5 +#define DxF0x60_MaxPayloadSize_WIDTH 3 +#define DxF0x60_MaxPayloadSize_MASK 0xe0 +#define DxF0x60_ExtendedTagEn_OFFSET 8 +#define DxF0x60_ExtendedTagEn_WIDTH 1 +#define DxF0x60_ExtendedTagEn_MASK 0x100 +#define DxF0x60_PhantomFuncEn_OFFSET 9 +#define DxF0x60_PhantomFuncEn_WIDTH 1 +#define DxF0x60_PhantomFuncEn_MASK 0x200 +#define DxF0x60_AuxPowerPmEn_OFFSET 10 +#define DxF0x60_AuxPowerPmEn_WIDTH 1 +#define DxF0x60_AuxPowerPmEn_MASK 0x400 +#define DxF0x60_NoSnoopEnable_OFFSET 11 +#define DxF0x60_NoSnoopEnable_WIDTH 1 +#define DxF0x60_NoSnoopEnable_MASK 0x800 +#define DxF0x60_MaxRequestSize_OFFSET 12 +#define DxF0x60_MaxRequestSize_WIDTH 3 +#define DxF0x60_MaxRequestSize_MASK 0x7000 +#define DxF0x60_BridgeCfgRetryEn_OFFSET 15 +#define DxF0x60_BridgeCfgRetryEn_WIDTH 1 +#define DxF0x60_BridgeCfgRetryEn_MASK 0x8000 +#define DxF0x60_CorrErr_OFFSET 16 +#define DxF0x60_CorrErr_WIDTH 1 +#define DxF0x60_CorrErr_MASK 0x10000 +#define DxF0x60_NonFatalErr_OFFSET 17 +#define DxF0x60_NonFatalErr_WIDTH 1 +#define DxF0x60_NonFatalErr_MASK 0x20000 +#define DxF0x60_FatalErr_OFFSET 18 +#define DxF0x60_FatalErr_WIDTH 1 +#define DxF0x60_FatalErr_MASK 0x40000 +#define DxF0x60_UsrDetected_OFFSET 19 +#define DxF0x60_UsrDetected_WIDTH 1 +#define DxF0x60_UsrDetected_MASK 0x80000 +#define DxF0x60_AuxPwr_OFFSET 20 +#define DxF0x60_AuxPwr_WIDTH 1 +#define DxF0x60_AuxPwr_MASK 0x100000 +#define DxF0x60_TransactionsPending_OFFSET 21 +#define DxF0x60_TransactionsPending_WIDTH 1 +#define DxF0x60_TransactionsPending_MASK 0x200000 +#define DxF0x60_Reserved_31_22_OFFSET 22 +#define DxF0x60_Reserved_31_22_WIDTH 10 +#define DxF0x60_Reserved_31_22_MASK 0xffc00000 + +/// DxF0x60 +typedef union { + struct { ///< + UINT32 CorrErrEn:1 ; ///< + UINT32 NonFatalErrEn:1 ; ///< + UINT32 FatalErrEn:1 ; ///< + UINT32 UsrReportEn:1 ; ///< + UINT32 RelaxedOrdEn:1 ; ///< + UINT32 MaxPayloadSize:3 ; ///< + UINT32 ExtendedTagEn:1 ; ///< + UINT32 PhantomFuncEn:1 ; ///< + UINT32 AuxPowerPmEn:1 ; ///< + UINT32 NoSnoopEnable:1 ; ///< + UINT32 MaxRequestSize:3 ; ///< + UINT32 BridgeCfgRetryEn:1 ; ///< + UINT32 CorrErr:1 ; ///< + UINT32 NonFatalErr:1 ; ///< + UINT32 FatalErr:1 ; ///< + UINT32 UsrDetected:1 ; ///< + UINT32 AuxPwr:1 ; ///< + UINT32 TransactionsPending:1 ; ///< + UINT32 Reserved_31_22:10; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x60_STRUCT; + +// **** DxF0x64 Register Definition **** +// Address +#define DxF0x64_ADDRESS 0x64 + +// Type +#define DxF0x64_TYPE TYPE_D4F0 +// Field Data +#define DxF0x64_LinkSpeed_OFFSET 0 +#define DxF0x64_LinkSpeed_WIDTH 4 +#define DxF0x64_LinkSpeed_MASK 0xf +#define DxF0x64_LinkWidth_OFFSET 4 +#define DxF0x64_LinkWidth_WIDTH 6 +#define DxF0x64_LinkWidth_MASK 0x3f0 +#define DxF0x64_PMSupport_OFFSET 10 +#define DxF0x64_PMSupport_WIDTH 2 +#define DxF0x64_PMSupport_MASK 0xc00 +#define DxF0x64_L0sExitLatency_OFFSET 12 +#define DxF0x64_L0sExitLatency_WIDTH 3 +#define DxF0x64_L0sExitLatency_MASK 0x7000 +#define DxF0x64_L1ExitLatency_OFFSET 15 +#define DxF0x64_L1ExitLatency_WIDTH 3 +#define DxF0x64_L1ExitLatency_MASK 0x38000 +#define DxF0x64_ClockPowerManagement_OFFSET 18 +#define DxF0x64_ClockPowerManagement_WIDTH 1 +#define DxF0x64_ClockPowerManagement_MASK 0x40000 +#define DxF0x64_SurpriseDownErrReporting_OFFSET 19 +#define DxF0x64_SurpriseDownErrReporting_WIDTH 1 +#define DxF0x64_SurpriseDownErrReporting_MASK 0x80000 +#define DxF0x64_DlActiveReportingCapable_OFFSET 20 +#define DxF0x64_DlActiveReportingCapable_WIDTH 1 +#define DxF0x64_DlActiveReportingCapable_MASK 0x100000 +#define DxF0x64_LinkBWNotificationCap_OFFSET 21 +#define DxF0x64_LinkBWNotificationCap_WIDTH 1 +#define DxF0x64_LinkBWNotificationCap_MASK 0x200000 +#define DxF0x64_AspmOptionalityCompliance_OFFSET 22 +#define DxF0x64_AspmOptionalityCompliance_WIDTH 1 +#define DxF0x64_AspmOptionalityCompliance_MASK 0x400000 +#define DxF0x64_Reserved_23_23_OFFSET 23 +#define DxF0x64_Reserved_23_23_WIDTH 1 +#define DxF0x64_Reserved_23_23_MASK 0x800000 +#define DxF0x64_PortNumber_OFFSET 24 +#define DxF0x64_PortNumber_WIDTH 8 +#define DxF0x64_PortNumber_MASK 0xff000000 + +/// DxF0x64 +typedef union { + struct { ///< + UINT32 LinkSpeed:4 ; ///< + UINT32 LinkWidth:6 ; ///< + UINT32 PMSupport:2 ; ///< + UINT32 L0sExitLatency:3 ; ///< + UINT32 L1ExitLatency:3 ; ///< + UINT32 ClockPowerManagement:1 ; ///< + UINT32 SurpriseDownErrReporting:1 ; ///< + UINT32 DlActiveReportingCapable:1 ; ///< + UINT32 LinkBWNotificationCap:1 ; ///< + UINT32 AspmOptionalityCompliance:1 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 PortNumber:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x64_STRUCT; + +// **** DxF0x68 Register Definition **** +// Address +#define DxF0x68_ADDRESS 0x68 + +// Type +#define DxF0x68_TYPE TYPE_D4F0 +// Field Data +#define DxF0x68_PmControl_OFFSET 0 +#define DxF0x68_PmControl_WIDTH 2 +#define DxF0x68_PmControl_MASK 0x3 +#define DxF0x68_Reserved_2_2_OFFSET 2 +#define DxF0x68_Reserved_2_2_WIDTH 1 +#define DxF0x68_Reserved_2_2_MASK 0x4 +#define DxF0x68_ReadCplBoundary_OFFSET 3 +#define DxF0x68_ReadCplBoundary_WIDTH 1 +#define DxF0x68_ReadCplBoundary_MASK 0x8 +#define DxF0x68_LinkDis_OFFSET 4 +#define DxF0x68_LinkDis_WIDTH 1 +#define DxF0x68_LinkDis_MASK 0x10 +#define DxF0x68_RetrainLink_OFFSET 5 +#define DxF0x68_RetrainLink_WIDTH 1 +#define DxF0x68_RetrainLink_MASK 0x20 +#define DxF0x68_CommonClockCfg_OFFSET 6 +#define DxF0x68_CommonClockCfg_WIDTH 1 +#define DxF0x68_CommonClockCfg_MASK 0x40 +#define DxF0x68_ExtendedSync_OFFSET 7 +#define DxF0x68_ExtendedSync_WIDTH 1 +#define DxF0x68_ExtendedSync_MASK 0x80 +#define DxF0x68_ClockPowerManagementEn_OFFSET 8 +#define DxF0x68_ClockPowerManagementEn_WIDTH 1 +#define DxF0x68_ClockPowerManagementEn_MASK 0x100 +#define DxF0x68_HWAutonomousWidthDisable_OFFSET 9 +#define DxF0x68_HWAutonomousWidthDisable_WIDTH 1 +#define DxF0x68_HWAutonomousWidthDisable_MASK 0x200 +#define DxF0x68_LinkBWManagementEn_OFFSET 10 +#define DxF0x68_LinkBWManagementEn_WIDTH 1 +#define DxF0x68_LinkBWManagementEn_MASK 0x400 +#define DxF0x68_LinkAutonomousBWIntEn_OFFSET 11 +#define DxF0x68_LinkAutonomousBWIntEn_WIDTH 1 +#define DxF0x68_LinkAutonomousBWIntEn_MASK 0x800 +#define DxF0x68_Reserved_15_12_OFFSET 12 +#define DxF0x68_Reserved_15_12_WIDTH 4 +#define DxF0x68_Reserved_15_12_MASK 0xf000 +#define DxF0x68_LinkSpeed_OFFSET 16 +#define DxF0x68_LinkSpeed_WIDTH 4 +#define DxF0x68_LinkSpeed_MASK 0xf0000 +#define DxF0x68_NegotiatedLinkWidth_OFFSET 20 +#define DxF0x68_NegotiatedLinkWidth_WIDTH 6 +#define DxF0x68_NegotiatedLinkWidth_MASK 0x3f00000 +#define DxF0x68_Reserved_26_26_OFFSET 26 +#define DxF0x68_Reserved_26_26_WIDTH 1 +#define DxF0x68_Reserved_26_26_MASK 0x4000000 +#define DxF0x68_LinkTraining_OFFSET 27 +#define DxF0x68_LinkTraining_WIDTH 1 +#define DxF0x68_LinkTraining_MASK 0x8000000 +#define DxF0x68_SlotClockCfg_OFFSET 28 +#define DxF0x68_SlotClockCfg_WIDTH 1 +#define DxF0x68_SlotClockCfg_MASK 0x10000000 +#define DxF0x68_DlActive_OFFSET 29 +#define DxF0x68_DlActive_WIDTH 1 +#define DxF0x68_DlActive_MASK 0x20000000 +#define DxF0x68_LinkBWManagementStatus_OFFSET 30 +#define DxF0x68_LinkBWManagementStatus_WIDTH 1 +#define DxF0x68_LinkBWManagementStatus_MASK 0x40000000 +#define DxF0x68_LinkAutonomousBWStatus_OFFSET 31 +#define DxF0x68_LinkAutonomousBWStatus_WIDTH 1 +#define DxF0x68_LinkAutonomousBWStatus_MASK 0x80000000 + +/// DxF0x68 +typedef union { + struct { ///< + UINT32 PmControl:2 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 ReadCplBoundary:1 ; ///< + UINT32 LinkDis:1 ; ///< + UINT32 RetrainLink:1 ; ///< + UINT32 CommonClockCfg:1 ; ///< + UINT32 ExtendedSync:1 ; ///< + UINT32 ClockPowerManagementEn:1 ; ///< + UINT32 HWAutonomousWidthDisable:1 ; ///< + UINT32 LinkBWManagementEn:1 ; ///< + UINT32 LinkAutonomousBWIntEn:1 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 LinkSpeed:4 ; ///< + UINT32 NegotiatedLinkWidth:6 ; ///< + UINT32 Reserved_26_26:1 ; ///< + UINT32 LinkTraining:1 ; ///< + UINT32 SlotClockCfg:1 ; ///< + UINT32 DlActive:1 ; ///< + UINT32 LinkBWManagementStatus:1 ; ///< + UINT32 LinkAutonomousBWStatus:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x68_STRUCT; + +// **** DxF0x6C Register Definition **** +// Address +#define DxF0x6C_ADDRESS 0x6c + +// Type +#define DxF0x6C_TYPE TYPE_D4F0 +// Field Data +#define DxF0x6C_AttnButtonPresent_OFFSET 0 +#define DxF0x6C_AttnButtonPresent_WIDTH 1 +#define DxF0x6C_AttnButtonPresent_MASK 0x1 +#define DxF0x6C_PwrControllerPresent_OFFSET 1 +#define DxF0x6C_PwrControllerPresent_WIDTH 1 +#define DxF0x6C_PwrControllerPresent_MASK 0x2 +#define DxF0x6C_MrlSensorPresent_OFFSET 2 +#define DxF0x6C_MrlSensorPresent_WIDTH 1 +#define DxF0x6C_MrlSensorPresent_MASK 0x4 +#define DxF0x6C_AttnIndicatorPresent_OFFSET 3 +#define DxF0x6C_AttnIndicatorPresent_WIDTH 1 +#define DxF0x6C_AttnIndicatorPresent_MASK 0x8 +#define DxF0x6C_PwrIndicatorPresent_OFFSET 4 +#define DxF0x6C_PwrIndicatorPresent_WIDTH 1 +#define DxF0x6C_PwrIndicatorPresent_MASK 0x10 +#define DxF0x6C_HotplugSurprise_OFFSET 5 +#define DxF0x6C_HotplugSurprise_WIDTH 1 +#define DxF0x6C_HotplugSurprise_MASK 0x20 +#define DxF0x6C_HotplugCapable_OFFSET 6 +#define DxF0x6C_HotplugCapable_WIDTH 1 +#define DxF0x6C_HotplugCapable_MASK 0x40 +#define DxF0x6C_SlotPwrLimitValue_OFFSET 7 +#define DxF0x6C_SlotPwrLimitValue_WIDTH 8 +#define DxF0x6C_SlotPwrLimitValue_MASK 0x7f80 +#define DxF0x6C_SlotPwrLimitScale_OFFSET 15 +#define DxF0x6C_SlotPwrLimitScale_WIDTH 2 +#define DxF0x6C_SlotPwrLimitScale_MASK 0x18000 +#define DxF0x6C_ElecMechIlPresent_OFFSET 17 +#define DxF0x6C_ElecMechIlPresent_WIDTH 1 +#define DxF0x6C_ElecMechIlPresent_MASK 0x20000 +#define DxF0x6C_NoCmdCplSupport_OFFSET 18 +#define DxF0x6C_NoCmdCplSupport_WIDTH 1 +#define DxF0x6C_NoCmdCplSupport_MASK 0x40000 +#define DxF0x6C_PhysicalSlotNumber_OFFSET 19 +#define DxF0x6C_PhysicalSlotNumber_WIDTH 13 +#define DxF0x6C_PhysicalSlotNumber_MASK 0xfff80000 + +/// DxF0x6C +typedef union { + struct { ///< + UINT32 AttnButtonPresent:1 ; ///< + UINT32 PwrControllerPresent:1 ; ///< + UINT32 MrlSensorPresent:1 ; ///< + UINT32 AttnIndicatorPresent:1 ; ///< + UINT32 PwrIndicatorPresent:1 ; ///< + UINT32 HotplugSurprise:1 ; ///< + UINT32 HotplugCapable:1 ; ///< + UINT32 SlotPwrLimitValue:8 ; ///< + UINT32 SlotPwrLimitScale:2 ; ///< + UINT32 ElecMechIlPresent:1 ; ///< + UINT32 NoCmdCplSupport:1 ; ///< + UINT32 PhysicalSlotNumber:13; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x6C_STRUCT; + +// **** DxF0x70 Register Definition **** +// Address +#define DxF0x70_ADDRESS 0x70 + +// Type +#define DxF0x70_TYPE TYPE_D4F0 +// Field Data +#define DxF0x70_AttnButtonPressedEn_OFFSET 0 +#define DxF0x70_AttnButtonPressedEn_WIDTH 1 +#define DxF0x70_AttnButtonPressedEn_MASK 0x1 +#define DxF0x70_PwrFaultDetectedEn_OFFSET 1 +#define DxF0x70_PwrFaultDetectedEn_WIDTH 1 +#define DxF0x70_PwrFaultDetectedEn_MASK 0x2 +#define DxF0x70_MrlSensorChangedEn_OFFSET 2 +#define DxF0x70_MrlSensorChangedEn_WIDTH 1 +#define DxF0x70_MrlSensorChangedEn_MASK 0x4 +#define DxF0x70_PresenceDetectChangedEn_OFFSET 3 +#define DxF0x70_PresenceDetectChangedEn_WIDTH 1 +#define DxF0x70_PresenceDetectChangedEn_MASK 0x8 +#define DxF0x70_CmdCplIntrEn_OFFSET 4 +#define DxF0x70_CmdCplIntrEn_WIDTH 1 +#define DxF0x70_CmdCplIntrEn_MASK 0x10 +#define DxF0x70_HotplugIntrEn_OFFSET 5 +#define DxF0x70_HotplugIntrEn_WIDTH 1 +#define DxF0x70_HotplugIntrEn_MASK 0x20 +#define DxF0x70_AttnIndicatorControl_OFFSET 6 +#define DxF0x70_AttnIndicatorControl_WIDTH 2 +#define DxF0x70_AttnIndicatorControl_MASK 0xc0 +#define DxF0x70_PwrIndicatorCntl_OFFSET 8 +#define DxF0x70_PwrIndicatorCntl_WIDTH 2 +#define DxF0x70_PwrIndicatorCntl_MASK 0x300 +#define DxF0x70_PwrControllerCntl_OFFSET 10 +#define DxF0x70_PwrControllerCntl_WIDTH 1 +#define DxF0x70_PwrControllerCntl_MASK 0x400 +#define DxF0x70_ElecMechIlCntl_OFFSET 11 +#define DxF0x70_ElecMechIlCntl_WIDTH 1 +#define DxF0x70_ElecMechIlCntl_MASK 0x800 +#define DxF0x70_DlStateChangedEn_OFFSET 12 +#define DxF0x70_DlStateChangedEn_WIDTH 1 +#define DxF0x70_DlStateChangedEn_MASK 0x1000 +#define DxF0x70_Reserved_15_13_OFFSET 13 +#define DxF0x70_Reserved_15_13_WIDTH 3 +#define DxF0x70_Reserved_15_13_MASK 0xe000 +#define DxF0x70_AttnButtonPressed_OFFSET 16 +#define DxF0x70_AttnButtonPressed_WIDTH 1 +#define DxF0x70_AttnButtonPressed_MASK 0x10000 +#define DxF0x70_PwrFaultDetected_OFFSET 17 +#define DxF0x70_PwrFaultDetected_WIDTH 1 +#define DxF0x70_PwrFaultDetected_MASK 0x20000 +#define DxF0x70_MrlSensorChanged_OFFSET 18 +#define DxF0x70_MrlSensorChanged_WIDTH 1 +#define DxF0x70_MrlSensorChanged_MASK 0x40000 +#define DxF0x70_PresenceDetectChanged_OFFSET 19 +#define DxF0x70_PresenceDetectChanged_WIDTH 1 +#define DxF0x70_PresenceDetectChanged_MASK 0x80000 +#define DxF0x70_CmdCpl_OFFSET 20 +#define DxF0x70_CmdCpl_WIDTH 1 +#define DxF0x70_CmdCpl_MASK 0x100000 +#define DxF0x70_MrlSensorState_OFFSET 21 +#define DxF0x70_MrlSensorState_WIDTH 1 +#define DxF0x70_MrlSensorState_MASK 0x200000 +#define DxF0x70_PresenceDetectState_OFFSET 22 +#define DxF0x70_PresenceDetectState_WIDTH 1 +#define DxF0x70_PresenceDetectState_MASK 0x400000 +#define DxF0x70_ElecMechIlSts_OFFSET 23 +#define DxF0x70_ElecMechIlSts_WIDTH 1 +#define DxF0x70_ElecMechIlSts_MASK 0x800000 +#define DxF0x70_DlStateChanged_OFFSET 24 +#define DxF0x70_DlStateChanged_WIDTH 1 +#define DxF0x70_DlStateChanged_MASK 0x1000000 +#define DxF0x70_Reserved_31_25_OFFSET 25 +#define DxF0x70_Reserved_31_25_WIDTH 7 +#define DxF0x70_Reserved_31_25_MASK 0xfe000000 + +/// DxF0x70 +typedef union { + struct { ///< + UINT32 AttnButtonPressedEn:1 ; ///< + UINT32 PwrFaultDetectedEn:1 ; ///< + UINT32 MrlSensorChangedEn:1 ; ///< + UINT32 PresenceDetectChangedEn:1 ; ///< + UINT32 CmdCplIntrEn:1 ; ///< + UINT32 HotplugIntrEn:1 ; ///< + UINT32 AttnIndicatorControl:2 ; ///< + UINT32 PwrIndicatorCntl:2 ; ///< + UINT32 PwrControllerCntl:1 ; ///< + UINT32 ElecMechIlCntl:1 ; ///< + UINT32 DlStateChangedEn:1 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 AttnButtonPressed:1 ; ///< + UINT32 PwrFaultDetected:1 ; ///< + UINT32 MrlSensorChanged:1 ; ///< + UINT32 PresenceDetectChanged:1 ; ///< + UINT32 CmdCpl:1 ; ///< + UINT32 MrlSensorState:1 ; ///< + UINT32 PresenceDetectState:1 ; ///< + UINT32 ElecMechIlSts:1 ; ///< + UINT32 DlStateChanged:1 ; ///< + UINT32 Reserved_31_25:7 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x70_STRUCT; + +// **** DxF0x74 Register Definition **** +// Address +#define DxF0x74_ADDRESS 0x74 + +// Type +#define DxF0x74_TYPE TYPE_D4F0 +// Field Data +#define DxF0x74_SerrOnCorrErrEn_OFFSET 0 +#define DxF0x74_SerrOnCorrErrEn_WIDTH 1 +#define DxF0x74_SerrOnCorrErrEn_MASK 0x1 +#define DxF0x74_SerrOnNonFatalErrEn_OFFSET 1 +#define DxF0x74_SerrOnNonFatalErrEn_WIDTH 1 +#define DxF0x74_SerrOnNonFatalErrEn_MASK 0x2 +#define DxF0x74_SerrOnFatalErrEn_OFFSET 2 +#define DxF0x74_SerrOnFatalErrEn_WIDTH 1 +#define DxF0x74_SerrOnFatalErrEn_MASK 0x4 +#define DxF0x74_PmIntEn_OFFSET 3 +#define DxF0x74_PmIntEn_WIDTH 1 +#define DxF0x74_PmIntEn_MASK 0x8 +#define DxF0x74_CrsSoftVisibilityEn_OFFSET 4 +#define DxF0x74_CrsSoftVisibilityEn_WIDTH 1 +#define DxF0x74_CrsSoftVisibilityEn_MASK 0x10 +#define DxF0x74_Reserved_15_5_OFFSET 5 +#define DxF0x74_Reserved_15_5_WIDTH 11 +#define DxF0x74_Reserved_15_5_MASK 0xffe0 +#define DxF0x74_CrsSoftVisibility_OFFSET 16 +#define DxF0x74_CrsSoftVisibility_WIDTH 1 +#define DxF0x74_CrsSoftVisibility_MASK 0x10000 +#define DxF0x74_Reserved_31_17_OFFSET 17 +#define DxF0x74_Reserved_31_17_WIDTH 15 +#define DxF0x74_Reserved_31_17_MASK 0xfffe0000 + +/// DxF0x74 +typedef union { + struct { ///< + UINT32 SerrOnCorrErrEn:1 ; ///< + UINT32 SerrOnNonFatalErrEn:1 ; ///< + UINT32 SerrOnFatalErrEn:1 ; ///< + UINT32 PmIntEn:1 ; ///< + UINT32 CrsSoftVisibilityEn:1 ; ///< + UINT32 Reserved_15_5:11; ///< + UINT32 CrsSoftVisibility:1 ; ///< + UINT32 Reserved_31_17:15; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x74_STRUCT; + +// **** DxF0x78 Register Definition **** +// Address +#define DxF0x78_ADDRESS 0x78 + +// Type +#define DxF0x78_TYPE TYPE_D4F0 +// Field Data +#define DxF0x78_PmeRequestorId_OFFSET 0 +#define DxF0x78_PmeRequestorId_WIDTH 16 +#define DxF0x78_PmeRequestorId_MASK 0xffff +#define DxF0x78_PmeStatus_OFFSET 16 +#define DxF0x78_PmeStatus_WIDTH 1 +#define DxF0x78_PmeStatus_MASK 0x10000 +#define DxF0x78_PmePending_OFFSET 17 +#define DxF0x78_PmePending_WIDTH 1 +#define DxF0x78_PmePending_MASK 0x20000 +#define DxF0x78_Reserved_31_18_OFFSET 18 +#define DxF0x78_Reserved_31_18_WIDTH 14 +#define DxF0x78_Reserved_31_18_MASK 0xfffc0000 + +/// DxF0x78 +typedef union { + struct { ///< + UINT32 PmeRequestorId:16; ///< + UINT32 PmeStatus:1 ; ///< + UINT32 PmePending:1 ; ///< + UINT32 Reserved_31_18:14; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x78_STRUCT; + +// **** DxF0x7C Register Definition **** +// Address +#define DxF0x7C_ADDRESS 0x7c + +// Type +#define DxF0x7C_TYPE TYPE_D4F0 +// Field Data +#define DxF0x7C_CplTimeoutRangeSup_OFFSET 0 +#define DxF0x7C_CplTimeoutRangeSup_WIDTH 4 +#define DxF0x7C_CplTimeoutRangeSup_MASK 0xf +#define DxF0x7C_CplTimeoutDisSup_OFFSET 4 +#define DxF0x7C_CplTimeoutDisSup_WIDTH 1 +#define DxF0x7C_CplTimeoutDisSup_MASK 0x10 +#define DxF0x7C_AriForwardingSupported_OFFSET 5 +#define DxF0x7C_AriForwardingSupported_WIDTH 1 +#define DxF0x7C_AriForwardingSupported_MASK 0x20 +#define DxF0x7C_Reserved_31_6_OFFSET 6 +#define DxF0x7C_Reserved_31_6_WIDTH 26 +#define DxF0x7C_Reserved_31_6_MASK 0xffffffc0 + +/// DxF0x7C +typedef union { + struct { ///< + UINT32 CplTimeoutRangeSup:4 ; ///< + UINT32 CplTimeoutDisSup:1 ; ///< + UINT32 AriForwardingSupported:1 ; ///< + UINT32 Reserved_31_6:26; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x7C_STRUCT; + +// **** DxF0x80 Register Definition **** +// Address +#define DxF0x80_ADDRESS 0x80 + +// Type +#define DxF0x80_TYPE TYPE_D4F0 +// Field Data +#define DxF0x80_CplTimeoutValue_OFFSET 0 +#define DxF0x80_CplTimeoutValue_WIDTH 4 +#define DxF0x80_CplTimeoutValue_MASK 0xf +#define DxF0x80_CplTimeoutDis_OFFSET 4 +#define DxF0x80_CplTimeoutDis_WIDTH 1 +#define DxF0x80_CplTimeoutDis_MASK 0x10 +#define DxF0x80_AriForwardingEn_OFFSET 5 +#define DxF0x80_AriForwardingEn_WIDTH 1 +#define DxF0x80_AriForwardingEn_MASK 0x20 +#define DxF0x80_Reserved_31_6_OFFSET 6 +#define DxF0x80_Reserved_31_6_WIDTH 26 +#define DxF0x80_Reserved_31_6_MASK 0xffffffc0 + +/// DxF0x80 +typedef union { + struct { ///< + UINT32 CplTimeoutValue:4 ; ///< + UINT32 CplTimeoutDis:1 ; ///< + UINT32 AriForwardingEn:1 ; ///< + UINT32 Reserved_31_6:26; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x80_STRUCT; + +// **** DxF0x84 Register Definition **** +// Address +#define DxF0x84_ADDRESS 0x84 + +// Type +#define DxF0x84_TYPE TYPE_D4F0 +// Field Data +#define DxF0x84_Reserved_31_0_OFFSET 0 +#define DxF0x84_Reserved_31_0_WIDTH 32 +#define DxF0x84_Reserved_31_0_MASK 0xffffffff + +/// DxF0x84 +typedef union { + struct { ///< + UINT32 Reserved_31_0:32; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x84_STRUCT; + +// **** DxF0x88 Register Definition **** +// Address +#define DxF0x88_ADDRESS 0x88 + +// Type +#define DxF0x88_TYPE TYPE_D4F0 +// Field Data +#define DxF0x88_TargetLinkSpeed_OFFSET 0 +#define DxF0x88_TargetLinkSpeed_WIDTH 4 +#define DxF0x88_TargetLinkSpeed_MASK 0xf +#define DxF0x88_EnterCompliance_OFFSET 4 +#define DxF0x88_EnterCompliance_WIDTH 1 +#define DxF0x88_EnterCompliance_MASK 0x10 +#define DxF0x88_HwAutonomousSpeedDisable_OFFSET 5 +#define DxF0x88_HwAutonomousSpeedDisable_WIDTH 1 +#define DxF0x88_HwAutonomousSpeedDisable_MASK 0x20 +#define DxF0x88_SelectableDeemphasis_OFFSET 6 +#define DxF0x88_SelectableDeemphasis_WIDTH 1 +#define DxF0x88_SelectableDeemphasis_MASK 0x40 +#define DxF0x88_XmitMargin_OFFSET 7 +#define DxF0x88_XmitMargin_WIDTH 3 +#define DxF0x88_XmitMargin_MASK 0x380 +#define DxF0x88_EnterModCompliance_OFFSET 10 +#define DxF0x88_EnterModCompliance_WIDTH 1 +#define DxF0x88_EnterModCompliance_MASK 0x400 +#define DxF0x88_ComplianceSOS_OFFSET 11 +#define DxF0x88_ComplianceSOS_WIDTH 1 +#define DxF0x88_ComplianceSOS_MASK 0x800 +#define DxF0x88_ComplianceDeemphasis_OFFSET 12 +#define DxF0x88_ComplianceDeemphasis_WIDTH 1 +#define DxF0x88_ComplianceDeemphasis_MASK 0x1000 +#define DxF0x88_Reserved_15_13_OFFSET 13 +#define DxF0x88_Reserved_15_13_WIDTH 3 +#define DxF0x88_Reserved_15_13_MASK 0xe000 +#define DxF0x88_CurDeemphasisLevel_OFFSET 16 +#define DxF0x88_CurDeemphasisLevel_WIDTH 1 +#define DxF0x88_CurDeemphasisLevel_MASK 0x10000 +#define DxF0x88_Reserved_31_17_OFFSET 17 +#define DxF0x88_Reserved_31_17_WIDTH 15 +#define DxF0x88_Reserved_31_17_MASK 0xfffe0000 + +/// DxF0x88 +typedef union { + struct { ///< + UINT32 TargetLinkSpeed:4 ; ///< + UINT32 EnterCompliance:1 ; ///< + UINT32 HwAutonomousSpeedDisable:1 ; ///< + UINT32 SelectableDeemphasis:1 ; ///< + UINT32 XmitMargin:3 ; ///< + UINT32 EnterModCompliance:1 ; ///< + UINT32 ComplianceSOS:1 ; ///< + UINT32 ComplianceDeemphasis:1 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 CurDeemphasisLevel:1 ; ///< + UINT32 Reserved_31_17:15; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x88_STRUCT; + +// **** DxF0x8C Register Definition **** +// Address +#define DxF0x8C_ADDRESS 0x8c + +// Type +#define DxF0x8C_TYPE TYPE_D4F0 +// Field Data +#define DxF0x8C_Reserved_31_0_OFFSET 0 +#define DxF0x8C_Reserved_31_0_WIDTH 32 +#define DxF0x8C_Reserved_31_0_MASK 0xffffffff + +/// DxF0x8C +typedef union { + struct { ///< + UINT32 Reserved_31_0:32; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x8C_STRUCT; + +// **** DxF0x90 Register Definition **** +// Address +#define DxF0x90_ADDRESS 0x90 + +// Type +#define DxF0x90_TYPE TYPE_D4F0 +// Field Data +#define DxF0x90_Reserved_31_0_OFFSET 0 +#define DxF0x90_Reserved_31_0_WIDTH 32 +#define DxF0x90_Reserved_31_0_MASK 0xffffffff + +/// DxF0x90 +typedef union { + struct { ///< + UINT32 Reserved_31_0:32; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x90_STRUCT; + +// **** DxF0x128 Register Definition **** +// Address +#define DxF0x128_ADDRESS 0x128 + +// Type +#define DxF0x128_TYPE TYPE_D4F0 +// Field Data +#define DxF0x128_Reserved_15_0_OFFSET 0 +#define DxF0x128_Reserved_15_0_WIDTH 16 +#define DxF0x128_Reserved_15_0_MASK 0xffff +#define DxF0x128_PortArbTableStatus_OFFSET 16 +#define DxF0x128_PortArbTableStatus_WIDTH 1 +#define DxF0x128_PortArbTableStatus_MASK 0x10000 +#define DxF0x128_VcNegotiationPending_OFFSET 17 +#define DxF0x128_VcNegotiationPending_WIDTH 1 +#define DxF0x128_VcNegotiationPending_MASK 0x20000 +#define DxF0x128_Reserved_31_18_OFFSET 18 +#define DxF0x128_Reserved_31_18_WIDTH 14 +#define DxF0x128_Reserved_31_18_MASK 0xfffc0000 + +/// DxF0x128 +typedef union { + struct { ///< + UINT32 Reserved_15_0:16; ///< + UINT32 PortArbTableStatus:1 ; ///< + UINT32 VcNegotiationPending:1 ; ///< + UINT32 Reserved_31_18:14; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0x128_STRUCT; + +// **** D0F0x64_x00 Register Definition **** +// Address +#define D0F0x64_x00_ADDRESS 0x0 + +// Type +#define D0F0x64_x00_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x00_Reserved_5_0_OFFSET 0 +#define D0F0x64_x00_Reserved_5_0_WIDTH 6 +#define D0F0x64_x00_Reserved_5_0_MASK 0x3f +#define D0F0x64_x00_NbFchCfgEn_OFFSET 6 +#define D0F0x64_x00_NbFchCfgEn_WIDTH 1 +#define D0F0x64_x00_NbFchCfgEn_MASK 0x40 +#define D0F0x64_x00_HwInitWrLock_OFFSET 7 +#define D0F0x64_x00_HwInitWrLock_WIDTH 1 +#define D0F0x64_x00_HwInitWrLock_MASK 0x80 +#define D0F0x64_x00_Reserved_31_8_OFFSET 8 +#define D0F0x64_x00_Reserved_31_8_WIDTH 24 +#define D0F0x64_x00_Reserved_31_8_MASK 0xffffff00 + +/// D0F0x64_x00 +typedef union { + struct { ///< + UINT32 Reserved_5_0:6 ; ///< + UINT32 NbFchCfgEn:1 ; ///< + UINT32 HwInitWrLock:1 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x00_STRUCT; + +// **** D0F0x64_x0B Register Definition **** +// Address +#define D0F0x64_x0B_ADDRESS 0xb + +// Type +#define D0F0x64_x0B_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x0B_Reserved_19_0_OFFSET 0 +#define D0F0x64_x0B_Reserved_19_0_WIDTH 20 +#define D0F0x64_x0B_Reserved_19_0_MASK 0xfffff +#define D0F0x64_x0B_SetPowEn_OFFSET 20 +#define D0F0x64_x0B_SetPowEn_WIDTH 1 +#define D0F0x64_x0B_SetPowEn_MASK 0x100000 +#define D0F0x64_x0B_IocFchSetPowEn_OFFSET 21 +#define D0F0x64_x0B_IocFchSetPowEn_WIDTH 1 +#define D0F0x64_x0B_IocFchSetPowEn_MASK 0x200000 +#define D0F0x64_x0B_Reserved_22_22_OFFSET 22 +#define D0F0x64_x0B_Reserved_22_22_WIDTH 1 +#define D0F0x64_x0B_Reserved_22_22_MASK 0x400000 +#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_OFFSET 23 +#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_WIDTH 1 +#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_MASK 0x800000 +#define D0F0x64_x0B_Reserved_31_24_OFFSET 24 +#define D0F0x64_x0B_Reserved_31_24_WIDTH 8 +#define D0F0x64_x0B_Reserved_31_24_MASK 0xff000000 + +/// D0F0x64_x0B +typedef union { + struct { ///< + UINT32 Reserved_19_0:20; ///< + UINT32 SetPowEn:1 ; ///< + UINT32 IocFchSetPowEn:1 ; ///< + UINT32 Reserved_22_22:1 ; ///< + UINT32 IocFchSetPmeTurnOffEn:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x0B_STRUCT; + +// **** D0F0x64_x0C Register Definition **** +// Address +#define D0F0x64_x0C_ADDRESS 0xc + +// Type +#define D0F0x64_x0C_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x0C_Reserved_1_0_OFFSET 0 +#define D0F0x64_x0C_Reserved_1_0_WIDTH 2 +#define D0F0x64_x0C_Reserved_1_0_MASK 0x3 +#define D0F0x64_x0C_Dev2BridgeDis_OFFSET 2 +#define D0F0x64_x0C_Dev2BridgeDis_WIDTH 1 +#define D0F0x64_x0C_Dev2BridgeDis_MASK 0x4 +#define D0F0x64_x0C_Dev3BridgeDis_OFFSET 3 +#define D0F0x64_x0C_Dev3BridgeDis_WIDTH 1 +#define D0F0x64_x0C_Dev3BridgeDis_MASK 0x8 +#define D0F0x64_x0C_Dev4BridgeDis_OFFSET 4 +#define D0F0x64_x0C_Dev4BridgeDis_WIDTH 1 +#define D0F0x64_x0C_Dev4BridgeDis_MASK 0x10 +#define D0F0x64_x0C_Dev5BridgeDis_OFFSET 5 +#define D0F0x64_x0C_Dev5BridgeDis_WIDTH 1 +#define D0F0x64_x0C_Dev5BridgeDis_MASK 0x20 +#define D0F0x64_x0C_Dev6BridgeDis_OFFSET 6 +#define D0F0x64_x0C_Dev6BridgeDis_WIDTH 1 +#define D0F0x64_x0C_Dev6BridgeDis_MASK 0x40 +#define D0F0x64_x0C_Dev7BridgeDis_OFFSET 7 +#define D0F0x64_x0C_Dev7BridgeDis_WIDTH 1 +#define D0F0x64_x0C_Dev7BridgeDis_MASK 0x80 +#define D0F0x64_x0C_Reserved_31_8_OFFSET 8 +#define D0F0x64_x0C_Reserved_31_8_WIDTH 24 +#define D0F0x64_x0C_Reserved_31_8_MASK 0xffffff00 + +/// D0F0x64_x0C +typedef union { + struct { ///< + UINT32 Reserved_1_0:2 ; ///< + UINT32 Dev2BridgeDis:1 ; ///< + UINT32 Dev3BridgeDis:1 ; ///< + UINT32 Dev4BridgeDis:1 ; ///< + UINT32 Dev5BridgeDis:1 ; ///< + UINT32 Dev6BridgeDis:1 ; ///< + UINT32 Dev7BridgeDis:1 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x0C_STRUCT; + +// **** D0F0x64_x0D Register Definition **** +// Address +#define D0F0x64_x0D_ADDRESS 0xd + +// Type +#define D0F0x64_x0D_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x0D_PciDev0Fn2RegEn_OFFSET 0 +#define D0F0x64_x0D_PciDev0Fn2RegEn_WIDTH 1 +#define D0F0x64_x0D_PciDev0Fn2RegEn_MASK 0x1 +#define D0F0x64_x0D_Reserved_31_1_OFFSET 1 +#define D0F0x64_x0D_Reserved_31_1_WIDTH 31 +#define D0F0x64_x0D_Reserved_31_1_MASK 0xfffffffe + +/// D0F0x64_x0D +typedef union { + struct { ///< + UINT32 PciDev0Fn2RegEn:1 ; ///< + UINT32 Reserved_31_1:31; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x0D_STRUCT; + +// **** D0F0x64_x16 Register Definition **** +// Address +#define D0F0x64_x16_ADDRESS 0x16 + +// Type +#define D0F0x64_x16_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x16_AerUrMsgEn_OFFSET 0 +#define D0F0x64_x16_AerUrMsgEn_WIDTH 1 +#define D0F0x64_x16_AerUrMsgEn_MASK 0x1 +#define D0F0x64_x16_Reserved_31_1_OFFSET 1 +#define D0F0x64_x16_Reserved_31_1_WIDTH 31 +#define D0F0x64_x16_Reserved_31_1_MASK 0xfffffffe + +/// D0F0x64_x16 +typedef union { + struct { ///< + UINT32 AerUrMsgEn:1 ; ///< + UINT32 Reserved_31_1:31; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x16_STRUCT; + +// **** D0F0x64_x19 Register Definition **** +// Address +#define D0F0x64_x19_ADDRESS 0x19 + +// Type +#define D0F0x64_x19_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x19_TomEn_OFFSET 0 +#define D0F0x64_x19_TomEn_WIDTH 1 +#define D0F0x64_x19_TomEn_MASK 0x1 +#define D0F0x64_x19_Reserved_22_1_OFFSET 1 +#define D0F0x64_x19_Reserved_22_1_WIDTH 22 +#define D0F0x64_x19_Reserved_22_1_MASK 0x7ffffe +#define D0F0x64_x19_Tom2_31_23__OFFSET 23 +#define D0F0x64_x19_Tom2_31_23__WIDTH 9 +#define D0F0x64_x19_Tom2_31_23__MASK 0xff800000 + +/// D0F0x64_x19 +typedef union { + struct { ///< + UINT32 TomEn:1 ; ///< + UINT32 Reserved_22_1:22; ///< + UINT32 Tom2_31_23_:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x19_STRUCT; + +// **** D0F0x64_x1A Register Definition **** +// Address +#define D0F0x64_x1A_ADDRESS 0x1a + +// Type +#define D0F0x64_x1A_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x1A_Tom2_39_32__OFFSET 0 +#define D0F0x64_x1A_Tom2_39_32__WIDTH 8 +#define D0F0x64_x1A_Tom2_39_32__MASK 0xff +#define D0F0x64_x1A_Reserved_31_8_OFFSET 8 +#define D0F0x64_x1A_Reserved_31_8_WIDTH 24 +#define D0F0x64_x1A_Reserved_31_8_MASK 0xffffff00 + +/// D0F0x64_x1A +typedef union { + struct { ///< + UINT32 Tom2_39_32_:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x1A_STRUCT; + +// **** D0F0x64_x1C Register Definition **** +// Address +#define D0F0x64_x1C_ADDRESS 0x1c + +// Type +#define D0F0x64_x1C_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x1C_WriteDis_OFFSET 0 +#define D0F0x64_x1C_WriteDis_WIDTH 1 +#define D0F0x64_x1C_WriteDis_MASK 0x1 +#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_OFFSET 1 +#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_WIDTH 1 +#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_MASK 0x2 +#define D0F0x64_x1C_F064BarEn_OFFSET 2 +#define D0F0x64_x1C_F064BarEn_WIDTH 1 +#define D0F0x64_x1C_F064BarEn_MASK 0x4 +#define D0F0x64_x1C_MemApSize_OFFSET 3 +#define D0F0x64_x1C_MemApSize_WIDTH 3 +#define D0F0x64_x1C_MemApSize_MASK 0x38 +#define D0F0x64_x1C_RegApSize_OFFSET 6 +#define D0F0x64_x1C_RegApSize_WIDTH 1 +#define D0F0x64_x1C_RegApSize_MASK 0x40 +#define D0F0x64_x1C_Reserved_7_7_OFFSET 7 +#define D0F0x64_x1C_Reserved_7_7_WIDTH 1 +#define D0F0x64_x1C_Reserved_7_7_MASK 0x80 +#define D0F0x64_x1C_AudioEn_OFFSET 8 +#define D0F0x64_x1C_AudioEn_WIDTH 1 +#define D0F0x64_x1C_AudioEn_MASK 0x100 +#define D0F0x64_x1C_MsiDis_OFFSET 9 +#define D0F0x64_x1C_MsiDis_WIDTH 1 +#define D0F0x64_x1C_MsiDis_MASK 0x200 +#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_OFFSET 10 +#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_WIDTH 1 +#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_MASK 0x400 +#define D0F0x64_x1C_Audio64BarEn_OFFSET 11 +#define D0F0x64_x1C_Audio64BarEn_WIDTH 1 +#define D0F0x64_x1C_Audio64BarEn_MASK 0x800 +#define D0F0x64_x1C_Reserved_15_12_OFFSET 12 +#define D0F0x64_x1C_Reserved_15_12_WIDTH 4 +#define D0F0x64_x1C_Reserved_15_12_MASK 0xf000 +#define D0F0x64_x1C_IoBarDis_OFFSET 16 +#define D0F0x64_x1C_IoBarDis_WIDTH 1 +#define D0F0x64_x1C_IoBarDis_MASK 0x10000 +#define D0F0x64_x1C_F0En_OFFSET 17 +#define D0F0x64_x1C_F0En_WIDTH 1 +#define D0F0x64_x1C_F0En_MASK 0x20000 +#define D0F0x64_x1C_Reserved_22_18_OFFSET 18 +#define D0F0x64_x1C_Reserved_22_18_WIDTH 5 +#define D0F0x64_x1C_Reserved_22_18_MASK 0x7c0000 +#define D0F0x64_x1C_RcieEn_OFFSET 23 +#define D0F0x64_x1C_RcieEn_WIDTH 1 +#define D0F0x64_x1C_RcieEn_MASK 0x800000 +#define D0F0x64_x1C_Reserved_31_24_OFFSET 24 +#define D0F0x64_x1C_Reserved_31_24_WIDTH 8 +#define D0F0x64_x1C_Reserved_31_24_MASK 0xff000000 + +/// D0F0x64_x1C +typedef union { + struct { ///< + UINT32 WriteDis:1 ; ///< + UINT32 F0NonlegacyDeviceTypeEn:1 ; ///< + UINT32 F064BarEn:1 ; ///< + UINT32 MemApSize:3 ; ///< + UINT32 RegApSize:1 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 AudioEn:1 ; ///< + UINT32 MsiDis:1 ; ///< + UINT32 AudioNonlegacyDeviceTypeEn:1 ; ///< + UINT32 Audio64BarEn:1 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 IoBarDis:1 ; ///< + UINT32 F0En:1 ; ///< + UINT32 Reserved_22_18:5 ; ///< + UINT32 RcieEn:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x1C_STRUCT; + +// **** D0F0x64_x1D Register Definition **** +// Address +#define D0F0x64_x1D_ADDRESS 0x1d + +// Type +#define D0F0x64_x1D_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x1D_IntGfxAsPcieEn_OFFSET 0 +#define D0F0x64_x1D_IntGfxAsPcieEn_WIDTH 1 +#define D0F0x64_x1D_IntGfxAsPcieEn_MASK 0x1 +#define D0F0x64_x1D_VgaEn_OFFSET 1 +#define D0F0x64_x1D_VgaEn_WIDTH 1 +#define D0F0x64_x1D_VgaEn_MASK 0x2 +#define D0F0x64_x1D_Reserved_2_2_OFFSET 2 +#define D0F0x64_x1D_Reserved_2_2_WIDTH 1 +#define D0F0x64_x1D_Reserved_2_2_MASK 0x4 +#define D0F0x64_x1D_Vga16En_OFFSET 3 +#define D0F0x64_x1D_Vga16En_WIDTH 1 +#define D0F0x64_x1D_Vga16En_MASK 0x8 +#define D0F0x64_x1D_Reserved_31_4_OFFSET 4 +#define D0F0x64_x1D_Reserved_31_4_WIDTH 28 +#define D0F0x64_x1D_Reserved_31_4_MASK 0xfffffff0 + +/// D0F0x64_x1D +typedef union { + struct { ///< + UINT32 IntGfxAsPcieEn:1 ; ///< + UINT32 VgaEn:1 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 Vga16En:1 ; ///< + UINT32 Reserved_31_4:28; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x1D_STRUCT; + +// **** D0F0x64_x20 Register Definition **** +// Address +#define D0F0x64_x20_ADDRESS 0x20 + +// Type +#define D0F0x64_x20_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x20_ProgDevMapEn_OFFSET 0 +#define D0F0x64_x20_ProgDevMapEn_WIDTH 1 +#define D0F0x64_x20_ProgDevMapEn_MASK 0x1 +#define D0F0x64_x20_IocPcieDevRemapDis_OFFSET 1 +#define D0F0x64_x20_IocPcieDevRemapDis_WIDTH 1 +#define D0F0x64_x20_IocPcieDevRemapDis_MASK 0x2 +#define D0F0x64_x20_Reserved_3_2_OFFSET 2 +#define D0F0x64_x20_Reserved_3_2_WIDTH 2 +#define D0F0x64_x20_Reserved_3_2_MASK 0xc +#define D0F0x64_x20_GppPortBDevmap_OFFSET 4 +#define D0F0x64_x20_GppPortBDevmap_WIDTH 4 +#define D0F0x64_x20_GppPortBDevmap_MASK 0xf0 +#define D0F0x64_x20_GppPortCDevmap_OFFSET 8 +#define D0F0x64_x20_GppPortCDevmap_WIDTH 4 +#define D0F0x64_x20_GppPortCDevmap_MASK 0xf00 +#define D0F0x64_x20_GppPortDDevmap_OFFSET 12 +#define D0F0x64_x20_GppPortDDevmap_WIDTH 4 +#define D0F0x64_x20_GppPortDDevmap_MASK 0xf000 +#define D0F0x64_x20_GppPortEDevmap_OFFSET 16 +#define D0F0x64_x20_GppPortEDevmap_WIDTH 4 +#define D0F0x64_x20_GppPortEDevmap_MASK 0xf0000 +#define D0F0x64_x20_Reserved_31_20_OFFSET 20 +#define D0F0x64_x20_Reserved_31_20_WIDTH 12 +#define D0F0x64_x20_Reserved_31_20_MASK 0xfff00000 + +/// D0F0x64_x20 +typedef union { + struct { ///< + UINT32 ProgDevMapEn:1 ; ///< + UINT32 IocPcieDevRemapDis:1 ; ///< + UINT32 Reserved_3_2:2 ; ///< + UINT32 GppPortBDevmap:4 ; ///< + UINT32 GppPortCDevmap:4 ; ///< + UINT32 GppPortDDevmap:4 ; ///< + UINT32 GppPortEDevmap:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x20_STRUCT; + +// **** D0F0x64_x21 Register Definition **** +// Address +#define D0F0x64_x21_ADDRESS 0x21 + +// Type +#define D0F0x64_x21_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x21_Reserved_11_0_OFFSET 0 +#define D0F0x64_x21_Reserved_11_0_WIDTH 12 +#define D0F0x64_x21_Reserved_11_0_MASK 0xfff +#define D0F0x64_x21_GfxPortADevmap_OFFSET 12 +#define D0F0x64_x21_GfxPortADevmap_WIDTH 4 +#define D0F0x64_x21_GfxPortADevmap_MASK 0xf000 +#define D0F0x64_x21_GfxPortBDevmap_OFFSET 16 +#define D0F0x64_x21_GfxPortBDevmap_WIDTH 4 +#define D0F0x64_x21_GfxPortBDevmap_MASK 0xf0000 +#define D0F0x64_x21_Reserved_31_20_OFFSET 20 +#define D0F0x64_x21_Reserved_31_20_WIDTH 12 +#define D0F0x64_x21_Reserved_31_20_MASK 0xfff00000 + +/// D0F0x64_x21 +typedef union { + struct { ///< + UINT32 Reserved_11_0:12; ///< + UINT32 GfxPortADevmap:4 ; ///< + UINT32 GfxPortBDevmap:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x21_STRUCT; + +// **** D0F0x64_x22 Register Definition **** +// Address +#define D0F0x64_x22_ADDRESS 0x22 + +// Type +#define D0F0x64_x22_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x22_Reserved_25_0_OFFSET 0 +#define D0F0x64_x22_Reserved_25_0_WIDTH 26 +#define D0F0x64_x22_Reserved_25_0_MASK 0x3ffffff +#define D0F0x64_x22_SoftOverrideClk4_OFFSET 26 +#define D0F0x64_x22_SoftOverrideClk4_WIDTH 1 +#define D0F0x64_x22_SoftOverrideClk4_MASK 0x4000000 +#define D0F0x64_x22_SoftOverrideClk3_OFFSET 27 +#define D0F0x64_x22_SoftOverrideClk3_WIDTH 1 +#define D0F0x64_x22_SoftOverrideClk3_MASK 0x8000000 +#define D0F0x64_x22_SoftOverrideClk2_OFFSET 28 +#define D0F0x64_x22_SoftOverrideClk2_WIDTH 1 +#define D0F0x64_x22_SoftOverrideClk2_MASK 0x10000000 +#define D0F0x64_x22_SoftOverrideClk1_OFFSET 29 +#define D0F0x64_x22_SoftOverrideClk1_WIDTH 1 +#define D0F0x64_x22_SoftOverrideClk1_MASK 0x20000000 +#define D0F0x64_x22_SoftOverrideClk0_OFFSET 30 +#define D0F0x64_x22_SoftOverrideClk0_WIDTH 1 +#define D0F0x64_x22_SoftOverrideClk0_MASK 0x40000000 +#define D0F0x64_x22_Reserved_31_31_OFFSET 31 +#define D0F0x64_x22_Reserved_31_31_WIDTH 1 +#define D0F0x64_x22_Reserved_31_31_MASK 0x80000000 + +/// D0F0x64_x22 +typedef union { + struct { ///< + UINT32 Reserved_25_0:26; ///< + UINT32 SoftOverrideClk4:1 ; ///< + UINT32 SoftOverrideClk3:1 ; ///< + UINT32 SoftOverrideClk2:1 ; ///< + UINT32 SoftOverrideClk1:1 ; ///< + UINT32 SoftOverrideClk0:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x22_STRUCT; + +// **** D0F0x64_x23 Register Definition **** +// Address +#define D0F0x64_x23_ADDRESS 0x23 + +// Type +#define D0F0x64_x23_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x23_Reserved_25_0_OFFSET 0 +#define D0F0x64_x23_Reserved_25_0_WIDTH 26 +#define D0F0x64_x23_Reserved_25_0_MASK 0x3ffffff +#define D0F0x64_x23_SoftOverrideClk4_OFFSET 26 +#define D0F0x64_x23_SoftOverrideClk4_WIDTH 1 +#define D0F0x64_x23_SoftOverrideClk4_MASK 0x4000000 +#define D0F0x64_x23_SoftOverrideClk3_OFFSET 27 +#define D0F0x64_x23_SoftOverrideClk3_WIDTH 1 +#define D0F0x64_x23_SoftOverrideClk3_MASK 0x8000000 +#define D0F0x64_x23_SoftOverrideClk2_OFFSET 28 +#define D0F0x64_x23_SoftOverrideClk2_WIDTH 1 +#define D0F0x64_x23_SoftOverrideClk2_MASK 0x10000000 +#define D0F0x64_x23_SoftOverrideClk1_OFFSET 29 +#define D0F0x64_x23_SoftOverrideClk1_WIDTH 1 +#define D0F0x64_x23_SoftOverrideClk1_MASK 0x20000000 +#define D0F0x64_x23_SoftOverrideClk0_OFFSET 30 +#define D0F0x64_x23_SoftOverrideClk0_WIDTH 1 +#define D0F0x64_x23_SoftOverrideClk0_MASK 0x40000000 +#define D0F0x64_x23_Reserved_31_31_OFFSET 31 +#define D0F0x64_x23_Reserved_31_31_WIDTH 1 +#define D0F0x64_x23_Reserved_31_31_MASK 0x80000000 + +/// D0F0x64_x23 +typedef union { + struct { ///< + UINT32 Reserved_25_0:26; ///< + UINT32 SoftOverrideClk4:1 ; ///< + UINT32 SoftOverrideClk3:1 ; ///< + UINT32 SoftOverrideClk2:1 ; ///< + UINT32 SoftOverrideClk1:1 ; ///< + UINT32 SoftOverrideClk0:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x23_STRUCT; + + +// **** D0F0x64_x46 Register Definition **** +// Address +#define D0F0x64_x46_ADDRESS 0x46 + +// Type +#define D0F0x64_x46_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x46_Reserved_0_0_OFFSET 0 +#define D0F0x64_x46_Reserved_0_0_WIDTH 1 +#define D0F0x64_x46_Reserved_0_0_MASK 0x1 +#define D0F0x64_x46_Reserved_15_3_OFFSET 3 +#define D0F0x64_x46_Reserved_15_3_WIDTH 13 +#define D0F0x64_x46_Reserved_15_3_MASK 0xfff8 +#define D0F0x64_x46_Msi64bitEn_OFFSET 16 +#define D0F0x64_x46_Msi64bitEn_WIDTH 1 +#define D0F0x64_x46_Msi64bitEn_MASK 0x10000 +#define D0F0x64_x46_Reserved_31_17_OFFSET 17 +#define D0F0x64_x46_Reserved_31_17_WIDTH 15 +#define D0F0x64_x46_Reserved_31_17_MASK 0xfffe0000 + +/// D0F0x64_x46 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 :2 ; ///< + UINT32 Reserved_15_3:13; ///< + UINT32 Msi64bitEn:1 ; ///< + UINT32 Reserved_31_17:15; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x46_STRUCT; + + +// **** D0F0x64_x53 Register Definition **** +// Address +#define D0F0x64_x53_ADDRESS 0x53 + +// Type +#define D0F0x64_x53_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x53_Reserved_19_0_OFFSET 0 +#define D0F0x64_x53_Reserved_19_0_WIDTH 20 +#define D0F0x64_x53_Reserved_19_0_MASK 0xfffff +#define D0F0x64_x53_SetPowEn_OFFSET 20 +#define D0F0x64_x53_SetPowEn_WIDTH 1 +#define D0F0x64_x53_SetPowEn_MASK 0x100000 +#define D0F0x64_x53_Reserved_31_21_OFFSET 21 +#define D0F0x64_x53_Reserved_31_21_WIDTH 11 +#define D0F0x64_x53_Reserved_31_21_MASK 0xffe00000 + +/// D0F0x64_x53 +typedef union { + struct { ///< + UINT32 Reserved_19_0:20; ///< + UINT32 SetPowEn:1 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x53_STRUCT; + +// **** D0F0x64_x55 Register Definition **** +// Address +#define D0F0x64_x55_ADDRESS 0x55 + +// Type +#define D0F0x64_x55_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x55_Reserved_19_0_OFFSET 0 +#define D0F0x64_x55_Reserved_19_0_WIDTH 20 +#define D0F0x64_x55_Reserved_19_0_MASK 0xfffff +#define D0F0x64_x55_SetPowEn_OFFSET 20 +#define D0F0x64_x55_SetPowEn_WIDTH 1 +#define D0F0x64_x55_SetPowEn_MASK 0x100000 +#define D0F0x64_x55_Reserved_31_21_OFFSET 21 +#define D0F0x64_x55_Reserved_31_21_WIDTH 11 +#define D0F0x64_x55_Reserved_31_21_MASK 0xffe00000 + +/// D0F0x64_x55 +typedef union { + struct { ///< + UINT32 Reserved_19_0:20; ///< + UINT32 SetPowEn:1 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x55_STRUCT; + +// **** D0F0x64_x57 Register Definition **** +// Address +#define D0F0x64_x57_ADDRESS 0x57 + +// Type +#define D0F0x64_x57_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x57_Reserved_19_0_OFFSET 0 +#define D0F0x64_x57_Reserved_19_0_WIDTH 20 +#define D0F0x64_x57_Reserved_19_0_MASK 0xfffff +#define D0F0x64_x57_SetPowEn_OFFSET 20 +#define D0F0x64_x57_SetPowEn_WIDTH 1 +#define D0F0x64_x57_SetPowEn_MASK 0x100000 +#define D0F0x64_x57_Reserved_31_21_OFFSET 21 +#define D0F0x64_x57_Reserved_31_21_WIDTH 11 +#define D0F0x64_x57_Reserved_31_21_MASK 0xffe00000 + +/// D0F0x64_x57 +typedef union { + struct { ///< + UINT32 Reserved_19_0:20; ///< + UINT32 SetPowEn:1 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x57_STRUCT; + +// **** D0F0x64_x59 Register Definition **** +// Address +#define D0F0x64_x59_ADDRESS 0x59 + +// Type +#define D0F0x64_x59_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x59_Reserved_19_0_OFFSET 0 +#define D0F0x64_x59_Reserved_19_0_WIDTH 20 +#define D0F0x64_x59_Reserved_19_0_MASK 0xfffff +#define D0F0x64_x59_SetPowEn_OFFSET 20 +#define D0F0x64_x59_SetPowEn_WIDTH 1 +#define D0F0x64_x59_SetPowEn_MASK 0x100000 +#define D0F0x64_x59_Reserved_31_21_OFFSET 21 +#define D0F0x64_x59_Reserved_31_21_WIDTH 11 +#define D0F0x64_x59_Reserved_31_21_MASK 0xffe00000 + +/// D0F0x64_x59 +typedef union { + struct { ///< + UINT32 Reserved_19_0:20; ///< + UINT32 SetPowEn:1 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x59_STRUCT; + +// **** D0F0x64_x5B Register Definition **** +// Address +#define D0F0x64_x5B_ADDRESS 0x5b + +// Type +#define D0F0x64_x5B_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x5B_Reserved_19_0_OFFSET 0 +#define D0F0x64_x5B_Reserved_19_0_WIDTH 20 +#define D0F0x64_x5B_Reserved_19_0_MASK 0xfffff +#define D0F0x64_x5B_SetPowEn_OFFSET 20 +#define D0F0x64_x5B_SetPowEn_WIDTH 1 +#define D0F0x64_x5B_SetPowEn_MASK 0x100000 +#define D0F0x64_x5B_Reserved_31_21_OFFSET 21 +#define D0F0x64_x5B_Reserved_31_21_WIDTH 11 +#define D0F0x64_x5B_Reserved_31_21_MASK 0xffe00000 + +/// D0F0x64_x5B +typedef union { + struct { ///< + UINT32 Reserved_19_0:20; ///< + UINT32 SetPowEn:1 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x5B_STRUCT; + +// **** D0F0x98_x06 Register Definition **** +// Address +#define D0F0x98_x06_ADDRESS 0x6 + +// Type +#define D0F0x98_x06_TYPE TYPE_D0F0x98 +// Field Data +#define D0F0x98_x06_Reserved_25_0_OFFSET 0 +#define D0F0x98_x06_Reserved_25_0_WIDTH 26 +#define D0F0x98_x06_Reserved_25_0_MASK 0x3ffffff +#define D0F0x98_x06_UmiNpMemWrEn_OFFSET 26 +#define D0F0x98_x06_UmiNpMemWrEn_WIDTH 1 +#define D0F0x98_x06_UmiNpMemWrEn_MASK 0x4000000 +#define D0F0x98_x06_Reserved_31_27_OFFSET 27 +#define D0F0x98_x06_Reserved_31_27_WIDTH 5 +#define D0F0x98_x06_Reserved_31_27_MASK 0xf8000000 + +/// D0F0x98_x06 +typedef union { + struct { ///< + UINT32 Reserved_25_0:26; ///< + UINT32 UmiNpMemWrEn:1 ; ///< + UINT32 Reserved_31_27:5 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_x06_STRUCT; + +// **** D0F0x98_x07 Register Definition **** +// Address +#define D0F0x98_x07_ADDRESS 0x7 + +// Type +#define D0F0x98_x07_TYPE TYPE_D0F0x98 +// Field Data +#define D0F0x98_x07_IocBwOptEn_OFFSET 0 +#define D0F0x98_x07_IocBwOptEn_WIDTH 1 +#define D0F0x98_x07_IocBwOptEn_MASK 0x1 +#define D0F0x98_x07_Reserved_3_1_OFFSET 1 +#define D0F0x98_x07_Reserved_3_1_WIDTH 3 +#define D0F0x98_x07_Reserved_3_1_MASK 0xe +#define D0F0x98_x07_IommuBwOptEn_OFFSET 4 +#define D0F0x98_x07_IommuBwOptEn_WIDTH 1 +#define D0F0x98_x07_IommuBwOptEn_MASK 0x10 +#define D0F0x98_x07_Reserved_5_5_OFFSET 5 +#define D0F0x98_x07_Reserved_5_5_WIDTH 1 +#define D0F0x98_x07_Reserved_5_5_MASK 0x20 +#define D0F0x98_x07_DmaReqRespPassPWMode_OFFSET 6 +#define D0F0x98_x07_DmaReqRespPassPWMode_WIDTH 1 +#define D0F0x98_x07_DmaReqRespPassPWMode_MASK 0x40 +#define D0F0x98_x07_IommuIsocPassPWMode_OFFSET 7 +#define D0F0x98_x07_IommuIsocPassPWMode_WIDTH 1 +#define D0F0x98_x07_IommuIsocPassPWMode_MASK 0x80 +#define D0F0x98_x07_Reserved_13_8_OFFSET 8 +#define D0F0x98_x07_Reserved_13_8_WIDTH 6 +#define D0F0x98_x07_Reserved_13_8_MASK 0x3f00 +#define D0F0x98_x07_MSIHTIntConversionEn_OFFSET 14 +#define D0F0x98_x07_MSIHTIntConversionEn_WIDTH 1 +#define D0F0x98_x07_MSIHTIntConversionEn_MASK 0x4000 +#define D0F0x98_x07_DropZeroMaskWrEn_OFFSET 15 +#define D0F0x98_x07_DropZeroMaskWrEn_WIDTH 1 +#define D0F0x98_x07_DropZeroMaskWrEn_MASK 0x8000 +#define D0F0x98_x07_Reserved_29_16_OFFSET 16 +#define D0F0x98_x07_Reserved_29_16_WIDTH 14 +#define D0F0x98_x07_Reserved_29_16_MASK 0x3fff0000 +#define D0F0x98_x07_UnadjustThrottlingStpclk_OFFSET 30 +#define D0F0x98_x07_UnadjustThrottlingStpclk_WIDTH 1 +#define D0F0x98_x07_UnadjustThrottlingStpclk_MASK 0x40000000 +#define D0F0x98_x07_SMUCsrIsocEn_OFFSET 31 +#define D0F0x98_x07_SMUCsrIsocEn_WIDTH 1 +#define D0F0x98_x07_SMUCsrIsocEn_MASK 0x80000000 + +/// D0F0x98_x07 +typedef union { + struct { ///< + UINT32 IocBwOptEn:1 ; ///< + UINT32 Reserved_3_1:3 ; ///< + UINT32 IommuBwOptEn:1 ; ///< + UINT32 Reserved_5_5:1 ; ///< + UINT32 DmaReqRespPassPWMode:1 ; ///< + UINT32 IommuIsocPassPWMode:1 ; ///< + UINT32 Reserved_13_8:6 ; ///< + UINT32 MSIHTIntConversionEn:1 ; ///< + UINT32 DropZeroMaskWrEn:1 ; ///< + UINT32 Reserved_29_16:14; ///< + UINT32 UnadjustThrottlingStpclk:1 ; ///< + UINT32 SMUCsrIsocEn:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_x07_STRUCT; + +// **** D0F0x98_x08 Register Definition **** +// Address +#define D0F0x98_x08_ADDRESS 0x8 + +// Type +#define D0F0x98_x08_TYPE TYPE_D0F0x98 +// Field Data +#define D0F0x98_x08_NpWrrLenA_OFFSET 0 +#define D0F0x98_x08_NpWrrLenA_WIDTH 8 +#define D0F0x98_x08_NpWrrLenA_MASK 0xff +#define D0F0x98_x08_NpWrrLenB_OFFSET 8 +#define D0F0x98_x08_NpWrrLenB_WIDTH 8 +#define D0F0x98_x08_NpWrrLenB_MASK 0xff00 +#define D0F0x98_x08_NpWrrLenC_OFFSET 16 +#define D0F0x98_x08_NpWrrLenC_WIDTH 8 +#define D0F0x98_x08_NpWrrLenC_MASK 0xff0000 +#define D0F0x98_x08_Reserved_31_24_OFFSET 24 +#define D0F0x98_x08_Reserved_31_24_WIDTH 8 +#define D0F0x98_x08_Reserved_31_24_MASK 0xff000000 + +/// D0F0x98_x08 +typedef union { + struct { ///< + UINT32 NpWrrLenA:8 ; ///< + UINT32 NpWrrLenB:8 ; ///< + UINT32 NpWrrLenC:8 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_x08_STRUCT; + +// **** D0F0x98_x09 Register Definition **** +// Address +#define D0F0x98_x09_ADDRESS 0x9 + +// Type +#define D0F0x98_x09_TYPE TYPE_D0F0x98 +// Field Data +#define D0F0x98_x09_PWrrLenA_OFFSET 0 +#define D0F0x98_x09_PWrrLenA_WIDTH 8 +#define D0F0x98_x09_PWrrLenA_MASK 0xff +#define D0F0x98_x09_PWrrLenB_OFFSET 8 +#define D0F0x98_x09_PWrrLenB_WIDTH 8 +#define D0F0x98_x09_PWrrLenB_MASK 0xff00 +#define D0F0x98_x09_Reserved_31_16_OFFSET 16 +#define D0F0x98_x09_Reserved_31_16_WIDTH 16 +#define D0F0x98_x09_Reserved_31_16_MASK 0xffff0000 + +/// D0F0x98_x09 +typedef union { + struct { ///< + UINT32 PWrrLenA:8 ; ///< + UINT32 PWrrLenB:8 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_x09_STRUCT; + +// **** D0F0x98_x0C Register Definition **** +// Address +#define D0F0x98_x0C_ADDRESS 0xc + +// Type +#define D0F0x98_x0C_TYPE TYPE_D0F0x98 +// Field Data +#define D0F0x98_x0C_GcmWrrLenA_OFFSET 0 +#define D0F0x98_x0C_GcmWrrLenA_WIDTH 8 +#define D0F0x98_x0C_GcmWrrLenA_MASK 0xff +#define D0F0x98_x0C_GcmWrrLenB_OFFSET 8 +#define D0F0x98_x0C_GcmWrrLenB_WIDTH 8 +#define D0F0x98_x0C_GcmWrrLenB_MASK 0xff00 +#define D0F0x98_x0C_Reserved_29_16_OFFSET 16 +#define D0F0x98_x0C_Reserved_29_16_WIDTH 14 +#define D0F0x98_x0C_Reserved_29_16_MASK 0x3fff0000 +#define D0F0x98_x0C_StrictSelWinnerEn_OFFSET 30 +#define D0F0x98_x0C_StrictSelWinnerEn_WIDTH 1 +#define D0F0x98_x0C_StrictSelWinnerEn_MASK 0x40000000 +#define D0F0x98_x0C_Reserved_31_31_OFFSET 31 +#define D0F0x98_x0C_Reserved_31_31_WIDTH 1 +#define D0F0x98_x0C_Reserved_31_31_MASK 0x80000000 + +/// D0F0x98_x0C +typedef union { + struct { ///< + UINT32 GcmWrrLenA:8 ; ///< + UINT32 GcmWrrLenB:8 ; ///< + UINT32 Reserved_29_16:14; ///< + UINT32 StrictSelWinnerEn:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_x0C_STRUCT; + +// **** D0F0x98_x1E Register Definition **** +// Address +#define D0F0x98_x1E_ADDRESS 0x1e + +// Type +#define D0F0x98_x1E_TYPE TYPE_D0F0x98 +// Field Data +#define D0F0x98_x1E_Reserved_0_0_OFFSET 0 +#define D0F0x98_x1E_Reserved_0_0_WIDTH 1 +#define D0F0x98_x1E_Reserved_0_0_MASK 0x1 +#define D0F0x98_x1E_HiPriEn_OFFSET 1 +#define D0F0x98_x1E_HiPriEn_WIDTH 1 +#define D0F0x98_x1E_HiPriEn_MASK 0x2 +#define D0F0x98_x1E_Reserved_31_2_OFFSET 2 +#define D0F0x98_x1E_Reserved_31_2_WIDTH 30 +#define D0F0x98_x1E_Reserved_31_2_MASK 0xfffffffc + +/// D0F0x98_x1E +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 HiPriEn:1 ; ///< + UINT32 Reserved_31_2:30; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_x1E_STRUCT; + +// **** D0F0x98_x26 Register Definition **** +// Address +#define D0F0x98_x26_ADDRESS 0x26 + +// Type +#define D0F0x98_x26_TYPE TYPE_D0F0x98 +// Field Data +#define D0F0x98_x26_IOMMUUrAddr_39_32__OFFSET 0 +#define D0F0x98_x26_IOMMUUrAddr_39_32__WIDTH 8 +#define D0F0x98_x26_IOMMUUrAddr_39_32__MASK 0xff +#define D0F0x98_x26_Reserved_31_8_OFFSET 8 +#define D0F0x98_x26_Reserved_31_8_WIDTH 24 +#define D0F0x98_x26_Reserved_31_8_MASK 0xffffff00 + +/// D0F0x98_x26 +typedef union { + struct { ///< + UINT32 IOMMUUrAddr_39_32_:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_x26_STRUCT; + +// **** D0F0x98_x27 Register Definition **** +// Address +#define D0F0x98_x27_ADDRESS 0x27 + +// Type +#define D0F0x98_x27_TYPE TYPE_D0F0x98 +// Field Data +#define D0F0x98_x27_Reserved_5_0_OFFSET 0 +#define D0F0x98_x27_Reserved_5_0_WIDTH 6 +#define D0F0x98_x27_Reserved_5_0_MASK 0x3f +#define D0F0x98_x27_IOMMUUrAddr_31_6__OFFSET 6 +#define D0F0x98_x27_IOMMUUrAddr_31_6__WIDTH 26 +#define D0F0x98_x27_IOMMUUrAddr_31_6__MASK 0xffffffc0 + +/// D0F0x98_x27 +typedef union { + struct { ///< + UINT32 Reserved_5_0:6 ; ///< + UINT32 IOMMUUrAddr_31_6_:26; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_x27_STRUCT; + +// **** D0F0x98_x28 Register Definition **** +// Address +#define D0F0x98_x28_ADDRESS 0x28 + +// Type +#define D0F0x98_x28_TYPE TYPE_D0F0x98 +// Field Data +#define D0F0x98_x28_Reserved_0_0_OFFSET 0 +#define D0F0x98_x28_Reserved_0_0_WIDTH 1 +#define D0F0x98_x28_Reserved_0_0_MASK 0x1 +#define D0F0x98_x28_ForceCoherentIntr_OFFSET 1 +#define D0F0x98_x28_ForceCoherentIntr_WIDTH 1 +#define D0F0x98_x28_ForceCoherentIntr_MASK 0x2 +#define D0F0x98_x28_Reserved_31_2_OFFSET 2 +#define D0F0x98_x28_Reserved_31_2_WIDTH 30 +#define D0F0x98_x28_Reserved_31_2_MASK 0xfffffffc + +/// D0F0x98_x28 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 ForceCoherentIntr:1 ; ///< + UINT32 Reserved_31_2:30; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_x28_STRUCT; + + +// **** D0F0x98_x2C Register Definition **** +// Address +#define D0F0x98_x2C_ADDRESS 0x2c + +// Type +#define D0F0x98_x2C_TYPE TYPE_D0F0x98 +// Field Data +#define D0F0x98_x2C_Reserved_0_0_OFFSET 0 +#define D0F0x98_x2C_Reserved_0_0_WIDTH 1 +#define D0F0x98_x2C_Reserved_0_0_MASK 0x1 +#define D0F0x98_x2C_DynWakeEn_OFFSET 1 +#define D0F0x98_x2C_DynWakeEn_WIDTH 1 +#define D0F0x98_x2C_DynWakeEn_MASK 0x2 +#define D0F0x98_x2C_Reserved_7_2_OFFSET 2 +#define D0F0x98_x2C_Reserved_7_2_WIDTH 6 +#define D0F0x98_x2C_Reserved_7_2_MASK 0xfc +#define D0F0x98_x2C_OrbRxIdlesMask_OFFSET 8 +#define D0F0x98_x2C_OrbRxIdlesMask_WIDTH 1 +#define D0F0x98_x2C_OrbRxIdlesMask_MASK 0x100 +#define D0F0x98_x2C_SBDmaActiveMask_OFFSET 9 +#define D0F0x98_x2C_SBDmaActiveMask_WIDTH 1 +#define D0F0x98_x2C_SBDmaActiveMask_MASK 0x200 +#define D0F0x98_x2C_NBOutbWakeMask_OFFSET 10 +#define D0F0x98_x2C_NBOutbWakeMask_WIDTH 1 +#define D0F0x98_x2C_NBOutbWakeMask_MASK 0x400 +#define D0F0x98_x2C_Reserved_15_11_OFFSET 11 +#define D0F0x98_x2C_Reserved_15_11_WIDTH 5 +#define D0F0x98_x2C_Reserved_15_11_MASK 0xf800 +#define D0F0x98_x2C_WakeHysteresis_OFFSET 16 +#define D0F0x98_x2C_WakeHysteresis_WIDTH 16 +#define D0F0x98_x2C_WakeHysteresis_MASK 0xffff0000 + +/// D0F0x98_x2C +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 DynWakeEn:1 ; ///< + UINT32 Reserved_7_2:6 ; ///< + UINT32 OrbRxIdlesMask:1 ; ///< + UINT32 SBDmaActiveMask:1 ; ///< + UINT32 NBOutbWakeMask:1 ; ///< + UINT32 Reserved_15_11:5 ; ///< + UINT32 WakeHysteresis:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_x2C_STRUCT; + +// **** D0F0x98_x3A Register Definition **** +// Address +#define D0F0x98_x3A_ADDRESS 0x3a + +// Type +#define D0F0x98_x3A_TYPE TYPE_D0F0x98 +// Field Data +#define D0F0x98_x3A_ClumpingEn_OFFSET 0 +#define D0F0x98_x3A_ClumpingEn_WIDTH 32 +#define D0F0x98_x3A_ClumpingEn_MASK 0xffffffff + +/// D0F0x98_x3A +typedef union { + struct { ///< + UINT32 ClumpingEn:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_x3A_STRUCT; + +// **** D0F0x98_x49 Register Definition **** +// Address +#define D0F0x98_x49_ADDRESS 0x49 + +// Type +#define D0F0x98_x49_TYPE TYPE_D0F0x98 +// Field Data +#define D0F0x98_x49_Reserved_23_0_OFFSET 0 +#define D0F0x98_x49_Reserved_23_0_WIDTH 24 +#define D0F0x98_x49_Reserved_23_0_MASK 0xffffff +#define D0F0x98_x49_SoftOverrideClk6_OFFSET 24 +#define D0F0x98_x49_SoftOverrideClk6_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk6_MASK 0x1000000 +#define D0F0x98_x49_SoftOverrideClk5_OFFSET 25 +#define D0F0x98_x49_SoftOverrideClk5_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk5_MASK 0x2000000 +#define D0F0x98_x49_SoftOverrideClk4_OFFSET 26 +#define D0F0x98_x49_SoftOverrideClk4_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk4_MASK 0x4000000 +#define D0F0x98_x49_SoftOverrideClk3_OFFSET 27 +#define D0F0x98_x49_SoftOverrideClk3_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk3_MASK 0x8000000 +#define D0F0x98_x49_SoftOverrideClk2_OFFSET 28 +#define D0F0x98_x49_SoftOverrideClk2_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk2_MASK 0x10000000 +#define D0F0x98_x49_SoftOverrideClk1_OFFSET 29 +#define D0F0x98_x49_SoftOverrideClk1_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk1_MASK 0x20000000 +#define D0F0x98_x49_SoftOverrideClk0_OFFSET 30 +#define D0F0x98_x49_SoftOverrideClk0_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk0_MASK 0x40000000 +#define D0F0x98_x49_Reserved_31_31_OFFSET 31 +#define D0F0x98_x49_Reserved_31_31_WIDTH 1 +#define D0F0x98_x49_Reserved_31_31_MASK 0x80000000 + +/// D0F0x98_x49 +typedef union { + struct { ///< + UINT32 Reserved_23_0:24; ///< + UINT32 SoftOverrideClk6:1 ; ///< + UINT32 SoftOverrideClk5:1 ; ///< + UINT32 SoftOverrideClk4:1 ; ///< + UINT32 SoftOverrideClk3:1 ; ///< + UINT32 SoftOverrideClk2:1 ; ///< + UINT32 SoftOverrideClk1:1 ; ///< + UINT32 SoftOverrideClk0:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_x49_STRUCT; + +// **** D0F0x98_x4A Register Definition **** +// Address +#define D0F0x98_x4A_ADDRESS 0x4a + +// Type +#define D0F0x98_x4A_TYPE TYPE_D0F0x98 +// Field Data +#define D0F0x98_x4A_Reserved_23_0_OFFSET 0 +#define D0F0x98_x4A_Reserved_23_0_WIDTH 24 +#define D0F0x98_x4A_Reserved_23_0_MASK 0xffffff +#define D0F0x98_x4A_SoftOverrideClk6_OFFSET 24 +#define D0F0x98_x4A_SoftOverrideClk6_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk6_MASK 0x1000000 +#define D0F0x98_x4A_SoftOverrideClk5_OFFSET 25 +#define D0F0x98_x4A_SoftOverrideClk5_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk5_MASK 0x2000000 +#define D0F0x98_x4A_SoftOverrideClk4_OFFSET 26 +#define D0F0x98_x4A_SoftOverrideClk4_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk4_MASK 0x4000000 +#define D0F0x98_x4A_SoftOverrideClk3_OFFSET 27 +#define D0F0x98_x4A_SoftOverrideClk3_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk3_MASK 0x8000000 +#define D0F0x98_x4A_SoftOverrideClk2_OFFSET 28 +#define D0F0x98_x4A_SoftOverrideClk2_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk2_MASK 0x10000000 +#define D0F0x98_x4A_SoftOverrideClk1_OFFSET 29 +#define D0F0x98_x4A_SoftOverrideClk1_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk1_MASK 0x20000000 +#define D0F0x98_x4A_SoftOverrideClk0_OFFSET 30 +#define D0F0x98_x4A_SoftOverrideClk0_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk0_MASK 0x40000000 +#define D0F0x98_x4A_Reserved_31_31_OFFSET 31 +#define D0F0x98_x4A_Reserved_31_31_WIDTH 1 +#define D0F0x98_x4A_Reserved_31_31_MASK 0x80000000 + +/// D0F0x98_x4A +typedef union { + struct { ///< + UINT32 Reserved_23_0:24; ///< + UINT32 SoftOverrideClk6:1 ; ///< + UINT32 SoftOverrideClk5:1 ; ///< + UINT32 SoftOverrideClk4:1 ; ///< + UINT32 SoftOverrideClk3:1 ; ///< + UINT32 SoftOverrideClk2:1 ; ///< + UINT32 SoftOverrideClk1:1 ; ///< + UINT32 SoftOverrideClk0:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_x4A_STRUCT; + +// **** D0F0xBC_x1F200 Register Definition **** +// Address +#define D0F0xBC_x1F200_ADDRESS 0x1f200 + +// Type +#define D0F0xBC_x1F200_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F200_StateValid_OFFSET 0 +#define D0F0xBC_x1F200_StateValid_WIDTH 1 +#define D0F0xBC_x1F200_StateValid_MASK 0x1 +#define D0F0xBC_x1F200_Reserved_7_1_OFFSET 1 +#define D0F0xBC_x1F200_Reserved_7_1_WIDTH 7 +#define D0F0xBC_x1F200_Reserved_7_1_MASK 0xfe +#define D0F0xBC_x1F200_LclkDivider_OFFSET 8 +#define D0F0xBC_x1F200_LclkDivider_WIDTH 8 +#define D0F0xBC_x1F200_LclkDivider_MASK 0xff00 +#define D0F0xBC_x1F200_VID_OFFSET 16 +#define D0F0xBC_x1F200_VID_WIDTH 8 +#define D0F0xBC_x1F200_VID_MASK 0xff0000 +#define D0F0xBC_x1F200_LowVoltageReqThreshold_OFFSET 24 +#define D0F0xBC_x1F200_LowVoltageReqThreshold_WIDTH 8 +#define D0F0xBC_x1F200_LowVoltageReqThreshold_MASK 0xff000000 + +/// D0F0xBC_x1F200 +typedef union { + struct { ///< + UINT32 StateValid:1 ; ///< + UINT32 Reserved_7_1:7 ; ///< + UINT32 LclkDivider:8 ; ///< + UINT32 VID:8 ; ///< + UINT32 LowVoltageReqThreshold:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F200_STRUCT; + +// **** D0F0xBC_x1F208 Register Definition **** +// Address +#define D0F0xBC_x1F208_ADDRESS 0x1f208 + +// Type +#define D0F0xBC_x1F208_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F208_HysteresisUp_OFFSET 0 +#define D0F0xBC_x1F208_HysteresisUp_WIDTH 8 +#define D0F0xBC_x1F208_HysteresisUp_MASK 0xff +#define D0F0xBC_x1F208_HysteresisDown_OFFSET 8 +#define D0F0xBC_x1F208_HysteresisDown_WIDTH 8 +#define D0F0xBC_x1F208_HysteresisDown_MASK 0xff00 +#define D0F0xBC_x1F208_ResidencyCounter_OFFSET 16 +#define D0F0xBC_x1F208_ResidencyCounter_WIDTH 16 +#define D0F0xBC_x1F208_ResidencyCounter_MASK 0xffff0000 + +/// D0F0xBC_x1F208 +typedef union { + struct { ///< + UINT32 HysteresisUp:8 ; ///< + UINT32 HysteresisDown:8 ; ///< + UINT32 ResidencyCounter:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F208_STRUCT; + +// **** D0F0xBC_x1F210 Register Definition **** +// Address +#define D0F0xBC_x1F210_ADDRESS 0x1f210 + +// Type +#define D0F0xBC_x1F210_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F210_ActivityThreshold_OFFSET 0 +#define D0F0xBC_x1F210_ActivityThreshold_WIDTH 8 +#define D0F0xBC_x1F210_ActivityThreshold_MASK 0xff +#define D0F0xBC_x1F210_Reserved_31_8_OFFSET 8 +#define D0F0xBC_x1F210_Reserved_31_8_WIDTH 24 +#define D0F0xBC_x1F210_Reserved_31_8_MASK 0xffffff00 + +/// D0F0xBC_x1F210 +typedef union { + struct { ///< + UINT32 ActivityThreshold:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F210_STRUCT; + +// **** D0F0xBC_x1F220 Register Definition **** +// Address +#define D0F0xBC_x1F220_ADDRESS 0x1f220 + +// Type +#define D0F0xBC_x1F220_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F220_StateValid_OFFSET 0 +#define D0F0xBC_x1F220_StateValid_WIDTH 1 +#define D0F0xBC_x1F220_StateValid_MASK 0x1 +#define D0F0xBC_x1F220_Reserved_7_1_OFFSET 1 +#define D0F0xBC_x1F220_Reserved_7_1_WIDTH 7 +#define D0F0xBC_x1F220_Reserved_7_1_MASK 0xfe +#define D0F0xBC_x1F220_LclkDivider_OFFSET 8 +#define D0F0xBC_x1F220_LclkDivider_WIDTH 8 +#define D0F0xBC_x1F220_LclkDivider_MASK 0xff00 +#define D0F0xBC_x1F220_VID_OFFSET 16 +#define D0F0xBC_x1F220_VID_WIDTH 8 +#define D0F0xBC_x1F220_VID_MASK 0xff0000 +#define D0F0xBC_x1F220_LowVoltageReqThreshold_OFFSET 24 +#define D0F0xBC_x1F220_LowVoltageReqThreshold_WIDTH 8 +#define D0F0xBC_x1F220_LowVoltageReqThreshold_MASK 0xff000000 + +/// D0F0xBC_x1F220 +typedef union { + struct { ///< + UINT32 StateValid:1 ; ///< + UINT32 Reserved_7_1:7 ; ///< + UINT32 LclkDivider:8 ; ///< + UINT32 VID:8 ; ///< + UINT32 LowVoltageReqThreshold:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F220_STRUCT; + +// **** D0F0xBC_x1F228 Register Definition **** +// Address +#define D0F0xBC_x1F228_ADDRESS 0x1f228 + +// Type +#define D0F0xBC_x1F228_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F228_HysteresisUp_OFFSET 0 +#define D0F0xBC_x1F228_HysteresisUp_WIDTH 8 +#define D0F0xBC_x1F228_HysteresisUp_MASK 0xff +#define D0F0xBC_x1F228_HysteresisDown_OFFSET 8 +#define D0F0xBC_x1F228_HysteresisDown_WIDTH 8 +#define D0F0xBC_x1F228_HysteresisDown_MASK 0xff00 +#define D0F0xBC_x1F228_ResidencyCounter_OFFSET 16 +#define D0F0xBC_x1F228_ResidencyCounter_WIDTH 16 +#define D0F0xBC_x1F228_ResidencyCounter_MASK 0xffff0000 + +/// D0F0xBC_x1F228 +typedef union { + struct { ///< + UINT32 HysteresisUp:8 ; ///< + UINT32 HysteresisDown:8 ; ///< + UINT32 ResidencyCounter:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F228_STRUCT; + +// **** D0F0xBC_x1F230 Register Definition **** +// Address +#define D0F0xBC_x1F230_ADDRESS 0x1f230 + +// Type +#define D0F0xBC_x1F230_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F230_ActivityThreshold_OFFSET 0 +#define D0F0xBC_x1F230_ActivityThreshold_WIDTH 8 +#define D0F0xBC_x1F230_ActivityThreshold_MASK 0xff +#define D0F0xBC_x1F230_Reserved_31_8_OFFSET 8 +#define D0F0xBC_x1F230_Reserved_31_8_WIDTH 24 +#define D0F0xBC_x1F230_Reserved_31_8_MASK 0xffffff00 + +/// D0F0xBC_x1F230 +typedef union { + struct { ///< + UINT32 ActivityThreshold:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F230_STRUCT; + +// **** D0F0xBC_x1F240 Register Definition **** +// Address +#define D0F0xBC_x1F240_ADDRESS 0x1f240 + +// Type +#define D0F0xBC_x1F240_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F240_StateValid_OFFSET 0 +#define D0F0xBC_x1F240_StateValid_WIDTH 1 +#define D0F0xBC_x1F240_StateValid_MASK 0x1 +#define D0F0xBC_x1F240_Reserved_7_1_OFFSET 1 +#define D0F0xBC_x1F240_Reserved_7_1_WIDTH 7 +#define D0F0xBC_x1F240_Reserved_7_1_MASK 0xfe +#define D0F0xBC_x1F240_LclkDivider_OFFSET 8 +#define D0F0xBC_x1F240_LclkDivider_WIDTH 8 +#define D0F0xBC_x1F240_LclkDivider_MASK 0xff00 +#define D0F0xBC_x1F240_VID_OFFSET 16 +#define D0F0xBC_x1F240_VID_WIDTH 8 +#define D0F0xBC_x1F240_VID_MASK 0xff0000 +#define D0F0xBC_x1F240_LowVoltageReqThreshold_OFFSET 24 +#define D0F0xBC_x1F240_LowVoltageReqThreshold_WIDTH 8 +#define D0F0xBC_x1F240_LowVoltageReqThreshold_MASK 0xff000000 + +/// D0F0xBC_x1F240 +typedef union { + struct { ///< + UINT32 StateValid:1 ; ///< + UINT32 Reserved_7_1:7 ; ///< + UINT32 LclkDivider:8 ; ///< + UINT32 VID:8 ; ///< + UINT32 LowVoltageReqThreshold:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F240_STRUCT; + +// **** D0F0xBC_x1F248 Register Definition **** +// Address +#define D0F0xBC_x1F248_ADDRESS 0x1f248 + +// Type +#define D0F0xBC_x1F248_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F248_HysteresisUp_OFFSET 0 +#define D0F0xBC_x1F248_HysteresisUp_WIDTH 8 +#define D0F0xBC_x1F248_HysteresisUp_MASK 0xff +#define D0F0xBC_x1F248_HysteresisDown_OFFSET 8 +#define D0F0xBC_x1F248_HysteresisDown_WIDTH 8 +#define D0F0xBC_x1F248_HysteresisDown_MASK 0xff00 +#define D0F0xBC_x1F248_ResidencyCounter_OFFSET 16 +#define D0F0xBC_x1F248_ResidencyCounter_WIDTH 16 +#define D0F0xBC_x1F248_ResidencyCounter_MASK 0xffff0000 + +/// D0F0xBC_x1F248 +typedef union { + struct { ///< + UINT32 HysteresisUp:8 ; ///< + UINT32 HysteresisDown:8 ; ///< + UINT32 ResidencyCounter:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F248_STRUCT; + +// **** D0F0xBC_x1F250 Register Definition **** +// Address +#define D0F0xBC_x1F250_ADDRESS 0x1f250 + +// Type +#define D0F0xBC_x1F250_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F250_ActivityThreshold_OFFSET 0 +#define D0F0xBC_x1F250_ActivityThreshold_WIDTH 8 +#define D0F0xBC_x1F250_ActivityThreshold_MASK 0xff +#define D0F0xBC_x1F250_Reserved_31_8_OFFSET 8 +#define D0F0xBC_x1F250_Reserved_31_8_WIDTH 24 +#define D0F0xBC_x1F250_Reserved_31_8_MASK 0xffffff00 + +/// D0F0xBC_x1F250 +typedef union { + struct { ///< + UINT32 ActivityThreshold:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F250_STRUCT; + +// **** D0F0xBC_x1F260 Register Definition **** +// Address +#define D0F0xBC_x1F260_ADDRESS 0x1f260 + +// Type +#define D0F0xBC_x1F260_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F260_StateValid_OFFSET 0 +#define D0F0xBC_x1F260_StateValid_WIDTH 1 +#define D0F0xBC_x1F260_StateValid_MASK 0x1 +#define D0F0xBC_x1F260_Reserved_7_1_OFFSET 1 +#define D0F0xBC_x1F260_Reserved_7_1_WIDTH 7 +#define D0F0xBC_x1F260_Reserved_7_1_MASK 0xfe +#define D0F0xBC_x1F260_LclkDivider_OFFSET 8 +#define D0F0xBC_x1F260_LclkDivider_WIDTH 8 +#define D0F0xBC_x1F260_LclkDivider_MASK 0xff00 +#define D0F0xBC_x1F260_VID_OFFSET 16 +#define D0F0xBC_x1F260_VID_WIDTH 8 +#define D0F0xBC_x1F260_VID_MASK 0xff0000 +#define D0F0xBC_x1F260_LowVoltageReqThreshold_OFFSET 24 +#define D0F0xBC_x1F260_LowVoltageReqThreshold_WIDTH 8 +#define D0F0xBC_x1F260_LowVoltageReqThreshold_MASK 0xff000000 + +/// D0F0xBC_x1F260 +typedef union { + struct { ///< + UINT32 StateValid:1 ; ///< + UINT32 Reserved_7_1:7 ; ///< + UINT32 LclkDivider:8 ; ///< + UINT32 VID:8 ; ///< + UINT32 LowVoltageReqThreshold:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F260_STRUCT; + +// **** D0F0xBC_x1F268 Register Definition **** +// Address +#define D0F0xBC_x1F268_ADDRESS 0x1f268 + +// Type +#define D0F0xBC_x1F268_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F268_HysteresisUp_OFFSET 0 +#define D0F0xBC_x1F268_HysteresisUp_WIDTH 8 +#define D0F0xBC_x1F268_HysteresisUp_MASK 0xff +#define D0F0xBC_x1F268_HysteresisDown_OFFSET 8 +#define D0F0xBC_x1F268_HysteresisDown_WIDTH 8 +#define D0F0xBC_x1F268_HysteresisDown_MASK 0xff00 +#define D0F0xBC_x1F268_ResidencyCounter_OFFSET 16 +#define D0F0xBC_x1F268_ResidencyCounter_WIDTH 16 +#define D0F0xBC_x1F268_ResidencyCounter_MASK 0xffff0000 + +/// D0F0xBC_x1F268 +typedef union { + struct { ///< + UINT32 HysteresisUp:8 ; ///< + UINT32 HysteresisDown:8 ; ///< + UINT32 ResidencyCounter:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F268_STRUCT; + +// **** D0F0xBC_x1F270 Register Definition **** +// Address +#define D0F0xBC_x1F270_ADDRESS 0x1f270 + +// Type +#define D0F0xBC_x1F270_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F270_ActivityThreshold_OFFSET 0 +#define D0F0xBC_x1F270_ActivityThreshold_WIDTH 8 +#define D0F0xBC_x1F270_ActivityThreshold_MASK 0xff +#define D0F0xBC_x1F270_Reserved_31_8_OFFSET 8 +#define D0F0xBC_x1F270_Reserved_31_8_WIDTH 24 +#define D0F0xBC_x1F270_Reserved_31_8_MASK 0xffffff00 + +/// D0F0xBC_x1F270 +typedef union { + struct { ///< + UINT32 ActivityThreshold:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F270_STRUCT; + +// **** D0F0xBC_x1F280 Register Definition **** +// Address +#define D0F0xBC_x1F280_ADDRESS 0x1f280 + +// Type +#define D0F0xBC_x1F280_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F280_StateValid_OFFSET 0 +#define D0F0xBC_x1F280_StateValid_WIDTH 1 +#define D0F0xBC_x1F280_StateValid_MASK 0x1 +#define D0F0xBC_x1F280_Reserved_7_1_OFFSET 1 +#define D0F0xBC_x1F280_Reserved_7_1_WIDTH 7 +#define D0F0xBC_x1F280_Reserved_7_1_MASK 0xfe +#define D0F0xBC_x1F280_LclkDivider_OFFSET 8 +#define D0F0xBC_x1F280_LclkDivider_WIDTH 8 +#define D0F0xBC_x1F280_LclkDivider_MASK 0xff00 +#define D0F0xBC_x1F280_VID_OFFSET 16 +#define D0F0xBC_x1F280_VID_WIDTH 8 +#define D0F0xBC_x1F280_VID_MASK 0xff0000 +#define D0F0xBC_x1F280_LowVoltageReqThreshold_OFFSET 24 +#define D0F0xBC_x1F280_LowVoltageReqThreshold_WIDTH 8 +#define D0F0xBC_x1F280_LowVoltageReqThreshold_MASK 0xff000000 + +/// D0F0xBC_x1F280 +typedef union { + struct { ///< + UINT32 StateValid:1 ; ///< + UINT32 Reserved_7_1:7 ; ///< + UINT32 LclkDivider:8 ; ///< + UINT32 VID:8 ; ///< + UINT32 LowVoltageReqThreshold:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F280_STRUCT; + +// **** D0F0xBC_x1F288 Register Definition **** +// Address +#define D0F0xBC_x1F288_ADDRESS 0x1f288 + +// Type +#define D0F0xBC_x1F288_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F288_HysteresisUp_OFFSET 0 +#define D0F0xBC_x1F288_HysteresisUp_WIDTH 8 +#define D0F0xBC_x1F288_HysteresisUp_MASK 0xff +#define D0F0xBC_x1F288_HysteresisDown_OFFSET 8 +#define D0F0xBC_x1F288_HysteresisDown_WIDTH 8 +#define D0F0xBC_x1F288_HysteresisDown_MASK 0xff00 +#define D0F0xBC_x1F288_ResidencyCounter_OFFSET 16 +#define D0F0xBC_x1F288_ResidencyCounter_WIDTH 16 +#define D0F0xBC_x1F288_ResidencyCounter_MASK 0xffff0000 + +/// D0F0xBC_x1F288 +typedef union { + struct { ///< + UINT32 HysteresisUp:8 ; ///< + UINT32 HysteresisDown:8 ; ///< + UINT32 ResidencyCounter:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F288_STRUCT; + +// **** D0F0xBC_x1F290 Register Definition **** +// Address +#define D0F0xBC_x1F290_ADDRESS 0x1f290 + +// Type +#define D0F0xBC_x1F290_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F290_ActivityThreshold_OFFSET 0 +#define D0F0xBC_x1F290_ActivityThreshold_WIDTH 8 +#define D0F0xBC_x1F290_ActivityThreshold_MASK 0xff +#define D0F0xBC_x1F290_Reserved_31_8_OFFSET 8 +#define D0F0xBC_x1F290_Reserved_31_8_WIDTH 24 +#define D0F0xBC_x1F290_Reserved_31_8_MASK 0xffffff00 + +/// D0F0xBC_x1F290 +typedef union { + struct { ///< + UINT32 ActivityThreshold:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F290_STRUCT; + +// **** D0F0xBC_x1F2A0 Register Definition **** +// Address +#define D0F0xBC_x1F2A0_ADDRESS 0x1f2a0 + +// Type +#define D0F0xBC_x1F2A0_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F2A0_StateValid_OFFSET 0 +#define D0F0xBC_x1F2A0_StateValid_WIDTH 1 +#define D0F0xBC_x1F2A0_StateValid_MASK 0x1 +#define D0F0xBC_x1F2A0_Reserved_7_1_OFFSET 1 +#define D0F0xBC_x1F2A0_Reserved_7_1_WIDTH 7 +#define D0F0xBC_x1F2A0_Reserved_7_1_MASK 0xfe +#define D0F0xBC_x1F2A0_LclkDivider_OFFSET 8 +#define D0F0xBC_x1F2A0_LclkDivider_WIDTH 8 +#define D0F0xBC_x1F2A0_LclkDivider_MASK 0xff00 +#define D0F0xBC_x1F2A0_VID_OFFSET 16 +#define D0F0xBC_x1F2A0_VID_WIDTH 8 +#define D0F0xBC_x1F2A0_VID_MASK 0xff0000 +#define D0F0xBC_x1F2A0_LowVoltageReqThreshold_OFFSET 24 +#define D0F0xBC_x1F2A0_LowVoltageReqThreshold_WIDTH 8 +#define D0F0xBC_x1F2A0_LowVoltageReqThreshold_MASK 0xff000000 + +/// D0F0xBC_x1F2A0 +typedef union { + struct { ///< + UINT32 StateValid:1 ; ///< + UINT32 Reserved_7_1:7 ; ///< + UINT32 LclkDivider:8 ; ///< + UINT32 VID:8 ; ///< + UINT32 LowVoltageReqThreshold:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F2A0_STRUCT; + +// **** D0F0xBC_x1F2A8 Register Definition **** +// Address +#define D0F0xBC_x1F2A8_ADDRESS 0x1f2a8 + +// Type +#define D0F0xBC_x1F2A8_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F2A8_HysteresisUp_OFFSET 0 +#define D0F0xBC_x1F2A8_HysteresisUp_WIDTH 8 +#define D0F0xBC_x1F2A8_HysteresisUp_MASK 0xff +#define D0F0xBC_x1F2A8_HysteresisDown_OFFSET 8 +#define D0F0xBC_x1F2A8_HysteresisDown_WIDTH 8 +#define D0F0xBC_x1F2A8_HysteresisDown_MASK 0xff00 +#define D0F0xBC_x1F2A8_ResidencyCounter_OFFSET 16 +#define D0F0xBC_x1F2A8_ResidencyCounter_WIDTH 16 +#define D0F0xBC_x1F2A8_ResidencyCounter_MASK 0xffff0000 + +/// D0F0xBC_x1F2A8 +typedef union { + struct { ///< + UINT32 HysteresisUp:8 ; ///< + UINT32 HysteresisDown:8 ; ///< + UINT32 ResidencyCounter:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F2A8_STRUCT; + +// **** D0F0xBC_x1F2B0 Register Definition **** +// Address +#define D0F0xBC_x1F2B0_ADDRESS 0x1f2b0 + +// Type +#define D0F0xBC_x1F2B0_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F2B0_ActivityThreshold_OFFSET 0 +#define D0F0xBC_x1F2B0_ActivityThreshold_WIDTH 8 +#define D0F0xBC_x1F2B0_ActivityThreshold_MASK 0xff +#define D0F0xBC_x1F2B0_Reserved_31_8_OFFSET 8 +#define D0F0xBC_x1F2B0_Reserved_31_8_WIDTH 24 +#define D0F0xBC_x1F2B0_Reserved_31_8_MASK 0xffffff00 + +/// D0F0xBC_x1F2B0 +typedef union { + struct { ///< + UINT32 ActivityThreshold:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F2B0_STRUCT; + +// **** D0F0xBC_x1F2C0 Register Definition **** +// Address +#define D0F0xBC_x1F2C0_ADDRESS 0x1f2c0 + +// Type +#define D0F0xBC_x1F2C0_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F2C0_StateValid_OFFSET 0 +#define D0F0xBC_x1F2C0_StateValid_WIDTH 1 +#define D0F0xBC_x1F2C0_StateValid_MASK 0x1 +#define D0F0xBC_x1F2C0_Reserved_7_1_OFFSET 1 +#define D0F0xBC_x1F2C0_Reserved_7_1_WIDTH 7 +#define D0F0xBC_x1F2C0_Reserved_7_1_MASK 0xfe +#define D0F0xBC_x1F2C0_LclkDivider_OFFSET 8 +#define D0F0xBC_x1F2C0_LclkDivider_WIDTH 8 +#define D0F0xBC_x1F2C0_LclkDivider_MASK 0xff00 +#define D0F0xBC_x1F2C0_VID_OFFSET 16 +#define D0F0xBC_x1F2C0_VID_WIDTH 8 +#define D0F0xBC_x1F2C0_VID_MASK 0xff0000 +#define D0F0xBC_x1F2C0_LowVoltageReqThreshold_OFFSET 24 +#define D0F0xBC_x1F2C0_LowVoltageReqThreshold_WIDTH 8 +#define D0F0xBC_x1F2C0_LowVoltageReqThreshold_MASK 0xff000000 + +/// D0F0xBC_x1F2C0 +typedef union { + struct { ///< + UINT32 StateValid:1 ; ///< + UINT32 Reserved_7_1:7 ; ///< + UINT32 LclkDivider:8 ; ///< + UINT32 VID:8 ; ///< + UINT32 LowVoltageReqThreshold:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F2C0_STRUCT; + +// **** D0F0xBC_x1F2C8 Register Definition **** +// Address +#define D0F0xBC_x1F2C8_ADDRESS 0x1f2c8 + +// Type +#define D0F0xBC_x1F2C8_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F2C8_HysteresisUp_OFFSET 0 +#define D0F0xBC_x1F2C8_HysteresisUp_WIDTH 8 +#define D0F0xBC_x1F2C8_HysteresisUp_MASK 0xff +#define D0F0xBC_x1F2C8_HysteresisDown_OFFSET 8 +#define D0F0xBC_x1F2C8_HysteresisDown_WIDTH 8 +#define D0F0xBC_x1F2C8_HysteresisDown_MASK 0xff00 +#define D0F0xBC_x1F2C8_ResidencyCounter_OFFSET 16 +#define D0F0xBC_x1F2C8_ResidencyCounter_WIDTH 16 +#define D0F0xBC_x1F2C8_ResidencyCounter_MASK 0xffff0000 + +/// D0F0xBC_x1F2C8 +typedef union { + struct { ///< + UINT32 HysteresisUp:8 ; ///< + UINT32 HysteresisDown:8 ; ///< + UINT32 ResidencyCounter:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F2C8_STRUCT; + +// **** D0F0xBC_x1F2D0 Register Definition **** +// Address +#define D0F0xBC_x1F2D0_ADDRESS 0x1f2d0 + +// Type +#define D0F0xBC_x1F2D0_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F2D0_ActivityThreshold_OFFSET 0 +#define D0F0xBC_x1F2D0_ActivityThreshold_WIDTH 8 +#define D0F0xBC_x1F2D0_ActivityThreshold_MASK 0xff +#define D0F0xBC_x1F2D0_Reserved_31_8_OFFSET 8 +#define D0F0xBC_x1F2D0_Reserved_31_8_WIDTH 24 +#define D0F0xBC_x1F2D0_Reserved_31_8_MASK 0xffffff00 + +/// D0F0xBC_x1F2D0 +typedef union { + struct { ///< + UINT32 ActivityThreshold:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F2D0_STRUCT; + +// **** D0F0xBC_x1F2E0 Register Definition **** +// Address +#define D0F0xBC_x1F2E0_ADDRESS 0x1f2e0 + +// Type +#define D0F0xBC_x1F2E0_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F2E0_StateValid_OFFSET 0 +#define D0F0xBC_x1F2E0_StateValid_WIDTH 1 +#define D0F0xBC_x1F2E0_StateValid_MASK 0x1 +#define D0F0xBC_x1F2E0_Reserved_7_1_OFFSET 1 +#define D0F0xBC_x1F2E0_Reserved_7_1_WIDTH 7 +#define D0F0xBC_x1F2E0_Reserved_7_1_MASK 0xfe +#define D0F0xBC_x1F2E0_LclkDivider_OFFSET 8 +#define D0F0xBC_x1F2E0_LclkDivider_WIDTH 8 +#define D0F0xBC_x1F2E0_LclkDivider_MASK 0xff00 +#define D0F0xBC_x1F2E0_VID_OFFSET 16 +#define D0F0xBC_x1F2E0_VID_WIDTH 8 +#define D0F0xBC_x1F2E0_VID_MASK 0xff0000 +#define D0F0xBC_x1F2E0_LowVoltageReqThreshold_OFFSET 24 +#define D0F0xBC_x1F2E0_LowVoltageReqThreshold_WIDTH 8 +#define D0F0xBC_x1F2E0_LowVoltageReqThreshold_MASK 0xff000000 + +/// D0F0xBC_x1F2E0 +typedef union { + struct { ///< + UINT32 StateValid:1 ; ///< + UINT32 Reserved_7_1:7 ; ///< + UINT32 LclkDivider:8 ; ///< + UINT32 VID:8 ; ///< + UINT32 LowVoltageReqThreshold:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F2E0_STRUCT; + +// **** D0F0xBC_x1F2E8 Register Definition **** +// Address +#define D0F0xBC_x1F2E8_ADDRESS 0x1f2e8 + +// Type +#define D0F0xBC_x1F2E8_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F2E8_HysteresisUp_OFFSET 0 +#define D0F0xBC_x1F2E8_HysteresisUp_WIDTH 8 +#define D0F0xBC_x1F2E8_HysteresisUp_MASK 0xff +#define D0F0xBC_x1F2E8_HysteresisDown_OFFSET 8 +#define D0F0xBC_x1F2E8_HysteresisDown_WIDTH 8 +#define D0F0xBC_x1F2E8_HysteresisDown_MASK 0xff00 +#define D0F0xBC_x1F2E8_ResidencyCounter_OFFSET 16 +#define D0F0xBC_x1F2E8_ResidencyCounter_WIDTH 16 +#define D0F0xBC_x1F2E8_ResidencyCounter_MASK 0xffff0000 + +/// D0F0xBC_x1F2E8 +typedef union { + struct { ///< + UINT32 HysteresisUp:8 ; ///< + UINT32 HysteresisDown:8 ; ///< + UINT32 ResidencyCounter:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F2E8_STRUCT; + +// **** D0F0xBC_x1F2F0 Register Definition **** +// Address +#define D0F0xBC_x1F2F0_ADDRESS 0x1f2f0 + +// Type +#define D0F0xBC_x1F2F0_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F2F0_ActivityThreshold_OFFSET 0 +#define D0F0xBC_x1F2F0_ActivityThreshold_WIDTH 8 +#define D0F0xBC_x1F2F0_ActivityThreshold_MASK 0xff +#define D0F0xBC_x1F2F0_Reserved_31_8_OFFSET 8 +#define D0F0xBC_x1F2F0_Reserved_31_8_WIDTH 24 +#define D0F0xBC_x1F2F0_Reserved_31_8_MASK 0xffffff00 + +/// D0F0xBC_x1F2F0 +typedef union { + struct { ///< + UINT32 ActivityThreshold:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F2F0_STRUCT; + +// **** D0F0xBC_x1F300 Register Definition **** +// Address +#define D0F0xBC_x1F300_ADDRESS 0x1f300 + +// Type +#define D0F0xBC_x1F300_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F300_LclkDpmEn_OFFSET 0 +#define D0F0xBC_x1F300_LclkDpmEn_WIDTH 1 +#define D0F0xBC_x1F300_LclkDpmEn_MASK 0x1 +#define D0F0xBC_x1F300_Reserved_7_1_OFFSET 1 +#define D0F0xBC_x1F300_Reserved_7_1_WIDTH 7 +#define D0F0xBC_x1F300_Reserved_7_1_MASK 0xfe +#define D0F0xBC_x1F300_LclkDpmType_OFFSET 8 +#define D0F0xBC_x1F300_LclkDpmType_WIDTH 1 +#define D0F0xBC_x1F300_LclkDpmType_MASK 0x100 +#define D0F0xBC_x1F300_Reserved_15_9_OFFSET 9 +#define D0F0xBC_x1F300_Reserved_15_9_WIDTH 7 +#define D0F0xBC_x1F300_Reserved_15_9_MASK 0xfe00 +#define D0F0xBC_x1F300_LclkDpmBootState_OFFSET 16 +#define D0F0xBC_x1F300_LclkDpmBootState_WIDTH 8 +#define D0F0xBC_x1F300_LclkDpmBootState_MASK 0xff0000 +#define D0F0xBC_x1F300_VoltageChgEn_OFFSET 24 +#define D0F0xBC_x1F300_VoltageChgEn_WIDTH 1 +#define D0F0xBC_x1F300_VoltageChgEn_MASK 0x1000000 +#define D0F0xBC_x1F300_Reserved_31_25_OFFSET 25 +#define D0F0xBC_x1F300_Reserved_31_25_WIDTH 7 +#define D0F0xBC_x1F300_Reserved_31_25_MASK 0xfe000000 + +/// D0F0xBC_x1F300 +typedef union { + struct { ///< + UINT32 LclkDpmEn:1 ; ///< + UINT32 Reserved_7_1:7 ; ///< + UINT32 LclkDpmType:1 ; ///< + UINT32 Reserved_15_9:7 ; ///< + UINT32 LclkDpmBootState:8 ; ///< + UINT32 VoltageChgEn:1 ; ///< + UINT32 Reserved_31_25:7 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F300_STRUCT; + +// **** D0F0xBC_x1F308 Register Definition **** +// Address +#define D0F0xBC_x1F308_ADDRESS 0x1f308 + +// Type +#define D0F0xBC_x1F308_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F308_LclkThermalThrottlingEn_OFFSET 0 +#define D0F0xBC_x1F308_LclkThermalThrottlingEn_WIDTH 1 +#define D0F0xBC_x1F308_LclkThermalThrottlingEn_MASK 0x1 +#define D0F0xBC_x1F308_Reserved_7_1_OFFSET 1 +#define D0F0xBC_x1F308_Reserved_7_1_WIDTH 7 +#define D0F0xBC_x1F308_Reserved_7_1_MASK 0xfe +#define D0F0xBC_x1F308_TemperatureSel_OFFSET 8 +#define D0F0xBC_x1F308_TemperatureSel_WIDTH 1 +#define D0F0xBC_x1F308_TemperatureSel_MASK 0x100 +#define D0F0xBC_x1F308_Reserved_15_9_OFFSET 9 +#define D0F0xBC_x1F308_Reserved_15_9_WIDTH 7 +#define D0F0xBC_x1F308_Reserved_15_9_MASK 0xfe00 +#define D0F0xBC_x1F308_LclkTtMode_OFFSET 16 +#define D0F0xBC_x1F308_LclkTtMode_WIDTH 3 +#define D0F0xBC_x1F308_LclkTtMode_MASK 0x70000 + +/// D0F0xBC_x1F308 +typedef union { + struct { ///< + UINT32 LclkThermalThrottlingEn:1 ; ///< + UINT32 Reserved_7_1:7 ; ///< + UINT32 TemperatureSel:1 ; ///< + UINT32 Reserved_15_9:7 ; ///< + UINT32 LclkTtMode:3 ; ///< + UINT32 :13; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F308_STRUCT; + +// **** D0F0xBC_x1F30C Register Definition **** +// Address +#define D0F0xBC_x1F30C_ADDRESS 0x1f30c + +// Type +#define D0F0xBC_x1F30C_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F30C_LowThreshold_OFFSET 0 +#define D0F0xBC_x1F30C_LowThreshold_WIDTH 16 +#define D0F0xBC_x1F30C_LowThreshold_MASK 0xffff +#define D0F0xBC_x1F30C_HighThreshold_OFFSET 16 +#define D0F0xBC_x1F30C_HighThreshold_WIDTH 16 +#define D0F0xBC_x1F30C_HighThreshold_MASK 0xffff0000 + +/// D0F0xBC_x1F30C +typedef union { + struct { ///< + UINT32 LowThreshold:16; ///< + UINT32 HighThreshold:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F30C_STRUCT; + +// **** D0F0xBC_x1F380 Register Definition **** +// Address +#define D0F0xBC_x1F380_ADDRESS 0x1f380 + +// Type +#define D0F0xBC_x1F380_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F380_InterruptsEnabled_OFFSET 0 +#define D0F0xBC_x1F380_InterruptsEnabled_WIDTH 1 +#define D0F0xBC_x1F380_InterruptsEnabled_MASK 0x1 +#define D0F0xBC_x1F380_Reserved_23_1_OFFSET 1 +#define D0F0xBC_x1F380_Reserved_23_1_WIDTH 23 +#define D0F0xBC_x1F380_Reserved_23_1_MASK 0xfffffe +#define D0F0xBC_x1F380_TestCount_OFFSET 24 +#define D0F0xBC_x1F380_TestCount_WIDTH 8 +#define D0F0xBC_x1F380_TestCount_MASK 0xff000000 + +/// D0F0xBC_x1F380 +typedef union { + struct { ///< + UINT32 InterruptsEnabled:1 ; ///< + UINT32 Reserved_23_1:23; ///< + UINT32 TestCount:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F380_STRUCT; + +// **** D0F0xBC_x1F384 Register Definition **** +// Address +#define D0F0xBC_x1F384_ADDRESS 0x1f384 + +// Type +#define D0F0xBC_x1F384_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F384_FirmwareVid_OFFSET 0 +#define D0F0xBC_x1F384_FirmwareVid_WIDTH 8 +#define D0F0xBC_x1F384_FirmwareVid_MASK 0xff +#define D0F0xBC_x1F384_Reserved_31_8_OFFSET 8 +#define D0F0xBC_x1F384_Reserved_31_8_WIDTH 24 +#define D0F0xBC_x1F384_Reserved_31_8_MASK 0xffffff00 + +/// D0F0xBC_x1F384 +typedef union { + struct { ///< + UINT32 FirmwareVid:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F384_STRUCT; + +// **** D0F0xBC_x1F388 Register Definition **** +// Address +#define D0F0xBC_x1F388_ADDRESS 0x1f388 + +// Type +#define D0F0xBC_x1F388_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F388_CsrAddr_OFFSET 0 +#define D0F0xBC_x1F388_CsrAddr_WIDTH 6 +#define D0F0xBC_x1F388_CsrAddr_MASK 0x3f +#define D0F0xBC_x1F388_TcenId_OFFSET 6 +#define D0F0xBC_x1F388_TcenId_WIDTH 4 +#define D0F0xBC_x1F388_TcenId_MASK 0x3c0 +#define D0F0xBC_x1F388_Reserved_31_10_OFFSET 10 +#define D0F0xBC_x1F388_Reserved_31_10_WIDTH 22 +#define D0F0xBC_x1F388_Reserved_31_10_MASK 0xfffffc00 + +/// D0F0xBC_x1F388 +typedef union { + struct { ///< + UINT32 CsrAddr:6 ; ///< + UINT32 TcenId:4 ; ///< + UINT32 Reserved_31_10:22; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F388_STRUCT; + +// **** D0F0xBC_x1F39C Register Definition **** +// Address +#define D0F0xBC_x1F39C_ADDRESS 0x1f39c + +// Type +#define D0F0xBC_x1F39C_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F39C_Rx_OFFSET 0 +#define D0F0xBC_x1F39C_Rx_WIDTH 1 +#define D0F0xBC_x1F39C_Rx_MASK 0x1 +#define D0F0xBC_x1F39C_Tx_OFFSET 1 +#define D0F0xBC_x1F39C_Tx_WIDTH 1 +#define D0F0xBC_x1F39C_Tx_MASK 0x2 +#define D0F0xBC_x1F39C_Core_OFFSET 2 +#define D0F0xBC_x1F39C_Core_WIDTH 1 +#define D0F0xBC_x1F39C_Core_MASK 0x4 +#define D0F0xBC_x1F39C_SkipPhy_OFFSET 3 +#define D0F0xBC_x1F39C_SkipPhy_WIDTH 1 +#define D0F0xBC_x1F39C_SkipPhy_MASK 0x8 +#define D0F0xBC_x1F39C_SkipCore_OFFSET 4 +#define D0F0xBC_x1F39C_SkipCore_WIDTH 1 +#define D0F0xBC_x1F39C_SkipCore_MASK 0x10 +#define D0F0xBC_x1F39C_Reserved_15_5_OFFSET 5 +#define D0F0xBC_x1F39C_Reserved_15_5_WIDTH 11 +#define D0F0xBC_x1F39C_Reserved_15_5_MASK 0xffe0 +#define D0F0xBC_x1F39C_LowerLaneID_OFFSET 16 +#define D0F0xBC_x1F39C_LowerLaneID_WIDTH 8 +#define D0F0xBC_x1F39C_LowerLaneID_MASK 0xff0000 +#define D0F0xBC_x1F39C_UpperLaneID_OFFSET 24 +#define D0F0xBC_x1F39C_UpperLaneID_WIDTH 8 +#define D0F0xBC_x1F39C_UpperLaneID_MASK 0xff000000 + +/// D0F0xBC_x1F39C +typedef union { + struct { ///< + UINT32 Rx:1 ; ///< + UINT32 Tx:1 ; ///< + UINT32 Core:1 ; ///< + UINT32 SkipPhy:1 ; ///< + UINT32 SkipCore:1 ; ///< + UINT32 Reserved_15_5:11; ///< + UINT32 LowerLaneID:8 ; ///< + UINT32 UpperLaneID:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F39C_STRUCT; + +// **** D0F0xBC_x1F3D8 Register Definition **** +// Address +#define D0F0xBC_x1F3D8_ADDRESS 0x1f3d8 + +// Type +#define D0F0xBC_x1F3D8_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F3D8_LoadLineTrim3_OFFSET 0 +#define D0F0xBC_x1F3D8_LoadLineTrim3_WIDTH 8 +#define D0F0xBC_x1F3D8_LoadLineTrim3_MASK 0xff +#define D0F0xBC_x1F3D8_LoadLineTrim2_OFFSET 8 +#define D0F0xBC_x1F3D8_LoadLineTrim2_WIDTH 8 +#define D0F0xBC_x1F3D8_LoadLineTrim2_MASK 0xff00 +#define D0F0xBC_x1F3D8_LoadLineTrim1_OFFSET 16 +#define D0F0xBC_x1F3D8_LoadLineTrim1_WIDTH 8 +#define D0F0xBC_x1F3D8_LoadLineTrim1_MASK 0xff0000 +#define D0F0xBC_x1F3D8_LoadLineTrim0_OFFSET 24 +#define D0F0xBC_x1F3D8_LoadLineTrim0_WIDTH 8 +#define D0F0xBC_x1F3D8_LoadLineTrim0_MASK 0xff000000 + +/// D0F0xBC_x1F3D8 +typedef union { + struct { ///< + UINT32 LoadLineTrim3:8 ; ///< + UINT32 LoadLineTrim2:8 ; ///< + UINT32 LoadLineTrim1:8 ; ///< + UINT32 LoadLineTrim0:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F3D8_STRUCT; + +// **** D0F0xBC_x1F3DC Register Definition **** +// Address +#define D0F0xBC_x1F3DC_ADDRESS 0x1f3dc + +// Type +#define D0F0xBC_x1F3DC_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F3DC_LoadLineTrim7_OFFSET 0 +#define D0F0xBC_x1F3DC_LoadLineTrim7_WIDTH 8 +#define D0F0xBC_x1F3DC_LoadLineTrim7_MASK 0xff +#define D0F0xBC_x1F3DC_LoadLineTrim6_OFFSET 8 +#define D0F0xBC_x1F3DC_LoadLineTrim6_WIDTH 8 +#define D0F0xBC_x1F3DC_LoadLineTrim6_MASK 0xff00 +#define D0F0xBC_x1F3DC_LoadLineTrim5_OFFSET 16 +#define D0F0xBC_x1F3DC_LoadLineTrim5_WIDTH 8 +#define D0F0xBC_x1F3DC_LoadLineTrim5_MASK 0xff0000 +#define D0F0xBC_x1F3DC_LoadLineTrim4_OFFSET 24 +#define D0F0xBC_x1F3DC_LoadLineTrim4_WIDTH 8 +#define D0F0xBC_x1F3DC_LoadLineTrim4_MASK 0xff000000 + +/// D0F0xBC_x1F3DC +typedef union { + struct { ///< + UINT32 LoadLineTrim7:8 ; ///< + UINT32 LoadLineTrim6:8 ; ///< + UINT32 LoadLineTrim5:8 ; ///< + UINT32 LoadLineTrim4:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F3DC_STRUCT; + +// **** D0F0xBC_x1F3F8 Register Definition **** +// Address +#define D0F0xBC_x1F3F8_ADDRESS 0x1f3f8 + +// Type +#define D0F0xBC_x1F3F8_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F3F8_SviInitLoadLineVdd_OFFSET 0 +#define D0F0xBC_x1F3F8_SviInitLoadLineVdd_WIDTH 8 +#define D0F0xBC_x1F3F8_SviInitLoadLineVdd_MASK 0xff +#define D0F0xBC_x1F3F8_SviInitLoadLineVddNB_OFFSET 8 +#define D0F0xBC_x1F3F8_SviInitLoadLineVddNB_WIDTH 8 +#define D0F0xBC_x1F3F8_SviInitLoadLineVddNB_MASK 0xff00 +#define D0F0xBC_x1F3F8_SviTrimValueVdd_OFFSET 16 +#define D0F0xBC_x1F3F8_SviTrimValueVdd_WIDTH 8 +#define D0F0xBC_x1F3F8_SviTrimValueVdd_MASK 0xff0000 +#define D0F0xBC_x1F3F8_SviTrimValueVddNB_OFFSET 24 +#define D0F0xBC_x1F3F8_SviTrimValueVddNB_WIDTH 8 +#define D0F0xBC_x1F3F8_SviTrimValueVddNB_MASK 0xff000000 + +/// D0F0xBC_x1F3F8 +typedef union { + struct { ///< + UINT32 SviInitLoadLineVdd:8 ; ///< + UINT32 SviInitLoadLineVddNB:8 ; ///< + UINT32 SviTrimValueVdd:8 ; ///< + UINT32 SviTrimValueVddNB:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F3F8_STRUCT; + +// **** D0F0xBC_x1F3FC Register Definition **** +// Address +#define D0F0xBC_x1F3FC_ADDRESS 0x1f3fc + +// Type +#define D0F0xBC_x1F3FC_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F3FC_SviVidStepBase_OFFSET 0 +#define D0F0xBC_x1F3FC_SviVidStepBase_WIDTH 16 +#define D0F0xBC_x1F3FC_SviVidStepBase_MASK 0xffff +#define D0F0xBC_x1F3FC_SviVidStep_OFFSET 16 +#define D0F0xBC_x1F3FC_SviVidStep_WIDTH 16 +#define D0F0xBC_x1F3FC_SviVidStep_MASK 0xffff0000 + +/// D0F0xBC_x1F3FC +typedef union { + struct { ///< + UINT32 SviVidStepBase:16; ///< + UINT32 SviVidStep:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F3FC_STRUCT; + +// **** D0F0xBC_x1F400 Register Definition **** +// Address +#define D0F0xBC_x1F400_ADDRESS 0x1f400 + +// Type +#define D0F0xBC_x1F400_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F400_SviLoadLineOffsetVdd_OFFSET 0 +#define D0F0xBC_x1F400_SviLoadLineOffsetVdd_WIDTH 8 +#define D0F0xBC_x1F400_SviLoadLineOffsetVdd_MASK 0xff +#define D0F0xBC_x1F400_SviLoadLineOffsetVddNB_OFFSET 8 +#define D0F0xBC_x1F400_SviLoadLineOffsetVddNB_WIDTH 8 +#define D0F0xBC_x1F400_SviLoadLineOffsetVddNB_MASK 0xff00 +#define D0F0xBC_x1F400_PstateMax_OFFSET 16 +#define D0F0xBC_x1F400_PstateMax_WIDTH 8 +#define D0F0xBC_x1F400_PstateMax_MASK 0xff0000 +#define D0F0xBC_x1F400_Reserved_31_24_OFFSET 24 +#define D0F0xBC_x1F400_Reserved_31_24_WIDTH 8 +#define D0F0xBC_x1F400_Reserved_31_24_MASK 0xff000000 + +/// D0F0xBC_x1F400 +typedef union { + struct { ///< + UINT32 SviLoadLineOffsetVdd:8 ; ///< + UINT32 SviLoadLineOffsetVddNB:8 ; ///< + UINT32 PstateMax:8 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F400_STRUCT; + +// **** D0F0xBC_x1F404 Register Definition **** +// Address +#define D0F0xBC_x1F404_ADDRESS 0x1f404 + +// Type +#define D0F0xBC_x1F404_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F404_LoadLineOffset3_OFFSET 0 +#define D0F0xBC_x1F404_LoadLineOffset3_WIDTH 8 +#define D0F0xBC_x1F404_LoadLineOffset3_MASK 0xff +#define D0F0xBC_x1F404_LoadLineOffset2_OFFSET 8 +#define D0F0xBC_x1F404_LoadLineOffset2_WIDTH 8 +#define D0F0xBC_x1F404_LoadLineOffset2_MASK 0xff00 +#define D0F0xBC_x1F404_LoadLineOffset1_OFFSET 16 +#define D0F0xBC_x1F404_LoadLineOffset1_WIDTH 8 +#define D0F0xBC_x1F404_LoadLineOffset1_MASK 0xff0000 +#define D0F0xBC_x1F404_LoadLineOffset0_OFFSET 24 +#define D0F0xBC_x1F404_LoadLineOffset0_WIDTH 8 +#define D0F0xBC_x1F404_LoadLineOffset0_MASK 0xff000000 + +/// D0F0xBC_x1F404 +typedef union { + struct { ///< + UINT32 LoadLineOffset3:8 ; ///< + UINT32 LoadLineOffset2:8 ; ///< + UINT32 LoadLineOffset1:8 ; ///< + UINT32 LoadLineOffset0:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F404_STRUCT; + +// **** D0F0xBC_x1F428 Register Definition **** +// Address +#define D0F0xBC_x1F428_ADDRESS 0x1f428 + +// Type +#define D0F0xBC_x1F428_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F428_EnableVpcAccumulators_OFFSET 0 +#define D0F0xBC_x1F428_EnableVpcAccumulators_WIDTH 1 +#define D0F0xBC_x1F428_EnableVpcAccumulators_MASK 0x1 +#define D0F0xBC_x1F428_EnableBapm_OFFSET 1 +#define D0F0xBC_x1F428_EnableBapm_WIDTH 1 +#define D0F0xBC_x1F428_EnableBapm_MASK 0x2 +#define D0F0xBC_x1F428_EnableTdcLimit_OFFSET 2 +#define D0F0xBC_x1F428_EnableTdcLimit_WIDTH 1 +#define D0F0xBC_x1F428_EnableTdcLimit_MASK 0x4 +#define D0F0xBC_x1F428_EnableLpmx_OFFSET 3 +#define D0F0xBC_x1F428_EnableLpmx_WIDTH 1 +#define D0F0xBC_x1F428_EnableLpmx_MASK 0x8 +#define D0F0xBC_x1F428_EnableHtcLimit_OFFSET 4 +#define D0F0xBC_x1F428_EnableHtcLimit_WIDTH 1 +#define D0F0xBC_x1F428_EnableHtcLimit_MASK 0x10 +#define D0F0xBC_x1F428_EnableNbDpm_OFFSET 5 +#define D0F0xBC_x1F428_EnableNbDpm_WIDTH 1 +#define D0F0xBC_x1F428_EnableNbDpm_MASK 0x20 +#define D0F0xBC_x1F428_EnableLoadline_OFFSET 6 +#define D0F0xBC_x1F428_EnableLoadline_WIDTH 1 +#define D0F0xBC_x1F428_EnableLoadline_MASK 0x40 +#define D0F0xBC_x1F428_Reserved_15_7_OFFSET 7 +#define D0F0xBC_x1F428_Reserved_15_7_WIDTH 9 +#define D0F0xBC_x1F428_Reserved_15_7_MASK 0xff80 +#define D0F0xBC_x1F428_Reserved_23_20_OFFSET 20 +#define D0F0xBC_x1F428_Reserved_23_20_WIDTH 4 +#define D0F0xBC_x1F428_Reserved_23_20_MASK 0xf00000 +#define D0F0xBC_x1F428_PstateAllCpusIdle_OFFSET 24 +#define D0F0xBC_x1F428_PstateAllCpusIdle_WIDTH 3 +#define D0F0xBC_x1F428_PstateAllCpusIdle_MASK 0x7000000 +#define D0F0xBC_x1F428_NbPstateAllCpusIdle_OFFSET 27 +#define D0F0xBC_x1F428_NbPstateAllCpusIdle_WIDTH 1 +#define D0F0xBC_x1F428_NbPstateAllCpusIdle_MASK 0x8000000 +#define D0F0xBC_x1F428_BapmCoeffOverride_OFFSET 28 +#define D0F0xBC_x1F428_BapmCoeffOverride_WIDTH 1 +#define D0F0xBC_x1F428_BapmCoeffOverride_MASK 0x10000000 +#define D0F0xBC_x1F428_SviMode_OFFSET 29 +#define D0F0xBC_x1F428_SviMode_WIDTH 1 +#define D0F0xBC_x1F428_SviMode_MASK 0x20000000 +#define D0F0xBC_x1F428_Reserved_31_30_OFFSET 30 +#define D0F0xBC_x1F428_Reserved_31_30_WIDTH 2 +#define D0F0xBC_x1F428_Reserved_31_30_MASK 0xc0000000 + +/// D0F0xBC_x1F428 +typedef union { + struct { ///< + UINT32 EnableVpcAccumulators:1 ; ///< + UINT32 EnableBapm:1 ; ///< + UINT32 EnableTdcLimit:1 ; ///< + UINT32 EnableLpmx:1 ; ///< + UINT32 field_4:1; + UINT32 EnableNbDpm:1 ; ///< + UINT32 EnableLoadline:1 ; ///< + UINT32 Reserved_15_7:9 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 line180 :1 ; ///< + UINT32 Reserved_23_20:4 ; ///< + UINT32 PstateAllCpusIdle:3 ; ///< + UINT32 NbPstateAllCpusIdle:1 ; ///< + UINT32 BapmCoeffOverride:1 ; ///< + UINT32 SviMode:1 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F428_STRUCT; + +// **** D0F0xBC_x1F460 Register Definition **** +// Address +#define D0F0xBC_x1F460_ADDRESS 0x1f460 + +// Type +#define D0F0xBC_x1F460_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F460_LclkDpm_OFFSET 0 +#define D0F0xBC_x1F460_LclkDpm_WIDTH 8 +#define D0F0xBC_x1F460_LclkDpm_MASK 0xff +#define D0F0xBC_x1F460_ThermalCntl_OFFSET 8 +#define D0F0xBC_x1F460_ThermalCntl_WIDTH 8 +#define D0F0xBC_x1F460_ThermalCntl_MASK 0xff00 +#define D0F0xBC_x1F460_VoltageCntl_OFFSET 16 +#define D0F0xBC_x1F460_VoltageCntl_WIDTH 8 +#define D0F0xBC_x1F460_VoltageCntl_MASK 0xff0000 +#define D0F0xBC_x1F460_Loadline_OFFSET 24 +#define D0F0xBC_x1F460_Loadline_WIDTH 8 +#define D0F0xBC_x1F460_Loadline_MASK 0xff000000 + +/// D0F0xBC_x1F460 +typedef union { + struct { ///< + UINT32 LclkDpm:8 ; ///< + UINT32 ThermalCntl:8 ; ///< + UINT32 VoltageCntl:8 ; ///< + UINT32 Loadline:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F460_STRUCT; + +// **** D0F0xBC_x1F464 Register Definition **** +// Address +#define D0F0xBC_x1F464_ADDRESS 0x1f464 + +// Type +#define D0F0xBC_x1F464_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F464_SclkDpm_OFFSET 0 +#define D0F0xBC_x1F464_SclkDpm_WIDTH 8 +#define D0F0xBC_x1F464_SclkDpm_MASK 0xff +#define D0F0xBC_x1F464_StaticSimdPgCntl_OFFSET 8 +#define D0F0xBC_x1F464_StaticSimdPgCntl_WIDTH 8 +#define D0F0xBC_x1F464_StaticSimdPgCntl_MASK 0xff00 +#define D0F0xBC_x1F464_DynSimdPgCntl_OFFSET 16 +#define D0F0xBC_x1F464_DynSimdPgCntl_WIDTH 8 +#define D0F0xBC_x1F464_DynSimdPgCntl_MASK 0xff0000 +#define D0F0xBC_x1F464_TdpCntl_OFFSET 24 +#define D0F0xBC_x1F464_TdpCntl_WIDTH 8 +#define D0F0xBC_x1F464_TdpCntl_MASK 0xff000000 + +/// D0F0xBC_x1F464 +typedef union { + struct { ///< + UINT32 SclkDpm:8 ; ///< + UINT32 StaticSimdPgCntl:8 ; ///< + UINT32 DynSimdPgCntl:8 ; ///< + UINT32 TdpCntl:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F464_STRUCT; + +// **** D0F0xBC_x1F468 Register Definition **** +// Address +#define D0F0xBC_x1F468_ADDRESS 0x1f468 + +// Type +#define D0F0xBC_x1F468_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F468_TimerPeriod_OFFSET 0 +#define D0F0xBC_x1F468_TimerPeriod_WIDTH 32 +#define D0F0xBC_x1F468_TimerPeriod_MASK 0xffffffff + +/// D0F0xBC_x1F468 +typedef union { + struct { ///< + UINT32 TimerPeriod:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F468_STRUCT; + +// **** D0F0xBC_x1F46C Register Definition **** +// Address +#define D0F0xBC_x1F46C_ADDRESS 0x1f46c + +// Type +#define D0F0xBC_x1F46C_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F46C_VpcPeriod_OFFSET 0 +#define D0F0xBC_x1F46C_VpcPeriod_WIDTH 16 +#define D0F0xBC_x1F46C_VpcPeriod_MASK 0xffff +#define D0F0xBC_x1F46C_BapmPeriod_OFFSET 16 +#define D0F0xBC_x1F46C_BapmPeriod_WIDTH 8 +#define D0F0xBC_x1F46C_BapmPeriod_MASK 0xff0000 +#define D0F0xBC_x1F46C_LpmxPeriod_OFFSET 24 +#define D0F0xBC_x1F46C_LpmxPeriod_WIDTH 8 +#define D0F0xBC_x1F46C_LpmxPeriod_MASK 0xff000000 + +/// D0F0xBC_x1F46C +typedef union { + struct { ///< + UINT32 VpcPeriod:16; ///< + UINT32 BapmPeriod:8 ; ///< + UINT32 LpmxPeriod:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F46C_STRUCT; + +// **** D0F0xBC_x1F5F8 Register Definition **** +// Address +#define D0F0xBC_x1F5F8_ADDRESS 0x1f5f8 + +// Type +#define D0F0xBC_x1F5F8_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F5F8_Dpm0PgNbPsLo_OFFSET 0 +#define D0F0xBC_x1F5F8_Dpm0PgNbPsLo_WIDTH 2 +#define D0F0xBC_x1F5F8_Dpm0PgNbPsLo_MASK 0x3 +#define D0F0xBC_x1F5F8_Dpm0PgNbPsHi_OFFSET 2 +#define D0F0xBC_x1F5F8_Dpm0PgNbPsHi_WIDTH 2 +#define D0F0xBC_x1F5F8_Dpm0PgNbPsHi_MASK 0xc +#define D0F0xBC_x1F5F8_DpmXNbPsLo_OFFSET 4 +#define D0F0xBC_x1F5F8_DpmXNbPsLo_WIDTH 2 +#define D0F0xBC_x1F5F8_DpmXNbPsLo_MASK 0x30 +#define D0F0xBC_x1F5F8_DpmXNbPsHi_OFFSET 6 +#define D0F0xBC_x1F5F8_DpmXNbPsHi_WIDTH 2 +#define D0F0xBC_x1F5F8_DpmXNbPsHi_MASK 0xc0 +#define D0F0xBC_x1F5F8_Hysteresis_OFFSET 8 +#define D0F0xBC_x1F5F8_Hysteresis_WIDTH 8 +#define D0F0xBC_x1F5F8_Hysteresis_MASK 0xff00 +#define D0F0xBC_x1F5F8_SkipPG_OFFSET 16 +#define D0F0xBC_x1F5F8_SkipPG_WIDTH 1 +#define D0F0xBC_x1F5F8_SkipPG_MASK 0x10000 +#define D0F0xBC_x1F5F8_SkipDPM0_OFFSET 17 +#define D0F0xBC_x1F5F8_SkipDPM0_WIDTH 1 +#define D0F0xBC_x1F5F8_SkipDPM0_MASK 0x20000 +#define D0F0xBC_x1F5F8_Reserved_21_18_OFFSET 18 +#define D0F0xBC_x1F5F8_Reserved_21_18_WIDTH 4 +#define D0F0xBC_x1F5F8_Reserved_21_18_MASK 0x3c0000 +#define D0F0xBC_x1F5F8_EnableNbPsi1_OFFSET 22 +#define D0F0xBC_x1F5F8_EnableNbPsi1_WIDTH 1 +#define D0F0xBC_x1F5F8_EnableNbPsi1_MASK 0x400000 +#define D0F0xBC_x1F5F8_EnableDpmPstatePoll_OFFSET 23 +#define D0F0xBC_x1F5F8_EnableDpmPstatePoll_WIDTH 1 +#define D0F0xBC_x1F5F8_EnableDpmPstatePoll_MASK 0x800000 +#define D0F0xBC_x1F5F8_Reserved_31_24_OFFSET 24 +#define D0F0xBC_x1F5F8_Reserved_31_24_WIDTH 8 +#define D0F0xBC_x1F5F8_Reserved_31_24_MASK 0xff000000 + +/// D0F0xBC_x1F5F8 +typedef union { + struct { ///< + UINT32 Dpm0PgNbPsLo:2 ; ///< + UINT32 Dpm0PgNbPsHi:2 ; ///< + UINT32 DpmXNbPsLo:2 ; ///< + UINT32 DpmXNbPsHi:2 ; ///< + UINT32 Hysteresis:8 ; ///< + UINT32 SkipPG:1 ; ///< + UINT32 SkipDPM0:1 ; ///< + UINT32 Reserved_21_18:4 ; ///< + UINT32 EnableNbPsi1:1 ; ///< + UINT32 EnableDpmPstatePoll:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F5F8_STRUCT; + +// **** D0F0xBC_x1F5FC Register Definition **** +// Address +#define D0F0xBC_x1F5FC_ADDRESS 0x1f5fc + +// Type +#define D0F0xBC_x1F5FC_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F5FC_ChangeInProgress_OFFSET 0 +#define D0F0xBC_x1F5FC_ChangeInProgress_WIDTH 1 +#define D0F0xBC_x1F5FC_ChangeInProgress_MASK 0x1 +#define D0F0xBC_x1F5FC_CurrentPstatePair_OFFSET 1 +#define D0F0xBC_x1F5FC_CurrentPstatePair_WIDTH 1 +#define D0F0xBC_x1F5FC_CurrentPstatePair_MASK 0x2 +#define D0F0xBC_x1F5FC_Reserved_7_2_OFFSET 2 +#define D0F0xBC_x1F5FC_Reserved_7_2_WIDTH 6 +#define D0F0xBC_x1F5FC_Reserved_7_2_MASK 0xfc +#define D0F0xBC_x1F5FC_PSI1Sts_OFFSET 8 +#define D0F0xBC_x1F5FC_PSI1Sts_WIDTH 1 +#define D0F0xBC_x1F5FC_PSI1Sts_MASK 0x100 +#define D0F0xBC_x1F5FC_Reserved_31_9_OFFSET 9 +#define D0F0xBC_x1F5FC_Reserved_31_9_WIDTH 23 +#define D0F0xBC_x1F5FC_Reserved_31_9_MASK 0xfffffe00 + +/// D0F0xBC_x1F5FC +typedef union { + struct { ///< + UINT32 ChangeInProgress:1 ; ///< + UINT32 CurrentPstatePair:1 ; ///< + UINT32 Reserved_7_2:6 ; ///< + UINT32 PSI1Sts:1 ; ///< + UINT32 Reserved_31_9:23; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F5FC_STRUCT; + +// **** D0F0xBC_x1F610 Register Definition **** +// Address +#define D0F0xBC_x1F610_ADDRESS 0x1f610 + +// Type +#define D0F0xBC_x1F610_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F610_RESERVED_OFFSET 0 +#define D0F0xBC_x1F610_RESERVED_WIDTH 8 +#define D0F0xBC_x1F610_RESERVED_MASK 0xff +#define D0F0xBC_x1F610_GFXH_OFFSET 8 +#define D0F0xBC_x1F610_GFXH_WIDTH 8 +#define D0F0xBC_x1F610_GFXH_MASK 0xff00 +#define D0F0xBC_x1F610_GFXL_OFFSET 16 +#define D0F0xBC_x1F610_GFXL_WIDTH 8 +#define D0F0xBC_x1F610_GFXL_MASK 0xff0000 +#define D0F0xBC_x1F610_GPPSB_OFFSET 24 +#define D0F0xBC_x1F610_GPPSB_WIDTH 8 +#define D0F0xBC_x1F610_GPPSB_MASK 0xff000000 + +/// D0F0xBC_x1F610 +typedef union { + struct { ///< + UINT32 RESERVED:8 ; ///< + UINT32 GFXH:8 ; ///< + UINT32 GFXL:8 ; ///< + UINT32 GPPSB:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F610_STRUCT; + + +// **** D0F0xBC_x1F628 Register Definition **** +// Address +#define D0F0xBC_x1F628_ADDRESS 0x1f628 + +// Type +#define D0F0xBC_x1F628_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F628_Reserved_15_0_OFFSET 0 +#define D0F0xBC_x1F628_Reserved_15_0_WIDTH 16 +#define D0F0xBC_x1F628_Reserved_15_0_MASK 0xffff +#define D0F0xBC_x1F628_HtcActivePstateLimit_OFFSET 16 +#define D0F0xBC_x1F628_HtcActivePstateLimit_WIDTH 8 +#define D0F0xBC_x1F628_HtcActivePstateLimit_MASK 0xff0000 +#define D0F0xBC_x1F628_Reserved_31_24_OFFSET 24 +#define D0F0xBC_x1F628_Reserved_31_24_WIDTH 8 +#define D0F0xBC_x1F628_Reserved_31_24_MASK 0xff000000 + +/// D0F0xBC_x1F628 +typedef union { + struct { ///< + UINT32 Reserved_15_0:16;///< + UINT32 HtcActivePstateLimit:8; ///< + UINT32 Reserved_31_24:8; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F628_STRUCT; + +// **** D0F0xBC_x1F62C Register Definition **** +// Address +#define D0F0xBC_x1F62C_ADDRESS 0x1f62c + +// Type +#define D0F0xBC_x1F62C_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F62C_Idd_OFFSET 0 +#define D0F0xBC_x1F62C_Idd_WIDTH 16 +#define D0F0xBC_x1F62C_Idd_MASK 0xffff +#define D0F0xBC_x1F62C_Iddnb_OFFSET 16 +#define D0F0xBC_x1F62C_Iddnb_WIDTH 16 +#define D0F0xBC_x1F62C_Iddnb_MASK 0xffff0000 + +/// D0F0xBC_x1F62C +typedef union { + struct { ///< + UINT32 Idd:16; ///< + UINT32 Iddnb:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F62C_STRUCT; + +// **** D0F0xBC_x1F638 Register Definition **** +// Address +#define D0F0xBC_x1F638_ADDRESS 0x1f638 + +// Type +#define D0F0xBC_x1F638_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F638_TdcPeriod_OFFSET 0 +#define D0F0xBC_x1F638_TdcPeriod_WIDTH 8 +#define D0F0xBC_x1F638_TdcPeriod_MASK 0xff +#define D0F0xBC_x1F638_HtcPeriod_OFFSET 8 +#define D0F0xBC_x1F638_HtcPeriod_WIDTH 8 +#define D0F0xBC_x1F638_HtcPeriod_MASK 0xff00 +#define D0F0xBC_x1F638_NbdpmPeriod_OFFSET 16 +#define D0F0xBC_x1F638_NbdpmPeriod_WIDTH 8 +#define D0F0xBC_x1F638_NbdpmPeriod_MASK 0xff0000 +#define D0F0xBC_x1F638_PginterlockPeriod_OFFSET 24 +#define D0F0xBC_x1F638_PginterlockPeriod_WIDTH 8 +#define D0F0xBC_x1F638_PginterlockPeriod_MASK 0xff000000 + +/// D0F0xBC_x1F638 +typedef union { + struct { ///< + UINT32 TdcPeriod:8 ; ///< + UINT32 HtcPeriod:8 ; ///< + UINT32 NbdpmPeriod:8 ; ///< + UINT32 PginterlockPeriod:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F638_STRUCT; + +// **** D0F0xBC_x1F6E4 Register Definition **** +// Address +#define D0F0xBC_x1F6E4_ADDRESS 0x1f6e4 + +// Type +#define D0F0xBC_x1F6E4_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F6E4_DdrVoltFloor_OFFSET 0 +#define D0F0xBC_x1F6E4_DdrVoltFloor_WIDTH 8 +#define D0F0xBC_x1F6E4_DdrVoltFloor_MASK 0xff +#define D0F0xBC_x1F6E4_BapmDdrVoltFloor_OFFSET 8 +#define D0F0xBC_x1F6E4_BapmDdrVoltFloor_WIDTH 8 +#define D0F0xBC_x1F6E4_BapmDdrVoltFloor_MASK 0xff00 +#define D0F0xBC_x1F6E4_Reserved_OFFSET 16 +#define D0F0xBC_x1F6E4_Reserved_WIDTH 16 +#define D0F0xBC_x1F6E4_Reserved_MASK 0xffff0000 + +/// D0F0xBC_x1F6E4 +typedef union { + struct { ///< + UINT32 DdrVoltFloor:8 ; ///< + UINT32 BapmDdrVoltFloor:8 ; ///< + UINT32 Reserved:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F6E4_STRUCT; + +typedef union { + struct { ///< + UINT32 ex996_0:8 ; + UINT32 ex996_1:8 ; + UINT32 ex996_2:8 ; + UINT32 ex996_3:8 ; + } Field; ///< + UINT32 Value; ///< +} ex996_STRUCT; + +typedef union { + struct { ///< + UINT32 ex997_0:16; + UINT32 ex997_1:16; + } Field; ///< + UINT32 Value; ///< +} ex997_STRUCT; + +// **** D0F0xBC_x1F6B4 Register Definition **** +// Address +#define D0F0xBC_x1F6B4_ADDRESS 0x1f6b4 + +// Type +#define D0F0xBC_x1F6B4_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F6B4_TjOffset_OFFSET 0 +#define D0F0xBC_x1F6B4_TjOffset_WIDTH 8 +#define D0F0xBC_x1F6B4_TjOffset_MASK 0xff +#define D0F0xBC_x1F6B4_Reserved_OFFSET 8 +#define D0F0xBC_x1F6B4_Reserved_WIDTH 24 +#define D0F0xBC_x1F6B4_Reserved_MASK 0xffffff00 + +/// D0F0xBC_x1F6B4 +typedef union { + struct { ///< + UINT32 TjOffset:8 ; ///< + UINT32 Reserved:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F6B4_STRUCT; + +typedef union { + struct { ///< + UINT32 ex998_0:16; + UINT32 ex998_1:8; + UINT32 ex998_2:8; + } Field; ///< + UINT32 Value; ///< +} ex998_STRUCT; + +// **** D0F0xBC_x1F844 Register Definition **** +// Address +#define D0F0xBC_x1F844_ADDRESS 0x1f844 + +// Type +#define D0F0xBC_x1F844_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F844_CsrAddr_OFFSET 0 +#define D0F0xBC_x1F844_CsrAddr_WIDTH 6 +#define D0F0xBC_x1F844_CsrAddr_MASK 0x3f +#define D0F0xBC_x1F844_TcenId_OFFSET 6 +#define D0F0xBC_x1F844_TcenId_WIDTH 4 +#define D0F0xBC_x1F844_TcenId_MASK 0x3c0 +#define D0F0xBC_x1F844_Reserved_31_10_OFFSET 10 +#define D0F0xBC_x1F844_Reserved_31_10_WIDTH 22 +#define D0F0xBC_x1F844_Reserved_31_10_MASK 0xfffffc00 + +/// D0F0xBC_x1F844 +typedef union { + struct { ///< + UINT32 CsrAddr:6; ///< + UINT32 TcenId:4; ///< + UINT32 Reserved_31_10:22; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F844_STRUCT; + +// **** D0F0xBC_x1F848 Register Definition **** +// Address +#define D0F0xBC_x1F848_ADDRESS 0x1f848 + +// Type +#define D0F0xBC_x1F848_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F848_CsrAddr_OFFSET 0 +#define D0F0xBC_x1F848_CsrAddr_WIDTH 6 +#define D0F0xBC_x1F848_CsrAddr_MASK 0x3f +#define D0F0xBC_x1F848_TcenId_OFFSET 6 +#define D0F0xBC_x1F848_TcenId_WIDTH 4 +#define D0F0xBC_x1F848_TcenId_MASK 0x3c0 +#define D0F0xBC_x1F848_Reserved_31_10_OFFSET 10 +#define D0F0xBC_x1F848_Reserved_31_10_WIDTH 22 +#define D0F0xBC_x1F848_Reserved_31_10_MASK 0xfffffc00 + +/// D0F0xBC_x1F848 +typedef union { + struct { ///< + UINT32 CsrAddr:6; ///< + UINT32 TcenId:4; ///< + UINT32 Reserved_31_10:22; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F848_STRUCT; + +// **** D0F0xBC_x1F84C Register Definition **** +// Address +#define D0F0xBC_x1F84C_ADDRESS 0x1f84c + +// Type +#define D0F0xBC_x1F84C_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F84C_CsrAddr_OFFSET 0 +#define D0F0xBC_x1F84C_CsrAddr_WIDTH 6 +#define D0F0xBC_x1F84C_CsrAddr_MASK 0x3f +#define D0F0xBC_x1F84C_TcenId_OFFSET 6 +#define D0F0xBC_x1F84C_TcenId_WIDTH 4 +#define D0F0xBC_x1F84C_TcenId_MASK 0x3c0 +#define D0F0xBC_x1F84C_Reserved_31_10_OFFSET 10 +#define D0F0xBC_x1F84C_Reserved_31_10_WIDTH 22 +#define D0F0xBC_x1F84C_Reserved_31_10_MASK 0xfffffc00 + +/// D0F0xBC_x1F84C +typedef union { + struct { ///< + UINT32 CsrAddr:6; ///< + UINT32 TcenId:4; ///< + UINT32 Reserved_31_10:22; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F84C_STRUCT; + +typedef union { + struct { ///< + UINT32 ex999_0:8; + UINT32 ex999_1:8; + UINT32 ex999_2:8; + UINT32 ex999_3:8; + } Field; ///< + UINT32 Value; ///< +} ex999_STRUCT; + +// **** D0F0xBC_x1F870 Register Definition **** +// Address +#define D0F0xBC_x1F870_ADDRESS 0x1f870 + +// Type +#define D0F0xBC_x1F870_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F870_AmbientTempBase_OFFSET 0 +#define D0F0xBC_x1F870_AmbientTempBase_WIDTH 8 +#define D0F0xBC_x1F870_AmbientTempBase_MASK 0xff +#define D0F0xBC_x1F870_BAPMTI_TjOffset_2_OFFSET 8 +#define D0F0xBC_x1F870_BAPMTI_TjOffset_2_WIDTH 8 +#define D0F0xBC_x1F870_BAPMTI_TjOffset_2_MASK 0xff00 +#define D0F0xBC_x1F870_BAPMTI_TjOffset_1_OFFSET 16 +#define D0F0xBC_x1F870_BAPMTI_TjOffset_1_WIDTH 8 +#define D0F0xBC_x1F870_BAPMTI_TjOffset_1_MASK 0xff0000 +#define D0F0xBC_x1F870_BAPMTI_TjOffset_0_OFFSET 24 +#define D0F0xBC_x1F870_BAPMTI_TjOffset_0_WIDTH 8 +#define D0F0xBC_x1F870_BAPMTI_TjOffset_0_MASK 0xff000000 + +/// D0F0xBC_x1F870 +typedef union { + struct { ///< + UINT32 AmbientTempBase:8; ///< + UINT32 BAPMTI_TjOffset_2:8; ///< + UINT32 BAPMTI_TjOffset_1:8; ///< + UINT32 BAPMTI_TjOffset_0:8; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F870_STRUCT; + +/// D0F0xBC_x1F878 +typedef union { + struct { ///< + UINT32 FUSE_DATA:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F878_STRUCT; + +// **** D0F0xBC_x1F87C Register Definition **** +// Address +#define D0F0xBC_x1F87C_ADDRESS 0x1f87c + +// Type +#define D0F0xBC_x1F87C_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F87C_LL_PCIE_LoadStep_OFFSET 0 +#define D0F0xBC_x1F87C_LL_PCIE_LoadStep_WIDTH 16 +#define D0F0xBC_x1F87C_LL_PCIE_LoadStep_MASK 0xffff +#define D0F0xBC_x1F87C_LL_VddNbLoadStepBase_OFFSET 16 +#define D0F0xBC_x1F87C_LL_VddNbLoadStepBase_WIDTH 16 +#define D0F0xBC_x1F87C_LL_VddNbLoadStepBase_MASK 0xffff0000 + +/// D0F0xBC_x1F87C +typedef union { + struct { ///< + UINT32 LL_PCIE_LoadStep:16; ///< + UINT32 LL_VddNbLoadStepBase:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F87C_STRUCT; + +// **** D0F0xBC_x1F880 Register Definition **** +// Address +#define D0F0xBC_x1F880_ADDRESS 0x1f880 + +// Type +#define D0F0xBC_x1F880_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F880_LL_VCE_LoadStep_OFFSET 0 +#define D0F0xBC_x1F880_LL_VCE_LoadStep_WIDTH 16 +#define D0F0xBC_x1F880_LL_VCE_LoadStep_MASK 0xffff +#define D0F0xBC_x1F880_LL_UVD_LoadStep_OFFSET 16 +#define D0F0xBC_x1F880_LL_UVD_LoadStep_WIDTH 16 +#define D0F0xBC_x1F880_LL_UVD_LoadStep_MASK 0xffff0000 + +/// D0F0xBC_x1F880 +typedef union { + struct { ///< + UINT32 LL_VCE_LoadStep:16; ///< + UINT32 LL_UVD_LoadStep:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F880_STRUCT; + +// **** D0F0xBC_x1F884 Register Definition **** +// Address +#define D0F0xBC_x1F884_ADDRESS 0x1f884 + +// Type +#define D0F0xBC_x1F884_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F884_LL_DCE2_LoadStep_OFFSET 0 +#define D0F0xBC_x1F884_LL_DCE2_LoadStep_WIDTH 16 +#define D0F0xBC_x1F884_LL_DCE2_LoadStep_MASK 0xffff +#define D0F0xBC_x1F884_LL_DCE_LoadStep_OFFSET 16 +#define D0F0xBC_x1F884_LL_DCE_LoadStep_WIDTH 16 +#define D0F0xBC_x1F884_LL_DCE_LoadStep_MASK 0xffff0000 + +/// D0F0xBC_x1F884 +typedef union { + struct { ///< + UINT32 LL_DCE2_LoadStep:16; ///< + UINT32 LL_DCE_LoadStep:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F884_STRUCT; + +// **** D0F0xBC_x1F888 Register Definition **** +// Address +#define D0F0xBC_x1F888_ADDRESS 0x1f888 + +// Type +#define D0F0xBC_x1F888_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F888_VddNbTdp_OFFSET 0 +#define D0F0xBC_x1F888_VddNbTdp_WIDTH 16 +#define D0F0xBC_x1F888_VddNbTdp_MASK 0xffff +#define D0F0xBC_x1F888_LL_GPU_LoadStep_OFFSET 16 +#define D0F0xBC_x1F888_LL_GPU_LoadStep_WIDTH 16 +#define D0F0xBC_x1F888_LL_GPU_LoadStep_MASK 0xffff0000 + +/// D0F0xBC_x1F888 +typedef union { + struct { ///< + UINT32 VddNbTdp:16; ///< + UINT32 LL_GPU_LoadStep:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F888_STRUCT; + +// **** D0F0xBC_x1F88C Register Definition **** +// Address +#define D0F0xBC_x1F88C_ADDRESS 0x1f88c + +// Type +#define D0F0xBC_x1F88C_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F88C_NbVid_3_OFFSET 0 +#define D0F0xBC_x1F88C_NbVid_3_WIDTH 8 +#define D0F0xBC_x1F88C_NbVid_3_MASK 0xff +#define D0F0xBC_x1F88C_NbVid_2_OFFSET 8 +#define D0F0xBC_x1F88C_NbVid_2_WIDTH 8 +#define D0F0xBC_x1F88C_NbVid_2_MASK 0xff00 +#define D0F0xBC_x1F88C_NbVid_1_OFFSET 16 +#define D0F0xBC_x1F88C_NbVid_1_WIDTH 8 +#define D0F0xBC_x1F88C_NbVid_1_MASK 0xff0000 +#define D0F0xBC_x1F88C_NbVid_0_OFFSET 24 +#define D0F0xBC_x1F88C_NbVid_0_WIDTH 8 +#define D0F0xBC_x1F88C_NbVid_0_MASK 0xff000000 + +/// D0F0xBC_x1F88C +typedef union { + struct { ///< + UINT32 NbVid_3:8 ; ///< + UINT32 NbVid_2:8 ; ///< + UINT32 NbVid_1:8 ; ///< + UINT32 NbVid_0:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F88C_STRUCT; + +// **** D0F0xBC_x1F890 Register Definition **** +// Address +#define D0F0xBC_x1F890_ADDRESS 0x1f890 + +// Type +#define D0F0xBC_x1F890_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F890_CpuVid_3_OFFSET 0 +#define D0F0xBC_x1F890_CpuVid_3_WIDTH 8 +#define D0F0xBC_x1F890_CpuVid_3_MASK 0xff +#define D0F0xBC_x1F890_CpuVid_2_OFFSET 8 +#define D0F0xBC_x1F890_CpuVid_2_WIDTH 8 +#define D0F0xBC_x1F890_CpuVid_2_MASK 0xff00 +#define D0F0xBC_x1F890_CpuVid_1_OFFSET 16 +#define D0F0xBC_x1F890_CpuVid_1_WIDTH 8 +#define D0F0xBC_x1F890_CpuVid_1_MASK 0xff0000 +#define D0F0xBC_x1F890_CpuVid_0_OFFSET 24 +#define D0F0xBC_x1F890_CpuVid_0_WIDTH 8 +#define D0F0xBC_x1F890_CpuVid_0_MASK 0xff000000 + +/// D0F0xBC_x1F890 +typedef union { + struct { ///< + UINT32 CpuVid_3:8 ; ///< + UINT32 CpuVid_2:8 ; ///< + UINT32 CpuVid_1:8 ; ///< + UINT32 CpuVid_0:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F890_STRUCT; + +// **** D0F0xBC_x1F894 Register Definition **** +// Address +#define D0F0xBC_x1F894_ADDRESS 0x1f894 + +// Type +#define D0F0xBC_x1F894_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F894_CpuVid_7_OFFSET 0 +#define D0F0xBC_x1F894_CpuVid_7_WIDTH 8 +#define D0F0xBC_x1F894_CpuVid_7_MASK 0xff +#define D0F0xBC_x1F894_CpuVid_6_OFFSET 8 +#define D0F0xBC_x1F894_CpuVid_6_WIDTH 8 +#define D0F0xBC_x1F894_CpuVid_6_MASK 0xff00 +#define D0F0xBC_x1F894_CpuVid_5_OFFSET 16 +#define D0F0xBC_x1F894_CpuVid_5_WIDTH 8 +#define D0F0xBC_x1F894_CpuVid_5_MASK 0xff0000 +#define D0F0xBC_x1F894_CpuVid_4_OFFSET 24 +#define D0F0xBC_x1F894_CpuVid_4_WIDTH 8 +#define D0F0xBC_x1F894_CpuVid_4_MASK 0xff000000 + +/// D0F0xBC_x1F894 +typedef union { + struct { ///< + UINT32 CpuVid_7:8 ; ///< + UINT32 CpuVid_6:8 ; ///< + UINT32 CpuVid_5:8 ; ///< + UINT32 CpuVid_4:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F894_STRUCT; + +typedef union { + struct { ///< + UINT32 ex1000_0:16; + UINT32 ex1000_1:16; + } Field; ///< + UINT32 Value; ///< +} ex1000_STRUCT; + +typedef union { + struct { ///< + UINT32 ex1001_0:16; + UINT32 ex1001_1:8; + UINT32 ex1001_2:8; + } Field; ///< + UINT32 Value; ///< +} ex1001_STRUCT; + +// **** D0F0xBC_x1F8D4 Register Definition **** +// Address +#define D0F0xBC_x1F8D4_ADDRESS 0x1f8d4 + +// Type +#define D0F0xBC_x1F8D4_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F8D4_BapmPstateVid_3_OFFSET 0 +#define D0F0xBC_x1F8D4_BapmPstateVid_3_WIDTH 8 +#define D0F0xBC_x1F8D4_BapmPstateVid_3_MASK 0xff +#define D0F0xBC_x1F8D4_BapmPstateVid_2_OFFSET 8 +#define D0F0xBC_x1F8D4_BapmPstateVid_2_WIDTH 8 +#define D0F0xBC_x1F8D4_BapmPstateVid_2_MASK 0xff00 +#define D0F0xBC_x1F8D4_BapmPstateVid_1_OFFSET 16 +#define D0F0xBC_x1F8D4_BapmPstateVid_1_WIDTH 8 +#define D0F0xBC_x1F8D4_BapmPstateVid_1_MASK 0xff0000 +#define D0F0xBC_x1F8D4_BapmPstateVid_0_OFFSET 24 +#define D0F0xBC_x1F8D4_BapmPstateVid_0_WIDTH 8 +#define D0F0xBC_x1F8D4_BapmPstateVid_0_MASK 0xff000000 + +/// D0F0xBC_x1F8D4 +typedef union { + struct { ///< + UINT32 BapmPstateVid_3:8; ///< + UINT32 BapmPstateVid_2:8; ///< + UINT32 BapmPstateVid_1:8; ///< + UINT32 BapmPstateVid_0:8; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F8D4_STRUCT; + +// **** D0F0xBC_x1F8D4 Register Definition **** +// Address +#define D0F0xBC_x1F8D8_ADDRESS 0x1f8d8 + +// Type +#define D0F0xBC_x1F8D8_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F8D8_BapmPstateVid_7_OFFSET 0 +#define D0F0xBC_x1F8D8_BapmPstateVid_7_WIDTH 8 +#define D0F0xBC_x1F8D8_BapmPstateVid_7_MASK 0xff +#define D0F0xBC_x1F8D8_BapmPstateVid_6_OFFSET 8 +#define D0F0xBC_x1F8D8_BapmPstateVid_6_WIDTH 8 +#define D0F0xBC_x1F8D8_BapmPstateVid_6_MASK 0xff00 +#define D0F0xBC_x1F8D8_BapmPstateVid_5_OFFSET 16 +#define D0F0xBC_x1F8D8_BapmPstateVid_5_WIDTH 8 +#define D0F0xBC_x1F8D8_BapmPstateVid_5_MASK 0xff0000 +#define D0F0xBC_x1F8D8_BapmPstateVid_4_OFFSET 24 +#define D0F0xBC_x1F8D8_BapmPstateVid_4_WIDTH 8 +#define D0F0xBC_x1F8D8_BapmPstateVid_4_MASK 0xff000000 + +/// D0F0xBC_x1F8D8 +typedef union { + struct { ///< + UINT32 BapmPstateVid_7:8; ///< + UINT32 BapmPstateVid_6:8; ///< + UINT32 BapmPstateVid_5:8; ///< + UINT32 BapmPstateVid_4:8; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F8D8_STRUCT; + +// **** D0F0xBC_x1F8DC Register Definition **** +// Address +#define D0F0xBC_x1F8DC_ADDRESS 0x1f8dc + +// Type +#define D0F0xBC_x1F8DC_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F8DC_SClkVid3_OFFSET 0 +#define D0F0xBC_x1F8DC_SClkVid3_WIDTH 8 +#define D0F0xBC_x1F8DC_SClkVid3_MASK 0xff +#define D0F0xBC_x1F8DC_SClkVid2_OFFSET 8 +#define D0F0xBC_x1F8DC_SClkVid2_WIDTH 8 +#define D0F0xBC_x1F8DC_SClkVid2_MASK 0xff00 +#define D0F0xBC_x1F8DC_SClkVid1_OFFSET 16 +#define D0F0xBC_x1F8DC_SClkVid1_WIDTH 8 +#define D0F0xBC_x1F8DC_SClkVid1_MASK 0xff0000 +#define D0F0xBC_x1F8DC_SClkVid0_OFFSET 24 +#define D0F0xBC_x1F8DC_SClkVid0_WIDTH 8 +#define D0F0xBC_x1F8DC_SClkVid0_MASK 0xff000000 + +/// D0F0xBC_x1F8DC +typedef union { + struct { ///< + UINT32 SClkVid3:8; ///< + UINT32 SClkVid2:8; ///< + UINT32 SClkVid1:8; ///< + UINT32 SClkVid0:8; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F8DC_STRUCT; + +// **** D0F0xBC_x1F8E0 Register Definition **** +// Address +#define D0F0xBC_x1F8E0_ADDRESS 0x1f8e0 + +// Type +#define D0F0xBC_x1F8E0_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F8E0_BapmSclkVid_2_OFFSET 0 +#define D0F0xBC_x1F8E0_BapmSclkVid_2_WIDTH 8 +#define D0F0xBC_x1F8E0_BapmSclkVid_2_MASK 0xff +#define D0F0xBC_x1F8E0_BapmSclkVid_1_OFFSET 8 +#define D0F0xBC_x1F8E0_BapmSclkVid_1_WIDTH 8 +#define D0F0xBC_x1F8E0_BapmSclkVid_1_MASK 0xff00 +#define D0F0xBC_x1F8E0_BapmSclkVid_0_OFFSET 16 +#define D0F0xBC_x1F8E0_BapmSclkVid_0_WIDTH 8 +#define D0F0xBC_x1F8E0_BapmSclkVid_0_MASK 0xff0000 +#define D0F0xBC_x1F8E0_DdrVoltFloor_OFFSET 24 +#define D0F0xBC_x1F8E0_DdrVoltFloor_WIDTH 8 +#define D0F0xBC_x1F8E0_DdrVoltFloor_MASK 0xff000000 + +/// D0F0xBC_x1F8E0 +typedef union { + struct { ///< + UINT32 BapmSclkVid_2:8; ///< + UINT32 BapmSclkVid_1:8; ///< + UINT32 BapmSclkVid_0:8; ///< + UINT32 DdrVoltFloor:8; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F8E0_STRUCT; + +// **** D0F0xBC_x1F8E4 Register Definition **** +// Address +#define D0F0xBC_x1F8E4_ADDRESS 0x1f8e4 + +// Type +#define D0F0xBC_x1F8E4_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F8E4_BapmNbVid_1_OFFSET 0 +#define D0F0xBC_x1F8E4_BapmNbVid_1_WIDTH 8 +#define D0F0xBC_x1F8E4_BapmNbVid_1_MASK 0xff +#define D0F0xBC_x1F8E4_BapmNbVid_0_OFFSET 8 +#define D0F0xBC_x1F8E4_BapmNbVid_0_WIDTH 8 +#define D0F0xBC_x1F8E4_BapmNbVid_0_MASK 0xff00 +#define D0F0xBC_x1F8E4_BapmDdrVoltFloor_OFFSET 16 +#define D0F0xBC_x1F8E4_BapmDdrVoltFloor_WIDTH 8 +#define D0F0xBC_x1F8E4_BapmDdrVoltFloor_MASK 0xff0000 +#define D0F0xBC_x1F8E4_BapmSclkVid_3_OFFSET 24 +#define D0F0xBC_x1F8E4_BapmSclkVid_3_WIDTH 8 +#define D0F0xBC_x1F8E4_BapmSclkVid_3_MASK 0xff000000 + +/// D0F0xBC_x1F8E4 +typedef union { + struct { ///< + UINT32 BapmNbVid_1:8; ///< + UINT32 BapmNbVid_0:8; ///< + UINT32 BapmDdrVoltFloor:8; ///< + UINT32 BapmSclkVid_3:8; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F8E4_STRUCT; + +// **** D0F0xBC_x1F8E8 Register Definition **** +// Address +#define D0F0xBC_x1F8E8_ADDRESS 0x1f8e8 + +// Type +#define D0F0xBC_x1F8E8_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F8E8_Reserved_15_0_OFFSET 0 +#define D0F0xBC_x1F8E8_Reserved_15_0_WIDTH 16 +#define D0F0xBC_x1F8E8_Reserved_15_0_MASK 0xffff +#define D0F0xBC_x1F8E8_BapmNbVid_3_OFFSET 16 +#define D0F0xBC_x1F8E8_BapmNbVid_3_WIDTH 8 +#define D0F0xBC_x1F8E8_BapmNbVid_3_MASK 0xff0000 +#define D0F0xBC_x1F8E8_BapmNbVid_2_OFFSET 24 +#define D0F0xBC_x1F8E8_BapmNbVid_2_WIDTH 8 +#define D0F0xBC_x1F8E8_BapmNbVid_2_MASK 0xff000000 + +/// D0F0xBC_x1F8E8 +typedef union { + struct { ///< + UINT32 Reserved_15_0:16; ///< + UINT32 BapmNbVid_3:8; ///< + UINT32 BapmNbVid_2:8; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F8E8_STRUCT; + +typedef union { + struct { ///< + UINT32 ex1002_0:10; + UINT32 ex1002_1:20; + UINT32 ex1002_2:2; + } Field; ///< + UINT32 Value; ///< +} ex1002_STRUCT; + +// **** D0F0xBC_x1F85C Register Definition **** +// Address +#define D0F0xBC_x1F85C_ADDRESS 0x1f85c + +// Type +#define D0F0xBC_x1F85C_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F85C_VCETdp_OFFSET 0 +#define D0F0xBC_x1F85C_VCETdp_WIDTH 20 +#define D0F0xBC_x1F85C_VCETdp_MASK 0xfffff +#define D0F0xBC_x1F85C_spare8_OFFSET 20 +#define D0F0xBC_x1F85C_spare8_WIDTH 1 +#define D0F0xBC_x1F85C_spare8_MASK 0x100000 +#define D0F0xBC_x1F85C_TdpAgeValue_OFFSET 21 +#define D0F0xBC_x1F85C_TdpAgeValue_WIDTH 3 +#define D0F0xBC_x1F85C_TdpAgeValue_MASK 0xe00000 +#define D0F0xBC_x1F85C_TdpAgeRate_OFFSET 24 +#define D0F0xBC_x1F85C_TdpAgeRate_WIDTH 8 +#define D0F0xBC_x1F85C_TdpAgeRate_MASK 0xff000000 + +/// D0F0xBC_x1F85C +typedef union { + struct { ///< + UINT32 VCETdp:20; ///< + UINT32 spare8:1; ///< + UINT32 TdpAgeValue:3; ///< + UINT32 TdpAgeRate:8; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F85C_STRUCT; + +// **** D0F0xBC_x1F860 Register Definition **** +// Address +#define D0F0xBC_x1F860_ADDRESS 0x1f860 + +// Type +#define D0F0xBC_x1F860_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F860_BAPMTI_TjHyst_1_OFFSET 0 +#define D0F0xBC_x1F860_BAPMTI_TjHyst_1_WIDTH 8 +#define D0F0xBC_x1F860_BAPMTI_TjHyst_1_MASK 0xff +#define D0F0xBC_x1F860_BAPMTI_TjMax_1_OFFSET 8 +#define D0F0xBC_x1F860_BAPMTI_TjMax_1_WIDTH 8 +#define D0F0xBC_x1F860_BAPMTI_TjMax_1_MASK 0xff00 +#define D0F0xBC_x1F860_BAPMTI_TjHyst_0_OFFSET 16 +#define D0F0xBC_x1F860_BAPMTI_TjHyst_0_WIDTH 8 +#define D0F0xBC_x1F860_BAPMTI_TjHyst_0_MASK 0xff0000 +#define D0F0xBC_x1F860_BAPMTI_TjMax_0_OFFSET 24 +#define D0F0xBC_x1F860_BAPMTI_TjMax_0_WIDTH 8 +#define D0F0xBC_x1F860_BAPMTI_TjMax_0_MASK 0xff000000 + +/// D0F0xBC_x1F860 +typedef union { + struct { ///< + UINT32 BAPMTI_TjHyst_1:8; ///< + UINT32 BAPMTI_TjMax_1:8; ///< + UINT32 BAPMTI_TjHyst_0:8; ///< + UINT32 BAPMTI_TjMax_0:8; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F860_STRUCT; + +// **** D0F0xBC_x1F864 Register Definition **** +// Address +#define D0F0xBC_x1F864_ADDRESS 0x1f864 + +// Type +#define D0F0xBC_x1F864_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F864_PCIe2PhyOffset_OFFSET 0 +#define D0F0xBC_x1F864_PCIe2PhyOffset_WIDTH 8 +#define D0F0xBC_x1F864_PCIe2PhyOffset_MASK 0xff +#define D0F0xBC_x1F864_PCIe1PhyOffset_OFFSET 8 +#define D0F0xBC_x1F864_PCIe1PhyOffset_WIDTH 8 +#define D0F0xBC_x1F864_PCIe1PhyOffset_MASK 0xff00 +#define D0F0xBC_x1F864_BAPMTI_GpuTjHyst_OFFSET 16 +#define D0F0xBC_x1F864_BAPMTI_GpuTjHyst_WIDTH 8 +#define D0F0xBC_x1F864_BAPMTI_GpuTjHyst_MASK 0xff0000 +#define D0F0xBC_x1F864_BAPMTI_GpuTjMax_OFFSET 24 +#define D0F0xBC_x1F864_BAPMTI_GpuTjMax_WIDTH 8 +#define D0F0xBC_x1F864_BAPMTI_GpuTjMax_MASK 0xff000000 + +/// D0F0xBC_x1F864 +typedef union { + struct { ///< + UINT32 PCIe2PhyOffset:8; ///< + UINT32 PCIe1PhyOffset:8; ///< + UINT32 BAPMTI_GpuTjHyst:8; ///< + UINT32 BAPMTI_GpuTjMax:8; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F864_STRUCT; + +// **** D0F0xBC_x1F86C Register Definition **** +// Address +#define D0F0xBC_x1F86C_ADDRESS 0x1f86c + +// Type +#define D0F0xBC_x1F86C_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F86C_Reserved_22_0_OFFSET 0 +#define D0F0xBC_x1F86C_Reserved_22_0_WIDTH 23 +#define D0F0xBC_x1F86C_Reserved_22_0_MASK 0x7fffff +#define D0F0xBC_x1F86C_BapmLhtcCap_OFFSET 23 +#define D0F0xBC_x1F86C_BapmLhtcCap_WIDTH 1 +#define D0F0xBC_x1F86C_BapmLhtcCap_MASK 0x800000 +#define D0F0xBC_x1F86C_Reserved_31_24_OFFSET 24 +#define D0F0xBC_x1F86C_Reserved_31_24_WIDTH 8 +#define D0F0xBC_x1F86C_Reserved_31_24_MASK 0xff000000 + +/// D0F0xBC_x1F86C +typedef union { + struct { ///< + UINT32 Reserved_22_0:23;///< + UINT32 BapmLhtcCap:1; ///< + UINT32 Reserved_31_24:8; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F86C_STRUCT; + + +typedef union { + struct { ///< + UINT32 ex1003_0:32; + } Field; ///< + UINT32 Value; ///< +} ex1003_STRUCT; + + + +// **** D0F0xBC_x1FE00 Register Definition **** +// Address +#define D0F0xBC_x1FE00_ADDRESS 0x1fe00 + +// Type +#define D0F0xBC_x1FE00_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1FE00_Data_OFFSET 0 +#define D0F0xBC_x1FE00_Data_WIDTH 32 +#define D0F0xBC_x1FE00_Data_MASK 0xffffffff + +/// D0F0xBC_x1FE00 +typedef union { + struct { ///< + UINT32 Data:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1FE00_STRUCT; + + +typedef union { + struct { ///< + UINT32 INTR_MASK_0:1 ; ///< + UINT32 INTR_MASK_1:1 ; ///< + UINT32 INTR_MASK_2:1 ; ///< + UINT32 INTR_MASK_3:1 ; ///< + UINT32 INTR_MASK_4:1 ; ///< + UINT32 INTR_MASK_5:1 ; ///< + UINT32 INTR_MASK_6:1 ; ///< + UINT32 INTR_MASK_7:1 ; ///< + UINT32 INTR_MASK_8:1 ; ///< + UINT32 INTR_MASK_9:1 ; ///< + UINT32 INTR_MASK_10:1 ; ///< + UINT32 INTR_MASK_11:1 ; ///< + UINT32 INTR_MASK_12:1 ; ///< + UINT32 INTR_MASK_13:1 ; ///< + UINT32 INTR_MASK_14:1 ; ///< + UINT32 INTR_MASK_15:1 ; ///< + UINT32 INTR_MASK_16:1 ; ///< + UINT32 INTR_MASK_17:1 ; ///< + UINT32 INTR_MASK_18:1 ; ///< + UINT32 INTR_MASK_19:1 ; ///< + UINT32 INTR_MASK_20:1 ; ///< + UINT32 INTR_MASK_21:1 ; ///< + UINT32 INTR_MASK_22:1 ; ///< + UINT32 INTR_MASK_23:1 ; ///< + UINT32 INTR_MASK_24:1 ; ///< + UINT32 INTR_MASK_25:1 ; ///< + UINT32 INTR_MASK_26:1 ; ///< + UINT32 INTR_MASK_27:1 ; ///< + UINT32 INTR_MASK_28:1 ; ///< + UINT32 INTR_MASK_29:1 ; ///< + UINT32 INTR_MASK_30:1 ; ///< + UINT32 INTR_MASK_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} ex1005_STRUCT; + +// **** D0F0xBC_xE0000004 Register Definition **** +// Address +#define D0F0xBC_xE0000004_ADDRESS 0xe0000004 + +// Type +#define D0F0xBC_xE0000004_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0000004_RCU_TST_jpc_rep_req_OFFSET 0 +#define D0F0xBC_xE0000004_RCU_TST_jpc_rep_req_WIDTH 1 +#define D0F0xBC_xE0000004_RCU_TST_jpc_rep_req_MASK 0x1 +#define D0F0xBC_xE0000004_RCU_TST_jpc_rep_done_OFFSET 1 +#define D0F0xBC_xE0000004_RCU_TST_jpc_rep_done_WIDTH 1 +#define D0F0xBC_xE0000004_RCU_TST_jpc_rep_done_MASK 0x2 +#define D0F0xBC_xE0000004_drv_rst_mode_OFFSET 2 +#define D0F0xBC_xE0000004_drv_rst_mode_WIDTH 1 +#define D0F0xBC_xE0000004_drv_rst_mode_MASK 0x4 +#define D0F0xBC_xE0000004_SMU_DC_efuse_status_invalid_OFFSET 3 +#define D0F0xBC_xE0000004_SMU_DC_efuse_status_invalid_WIDTH 1 +#define D0F0xBC_xE0000004_SMU_DC_efuse_status_invalid_MASK 0x8 +#define D0F0xBC_xE0000004_Reserved_OFFSET 4 +#define D0F0xBC_xE0000004_Reserved_WIDTH 1 +#define D0F0xBC_xE0000004_Reserved_MASK 0x10 +#define D0F0xBC_xE0000004_TST_RCU_jpc_DtmSMSCntDone_OFFSET 5 +#define D0F0xBC_xE0000004_TST_RCU_jpc_DtmSMSCntDone_WIDTH 1 +#define D0F0xBC_xE0000004_TST_RCU_jpc_DtmSMSCntDone_MASK 0x20 +#define D0F0xBC_xE0000004_TP_Tester_OFFSET 6 +#define D0F0xBC_xE0000004_TP_Tester_WIDTH 1 +#define D0F0xBC_xE0000004_TP_Tester_MASK 0x40 +#define D0F0xBC_xE0000004_boot_seq_done_OFFSET 7 +#define D0F0xBC_xE0000004_boot_seq_done_WIDTH 1 +#define D0F0xBC_xE0000004_boot_seq_done_MASK 0x80 +#define D0F0xBC_xE0000004_sclk_deep_sleep_exit_OFFSET 8 +#define D0F0xBC_xE0000004_sclk_deep_sleep_exit_WIDTH 1 +#define D0F0xBC_xE0000004_sclk_deep_sleep_exit_MASK 0x100 +#define D0F0xBC_xE0000004_BREAK_PT1_ACTIVE_OFFSET 9 +#define D0F0xBC_xE0000004_BREAK_PT1_ACTIVE_WIDTH 1 +#define D0F0xBC_xE0000004_BREAK_PT1_ACTIVE_MASK 0x200 +#define D0F0xBC_xE0000004_BREAK_PT2_ACTIVE_OFFSET 10 +#define D0F0xBC_xE0000004_BREAK_PT2_ACTIVE_WIDTH 1 +#define D0F0xBC_xE0000004_BREAK_PT2_ACTIVE_MASK 0x400 +#define D0F0xBC_xE0000004_FCH_HALT_OFFSET 11 +#define D0F0xBC_xE0000004_FCH_HALT_WIDTH 1 +#define D0F0xBC_xE0000004_FCH_HALT_MASK 0x800 +#define D0F0xBC_xE0000004_FCH_LOCKDOWN_WRITE_DIS_OFFSET 12 +#define D0F0xBC_xE0000004_FCH_LOCKDOWN_WRITE_DIS_WIDTH 1 +#define D0F0xBC_xE0000004_FCH_LOCKDOWN_WRITE_DIS_MASK 0x1000 +#define D0F0xBC_xE0000004_RCU_GIO_fch_lockdown_OFFSET 13 +#define D0F0xBC_xE0000004_RCU_GIO_fch_lockdown_WIDTH 1 +#define D0F0xBC_xE0000004_RCU_GIO_fch_lockdown_MASK 0x2000 +#define D0F0xBC_xE0000004_Reserved14_23_OFFSET 14 +#define D0F0xBC_xE0000004_Reserved14_23_WIDTH 10 +#define D0F0xBC_xE0000004_Reserved14_23_MASK 0xffc000 +#define D0F0xBC_xE0000004_lm32_irq31_sel_OFFSET 24 +#define D0F0xBC_xE0000004_lm32_irq31_sel_WIDTH 2 +#define D0F0xBC_xE0000004_lm32_irq31_sel_MASK 0x3000000 +#define D0F0xBC_xE0000004_Reserved26_31_OFFSET 26 +#define D0F0xBC_xE0000004_Reserved26_31_WIDTH 6 +#define D0F0xBC_xE0000004_Reserved26_31_MASK 0xfc000000 + +/// D0F0xBC_xE0000004 +typedef union { + struct { ///< + UINT32 RCU_TST_jpc_rep_req:1 ; ///< + UINT32 RCU_TST_jpc_rep_done:1 ; ///< + UINT32 drv_rst_mode:1 ; ///< + UINT32 SMU_DC_efuse_status_invalid:1 ; ///< + UINT32 Reserved:1 ; ///< + UINT32 TST_RCU_jpc_DtmSMSCntDone:1 ; ///< + UINT32 TP_Tester:1 ; ///< + UINT32 boot_seq_done:1 ; ///< + UINT32 sclk_deep_sleep_exit:1 ; ///< + UINT32 BREAK_PT1_ACTIVE:1 ; ///< + UINT32 BREAK_PT2_ACTIVE:1 ; ///< + UINT32 FCH_HALT:1 ; ///< + UINT32 FCH_LOCKDOWN_WRITE_DIS:1 ; ///< + UINT32 RCU_GIO_fch_lockdown:1 ; ///< + UINT32 Reserved14_23:10; ///< + UINT32 lm32_irq31_sel:2 ; ///< + UINT32 Reserved26_31:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0000004_STRUCT; + +// **** D0F0xBC_xE0000120 Register Definition **** +// Address +#define D0F0xBC_xE0000120_ADDRESS 0xe0000120 + +// Type +#define D0F0xBC_xE0000120_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0000120_ActivityCntRst_OFFSET 0 +#define D0F0xBC_xE0000120_ActivityCntRst_WIDTH 1 +#define D0F0xBC_xE0000120_ActivityCntRst_MASK 0x1 +#define D0F0xBC_xE0000120_PeriodCntRst_OFFSET 1 +#define D0F0xBC_xE0000120_PeriodCntRst_WIDTH 1 +#define D0F0xBC_xE0000120_PeriodCntRst_MASK 0x2 +#define D0F0xBC_xE0000120_Reserved_2_2_OFFSET 2 +#define D0F0xBC_xE0000120_Reserved_2_2_WIDTH 1 +#define D0F0xBC_xE0000120_Reserved_2_2_MASK 0x4 +#define D0F0xBC_xE0000120_BusyCntSel_OFFSET 3 +#define D0F0xBC_xE0000120_BusyCntSel_WIDTH 2 +#define D0F0xBC_xE0000120_BusyCntSel_MASK 0x18 +#define D0F0xBC_xE0000120_Reserved_7_5_OFFSET 5 +#define D0F0xBC_xE0000120_Reserved_7_5_WIDTH 3 +#define D0F0xBC_xE0000120_Reserved_7_5_MASK 0xe0 +#define D0F0xBC_xE0000120_EnBifCnt_OFFSET 8 +#define D0F0xBC_xE0000120_EnBifCnt_WIDTH 1 +#define D0F0xBC_xE0000120_EnBifCnt_MASK 0x100 +#define D0F0xBC_xE0000120_EnOrbUsCnt_OFFSET 9 +#define D0F0xBC_xE0000120_EnOrbUsCnt_WIDTH 1 +#define D0F0xBC_xE0000120_EnOrbUsCnt_MASK 0x200 +#define D0F0xBC_xE0000120_EnOrbDsCnt_OFFSET 10 +#define D0F0xBC_xE0000120_EnOrbDsCnt_WIDTH 1 +#define D0F0xBC_xE0000120_EnOrbDsCnt_MASK 0x400 +#define D0F0xBC_xE0000120_Reserved_31_11_OFFSET 11 +#define D0F0xBC_xE0000120_Reserved_31_11_WIDTH 21 +#define D0F0xBC_xE0000120_Reserved_31_11_MASK 0xfffff800 + +/// D0F0xBC_xE0000120 +typedef union { + struct { ///< + UINT32 ActivityCntRst:1 ; ///< + UINT32 PeriodCntRst:1 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 BusyCntSel:2 ; ///< + UINT32 Reserved_7_5:3 ; ///< + UINT32 EnBifCnt:1 ; ///< + UINT32 EnOrbUsCnt:1 ; ///< + UINT32 EnOrbDsCnt:1 ; ///< + UINT32 Reserved_31_11:21; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0000120_STRUCT; + +// **** D0F0xBC_xE0001008 Register Definition **** +// Address +#define D0F0xBC_xE0001008_ADDRESS 0xe0001008 + +// Type +#define D0F0xBC_xE0001008_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0001008_SClkVid0_OFFSET 0 +#define D0F0xBC_xE0001008_SClkVid0_WIDTH 8 +#define D0F0xBC_xE0001008_SClkVid0_MASK 0xff +#define D0F0xBC_xE0001008_SClkVid1_OFFSET 8 +#define D0F0xBC_xE0001008_SClkVid1_WIDTH 8 +#define D0F0xBC_xE0001008_SClkVid1_MASK 0xff00 +#define D0F0xBC_xE0001008_SClkVid2_OFFSET 16 +#define D0F0xBC_xE0001008_SClkVid2_WIDTH 8 +#define D0F0xBC_xE0001008_SClkVid2_MASK 0xff0000 +#define D0F0xBC_xE0001008_SClkVid3_OFFSET 24 +#define D0F0xBC_xE0001008_SClkVid3_WIDTH 8 +#define D0F0xBC_xE0001008_SClkVid3_MASK 0xff000000 + +/// D0F0xBC_xE0001008 +typedef union { + struct { ///< + UINT32 SClkVid0:8 ; ///< + UINT32 SClkVid1:8 ; ///< + UINT32 SClkVid2:8 ; ///< + UINT32 SClkVid3:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0001008_STRUCT; + +typedef union { + struct { ///< + UINT32 WriteDis:1 ; ///< + UINT32 RfRm7:1 ; ///< + UINT32 Rme:1 ; ///< + UINT32 MbistDisable:1 ; ///< + UINT32 HardRepairDisable:1 ; ///< + UINT32 SoftRepairDisable:1 ; ///< + UINT32 SmsPwrdwnDisable:1 ; ///< + UINT32 Crbbmp1500Disa:1 ; ///< + UINT32 Crbbmp1500Disb:1 ; ///< + UINT32 GpuDis:1 ; ///< + UINT32 ex1006_0:6; + UINT32 ex1006_1:2; + UINT32 DftSpare1:1 ; ///< + UINT32 DftSpare2:1 ; ///< + UINT32 DftSpare3:1 ; ///< + UINT32 VceDisable:1 ; ///< + UINT32 DceScanDisable:1 ; ///< + UINT32 Reserved_31_23:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} ex1006_STRUCT; + +// **** D0F0xBC_xE0003000 Register Definition **** +// Address +#define D0F0xBC_xE0003000_ADDRESS 0xe0003000 + +// Type +#define D0F0xBC_xE0003000_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0003000_IntToggle_OFFSET 0 +#define D0F0xBC_xE0003000_IntToggle_WIDTH 1 +#define D0F0xBC_xE0003000_IntToggle_MASK 0x1 +#define D0F0xBC_xE0003000_ServiceIndex_OFFSET 1 +#define D0F0xBC_xE0003000_ServiceIndex_WIDTH 16 +#define D0F0xBC_xE0003000_ServiceIndex_MASK 0x1fffe +#define D0F0xBC_xE0003000_Reserved_31_17_OFFSET 17 +#define D0F0xBC_xE0003000_Reserved_31_17_WIDTH 15 +#define D0F0xBC_xE0003000_Reserved_31_17_MASK 0xfffe0000 + +/// D0F0xBC_xE0003000 +typedef union { + struct { ///< + UINT32 IntToggle:1 ; ///< + UINT32 ServiceIndex:16; ///< + UINT32 Reserved_31_17:15; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0003000_STRUCT; + +// **** D0F0xBC_xE0003004 Register Definition **** +// Address +#define D0F0xBC_xE0003004_ADDRESS 0xe0003004 + +// Type +#define D0F0xBC_xE0003004_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0003004_IntAck_OFFSET 0 +#define D0F0xBC_xE0003004_IntAck_WIDTH 1 +#define D0F0xBC_xE0003004_IntAck_MASK 0x1 +#define D0F0xBC_xE0003004_IntDone_OFFSET 1 +#define D0F0xBC_xE0003004_IntDone_WIDTH 1 +#define D0F0xBC_xE0003004_IntDone_MASK 0x2 +#define D0F0xBC_xE0003004_Reserved_31_2_OFFSET 2 +#define D0F0xBC_xE0003004_Reserved_31_2_WIDTH 30 +#define D0F0xBC_xE0003004_Reserved_31_2_MASK 0xfffffffc + +/// D0F0xBC_xE0003004 +typedef union { + struct { ///< + UINT32 IntAck:1 ; ///< + UINT32 IntDone:1 ; ///< + UINT32 Reserved_31_2:30; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0003004_STRUCT; + +// **** D0F0xBC_xE0003024 Register Definition **** +// Address +#define D0F0xBC_xE0003024_ADDRESS 0xe0003024 + +// Type +#define D0F0xBC_xE0003024_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0003024_SMU_SCRATCH_A_OFFSET 0 +#define D0F0xBC_xE0003024_SMU_SCRATCH_A_WIDTH 32 +#define D0F0xBC_xE0003024_SMU_SCRATCH_A_MASK 0xffffffff + +/// D0F0xBC_xE0003024 +typedef union { + struct { ///< + UINT32 SMU_SCRATCH_A:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0003024_STRUCT; + +// **** D0F0xBC_xE0003034 Register Definition **** +// Address +#define D0F0xBC_xE0003034_ADDRESS 0xe0003034 + +// Type +#define D0F0xBC_xE0003034_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0003034_PmAllcpusincc6_OFFSET 0 +#define D0F0xBC_xE0003034_PmAllcpusincc6_WIDTH 1 +#define D0F0xBC_xE0003034_PmAllcpusincc6_MASK 0x1 +#define D0F0xBC_xE0003034_PmNbps_OFFSET 1 +#define D0F0xBC_xE0003034_PmNbps_WIDTH 1 +#define D0F0xBC_xE0003034_PmNbps_MASK 0x2 +#define D0F0xBC_xE0003034_PmCommitselfrefr_OFFSET 2 +#define D0F0xBC_xE0003034_PmCommitselfrefr_WIDTH 2 +#define D0F0xBC_xE0003034_PmCommitselfrefr_MASK 0xc +#define D0F0xBC_xE0003034_PmPreselfrefresh_OFFSET 4 +#define D0F0xBC_xE0003034_PmPreselfrefresh_WIDTH 1 +#define D0F0xBC_xE0003034_PmPreselfrefresh_MASK 0x10 +#define D0F0xBC_xE0003034_PmReqnbpstate_OFFSET 5 +#define D0F0xBC_xE0003034_PmReqnbpstate_WIDTH 1 +#define D0F0xBC_xE0003034_PmReqnbpstate_MASK 0x20 +#define D0F0xBC_xE0003034_Reserved_8_6_OFFSET 6 +#define D0F0xBC_xE0003034_Reserved_8_6_WIDTH 3 +#define D0F0xBC_xE0003034_Reserved_8_6_MASK 0x1c0 +#define D0F0xBC_xE0003034_NbNbps_OFFSET 9 +#define D0F0xBC_xE0003034_NbNbps_WIDTH 1 +#define D0F0xBC_xE0003034_NbNbps_MASK 0x200 +#define D0F0xBC_xE0003034_NbCommitselfrefr_OFFSET 10 +#define D0F0xBC_xE0003034_NbCommitselfrefr_WIDTH 2 +#define D0F0xBC_xE0003034_NbCommitselfrefr_MASK 0xc00 +#define D0F0xBC_xE0003034_NbPreselfrefresh_OFFSET 12 +#define D0F0xBC_xE0003034_NbPreselfrefresh_WIDTH 1 +#define D0F0xBC_xE0003034_NbPreselfrefresh_MASK 0x1000 +#define D0F0xBC_xE0003034_NbReqnbpstate_OFFSET 13 +#define D0F0xBC_xE0003034_NbReqnbpstate_WIDTH 1 +#define D0F0xBC_xE0003034_NbReqnbpstate_MASK 0x2000 +#define D0F0xBC_xE0003034_McNbps_OFFSET 14 +#define D0F0xBC_xE0003034_McNbps_WIDTH 1 +#define D0F0xBC_xE0003034_McNbps_MASK 0x4000 +#define D0F0xBC_xE0003034_GmconCommitselfrefr_OFFSET 15 +#define D0F0xBC_xE0003034_GmconCommitselfrefr_WIDTH 2 +#define D0F0xBC_xE0003034_GmconCommitselfrefr_MASK 0x18000 +#define D0F0xBC_xE0003034_GmconPreselfrefresh_OFFSET 17 +#define D0F0xBC_xE0003034_GmconPreselfrefresh_WIDTH 1 +#define D0F0xBC_xE0003034_GmconPreselfrefresh_MASK 0x20000 +#define D0F0xBC_xE0003034_GmconReqnbpstate_OFFSET 18 +#define D0F0xBC_xE0003034_GmconReqnbpstate_WIDTH 1 +#define D0F0xBC_xE0003034_GmconReqnbpstate_MASK 0x40000 +#define D0F0xBC_xE0003034_SysIso_OFFSET 19 +#define D0F0xBC_xE0003034_SysIso_WIDTH 1 +#define D0F0xBC_xE0003034_SysIso_MASK 0x80000 +#define D0F0xBC_xE0003034_CpIso_OFFSET 20 +#define D0F0xBC_xE0003034_CpIso_WIDTH 1 +#define D0F0xBC_xE0003034_CpIso_MASK 0x100000 +#define D0F0xBC_xE0003034_Dc0Iso_OFFSET 21 +#define D0F0xBC_xE0003034_Dc0Iso_WIDTH 1 +#define D0F0xBC_xE0003034_Dc0Iso_MASK 0x200000 +#define D0F0xBC_xE0003034_Dc1Iso_OFFSET 22 +#define D0F0xBC_xE0003034_Dc1Iso_WIDTH 1 +#define D0F0xBC_xE0003034_Dc1Iso_MASK 0x400000 +#define D0F0xBC_xE0003034_DciIso_OFFSET 23 +#define D0F0xBC_xE0003034_DciIso_WIDTH 1 +#define D0F0xBC_xE0003034_DciIso_MASK 0x800000 +#define D0F0xBC_xE0003034_DcipgIso_OFFSET 24 +#define D0F0xBC_xE0003034_DcipgIso_WIDTH 1 +#define D0F0xBC_xE0003034_DcipgIso_MASK 0x1000000 +#define D0F0xBC_xE0003034_DdiIso_OFFSET 25 +#define D0F0xBC_xE0003034_DdiIso_WIDTH 1 +#define D0F0xBC_xE0003034_DdiIso_MASK 0x2000000 +#define D0F0xBC_xE0003034_GmcIso_OFFSET 26 +#define D0F0xBC_xE0003034_GmcIso_WIDTH 1 +#define D0F0xBC_xE0003034_GmcIso_MASK 0x4000000 +#define D0F0xBC_xE0003034_Reserved_27_27_OFFSET 27 +#define D0F0xBC_xE0003034_Reserved_27_27_WIDTH 1 +#define D0F0xBC_xE0003034_Reserved_27_27_MASK 0x8000000 +#define D0F0xBC_xE0003034_GmcPmSel_OFFSET 28 +#define D0F0xBC_xE0003034_GmcPmSel_WIDTH 2 +#define D0F0xBC_xE0003034_GmcPmSel_MASK 0x30000000 +#define D0F0xBC_xE0003034_CpPmSel_OFFSET 30 +#define D0F0xBC_xE0003034_CpPmSel_WIDTH 2 +#define D0F0xBC_xE0003034_CpPmSel_MASK 0xc0000000 + +/// D0F0xBC_xE0003034 +typedef union { + struct { ///< + UINT32 PmAllcpusincc6:1 ; ///< + UINT32 PmNbps:1 ; ///< + UINT32 PmCommitselfrefr:2 ; ///< + UINT32 PmPreselfrefresh:1 ; ///< + UINT32 PmReqnbpstate:1 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 NbNbps:1 ; ///< + UINT32 NbCommitselfrefr:2 ; ///< + UINT32 NbPreselfrefresh:1 ; ///< + UINT32 NbReqnbpstate:1 ; ///< + UINT32 McNbps:1 ; ///< + UINT32 GmconCommitselfrefr:2 ; ///< + UINT32 GmconPreselfrefresh:1 ; ///< + UINT32 GmconReqnbpstate:1 ; ///< + UINT32 SysIso:1 ; ///< + UINT32 CpIso:1 ; ///< + UINT32 Dc0Iso:1 ; ///< + UINT32 Dc1Iso:1 ; ///< + UINT32 DciIso:1 ; ///< + UINT32 DcipgIso:1 ; ///< + UINT32 DdiIso:1 ; ///< + UINT32 GmcIso:1 ; ///< + UINT32 Reserved_27_27:1 ; ///< + UINT32 GmcPmSel:2 ; ///< + UINT32 CpPmSel:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0003034_STRUCT; + +// **** D0F0xBC_xE0003048 Register Definition **** +// Address +#define D0F0xBC_xE0003048_ADDRESS 0xe0003048 + +// Type +#define D0F0xBC_xE0003048_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0003048_Fracv_OFFSET 0 +#define D0F0xBC_xE0003048_Fracv_WIDTH 12 +#define D0F0xBC_xE0003048_Fracv_MASK 0xfff +#define D0F0xBC_xE0003048_Intv_OFFSET 12 +#define D0F0xBC_xE0003048_Intv_WIDTH 7 +#define D0F0xBC_xE0003048_Intv_MASK 0x7f000 +#define D0F0xBC_xE0003048_Reserved_31_19_OFFSET 19 +#define D0F0xBC_xE0003048_Reserved_31_19_WIDTH 13 +#define D0F0xBC_xE0003048_Reserved_31_19_MASK 0xfff80000 + +/// D0F0xBC_xE0003048 +typedef union { + struct { ///< + UINT32 Fracv:12; ///< + UINT32 Intv:7 ; ///< + UINT32 Reserved_31_19:13; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0003048_STRUCT; + +// **** D0F0xBC_xE0003088 Register Definition **** +// Address +#define D0F0xBC_xE0003088_ADDRESS 0xe0003088 + +// Type +#define D0F0xBC_xE0003088_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0003088_SmuAuthDone_OFFSET 0 +#define D0F0xBC_xE0003088_SmuAuthDone_WIDTH 1 +#define D0F0xBC_xE0003088_SmuAuthDone_MASK 0x1 +#define D0F0xBC_xE0003088_SmuAuthPass_OFFSET 1 +#define D0F0xBC_xE0003088_SmuAuthPass_WIDTH 1 +#define D0F0xBC_xE0003088_SmuAuthPass_MASK 0x2 +#define D0F0xBC_xE0003088_Reserved_31_2_OFFSET 2 +#define D0F0xBC_xE0003088_Reserved_31_2_WIDTH 30 +#define D0F0xBC_xE0003088_Reserved_31_2_MASK 0xfffffffc + +/// D0F0xBC_xE0003088 +typedef union { + struct { ///< + UINT32 SmuAuthDone:1 ; ///< + UINT32 SmuAuthPass:1 ; ///< + UINT32 Reserved_31_2:30; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0003088_STRUCT; + +// **** D0F0xBC_xE00030A4 Register Definition **** +// Address +#define D0F0xBC_xE00030A4_ADDRESS 0xe00030a4 + +// Type +#define D0F0xBC_xE00030A4_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE00030A4_Reserved_15_0_OFFSET 0 +#define D0F0xBC_xE00030A4_Reserved_15_0_WIDTH 16 +#define D0F0xBC_xE00030A4_Reserved_15_0_MASK 0xffff +#define D0F0xBC_xE00030A4_SmuProtectedMode_OFFSET 16 +#define D0F0xBC_xE00030A4_SmuProtectedMode_WIDTH 1 +#define D0F0xBC_xE00030A4_SmuProtectedMode_MASK 0x10000 +#define D0F0xBC_xE00030A4_Reserved_31_17_OFFSET 17 +#define D0F0xBC_xE00030A4_Reserved_31_17_WIDTH 15 +#define D0F0xBC_xE00030A4_Reserved_31_17_MASK 0xfffe0000 + +/// D0F0xBC_xE00030A4 +typedef union { + struct { ///< + UINT32 Reserved_15_0:16; ///< + UINT32 SmuProtectedMode:1 ; ///< + UINT32 Reserved_31_17:15; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE00030A4_STRUCT; + +// **** D0F0xBC_xE0104040 Register Definition **** +// Address +#define D0F0xBC_xE0104040_ADDRESS 0xe0104040 + +// Type +#define D0F0xBC_xE0104040_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0104040_Reserved_6_0_OFFSET 0 +#define D0F0xBC_xE0104040_Reserved_6_0_WIDTH 7 +#define D0F0xBC_xE0104040_Reserved_6_0_MASK 0x7f +#define D0F0xBC_xE0104040_DeviceID_OFFSET 7 +#define D0F0xBC_xE0104040_DeviceID_WIDTH 16 +#define D0F0xBC_xE0104040_DeviceID_MASK 0x7fff80 +#define D0F0xBC_xE0104040_Reserved_31_17_OFFSET 23 +#define D0F0xBC_xE0104040_Reserved_31_17_WIDTH 9 +#define D0F0xBC_xE0104040_Reserved_31_17_MASK 0xff800000 + +/// D0F0xBC_xE0104040 +typedef union { + struct { ///< + UINT32 Reserved_6_0:7; ///< + UINT32 DeviceID:16 ; ///< + UINT32 Reserved_31_23:9; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0104040_STRUCT; + +// **** D0F0xBC_xE0104168 Register Definition **** +// Address +#define D0F0xBC_xE0104168_ADDRESS 0xe0104168 + +// Type +#define D0F0xBC_xE0104168_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0104168_GnbLPML15_5_0_OFFSET 0 +#define D0F0xBC_xE0104168_GnbLPML15_5_0_WIDTH 6 +#define D0F0xBC_xE0104168_GnbLPML15_5_0_MASK 0x3f +#define D0F0xBC_xE0104168_MemClkVid0_7_0_OFFSET 6 +#define D0F0xBC_xE0104168_MemClkVid0_7_0_WIDTH 8 +#define D0F0xBC_xE0104168_MemClkVid0_7_0_MASK 0x3fc0 +#define D0F0xBC_xE0104168_MemClkVid1_7_0_OFFSET 14 +#define D0F0xBC_xE0104168_MemClkVid1_7_0_WIDTH 8 +#define D0F0xBC_xE0104168_MemClkVid1_7_0_MASK 0x3fc000 +#define D0F0xBC_xE0104168_MemClkVid2_7_0_OFFSET 22 +#define D0F0xBC_xE0104168_MemClkVid2_7_0_WIDTH 8 +#define D0F0xBC_xE0104168_MemClkVid2_7_0_MASK 0x3fc00000 +#define D0F0xBC_xE0104168_MemClkVid3_1_0_OFFSET 30 +#define D0F0xBC_xE0104168_MemClkVid3_1_0_WIDTH 2 +#define D0F0xBC_xE0104168_MemClkVid3_1_0_MASK 0xc0000000 + +/// D0F0xBC_xE0104168 +typedef union { + struct { ///< + UINT32 GnbLPML15_5_0:6 ; ///< + UINT32 MemClkVid0_7_0:8 ; ///< + UINT32 MemClkVid1_7_0:8 ; ///< + UINT32 MemClkVid2_7_0:8 ; ///< + UINT32 MemClkVid3_1_0:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0104168_STRUCT; + +// **** D0F0xBC_xE010416C Register Definition **** +// Address +#define D0F0xBC_xE010416C_ADDRESS 0xe010416c + +// Type +#define D0F0xBC_xE010416C_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE010416C_MemClkVid3_7_2_OFFSET 0 +#define D0F0xBC_xE010416C_MemClkVid3_7_2_WIDTH 6 +#define D0F0xBC_xE010416C_MemClkVid3_7_2_MASK 0x3f +#define D0F0xBC_xE010416C_MemClkVid4_7_0_OFFSET 6 +#define D0F0xBC_xE010416C_MemClkVid4_7_0_WIDTH 8 +#define D0F0xBC_xE010416C_MemClkVid4_7_0_MASK 0x3fc0 +#define D0F0xBC_xE010416C_MemClkVid5_7_0_OFFSET 14 +#define D0F0xBC_xE010416C_MemClkVid5_7_0_WIDTH 8 +#define D0F0xBC_xE010416C_MemClkVid5_7_0_MASK 0x3fc000 +#define D0F0xBC_xE010416C_MemClkVid6_7_0_OFFSET 22 +#define D0F0xBC_xE010416C_MemClkVid6_7_0_WIDTH 8 +#define D0F0xBC_xE010416C_MemClkVid6_7_0_MASK 0x3fc00000 +#define D0F0xBC_xE010416C_MemClkVid7_1_0_OFFSET 30 +#define D0F0xBC_xE010416C_MemClkVid7_1_0_WIDTH 2 +#define D0F0xBC_xE010416C_MemClkVid7_1_0_MASK 0xc0000000 + +/// D0F0xBC_xE010416C +typedef union { + struct { ///< + UINT32 MemClkVid3_7_2:6 ; ///< + UINT32 MemClkVid4_7_0:8 ; ///< + UINT32 MemClkVid5_7_0:8 ; ///< + UINT32 MemClkVid6_7_0:8 ; ///< + UINT32 MemClkVid7_1_0:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE010416C_STRUCT; + +// **** D0F0xBC_xE0104170 Register Definition **** +// Address +#define D0F0xBC_xE0104170_ADDRESS 0xe0104170 + +// Type +#define D0F0xBC_xE0104170_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0104170_MemClkVid7_7_2_OFFSET 0 +#define D0F0xBC_xE0104170_MemClkVid7_7_2_WIDTH 6 +#define D0F0xBC_xE0104170_MemClkVid7_7_2_MASK 0x3f +#define D0F0xBC_xE0104170_MemClkVid8_7_0_OFFSET 6 +#define D0F0xBC_xE0104170_MemClkVid8_7_0_WIDTH 8 +#define D0F0xBC_xE0104170_MemClkVid8_7_0_MASK 0x3fc0 +#define D0F0xBC_xE0104170_AmbientTempBase_7_0_OFFSET 14 +#define D0F0xBC_xE0104170_AmbientTempBase_7_0_WIDTH 8 +#define D0F0xBC_xE0104170_AmbientTempBase_7_0_MASK 0x3fc000 +#define D0F0xBC_xE0104170_SMU_SPARE31_9_0_OFFSET 22 +#define D0F0xBC_xE0104170_SMU_SPARE31_9_0_WIDTH 10 +#define D0F0xBC_xE0104170_SMU_SPARE31_9_0_MASK 0xffc00000 + +/// D0F0xBC_xE0104170 +typedef union { + struct { ///< + UINT32 MemClkVid7_7_2:6 ; ///< + UINT32 MemClkVid8_7_0:8 ; ///< + UINT32 AmbientTempBase_7_0:8 ; ///< + UINT32 SMU_SPARE31_9_0:10; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0104170_STRUCT; + +// **** D0F0xBC_xE0300000 Register Definition **** +// Address +#define D0F0xBC_xE0300000_ADDRESS 0xe0300000 + +// Type +#define D0F0xBC_xE0300000_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0300000_FsmAddr_OFFSET 0 +#define D0F0xBC_xE0300000_FsmAddr_WIDTH 8 +#define D0F0xBC_xE0300000_FsmAddr_MASK 0xff +#define D0F0xBC_xE0300000_PowerDown_OFFSET 8 +#define D0F0xBC_xE0300000_PowerDown_WIDTH 1 +#define D0F0xBC_xE0300000_PowerDown_MASK 0x100 +#define D0F0xBC_xE0300000_PowerUp_OFFSET 9 +#define D0F0xBC_xE0300000_PowerUp_WIDTH 1 +#define D0F0xBC_xE0300000_PowerUp_MASK 0x200 +#define D0F0xBC_xE0300000_P1Select_OFFSET 10 +#define D0F0xBC_xE0300000_P1Select_WIDTH 1 +#define D0F0xBC_xE0300000_P1Select_MASK 0x400 +#define D0F0xBC_xE0300000_P2Select_OFFSET 11 +#define D0F0xBC_xE0300000_P2Select_WIDTH 1 +#define D0F0xBC_xE0300000_P2Select_MASK 0x800 +#define D0F0xBC_xE0300000_WriteOp_OFFSET 12 +#define D0F0xBC_xE0300000_WriteOp_WIDTH 1 +#define D0F0xBC_xE0300000_WriteOp_MASK 0x1000 +#define D0F0xBC_xE0300000_ReadOp_OFFSET 13 +#define D0F0xBC_xE0300000_ReadOp_WIDTH 1 +#define D0F0xBC_xE0300000_ReadOp_MASK 0x2000 +#define D0F0xBC_xE0300000_Reserved_27_14_OFFSET 14 +#define D0F0xBC_xE0300000_Reserved_27_14_WIDTH 14 +#define D0F0xBC_xE0300000_Reserved_27_14_MASK 0xfffc000 +#define D0F0xBC_xE0300000_RegAddr_OFFSET 28 +#define D0F0xBC_xE0300000_RegAddr_WIDTH 4 +#define D0F0xBC_xE0300000_RegAddr_MASK 0xf0000000 + +/// D0F0xBC_xE0300000 +typedef union { + struct { ///< + UINT32 FsmAddr:8 ; ///< + UINT32 PowerDown:1 ; ///< + UINT32 PowerUp:1 ; ///< + UINT32 P1Select:1 ; ///< + UINT32 P2Select:1 ; ///< + UINT32 WriteOp:1 ; ///< + UINT32 ReadOp:1 ; ///< + UINT32 Reserved_27_14:14; ///< + UINT32 RegAddr:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0300000_STRUCT; + +// **** D0F0xBC_xE0300004 Register Definition **** +// Address +#define D0F0xBC_xE0300004_ADDRESS 0xe0300004 + +// Type +#define D0F0xBC_xE0300004_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0300004_Write_value_OFFSET 0 +#define D0F0xBC_xE0300004_Write_value_WIDTH 32 +#define D0F0xBC_xE0300004_Write_value_MASK 0xffffffff + +/// D0F0xBC_xE0300004 +typedef union { + struct { ///< + UINT32 Write_value:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0300004_STRUCT; + +// **** D0F0xBC_xE0300008 Register Definition **** +// Address +#define D0F0xBC_xE0300008_ADDRESS 0xe0300008 + +// Type +#define D0F0xBC_xE0300008_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0300008_ReadValue_OFFSET 0 +#define D0F0xBC_xE0300008_ReadValue_WIDTH 24 +#define D0F0xBC_xE0300008_ReadValue_MASK 0xffffff +#define D0F0xBC_xE0300008_ReadValid_OFFSET 24 +#define D0F0xBC_xE0300008_ReadValid_WIDTH 1 +#define D0F0xBC_xE0300008_ReadValid_MASK 0x1000000 +#define D0F0xBC_xE0300008_Reserved_31_25_OFFSET 25 +#define D0F0xBC_xE0300008_Reserved_31_25_WIDTH 7 +#define D0F0xBC_xE0300008_Reserved_31_25_MASK 0xfe000000 + +/// D0F0xBC_xE0300008 +typedef union { + struct { ///< + UINT32 ReadValue:24; ///< + UINT32 ReadValid:1 ; ///< + UINT32 Reserved_31_25:7 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0300008_STRUCT; + +// **** D0F0xBC_xE030000C Register Definition **** +// Address +#define D0F0xBC_xE030000C_ADDRESS 0xe030000c + +// Type +#define D0F0xBC_xE030000C_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE030000C_FsmAddr_OFFSET 0 +#define D0F0xBC_xE030000C_FsmAddr_WIDTH 8 +#define D0F0xBC_xE030000C_FsmAddr_MASK 0xff +#define D0F0xBC_xE030000C_PowerDown_OFFSET 8 +#define D0F0xBC_xE030000C_PowerDown_WIDTH 1 +#define D0F0xBC_xE030000C_PowerDown_MASK 0x100 +#define D0F0xBC_xE030000C_PowerUp_OFFSET 9 +#define D0F0xBC_xE030000C_PowerUp_WIDTH 1 +#define D0F0xBC_xE030000C_PowerUp_MASK 0x200 +#define D0F0xBC_xE030000C_P1Select_OFFSET 10 +#define D0F0xBC_xE030000C_P1Select_WIDTH 1 +#define D0F0xBC_xE030000C_P1Select_MASK 0x400 +#define D0F0xBC_xE030000C_P2Select_OFFSET 11 +#define D0F0xBC_xE030000C_P2Select_WIDTH 1 +#define D0F0xBC_xE030000C_P2Select_MASK 0x800 +#define D0F0xBC_xE030000C_WriteOp_OFFSET 12 +#define D0F0xBC_xE030000C_WriteOp_WIDTH 1 +#define D0F0xBC_xE030000C_WriteOp_MASK 0x1000 +#define D0F0xBC_xE030000C_ReadOp_OFFSET 13 +#define D0F0xBC_xE030000C_ReadOp_WIDTH 1 +#define D0F0xBC_xE030000C_ReadOp_MASK 0x2000 +#define D0F0xBC_xE030000C_Reserved_27_14_OFFSET 14 +#define D0F0xBC_xE030000C_Reserved_27_14_WIDTH 14 +#define D0F0xBC_xE030000C_Reserved_27_14_MASK 0xfffc000 +#define D0F0xBC_xE030000C_RegAddr_OFFSET 28 +#define D0F0xBC_xE030000C_RegAddr_WIDTH 4 +#define D0F0xBC_xE030000C_RegAddr_MASK 0xf0000000 + +/// D0F0xBC_xE030000C +typedef union { + struct { ///< + UINT32 FsmAddr:8 ; ///< + UINT32 PowerDown:1 ; ///< + UINT32 PowerUp:1 ; ///< + UINT32 P1Select:1 ; ///< + UINT32 P2Select:1 ; ///< + UINT32 WriteOp:1 ; ///< + UINT32 ReadOp:1 ; ///< + UINT32 Reserved_27_14:14; ///< + UINT32 RegAddr:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE030000C_STRUCT; + +// **** D0F0xBC_xE0300010 Register Definition **** +// Address +#define D0F0xBC_xE0300010_ADDRESS 0xe0300010 + +// Type +#define D0F0xBC_xE0300010_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0300010_Write_value_OFFSET 0 +#define D0F0xBC_xE0300010_Write_value_WIDTH 32 +#define D0F0xBC_xE0300010_Write_value_MASK 0xffffffff + +/// D0F0xBC_xE0300010 +typedef union { + struct { ///< + UINT32 Write_value:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0300010_STRUCT; + +// **** D0F0xBC_xE0300018 Register Definition **** +// Address +#define D0F0xBC_xE0300018_ADDRESS 0xe0300018 + +// Type +#define D0F0xBC_xE0300018_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0300018_FsmAddr_OFFSET 0 +#define D0F0xBC_xE0300018_FsmAddr_WIDTH 8 +#define D0F0xBC_xE0300018_FsmAddr_MASK 0xff +#define D0F0xBC_xE0300018_PowerDown_OFFSET 8 +#define D0F0xBC_xE0300018_PowerDown_WIDTH 1 +#define D0F0xBC_xE0300018_PowerDown_MASK 0x100 +#define D0F0xBC_xE0300018_PowerUp_OFFSET 9 +#define D0F0xBC_xE0300018_PowerUp_WIDTH 1 +#define D0F0xBC_xE0300018_PowerUp_MASK 0x200 +#define D0F0xBC_xE0300018_P1Select_OFFSET 10 +#define D0F0xBC_xE0300018_P1Select_WIDTH 1 +#define D0F0xBC_xE0300018_P1Select_MASK 0x400 +#define D0F0xBC_xE0300018_P2Select_OFFSET 11 +#define D0F0xBC_xE0300018_P2Select_WIDTH 1 +#define D0F0xBC_xE0300018_P2Select_MASK 0x800 +#define D0F0xBC_xE0300018_WriteOp_OFFSET 12 +#define D0F0xBC_xE0300018_WriteOp_WIDTH 1 +#define D0F0xBC_xE0300018_WriteOp_MASK 0x1000 +#define D0F0xBC_xE0300018_ReadOp_OFFSET 13 +#define D0F0xBC_xE0300018_ReadOp_WIDTH 1 +#define D0F0xBC_xE0300018_ReadOp_MASK 0x2000 +#define D0F0xBC_xE0300018_Reserved_27_14_OFFSET 14 +#define D0F0xBC_xE0300018_Reserved_27_14_WIDTH 14 +#define D0F0xBC_xE0300018_Reserved_27_14_MASK 0xfffc000 +#define D0F0xBC_xE0300018_RegAddr_OFFSET 28 +#define D0F0xBC_xE0300018_RegAddr_WIDTH 4 +#define D0F0xBC_xE0300018_RegAddr_MASK 0xf0000000 + +/// D0F0xBC_xE0300018 +typedef union { + struct { ///< + UINT32 FsmAddr:8 ; ///< + UINT32 PowerDown:1 ; ///< + UINT32 PowerUp:1 ; ///< + UINT32 P1Select:1 ; ///< + UINT32 P2Select:1 ; ///< + UINT32 WriteOp:1 ; ///< + UINT32 ReadOp:1 ; ///< + UINT32 Reserved_27_14:14; ///< + UINT32 RegAddr:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0300018_STRUCT; + +// **** D0F0xBC_xE030001C Register Definition **** +// Address +#define D0F0xBC_xE030001C_ADDRESS 0xe030001c + +// Type +#define D0F0xBC_xE030001C_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE030001C_Write_value_OFFSET 0 +#define D0F0xBC_xE030001C_Write_value_WIDTH 32 +#define D0F0xBC_xE030001C_Write_value_MASK 0xffffffff + +/// D0F0xBC_xE030001C +typedef union { + struct { ///< + UINT32 Write_value:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE030001C_STRUCT; + +// **** D0F0xBC_xE0300024 Register Definition **** +// Address +#define D0F0xBC_xE0300024_ADDRESS 0xe0300024 + +// Type +#define D0F0xBC_xE0300024_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0300024_FsmAddr_OFFSET 0 +#define D0F0xBC_xE0300024_FsmAddr_WIDTH 8 +#define D0F0xBC_xE0300024_FsmAddr_MASK 0xff +#define D0F0xBC_xE0300024_PowerDown_OFFSET 8 +#define D0F0xBC_xE0300024_PowerDown_WIDTH 1 +#define D0F0xBC_xE0300024_PowerDown_MASK 0x100 +#define D0F0xBC_xE0300024_PowerUp_OFFSET 9 +#define D0F0xBC_xE0300024_PowerUp_WIDTH 1 +#define D0F0xBC_xE0300024_PowerUp_MASK 0x200 +#define D0F0xBC_xE0300024_P1Select_OFFSET 10 +#define D0F0xBC_xE0300024_P1Select_WIDTH 1 +#define D0F0xBC_xE0300024_P1Select_MASK 0x400 +#define D0F0xBC_xE0300024_P2Select_OFFSET 11 +#define D0F0xBC_xE0300024_P2Select_WIDTH 1 +#define D0F0xBC_xE0300024_P2Select_MASK 0x800 +#define D0F0xBC_xE0300024_WriteOp_OFFSET 12 +#define D0F0xBC_xE0300024_WriteOp_WIDTH 1 +#define D0F0xBC_xE0300024_WriteOp_MASK 0x1000 +#define D0F0xBC_xE0300024_ReadOp_OFFSET 13 +#define D0F0xBC_xE0300024_ReadOp_WIDTH 1 +#define D0F0xBC_xE0300024_ReadOp_MASK 0x2000 +#define D0F0xBC_xE0300024_Reserved_27_14_OFFSET 14 +#define D0F0xBC_xE0300024_Reserved_27_14_WIDTH 14 +#define D0F0xBC_xE0300024_Reserved_27_14_MASK 0xfffc000 +#define D0F0xBC_xE0300024_RegAddr_OFFSET 28 +#define D0F0xBC_xE0300024_RegAddr_WIDTH 4 +#define D0F0xBC_xE0300024_RegAddr_MASK 0xf0000000 + +/// D0F0xBC_xE0300024 +typedef union { + struct { ///< + UINT32 FsmAddr:8 ; ///< + UINT32 PowerDown:1 ; ///< + UINT32 PowerUp:1 ; ///< + UINT32 P1Select:1 ; ///< + UINT32 P2Select:1 ; ///< + UINT32 WriteOp:1 ; ///< + UINT32 ReadOp:1 ; ///< + UINT32 Reserved_27_14:14; ///< + UINT32 RegAddr:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0300024_STRUCT; + +// **** D0F0xBC_xE0300028 Register Definition **** +// Address +#define D0F0xBC_xE0300028_ADDRESS 0xe0300028 + +// Type +#define D0F0xBC_xE0300028_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0300028_Write_value_OFFSET 0 +#define D0F0xBC_xE0300028_Write_value_WIDTH 32 +#define D0F0xBC_xE0300028_Write_value_MASK 0xffffffff + +/// D0F0xBC_xE0300028 +typedef union { + struct { ///< + UINT32 Write_value:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0300028_STRUCT; + +// **** D0F0xBC_xE0300030 Register Definition **** +// Address +#define D0F0xBC_xE0300030_ADDRESS 0xe0300030 + +// Type +#define D0F0xBC_xE0300030_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0300030_FsmAddr_OFFSET 0 +#define D0F0xBC_xE0300030_FsmAddr_WIDTH 8 +#define D0F0xBC_xE0300030_FsmAddr_MASK 0xff +#define D0F0xBC_xE0300030_PowerDown_OFFSET 8 +#define D0F0xBC_xE0300030_PowerDown_WIDTH 1 +#define D0F0xBC_xE0300030_PowerDown_MASK 0x100 +#define D0F0xBC_xE0300030_PowerUp_OFFSET 9 +#define D0F0xBC_xE0300030_PowerUp_WIDTH 1 +#define D0F0xBC_xE0300030_PowerUp_MASK 0x200 +#define D0F0xBC_xE0300030_P1Select_OFFSET 10 +#define D0F0xBC_xE0300030_P1Select_WIDTH 1 +#define D0F0xBC_xE0300030_P1Select_MASK 0x400 +#define D0F0xBC_xE0300030_P2Select_OFFSET 11 +#define D0F0xBC_xE0300030_P2Select_WIDTH 1 +#define D0F0xBC_xE0300030_P2Select_MASK 0x800 +#define D0F0xBC_xE0300030_WriteOp_OFFSET 12 +#define D0F0xBC_xE0300030_WriteOp_WIDTH 1 +#define D0F0xBC_xE0300030_WriteOp_MASK 0x1000 +#define D0F0xBC_xE0300030_ReadOp_OFFSET 13 +#define D0F0xBC_xE0300030_ReadOp_WIDTH 1 +#define D0F0xBC_xE0300030_ReadOp_MASK 0x2000 +#define D0F0xBC_xE0300030_Reserved_27_14_OFFSET 14 +#define D0F0xBC_xE0300030_Reserved_27_14_WIDTH 14 +#define D0F0xBC_xE0300030_Reserved_27_14_MASK 0xfffc000 +#define D0F0xBC_xE0300030_RegAddr_OFFSET 28 +#define D0F0xBC_xE0300030_RegAddr_WIDTH 4 +#define D0F0xBC_xE0300030_RegAddr_MASK 0xf0000000 + +/// D0F0xBC_xE0300030 +typedef union { + struct { ///< + UINT32 FsmAddr:8 ; ///< + UINT32 PowerDown:1 ; ///< + UINT32 PowerUp:1 ; ///< + UINT32 P1Select:1 ; ///< + UINT32 P2Select:1 ; ///< + UINT32 WriteOp:1 ; ///< + UINT32 ReadOp:1 ; ///< + UINT32 Reserved_27_14:14; ///< + UINT32 RegAddr:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0300030_STRUCT; + +// **** D0F0xBC_xE0300034 Register Definition **** +// Address +#define D0F0xBC_xE0300034_ADDRESS 0xe0300034 + +// Type +#define D0F0xBC_xE0300034_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0300034_Write_value_OFFSET 0 +#define D0F0xBC_xE0300034_Write_value_WIDTH 32 +#define D0F0xBC_xE0300034_Write_value_MASK 0xffffffff + +/// D0F0xBC_xE0300034 +typedef union { + struct { ///< + UINT32 Write_value:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0300034_STRUCT; + +// **** D0F0xBC_xE030003C Register Definition **** +// Address +#define D0F0xBC_xE030003C_ADDRESS 0xe030003c + +// Type +#define D0F0xBC_xE030003C_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE030003C_FsmAddr_OFFSET 0 +#define D0F0xBC_xE030003C_FsmAddr_WIDTH 8 +#define D0F0xBC_xE030003C_FsmAddr_MASK 0xff +#define D0F0xBC_xE030003C_PowerDown_OFFSET 8 +#define D0F0xBC_xE030003C_PowerDown_WIDTH 1 +#define D0F0xBC_xE030003C_PowerDown_MASK 0x100 +#define D0F0xBC_xE030003C_PowerUp_OFFSET 9 +#define D0F0xBC_xE030003C_PowerUp_WIDTH 1 +#define D0F0xBC_xE030003C_PowerUp_MASK 0x200 +#define D0F0xBC_xE030003C_P1Select_OFFSET 10 +#define D0F0xBC_xE030003C_P1Select_WIDTH 1 +#define D0F0xBC_xE030003C_P1Select_MASK 0x400 +#define D0F0xBC_xE030003C_P2Select_OFFSET 11 +#define D0F0xBC_xE030003C_P2Select_WIDTH 1 +#define D0F0xBC_xE030003C_P2Select_MASK 0x800 +#define D0F0xBC_xE030003C_WriteOp_OFFSET 12 +#define D0F0xBC_xE030003C_WriteOp_WIDTH 1 +#define D0F0xBC_xE030003C_WriteOp_MASK 0x1000 +#define D0F0xBC_xE030003C_ReadOp_OFFSET 13 +#define D0F0xBC_xE030003C_ReadOp_WIDTH 1 +#define D0F0xBC_xE030003C_ReadOp_MASK 0x2000 +#define D0F0xBC_xE030003C_Reserved_27_14_OFFSET 14 +#define D0F0xBC_xE030003C_Reserved_27_14_WIDTH 14 +#define D0F0xBC_xE030003C_Reserved_27_14_MASK 0xfffc000 +#define D0F0xBC_xE030003C_RegAddr_OFFSET 28 +#define D0F0xBC_xE030003C_RegAddr_WIDTH 4 +#define D0F0xBC_xE030003C_RegAddr_MASK 0xf0000000 + +/// D0F0xBC_xE030003C +typedef union { + struct { ///< + UINT32 FsmAddr:8 ; ///< + UINT32 PowerDown:1 ; ///< + UINT32 PowerUp:1 ; ///< + UINT32 P1Select:1 ; ///< + UINT32 P2Select:1 ; ///< + UINT32 WriteOp:1 ; ///< + UINT32 ReadOp:1 ; ///< + UINT32 Reserved_27_14:14; ///< + UINT32 RegAddr:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE030003C_STRUCT; + +// **** D0F0xBC_xE0300040 Register Definition **** +// Address +#define D0F0xBC_xE0300040_ADDRESS 0xe0300040 + +// Type +#define D0F0xBC_xE0300040_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0300040_Write_value_OFFSET 0 +#define D0F0xBC_xE0300040_Write_value_WIDTH 32 +#define D0F0xBC_xE0300040_Write_value_MASK 0xffffffff + +/// D0F0xBC_xE0300040 +typedef union { + struct { ///< + UINT32 Write_value:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0300040_STRUCT; + +// **** D0F0xBC_xE0300054 Register Definition **** +// Address +#define D0F0xBC_xE0300054_ADDRESS 0xe0300054 + +// Type +#define D0F0xBC_xE0300054_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0300054_FsmAddr_OFFSET 0 +#define D0F0xBC_xE0300054_FsmAddr_WIDTH 8 +#define D0F0xBC_xE0300054_FsmAddr_MASK 0xff +#define D0F0xBC_xE0300054_PowerDown_OFFSET 8 +#define D0F0xBC_xE0300054_PowerDown_WIDTH 1 +#define D0F0xBC_xE0300054_PowerDown_MASK 0x100 +#define D0F0xBC_xE0300054_PowerUp_OFFSET 9 +#define D0F0xBC_xE0300054_PowerUp_WIDTH 1 +#define D0F0xBC_xE0300054_PowerUp_MASK 0x200 +#define D0F0xBC_xE0300054_P1Select_OFFSET 10 +#define D0F0xBC_xE0300054_P1Select_WIDTH 1 +#define D0F0xBC_xE0300054_P1Select_MASK 0x400 +#define D0F0xBC_xE0300054_P2Select_OFFSET 11 +#define D0F0xBC_xE0300054_P2Select_WIDTH 1 +#define D0F0xBC_xE0300054_P2Select_MASK 0x800 +#define D0F0xBC_xE0300054_WriteOp_OFFSET 12 +#define D0F0xBC_xE0300054_WriteOp_WIDTH 1 +#define D0F0xBC_xE0300054_WriteOp_MASK 0x1000 +#define D0F0xBC_xE0300054_ReadOp_OFFSET 13 +#define D0F0xBC_xE0300054_ReadOp_WIDTH 1 +#define D0F0xBC_xE0300054_ReadOp_MASK 0x2000 +#define D0F0xBC_xE0300054_Reserved_27_14_OFFSET 14 +#define D0F0xBC_xE0300054_Reserved_27_14_WIDTH 14 +#define D0F0xBC_xE0300054_Reserved_27_14_MASK 0xfffc000 +#define D0F0xBC_xE0300054_RegAddr_OFFSET 28 +#define D0F0xBC_xE0300054_RegAddr_WIDTH 4 +#define D0F0xBC_xE0300054_RegAddr_MASK 0xf0000000 + +/// D0F0xBC_xE0300054 +typedef union { + struct { ///< + UINT32 FsmAddr:8 ; ///< + UINT32 PowerDown:1 ; ///< + UINT32 PowerUp:1 ; ///< + UINT32 P1Select:1 ; ///< + UINT32 P2Select:1 ; ///< + UINT32 WriteOp:1 ; ///< + UINT32 ReadOp:1 ; ///< + UINT32 Reserved_27_14:14; ///< + UINT32 RegAddr:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0300054_STRUCT; + +// **** D0F0xBC_xE0300058 Register Definition **** +// Address +#define D0F0xBC_xE0300058_ADDRESS 0xe0300058 + +// Type +#define D0F0xBC_xE0300058_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0300058_WriteValue_OFFSET 0 +#define D0F0xBC_xE0300058_WriteValue_WIDTH 32 +#define D0F0xBC_xE0300058_WriteValue_MASK 0xffffffff + +/// D0F0xBC_xE0300058 +typedef union { + struct { ///< + UINT32 WriteValue:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0300058_STRUCT; + +// **** D0F0xBC_xE0300070 Register Definition **** +// Address +#define D0F0xBC_xE0300070_ADDRESS 0xe0300070 + +// Type +#define D0F0xBC_xE0300070_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0300070_FsmAddr_OFFSET 0 +#define D0F0xBC_xE0300070_FsmAddr_WIDTH 8 +#define D0F0xBC_xE0300070_FsmAddr_MASK 0xff +#define D0F0xBC_xE0300070_PowerDown_OFFSET 8 +#define D0F0xBC_xE0300070_PowerDown_WIDTH 1 +#define D0F0xBC_xE0300070_PowerDown_MASK 0x100 +#define D0F0xBC_xE0300070_PowerUp_OFFSET 9 +#define D0F0xBC_xE0300070_PowerUp_WIDTH 1 +#define D0F0xBC_xE0300070_PowerUp_MASK 0x200 +#define D0F0xBC_xE0300070_P1Select_OFFSET 10 +#define D0F0xBC_xE0300070_P1Select_WIDTH 1 +#define D0F0xBC_xE0300070_P1Select_MASK 0x400 +#define D0F0xBC_xE0300070_P2Select_OFFSET 11 +#define D0F0xBC_xE0300070_P2Select_WIDTH 1 +#define D0F0xBC_xE0300070_P2Select_MASK 0x800 +#define D0F0xBC_xE0300070_WriteOp_OFFSET 12 +#define D0F0xBC_xE0300070_WriteOp_WIDTH 1 +#define D0F0xBC_xE0300070_WriteOp_MASK 0x1000 +#define D0F0xBC_xE0300070_ReadOp_OFFSET 13 +#define D0F0xBC_xE0300070_ReadOp_WIDTH 1 +#define D0F0xBC_xE0300070_ReadOp_MASK 0x2000 +#define D0F0xBC_xE0300070_Reserved_27_14_OFFSET 14 +#define D0F0xBC_xE0300070_Reserved_27_14_WIDTH 14 +#define D0F0xBC_xE0300070_Reserved_27_14_MASK 0xfffc000 +#define D0F0xBC_xE0300070_RegAddr_OFFSET 28 +#define D0F0xBC_xE0300070_RegAddr_WIDTH 4 +#define D0F0xBC_xE0300070_RegAddr_MASK 0xf0000000 + +/// D0F0xBC_xE0300070 +typedef union { + struct { ///< + UINT32 FsmAddr:8 ; ///< + UINT32 PowerDown:1 ; ///< + UINT32 PowerUp:1 ; ///< + UINT32 P1Select:1 ; ///< + UINT32 P2Select:1 ; ///< + UINT32 WriteOp:1 ; ///< + UINT32 ReadOp:1 ; ///< + UINT32 Reserved_27_14:14; ///< + UINT32 RegAddr:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0300070_STRUCT; + +// **** D0F0xBC_xE0300074 Register Definition **** +// Address +#define D0F0xBC_xE0300074_ADDRESS 0xe0300074 + +// Type +#define D0F0xBC_xE0300074_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0300074_WriteValue_OFFSET 0 +#define D0F0xBC_xE0300074_WriteValue_WIDTH 32 +#define D0F0xBC_xE0300074_WriteValue_MASK 0xffffffff + +/// D0F0xBC_xE0300074 +typedef union { + struct { ///< + UINT32 WriteValue:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0300074_STRUCT; + +// **** D0F0xBC_xE030008C Register Definition **** +// Address +#define D0F0xBC_xE030008C_ADDRESS 0xe030008c + +// Type +#define D0F0xBC_xE030008C_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE030008C_FsmAddr_OFFSET 0 +#define D0F0xBC_xE030008C_FsmAddr_WIDTH 8 +#define D0F0xBC_xE030008C_FsmAddr_MASK 0xff +#define D0F0xBC_xE030008C_PowerDown_OFFSET 8 +#define D0F0xBC_xE030008C_PowerDown_WIDTH 1 +#define D0F0xBC_xE030008C_PowerDown_MASK 0x100 +#define D0F0xBC_xE030008C_PowerUp_OFFSET 9 +#define D0F0xBC_xE030008C_PowerUp_WIDTH 1 +#define D0F0xBC_xE030008C_PowerUp_MASK 0x200 +#define D0F0xBC_xE030008C_P1Select_OFFSET 10 +#define D0F0xBC_xE030008C_P1Select_WIDTH 1 +#define D0F0xBC_xE030008C_P1Select_MASK 0x400 +#define D0F0xBC_xE030008C_P2Select_OFFSET 11 +#define D0F0xBC_xE030008C_P2Select_WIDTH 1 +#define D0F0xBC_xE030008C_P2Select_MASK 0x800 +#define D0F0xBC_xE030008C_WriteOp_OFFSET 12 +#define D0F0xBC_xE030008C_WriteOp_WIDTH 1 +#define D0F0xBC_xE030008C_WriteOp_MASK 0x1000 +#define D0F0xBC_xE030008C_ReadOp_OFFSET 13 +#define D0F0xBC_xE030008C_ReadOp_WIDTH 1 +#define D0F0xBC_xE030008C_ReadOp_MASK 0x2000 +#define D0F0xBC_xE030008C_Reserved_27_14_OFFSET 14 +#define D0F0xBC_xE030008C_Reserved_27_14_WIDTH 14 +#define D0F0xBC_xE030008C_Reserved_27_14_MASK 0xfffc000 +#define D0F0xBC_xE030008C_RegAddr_OFFSET 28 +#define D0F0xBC_xE030008C_RegAddr_WIDTH 4 +#define D0F0xBC_xE030008C_RegAddr_MASK 0xf0000000 + +/// D0F0xBC_xE030008C +typedef union { + struct { ///< + UINT32 FsmAddr:8 ; ///< + UINT32 PowerDown:1 ; ///< + UINT32 PowerUp:1 ; ///< + UINT32 P1Select:1 ; ///< + UINT32 P2Select:1 ; ///< + UINT32 WriteOp:1 ; ///< + UINT32 ReadOp:1 ; ///< + UINT32 Reserved_27_14:14; ///< + UINT32 RegAddr:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE030008C_STRUCT; + +// **** D0F0xBC_xE0300090 Register Definition **** +// Address +#define D0F0xBC_xE0300090_ADDRESS 0xe0300090 + +// Type +#define D0F0xBC_xE0300090_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0300090_WriteValue_OFFSET 0 +#define D0F0xBC_xE0300090_WriteValue_WIDTH 32 +#define D0F0xBC_xE0300090_WriteValue_MASK 0xffffffff + +/// D0F0xBC_xE0300090 +typedef union { + struct { ///< + UINT32 WriteValue:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0300090_STRUCT; + +// **** D0F0xBC_xE03000A8 Register Definition **** +// Address +#define D0F0xBC_xE03000A8_ADDRESS 0xe03000a8 + +// Type +#define D0F0xBC_xE03000A8_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE03000A8_FsmAddr_OFFSET 0 +#define D0F0xBC_xE03000A8_FsmAddr_WIDTH 8 +#define D0F0xBC_xE03000A8_FsmAddr_MASK 0xff +#define D0F0xBC_xE03000A8_PowerDown_OFFSET 8 +#define D0F0xBC_xE03000A8_PowerDown_WIDTH 1 +#define D0F0xBC_xE03000A8_PowerDown_MASK 0x100 +#define D0F0xBC_xE03000A8_PowerUp_OFFSET 9 +#define D0F0xBC_xE03000A8_PowerUp_WIDTH 1 +#define D0F0xBC_xE03000A8_PowerUp_MASK 0x200 +#define D0F0xBC_xE03000A8_P1Select_OFFSET 10 +#define D0F0xBC_xE03000A8_P1Select_WIDTH 1 +#define D0F0xBC_xE03000A8_P1Select_MASK 0x400 +#define D0F0xBC_xE03000A8_P2Select_OFFSET 11 +#define D0F0xBC_xE03000A8_P2Select_WIDTH 1 +#define D0F0xBC_xE03000A8_P2Select_MASK 0x800 +#define D0F0xBC_xE03000A8_WriteOp_OFFSET 12 +#define D0F0xBC_xE03000A8_WriteOp_WIDTH 1 +#define D0F0xBC_xE03000A8_WriteOp_MASK 0x1000 +#define D0F0xBC_xE03000A8_ReadOp_OFFSET 13 +#define D0F0xBC_xE03000A8_ReadOp_WIDTH 1 +#define D0F0xBC_xE03000A8_ReadOp_MASK 0x2000 +#define D0F0xBC_xE03000A8_Reserved_27_14_OFFSET 14 +#define D0F0xBC_xE03000A8_Reserved_27_14_WIDTH 14 +#define D0F0xBC_xE03000A8_Reserved_27_14_MASK 0xfffc000 +#define D0F0xBC_xE03000A8_RegAddr_OFFSET 28 +#define D0F0xBC_xE03000A8_RegAddr_WIDTH 4 +#define D0F0xBC_xE03000A8_RegAddr_MASK 0xf0000000 + +/// D0F0xBC_xE03000A8 +typedef union { + struct { ///< + UINT32 FsmAddr:8 ; ///< + UINT32 PowerDown:1 ; ///< + UINT32 PowerUp:1 ; ///< + UINT32 P1Select:1 ; ///< + UINT32 P2Select:1 ; ///< + UINT32 WriteOp:1 ; ///< + UINT32 ReadOp:1 ; ///< + UINT32 Reserved_27_14:14; ///< + UINT32 RegAddr:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE03000A8_STRUCT; + +// **** D0F0xBC_xE03000AC Register Definition **** +// Address +#define D0F0xBC_xE03000AC_ADDRESS 0xe03000ac + +// Type +#define D0F0xBC_xE03000AC_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE03000AC_WriteValue_OFFSET 0 +#define D0F0xBC_xE03000AC_WriteValue_WIDTH 32 +#define D0F0xBC_xE03000AC_WriteValue_MASK 0xffffffff + +/// D0F0xBC_xE03000AC +typedef union { + struct { ///< + UINT32 WriteValue:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE03000AC_STRUCT; + +// **** D0F0xBC_xE03000C4 Register Definition **** +// Address +#define D0F0xBC_xE03000C4_ADDRESS 0xe03000c4 + +// Type +#define D0F0xBC_xE03000C4_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE03000C4_FsmAddr_OFFSET 0 +#define D0F0xBC_xE03000C4_FsmAddr_WIDTH 8 +#define D0F0xBC_xE03000C4_FsmAddr_MASK 0xff +#define D0F0xBC_xE03000C4_PowerDown_OFFSET 8 +#define D0F0xBC_xE03000C4_PowerDown_WIDTH 1 +#define D0F0xBC_xE03000C4_PowerDown_MASK 0x100 +#define D0F0xBC_xE03000C4_PowerUp_OFFSET 9 +#define D0F0xBC_xE03000C4_PowerUp_WIDTH 1 +#define D0F0xBC_xE03000C4_PowerUp_MASK 0x200 +#define D0F0xBC_xE03000C4_P1Select_OFFSET 10 +#define D0F0xBC_xE03000C4_P1Select_WIDTH 1 +#define D0F0xBC_xE03000C4_P1Select_MASK 0x400 +#define D0F0xBC_xE03000C4_P2Select_OFFSET 11 +#define D0F0xBC_xE03000C4_P2Select_WIDTH 1 +#define D0F0xBC_xE03000C4_P2Select_MASK 0x800 +#define D0F0xBC_xE03000C4_WriteOp_OFFSET 12 +#define D0F0xBC_xE03000C4_WriteOp_WIDTH 1 +#define D0F0xBC_xE03000C4_WriteOp_MASK 0x1000 +#define D0F0xBC_xE03000C4_ReadOp_OFFSET 13 +#define D0F0xBC_xE03000C4_ReadOp_WIDTH 1 +#define D0F0xBC_xE03000C4_ReadOp_MASK 0x2000 +#define D0F0xBC_xE03000C4_Reserved_27_14_OFFSET 14 +#define D0F0xBC_xE03000C4_Reserved_27_14_WIDTH 14 +#define D0F0xBC_xE03000C4_Reserved_27_14_MASK 0xfffc000 +#define D0F0xBC_xE03000C4_RegAddr_OFFSET 28 +#define D0F0xBC_xE03000C4_RegAddr_WIDTH 4 +#define D0F0xBC_xE03000C4_RegAddr_MASK 0xf0000000 + +/// D0F0xBC_xE03000C4 +typedef union { + struct { ///< + UINT32 FsmAddr:8 ; ///< + UINT32 PowerDown:1 ; ///< + UINT32 PowerUp:1 ; ///< + UINT32 P1Select:1 ; ///< + UINT32 P2Select:1 ; ///< + UINT32 WriteOp:1 ; ///< + UINT32 ReadOp:1 ; ///< + UINT32 Reserved_27_14:14; ///< + UINT32 RegAddr:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE03000C4_STRUCT; + +// **** D0F0xBC_xE03000C8 Register Definition **** +// Address +#define D0F0xBC_xE03000C8_ADDRESS 0xe03000c8 + +// Type +#define D0F0xBC_xE03000C8_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE03000C8_WriteValue_OFFSET 0 +#define D0F0xBC_xE03000C8_WriteValue_WIDTH 32 +#define D0F0xBC_xE03000C8_WriteValue_MASK 0xffffffff + +/// D0F0xBC_xE03000C8 +typedef union { + struct { ///< + UINT32 WriteValue:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE03000C8_STRUCT; + +// **** D0F0xBC_xE03000E0 Register Definition **** +// Address +#define D0F0xBC_xE03000E0_ADDRESS 0xe03000e0 + +// Type +#define D0F0xBC_xE03000E0_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE03000E0_FsmAddr_OFFSET 0 +#define D0F0xBC_xE03000E0_FsmAddr_WIDTH 8 +#define D0F0xBC_xE03000E0_FsmAddr_MASK 0xff +#define D0F0xBC_xE03000E0_PowerDown_OFFSET 8 +#define D0F0xBC_xE03000E0_PowerDown_WIDTH 1 +#define D0F0xBC_xE03000E0_PowerDown_MASK 0x100 +#define D0F0xBC_xE03000E0_PowerUp_OFFSET 9 +#define D0F0xBC_xE03000E0_PowerUp_WIDTH 1 +#define D0F0xBC_xE03000E0_PowerUp_MASK 0x200 +#define D0F0xBC_xE03000E0_P1Select_OFFSET 10 +#define D0F0xBC_xE03000E0_P1Select_WIDTH 1 +#define D0F0xBC_xE03000E0_P1Select_MASK 0x400 +#define D0F0xBC_xE03000E0_P2Select_OFFSET 11 +#define D0F0xBC_xE03000E0_P2Select_WIDTH 1 +#define D0F0xBC_xE03000E0_P2Select_MASK 0x800 +#define D0F0xBC_xE03000E0_WriteOp_OFFSET 12 +#define D0F0xBC_xE03000E0_WriteOp_WIDTH 1 +#define D0F0xBC_xE03000E0_WriteOp_MASK 0x1000 +#define D0F0xBC_xE03000E0_ReadOp_OFFSET 13 +#define D0F0xBC_xE03000E0_ReadOp_WIDTH 1 +#define D0F0xBC_xE03000E0_ReadOp_MASK 0x2000 +#define D0F0xBC_xE03000E0_Reserved_27_14_OFFSET 14 +#define D0F0xBC_xE03000E0_Reserved_27_14_WIDTH 14 +#define D0F0xBC_xE03000E0_Reserved_27_14_MASK 0xfffc000 +#define D0F0xBC_xE03000E0_RegAddr_OFFSET 28 +#define D0F0xBC_xE03000E0_RegAddr_WIDTH 4 +#define D0F0xBC_xE03000E0_RegAddr_MASK 0xf0000000 + +/// D0F0xBC_xE03000E0 +typedef union { + struct { ///< + UINT32 FsmAddr:8 ; ///< + UINT32 PowerDown:1 ; ///< + UINT32 PowerUp:1 ; ///< + UINT32 P1Select:1 ; ///< + UINT32 P2Select:1 ; ///< + UINT32 WriteOp:1 ; ///< + UINT32 ReadOp:1 ; ///< + UINT32 Reserved_27_14:14; ///< + UINT32 RegAddr:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE03000E0_STRUCT; + +// **** D0F0xBC_xE03000E4 Register Definition **** +// Address +#define D0F0xBC_xE03000E4_ADDRESS 0xe03000e4 + +// Type +#define D0F0xBC_xE03000E4_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE03000E4_WriteValue_OFFSET 0 +#define D0F0xBC_xE03000E4_WriteValue_WIDTH 32 +#define D0F0xBC_xE03000E4_WriteValue_MASK 0xffffffff + +/// D0F0xBC_xE03000E4 +typedef union { + struct { ///< + UINT32 WriteValue:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE03000E4_STRUCT; + +// **** D0F0xBC_xE03000FC Register Definition **** +// Address +#define D0F0xBC_xE03000FC_ADDRESS 0xe03000fc + +// Type +#define D0F0xBC_xE03000FC_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE03000FC_FsmAddr_OFFSET 0 +#define D0F0xBC_xE03000FC_FsmAddr_WIDTH 8 +#define D0F0xBC_xE03000FC_FsmAddr_MASK 0xff +#define D0F0xBC_xE03000FC_PowerDown_OFFSET 8 +#define D0F0xBC_xE03000FC_PowerDown_WIDTH 1 +#define D0F0xBC_xE03000FC_PowerDown_MASK 0x100 +#define D0F0xBC_xE03000FC_PowerUp_OFFSET 9 +#define D0F0xBC_xE03000FC_PowerUp_WIDTH 1 +#define D0F0xBC_xE03000FC_PowerUp_MASK 0x200 +#define D0F0xBC_xE03000FC_P1Select_OFFSET 10 +#define D0F0xBC_xE03000FC_P1Select_WIDTH 1 +#define D0F0xBC_xE03000FC_P1Select_MASK 0x400 +#define D0F0xBC_xE03000FC_P2Select_OFFSET 11 +#define D0F0xBC_xE03000FC_P2Select_WIDTH 1 +#define D0F0xBC_xE03000FC_P2Select_MASK 0x800 +#define D0F0xBC_xE03000FC_WriteOp_OFFSET 12 +#define D0F0xBC_xE03000FC_WriteOp_WIDTH 1 +#define D0F0xBC_xE03000FC_WriteOp_MASK 0x1000 +#define D0F0xBC_xE03000FC_ReadOp_OFFSET 13 +#define D0F0xBC_xE03000FC_ReadOp_WIDTH 1 +#define D0F0xBC_xE03000FC_ReadOp_MASK 0x2000 +#define D0F0xBC_xE03000FC_Reserved_27_14_OFFSET 14 +#define D0F0xBC_xE03000FC_Reserved_27_14_WIDTH 14 +#define D0F0xBC_xE03000FC_Reserved_27_14_MASK 0xfffc000 +#define D0F0xBC_xE03000FC_RegAddr_OFFSET 28 +#define D0F0xBC_xE03000FC_RegAddr_WIDTH 4 +#define D0F0xBC_xE03000FC_RegAddr_MASK 0xf0000000 + +/// D0F0xBC_xE03000FC +typedef union { + struct { ///< + UINT32 FsmAddr:8 ; ///< + UINT32 PowerDown:1 ; ///< + UINT32 PowerUp:1 ; ///< + UINT32 P1Select:1 ; ///< + UINT32 P2Select:1 ; ///< + UINT32 WriteOp:1 ; ///< + UINT32 ReadOp:1 ; ///< + UINT32 Reserved_27_14:14; ///< + UINT32 RegAddr:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE03000FC_STRUCT; + +// **** D0F0xBC_xE0300100 Register Definition **** +// Address +#define D0F0xBC_xE0300100_ADDRESS 0xe0300100 + +// Type +#define D0F0xBC_xE0300100_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0300100_WriteValue_OFFSET 0 +#define D0F0xBC_xE0300100_WriteValue_WIDTH 32 +#define D0F0xBC_xE0300100_WriteValue_MASK 0xffffffff + +/// D0F0xBC_xE0300100 +typedef union { + struct { ///< + UINT32 WriteValue:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0300100_STRUCT; + +// **** D0F0xBC_xE0300200 Register Definition **** +// Address +#define D0F0xBC_xE0300200_ADDRESS 0xe0300200 + +// Type +#define D0F0xBC_xE0300200_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0300200_Reserved_9_0_OFFSET 0 +#define D0F0xBC_xE0300200_Reserved_9_0_WIDTH 10 +#define D0F0xBC_xE0300200_Reserved_9_0_MASK 0x3ff +#define D0F0xBC_xE0300200_P1IsoN_OFFSET 10 +#define D0F0xBC_xE0300200_P1IsoN_WIDTH 1 +#define D0F0xBC_xE0300200_P1IsoN_MASK 0x400 +#define D0F0xBC_xE0300200_Reserved_31_11_OFFSET 11 +#define D0F0xBC_xE0300200_Reserved_31_11_WIDTH 21 +#define D0F0xBC_xE0300200_Reserved_31_11_MASK 0xfffff800 + +/// D0F0xBC_xE0300200 +typedef union { + struct { ///< + UINT32 Reserved_9_0:10; ///< + UINT32 P1IsoN:1 ; ///< + UINT32 Reserved_31_11:21; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0300200_STRUCT; + + +// Type +#define D0F0xBC_xE0300208_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0300208_Reserved_9_0_OFFSET 0 +#define D0F0xBC_xE0300208_Reserved_9_0_WIDTH 10 +#define D0F0xBC_xE0300208_Reserved_9_0_MASK 0x3ff +#define D0F0xBC_xE0300208_P1IsoN_OFFSET 10 +#define D0F0xBC_xE0300208_P1IsoN_WIDTH 1 +#define D0F0xBC_xE0300208_P1IsoN_MASK 0x400 +#define D0F0xBC_xE0300208_Reserved_12_11_OFFSET 11 +#define D0F0xBC_xE0300208_Reserved_12_11_WIDTH 2 +#define D0F0xBC_xE0300208_Reserved_12_11_MASK 0x1800 +#define D0F0xBC_xE0300208_P1PsoDaug_OFFSET 13 +#define D0F0xBC_xE0300208_P1PsoDaug_WIDTH 1 +#define D0F0xBC_xE0300208_P1PsoDaug_MASK 0x2000 +#define D0F0xBC_xE0300208_Reserved_31_14_OFFSET 14 +#define D0F0xBC_xE0300208_Reserved_31_14_WIDTH 18 +#define D0F0xBC_xE0300208_Reserved_31_14_MASK 0xffffc000 + +/// D0F0xBC_xE0300208 +typedef union { + struct { ///< + UINT32 Reserved_9_0:10; ///< + UINT32 P1IsoN:1 ; ///< + UINT32 Reserved_12_11:2 ; ///< + UINT32 :1 ; ///< + UINT32 Reserved_31_14:18; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0300208_STRUCT; + +// **** D0F0xBC_xE030020C Register Definition **** +// Address +#define D0F0xBC_xE030020C_ADDRESS 0xe030020c + +// Type +#define D0F0xBC_xE030020C_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE030020C_Reserved_9_0_OFFSET 0 +#define D0F0xBC_xE030020C_Reserved_9_0_WIDTH 10 +#define D0F0xBC_xE030020C_Reserved_9_0_MASK 0x3ff +#define D0F0xBC_xE030020C_P1IsoN_OFFSET 10 +#define D0F0xBC_xE030020C_P1IsoN_WIDTH 1 +#define D0F0xBC_xE030020C_P1IsoN_MASK 0x400 +#define D0F0xBC_xE030020C_Reserved_31_11_OFFSET 11 +#define D0F0xBC_xE030020C_Reserved_31_11_WIDTH 21 +#define D0F0xBC_xE030020C_Reserved_31_11_MASK 0xfffff800 + +/// D0F0xBC_xE030020C +typedef union { + struct { ///< + UINT32 Reserved_9_0:10; ///< + UINT32 P1IsoN:1 ; ///< + UINT32 Reserved_31_11:21; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE030020C_STRUCT; + +// **** D0F0xBC_xE0300210 Register Definition **** +// Address +#define D0F0xBC_xE0300210_ADDRESS 0xe0300210 + +// Type +#define D0F0xBC_xE0300210_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0300210_Reserved_9_0_OFFSET 0 +#define D0F0xBC_xE0300210_Reserved_9_0_WIDTH 10 +#define D0F0xBC_xE0300210_Reserved_9_0_MASK 0x3ff +#define D0F0xBC_xE0300210_P1IsoN_OFFSET 10 +#define D0F0xBC_xE0300210_P1IsoN_WIDTH 1 +#define D0F0xBC_xE0300210_P1IsoN_MASK 0x400 +#define D0F0xBC_xE0300210_Reserved_12_11_OFFSET 11 +#define D0F0xBC_xE0300210_Reserved_12_11_WIDTH 2 +#define D0F0xBC_xE0300210_Reserved_12_11_MASK 0x1800 +#define D0F0xBC_xE0300210_Reserved_31_14_OFFSET 14 +#define D0F0xBC_xE0300210_Reserved_31_14_WIDTH 18 +#define D0F0xBC_xE0300210_Reserved_31_14_MASK 0xffffc000 + +/// D0F0xBC_xE0300210 +typedef union { + struct { ///< + UINT32 Reserved_9_0:10; ///< + UINT32 P1IsoN:1 ; ///< + UINT32 Reserved_12_11:2 ; ///< + UINT32 :1 ; ///< + UINT32 Reserved_31_14:18; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0300210_STRUCT; + +// **** D0F0xBC_xE0300218 Register Definition **** +// Address +#define D0F0xBC_xE0300218_ADDRESS 0xe0300218 + +// Type +#define D0F0xBC_xE0300218_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0300218_Reserved_9_0_OFFSET 0 +#define D0F0xBC_xE0300218_Reserved_9_0_WIDTH 10 +#define D0F0xBC_xE0300218_Reserved_9_0_MASK 0x3ff +#define D0F0xBC_xE0300218_P1IsoN_OFFSET 10 +#define D0F0xBC_xE0300218_P1IsoN_WIDTH 1 +#define D0F0xBC_xE0300218_P1IsoN_MASK 0x400 +#define D0F0xBC_xE0300218_Reserved_31_11_OFFSET 11 +#define D0F0xBC_xE0300218_Reserved_31_11_WIDTH 21 +#define D0F0xBC_xE0300218_Reserved_31_11_MASK 0xfffff800 + +/// D0F0xBC_xE0300218 +typedef union { + struct { ///< + UINT32 Reserved_9_0:10; ///< + UINT32 P1IsoN:1 ; ///< + UINT32 Reserved_31_11:21; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0300218_STRUCT; + +// **** D0F0xBC_xE03002DC Register Definition **** +// Address +#define D0F0xBC_xE03002DC_ADDRESS 0xe03002dc + +// Type +#define D0F0xBC_xE03002DC_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE03002DC_DC2_PGFSM_CONTROL_OFFSET 0 +#define D0F0xBC_xE03002DC_DC2_PGFSM_CONTROL_WIDTH 1 +#define D0F0xBC_xE03002DC_DC2_PGFSM_CONTROL_MASK 0x1 +#define D0F0xBC_xE03002DC_Reserved_OFFSET 1 +#define D0F0xBC_xE03002DC_Reserved_WIDTH 31 +#define D0F0xBC_xE03002DC_Reserved_MASK 0xfffffffe + +/// D0F0xBC_xE03002DC +typedef union { + struct { ///< + UINT32 DC2_PGFSM_CONTROL:1 ; ///< + UINT32 Reserved:31; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE03002DC_STRUCT; + +// **** D0F0xBC_xE03002E4 Register Definition **** +// Address +#define D0F0xBC_xE03002E4_ADDRESS 0xe03002e4 + +// Type +#define D0F0xBC_xE03002E4_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE03002E4_SmuCb0PsoDaug_OFFSET 0 +#define D0F0xBC_xE03002E4_SmuCb0PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002E4_SmuCb0PsoDaug_MASK 0x1 +#define D0F0xBC_xE03002E4_SmuCb1PsoDaug_OFFSET 1 +#define D0F0xBC_xE03002E4_SmuCb1PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002E4_SmuCb1PsoDaug_MASK 0x2 +#define D0F0xBC_xE03002E4_SmuDb0PsoDaug_OFFSET 2 +#define D0F0xBC_xE03002E4_SmuDb0PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002E4_SmuDb0PsoDaug_MASK 0x4 +#define D0F0xBC_xE03002E4_SmuDb1PsoDaug_OFFSET 3 +#define D0F0xBC_xE03002E4_SmuDb1PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002E4_SmuDb1PsoDaug_MASK 0x8 +#define D0F0xBC_xE03002E4_SmuPaPsoDaug_OFFSET 4 +#define D0F0xBC_xE03002E4_SmuPaPsoDaug_WIDTH 1 +#define D0F0xBC_xE03002E4_SmuPaPsoDaug_MASK 0x10 +#define D0F0xBC_xE03002E4_SmuSpmPsoDaug_OFFSET 5 +#define D0F0xBC_xE03002E4_SmuSpmPsoDaug_WIDTH 1 +#define D0F0xBC_xE03002E4_SmuSpmPsoDaug_MASK 0x20 +#define D0F0xBC_xE03002E4_SmuSpsPsoDaug_OFFSET 6 +#define D0F0xBC_xE03002E4_SmuSpsPsoDaug_WIDTH 1 +#define D0F0xBC_xE03002E4_SmuSpsPsoDaug_MASK 0x40 +#define D0F0xBC_xE03002E4_SmuSqbPsoDaug_OFFSET 7 +#define D0F0xBC_xE03002E4_SmuSqbPsoDaug_WIDTH 1 +#define D0F0xBC_xE03002E4_SmuSqbPsoDaug_MASK 0x80 +#define D0F0xBC_xE03002E4_SmuSxmPsoDaug_OFFSET 8 +#define D0F0xBC_xE03002E4_SmuSxmPsoDaug_WIDTH 1 +#define D0F0xBC_xE03002E4_SmuSxmPsoDaug_MASK 0x100 +#define D0F0xBC_xE03002E4_SmuSxs0PsoDaug_OFFSET 9 +#define D0F0xBC_xE03002E4_SmuSxs0PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002E4_SmuSxs0PsoDaug_MASK 0x200 +#define D0F0xBC_xE03002E4_SmuSxs1PsoDaug_OFFSET 10 +#define D0F0xBC_xE03002E4_SmuSxs1PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002E4_SmuSxs1PsoDaug_MASK 0x400 +#define D0F0xBC_xE03002E4_SmuXbrPsoDaug_OFFSET 11 +#define D0F0xBC_xE03002E4_SmuXbrPsoDaug_WIDTH 1 +#define D0F0xBC_xE03002E4_SmuXbrPsoDaug_MASK 0x800 +#define D0F0xBC_xE03002E4_SmuGdsPsoDaug_OFFSET 12 +#define D0F0xBC_xE03002E4_SmuGdsPsoDaug_WIDTH 1 +#define D0F0xBC_xE03002E4_SmuGdsPsoDaug_MASK 0x1000 +#define D0F0xBC_xE03002E4_SmuVgtPsoDaug_OFFSET 13 +#define D0F0xBC_xE03002E4_SmuVgtPsoDaug_WIDTH 1 +#define D0F0xBC_xE03002E4_SmuVgtPsoDaug_MASK 0x2000 +#define D0F0xBC_xE03002E4_SmuSqaPsoDaug_OFFSET 14 +#define D0F0xBC_xE03002E4_SmuSqaPsoDaug_WIDTH 1 +#define D0F0xBC_xE03002E4_SmuSqaPsoDaug_MASK 0x4000 +#define D0F0xBC_xE03002E4_SmuSqcPsoDaug_OFFSET 15 +#define D0F0xBC_xE03002E4_SmuSqcPsoDaug_WIDTH 1 +#define D0F0xBC_xE03002E4_SmuSqcPsoDaug_MASK 0x8000 +#define D0F0xBC_xE03002E4_SmuTcPsoDaug_OFFSET 16 +#define D0F0xBC_xE03002E4_SmuTcPsoDaug_WIDTH 1 +#define D0F0xBC_xE03002E4_SmuTcPsoDaug_MASK 0x10000 +#define D0F0xBC_xE03002E4_SmuScPsoDaug_OFFSET 17 +#define D0F0xBC_xE03002E4_SmuScPsoDaug_WIDTH 1 +#define D0F0xBC_xE03002E4_SmuScPsoDaug_MASK 0x20000 +#define D0F0xBC_xE03002E4_Reserved_31_18_OFFSET 18 +#define D0F0xBC_xE03002E4_Reserved_31_18_WIDTH 14 +#define D0F0xBC_xE03002E4_Reserved_31_18_MASK 0xfffc0000 + +/// D0F0xBC_xE03002E4 +typedef union { + struct { ///< + UINT32 SmuCb0PsoDaug:1 ; ///< + UINT32 SmuCb1PsoDaug:1 ; ///< + UINT32 SmuDb0PsoDaug:1 ; ///< + UINT32 SmuDb1PsoDaug:1 ; ///< + UINT32 SmuPaPsoDaug:1 ; ///< + UINT32 SmuSpmPsoDaug:1 ; ///< + UINT32 SmuSpsPsoDaug:1 ; ///< + UINT32 SmuSqbPsoDaug:1 ; ///< + UINT32 SmuSxmPsoDaug:1 ; ///< + UINT32 SmuSxs0PsoDaug:1 ; ///< + UINT32 SmuSxs1PsoDaug:1 ; ///< + UINT32 SmuXbrPsoDaug:1 ; ///< + UINT32 SmuGdsPsoDaug:1 ; ///< + UINT32 SmuVgtPsoDaug:1 ; ///< + UINT32 SmuSqaPsoDaug:1 ; ///< + UINT32 SmuSqcPsoDaug:1 ; ///< + UINT32 SmuTcPsoDaug:1 ; ///< + UINT32 SmuScPsoDaug:1 ; ///< + UINT32 Reserved_31_18:14; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE03002E4_STRUCT; + +// **** D0F0xBC_xE03002F0 Register Definition **** +// Address +#define D0F0xBC_xE03002F0_ADDRESS 0xe03002f0 + +// Type +#define D0F0xBC_xE03002F0_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE03002F0_SmuTatd0P1IsoN_OFFSET 0 +#define D0F0xBC_xE03002F0_SmuTatd0P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuTatd0P1IsoN_MASK 0x1 +#define D0F0xBC_xE03002F0_SmuSp000P1IsoN_OFFSET 1 +#define D0F0xBC_xE03002F0_SmuSp000P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuSp000P1IsoN_MASK 0x2 +#define D0F0xBC_xE03002F0_SmuSp002P1IsoN_OFFSET 2 +#define D0F0xBC_xE03002F0_SmuSp002P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuSp002P1IsoN_MASK 0x4 +#define D0F0xBC_xE03002F0_SmuLds0P1IsoN_OFFSET 3 +#define D0F0xBC_xE03002F0_SmuLds0P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuLds0P1IsoN_MASK 0x8 +#define D0F0xBC_xE03002F0_SmuTcp0P1IsoN_OFFSET 4 +#define D0F0xBC_xE03002F0_SmuTcp0P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuTcp0P1IsoN_MASK 0x10 +#define D0F0xBC_xE03002F0_SmuTatd1P1IsoN_OFFSET 5 +#define D0F0xBC_xE03002F0_SmuTatd1P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuTatd1P1IsoN_MASK 0x20 +#define D0F0xBC_xE03002F0_SmuSp010P1IsoN_OFFSET 6 +#define D0F0xBC_xE03002F0_SmuSp010P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuSp010P1IsoN_MASK 0x40 +#define D0F0xBC_xE03002F0_SmuSp012P1IsoN_OFFSET 7 +#define D0F0xBC_xE03002F0_SmuSp012P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuSp012P1IsoN_MASK 0x80 +#define D0F0xBC_xE03002F0_SmuLds1P1IsoN_OFFSET 8 +#define D0F0xBC_xE03002F0_SmuLds1P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuLds1P1IsoN_MASK 0x100 +#define D0F0xBC_xE03002F0_SmuTcp1P1IsoN_OFFSET 9 +#define D0F0xBC_xE03002F0_SmuTcp1P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuTcp1P1IsoN_MASK 0x200 +#define D0F0xBC_xE03002F0_SmuTatd2P1IsoN_OFFSET 10 +#define D0F0xBC_xE03002F0_SmuTatd2P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuTatd2P1IsoN_MASK 0x400 +#define D0F0xBC_xE03002F0_SmuSp020P1IsoN_OFFSET 11 +#define D0F0xBC_xE03002F0_SmuSp020P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuSp020P1IsoN_MASK 0x800 +#define D0F0xBC_xE03002F0_SmuSp022P1IsoN_OFFSET 12 +#define D0F0xBC_xE03002F0_SmuSp022P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuSp022P1IsoN_MASK 0x1000 +#define D0F0xBC_xE03002F0_SmuLds2P1IsoN_OFFSET 13 +#define D0F0xBC_xE03002F0_SmuLds2P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuLds2P1IsoN_MASK 0x2000 +#define D0F0xBC_xE03002F0_SmuTcp2P1IsoN_OFFSET 14 +#define D0F0xBC_xE03002F0_SmuTcp2P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuTcp2P1IsoN_MASK 0x4000 +#define D0F0xBC_xE03002F0_SmuTatd3P1IsoN_OFFSET 15 +#define D0F0xBC_xE03002F0_SmuTatd3P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuTatd3P1IsoN_MASK 0x8000 +#define D0F0xBC_xE03002F0_SmuSp030P1IsoN_OFFSET 16 +#define D0F0xBC_xE03002F0_SmuSp030P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuSp030P1IsoN_MASK 0x10000 +#define D0F0xBC_xE03002F0_SmuSp032P1IsoN_OFFSET 17 +#define D0F0xBC_xE03002F0_SmuSp032P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuSp032P1IsoN_MASK 0x20000 +#define D0F0xBC_xE03002F0_SmuLds3P1IsoN_OFFSET 18 +#define D0F0xBC_xE03002F0_SmuLds3P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuLds3P1IsoN_MASK 0x40000 +#define D0F0xBC_xE03002F0_SmuTcp3P1IsoN_OFFSET 19 +#define D0F0xBC_xE03002F0_SmuTcp3P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuTcp3P1IsoN_MASK 0x80000 +#define D0F0xBC_xE03002F0_SmuTatd4P1IsoN_OFFSET 20 +#define D0F0xBC_xE03002F0_SmuTatd4P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuTatd4P1IsoN_MASK 0x100000 +#define D0F0xBC_xE03002F0_SmuSp040P1IsoN_OFFSET 21 +#define D0F0xBC_xE03002F0_SmuSp040P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuSp040P1IsoN_MASK 0x200000 +#define D0F0xBC_xE03002F0_SmuSp042P1IsoN_OFFSET 22 +#define D0F0xBC_xE03002F0_SmuSp042P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuSp042P1IsoN_MASK 0x400000 +#define D0F0xBC_xE03002F0_SmuLds4P1IsoN_OFFSET 23 +#define D0F0xBC_xE03002F0_SmuLds4P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuLds4P1IsoN_MASK 0x800000 +#define D0F0xBC_xE03002F0_SmuTcp4P1IsoN_OFFSET 24 +#define D0F0xBC_xE03002F0_SmuTcp4P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuTcp4P1IsoN_MASK 0x1000000 +#define D0F0xBC_xE03002F0_SmuTatd5P1IsoN_OFFSET 25 +#define D0F0xBC_xE03002F0_SmuTatd5P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuTatd5P1IsoN_MASK 0x2000000 +#define D0F0xBC_xE03002F0_SmuSp050P1IsoN_OFFSET 26 +#define D0F0xBC_xE03002F0_SmuSp050P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuSp050P1IsoN_MASK 0x4000000 +#define D0F0xBC_xE03002F0_SmuSp052P1IsoN_OFFSET 27 +#define D0F0xBC_xE03002F0_SmuSp052P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuSp052P1IsoN_MASK 0x8000000 +#define D0F0xBC_xE03002F0_SmuLds5P1IsoN_OFFSET 28 +#define D0F0xBC_xE03002F0_SmuLds5P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuLds5P1IsoN_MASK 0x10000000 +#define D0F0xBC_xE03002F0_SmuTcp5P1IsoN_OFFSET 29 +#define D0F0xBC_xE03002F0_SmuTcp5P1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F0_SmuTcp5P1IsoN_MASK 0x20000000 +#define D0F0xBC_xE03002F0_Reserved_31_30_OFFSET 30 +#define D0F0xBC_xE03002F0_Reserved_31_30_WIDTH 2 +#define D0F0xBC_xE03002F0_Reserved_31_30_MASK 0xc0000000 + +/// D0F0xBC_xE03002F0 +typedef union { + struct { ///< + UINT32 SmuTatd0P1IsoN:1 ; ///< + UINT32 SmuSp000P1IsoN:1 ; ///< + UINT32 SmuSp002P1IsoN:1 ; ///< + UINT32 SmuLds0P1IsoN:1 ; ///< + UINT32 SmuTcp0P1IsoN:1 ; ///< + UINT32 SmuTatd1P1IsoN:1 ; ///< + UINT32 SmuSp010P1IsoN:1 ; ///< + UINT32 SmuSp012P1IsoN:1 ; ///< + UINT32 SmuLds1P1IsoN:1 ; ///< + UINT32 SmuTcp1P1IsoN:1 ; ///< + UINT32 SmuTatd2P1IsoN:1 ; ///< + UINT32 SmuSp020P1IsoN:1 ; ///< + UINT32 SmuSp022P1IsoN:1 ; ///< + UINT32 SmuLds2P1IsoN:1 ; ///< + UINT32 SmuTcp2P1IsoN:1 ; ///< + UINT32 SmuTatd3P1IsoN:1 ; ///< + UINT32 SmuSp030P1IsoN:1 ; ///< + UINT32 SmuSp032P1IsoN:1 ; ///< + UINT32 SmuLds3P1IsoN:1 ; ///< + UINT32 SmuTcp3P1IsoN:1 ; ///< + UINT32 SmuTatd4P1IsoN:1 ; ///< + UINT32 SmuSp040P1IsoN:1 ; ///< + UINT32 SmuSp042P1IsoN:1 ; ///< + UINT32 SmuLds4P1IsoN:1 ; ///< + UINT32 SmuTcp4P1IsoN:1 ; ///< + UINT32 SmuTatd5P1IsoN:1 ; ///< + UINT32 SmuSp050P1IsoN:1 ; ///< + UINT32 SmuSp052P1IsoN:1 ; ///< + UINT32 SmuLds5P1IsoN:1 ; ///< + UINT32 SmuTcp5P1IsoN:1 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE03002F0_STRUCT; + +// **** D0F0xBC_xE03002F4 Register Definition **** +// Address +#define D0F0xBC_xE03002F4_ADDRESS 0xe03002f4 + +// Type +#define D0F0xBC_xE03002F4_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE03002F4_SmuCb0IsoN_OFFSET 0 +#define D0F0xBC_xE03002F4_SmuCb0IsoN_WIDTH 1 +#define D0F0xBC_xE03002F4_SmuCb0IsoN_MASK 0x1 +#define D0F0xBC_xE03002F4_SmuCb1IsoN_OFFSET 1 +#define D0F0xBC_xE03002F4_SmuCb1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F4_SmuCb1IsoN_MASK 0x2 +#define D0F0xBC_xE03002F4_SmuDb0IsoN_OFFSET 2 +#define D0F0xBC_xE03002F4_SmuDb0IsoN_WIDTH 1 +#define D0F0xBC_xE03002F4_SmuDb0IsoN_MASK 0x4 +#define D0F0xBC_xE03002F4_SmuDb1IsoN_OFFSET 3 +#define D0F0xBC_xE03002F4_SmuDb1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F4_SmuDb1IsoN_MASK 0x8 +#define D0F0xBC_xE03002F4_SmuPaIsoN_OFFSET 4 +#define D0F0xBC_xE03002F4_SmuPaIsoN_WIDTH 1 +#define D0F0xBC_xE03002F4_SmuPaIsoN_MASK 0x10 +#define D0F0xBC_xE03002F4_SmuSpmIsoN_OFFSET 5 +#define D0F0xBC_xE03002F4_SmuSpmIsoN_WIDTH 1 +#define D0F0xBC_xE03002F4_SmuSpmIsoN_MASK 0x20 +#define D0F0xBC_xE03002F4_SmuSpsIsoN_OFFSET 6 +#define D0F0xBC_xE03002F4_SmuSpsIsoN_WIDTH 1 +#define D0F0xBC_xE03002F4_SmuSpsIsoN_MASK 0x40 +#define D0F0xBC_xE03002F4_SmuSqbIsoN_OFFSET 7 +#define D0F0xBC_xE03002F4_SmuSqbIsoN_WIDTH 1 +#define D0F0xBC_xE03002F4_SmuSqbIsoN_MASK 0x80 +#define D0F0xBC_xE03002F4_SmuSxmIsoN_OFFSET 8 +#define D0F0xBC_xE03002F4_SmuSxmIsoN_WIDTH 1 +#define D0F0xBC_xE03002F4_SmuSxmIsoN_MASK 0x100 +#define D0F0xBC_xE03002F4_SmuSxs0IsoN_OFFSET 9 +#define D0F0xBC_xE03002F4_SmuSxs0IsoN_WIDTH 1 +#define D0F0xBC_xE03002F4_SmuSxs0IsoN_MASK 0x200 +#define D0F0xBC_xE03002F4_SmuSxs1IsoN_OFFSET 10 +#define D0F0xBC_xE03002F4_SmuSxs1IsoN_WIDTH 1 +#define D0F0xBC_xE03002F4_SmuSxs1IsoN_MASK 0x400 +#define D0F0xBC_xE03002F4_SmuXbrIsoN_OFFSET 11 +#define D0F0xBC_xE03002F4_SmuXbrIsoN_WIDTH 1 +#define D0F0xBC_xE03002F4_SmuXbrIsoN_MASK 0x800 +#define D0F0xBC_xE03002F4_SmuGdsIsoN_OFFSET 12 +#define D0F0xBC_xE03002F4_SmuGdsIsoN_WIDTH 1 +#define D0F0xBC_xE03002F4_SmuGdsIsoN_MASK 0x1000 +#define D0F0xBC_xE03002F4_SmuVgtIsoN_OFFSET 13 +#define D0F0xBC_xE03002F4_SmuVgtIsoN_WIDTH 1 +#define D0F0xBC_xE03002F4_SmuVgtIsoN_MASK 0x2000 +#define D0F0xBC_xE03002F4_SmuSqaIsoN_OFFSET 14 +#define D0F0xBC_xE03002F4_SmuSqaIsoN_WIDTH 1 +#define D0F0xBC_xE03002F4_SmuSqaIsoN_MASK 0x4000 +#define D0F0xBC_xE03002F4_SmuSqcIsoN_OFFSET 15 +#define D0F0xBC_xE03002F4_SmuSqcIsoN_WIDTH 1 +#define D0F0xBC_xE03002F4_SmuSqcIsoN_MASK 0x8000 +#define D0F0xBC_xE03002F4_SmuTcIsoN_OFFSET 16 +#define D0F0xBC_xE03002F4_SmuTcIsoN_WIDTH 1 +#define D0F0xBC_xE03002F4_SmuTcIsoN_MASK 0x10000 +#define D0F0xBC_xE03002F4_SmuScIsoN_OFFSET 17 +#define D0F0xBC_xE03002F4_SmuScIsoN_WIDTH 1 +#define D0F0xBC_xE03002F4_SmuScIsoN_MASK 0x20000 +#define D0F0xBC_xE03002F4_Reserved_31_18_OFFSET 18 +#define D0F0xBC_xE03002F4_Reserved_31_18_WIDTH 14 +#define D0F0xBC_xE03002F4_Reserved_31_18_MASK 0xfffc0000 + +/// D0F0xBC_xE03002F4 +typedef union { + struct { ///< + UINT32 SmuCb0IsoN:1 ; ///< + UINT32 SmuCb1IsoN:1 ; ///< + UINT32 SmuDb0IsoN:1 ; ///< + UINT32 SmuDb1IsoN:1 ; ///< + UINT32 SmuPaIsoN:1 ; ///< + UINT32 SmuSpmIsoN:1 ; ///< + UINT32 SmuSpsIsoN:1 ; ///< + UINT32 SmuSqbIsoN:1 ; ///< + UINT32 SmuSxmIsoN:1 ; ///< + UINT32 SmuSxs0IsoN:1 ; ///< + UINT32 SmuSxs1IsoN:1 ; ///< + UINT32 SmuXbrIsoN:1 ; ///< + UINT32 SmuGdsIsoN:1 ; ///< + UINT32 SmuVgtIsoN:1 ; ///< + UINT32 SmuSqaIsoN:1 ; ///< + UINT32 SmuSqcIsoN:1 ; ///< + UINT32 SmuTcIsoN:1 ; ///< + UINT32 SmuScIsoN:1 ; ///< + UINT32 Reserved_31_18:14; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE03002F4_STRUCT; + +// **** D0F0xBC_xE03002F8 Register Definition **** +// Address +#define D0F0xBC_xE03002F8_ADDRESS 0xe03002f8 + +// Type +#define D0F0xBC_xE03002F8_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE03002F8_SmuTatd0P2IsoN_OFFSET 0 +#define D0F0xBC_xE03002F8_SmuTatd0P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuTatd0P2IsoN_MASK 0x1 +#define D0F0xBC_xE03002F8_SmuSp000P2IsoN_OFFSET 1 +#define D0F0xBC_xE03002F8_SmuSp000P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuSp000P2IsoN_MASK 0x2 +#define D0F0xBC_xE03002F8_SmuSp002P2IsoN_OFFSET 2 +#define D0F0xBC_xE03002F8_SmuSp002P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuSp002P2IsoN_MASK 0x4 +#define D0F0xBC_xE03002F8_SmuLds0P2IsoN_OFFSET 3 +#define D0F0xBC_xE03002F8_SmuLds0P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuLds0P2IsoN_MASK 0x8 +#define D0F0xBC_xE03002F8_SmuTcp0P2IsoN_OFFSET 4 +#define D0F0xBC_xE03002F8_SmuTcp0P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuTcp0P2IsoN_MASK 0x10 +#define D0F0xBC_xE03002F8_SmuTatd1P2IsoN_OFFSET 5 +#define D0F0xBC_xE03002F8_SmuTatd1P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuTatd1P2IsoN_MASK 0x20 +#define D0F0xBC_xE03002F8_SmuSp010P2IsoN_OFFSET 6 +#define D0F0xBC_xE03002F8_SmuSp010P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuSp010P2IsoN_MASK 0x40 +#define D0F0xBC_xE03002F8_SmuSp012P2IsoN_OFFSET 7 +#define D0F0xBC_xE03002F8_SmuSp012P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuSp012P2IsoN_MASK 0x80 +#define D0F0xBC_xE03002F8_SmuLds1P2IsoN_OFFSET 8 +#define D0F0xBC_xE03002F8_SmuLds1P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuLds1P2IsoN_MASK 0x100 +#define D0F0xBC_xE03002F8_SmuTcp1P2IsoN_OFFSET 9 +#define D0F0xBC_xE03002F8_SmuTcp1P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuTcp1P2IsoN_MASK 0x200 +#define D0F0xBC_xE03002F8_SmuTatd2P2IsoN_OFFSET 10 +#define D0F0xBC_xE03002F8_SmuTatd2P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuTatd2P2IsoN_MASK 0x400 +#define D0F0xBC_xE03002F8_SmuSp020P2IsoN_OFFSET 11 +#define D0F0xBC_xE03002F8_SmuSp020P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuSp020P2IsoN_MASK 0x800 +#define D0F0xBC_xE03002F8_SmuSp022P2IsoN_OFFSET 12 +#define D0F0xBC_xE03002F8_SmuSp022P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuSp022P2IsoN_MASK 0x1000 +#define D0F0xBC_xE03002F8_SmuLds2P2IsoN_OFFSET 13 +#define D0F0xBC_xE03002F8_SmuLds2P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuLds2P2IsoN_MASK 0x2000 +#define D0F0xBC_xE03002F8_SmuTcp2P2IsoN_OFFSET 14 +#define D0F0xBC_xE03002F8_SmuTcp2P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuTcp2P2IsoN_MASK 0x4000 +#define D0F0xBC_xE03002F8_SmuTatd3P2IsoN_OFFSET 15 +#define D0F0xBC_xE03002F8_SmuTatd3P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuTatd3P2IsoN_MASK 0x8000 +#define D0F0xBC_xE03002F8_SmuSp030P2IsoN_OFFSET 16 +#define D0F0xBC_xE03002F8_SmuSp030P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuSp030P2IsoN_MASK 0x10000 +#define D0F0xBC_xE03002F8_SmuSp032P2IsoN_OFFSET 17 +#define D0F0xBC_xE03002F8_SmuSp032P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuSp032P2IsoN_MASK 0x20000 +#define D0F0xBC_xE03002F8_SmuLds3P2IsoN_OFFSET 18 +#define D0F0xBC_xE03002F8_SmuLds3P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuLds3P2IsoN_MASK 0x40000 +#define D0F0xBC_xE03002F8_SmuTcp3P2IsoN_OFFSET 19 +#define D0F0xBC_xE03002F8_SmuTcp3P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuTcp3P2IsoN_MASK 0x80000 +#define D0F0xBC_xE03002F8_SmuTatd4P2IsoN_OFFSET 20 +#define D0F0xBC_xE03002F8_SmuTatd4P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuTatd4P2IsoN_MASK 0x100000 +#define D0F0xBC_xE03002F8_SmuSp040P2IsoN_OFFSET 21 +#define D0F0xBC_xE03002F8_SmuSp040P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuSp040P2IsoN_MASK 0x200000 +#define D0F0xBC_xE03002F8_SmuSp042P2IsoN_OFFSET 22 +#define D0F0xBC_xE03002F8_SmuSp042P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuSp042P2IsoN_MASK 0x400000 +#define D0F0xBC_xE03002F8_SmuLds4P2IsoN_OFFSET 23 +#define D0F0xBC_xE03002F8_SmuLds4P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuLds4P2IsoN_MASK 0x800000 +#define D0F0xBC_xE03002F8_SmuTcp4P2IsoN_OFFSET 24 +#define D0F0xBC_xE03002F8_SmuTcp4P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuTcp4P2IsoN_MASK 0x1000000 +#define D0F0xBC_xE03002F8_SmuTatd5P2IsoN_OFFSET 25 +#define D0F0xBC_xE03002F8_SmuTatd5P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuTatd5P2IsoN_MASK 0x2000000 +#define D0F0xBC_xE03002F8_SmuSp050P2IsoN_OFFSET 26 +#define D0F0xBC_xE03002F8_SmuSp050P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuSp050P2IsoN_MASK 0x4000000 +#define D0F0xBC_xE03002F8_SmuSp052P2IsoN_OFFSET 27 +#define D0F0xBC_xE03002F8_SmuSp052P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuSp052P2IsoN_MASK 0x8000000 +#define D0F0xBC_xE03002F8_SmuLds5P2IsoN_OFFSET 28 +#define D0F0xBC_xE03002F8_SmuLds5P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuLds5P2IsoN_MASK 0x10000000 +#define D0F0xBC_xE03002F8_SmuTcp5P2IsoN_OFFSET 29 +#define D0F0xBC_xE03002F8_SmuTcp5P2IsoN_WIDTH 1 +#define D0F0xBC_xE03002F8_SmuTcp5P2IsoN_MASK 0x20000000 +#define D0F0xBC_xE03002F8_Reserved_31_30_OFFSET 30 +#define D0F0xBC_xE03002F8_Reserved_31_30_WIDTH 2 +#define D0F0xBC_xE03002F8_Reserved_31_30_MASK 0xc0000000 + +/// D0F0xBC_xE03002F8 +typedef union { + struct { ///< + UINT32 SmuTatd0P2IsoN:1 ; ///< + UINT32 SmuSp000P2IsoN:1 ; ///< + UINT32 SmuSp002P2IsoN:1 ; ///< + UINT32 SmuLds0P2IsoN:1 ; ///< + UINT32 SmuTcp0P2IsoN:1 ; ///< + UINT32 SmuTatd1P2IsoN:1 ; ///< + UINT32 SmuSp010P2IsoN:1 ; ///< + UINT32 SmuSp012P2IsoN:1 ; ///< + UINT32 SmuLds1P2IsoN:1 ; ///< + UINT32 SmuTcp1P2IsoN:1 ; ///< + UINT32 SmuTatd2P2IsoN:1 ; ///< + UINT32 SmuSp020P2IsoN:1 ; ///< + UINT32 SmuSp022P2IsoN:1 ; ///< + UINT32 SmuLds2P2IsoN:1 ; ///< + UINT32 SmuTcp2P2IsoN:1 ; ///< + UINT32 SmuTatd3P2IsoN:1 ; ///< + UINT32 SmuSp030P2IsoN:1 ; ///< + UINT32 SmuSp032P2IsoN:1 ; ///< + UINT32 SmuLds3P2IsoN:1 ; ///< + UINT32 SmuTcp3P2IsoN:1 ; ///< + UINT32 SmuTatd4P2IsoN:1 ; ///< + UINT32 SmuSp040P2IsoN:1 ; ///< + UINT32 SmuSp042P2IsoN:1 ; ///< + UINT32 SmuLds4P2IsoN:1 ; ///< + UINT32 SmuTcp4P2IsoN:1 ; ///< + UINT32 SmuTatd5P2IsoN:1 ; ///< + UINT32 SmuSp050P2IsoN:1 ; ///< + UINT32 SmuSp052P2IsoN:1 ; ///< + UINT32 SmuLds5P2IsoN:1 ; ///< + UINT32 SmuTcp5P2IsoN:1 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE03002F8_STRUCT; + +// **** D0F0xBC_xE03002FC Register Definition **** +// Address +#define D0F0xBC_xE03002FC_ADDRESS 0xe03002fc + +// Type +#define D0F0xBC_xE03002FC_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE03002FC_SmuTatd0P2PsoDaug_OFFSET 0 +#define D0F0xBC_xE03002FC_SmuTatd0P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuTatd0P2PsoDaug_MASK 0x1 +#define D0F0xBC_xE03002FC_SmuSp000P2PsoDaug_OFFSET 1 +#define D0F0xBC_xE03002FC_SmuSp000P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuSp000P2PsoDaug_MASK 0x2 +#define D0F0xBC_xE03002FC_SmuSp002P2PsoDaug_OFFSET 2 +#define D0F0xBC_xE03002FC_SmuSp002P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuSp002P2PsoDaug_MASK 0x4 +#define D0F0xBC_xE03002FC_SmuLds0P2PsoDaug_OFFSET 3 +#define D0F0xBC_xE03002FC_SmuLds0P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuLds0P2PsoDaug_MASK 0x8 +#define D0F0xBC_xE03002FC_SmuTcp0P2PsoDaug_OFFSET 4 +#define D0F0xBC_xE03002FC_SmuTcp0P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuTcp0P2PsoDaug_MASK 0x10 +#define D0F0xBC_xE03002FC_SmuTatd1P2PsoDaug_OFFSET 5 +#define D0F0xBC_xE03002FC_SmuTatd1P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuTatd1P2PsoDaug_MASK 0x20 +#define D0F0xBC_xE03002FC_SmuSp010P2PsoDaug_OFFSET 6 +#define D0F0xBC_xE03002FC_SmuSp010P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuSp010P2PsoDaug_MASK 0x40 +#define D0F0xBC_xE03002FC_SmuSp012P2PsoDaug_OFFSET 7 +#define D0F0xBC_xE03002FC_SmuSp012P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuSp012P2PsoDaug_MASK 0x80 +#define D0F0xBC_xE03002FC_SmuLds1P2PsoDaug_OFFSET 8 +#define D0F0xBC_xE03002FC_SmuLds1P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuLds1P2PsoDaug_MASK 0x100 +#define D0F0xBC_xE03002FC_SmuTcp1P2PsoDaug_OFFSET 9 +#define D0F0xBC_xE03002FC_SmuTcp1P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuTcp1P2PsoDaug_MASK 0x200 +#define D0F0xBC_xE03002FC_SmuTatd2P2PsoDaug_OFFSET 10 +#define D0F0xBC_xE03002FC_SmuTatd2P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuTatd2P2PsoDaug_MASK 0x400 +#define D0F0xBC_xE03002FC_SmuSp020P2PsoDaug_OFFSET 11 +#define D0F0xBC_xE03002FC_SmuSp020P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuSp020P2PsoDaug_MASK 0x800 +#define D0F0xBC_xE03002FC_SmuSp022P2PsoDaug_OFFSET 12 +#define D0F0xBC_xE03002FC_SmuSp022P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuSp022P2PsoDaug_MASK 0x1000 +#define D0F0xBC_xE03002FC_SmuLds2P2PsoDaug_OFFSET 13 +#define D0F0xBC_xE03002FC_SmuLds2P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuLds2P2PsoDaug_MASK 0x2000 +#define D0F0xBC_xE03002FC_SmuTcp2P2PsoDaug_OFFSET 14 +#define D0F0xBC_xE03002FC_SmuTcp2P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuTcp2P2PsoDaug_MASK 0x4000 +#define D0F0xBC_xE03002FC_SmuTatd3P2PsoDaug_OFFSET 15 +#define D0F0xBC_xE03002FC_SmuTatd3P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuTatd3P2PsoDaug_MASK 0x8000 +#define D0F0xBC_xE03002FC_SmuSp030P2PsoDaug_OFFSET 16 +#define D0F0xBC_xE03002FC_SmuSp030P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuSp030P2PsoDaug_MASK 0x10000 +#define D0F0xBC_xE03002FC_SmuSp032P2PsoDaug_OFFSET 17 +#define D0F0xBC_xE03002FC_SmuSp032P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuSp032P2PsoDaug_MASK 0x20000 +#define D0F0xBC_xE03002FC_SmuLds3P2PsoDaug_OFFSET 18 +#define D0F0xBC_xE03002FC_SmuLds3P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuLds3P2PsoDaug_MASK 0x40000 +#define D0F0xBC_xE03002FC_SmuTcp3P2PsoDaug_OFFSET 19 +#define D0F0xBC_xE03002FC_SmuTcp3P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuTcp3P2PsoDaug_MASK 0x80000 +#define D0F0xBC_xE03002FC_SmuTatd4P2PsoDaug_OFFSET 20 +#define D0F0xBC_xE03002FC_SmuTatd4P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuTatd4P2PsoDaug_MASK 0x100000 +#define D0F0xBC_xE03002FC_SmuSp040P2PsoDaug_OFFSET 21 +#define D0F0xBC_xE03002FC_SmuSp040P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuSp040P2PsoDaug_MASK 0x200000 +#define D0F0xBC_xE03002FC_SmuSp042P2PsoDaug_OFFSET 22 +#define D0F0xBC_xE03002FC_SmuSp042P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuSp042P2PsoDaug_MASK 0x400000 +#define D0F0xBC_xE03002FC_SmuLds4P2PsoDaug_OFFSET 23 +#define D0F0xBC_xE03002FC_SmuLds4P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuLds4P2PsoDaug_MASK 0x800000 +#define D0F0xBC_xE03002FC_SmuTcp4P2PsoDaug_OFFSET 24 +#define D0F0xBC_xE03002FC_SmuTcp4P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuTcp4P2PsoDaug_MASK 0x1000000 +#define D0F0xBC_xE03002FC_SmuTatd5P2PsoDaug_OFFSET 25 +#define D0F0xBC_xE03002FC_SmuTatd5P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuTatd5P2PsoDaug_MASK 0x2000000 +#define D0F0xBC_xE03002FC_SmuSp050P2PsoDaug_OFFSET 26 +#define D0F0xBC_xE03002FC_SmuSp050P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuSp050P2PsoDaug_MASK 0x4000000 +#define D0F0xBC_xE03002FC_SmuSp052P2PsoDaug_OFFSET 27 +#define D0F0xBC_xE03002FC_SmuSp052P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuSp052P2PsoDaug_MASK 0x8000000 +#define D0F0xBC_xE03002FC_SmuLds5P2PsoDaug_OFFSET 28 +#define D0F0xBC_xE03002FC_SmuLds5P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuLds5P2PsoDaug_MASK 0x10000000 +#define D0F0xBC_xE03002FC_SmuTcp5P2PsoDaug_OFFSET 29 +#define D0F0xBC_xE03002FC_SmuTcp5P2PsoDaug_WIDTH 1 +#define D0F0xBC_xE03002FC_SmuTcp5P2PsoDaug_MASK 0x20000000 +#define D0F0xBC_xE03002FC_Reserved_31_30_OFFSET 30 +#define D0F0xBC_xE03002FC_Reserved_31_30_WIDTH 2 +#define D0F0xBC_xE03002FC_Reserved_31_30_MASK 0xc0000000 + +/// D0F0xBC_xE03002FC +typedef union { + struct { ///< + UINT32 SmuTatd0P2PsoDaug:1 ; ///< + UINT32 SmuSp000P2PsoDaug:1 ; ///< + UINT32 SmuSp002P2PsoDaug:1 ; ///< + UINT32 SmuLds0P2PsoDaug:1 ; ///< + UINT32 SmuTcp0P2PsoDaug:1 ; ///< + UINT32 SmuTatd1P2PsoDaug:1 ; ///< + UINT32 SmuSp010P2PsoDaug:1 ; ///< + UINT32 SmuSp012P2PsoDaug:1 ; ///< + UINT32 SmuLds1P2PsoDaug:1 ; ///< + UINT32 SmuTcp1P2PsoDaug:1 ; ///< + UINT32 SmuTatd2P2PsoDaug:1 ; ///< + UINT32 SmuSp020P2PsoDaug:1 ; ///< + UINT32 SmuSp022P2PsoDaug:1 ; ///< + UINT32 SmuLds2P2PsoDaug:1 ; ///< + UINT32 SmuTcp2P2PsoDaug:1 ; ///< + UINT32 SmuTatd3P2PsoDaug:1 ; ///< + UINT32 SmuSp030P2PsoDaug:1 ; ///< + UINT32 SmuSp032P2PsoDaug:1 ; ///< + UINT32 SmuLds3P2PsoDaug:1 ; ///< + UINT32 SmuTcp3P2PsoDaug:1 ; ///< + UINT32 SmuTatd4P2PsoDaug:1 ; ///< + UINT32 SmuSp040P2PsoDaug:1 ; ///< + UINT32 SmuSp042P2PsoDaug:1 ; ///< + UINT32 SmuLds4P2PsoDaug:1 ; ///< + UINT32 SmuTcp4P2PsoDaug:1 ; ///< + UINT32 SmuTatd5P2PsoDaug:1 ; ///< + UINT32 SmuSp050P2PsoDaug:1 ; ///< + UINT32 SmuSp052P2PsoDaug:1 ; ///< + UINT32 SmuLds5P2PsoDaug:1 ; ///< + UINT32 SmuTcp5P2PsoDaug:1 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE03002FC_STRUCT; + +// **** D0F0xBC_xE0300320 Register Definition **** +// Address +#define D0F0xBC_xE0300320_ADDRESS 0xe0300320 + +// Type +#define D0F0xBC_xE0300320_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0300320_PgdPgfsmClockEn_OFFSET 0 +#define D0F0xBC_xE0300320_PgdPgfsmClockEn_WIDTH 1 +#define D0F0xBC_xE0300320_PgdPgfsmClockEn_MASK 0x1 +#define D0F0xBC_xE0300320_IommuPgfsmClockEn_OFFSET 1 +#define D0F0xBC_xE0300320_IommuPgfsmClockEn_WIDTH 1 +#define D0F0xBC_xE0300320_IommuPgfsmClockEn_MASK 0x2 +#define D0F0xBC_xE0300320_Reserved_31_2_OFFSET 2 +#define D0F0xBC_xE0300320_Reserved_31_2_WIDTH 30 +#define D0F0xBC_xE0300320_Reserved_31_2_MASK 0xfffffffc + +/// D0F0xBC_xE0300320 +typedef union { + struct { ///< + UINT32 PgdPgfsmClockEn:1 ; ///< + UINT32 IommuPgfsmClockEn:1 ; ///< + UINT32 Reserved_31_2:30; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0300320_STRUCT; + +// **** D0F0xBC_xE0300324 Register Definition **** +// Address +#define D0F0xBC_xE0300324_ADDRESS 0xe0300324 + +// Type +#define D0F0xBC_xE0300324_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE0300324_VcePgfsmClockEn_OFFSET 0 +#define D0F0xBC_xE0300324_VcePgfsmClockEn_WIDTH 1 +#define D0F0xBC_xE0300324_VcePgfsmClockEn_MASK 0x1 +#define D0F0xBC_xE0300324_UvdPgfsmClockEn_OFFSET 1 +#define D0F0xBC_xE0300324_UvdPgfsmClockEn_WIDTH 1 +#define D0F0xBC_xE0300324_UvdPgfsmClockEn_MASK 0x2 +#define D0F0xBC_xE0300324_Dc2PgfsmClockEn_OFFSET 2 +#define D0F0xBC_xE0300324_Dc2PgfsmClockEn_WIDTH 1 +#define D0F0xBC_xE0300324_Dc2PgfsmClockEn_MASK 0x4 +#define D0F0xBC_xE0300324_Reserved_31_3_OFFSET 3 +#define D0F0xBC_xE0300324_Reserved_31_3_WIDTH 29 +#define D0F0xBC_xE0300324_Reserved_31_3_MASK 0xfffffff8 + +/// D0F0xBC_xE0300324 +typedef union { + struct { ///< + UINT32 VcePgfsmClockEn:1 ; ///< + UINT32 UvdPgfsmClockEn:1 ; ///< + UINT32 Dc2PgfsmClockEn:1 ; ///< + UINT32 Reserved_31_3:29; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0300324_STRUCT; + +typedef union { + struct { ///< + UINT32 Simd0PgfsmClockEn:1 ; ///< + UINT32 Simd1PgfsmClockEn:1 ; ///< + UINT32 Simd2PgfsmClockEn:1 ; ///< + UINT32 Simd3PgfsmClockEn:1 ; ///< + UINT32 Simd4PgfsmClockEn:1 ; ///< + UINT32 ex1009_0:1; + UINT32 ex1009_1:1; + UINT32 Reserved_31_7:25; ///< + } Field; ///< + UINT32 Value; ///< +} ex1009_STRUCT; + +// **** D0F0xBC_xFF000000 Register Definition **** +// Address +#define D0F0xBC_xFF000000_ADDRESS 0xff000000 + +// Type +#define D0F0xBC_xFF000000_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xFF000000_GckFuseProg_OFFSET 0 +#define D0F0xBC_xFF000000_GckFuseProg_WIDTH 1 +#define D0F0xBC_xFF000000_GckFuseProg_MASK 0x1 +#define D0F0xBC_xFF000000_MainPllOpFreqIdStartup_OFFSET 1 +#define D0F0xBC_xFF000000_MainPllOpFreqIdStartup_WIDTH 6 +#define D0F0xBC_xFF000000_MainPllOpFreqIdStartup_MASK 0x7e +#define D0F0xBC_xFF000000_MainPllOpFreqIdMax_OFFSET 7 +#define D0F0xBC_xFF000000_MainPllOpFreqIdMax_WIDTH 6 +#define D0F0xBC_xFF000000_MainPllOpFreqIdMax_MASK 0x1f80 +#define D0F0xBC_xFF000000_MainPllRefAdj_OFFSET 13 +#define D0F0xBC_xFF000000_MainPllRefAdj_WIDTH 5 +#define D0F0xBC_xFF000000_MainPllRefAdj_MASK 0x3e000 +#define D0F0xBC_xFF000000_PllMiscFuseCtl_OFFSET 18 +#define D0F0xBC_xFF000000_PllMiscFuseCtl_WIDTH 4 +#define D0F0xBC_xFF000000_PllMiscFuseCtl_MASK 0x3c0000 +#define D0F0xBC_xFF000000_Reserved_31_22_OFFSET 22 +#define D0F0xBC_xFF000000_Reserved_31_22_WIDTH 10 +#define D0F0xBC_xFF000000_Reserved_31_22_MASK 0xffc00000 + +/// D0F0xBC_xFF000000 +typedef union { + struct { ///< + UINT32 GckFuseProg:1 ; ///< + UINT32 MainPllOpFreqIdStartup:6 ; ///< + UINT32 MainPllOpFreqIdMax:6 ; ///< + UINT32 MainPllRefAdj:5 ; ///< + UINT32 PllMiscFuseCtl:4 ; ///< + UINT32 Reserved_31_22:10; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xFF000000_STRUCT; + +// **** D0F0xE4_WRAP_0046 Register Definition **** +// Address +#define D0F0xE4_WRAP_0046_ADDRESS 0x46 + +// Type +#define D0F0xE4_WRAP_0046_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_0046_SubsystemVendorID_OFFSET 0 +#define D0F0xE4_WRAP_0046_SubsystemVendorID_WIDTH 16 +#define D0F0xE4_WRAP_0046_SubsystemVendorID_MASK 0xffff +#define D0F0xE4_WRAP_0046_SubsystemID_OFFSET 16 +#define D0F0xE4_WRAP_0046_SubsystemID_WIDTH 16 +#define D0F0xE4_WRAP_0046_SubsystemID_MASK 0xffff0000 + +/// D0F0xE4_WRAP_0046 +typedef union { + struct { ///< + UINT32 SubsystemVendorID:16; ///< + UINT32 SubsystemID:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_0046_STRUCT; + +// **** D0F0xE4_WRAP_0080 Register Definition **** +// Address +#define D0F0xE4_WRAP_0080_ADDRESS 0x80 + +// Type +#define D0F0xE4_WRAP_0080_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_OFFSET 0 +#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_WIDTH 4 +#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_MASK 0xf +#define D0F0xE4_WRAP_0080_Reserved_31_4_OFFSET 4 +#define D0F0xE4_WRAP_0080_Reserved_31_4_WIDTH 28 +#define D0F0xE4_WRAP_0080_Reserved_31_4_MASK 0xfffffff0 + +/// D0F0xE4_WRAP_0080 +typedef union { + struct { ///< + UINT32 StrapBifLinkConfig:4 ; ///< + UINT32 Reserved_31_4:28; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_0080_STRUCT; + +// **** D0F0xE4_WRAP_0800 Register Definition **** +// Address +#define D0F0xE4_WRAP_0800_ADDRESS 0x800 + +// Type +#define D0F0xE4_WRAP_0800_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_0800_HoldTraining_OFFSET 0 +#define D0F0xE4_WRAP_0800_HoldTraining_WIDTH 1 +#define D0F0xE4_WRAP_0800_HoldTraining_MASK 0x1 +#define D0F0xE4_WRAP_0800_Reserved_31_1_OFFSET 1 +#define D0F0xE4_WRAP_0800_Reserved_31_1_WIDTH 31 +#define D0F0xE4_WRAP_0800_Reserved_31_1_MASK 0xfffffffe + +/// D0F0xE4_WRAP_0800 +typedef union { + struct { ///< + UINT32 HoldTraining:1 ; ///< + UINT32 Reserved_31_1:31; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_0800_STRUCT; + +// **** D0F0xE4_WRAP_0803 Register Definition **** +// Address +#define D0F0xE4_WRAP_0803_ADDRESS 0x803 + +// Type +#define D0F0xE4_WRAP_0803_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_0803_Reserved_4_0_OFFSET 0 +#define D0F0xE4_WRAP_0803_Reserved_4_0_WIDTH 5 +#define D0F0xE4_WRAP_0803_Reserved_4_0_MASK 0x1f +#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET 5 +#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH 1 +#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_MASK 0x20 +#define D0F0xE4_WRAP_0803_Reserved_31_6_OFFSET 6 +#define D0F0xE4_WRAP_0803_Reserved_31_6_WIDTH 26 +#define D0F0xE4_WRAP_0803_Reserved_31_6_MASK 0xffffffc0 + +/// D0F0xE4_WRAP_0803 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 StrapBifDeemphasisSel:1 ; ///< + UINT32 Reserved_31_6:26; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_0803_STRUCT; + +// **** D0F0xE4_WRAP_0903 Register Definition **** +// Address +#define D0F0xE4_WRAP_0903_ADDRESS 0x903 + +// Type +#define D0F0xE4_WRAP_0903_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_0903_Reserved_4_0_OFFSET 0 +#define D0F0xE4_WRAP_0903_Reserved_4_0_WIDTH 5 +#define D0F0xE4_WRAP_0903_Reserved_4_0_MASK 0x1f +#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_OFFSET 5 +#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_WIDTH 1 +#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_MASK 0x20 +#define D0F0xE4_WRAP_0903_Reserved_31_6_OFFSET 6 +#define D0F0xE4_WRAP_0903_Reserved_31_6_WIDTH 26 +#define D0F0xE4_WRAP_0903_Reserved_31_6_MASK 0xffffffc0 + +/// D0F0xE4_WRAP_0903 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 StrapBifDeemphasisSel:1 ; ///< + UINT32 Reserved_31_6:26; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_0903_STRUCT; + + +// **** D0F0xE4_WRAP_8011 Register Definition **** +// Address +#define D0F0xE4_WRAP_8011_ADDRESS 0x8011 + +// Type +#define D0F0xE4_WRAP_8011_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_OFFSET 0 +#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_MASK 0x3f +#define D0F0xE4_WRAP_8011_TxclkPermGateEven_OFFSET 6 +#define D0F0xE4_WRAP_8011_TxclkPermGateEven_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkPermGateEven_MASK 0x40 +#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_OFFSET 7 +#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_MASK 0x80 +#define D0F0xE4_WRAP_8011_TxclkPermStop_OFFSET 8 +#define D0F0xE4_WRAP_8011_TxclkPermStop_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkPermStop_MASK 0x100 +#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_OFFSET 9 +#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_MASK 0x200 +#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_OFFSET 10 +#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_MASK 0xfc00 +#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_OFFSET 16 +#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_MASK 0x10000 +#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_OFFSET 17 +#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_MASK 0x7e0000 +#define D0F0xE4_WRAP_8011_DebugBusClkEnable_OFFSET 23 +#define D0F0xE4_WRAP_8011_DebugBusClkEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_DebugBusClkEnable_MASK 0x800000 +#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_OFFSET 24 +#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_MASK 0x1000000 +#define D0F0xE4_WRAP_8011_DdiDualLinkOverride_OFFSET 25 +#define D0F0xE4_WRAP_8011_DdiDualLinkOverride_WIDTH 1 +#define D0F0xE4_WRAP_8011_DdiDualLinkOverride_MASK 0x2000000 +#define D0F0xE4_WRAP_8011_Reserved_30_26_OFFSET 26 +#define D0F0xE4_WRAP_8011_Reserved_30_26_WIDTH 5 +#define D0F0xE4_WRAP_8011_Reserved_30_26_MASK 0x7c000000 +#define D0F0xE4_WRAP_8011_StrapBifValid_OFFSET 31 +#define D0F0xE4_WRAP_8011_StrapBifValid_WIDTH 1 +#define D0F0xE4_WRAP_8011_StrapBifValid_MASK 0x80000000 + +/// D0F0xE4_WRAP_8011 +typedef union { + struct { ///< + UINT32 TxclkDynGateLatency:6 ; ///< + UINT32 TxclkPermGateEven:1 ; ///< + UINT32 TxclkDynGateEnable:1 ; ///< + UINT32 TxclkPermStop:1 ; ///< + UINT32 TxclkRegsGateEnable:1 ; ///< + UINT32 TxclkRegsGateLatency:6 ; ///< + UINT32 RcvrDetClkEnable:1 ; ///< + UINT32 TxclkPermGateLatency:6 ; ///< + UINT32 DebugBusClkEnable:1 ; ///< + UINT32 TxclkLcntGateEnable:1 ; ///< + UINT32 DdiDualLinkOverride:1 ; ///< + UINT32 Reserved_30_26:5 ; ///< + UINT32 StrapBifValid:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8011_STRUCT; + +// **** D0F0xE4_WRAP_8016 Register Definition **** +// Address +#define D0F0xE4_WRAP_8016_ADDRESS 0x8016 + +// Type +#define D0F0xE4_WRAP_8016_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8016_CalibAckLatency_OFFSET 0 +#define D0F0xE4_WRAP_8016_CalibAckLatency_WIDTH 6 +#define D0F0xE4_WRAP_8016_CalibAckLatency_MASK 0x3f +#define D0F0xE4_WRAP_8016_Reserved_15_6_OFFSET 6 +#define D0F0xE4_WRAP_8016_Reserved_15_6_WIDTH 10 +#define D0F0xE4_WRAP_8016_Reserved_15_6_MASK 0xffc0 +#define D0F0xE4_WRAP_8016_LclkDynGateLatency_OFFSET 16 +#define D0F0xE4_WRAP_8016_LclkDynGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8016_LclkDynGateLatency_MASK 0x3f0000 +#define D0F0xE4_WRAP_8016_LclkGateFree_OFFSET 22 +#define D0F0xE4_WRAP_8016_LclkGateFree_WIDTH 1 +#define D0F0xE4_WRAP_8016_LclkGateFree_MASK 0x400000 +#define D0F0xE4_WRAP_8016_LclkDynGateEnable_OFFSET 23 +#define D0F0xE4_WRAP_8016_LclkDynGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8016_LclkDynGateEnable_MASK 0x800000 +#define D0F0xE4_WRAP_8016_Reserved_31_24_OFFSET 24 +#define D0F0xE4_WRAP_8016_Reserved_31_24_WIDTH 8 +#define D0F0xE4_WRAP_8016_Reserved_31_24_MASK 0xff000000 + +/// D0F0xE4_WRAP_8016 +typedef union { + struct { ///< + UINT32 CalibAckLatency:6 ; ///< + UINT32 Reserved_15_6:10; ///< + UINT32 LclkDynGateLatency:6 ; ///< + UINT32 LclkGateFree:1 ; ///< + UINT32 LclkDynGateEnable:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8016_STRUCT; + +// **** D0F0xE4_WRAP_8021 Register Definition **** +// Address +#define D0F0xE4_WRAP_8021_ADDRESS 0x8021 + +// Type +#define D0F0xE4_WRAP_8021_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8021_Lanes10_OFFSET 0 +#define D0F0xE4_WRAP_8021_Lanes10_WIDTH 4 +#define D0F0xE4_WRAP_8021_Lanes10_MASK 0xf +#define D0F0xE4_WRAP_8021_Lanes32_OFFSET 4 +#define D0F0xE4_WRAP_8021_Lanes32_WIDTH 4 +#define D0F0xE4_WRAP_8021_Lanes32_MASK 0xf0 +#define D0F0xE4_WRAP_8021_Lanes54_OFFSET 8 +#define D0F0xE4_WRAP_8021_Lanes54_WIDTH 4 +#define D0F0xE4_WRAP_8021_Lanes54_MASK 0xf00 +#define D0F0xE4_WRAP_8021_Lanes76_OFFSET 12 +#define D0F0xE4_WRAP_8021_Lanes76_WIDTH 4 +#define D0F0xE4_WRAP_8021_Lanes76_MASK 0xf000 +#define D0F0xE4_WRAP_8021_Lanes98_OFFSET 16 +#define D0F0xE4_WRAP_8021_Lanes98_WIDTH 4 +#define D0F0xE4_WRAP_8021_Lanes98_MASK 0xf0000 +#define D0F0xE4_WRAP_8021_Lanes1110_OFFSET 20 +#define D0F0xE4_WRAP_8021_Lanes1110_WIDTH 4 +#define D0F0xE4_WRAP_8021_Lanes1110_MASK 0xf00000 +#define D0F0xE4_WRAP_8021_Lanes1312_OFFSET 24 +#define D0F0xE4_WRAP_8021_Lanes1312_WIDTH 4 +#define D0F0xE4_WRAP_8021_Lanes1312_MASK 0xf000000 +#define D0F0xE4_WRAP_8021_Lanes1514_OFFSET 28 +#define D0F0xE4_WRAP_8021_Lanes1514_WIDTH 4 +#define D0F0xE4_WRAP_8021_Lanes1514_MASK 0xf0000000 + +/// D0F0xE4_WRAP_8021 +typedef union { + struct { ///< + UINT32 Lanes10:4 ; ///< + UINT32 Lanes32:4 ; ///< + UINT32 Lanes54:4 ; ///< + UINT32 Lanes76:4 ; ///< + UINT32 Lanes98:4 ; ///< + UINT32 Lanes1110:4 ; ///< + UINT32 Lanes1312:4 ; ///< + UINT32 Lanes1514:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8021_STRUCT; + +// **** D0F0xE4_WRAP_8022 Register Definition **** +// Address +#define D0F0xE4_WRAP_8022_ADDRESS 0x8022 + +// Type +#define D0F0xE4_WRAP_8022_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8022_Lanes10_OFFSET 0 +#define D0F0xE4_WRAP_8022_Lanes10_WIDTH 4 +#define D0F0xE4_WRAP_8022_Lanes10_MASK 0xf +#define D0F0xE4_WRAP_8022_Lanes32_OFFSET 4 +#define D0F0xE4_WRAP_8022_Lanes32_WIDTH 4 +#define D0F0xE4_WRAP_8022_Lanes32_MASK 0xf0 +#define D0F0xE4_WRAP_8022_Lanes54_OFFSET 8 +#define D0F0xE4_WRAP_8022_Lanes54_WIDTH 4 +#define D0F0xE4_WRAP_8022_Lanes54_MASK 0xf00 +#define D0F0xE4_WRAP_8022_Lanes76_OFFSET 12 +#define D0F0xE4_WRAP_8022_Lanes76_WIDTH 4 +#define D0F0xE4_WRAP_8022_Lanes76_MASK 0xf000 +#define D0F0xE4_WRAP_8022_Lanes98_OFFSET 16 +#define D0F0xE4_WRAP_8022_Lanes98_WIDTH 4 +#define D0F0xE4_WRAP_8022_Lanes98_MASK 0xf0000 +#define D0F0xE4_WRAP_8022_Lanes1110_OFFSET 20 +#define D0F0xE4_WRAP_8022_Lanes1110_WIDTH 4 +#define D0F0xE4_WRAP_8022_Lanes1110_MASK 0xf00000 +#define D0F0xE4_WRAP_8022_Lanes1312_OFFSET 24 +#define D0F0xE4_WRAP_8022_Lanes1312_WIDTH 4 +#define D0F0xE4_WRAP_8022_Lanes1312_MASK 0xf000000 +#define D0F0xE4_WRAP_8022_Lanes1514_OFFSET 28 +#define D0F0xE4_WRAP_8022_Lanes1514_WIDTH 4 +#define D0F0xE4_WRAP_8022_Lanes1514_MASK 0xf0000000 + +/// D0F0xE4_WRAP_8022 +typedef union { + struct { ///< + UINT32 Lanes10:4 ; ///< + UINT32 Lanes32:4 ; ///< + UINT32 Lanes54:4 ; ///< + UINT32 Lanes76:4 ; ///< + UINT32 Lanes98:4 ; ///< + UINT32 Lanes1110:4 ; ///< + UINT32 Lanes1312:4 ; ///< + UINT32 Lanes1514:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8022_STRUCT; + +// **** D0F0xE4_WRAP_8023 Register Definition **** +// Address +#define D0F0xE4_WRAP_8023_ADDRESS 0x8023 + +// Type +#define D0F0xE4_WRAP_8023_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8023_LaneEnable_OFFSET 0 +#define D0F0xE4_WRAP_8023_LaneEnable_WIDTH 16 +#define D0F0xE4_WRAP_8023_LaneEnable_MASK 0xffff +#define D0F0xE4_WRAP_8023_Reserved_31_16_OFFSET 16 +#define D0F0xE4_WRAP_8023_Reserved_31_16_WIDTH 16 +#define D0F0xE4_WRAP_8023_Reserved_31_16_MASK 0xffff0000 + +/// D0F0xE4_WRAP_8023 +typedef union { + struct { ///< + UINT32 LaneEnable:16; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8023_STRUCT; + +// **** D0F0xE4_WRAP_8031 Register Definition **** +// Address +#define D0F0xE4_WRAP_8031_ADDRESS 0x8031 + +// Type +#define D0F0xE4_WRAP_8031_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8031_LnCntBandwidth_OFFSET 0 +#define D0F0xE4_WRAP_8031_LnCntBandwidth_WIDTH 10 +#define D0F0xE4_WRAP_8031_LnCntBandwidth_MASK 0x3ff +#define D0F0xE4_WRAP_8031_Reserved_15_10_OFFSET 10 +#define D0F0xE4_WRAP_8031_Reserved_15_10_WIDTH 6 +#define D0F0xE4_WRAP_8031_Reserved_15_10_MASK 0xfc00 +#define D0F0xE4_WRAP_8031_LnCntValid_OFFSET 16 +#define D0F0xE4_WRAP_8031_LnCntValid_WIDTH 1 +#define D0F0xE4_WRAP_8031_LnCntValid_MASK 0x10000 +#define D0F0xE4_WRAP_8031_Reserved_31_17_OFFSET 17 +#define D0F0xE4_WRAP_8031_Reserved_31_17_WIDTH 15 +#define D0F0xE4_WRAP_8031_Reserved_31_17_MASK 0xfffe0000 + +/// D0F0xE4_WRAP_8031 +typedef union { + struct { ///< + UINT32 LnCntBandwidth:10; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 LnCntValid:1 ; ///< + UINT32 Reserved_31_17:15; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8031_STRUCT; + +// **** D0F0xE4_WRAP_8040 Register Definition **** +// Address +#define D0F0xE4_WRAP_8040_ADDRESS 0x8040 + +// Type +#define D0F0xE4_WRAP_8040_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8040_OwnSlice_OFFSET 0 +#define D0F0xE4_WRAP_8040_OwnSlice_WIDTH 1 +#define D0F0xE4_WRAP_8040_OwnSlice_MASK 0x1 +#define D0F0xE4_WRAP_8040_Reserved_31_1_OFFSET 1 +#define D0F0xE4_WRAP_8040_Reserved_31_1_WIDTH 31 +#define D0F0xE4_WRAP_8040_Reserved_31_1_MASK 0xfffffffe + +/// D0F0xE4_WRAP_8040 +typedef union { + struct { ///< + UINT32 OwnSlice:1 ; ///< + UINT32 Reserved_31_1:31; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8040_STRUCT; + + + + + + + + + + + +// **** D0F0xE4_WRAP_8060 Register Definition **** +// Address +#define D0F0xE4_WRAP_8060_ADDRESS 0x8060 + +// Type +#define D0F0xE4_WRAP_8060_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8060_Reconfigure_OFFSET 0 +#define D0F0xE4_WRAP_8060_Reconfigure_WIDTH 1 +#define D0F0xE4_WRAP_8060_Reconfigure_MASK 0x1 +#define D0F0xE4_WRAP_8060_Reserved_1_1_OFFSET 1 +#define D0F0xE4_WRAP_8060_Reserved_1_1_WIDTH 1 +#define D0F0xE4_WRAP_8060_Reserved_1_1_MASK 0x2 +#define D0F0xE4_WRAP_8060_ResetComplete_OFFSET 2 +#define D0F0xE4_WRAP_8060_ResetComplete_WIDTH 1 +#define D0F0xE4_WRAP_8060_ResetComplete_MASK 0x4 +#define D0F0xE4_WRAP_8060_Reserved_15_3_OFFSET 3 +#define D0F0xE4_WRAP_8060_Reserved_15_3_WIDTH 13 +#define D0F0xE4_WRAP_8060_Reserved_15_3_MASK 0xfff8 +#define D0F0xE4_WRAP_8060_Bif0GlobalReset_OFFSET 16 +#define D0F0xE4_WRAP_8060_Bif0GlobalReset_WIDTH 1 +#define D0F0xE4_WRAP_8060_Bif0GlobalReset_MASK 0x10000 +#define D0F0xE4_WRAP_8060_Bif0CalibrationReset_OFFSET 17 +#define D0F0xE4_WRAP_8060_Bif0CalibrationReset_WIDTH 1 +#define D0F0xE4_WRAP_8060_Bif0CalibrationReset_MASK 0x20000 +#define D0F0xE4_WRAP_8060_Reserved_31_18_OFFSET 18 +#define D0F0xE4_WRAP_8060_Reserved_31_18_WIDTH 14 +#define D0F0xE4_WRAP_8060_Reserved_31_18_MASK 0xfffc0000 + +/// D0F0xE4_WRAP_8060 +typedef union { + struct { ///< + UINT32 Reconfigure:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 ResetComplete:1 ; ///< + UINT32 Reserved_15_3:13; ///< + UINT32 Bif0GlobalReset:1 ; ///< + UINT32 Bif0CalibrationReset:1 ; ///< + UINT32 Reserved_31_18:14; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8060_STRUCT; + +// **** D0F0xE4_WRAP_8062 Register Definition **** +// Address +#define D0F0xE4_WRAP_8062_ADDRESS 0x8062 + +// Type +#define D0F0xE4_WRAP_8062_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8062_ReconfigureEn_OFFSET 0 +#define D0F0xE4_WRAP_8062_ReconfigureEn_WIDTH 1 +#define D0F0xE4_WRAP_8062_ReconfigureEn_MASK 0x1 +#define D0F0xE4_WRAP_8062_Reserved_1_1_OFFSET 1 +#define D0F0xE4_WRAP_8062_Reserved_1_1_WIDTH 1 +#define D0F0xE4_WRAP_8062_Reserved_1_1_MASK 0x2 +#define D0F0xE4_WRAP_8062_ResetPeriod_OFFSET 2 +#define D0F0xE4_WRAP_8062_ResetPeriod_WIDTH 3 +#define D0F0xE4_WRAP_8062_ResetPeriod_MASK 0x1c +#define D0F0xE4_WRAP_8062_Reserved_9_5_OFFSET 5 +#define D0F0xE4_WRAP_8062_Reserved_9_5_WIDTH 5 +#define D0F0xE4_WRAP_8062_Reserved_9_5_MASK 0x3e0 +#define D0F0xE4_WRAP_8062_BlockOnIdle_OFFSET 10 +#define D0F0xE4_WRAP_8062_BlockOnIdle_WIDTH 1 +#define D0F0xE4_WRAP_8062_BlockOnIdle_MASK 0x400 +#define D0F0xE4_WRAP_8062_ConfigXferMode_OFFSET 11 +#define D0F0xE4_WRAP_8062_ConfigXferMode_WIDTH 1 +#define D0F0xE4_WRAP_8062_ConfigXferMode_MASK 0x800 +#define D0F0xE4_WRAP_8062_Reserved_31_12_OFFSET 12 +#define D0F0xE4_WRAP_8062_Reserved_31_12_WIDTH 20 +#define D0F0xE4_WRAP_8062_Reserved_31_12_MASK 0xfffff000 + +/// D0F0xE4_WRAP_8062 +typedef union { + struct { ///< + UINT32 ReconfigureEn:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 ResetPeriod:3 ; ///< + UINT32 Reserved_9_5:5 ; ///< + UINT32 BlockOnIdle:1 ; ///< + UINT32 ConfigXferMode:1 ; ///< + UINT32 Reserved_31_12:20; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8062_STRUCT; + +// **** D0F0xE4_WRAP_80F0 Register Definition **** +// Address +#define D0F0xE4_WRAP_80F0_ADDRESS 0x80f0 + +// Type +#define D0F0xE4_WRAP_80F0_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_80F0_MicroSeconds_OFFSET 0 +#define D0F0xE4_WRAP_80F0_MicroSeconds_WIDTH 32 +#define D0F0xE4_WRAP_80F0_MicroSeconds_MASK 0xffffffff + +/// D0F0xE4_WRAP_80F0 +typedef union { + struct { ///< + UINT32 MicroSeconds:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_80F0_STRUCT; + +// **** D0F0xE4_WRAP_80F1 Register Definition **** +// Address +#define D0F0xE4_WRAP_80F1_ADDRESS 0x80f1 + +// Type +#define D0F0xE4_WRAP_80F1_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_80F1_ClockRate_OFFSET 0 +#define D0F0xE4_WRAP_80F1_ClockRate_WIDTH 8 +#define D0F0xE4_WRAP_80F1_ClockRate_MASK 0xff +#define D0F0xE4_WRAP_80F1_Reserved_31_8_OFFSET 8 +#define D0F0xE4_WRAP_80F1_Reserved_31_8_WIDTH 24 +#define D0F0xE4_WRAP_80F1_Reserved_31_8_MASK 0xffffff00 + +/// D0F0xE4_WRAP_80F1 +typedef union { + struct { ///< + UINT32 ClockRate:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_80F1_STRUCT; + +// **** D0F0xE4_WRAP_FFF1 Register Definition **** +// Address +#define D0F0xE4_WRAP_FFF1_ADDRESS 0xfff1 + +// Type +#define D0F0xE4_WRAP_FFF1_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_FFF1_Reserved_0_0_OFFSET 0 +#define D0F0xE4_WRAP_FFF1_Reserved_0_0_WIDTH 1 +#define D0F0xE4_WRAP_FFF1_Reserved_0_0_MASK 0x1 +#define D0F0xE4_WRAP_FFF1_PcieSpareGppFch2_OFFSET 1 +#define D0F0xE4_WRAP_FFF1_PcieSpareGppFch2_WIDTH 4 +#define D0F0xE4_WRAP_FFF1_PcieSpareGppFch2_MASK 0x1e +#define D0F0xE4_WRAP_FFF1_CoreBphyRstPwrSnifferDis_OFFSET 5 +#define D0F0xE4_WRAP_FFF1_CoreBphyRstPwrSnifferDis_WIDTH 1 +#define D0F0xE4_WRAP_FFF1_CoreBphyRstPwrSnifferDis_MASK 0x20 +#define D0F0xE4_WRAP_FFF1_LcSupportGen2_OFFSET 6 +#define D0F0xE4_WRAP_FFF1_LcSupportGen2_WIDTH 1 +#define D0F0xE4_WRAP_FFF1_LcSupportGen2_MASK 0x40 +#define D0F0xE4_WRAP_FFF1_ROSupportGen2_OFFSET 7 +#define D0F0xE4_WRAP_FFF1_ROSupportGen2_WIDTH 1 +#define D0F0xE4_WRAP_FFF1_ROSupportGen2_MASK 0x80 +#define D0F0xE4_WRAP_FFF1_Reserved_31_8_OFFSET 8 +#define D0F0xE4_WRAP_FFF1_Reserved_31_8_WIDTH 24 +#define D0F0xE4_WRAP_FFF1_Reserved_31_8_MASK 0xffffff00 + +/// D0F0xE4_WRAP_FFF1 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 PcieSpareGppFch2:4 ; ///< + UINT32 CoreBphyRstPwrSnifferDis:1 ; ///< + UINT32 LcSupportGen2:1 ; ///< + UINT32 ROSupportGen2:1 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_FFF1_STRUCT; + +// **** D0F0xE4_PIF_0010 Register Definition **** +// Address +#define D0F0xE4_PIF_0010_ADDRESS 0x10 + +// Type +#define D0F0xE4_PIF_0010_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PIF_0010_Reserved_3_0_OFFSET 0 +#define D0F0xE4_PIF_0010_Reserved_3_0_WIDTH 4 +#define D0F0xE4_PIF_0010_Reserved_3_0_MASK 0xf +#define D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET 4 +#define D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH 1 +#define D0F0xE4_PIF_0010_EiDetCycleMode_MASK 0x10 +#define D0F0xE4_PIF_0010_Reserved_5_5_OFFSET 5 +#define D0F0xE4_PIF_0010_Reserved_5_5_WIDTH 1 +#define D0F0xE4_PIF_0010_Reserved_5_5_MASK 0x20 +#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_OFFSET 6 +#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_WIDTH 1 +#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_MASK 0x40 +#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_OFFSET 7 +#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_WIDTH 1 +#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_MASK 0x80 +#define D0F0xE4_PIF_0010_Reserved_16_8_OFFSET 8 +#define D0F0xE4_PIF_0010_Reserved_16_8_WIDTH 9 +#define D0F0xE4_PIF_0010_Reserved_16_8_MASK 0x1ff00 +#define D0F0xE4_PIF_0010_Ls2ExitTime_OFFSET 17 +#define D0F0xE4_PIF_0010_Ls2ExitTime_WIDTH 3 +#define D0F0xE4_PIF_0010_Ls2ExitTime_MASK 0xe0000 +#define D0F0xE4_PIF_0010_Reserved_31_20_OFFSET 20 +#define D0F0xE4_PIF_0010_Reserved_31_20_WIDTH 12 +#define D0F0xE4_PIF_0010_Reserved_31_20_MASK 0xfff00000 + +/// D0F0xE4_PIF_0010 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 EiDetCycleMode:1 ; ///< + UINT32 Reserved_5_5:1 ; ///< + UINT32 RxDetectFifoResetMode:1 ; ///< + UINT32 RxDetectTxPwrMode:1 ; ///< + UINT32 Reserved_16_8:9 ; ///< + UINT32 Ls2ExitTime:3 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PIF_0010_STRUCT; + +// **** D0F0xE4_PIF_0011 Register Definition **** +// Address +#define D0F0xE4_PIF_0011_ADDRESS 0x11 + +// Type +#define D0F0xE4_PIF_0011_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PIF_0011_X2Lane10_OFFSET 0 +#define D0F0xE4_PIF_0011_X2Lane10_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane10_MASK 0x1 +#define D0F0xE4_PIF_0011_X2Lane32_OFFSET 1 +#define D0F0xE4_PIF_0011_X2Lane32_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane32_MASK 0x2 +#define D0F0xE4_PIF_0011_X2Lane54_OFFSET 2 +#define D0F0xE4_PIF_0011_X2Lane54_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane54_MASK 0x4 +#define D0F0xE4_PIF_0011_X2Lane76_OFFSET 3 +#define D0F0xE4_PIF_0011_X2Lane76_WIDTH 1 +#define D0F0xE4_PIF_0011_X2Lane76_MASK 0x8 +#define D0F0xE4_PIF_0011_Reserved_7_4_OFFSET 4 +#define D0F0xE4_PIF_0011_Reserved_7_4_WIDTH 4 +#define D0F0xE4_PIF_0011_Reserved_7_4_MASK 0xf0 +#define D0F0xE4_PIF_0011_X4Lane30_OFFSET 8 +#define D0F0xE4_PIF_0011_X4Lane30_WIDTH 1 +#define D0F0xE4_PIF_0011_X4Lane30_MASK 0x100 +#define D0F0xE4_PIF_0011_X4Lane74_OFFSET 9 +#define D0F0xE4_PIF_0011_X4Lane74_WIDTH 1 +#define D0F0xE4_PIF_0011_X4Lane74_MASK 0x200 +#define D0F0xE4_PIF_0011_Reserved_11_10_OFFSET 10 +#define D0F0xE4_PIF_0011_Reserved_11_10_WIDTH 2 +#define D0F0xE4_PIF_0011_Reserved_11_10_MASK 0xc00 +#define D0F0xE4_PIF_0011_X4Lane52_OFFSET 12 +#define D0F0xE4_PIF_0011_X4Lane52_WIDTH 1 +#define D0F0xE4_PIF_0011_X4Lane52_MASK 0x1000 +#define D0F0xE4_PIF_0011_Reserved_15_13_OFFSET 13 +#define D0F0xE4_PIF_0011_Reserved_15_13_WIDTH 3 +#define D0F0xE4_PIF_0011_Reserved_15_13_MASK 0xe000 +#define D0F0xE4_PIF_0011_X8Lane70_OFFSET 16 +#define D0F0xE4_PIF_0011_X8Lane70_WIDTH 1 +#define D0F0xE4_PIF_0011_X8Lane70_MASK 0x10000 +#define D0F0xE4_PIF_0011_Reserved_24_17_OFFSET 17 +#define D0F0xE4_PIF_0011_Reserved_24_17_WIDTH 8 +#define D0F0xE4_PIF_0011_Reserved_24_17_MASK 0x1fe0000 +#define D0F0xE4_PIF_0011_MultiPif_OFFSET 25 +#define D0F0xE4_PIF_0011_MultiPif_WIDTH 1 +#define D0F0xE4_PIF_0011_MultiPif_MASK 0x2000000 +#define D0F0xE4_PIF_0011_Reserved_31_26_OFFSET 26 +#define D0F0xE4_PIF_0011_Reserved_31_26_WIDTH 6 +#define D0F0xE4_PIF_0011_Reserved_31_26_MASK 0xfc000000 + +/// D0F0xE4_PIF_0011 +typedef union { + struct { ///< + UINT32 X2Lane10:1 ; ///< + UINT32 X2Lane32:1 ; ///< + UINT32 X2Lane54:1 ; ///< + UINT32 X2Lane76:1 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 X4Lane30:1 ; ///< + UINT32 X4Lane74:1 ; ///< + UINT32 Reserved_11_10:2 ; ///< + UINT32 X4Lane52:1 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 X8Lane70:1 ; ///< + UINT32 Reserved_24_17:8 ; ///< + UINT32 MultiPif:1 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PIF_0011_STRUCT; + +// **** D0F0xE4_PIF_0012 Register Definition **** +// Address +#define D0F0xE4_PIF_0012_ADDRESS 0x12 + +// Type +#define D0F0xE4_PIF_0012_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_OFFSET 0 +#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_WIDTH 3 +#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_MASK 0x7 +#define D0F0xE4_PIF_0012_ForceRxEnInL0s_OFFSET 3 +#define D0F0xE4_PIF_0012_ForceRxEnInL0s_WIDTH 1 +#define D0F0xE4_PIF_0012_ForceRxEnInL0s_MASK 0x8 +#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_OFFSET 4 +#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_WIDTH 3 +#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_MASK 0x70 +#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_OFFSET 7 +#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_WIDTH 3 +#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_MASK 0x380 +#define D0F0xE4_PIF_0012_PllPowerStateInOff_OFFSET 10 +#define D0F0xE4_PIF_0012_PllPowerStateInOff_WIDTH 3 +#define D0F0xE4_PIF_0012_PllPowerStateInOff_MASK 0x1c00 +#define D0F0xE4_PIF_0012_Reserved_15_13_OFFSET 13 +#define D0F0xE4_PIF_0012_Reserved_15_13_WIDTH 3 +#define D0F0xE4_PIF_0012_Reserved_15_13_MASK 0xe000 +#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_OFFSET 16 +#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_WIDTH 1 +#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_MASK 0x10000 +#define D0F0xE4_PIF_0012_Reserved_23_17_OFFSET 17 +#define D0F0xE4_PIF_0012_Reserved_23_17_WIDTH 7 +#define D0F0xE4_PIF_0012_Reserved_23_17_MASK 0xfe0000 +#define D0F0xE4_PIF_0012_PllRampUpTime_OFFSET 24 +#define D0F0xE4_PIF_0012_PllRampUpTime_WIDTH 3 +#define D0F0xE4_PIF_0012_PllRampUpTime_MASK 0x7000000 +#define D0F0xE4_PIF_0012_Reserved_27_27_OFFSET 27 +#define D0F0xE4_PIF_0012_Reserved_27_27_WIDTH 1 +#define D0F0xE4_PIF_0012_Reserved_27_27_MASK 0x8000000 +#define D0F0xE4_PIF_0012_PllPwrOverrideEn_OFFSET 28 +#define D0F0xE4_PIF_0012_PllPwrOverrideEn_WIDTH 1 +#define D0F0xE4_PIF_0012_PllPwrOverrideEn_MASK 0x10000000 +#define D0F0xE4_PIF_0012_PllPwrOverrideVal_OFFSET 29 +#define D0F0xE4_PIF_0012_PllPwrOverrideVal_WIDTH 3 +#define D0F0xE4_PIF_0012_PllPwrOverrideVal_MASK 0xe0000000 + +/// D0F0xE4_PIF_0012 +typedef union { + struct { ///< + UINT32 TxPowerStateInTxs2:3 ; ///< + UINT32 ForceRxEnInL0s:1 ; ///< + UINT32 RxPowerStateInRxs2:3 ; ///< + UINT32 PllPowerStateInTxs2:3 ; ///< + UINT32 PllPowerStateInOff:3 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 Tx2p5clkClockGatingEn:1 ; ///< + UINT32 Reserved_23_17:7 ; ///< + UINT32 PllRampUpTime:3 ; ///< + UINT32 Reserved_27_27:1 ; ///< + UINT32 PllPwrOverrideEn:1 ; ///< + UINT32 PllPwrOverrideVal:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PIF_0012_STRUCT; + +// **** D0F0xE4_PIF_0013 Register Definition **** +// Address +#define D0F0xE4_PIF_0013_ADDRESS 0x13 + +// Type +#define D0F0xE4_PIF_0013_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_OFFSET 0 +#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_WIDTH 3 +#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_MASK 0x7 +#define D0F0xE4_PIF_0013_ForceRxEnInL0s_OFFSET 3 +#define D0F0xE4_PIF_0013_ForceRxEnInL0s_WIDTH 1 +#define D0F0xE4_PIF_0013_ForceRxEnInL0s_MASK 0x8 +#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_OFFSET 4 +#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_WIDTH 3 +#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_MASK 0x70 +#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_OFFSET 7 +#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_WIDTH 3 +#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_MASK 0x380 +#define D0F0xE4_PIF_0013_PllPowerStateInOff_OFFSET 10 +#define D0F0xE4_PIF_0013_PllPowerStateInOff_WIDTH 3 +#define D0F0xE4_PIF_0013_PllPowerStateInOff_MASK 0x1c00 +#define D0F0xE4_PIF_0013_Reserved_15_13_OFFSET 13 +#define D0F0xE4_PIF_0013_Reserved_15_13_WIDTH 3 +#define D0F0xE4_PIF_0013_Reserved_15_13_MASK 0xe000 +#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_OFFSET 16 +#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_WIDTH 1 +#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_MASK 0x10000 +#define D0F0xE4_PIF_0013_Reserved_23_17_OFFSET 17 +#define D0F0xE4_PIF_0013_Reserved_23_17_WIDTH 7 +#define D0F0xE4_PIF_0013_Reserved_23_17_MASK 0xfe0000 +#define D0F0xE4_PIF_0013_PllRampUpTime_OFFSET 24 +#define D0F0xE4_PIF_0013_PllRampUpTime_WIDTH 3 +#define D0F0xE4_PIF_0013_PllRampUpTime_MASK 0x7000000 +#define D0F0xE4_PIF_0013_Reserved_27_27_OFFSET 27 +#define D0F0xE4_PIF_0013_Reserved_27_27_WIDTH 1 +#define D0F0xE4_PIF_0013_Reserved_27_27_MASK 0x8000000 +#define D0F0xE4_PIF_0013_PllPwrOverrideEn_OFFSET 28 +#define D0F0xE4_PIF_0013_PllPwrOverrideEn_WIDTH 1 +#define D0F0xE4_PIF_0013_PllPwrOverrideEn_MASK 0x10000000 +#define D0F0xE4_PIF_0013_PllPwrOverrideVal_OFFSET 29 +#define D0F0xE4_PIF_0013_PllPwrOverrideVal_WIDTH 3 +#define D0F0xE4_PIF_0013_PllPwrOverrideVal_MASK 0xe0000000 + +/// D0F0xE4_PIF_0013 +typedef union { + struct { ///< + UINT32 TxPowerStateInTxs2:3 ; ///< + UINT32 ForceRxEnInL0s:1 ; ///< + UINT32 RxPowerStateInRxs2:3 ; ///< + UINT32 PllPowerStateInTxs2:3 ; ///< + UINT32 PllPowerStateInOff:3 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 Tx2p5clkClockGatingEn:1 ; ///< + UINT32 Reserved_23_17:7 ; ///< + UINT32 PllRampUpTime:3 ; ///< + UINT32 Reserved_27_27:1 ; ///< + UINT32 PllPwrOverrideEn:1 ; ///< + UINT32 PllPwrOverrideVal:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PIF_0013_STRUCT; + +// **** D0F0xE4_PIF_0015 Register Definition **** +// Address +#define D0F0xE4_PIF_0015_ADDRESS 0x15 + +// Type +#define D0F0xE4_PIF_0015_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PIF_0015_TxPhyStatus00_OFFSET 0 +#define D0F0xE4_PIF_0015_TxPhyStatus00_WIDTH 1 +#define D0F0xE4_PIF_0015_TxPhyStatus00_MASK 0x1 +#define D0F0xE4_PIF_0015_TxPhyStatus01_OFFSET 1 +#define D0F0xE4_PIF_0015_TxPhyStatus01_WIDTH 1 +#define D0F0xE4_PIF_0015_TxPhyStatus01_MASK 0x2 +#define D0F0xE4_PIF_0015_TxPhyStatus02_OFFSET 2 +#define D0F0xE4_PIF_0015_TxPhyStatus02_WIDTH 1 +#define D0F0xE4_PIF_0015_TxPhyStatus02_MASK 0x4 +#define D0F0xE4_PIF_0015_TxPhyStatus03_OFFSET 3 +#define D0F0xE4_PIF_0015_TxPhyStatus03_WIDTH 1 +#define D0F0xE4_PIF_0015_TxPhyStatus03_MASK 0x8 +#define D0F0xE4_PIF_0015_TxPhyStatus04_OFFSET 4 +#define D0F0xE4_PIF_0015_TxPhyStatus04_WIDTH 1 +#define D0F0xE4_PIF_0015_TxPhyStatus04_MASK 0x10 +#define D0F0xE4_PIF_0015_TxPhyStatus05_OFFSET 5 +#define D0F0xE4_PIF_0015_TxPhyStatus05_WIDTH 1 +#define D0F0xE4_PIF_0015_TxPhyStatus05_MASK 0x20 +#define D0F0xE4_PIF_0015_TxPhyStatus06_OFFSET 6 +#define D0F0xE4_PIF_0015_TxPhyStatus06_WIDTH 1 +#define D0F0xE4_PIF_0015_TxPhyStatus06_MASK 0x40 +#define D0F0xE4_PIF_0015_TxPhyStatus07_OFFSET 7 +#define D0F0xE4_PIF_0015_TxPhyStatus07_WIDTH 1 +#define D0F0xE4_PIF_0015_TxPhyStatus07_MASK 0x80 +#define D0F0xE4_PIF_0015_Reserved_31_8_OFFSET 8 +#define D0F0xE4_PIF_0015_Reserved_31_8_WIDTH 24 +#define D0F0xE4_PIF_0015_Reserved_31_8_MASK 0xffffff00 + +/// D0F0xE4_PIF_0015 +typedef union { + struct { ///< + UINT32 TxPhyStatus00:1 ; ///< + UINT32 TxPhyStatus01:1 ; ///< + UINT32 TxPhyStatus02:1 ; ///< + UINT32 TxPhyStatus03:1 ; ///< + UINT32 TxPhyStatus04:1 ; ///< + UINT32 TxPhyStatus05:1 ; ///< + UINT32 TxPhyStatus06:1 ; ///< + UINT32 TxPhyStatus07:1 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PIF_0015_STRUCT; + +// **** D0F0xE4_CORE_0002 Register Definition **** +// Address +#define D0F0xE4_CORE_0002_ADDRESS 0x2 + +// Type +#define D0F0xE4_CORE_0002_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_0002_HwDebug_0__OFFSET 0 +#define D0F0xE4_CORE_0002_HwDebug_0__WIDTH 1 +#define D0F0xE4_CORE_0002_HwDebug_0__MASK 0x1 +#define D0F0xE4_CORE_0002_Reserved_31_1_OFFSET 1 +#define D0F0xE4_CORE_0002_Reserved_31_1_WIDTH 31 +#define D0F0xE4_CORE_0002_Reserved_31_1_MASK 0xfffffffe + +/// D0F0xE4_CORE_0002 +typedef union { + struct { ///< + UINT32 HwDebug_0_:1 ; ///< + UINT32 Reserved_31_1:31; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_0002_STRUCT; + +// **** D0F0xE4_CORE_0010 Register Definition **** +// Address +#define D0F0xE4_CORE_0010_ADDRESS 0x10 + +// Type +#define D0F0xE4_CORE_0010_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_0010_HwInitWrLock_OFFSET 0 +#define D0F0xE4_CORE_0010_HwInitWrLock_WIDTH 1 +#define D0F0xE4_CORE_0010_HwInitWrLock_MASK 0x1 +#define D0F0xE4_CORE_0010_Reserved_8_1_OFFSET 1 +#define D0F0xE4_CORE_0010_Reserved_8_1_WIDTH 8 +#define D0F0xE4_CORE_0010_Reserved_8_1_MASK 0x1fe +#define D0F0xE4_CORE_0010_UmiNpMemWrite_OFFSET 9 +#define D0F0xE4_CORE_0010_UmiNpMemWrite_WIDTH 1 +#define D0F0xE4_CORE_0010_UmiNpMemWrite_MASK 0x200 +#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_OFFSET 10 +#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_WIDTH 3 +#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_MASK 0x1c00 +#define D0F0xE4_CORE_0010_Reserved_31_13_OFFSET 13 +#define D0F0xE4_CORE_0010_Reserved_31_13_WIDTH 19 +#define D0F0xE4_CORE_0010_Reserved_31_13_MASK 0xffffe000 + +/// D0F0xE4_CORE_0010 +typedef union { + struct { ///< + UINT32 HwInitWrLock:1 ; ///< + UINT32 Reserved_8_1:8 ; ///< + UINT32 UmiNpMemWrite:1 ; ///< + UINT32 RxSbAdjPayloadSize:3 ; ///< + UINT32 Reserved_31_13:19; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_0010_STRUCT; + +// **** D0F0xE4_CORE_0011 Register Definition **** +// Address +#define D0F0xE4_CORE_0011_ADDRESS 0x11 + +// Type +#define D0F0xE4_CORE_0011_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_0011_DynClkLatency_OFFSET 0 +#define D0F0xE4_CORE_0011_DynClkLatency_WIDTH 4 +#define D0F0xE4_CORE_0011_DynClkLatency_MASK 0xf +#define D0F0xE4_CORE_0011_Reserved_15_4_OFFSET 4 +#define D0F0xE4_CORE_0011_Reserved_15_4_WIDTH 12 +#define D0F0xE4_CORE_0011_Reserved_15_4_MASK 0xfff0 +#define D0F0xE4_CORE_0011_CiMaxPayloadSizeMode_OFFSET 16 +#define D0F0xE4_CORE_0011_CiMaxPayloadSizeMode_WIDTH 1 +#define D0F0xE4_CORE_0011_CiMaxPayloadSizeMode_MASK 0x10000 +#define D0F0xE4_CORE_0011_CiPrivMaxPayloadSize_OFFSET 17 +#define D0F0xE4_CORE_0011_CiPrivMaxPayloadSize_WIDTH 3 +#define D0F0xE4_CORE_0011_CiPrivMaxPayloadSize_MASK 0xe0000 +#define D0F0xE4_CORE_0011_CiMaxReadRequestSizeMode_OFFSET 20 +#define D0F0xE4_CORE_0011_CiMaxReadRequestSizeMode_WIDTH 1 +#define D0F0xE4_CORE_0011_CiMaxReadRequestSizeMode_MASK 0x100000 +#define D0F0xE4_CORE_0011_CiPrivMaxReadRequestSize_OFFSET 21 +#define D0F0xE4_CORE_0011_CiPrivMaxReadRequestSize_WIDTH 3 +#define D0F0xE4_CORE_0011_CiPrivMaxReadRequestSize_MASK 0xe00000 +#define D0F0xE4_CORE_0011_CiMaxReadSafeMode_OFFSET 24 +#define D0F0xE4_CORE_0011_CiMaxReadSafeMode_WIDTH 1 +#define D0F0xE4_CORE_0011_CiMaxReadSafeMode_MASK 0x1000000 +#define D0F0xE4_CORE_0011_CiExtendedTagEnOverride_OFFSET 25 +#define D0F0xE4_CORE_0011_CiExtendedTagEnOverride_WIDTH 1 +#define D0F0xE4_CORE_0011_CiExtendedTagEnOverride_MASK 0x2000000 +#define D0F0xE4_CORE_0011_CiMaxCplPayloadSizeMode_OFFSET 26 +#define D0F0xE4_CORE_0011_CiMaxCplPayloadSizeMode_WIDTH 1 +#define D0F0xE4_CORE_0011_CiMaxCplPayloadSizeMode_MASK 0x4000000 +#define D0F0xE4_CORE_0011_CiPrivMaxCplPayloadSize_OFFSET 27 +#define D0F0xE4_CORE_0011_CiPrivMaxCplPayloadSize_WIDTH 3 +#define D0F0xE4_CORE_0011_CiPrivMaxCplPayloadSize_MASK 0x38000000 +#define D0F0xE4_CORE_0011_Reserved_31_30_OFFSET 30 +#define D0F0xE4_CORE_0011_Reserved_31_30_WIDTH 2 +#define D0F0xE4_CORE_0011_Reserved_31_30_MASK 0xc0000000 + +/// D0F0xE4_CORE_0011 +typedef union { + struct { ///< + UINT32 DynClkLatency:4 ; ///< + UINT32 Reserved_15_4:12; ///< + UINT32 CiMaxPayloadSizeMode:1 ; ///< + UINT32 CiPrivMaxPayloadSize:3 ; ///< + UINT32 CiMaxReadRequestSizeMode:1 ; ///< + UINT32 CiPrivMaxReadRequestSize:3 ; ///< + UINT32 CiMaxReadSafeMode:1 ; ///< + UINT32 CiExtendedTagEnOverride:1 ; ///< + UINT32 CiMaxCplPayloadSizeMode:1 ; ///< + UINT32 CiPrivMaxCplPayloadSize:3 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_0011_STRUCT; + +// **** D0F0xE4_CORE_001C Register Definition **** +// Address +#define D0F0xE4_CORE_001C_ADDRESS 0x1c + +// Type +#define D0F0xE4_CORE_001C_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET 0 +#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_WIDTH 1 +#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK 0x1 +#define D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET 1 +#define D0F0xE4_CORE_001C_TxArbSlvLimit_WIDTH 5 +#define D0F0xE4_CORE_001C_TxArbSlvLimit_MASK 0x3e +#define D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET 6 +#define D0F0xE4_CORE_001C_TxArbMstLimit_WIDTH 5 +#define D0F0xE4_CORE_001C_TxArbMstLimit_MASK 0x7c0 +#define D0F0xE4_CORE_001C_Reserved_31_11_OFFSET 11 +#define D0F0xE4_CORE_001C_Reserved_31_11_WIDTH 21 +#define D0F0xE4_CORE_001C_Reserved_31_11_MASK 0xfffff800 + +/// D0F0xE4_CORE_001C +typedef union { + struct { ///< + UINT32 TxArbRoundRobinEn:1 ; ///< + UINT32 TxArbSlvLimit:5 ; ///< + UINT32 TxArbMstLimit:5 ; ///< + UINT32 Reserved_31_11:21; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_001C_STRUCT; + +// **** D0F0xE4_CORE_0020 Register Definition **** +// Address +#define D0F0xE4_CORE_0020_ADDRESS 0x20 + +// Type +#define D0F0xE4_CORE_0020_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_0020_Reserved_7_0_OFFSET 0 +#define D0F0xE4_CORE_0020_Reserved_7_0_WIDTH 8 +#define D0F0xE4_CORE_0020_Reserved_7_0_MASK 0xff +#define D0F0xE4_CORE_0020_CiSlvOrderingDis_OFFSET 8 +#define D0F0xE4_CORE_0020_CiSlvOrderingDis_WIDTH 1 +#define D0F0xE4_CORE_0020_CiSlvOrderingDis_MASK 0x100 +#define D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET 9 +#define D0F0xE4_CORE_0020_CiRcOrderingDis_WIDTH 1 +#define D0F0xE4_CORE_0020_CiRcOrderingDis_MASK 0x200 +#define D0F0xE4_CORE_0020_Reserved_31_10_OFFSET 10 +#define D0F0xE4_CORE_0020_Reserved_31_10_WIDTH 22 +#define D0F0xE4_CORE_0020_Reserved_31_10_MASK 0xfffffc00 + +/// D0F0xE4_CORE_0020 +typedef union { + struct { ///< + UINT32 Reserved_7_0:8 ; ///< + UINT32 CiSlvOrderingDis:1 ; ///< + UINT32 CiRcOrderingDis:1 ; ///< + UINT32 Reserved_31_10:22; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_0020_STRUCT; + +// **** D0F0xE4_CORE_0040 Register Definition **** +// Address +#define D0F0xE4_CORE_0040_ADDRESS 0x40 + +// Type +#define D0F0xE4_CORE_0040_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_0040_Reserved_13_0_OFFSET 0 +#define D0F0xE4_CORE_0040_Reserved_13_0_WIDTH 14 +#define D0F0xE4_CORE_0040_Reserved_13_0_MASK 0x3fff +#define D0F0xE4_CORE_0040_PElecIdleMode_OFFSET 14 +#define D0F0xE4_CORE_0040_PElecIdleMode_WIDTH 2 +#define D0F0xE4_CORE_0040_PElecIdleMode_MASK 0xc000 +#define D0F0xE4_CORE_0040_Reserved_31_16_OFFSET 16 +#define D0F0xE4_CORE_0040_Reserved_31_16_WIDTH 16 +#define D0F0xE4_CORE_0040_Reserved_31_16_MASK 0xffff0000 + +/// D0F0xE4_CORE_0040 +typedef union { + struct { ///< + UINT32 Reserved_13_0:14; ///< + UINT32 PElecIdleMode:2 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_0040_STRUCT; + +// **** D0F0xE4_CORE_00B0 Register Definition **** +// Address +#define D0F0xE4_CORE_00B0_ADDRESS 0xb0 + +// Type +#define D0F0xE4_CORE_00B0_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_00B0_Reserved_1_0_OFFSET 0 +#define D0F0xE4_CORE_00B0_Reserved_1_0_WIDTH 2 +#define D0F0xE4_CORE_00B0_Reserved_1_0_MASK 0x3 +#define D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET 2 +#define D0F0xE4_CORE_00B0_StrapF0MsiEn_WIDTH 1 +#define D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK 0x4 +#define D0F0xE4_CORE_00B0_Reserved_4_3_OFFSET 3 +#define D0F0xE4_CORE_00B0_Reserved_4_3_WIDTH 2 +#define D0F0xE4_CORE_00B0_Reserved_4_3_MASK 0x18 +#define D0F0xE4_CORE_00B0_StrapF0AerEn_OFFSET 5 +#define D0F0xE4_CORE_00B0_StrapF0AerEn_WIDTH 1 +#define D0F0xE4_CORE_00B0_StrapF0AerEn_MASK 0x20 +#define D0F0xE4_CORE_00B0_Reserved_31_6_OFFSET 6 +#define D0F0xE4_CORE_00B0_Reserved_31_6_WIDTH 26 +#define D0F0xE4_CORE_00B0_Reserved_31_6_MASK 0xffffffc0 + +/// D0F0xE4_CORE_00B0 +typedef union { + struct { ///< + UINT32 Reserved_1_0:2 ; ///< + UINT32 StrapF0MsiEn:1 ; ///< + UINT32 Reserved_4_3:2 ; ///< + UINT32 StrapF0AerEn:1 ; ///< + UINT32 Reserved_31_6:26; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_00B0_STRUCT; + +// **** D0F0xE4_CORE_00C0 Register Definition **** +// Address +#define D0F0xE4_CORE_00C0_ADDRESS 0xc0 + +// Type +#define D0F0xE4_CORE_00C0_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_00C0_Reserved_27_0_OFFSET 0 +#define D0F0xE4_CORE_00C0_Reserved_27_0_WIDTH 28 +#define D0F0xE4_CORE_00C0_Reserved_27_0_MASK 0xfffffff +#define D0F0xE4_CORE_00C0_StrapReverseAll_OFFSET 28 +#define D0F0xE4_CORE_00C0_StrapReverseAll_WIDTH 1 +#define D0F0xE4_CORE_00C0_StrapReverseAll_MASK 0x10000000 +#define D0F0xE4_CORE_00C0_StrapMstAdr64En_OFFSET 29 +#define D0F0xE4_CORE_00C0_StrapMstAdr64En_WIDTH 1 +#define D0F0xE4_CORE_00C0_StrapMstAdr64En_MASK 0x20000000 +#define D0F0xE4_CORE_00C0_StrapFlrEn_OFFSET 30 +#define D0F0xE4_CORE_00C0_StrapFlrEn_WIDTH 1 +#define D0F0xE4_CORE_00C0_StrapFlrEn_MASK 0x40000000 +#define D0F0xE4_CORE_00C0_Reserved_31_31_OFFSET 31 +#define D0F0xE4_CORE_00C0_Reserved_31_31_WIDTH 1 +#define D0F0xE4_CORE_00C0_Reserved_31_31_MASK 0x80000000 + +/// D0F0xE4_CORE_00C0 +typedef union { + struct { ///< + UINT32 Reserved_27_0:28; ///< + UINT32 StrapReverseAll:1 ; ///< + UINT32 StrapMstAdr64En:1 ; ///< + UINT32 StrapFlrEn:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_00C0_STRUCT; + +// **** D0F0xE4_CORE_00C1 Register Definition **** +// Address +#define D0F0xE4_CORE_00C1_ADDRESS 0xc1 + +// Type +#define D0F0xE4_CORE_00C1_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET 0 +#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_WIDTH 1 +#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK 0x1 +#define D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET 1 +#define D0F0xE4_CORE_00C1_StrapGen2Compliance_WIDTH 1 +#define D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK 0x2 +#define D0F0xE4_CORE_00C1_Reserved_31_2_OFFSET 2 +#define D0F0xE4_CORE_00C1_Reserved_31_2_WIDTH 30 +#define D0F0xE4_CORE_00C1_Reserved_31_2_MASK 0xfffffffc + +/// D0F0xE4_CORE_00C1 +typedef union { + struct { ///< + UINT32 StrapLinkBwNotificationCapEn:1 ; ///< + UINT32 StrapGen2Compliance:1 ; ///< + UINT32 Reserved_31_2:30; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_00C1_STRUCT; + +// **** D0F0xE4_PHY_0009 Register Definition **** +// Address +#define D0F0xE4_PHY_0009_ADDRESS 0x9 + +// Type +#define D0F0xE4_PHY_0009_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_0009_Reserved_23_0_OFFSET 0 +#define D0F0xE4_PHY_0009_Reserved_23_0_WIDTH 24 +#define D0F0xE4_PHY_0009_Reserved_23_0_MASK 0xffffff +#define D0F0xE4_PHY_0009_ClkOff_OFFSET 24 +#define D0F0xE4_PHY_0009_ClkOff_WIDTH 1 +#define D0F0xE4_PHY_0009_ClkOff_MASK 0x1000000 +#define D0F0xE4_PHY_0009_DisplayStream_OFFSET 25 +#define D0F0xE4_PHY_0009_DisplayStream_WIDTH 1 +#define D0F0xE4_PHY_0009_DisplayStream_MASK 0x2000000 +#define D0F0xE4_PHY_0009_Reserved_27_26_OFFSET 26 +#define D0F0xE4_PHY_0009_Reserved_27_26_WIDTH 2 +#define D0F0xE4_PHY_0009_Reserved_27_26_MASK 0xc000000 +#define D0F0xE4_PHY_0009_CascadedPllSel_OFFSET 28 +#define D0F0xE4_PHY_0009_CascadedPllSel_WIDTH 1 +#define D0F0xE4_PHY_0009_CascadedPllSel_MASK 0x10000000 +#define D0F0xE4_PHY_0009_Reserved_30_29_OFFSET 29 +#define D0F0xE4_PHY_0009_Reserved_30_29_WIDTH 2 +#define D0F0xE4_PHY_0009_Reserved_30_29_MASK 0x60000000 +#define D0F0xE4_PHY_0009_PCIePllSel_OFFSET 31 +#define D0F0xE4_PHY_0009_PCIePllSel_WIDTH 1 +#define D0F0xE4_PHY_0009_PCIePllSel_MASK 0x80000000 + +/// D0F0xE4_PHY_0009 +typedef union { + struct { ///< + UINT32 Reserved_23_0:24; ///< + UINT32 ClkOff:1 ; ///< + UINT32 DisplayStream:1 ; ///< + UINT32 Reserved_27_26:2 ; ///< + UINT32 CascadedPllSel:1 ; ///< + UINT32 Reserved_30_29:2 ; ///< + UINT32 PCIePllSel:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_0009_STRUCT; + +// **** D0F0xE4_PHY_000A Register Definition **** +// Address +#define D0F0xE4_PHY_000A_ADDRESS 0xa + +// Type +#define D0F0xE4_PHY_000A_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_000A_Reserved_23_0_OFFSET 0 +#define D0F0xE4_PHY_000A_Reserved_23_0_WIDTH 24 +#define D0F0xE4_PHY_000A_Reserved_23_0_MASK 0xffffff +#define D0F0xE4_PHY_000A_ClkOff_OFFSET 24 +#define D0F0xE4_PHY_000A_ClkOff_WIDTH 1 +#define D0F0xE4_PHY_000A_ClkOff_MASK 0x1000000 +#define D0F0xE4_PHY_000A_DisplayStream_OFFSET 25 +#define D0F0xE4_PHY_000A_DisplayStream_WIDTH 1 +#define D0F0xE4_PHY_000A_DisplayStream_MASK 0x2000000 +#define D0F0xE4_PHY_000A_Reserved_27_26_OFFSET 26 +#define D0F0xE4_PHY_000A_Reserved_27_26_WIDTH 2 +#define D0F0xE4_PHY_000A_Reserved_27_26_MASK 0xc000000 +#define D0F0xE4_PHY_000A_CascadedPllSel_OFFSET 28 +#define D0F0xE4_PHY_000A_CascadedPllSel_WIDTH 1 +#define D0F0xE4_PHY_000A_CascadedPllSel_MASK 0x10000000 +#define D0F0xE4_PHY_000A_Reserved_30_29_OFFSET 29 +#define D0F0xE4_PHY_000A_Reserved_30_29_WIDTH 2 +#define D0F0xE4_PHY_000A_Reserved_30_29_MASK 0x60000000 +#define D0F0xE4_PHY_000A_PCIePllSel_OFFSET 31 +#define D0F0xE4_PHY_000A_PCIePllSel_WIDTH 1 +#define D0F0xE4_PHY_000A_PCIePllSel_MASK 0x80000000 + +/// D0F0xE4_PHY_000A +typedef union { + struct { ///< + UINT32 Reserved_23_0:24; ///< + UINT32 ClkOff:1 ; ///< + UINT32 DisplayStream:1 ; ///< + UINT32 Reserved_27_26:2 ; ///< + UINT32 CascadedPllSel:1 ; ///< + UINT32 Reserved_30_29:2 ; ///< + UINT32 PCIePllSel:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_000A_STRUCT; + +// **** D0F0xE4_PHY_000B Register Definition **** +// Address +#define D0F0xE4_PHY_000B_ADDRESS 0xb + +// Type +#define D0F0xE4_PHY_000B_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_000B_TxPwrSbiEn_OFFSET 0 +#define D0F0xE4_PHY_000B_TxPwrSbiEn_WIDTH 1 +#define D0F0xE4_PHY_000B_TxPwrSbiEn_MASK 0x1 +#define D0F0xE4_PHY_000B_RxPwrSbiEn_OFFSET 1 +#define D0F0xE4_PHY_000B_RxPwrSbiEn_WIDTH 1 +#define D0F0xE4_PHY_000B_RxPwrSbiEn_MASK 0x2 +#define D0F0xE4_PHY_000B_PcieModeSbiEn_OFFSET 2 +#define D0F0xE4_PHY_000B_PcieModeSbiEn_WIDTH 1 +#define D0F0xE4_PHY_000B_PcieModeSbiEn_MASK 0x4 +#define D0F0xE4_PHY_000B_FreqDivSbiEn_OFFSET 3 +#define D0F0xE4_PHY_000B_FreqDivSbiEn_WIDTH 1 +#define D0F0xE4_PHY_000B_FreqDivSbiEn_MASK 0x8 +#define D0F0xE4_PHY_000B_DllLockSbiEn_OFFSET 4 +#define D0F0xE4_PHY_000B_DllLockSbiEn_WIDTH 1 +#define D0F0xE4_PHY_000B_DllLockSbiEn_MASK 0x10 +#define D0F0xE4_PHY_000B_OffsetCancelSbiEn_OFFSET 5 +#define D0F0xE4_PHY_000B_OffsetCancelSbiEn_WIDTH 1 +#define D0F0xE4_PHY_000B_OffsetCancelSbiEn_MASK 0x20 +#define D0F0xE4_PHY_000B_SkipBitSbiEn_OFFSET 6 +#define D0F0xE4_PHY_000B_SkipBitSbiEn_WIDTH 1 +#define D0F0xE4_PHY_000B_SkipBitSbiEn_MASK 0x40 +#define D0F0xE4_PHY_000B_IncoherentClkSbiEn_OFFSET 7 +#define D0F0xE4_PHY_000B_IncoherentClkSbiEn_WIDTH 1 +#define D0F0xE4_PHY_000B_IncoherentClkSbiEn_MASK 0x80 +#define D0F0xE4_PHY_000B_EiDetSbiEn_OFFSET 8 +#define D0F0xE4_PHY_000B_EiDetSbiEn_WIDTH 1 +#define D0F0xE4_PHY_000B_EiDetSbiEn_MASK 0x100 +#define D0F0xE4_PHY_000B_Reserved_13_9_OFFSET 9 +#define D0F0xE4_PHY_000B_Reserved_13_9_WIDTH 5 +#define D0F0xE4_PHY_000B_Reserved_13_9_MASK 0x3e00 +#define D0F0xE4_PHY_000B_MargPktSbiEn_OFFSET 14 +#define D0F0xE4_PHY_000B_MargPktSbiEn_WIDTH 1 +#define D0F0xE4_PHY_000B_MargPktSbiEn_MASK 0x4000 +#define D0F0xE4_PHY_000B_PllCmpPktSbiEn_OFFSET 15 +#define D0F0xE4_PHY_000B_PllCmpPktSbiEn_WIDTH 1 +#define D0F0xE4_PHY_000B_PllCmpPktSbiEn_MASK 0x8000 +#define D0F0xE4_PHY_000B_Reserved_31_16_OFFSET 16 +#define D0F0xE4_PHY_000B_Reserved_31_16_WIDTH 16 +#define D0F0xE4_PHY_000B_Reserved_31_16_MASK 0xffff0000 + +/// D0F0xE4_PHY_000B +typedef union { + struct { ///< + UINT32 TxPwrSbiEn:1 ; ///< + UINT32 RxPwrSbiEn:1 ; ///< + UINT32 PcieModeSbiEn:1 ; ///< + UINT32 FreqDivSbiEn:1 ; ///< + UINT32 DllLockSbiEn:1 ; ///< + UINT32 OffsetCancelSbiEn:1 ; ///< + UINT32 SkipBitSbiEn:1 ; ///< + UINT32 IncoherentClkSbiEn:1 ; ///< + UINT32 EiDetSbiEn:1 ; ///< + UINT32 Reserved_13_9:5 ; ///< + UINT32 MargPktSbiEn:1 ; ///< + UINT32 PllCmpPktSbiEn:1 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_000B_STRUCT; + +// **** D0F0xE4_PHY_2000 Register Definition **** +// Address +#define D0F0xE4_PHY_2000_ADDRESS 0x2000 + +// Type +#define D0F0xE4_PHY_2000_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_2000_PllPowerDownEn_OFFSET 0 +#define D0F0xE4_PHY_2000_PllPowerDownEn_WIDTH 3 +#define D0F0xE4_PHY_2000_PllPowerDownEn_MASK 0x7 +#define D0F0xE4_PHY_2000_PllAutoPwrDownDis_OFFSET 3 +#define D0F0xE4_PHY_2000_PllAutoPwrDownDis_WIDTH 1 +#define D0F0xE4_PHY_2000_PllAutoPwrDownDis_MASK 0x8 +#define D0F0xE4_PHY_2000_Reserved_31_4_OFFSET 4 +#define D0F0xE4_PHY_2000_Reserved_31_4_WIDTH 28 +#define D0F0xE4_PHY_2000_Reserved_31_4_MASK 0xfffffff0 + +/// D0F0xE4_PHY_2000 +typedef union { + struct { ///< + UINT32 PllPowerDownEn:3 ; ///< + UINT32 PllAutoPwrDownDis:1 ; ///< + UINT32 Reserved_31_4:28; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_2000_STRUCT; + +// **** D0F0xE4_PHY_2002 Register Definition **** +// Address +#define D0F0xE4_PHY_2002_ADDRESS 0x2002 + +// Type +#define D0F0xE4_PHY_2002_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_2002_Reserved_26_0_OFFSET 0 +#define D0F0xE4_PHY_2002_Reserved_26_0_WIDTH 27 +#define D0F0xE4_PHY_2002_Reserved_26_0_MASK 0x7ffffff +#define D0F0xE4_PHY_2002_RoCalEn_OFFSET 27 +#define D0F0xE4_PHY_2002_RoCalEn_WIDTH 1 +#define D0F0xE4_PHY_2002_RoCalEn_MASK 0x8000000 +#define D0F0xE4_PHY_2002_Reserved_30_28_OFFSET 28 +#define D0F0xE4_PHY_2002_Reserved_30_28_WIDTH 3 +#define D0F0xE4_PHY_2002_Reserved_30_28_MASK 0x70000000 +#define D0F0xE4_PHY_2002_IsLc_OFFSET 31 +#define D0F0xE4_PHY_2002_IsLc_WIDTH 1 +#define D0F0xE4_PHY_2002_IsLc_MASK 0x80000000 + +/// D0F0xE4_PHY_2002 +typedef union { + struct { ///< + UINT32 Reserved_26_0:27; ///< + UINT32 RoCalEn:1 ; ///< + UINT32 Reserved_30_28:3 ; ///< + UINT32 IsLc:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_2002_STRUCT; + +// **** D0F0xE4_PHY_2005 Register Definition **** +// Address +#define D0F0xE4_PHY_2005_ADDRESS 0x2005 + +// Type +#define D0F0xE4_PHY_2005_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_2005_PllClkFreq_OFFSET 0 +#define D0F0xE4_PHY_2005_PllClkFreq_WIDTH 4 +#define D0F0xE4_PHY_2005_PllClkFreq_MASK 0xf +#define D0F0xE4_PHY_2005_Reserved_8_4_OFFSET 4 +#define D0F0xE4_PHY_2005_Reserved_8_4_WIDTH 5 +#define D0F0xE4_PHY_2005_Reserved_8_4_MASK 0x1f0 +#define D0F0xE4_PHY_2005_PllClkFreqExt_OFFSET 9 +#define D0F0xE4_PHY_2005_PllClkFreqExt_WIDTH 2 +#define D0F0xE4_PHY_2005_PllClkFreqExt_MASK 0x600 +#define D0F0xE4_PHY_2005_Reserved_12_11_OFFSET 11 +#define D0F0xE4_PHY_2005_Reserved_12_11_WIDTH 2 +#define D0F0xE4_PHY_2005_Reserved_12_11_MASK 0x1800 +#define D0F0xE4_PHY_2005_PllMode_OFFSET 13 +#define D0F0xE4_PHY_2005_PllMode_WIDTH 2 +#define D0F0xE4_PHY_2005_PllMode_MASK 0x6000 +#define D0F0xE4_PHY_2005_Reserved_31_15_OFFSET 15 +#define D0F0xE4_PHY_2005_Reserved_31_15_WIDTH 17 +#define D0F0xE4_PHY_2005_Reserved_31_15_MASK 0xffff8000 + +/// D0F0xE4_PHY_2005 +typedef union { + struct { ///< + UINT32 PllClkFreq:4 ; ///< + UINT32 Reserved_8_4:5 ; ///< + UINT32 PllClkFreqExt:2 ; ///< + UINT32 Reserved_12_11:2 ; ///< + UINT32 PllMode:2 ; ///< + UINT32 Reserved_31_15:17; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_2005_STRUCT; + +// **** D0F0xE4_PHY_2008 Register Definition **** +// Address +#define D0F0xE4_PHY_2008_ADDRESS 0x2008 + +// Type +#define D0F0xE4_PHY_2008_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_2008_PllControlUpdate_OFFSET 0 +#define D0F0xE4_PHY_2008_PllControlUpdate_WIDTH 1 +#define D0F0xE4_PHY_2008_PllControlUpdate_MASK 0x1 +#define D0F0xE4_PHY_2008_Reserved_22_1_OFFSET 1 +#define D0F0xE4_PHY_2008_Reserved_22_1_WIDTH 22 +#define D0F0xE4_PHY_2008_Reserved_22_1_MASK 0x7ffffe +#define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__OFFSET 23 +#define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__WIDTH 3 +#define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__MASK 0x3800000 +#define D0F0xE4_PHY_2008_Reserved_28_26_OFFSET 26 +#define D0F0xE4_PHY_2008_Reserved_28_26_WIDTH 3 +#define D0F0xE4_PHY_2008_Reserved_28_26_MASK 0x1c000000 +#define D0F0xE4_PHY_2008_VdDetectEn_OFFSET 29 +#define D0F0xE4_PHY_2008_VdDetectEn_WIDTH 1 +#define D0F0xE4_PHY_2008_VdDetectEn_MASK 0x20000000 +#define D0F0xE4_PHY_2008_Reserved_31_30_OFFSET 30 +#define D0F0xE4_PHY_2008_Reserved_31_30_WIDTH 2 +#define D0F0xE4_PHY_2008_Reserved_31_30_MASK 0xc0000000 + +/// D0F0xE4_PHY_2008 +typedef union { + struct { ///< + UINT32 PllControlUpdate:1 ; ///< + UINT32 Reserved_22_1:22; ///< + UINT32 MeasCycCntVal_2_0_:3 ; ///< + UINT32 Reserved_28_26:3 ; ///< + UINT32 VdDetectEn:1 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_2008_STRUCT; + +// **** D0F0xE4_PHY_4001 Register Definition **** +// Address +#define D0F0xE4_PHY_4001_ADDRESS 0x4001 + +// Type +#define D0F0xE4_PHY_4001_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_4001_Reserved_14_0_OFFSET 0 +#define D0F0xE4_PHY_4001_Reserved_14_0_WIDTH 15 +#define D0F0xE4_PHY_4001_Reserved_14_0_MASK 0x7fff +#define D0F0xE4_PHY_4001_ForceDccRecalc_OFFSET 15 +#define D0F0xE4_PHY_4001_ForceDccRecalc_WIDTH 1 +#define D0F0xE4_PHY_4001_ForceDccRecalc_MASK 0x8000 +#define D0F0xE4_PHY_4001_Reserved_31_16_OFFSET 16 +#define D0F0xE4_PHY_4001_Reserved_31_16_WIDTH 16 +#define D0F0xE4_PHY_4001_Reserved_31_16_MASK 0xffff0000 + +/// D0F0xE4_PHY_4001 +typedef union { + struct { ///< + UINT32 Reserved_14_0:15; ///< + UINT32 ForceDccRecalc:1 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_4001_STRUCT; + +// **** D0F0xE4_PHY_4002 Register Definition **** +// Address +#define D0F0xE4_PHY_4002_ADDRESS 0x4002 + +// Type +#define D0F0xE4_PHY_4002_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_4002_Reserved_2_0_OFFSET 0 +#define D0F0xE4_PHY_4002_Reserved_2_0_WIDTH 3 +#define D0F0xE4_PHY_4002_Reserved_2_0_MASK 0x7 +#define D0F0xE4_PHY_4002_SamClkPiOffsetSign_OFFSET 3 +#define D0F0xE4_PHY_4002_SamClkPiOffsetSign_WIDTH 1 +#define D0F0xE4_PHY_4002_SamClkPiOffsetSign_MASK 0x8 +#define D0F0xE4_PHY_4002_SamClkPiOffset_OFFSET 4 +#define D0F0xE4_PHY_4002_SamClkPiOffset_WIDTH 3 +#define D0F0xE4_PHY_4002_SamClkPiOffset_MASK 0x70 +#define D0F0xE4_PHY_4002_SamClkPiOffsetEn_OFFSET 7 +#define D0F0xE4_PHY_4002_SamClkPiOffsetEn_WIDTH 1 +#define D0F0xE4_PHY_4002_SamClkPiOffsetEn_MASK 0x80 +#define D0F0xE4_PHY_4002_Reserved_13_8_OFFSET 8 +#define D0F0xE4_PHY_4002_Reserved_13_8_WIDTH 6 +#define D0F0xE4_PHY_4002_Reserved_13_8_MASK 0x3f00 +#define D0F0xE4_PHY_4002_LfcMin_OFFSET 14 +#define D0F0xE4_PHY_4002_LfcMin_WIDTH 8 +#define D0F0xE4_PHY_4002_LfcMin_MASK 0x3fc000 +#define D0F0xE4_PHY_4002_LfcMax_OFFSET 22 +#define D0F0xE4_PHY_4002_LfcMax_WIDTH 8 +#define D0F0xE4_PHY_4002_LfcMax_MASK 0x3fc00000 +#define D0F0xE4_PHY_4002_Reserved_31_30_OFFSET 30 +#define D0F0xE4_PHY_4002_Reserved_31_30_WIDTH 2 +#define D0F0xE4_PHY_4002_Reserved_31_30_MASK 0xc0000000 + +/// D0F0xE4_PHY_4002 +typedef union { + struct { ///< + UINT32 Reserved_2_0:3 ; ///< + UINT32 SamClkPiOffsetSign:1 ; ///< + UINT32 SamClkPiOffset:3 ; ///< + UINT32 SamClkPiOffsetEn:1 ; ///< + UINT32 Reserved_13_8:6 ; ///< + UINT32 LfcMin:8 ; ///< + UINT32 LfcMax:8 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_4002_STRUCT; + +// **** D0F0xE4_PHY_4005 Register Definition **** +// Address +#define D0F0xE4_PHY_4005_ADDRESS 0x4005 + +// Type +#define D0F0xE4_PHY_4005_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_4005_Reserved_8_0_OFFSET 0 +#define D0F0xE4_PHY_4005_Reserved_8_0_WIDTH 9 +#define D0F0xE4_PHY_4005_Reserved_8_0_MASK 0x1ff +#define D0F0xE4_PHY_4005_JitterInjHold_OFFSET 9 +#define D0F0xE4_PHY_4005_JitterInjHold_WIDTH 1 +#define D0F0xE4_PHY_4005_JitterInjHold_MASK 0x200 +#define D0F0xE4_PHY_4005_JitterInjOffCnt_OFFSET 10 +#define D0F0xE4_PHY_4005_JitterInjOffCnt_WIDTH 6 +#define D0F0xE4_PHY_4005_JitterInjOffCnt_MASK 0xfc00 +#define D0F0xE4_PHY_4005_Reserved_22_16_OFFSET 16 +#define D0F0xE4_PHY_4005_Reserved_22_16_WIDTH 7 +#define D0F0xE4_PHY_4005_Reserved_22_16_MASK 0x7f0000 +#define D0F0xE4_PHY_4005_JitterInjOnCnt_OFFSET 23 +#define D0F0xE4_PHY_4005_JitterInjOnCnt_WIDTH 6 +#define D0F0xE4_PHY_4005_JitterInjOnCnt_MASK 0x1f800000 +#define D0F0xE4_PHY_4005_JitterInjDir_OFFSET 29 +#define D0F0xE4_PHY_4005_JitterInjDir_WIDTH 1 +#define D0F0xE4_PHY_4005_JitterInjDir_MASK 0x20000000 +#define D0F0xE4_PHY_4005_JitterInjEn_OFFSET 30 +#define D0F0xE4_PHY_4005_JitterInjEn_WIDTH 1 +#define D0F0xE4_PHY_4005_JitterInjEn_MASK 0x40000000 +#define D0F0xE4_PHY_4005_Reserved_31_31_OFFSET 31 +#define D0F0xE4_PHY_4005_Reserved_31_31_WIDTH 1 +#define D0F0xE4_PHY_4005_Reserved_31_31_MASK 0x80000000 + +/// D0F0xE4_PHY_4005 +typedef union { + struct { ///< + UINT32 Reserved_8_0:9 ; ///< + UINT32 JitterInjHold:1 ; ///< + UINT32 JitterInjOffCnt:6 ; ///< + UINT32 Reserved_22_16:7 ; ///< + UINT32 JitterInjOnCnt:6 ; ///< + UINT32 JitterInjDir:1 ; ///< + UINT32 JitterInjEn:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_4005_STRUCT; + +// **** D0F0xE4_PHY_4006 Register Definition **** +// Address +#define D0F0xE4_PHY_4006_ADDRESS 0x4006 + +// Type +#define D0F0xE4_PHY_4006_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_4006_Reserved_4_0_OFFSET 0 +#define D0F0xE4_PHY_4006_Reserved_4_0_WIDTH 5 +#define D0F0xE4_PHY_4006_Reserved_4_0_MASK 0x1f +#define D0F0xE4_PHY_4006_DfeVoltage_OFFSET 5 +#define D0F0xE4_PHY_4006_DfeVoltage_WIDTH 2 +#define D0F0xE4_PHY_4006_DfeVoltage_MASK 0x60 +#define D0F0xE4_PHY_4006_DfeEn_OFFSET 7 +#define D0F0xE4_PHY_4006_DfeEn_WIDTH 1 +#define D0F0xE4_PHY_4006_DfeEn_MASK 0x80 +#define D0F0xE4_PHY_4006_Reserved_31_8_OFFSET 8 +#define D0F0xE4_PHY_4006_Reserved_31_8_WIDTH 24 +#define D0F0xE4_PHY_4006_Reserved_31_8_MASK 0xffffff00 + +/// D0F0xE4_PHY_4006 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 DfeVoltage:2 ; ///< + UINT32 DfeEn:1 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_4006_STRUCT; + +// **** D0F0xE4_PHY_400A Register Definition **** +// Address +#define D0F0xE4_PHY_400A_ADDRESS 0x400a + +// Type +#define D0F0xE4_PHY_400A_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_400A_EnCoreLoopFirst_OFFSET 0 +#define D0F0xE4_PHY_400A_EnCoreLoopFirst_WIDTH 1 +#define D0F0xE4_PHY_400A_EnCoreLoopFirst_MASK 0x1 +#define D0F0xE4_PHY_400A_Reserved_3_1_OFFSET 1 +#define D0F0xE4_PHY_400A_Reserved_3_1_WIDTH 3 +#define D0F0xE4_PHY_400A_Reserved_3_1_MASK 0xe +#define D0F0xE4_PHY_400A_LockDetOnLs2Exit_OFFSET 4 +#define D0F0xE4_PHY_400A_LockDetOnLs2Exit_WIDTH 1 +#define D0F0xE4_PHY_400A_LockDetOnLs2Exit_MASK 0x10 +#define D0F0xE4_PHY_400A_Reserved_6_5_OFFSET 5 +#define D0F0xE4_PHY_400A_Reserved_6_5_WIDTH 2 +#define D0F0xE4_PHY_400A_Reserved_6_5_MASK 0x60 +#define D0F0xE4_PHY_400A_BiasDisInLs2_OFFSET 7 +#define D0F0xE4_PHY_400A_BiasDisInLs2_WIDTH 1 +#define D0F0xE4_PHY_400A_BiasDisInLs2_MASK 0x80 +#define D0F0xE4_PHY_400A_Reserved_12_8_OFFSET 8 +#define D0F0xE4_PHY_400A_Reserved_12_8_WIDTH 5 +#define D0F0xE4_PHY_400A_Reserved_12_8_MASK 0x1f00 +#define D0F0xE4_PHY_400A_AnalogWaitTime_OFFSET 13 +#define D0F0xE4_PHY_400A_AnalogWaitTime_WIDTH 2 +#define D0F0xE4_PHY_400A_AnalogWaitTime_MASK 0x6000 +#define D0F0xE4_PHY_400A_Reserved_16_15_OFFSET 15 +#define D0F0xE4_PHY_400A_Reserved_16_15_WIDTH 2 +#define D0F0xE4_PHY_400A_Reserved_16_15_MASK 0x18000 +#define D0F0xE4_PHY_400A_DllLockFastModeEn_OFFSET 17 +#define D0F0xE4_PHY_400A_DllLockFastModeEn_WIDTH 1 +#define D0F0xE4_PHY_400A_DllLockFastModeEn_MASK 0x20000 +#define D0F0xE4_PHY_400A_Reserved_28_18_OFFSET 18 +#define D0F0xE4_PHY_400A_Reserved_28_18_WIDTH 11 +#define D0F0xE4_PHY_400A_Reserved_28_18_MASK 0x1ffc0000 +#define D0F0xE4_PHY_400A_Ls2ExitTime_OFFSET 29 +#define D0F0xE4_PHY_400A_Ls2ExitTime_WIDTH 3 +#define D0F0xE4_PHY_400A_Ls2ExitTime_MASK 0xe0000000 + +/// D0F0xE4_PHY_400A +typedef union { + struct { ///< + UINT32 EnCoreLoopFirst:1 ; ///< + UINT32 Reserved_3_1:3 ; ///< + UINT32 LockDetOnLs2Exit:1 ; ///< + UINT32 Reserved_6_5:2 ; ///< + UINT32 BiasDisInLs2:1 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 AnalogWaitTime:2 ; ///< + UINT32 Reserved_16_15:2 ; ///< + UINT32 DllLockFastModeEn:1 ; ///< + UINT32 Reserved_28_18:11; ///< + UINT32 Ls2ExitTime:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_400A_STRUCT; + +// **** D0F0xE4_PHY_4010 Register Definition **** +// Address +#define D0F0xE4_PHY_4010_ADDRESS 0x4010 + +// Type +#define D0F0xE4_PHY_4010_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_4010_PhyFuseValid_OFFSET 0 +#define D0F0xE4_PHY_4010_PhyFuseValid_WIDTH 1 +#define D0F0xE4_PHY_4010_PhyFuseValid_MASK 0x1 +#define D0F0xE4_PHY_4010_FuseFuncDllRCFilterOverride_OFFSET 1 +#define D0F0xE4_PHY_4010_FuseFuncDllRCFilterOverride_WIDTH 1 +#define D0F0xE4_PHY_4010_FuseFuncDllRCFilterOverride_MASK 0x2 +#define D0F0xE4_PHY_4010_Reserved_2_2_OFFSET 2 +#define D0F0xE4_PHY_4010_Reserved_2_2_WIDTH 1 +#define D0F0xE4_PHY_4010_Reserved_2_2_MASK 0x4 +#define D0F0xE4_PHY_4010_FuseFuncDllFastLockStepSize_OFFSET 3 +#define D0F0xE4_PHY_4010_FuseFuncDllFastLockStepSize_WIDTH 1 +#define D0F0xE4_PHY_4010_FuseFuncDllFastLockStepSize_MASK 0x8 +#define D0F0xE4_PHY_4010_Reserved_4_4_OFFSET 4 +#define D0F0xE4_PHY_4010_Reserved_4_4_WIDTH 1 +#define D0F0xE4_PHY_4010_Reserved_4_4_MASK 0x10 +#define D0F0xE4_PHY_4010_FuseFuncDllMidLockStepSize_OFFSET 5 +#define D0F0xE4_PHY_4010_FuseFuncDllMidLockStepSize_WIDTH 1 +#define D0F0xE4_PHY_4010_FuseFuncDllMidLockStepSize_MASK 0x20 +#define D0F0xE4_PHY_4010_Reserved_6_6_OFFSET 6 +#define D0F0xE4_PHY_4010_Reserved_6_6_WIDTH 1 +#define D0F0xE4_PHY_4010_Reserved_6_6_MASK 0x40 +#define D0F0xE4_PHY_4010_FuseFuncDllFastLockStop_OFFSET 7 +#define D0F0xE4_PHY_4010_FuseFuncDllFastLockStop_WIDTH 4 +#define D0F0xE4_PHY_4010_FuseFuncDllFastLockStop_MASK 0x780 +#define D0F0xE4_PHY_4010_Reserved_12_11_OFFSET 11 +#define D0F0xE4_PHY_4010_Reserved_12_11_WIDTH 2 +#define D0F0xE4_PHY_4010_Reserved_12_11_MASK 0x1800 +#define D0F0xE4_PHY_4010_FuseFuncDllInputDccDis_OFFSET 13 +#define D0F0xE4_PHY_4010_FuseFuncDllInputDccDis_WIDTH 1 +#define D0F0xE4_PHY_4010_FuseFuncDllInputDccDis_MASK 0x2000 +#define D0F0xE4_PHY_4010_Reserved_14_14_OFFSET 14 +#define D0F0xE4_PHY_4010_Reserved_14_14_WIDTH 1 +#define D0F0xE4_PHY_4010_Reserved_14_14_MASK 0x4000 +#define D0F0xE4_PHY_4010_FuseFuncDllProcessCompCtl_OFFSET 15 +#define D0F0xE4_PHY_4010_FuseFuncDllProcessCompCtl_WIDTH 2 +#define D0F0xE4_PHY_4010_FuseFuncDllProcessCompCtl_MASK 0x18000 +#define D0F0xE4_PHY_4010_Reserved_19_17_OFFSET 17 +#define D0F0xE4_PHY_4010_Reserved_19_17_WIDTH 3 +#define D0F0xE4_PHY_4010_Reserved_19_17_MASK 0xe0000 +#define D0F0xE4_PHY_4010_FuseFuncDllRdacSupSel_OFFSET 20 +#define D0F0xE4_PHY_4010_FuseFuncDllRdacSupSel_WIDTH 1 +#define D0F0xE4_PHY_4010_FuseFuncDllRdacSupSel_MASK 0x100000 +#define D0F0xE4_PHY_4010_FuseFuncRxSpare_OFFSET 21 +#define D0F0xE4_PHY_4010_FuseFuncRxSpare_WIDTH 1 +#define D0F0xE4_PHY_4010_FuseFuncRxSpare_MASK 0x200000 +#define D0F0xE4_PHY_4010_Reserved_31_22_OFFSET 22 +#define D0F0xE4_PHY_4010_Reserved_31_22_WIDTH 10 +#define D0F0xE4_PHY_4010_Reserved_31_22_MASK 0xffc00000 + +/// D0F0xE4_PHY_4010 +typedef union { + struct { ///< + UINT32 PhyFuseValid:1 ; ///< + UINT32 FuseFuncDllRCFilterOverride:1 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 FuseFuncDllFastLockStepSize:1 ; ///< + UINT32 Reserved_4_4:1 ; ///< + UINT32 FuseFuncDllMidLockStepSize:1 ; ///< + UINT32 Reserved_6_6:1 ; ///< + UINT32 FuseFuncDllFastLockStop:4 ; ///< + UINT32 Reserved_12_11:2 ; ///< + UINT32 FuseFuncDllInputDccDis:1 ; ///< + UINT32 Reserved_14_14:1 ; ///< + UINT32 FuseFuncDllProcessCompCtl:2 ; ///< + UINT32 Reserved_19_17:3 ; ///< + UINT32 FuseFuncDllRdacSupSel:1 ; ///< + UINT32 FuseFuncRxSpare:1 ; ///< + UINT32 Reserved_31_22:10; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_4010_STRUCT; + +// **** D0F0xE4_PHY_4011 Register Definition **** +// Address +#define D0F0xE4_PHY_4011_ADDRESS 0x4011 + +// Type +#define D0F0xE4_PHY_4011_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_4011_PhyFuseValid_OFFSET 0 +#define D0F0xE4_PHY_4011_PhyFuseValid_WIDTH 1 +#define D0F0xE4_PHY_4011_PhyFuseValid_MASK 0x1 +#define D0F0xE4_PHY_4011_FuseProcDllVrefAdj_OFFSET 1 +#define D0F0xE4_PHY_4011_FuseProcDllVrefAdj_WIDTH 3 +#define D0F0xE4_PHY_4011_FuseProcDllVrefAdj_MASK 0xe +#define D0F0xE4_PHY_4011_Reserved_5_4_OFFSET 4 +#define D0F0xE4_PHY_4011_Reserved_5_4_WIDTH 2 +#define D0F0xE4_PHY_4011_Reserved_5_4_MASK 0x30 +#define D0F0xE4_PHY_4011_FuseProcDllIrefAdj_OFFSET 6 +#define D0F0xE4_PHY_4011_FuseProcDllIrefAdj_WIDTH 3 +#define D0F0xE4_PHY_4011_FuseProcDllIrefAdj_MASK 0x1c0 +#define D0F0xE4_PHY_4011_Reserved_10_9_OFFSET 9 +#define D0F0xE4_PHY_4011_Reserved_10_9_WIDTH 2 +#define D0F0xE4_PHY_4011_Reserved_10_9_MASK 0x600 +#define D0F0xE4_PHY_4011_FuseProcDllProcessComp_OFFSET 11 +#define D0F0xE4_PHY_4011_FuseProcDllProcessComp_WIDTH 3 +#define D0F0xE4_PHY_4011_FuseProcDllProcessComp_MASK 0x3800 +#define D0F0xE4_PHY_4011_Reserved_15_14_OFFSET 14 +#define D0F0xE4_PHY_4011_Reserved_15_14_WIDTH 2 +#define D0F0xE4_PHY_4011_Reserved_15_14_MASK 0xc000 +#define D0F0xE4_PHY_4011_FuseProcDllRCFilterCtl_OFFSET 16 +#define D0F0xE4_PHY_4011_FuseProcDllRCFilterCtl_WIDTH 1 +#define D0F0xE4_PHY_4011_FuseProcDllRCFilterCtl_MASK 0x10000 +#define D0F0xE4_PHY_4011_Reserved_18_17_OFFSET 17 +#define D0F0xE4_PHY_4011_Reserved_18_17_WIDTH 2 +#define D0F0xE4_PHY_4011_Reserved_18_17_MASK 0x60000 +#define D0F0xE4_PHY_4011_FuseProcEiDetThresh_OFFSET 19 +#define D0F0xE4_PHY_4011_FuseProcEiDetThresh_WIDTH 2 +#define D0F0xE4_PHY_4011_FuseProcEiDetThresh_MASK 0x180000 +#define D0F0xE4_PHY_4011_Reserved_22_21_OFFSET 21 +#define D0F0xE4_PHY_4011_Reserved_22_21_WIDTH 2 +#define D0F0xE4_PHY_4011_Reserved_22_21_MASK 0x600000 +#define D0F0xE4_PHY_4011_FuseProcRxSpare_OFFSET 23 +#define D0F0xE4_PHY_4011_FuseProcRxSpare_WIDTH 1 +#define D0F0xE4_PHY_4011_FuseProcRxSpare_MASK 0x800000 +#define D0F0xE4_PHY_4011_Reserved_31_24_OFFSET 24 +#define D0F0xE4_PHY_4011_Reserved_31_24_WIDTH 8 +#define D0F0xE4_PHY_4011_Reserved_31_24_MASK 0xff000000 + +/// D0F0xE4_PHY_4011 +typedef union { + struct { ///< + UINT32 PhyFuseValid:1 ; ///< + UINT32 FuseProcDllVrefAdj:3 ; ///< + UINT32 Reserved_5_4:2 ; ///< + UINT32 FuseProcDllIrefAdj:3 ; ///< + UINT32 Reserved_10_9:2 ; ///< + UINT32 FuseProcDllProcessComp:3 ; ///< + UINT32 Reserved_15_14:1 ; ///< + UINT32 FuseProcDllRCFilterCtl:1 ; ///< + UINT32 Reserved_18_17:2 ; ///< + UINT32 FuseProcEiDetThresh:2 ; ///< + UINT32 Reserved_22_21:2 ; ///< + UINT32 FuseProcRxSpare:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_4011_STRUCT; + +// **** D0F0xE4_PHY_500F Register Definition **** +// Address +#define D0F0xE4_PHY_500F_ADDRESS 0x500F + +// Type +#define D0F0xE4_PHY_500F_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_500F_DllProcessFreqCtlIndex1_OFFSET 0 +#define D0F0xE4_PHY_500F_DllProcessFreqCtlIndex1_WIDTH 4 +#define D0F0xE4_PHY_500F_DllProcessFreqCtlIndex1_MASK 0xf +#define D0F0xE4_PHY_500F_Reserved_6_4_OFFSET 4 +#define D0F0xE4_PHY_500F_Reserved_6_4_WIDTH 3 +#define D0F0xE4_PHY_500F_Reserved_6_4_MASK 0x70 +#define D0F0xE4_PHY_500F_DllProcessFreqCtlIndex2_OFFSET 7 +#define D0F0xE4_PHY_500F_DllProcessFreqCtlIndex2_WIDTH 4 +#define D0F0xE4_PHY_500F_DllProcessFreqCtlIndex2_MASK 0x780 +#define D0F0xE4_PHY_500F_Reserved_11_11_OFFSET 11 +#define D0F0xE4_PHY_500F_Reserved_11_11_WIDTH 1 +#define D0F0xE4_PHY_500F_Reserved_11_11_MASK 0x800 +#define D0F0xE4_PHY_500F_DllProcessFreqCtlOverride_OFFSET 12 +#define D0F0xE4_PHY_500F_DllProcessFreqCtlOverride_WIDTH 1 +#define D0F0xE4_PHY_500F_DllProcessFreqCtlOverride_MASK 0x1000 +#define D0F0xE4_PHY_500F_Reserved_13_13_OFFSET 13 +#define D0F0xE4_PHY_500F_Reserved_13_13_WIDTH 1 +#define D0F0xE4_PHY_500F_Reserved_13_13_MASK 0x2000 + +/// D0F0xE4_PHY_500F +typedef union { + struct { ///< + UINT32 DllProcessFreqCtlIndex1:4 ; ///< + UINT32 Reserved_6_4:3 ; ///< + UINT32 DllProcessFreqCtlIndex2:4 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 DllProcessFreqCtlOverride:1 ; ///< + UINT32 Reserved_13_13:1 ; ///< + UINT32 :4 ; ///< + UINT32 :2 ; ///< + UINT32 :1 ; ///< + UINT32 :2 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + UINT32 :2 ; ///< + UINT32 :1 ; ///< + UINT32 :1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_500F_STRUCT; + +// **** D0F0xE4_PHY_6005 Register Definition **** +// Address +#define D0F0xE4_PHY_6005_ADDRESS 0x6005 + +// Type +#define D0F0xE4_PHY_6005_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_6005_Reserved_28_0_OFFSET 0 +#define D0F0xE4_PHY_6005_Reserved_28_0_WIDTH 29 +#define D0F0xE4_PHY_6005_Reserved_28_0_MASK 0x1fffffff +#define D0F0xE4_PHY_6005_IsOwnMstr_OFFSET 29 +#define D0F0xE4_PHY_6005_IsOwnMstr_WIDTH 1 +#define D0F0xE4_PHY_6005_IsOwnMstr_MASK 0x20000000 +#define D0F0xE4_PHY_6005_Reserved_30_30_OFFSET 30 +#define D0F0xE4_PHY_6005_Reserved_30_30_WIDTH 1 +#define D0F0xE4_PHY_6005_Reserved_30_30_MASK 0x40000000 +#define D0F0xE4_PHY_6005_GangedModeEn_OFFSET 31 +#define D0F0xE4_PHY_6005_GangedModeEn_WIDTH 1 +#define D0F0xE4_PHY_6005_GangedModeEn_MASK 0x80000000 + +/// D0F0xE4_PHY_6005 +typedef union { + struct { ///< + UINT32 Reserved_28_0:29; ///< + UINT32 IsOwnMstr:1 ; ///< + UINT32 Reserved_30_30:1 ; ///< + UINT32 GangedModeEn:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_6005_STRUCT; + +// **** D0F0xE4_PHY_6006 Register Definition **** +// Address +#define D0F0xE4_PHY_6006_ADDRESS 0x6006 + +// Type +#define D0F0xE4_PHY_6006_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_6006_TxMarginNom_OFFSET 0 +#define D0F0xE4_PHY_6006_TxMarginNom_WIDTH 8 +#define D0F0xE4_PHY_6006_TxMarginNom_MASK 0xff +#define D0F0xE4_PHY_6006_DeemphGen1Nom_OFFSET 8 +#define D0F0xE4_PHY_6006_DeemphGen1Nom_WIDTH 8 +#define D0F0xE4_PHY_6006_DeemphGen1Nom_MASK 0xff00 +#define D0F0xE4_PHY_6006_Reserved_31_16_OFFSET 16 +#define D0F0xE4_PHY_6006_Reserved_31_16_WIDTH 16 +#define D0F0xE4_PHY_6006_Reserved_31_16_MASK 0xffff0000 + +/// D0F0xE4_PHY_6006 +typedef union { + struct { ///< + UINT32 TxMarginNom:8 ; ///< + UINT32 DeemphGen1Nom:8 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_PHY_6006_STRUCT; + +// **** D0F2xF4_x00 Register Definition **** +// Address +#define D0F2xF4_x00_ADDRESS 0x0 + +// Type +#define D0F2xF4_x00_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x00_L2PerfEvent0_OFFSET 0 +#define D0F2xF4_x00_L2PerfEvent0_WIDTH 8 +#define D0F2xF4_x00_L2PerfEvent0_MASK 0xff +#define D0F2xF4_x00_L2PerfEvent1_OFFSET 8 +#define D0F2xF4_x00_L2PerfEvent1_WIDTH 8 +#define D0F2xF4_x00_L2PerfEvent1_MASK 0xff00 +#define D0F2xF4_x00_L2PerfCountUpper0_OFFSET 16 +#define D0F2xF4_x00_L2PerfCountUpper0_WIDTH 8 +#define D0F2xF4_x00_L2PerfCountUpper0_MASK 0xff0000 +#define D0F2xF4_x00_L2PerfCountUpper1_OFFSET 24 +#define D0F2xF4_x00_L2PerfCountUpper1_WIDTH 8 +#define D0F2xF4_x00_L2PerfCountUpper1_MASK 0xff000000 + +/// D0F2xF4_x00 +typedef union { + struct { ///< + UINT32 L2PerfEvent0:8 ; ///< + UINT32 L2PerfEvent1:8 ; ///< + UINT32 L2PerfCountUpper0:8 ; ///< + UINT32 L2PerfCountUpper1:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x00_STRUCT; + +// **** D0F2xF4_x01 Register Definition **** +// Address +#define D0F2xF4_x01_ADDRESS 0x1 + +// Type +#define D0F2xF4_x01_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x01_L2PerfCount0_OFFSET 0 +#define D0F2xF4_x01_L2PerfCount0_WIDTH 32 +#define D0F2xF4_x01_L2PerfCount0_MASK 0xffffffff + +/// D0F2xF4_x01 +typedef union { + struct { ///< + UINT32 L2PerfCount0:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x01_STRUCT; + +// **** D0F2xF4_x02 Register Definition **** +// Address +#define D0F2xF4_x02_ADDRESS 0x2 + +// Type +#define D0F2xF4_x02_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x02_L2PerfCount1_OFFSET 0 +#define D0F2xF4_x02_L2PerfCount1_WIDTH 32 +#define D0F2xF4_x02_L2PerfCount1_MASK 0xffffffff + +/// D0F2xF4_x02 +typedef union { + struct { ///< + UINT32 L2PerfCount1:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x02_STRUCT; + +// **** D0F2xF4_x03 Register Definition **** +// Address +#define D0F2xF4_x03_ADDRESS 0x3 + +// Type +#define D0F2xF4_x03_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x03_L2PerfEvent2_OFFSET 0 +#define D0F2xF4_x03_L2PerfEvent2_WIDTH 8 +#define D0F2xF4_x03_L2PerfEvent2_MASK 0xff +#define D0F2xF4_x03_L2PerfEvent3_OFFSET 8 +#define D0F2xF4_x03_L2PerfEvent3_WIDTH 8 +#define D0F2xF4_x03_L2PerfEvent3_MASK 0xff00 +#define D0F2xF4_x03_L2PerfCountUpper2_OFFSET 16 +#define D0F2xF4_x03_L2PerfCountUpper2_WIDTH 8 +#define D0F2xF4_x03_L2PerfCountUpper2_MASK 0xff0000 +#define D0F2xF4_x03_L2PerfCountUpper3_OFFSET 24 +#define D0F2xF4_x03_L2PerfCountUpper3_WIDTH 8 +#define D0F2xF4_x03_L2PerfCountUpper3_MASK 0xff000000 + +/// D0F2xF4_x03 +typedef union { + struct { ///< + UINT32 L2PerfEvent2:8 ; ///< + UINT32 L2PerfEvent3:8 ; ///< + UINT32 L2PerfCountUpper2:8 ; ///< + UINT32 L2PerfCountUpper3:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x03_STRUCT; + +// **** D0F2xF4_x04 Register Definition **** +// Address +#define D0F2xF4_x04_ADDRESS 0x4 + +// Type +#define D0F2xF4_x04_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x04_L2PerfCount2_OFFSET 0 +#define D0F2xF4_x04_L2PerfCount2_WIDTH 32 +#define D0F2xF4_x04_L2PerfCount2_MASK 0xffffffff + +/// D0F2xF4_x04 +typedef union { + struct { ///< + UINT32 L2PerfCount2:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x04_STRUCT; + +// **** D0F2xF4_x05 Register Definition **** +// Address +#define D0F2xF4_x05_ADDRESS 0x5 + +// Type +#define D0F2xF4_x05_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x05_L2PerfCount3_OFFSET 0 +#define D0F2xF4_x05_L2PerfCount3_WIDTH 32 +#define D0F2xF4_x05_L2PerfCount3_MASK 0xffffffff + +/// D0F2xF4_x05 +typedef union { + struct { ///< + UINT32 L2PerfCount3:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x05_STRUCT; + +// **** D0F2xF4_x06 Register Definition **** +// Address +#define D0F2xF4_x06_ADDRESS 0x6 + +// Type +#define D0F2xF4_x06_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x06_L2DEBUG0_OFFSET 0 +#define D0F2xF4_x06_L2DEBUG0_WIDTH 32 +#define D0F2xF4_x06_L2DEBUG0_MASK 0xffffffff + +/// D0F2xF4_x06 +typedef union { + struct { ///< + UINT32 L2DEBUG0:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x06_STRUCT; + +// **** D0F2xF4_x07 Register Definition **** +// Address +#define D0F2xF4_x07_ADDRESS 0x7 + +// Type +#define D0F2xF4_x07_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x07_L2DEBUG1_OFFSET 0 +#define D0F2xF4_x07_L2DEBUG1_WIDTH 32 +#define D0F2xF4_x07_L2DEBUG1_MASK 0xffffffff + +/// D0F2xF4_x07 +typedef union { + struct { ///< + UINT32 L2DEBUG1:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x07_STRUCT; + +// **** D0F2xF4_x08 Register Definition **** +// Address +#define D0F2xF4_x08_ADDRESS 0x8 + +// Type +#define D0F2xF4_x08_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x08_L2STATUS0_OFFSET 0 +#define D0F2xF4_x08_L2STATUS0_WIDTH 32 +#define D0F2xF4_x08_L2STATUS0_MASK 0xffffffff + +/// D0F2xF4_x08 +typedef union { + struct { ///< + UINT32 L2STATUS0:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x08_STRUCT; + +// **** D0F2xF4_x0C Register Definition **** +// Address +#define D0F2xF4_x0C_ADDRESS 0xc + +// Type +#define D0F2xF4_x0C_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x0C_PTCAddrTransReqCheck_OFFSET 0 +#define D0F2xF4_x0C_PTCAddrTransReqCheck_WIDTH 1 +#define D0F2xF4_x0C_PTCAddrTransReqCheck_MASK 0x1 +#define D0F2xF4_x0C_AllowL1CacheVZero_OFFSET 1 +#define D0F2xF4_x0C_AllowL1CacheVZero_WIDTH 1 +#define D0F2xF4_x0C_AllowL1CacheVZero_MASK 0x2 +#define D0F2xF4_x0C_AllowL1CacheATSRsp_OFFSET 2 +#define D0F2xF4_x0C_AllowL1CacheATSRsp_WIDTH 1 +#define D0F2xF4_x0C_AllowL1CacheATSRsp_MASK 0x4 +#define D0F2xF4_x0C_DTCHitVZeroOrIVZero_OFFSET 3 +#define D0F2xF4_x0C_DTCHitVZeroOrIVZero_WIDTH 1 +#define D0F2xF4_x0C_DTCHitVZeroOrIVZero_MASK 0x8 +#define D0F2xF4_x0C_IFifoTWCredits_OFFSET 4 +#define D0F2xF4_x0C_IFifoTWCredits_WIDTH 6 +#define D0F2xF4_x0C_IFifoTWCredits_MASK 0x3f0 +#define D0F2xF4_x0C_SIDEPTEOnUntransExcl_OFFSET 10 +#define D0F2xF4_x0C_SIDEPTEOnUntransExcl_WIDTH 1 +#define D0F2xF4_x0C_SIDEPTEOnUntransExcl_MASK 0x400 +#define D0F2xF4_x0C_SIDEPTEOnAddrTransExcl_OFFSET 11 +#define D0F2xF4_x0C_SIDEPTEOnAddrTransExcl_WIDTH 1 +#define D0F2xF4_x0C_SIDEPTEOnAddrTransExcl_MASK 0x800 +#define D0F2xF4_x0C_IFifoCMBCredits_OFFSET 12 +#define D0F2xF4_x0C_IFifoCMBCredits_WIDTH 6 +#define D0F2xF4_x0C_IFifoCMBCredits_MASK 0x3f000 +#define D0F2xF4_x0C_FLTCMBPriority_OFFSET 18 +#define D0F2xF4_x0C_FLTCMBPriority_WIDTH 1 +#define D0F2xF4_x0C_FLTCMBPriority_MASK 0x40000 +#define D0F2xF4_x0C_Reserved_19_19_OFFSET 19 +#define D0F2xF4_x0C_Reserved_19_19_WIDTH 1 +#define D0F2xF4_x0C_Reserved_19_19_MASK 0x80000 +#define D0F2xF4_x0C_IFifoBurstLength_OFFSET 20 +#define D0F2xF4_x0C_IFifoBurstLength_WIDTH 4 +#define D0F2xF4_x0C_IFifoBurstLength_MASK 0xf00000 +#define D0F2xF4_x0C_IFifoClientPriority_OFFSET 24 +#define D0F2xF4_x0C_IFifoClientPriority_WIDTH 8 +#define D0F2xF4_x0C_IFifoClientPriority_MASK 0xff000000 + +/// D0F2xF4_x0C +typedef union { + struct { ///< + UINT32 PTCAddrTransReqCheck:1 ; ///< + UINT32 AllowL1CacheVZero:1 ; ///< + UINT32 AllowL1CacheATSRsp:1 ; ///< + UINT32 DTCHitVZeroOrIVZero:1 ; ///< + UINT32 IFifoTWCredits:6 ; ///< + UINT32 SIDEPTEOnUntransExcl:1 ; ///< + UINT32 SIDEPTEOnAddrTransExcl:1 ; ///< + UINT32 IFifoCMBCredits:6 ; ///< + UINT32 FLTCMBPriority:1 ; ///< + UINT32 Reserved_19_19:1 ; ///< + UINT32 IFifoBurstLength:4 ; ///< + UINT32 IFifoClientPriority:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x0C_STRUCT; + +// **** D0F2xF4_x0D Register Definition **** +// Address +#define D0F2xF4_x0D_ADDRESS 0xd + +// Type +#define D0F2xF4_x0D_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x0D_SeqInvBurstLimitInv_OFFSET 0 +#define D0F2xF4_x0D_SeqInvBurstLimitInv_WIDTH 8 +#define D0F2xF4_x0D_SeqInvBurstLimitInv_MASK 0xff +#define D0F2xF4_x0D_SeqInvBurstLimitL2Req_OFFSET 8 +#define D0F2xF4_x0D_SeqInvBurstLimitL2Req_WIDTH 8 +#define D0F2xF4_x0D_SeqInvBurstLimitL2Req_MASK 0xff00 +#define D0F2xF4_x0D_SeqInvBurstLimitEn_OFFSET 16 +#define D0F2xF4_x0D_SeqInvBurstLimitEn_WIDTH 1 +#define D0F2xF4_x0D_SeqInvBurstLimitEn_MASK 0x10000 +#define D0F2xF4_x0D_Reserved_23_17_OFFSET 17 +#define D0F2xF4_x0D_Reserved_23_17_WIDTH 7 +#define D0F2xF4_x0D_Reserved_23_17_MASK 0xfe0000 +#define D0F2xF4_x0D_PerfThreshold_OFFSET 24 +#define D0F2xF4_x0D_PerfThreshold_WIDTH 8 +#define D0F2xF4_x0D_PerfThreshold_MASK 0xff000000 + +/// D0F2xF4_x0D +typedef union { + struct { ///< + UINT32 SeqInvBurstLimitInv:8 ; ///< + UINT32 SeqInvBurstLimitL2Req:8 ; ///< + UINT32 SeqInvBurstLimitEn:1 ; ///< + UINT32 Reserved_23_17:7 ; ///< + UINT32 PerfThreshold:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x0D_STRUCT; + +// **** D0F2xF4_x10 Register Definition **** +// Address +#define D0F2xF4_x10_ADDRESS 0x10 + +// Type +#define D0F2xF4_x10_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x10_DTCReplacementSel_OFFSET 0 +#define D0F2xF4_x10_DTCReplacementSel_WIDTH 2 +#define D0F2xF4_x10_DTCReplacementSel_MASK 0x3 +#define D0F2xF4_x10_Reserved_2_2_OFFSET 2 +#define D0F2xF4_x10_Reserved_2_2_WIDTH 1 +#define D0F2xF4_x10_Reserved_2_2_MASK 0x4 +#define D0F2xF4_x10_DTCLRUUpdatePri_OFFSET 3 +#define D0F2xF4_x10_DTCLRUUpdatePri_WIDTH 1 +#define D0F2xF4_x10_DTCLRUUpdatePri_MASK 0x8 +#define D0F2xF4_x10_DTCParityEn_OFFSET 4 +#define D0F2xF4_x10_DTCParityEn_WIDTH 1 +#define D0F2xF4_x10_DTCParityEn_MASK 0x10 +#define D0F2xF4_x10_Reserved_7_5_OFFSET 5 +#define D0F2xF4_x10_Reserved_7_5_WIDTH 3 +#define D0F2xF4_x10_Reserved_7_5_MASK 0xe0 +#define D0F2xF4_x10_DTCInvalidationSel_OFFSET 8 +#define D0F2xF4_x10_DTCInvalidationSel_WIDTH 2 +#define D0F2xF4_x10_DTCInvalidationSel_MASK 0x300 +#define D0F2xF4_x10_DTCSoftInvalidate_OFFSET 10 +#define D0F2xF4_x10_DTCSoftInvalidate_WIDTH 1 +#define D0F2xF4_x10_DTCSoftInvalidate_MASK 0x400 +#define D0F2xF4_x10_Reserved_12_11_OFFSET 11 +#define D0F2xF4_x10_Reserved_12_11_WIDTH 2 +#define D0F2xF4_x10_Reserved_12_11_MASK 0x1800 +#define D0F2xF4_x10_DTCBypass_OFFSET 13 +#define D0F2xF4_x10_DTCBypass_WIDTH 1 +#define D0F2xF4_x10_DTCBypass_MASK 0x2000 +#define D0F2xF4_x10_Reserved_14_14_OFFSET 14 +#define D0F2xF4_x10_Reserved_14_14_WIDTH 1 +#define D0F2xF4_x10_Reserved_14_14_MASK 0x4000 +#define D0F2xF4_x10_DTCParitySupport_OFFSET 15 +#define D0F2xF4_x10_DTCParitySupport_WIDTH 1 +#define D0F2xF4_x10_DTCParitySupport_MASK 0x8000 +#define D0F2xF4_x10_DTCWays_OFFSET 16 +#define D0F2xF4_x10_DTCWays_WIDTH 8 +#define D0F2xF4_x10_DTCWays_MASK 0xff0000 +#define D0F2xF4_x10_Reserved_27_24_OFFSET 24 +#define D0F2xF4_x10_Reserved_27_24_WIDTH 4 +#define D0F2xF4_x10_Reserved_27_24_MASK 0xf000000 +#define D0F2xF4_x10_DTCEntries_OFFSET 28 +#define D0F2xF4_x10_DTCEntries_WIDTH 4 +#define D0F2xF4_x10_DTCEntries_MASK 0xf0000000 + +/// D0F2xF4_x10 +typedef union { + struct { ///< + UINT32 DTCReplacementSel:2 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 DTCLRUUpdatePri:1 ; ///< + UINT32 DTCParityEn:1 ; ///< + UINT32 Reserved_7_5:3 ; ///< + UINT32 DTCInvalidationSel:2 ; ///< + UINT32 DTCSoftInvalidate:1 ; ///< + UINT32 Reserved_12_11:2 ; ///< + UINT32 DTCBypass:1 ; ///< + UINT32 Reserved_14_14:1 ; ///< + UINT32 DTCParitySupport:1 ; ///< + UINT32 DTCWays:8 ; ///< + UINT32 Reserved_27_24:4 ; ///< + UINT32 DTCEntries:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x10_STRUCT; + +// **** D0F2xF4_x11 Register Definition **** +// Address +#define D0F2xF4_x11_ADDRESS 0x11 + +// Type +#define D0F2xF4_x11_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x11_DTCFuncBits_OFFSET 0 +#define D0F2xF4_x11_DTCFuncBits_WIDTH 2 +#define D0F2xF4_x11_DTCFuncBits_MASK 0x3 +#define D0F2xF4_x11_DTCDevBits_OFFSET 2 +#define D0F2xF4_x11_DTCDevBits_WIDTH 3 +#define D0F2xF4_x11_DTCDevBits_MASK 0x1c +#define D0F2xF4_x11_DTCBusBits_OFFSET 5 +#define D0F2xF4_x11_DTCBusBits_WIDTH 4 +#define D0F2xF4_x11_DTCBusBits_MASK 0x1e0 +#define D0F2xF4_x11_Reserved_9_9_OFFSET 9 +#define D0F2xF4_x11_Reserved_9_9_WIDTH 1 +#define D0F2xF4_x11_Reserved_9_9_MASK 0x200 +#define D0F2xF4_x11_DtcAltHashEn_OFFSET 10 +#define D0F2xF4_x11_DtcAltHashEn_WIDTH 1 +#define D0F2xF4_x11_DtcAltHashEn_MASK 0x400 +#define D0F2xF4_x11_Reserved_15_11_OFFSET 11 +#define D0F2xF4_x11_Reserved_15_11_WIDTH 5 +#define D0F2xF4_x11_Reserved_15_11_MASK 0xf800 +#define D0F2xF4_x11_DtcAddressMask_OFFSET 16 +#define D0F2xF4_x11_DtcAddressMask_WIDTH 16 +#define D0F2xF4_x11_DtcAddressMask_MASK 0xffff0000 + +/// D0F2xF4_x11 +typedef union { + struct { ///< + UINT32 DTCFuncBits:2 ; ///< + UINT32 DTCDevBits:3 ; ///< + UINT32 DTCBusBits:4 ; ///< + UINT32 Reserved_9_9:1 ; ///< + UINT32 DtcAltHashEn:1 ; ///< + UINT32 Reserved_15_11:5 ; ///< + UINT32 DtcAddressMask:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x11_STRUCT; + +// **** D0F2xF4_x12 Register Definition **** +// Address +#define D0F2xF4_x12_ADDRESS 0x12 + +// Type +#define D0F2xF4_x12_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x12_DTCWayDisable_OFFSET 0 +#define D0F2xF4_x12_DTCWayDisable_WIDTH 16 +#define D0F2xF4_x12_DTCWayDisable_MASK 0xffff +#define D0F2xF4_x12_DTCWayAccessDisable_OFFSET 16 +#define D0F2xF4_x12_DTCWayAccessDisable_WIDTH 16 +#define D0F2xF4_x12_DTCWayAccessDisable_MASK 0xffff0000 + +/// D0F2xF4_x12 +typedef union { + struct { ///< + UINT32 DTCWayDisable:16; ///< + UINT32 DTCWayAccessDisable:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x12_STRUCT; + +// **** D0F2xF4_x14 Register Definition **** +// Address +#define D0F2xF4_x14_ADDRESS 0x14 + +// Type +#define D0F2xF4_x14_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x14_ITCReplacementSel_OFFSET 0 +#define D0F2xF4_x14_ITCReplacementSel_WIDTH 2 +#define D0F2xF4_x14_ITCReplacementSel_MASK 0x3 +#define D0F2xF4_x14_Reserved_2_2_OFFSET 2 +#define D0F2xF4_x14_Reserved_2_2_WIDTH 1 +#define D0F2xF4_x14_Reserved_2_2_MASK 0x4 +#define D0F2xF4_x14_ITCLRUUpdatePri_OFFSET 3 +#define D0F2xF4_x14_ITCLRUUpdatePri_WIDTH 1 +#define D0F2xF4_x14_ITCLRUUpdatePri_MASK 0x8 +#define D0F2xF4_x14_ITCParityEn_OFFSET 4 +#define D0F2xF4_x14_ITCParityEn_WIDTH 1 +#define D0F2xF4_x14_ITCParityEn_MASK 0x10 +#define D0F2xF4_x14_Reserved_7_5_OFFSET 5 +#define D0F2xF4_x14_Reserved_7_5_WIDTH 3 +#define D0F2xF4_x14_Reserved_7_5_MASK 0xe0 +#define D0F2xF4_x14_ITCInvalidationSel_OFFSET 8 +#define D0F2xF4_x14_ITCInvalidationSel_WIDTH 2 +#define D0F2xF4_x14_ITCInvalidationSel_MASK 0x300 +#define D0F2xF4_x14_ITCSoftInvalidate_OFFSET 10 +#define D0F2xF4_x14_ITCSoftInvalidate_WIDTH 1 +#define D0F2xF4_x14_ITCSoftInvalidate_MASK 0x400 +#define D0F2xF4_x14_Reserved_12_11_OFFSET 11 +#define D0F2xF4_x14_Reserved_12_11_WIDTH 2 +#define D0F2xF4_x14_Reserved_12_11_MASK 0x1800 +#define D0F2xF4_x14_ITCBypass_OFFSET 13 +#define D0F2xF4_x14_ITCBypass_WIDTH 1 +#define D0F2xF4_x14_ITCBypass_MASK 0x2000 +#define D0F2xF4_x14_Reserved_14_14_OFFSET 14 +#define D0F2xF4_x14_Reserved_14_14_WIDTH 1 +#define D0F2xF4_x14_Reserved_14_14_MASK 0x4000 +#define D0F2xF4_x14_ITCParitySupport_OFFSET 15 +#define D0F2xF4_x14_ITCParitySupport_WIDTH 1 +#define D0F2xF4_x14_ITCParitySupport_MASK 0x8000 +#define D0F2xF4_x14_ITCWays_OFFSET 16 +#define D0F2xF4_x14_ITCWays_WIDTH 8 +#define D0F2xF4_x14_ITCWays_MASK 0xff0000 +#define D0F2xF4_x14_Reserved_27_24_OFFSET 24 +#define D0F2xF4_x14_Reserved_27_24_WIDTH 4 +#define D0F2xF4_x14_Reserved_27_24_MASK 0xf000000 +#define D0F2xF4_x14_ITCEntries_OFFSET 28 +#define D0F2xF4_x14_ITCEntries_WIDTH 4 +#define D0F2xF4_x14_ITCEntries_MASK 0xf0000000 + +/// D0F2xF4_x14 +typedef union { + struct { ///< + UINT32 ITCReplacementSel:2 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 ITCLRUUpdatePri:1 ; ///< + UINT32 ITCParityEn:1 ; ///< + UINT32 Reserved_7_5:3 ; ///< + UINT32 ITCInvalidationSel:2 ; ///< + UINT32 ITCSoftInvalidate:1 ; ///< + UINT32 Reserved_12_11:2 ; ///< + UINT32 ITCBypass:1 ; ///< + UINT32 Reserved_14_14:1 ; ///< + UINT32 ITCParitySupport:1 ; ///< + UINT32 ITCWays:8 ; ///< + UINT32 Reserved_27_24:4 ; ///< + UINT32 ITCEntries:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x14_STRUCT; + +// **** D0F2xF4_x15 Register Definition **** +// Address +#define D0F2xF4_x15_ADDRESS 0x15 + +// Type +#define D0F2xF4_x15_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x15_ITCFuncBits_OFFSET 0 +#define D0F2xF4_x15_ITCFuncBits_WIDTH 2 +#define D0F2xF4_x15_ITCFuncBits_MASK 0x3 +#define D0F2xF4_x15_ITCDevBits_OFFSET 2 +#define D0F2xF4_x15_ITCDevBits_WIDTH 3 +#define D0F2xF4_x15_ITCDevBits_MASK 0x1c +#define D0F2xF4_x15_ITCBusBits_OFFSET 5 +#define D0F2xF4_x15_ITCBusBits_WIDTH 4 +#define D0F2xF4_x15_ITCBusBits_MASK 0x1e0 +#define D0F2xF4_x15_Reserved_9_9_OFFSET 9 +#define D0F2xF4_x15_Reserved_9_9_WIDTH 1 +#define D0F2xF4_x15_Reserved_9_9_MASK 0x200 +#define D0F2xF4_x15_ItcAltHashEn_OFFSET 10 +#define D0F2xF4_x15_ItcAltHashEn_WIDTH 1 +#define D0F2xF4_x15_ItcAltHashEn_MASK 0x400 +#define D0F2xF4_x15_Reserved_15_11_OFFSET 11 +#define D0F2xF4_x15_Reserved_15_11_WIDTH 5 +#define D0F2xF4_x15_Reserved_15_11_MASK 0xf800 +#define D0F2xF4_x15_ITCAddressMask_OFFSET 16 +#define D0F2xF4_x15_ITCAddressMask_WIDTH 16 +#define D0F2xF4_x15_ITCAddressMask_MASK 0xffff0000 + +/// D0F2xF4_x15 +typedef union { + struct { ///< + UINT32 ITCFuncBits:2 ; ///< + UINT32 ITCDevBits:3 ; ///< + UINT32 ITCBusBits:4 ; ///< + UINT32 Reserved_9_9:1 ; ///< + UINT32 ItcAltHashEn:1 ; ///< + UINT32 Reserved_15_11:5 ; ///< + UINT32 ITCAddressMask:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x15_STRUCT; + +// **** D0F2xF4_x16 Register Definition **** +// Address +#define D0F2xF4_x16_ADDRESS 0x16 + +// Type +#define D0F2xF4_x16_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x16_ITCWayDisable_OFFSET 0 +#define D0F2xF4_x16_ITCWayDisable_WIDTH 16 +#define D0F2xF4_x16_ITCWayDisable_MASK 0xffff +#define D0F2xF4_x16_ITCWayAccessDisable_OFFSET 16 +#define D0F2xF4_x16_ITCWayAccessDisable_WIDTH 16 +#define D0F2xF4_x16_ITCWayAccessDisable_MASK 0xffff0000 + +/// D0F2xF4_x16 +typedef union { + struct { ///< + UINT32 ITCWayDisable:16; ///< + UINT32 ITCWayAccessDisable:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x16_STRUCT; + +// **** D0F2xF4_x18 Register Definition **** +// Address +#define D0F2xF4_x18_ADDRESS 0x18 + +// Type +#define D0F2xF4_x18_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x18_PTCAReplacementSel_OFFSET 0 +#define D0F2xF4_x18_PTCAReplacementSel_WIDTH 2 +#define D0F2xF4_x18_PTCAReplacementSel_MASK 0x3 +#define D0F2xF4_x18_Reserved_2_2_OFFSET 2 +#define D0F2xF4_x18_Reserved_2_2_WIDTH 1 +#define D0F2xF4_x18_Reserved_2_2_MASK 0x4 +#define D0F2xF4_x18_PTCALRUUpdatePri_OFFSET 3 +#define D0F2xF4_x18_PTCALRUUpdatePri_WIDTH 1 +#define D0F2xF4_x18_PTCALRUUpdatePri_MASK 0x8 +#define D0F2xF4_x18_PTCAParityEn_OFFSET 4 +#define D0F2xF4_x18_PTCAParityEn_WIDTH 1 +#define D0F2xF4_x18_PTCAParityEn_MASK 0x10 +#define D0F2xF4_x18_Reserved_7_5_OFFSET 5 +#define D0F2xF4_x18_Reserved_7_5_WIDTH 3 +#define D0F2xF4_x18_Reserved_7_5_MASK 0xe0 +#define D0F2xF4_x18_PTCAInvalidationSel_OFFSET 8 +#define D0F2xF4_x18_PTCAInvalidationSel_WIDTH 2 +#define D0F2xF4_x18_PTCAInvalidationSel_MASK 0x300 +#define D0F2xF4_x18_PTCASoftInvalidate_OFFSET 10 +#define D0F2xF4_x18_PTCASoftInvalidate_WIDTH 1 +#define D0F2xF4_x18_PTCASoftInvalidate_MASK 0x400 +#define D0F2xF4_x18_PTCA2MMode_OFFSET 11 +#define D0F2xF4_x18_PTCA2MMode_WIDTH 1 +#define D0F2xF4_x18_PTCA2MMode_MASK 0x800 +#define D0F2xF4_x18_Reserved_12_12_OFFSET 12 +#define D0F2xF4_x18_Reserved_12_12_WIDTH 1 +#define D0F2xF4_x18_Reserved_12_12_MASK 0x1000 +#define D0F2xF4_x18_PTCABypass_OFFSET 13 +#define D0F2xF4_x18_PTCABypass_WIDTH 1 +#define D0F2xF4_x18_PTCABypass_MASK 0x2000 +#define D0F2xF4_x18_Reserved_14_14_OFFSET 14 +#define D0F2xF4_x18_Reserved_14_14_WIDTH 1 +#define D0F2xF4_x18_Reserved_14_14_MASK 0x4000 +#define D0F2xF4_x18_PTCAParitySupport_OFFSET 15 +#define D0F2xF4_x18_PTCAParitySupport_WIDTH 1 +#define D0F2xF4_x18_PTCAParitySupport_MASK 0x8000 +#define D0F2xF4_x18_PTCAWays_OFFSET 16 +#define D0F2xF4_x18_PTCAWays_WIDTH 8 +#define D0F2xF4_x18_PTCAWays_MASK 0xff0000 +#define D0F2xF4_x18_Reserved_27_24_OFFSET 24 +#define D0F2xF4_x18_Reserved_27_24_WIDTH 4 +#define D0F2xF4_x18_Reserved_27_24_MASK 0xf000000 +#define D0F2xF4_x18_PTCAEntries_OFFSET 28 +#define D0F2xF4_x18_PTCAEntries_WIDTH 4 +#define D0F2xF4_x18_PTCAEntries_MASK 0xf0000000 + +/// D0F2xF4_x18 +typedef union { + struct { ///< + UINT32 PTCAReplacementSel:2 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 PTCALRUUpdatePri:1 ; ///< + UINT32 PTCAParityEn:1 ; ///< + UINT32 Reserved_7_5:3 ; ///< + UINT32 PTCAInvalidationSel:2 ; ///< + UINT32 PTCASoftInvalidate:1 ; ///< + UINT32 PTCA2MMode:1 ; ///< + UINT32 Reserved_12_12:1 ; ///< + UINT32 PTCABypass:1 ; ///< + UINT32 Reserved_14_14:1 ; ///< + UINT32 PTCAParitySupport:1 ; ///< + UINT32 PTCAWays:8 ; ///< + UINT32 Reserved_27_24:4 ; ///< + UINT32 PTCAEntries:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x18_STRUCT; + +// **** D0F2xF4_x19 Register Definition **** +// Address +#define D0F2xF4_x19_ADDRESS 0x19 + +// Type +#define D0F2xF4_x19_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x19_PTCAFuncBits_OFFSET 0 +#define D0F2xF4_x19_PTCAFuncBits_WIDTH 2 +#define D0F2xF4_x19_PTCAFuncBits_MASK 0x3 +#define D0F2xF4_x19_PTCADevBits_OFFSET 2 +#define D0F2xF4_x19_PTCADevBits_WIDTH 3 +#define D0F2xF4_x19_PTCADevBits_MASK 0x1c +#define D0F2xF4_x19_PTCABusBits_OFFSET 5 +#define D0F2xF4_x19_PTCABusBits_WIDTH 4 +#define D0F2xF4_x19_PTCABusBits_MASK 0x1e0 +#define D0F2xF4_x19_Reserved_9_9_OFFSET 9 +#define D0F2xF4_x19_Reserved_9_9_WIDTH 1 +#define D0F2xF4_x19_Reserved_9_9_MASK 0x200 +#define D0F2xF4_x19_PtcAltHashEn_OFFSET 10 +#define D0F2xF4_x19_PtcAltHashEn_WIDTH 1 +#define D0F2xF4_x19_PtcAltHashEn_MASK 0x400 +#define D0F2xF4_x19_Reserved_15_11_OFFSET 11 +#define D0F2xF4_x19_Reserved_15_11_WIDTH 5 +#define D0F2xF4_x19_Reserved_15_11_MASK 0xf800 +#define D0F2xF4_x19_PTCAAddressMask_OFFSET 16 +#define D0F2xF4_x19_PTCAAddressMask_WIDTH 16 +#define D0F2xF4_x19_PTCAAddressMask_MASK 0xffff0000 + +/// D0F2xF4_x19 +typedef union { + struct { ///< + UINT32 PTCAFuncBits:2 ; ///< + UINT32 PTCADevBits:3 ; ///< + UINT32 PTCABusBits:4 ; ///< + UINT32 Reserved_9_9:1 ; ///< + UINT32 PtcAltHashEn:1 ; ///< + UINT32 Reserved_15_11:5 ; ///< + UINT32 PTCAAddressMask:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x19_STRUCT; + +// **** D0F2xF4_x1A Register Definition **** +// Address +#define D0F2xF4_x1A_ADDRESS 0x1a + +// Type +#define D0F2xF4_x1A_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x1A_PTCAWayDisable_OFFSET 0 +#define D0F2xF4_x1A_PTCAWayDisable_WIDTH 16 +#define D0F2xF4_x1A_PTCAWayDisable_MASK 0xffff +#define D0F2xF4_x1A_PTCAWayAccessDisable_OFFSET 16 +#define D0F2xF4_x1A_PTCAWayAccessDisable_WIDTH 16 +#define D0F2xF4_x1A_PTCAWayAccessDisable_MASK 0xffff0000 + +/// D0F2xF4_x1A +typedef union { + struct { ///< + UINT32 PTCAWayDisable:16; ///< + UINT32 PTCAWayAccessDisable:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x1A_STRUCT; + +// **** D0F2xF4_x20 Register Definition **** +// Address +#define D0F2xF4_x20_ADDRESS 0x20 + +// Type +#define D0F2xF4_x20_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x20_QUEUECredits_OFFSET 0 +#define D0F2xF4_x20_QUEUECredits_WIDTH 6 +#define D0F2xF4_x20_QUEUECredits_MASK 0x3f +#define D0F2xF4_x20_Reserved_6_6_OFFSET 6 +#define D0F2xF4_x20_Reserved_6_6_WIDTH 1 +#define D0F2xF4_x20_Reserved_6_6_MASK 0x40 +#define D0F2xF4_x20_QUEUEOverride_OFFSET 7 +#define D0F2xF4_x20_QUEUEOverride_WIDTH 1 +#define D0F2xF4_x20_QUEUEOverride_MASK 0x80 +#define D0F2xF4_x20_FLTCMBCredits_OFFSET 8 +#define D0F2xF4_x20_FLTCMBCredits_WIDTH 6 +#define D0F2xF4_x20_FLTCMBCredits_MASK 0x3f00 +#define D0F2xF4_x20_Reserved_14_14_OFFSET 14 +#define D0F2xF4_x20_Reserved_14_14_WIDTH 1 +#define D0F2xF4_x20_Reserved_14_14_MASK 0x4000 +#define D0F2xF4_x20_FLTCMBOverride_OFFSET 15 +#define D0F2xF4_x20_FLTCMBOverride_WIDTH 1 +#define D0F2xF4_x20_FLTCMBOverride_MASK 0x8000 +#define D0F2xF4_x20_FCELCredits_OFFSET 16 +#define D0F2xF4_x20_FCELCredits_WIDTH 6 +#define D0F2xF4_x20_FCELCredits_MASK 0x3f0000 +#define D0F2xF4_x20_Reserved_22_22_OFFSET 22 +#define D0F2xF4_x20_Reserved_22_22_WIDTH 1 +#define D0F2xF4_x20_Reserved_22_22_MASK 0x400000 +#define D0F2xF4_x20_FCELOverride_OFFSET 23 +#define D0F2xF4_x20_FCELOverride_WIDTH 1 +#define D0F2xF4_x20_FCELOverride_MASK 0x800000 +#define D0F2xF4_x20_PprLoggerCredits_OFFSET 24 +#define D0F2xF4_x20_PprLoggerCredits_WIDTH 4 +#define D0F2xF4_x20_PprLoggerCredits_MASK 0xf000000 +#define D0F2xF4_x20_Reserved_31_28_OFFSET 28 +#define D0F2xF4_x20_Reserved_31_28_WIDTH 4 +#define D0F2xF4_x20_Reserved_31_28_MASK 0xf0000000 + +/// D0F2xF4_x20 +typedef union { + struct { ///< + UINT32 QUEUECredits:6 ; ///< + UINT32 Reserved_6_6:1 ; ///< + UINT32 QUEUEOverride:1 ; ///< + UINT32 FLTCMBCredits:6 ; ///< + UINT32 Reserved_14_14:1 ; ///< + UINT32 FLTCMBOverride:1 ; ///< + UINT32 FCELCredits:6 ; ///< + UINT32 Reserved_22_22:1 ; ///< + UINT32 FCELOverride:1 ; ///< + UINT32 PprLoggerCredits:4 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x20_STRUCT; + +// **** D0F2xF4_x22 Register Definition **** +// Address +#define D0F2xF4_x22_ADDRESS 0x22 + +// Type +#define D0F2xF4_x22_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x22_L2aUpdateFilterBypass_OFFSET 0 +#define D0F2xF4_x22_L2aUpdateFilterBypass_WIDTH 1 +#define D0F2xF4_x22_L2aUpdateFilterBypass_MASK 0x1 +#define D0F2xF4_x22_L2aUpdateFilterRdlatency_OFFSET 1 +#define D0F2xF4_x22_L2aUpdateFilterRdlatency_WIDTH 4 +#define D0F2xF4_x22_L2aUpdateFilterRdlatency_MASK 0x1e +#define D0F2xF4_x22_Reserved_31_5_OFFSET 5 +#define D0F2xF4_x22_Reserved_31_5_WIDTH 27 +#define D0F2xF4_x22_Reserved_31_5_MASK 0xffffffe0 + +/// D0F2xF4_x22 +typedef union { + struct { ///< + UINT32 L2aUpdateFilterBypass:1 ; ///< + UINT32 L2aUpdateFilterRdlatency:4 ; ///< + UINT32 Reserved_31_5:27; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x22_STRUCT; + + + + + + + +// **** D0F2xF4_x30 Register Definition **** +// Address +#define D0F2xF4_x30_ADDRESS 0x30 + +// Type +#define D0F2xF4_x30_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x30_ERRRuleLock1_OFFSET 0 +#define D0F2xF4_x30_ERRRuleLock1_WIDTH 1 +#define D0F2xF4_x30_ERRRuleLock1_MASK 0x1 +#define D0F2xF4_x30_Reserved_3_1_OFFSET 1 +#define D0F2xF4_x30_Reserved_3_1_WIDTH 3 +#define D0F2xF4_x30_Reserved_3_1_MASK 0xe +#define D0F2xF4_x30_ERRRuleDisable3_OFFSET 4 +#define D0F2xF4_x30_ERRRuleDisable3_WIDTH 28 +#define D0F2xF4_x30_ERRRuleDisable3_MASK 0xfffffff0 + +/// D0F2xF4_x30 +typedef union { + struct { ///< + UINT32 ERRRuleLock1:1 ; ///< + UINT32 Reserved_3_1:3 ; ///< + UINT32 ERRRuleDisable3:28; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x30_STRUCT; + +// **** D0F2xF4_x31 Register Definition **** +// Address +#define D0F2xF4_x31_ADDRESS 0x31 + +// Type +#define D0F2xF4_x31_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x31_ERRRuleDisable4_OFFSET 0 +#define D0F2xF4_x31_ERRRuleDisable4_WIDTH 32 +#define D0F2xF4_x31_ERRRuleDisable4_MASK 0xffffffff + +/// D0F2xF4_x31 +typedef union { + struct { ///< + UINT32 ERRRuleDisable4:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x31_STRUCT; + +// **** D0F2xF4_x32 Register Definition **** +// Address +#define D0F2xF4_x32_ADDRESS 0x32 + +// Type +#define D0F2xF4_x32_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x32_ERRRuleDisable5_OFFSET 0 +#define D0F2xF4_x32_ERRRuleDisable5_WIDTH 32 +#define D0F2xF4_x32_ERRRuleDisable5_MASK 0xffffffff + +/// D0F2xF4_x32 +typedef union { + struct { ///< + UINT32 ERRRuleDisable5:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x32_STRUCT; + +// **** D0F2xF4_x33 Register Definition **** +// Address +#define D0F2xF4_x33_ADDRESS 0x33 + +// Type +#define D0F2xF4_x33_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x33_CKGateL2ARegsDisable_OFFSET 0 +#define D0F2xF4_x33_CKGateL2ARegsDisable_WIDTH 1 +#define D0F2xF4_x33_CKGateL2ARegsDisable_MASK 0x1 +#define D0F2xF4_x33_CKGateL2ADynamicDisable_OFFSET 1 +#define D0F2xF4_x33_CKGateL2ADynamicDisable_WIDTH 1 +#define D0F2xF4_x33_CKGateL2ADynamicDisable_MASK 0x2 +#define D0F2xF4_x33_CKGateL2ACacheDisable_OFFSET 2 +#define D0F2xF4_x33_CKGateL2ACacheDisable_WIDTH 1 +#define D0F2xF4_x33_CKGateL2ACacheDisable_MASK 0x4 +#define D0F2xF4_x33_CKGateL2ASpare_OFFSET 3 +#define D0F2xF4_x33_CKGateL2ASpare_WIDTH 1 +#define D0F2xF4_x33_CKGateL2ASpare_MASK 0x8 +#define D0F2xF4_x33_CKGateL2ALength_OFFSET 4 +#define D0F2xF4_x33_CKGateL2ALength_WIDTH 2 +#define D0F2xF4_x33_CKGateL2ALength_MASK 0x30 +#define D0F2xF4_x33_CKGateL2AStop_OFFSET 6 +#define D0F2xF4_x33_CKGateL2AStop_WIDTH 2 +#define D0F2xF4_x33_CKGateL2AStop_MASK 0xc0 +#define D0F2xF4_x33_Reserved_31_8_OFFSET 8 +#define D0F2xF4_x33_Reserved_31_8_WIDTH 24 +#define D0F2xF4_x33_Reserved_31_8_MASK 0xffffff00 + +/// D0F2xF4_x33 +typedef union { + struct { ///< + UINT32 CKGateL2ARegsDisable:1 ; ///< + UINT32 CKGateL2ADynamicDisable:1 ; ///< + UINT32 CKGateL2ACacheDisable:1 ; ///< + UINT32 CKGateL2ASpare:1 ; ///< + UINT32 CKGateL2ALength:2 ; ///< + UINT32 CKGateL2AStop:2 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x33_STRUCT; + +// **** D0F2xF4_x34 Register Definition **** +// Address +#define D0F2xF4_x34_ADDRESS 0x34 + +// Type +#define D0F2xF4_x34_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x34_L2aregGstPgsize_OFFSET 0 +#define D0F2xF4_x34_L2aregGstPgsize_WIDTH 2 +#define D0F2xF4_x34_L2aregGstPgsize_MASK 0x3 +#define D0F2xF4_x34_L2aregHostPgsize_OFFSET 2 +#define D0F2xF4_x34_L2aregHostPgsize_WIDTH 2 +#define D0F2xF4_x34_L2aregHostPgsize_MASK 0xc +#define D0F2xF4_x34_Reserved_31_4_OFFSET 4 +#define D0F2xF4_x34_Reserved_31_4_WIDTH 28 +#define D0F2xF4_x34_Reserved_31_4_MASK 0xfffffff0 + +/// D0F2xF4_x34 +typedef union { + struct { ///< + UINT32 L2aregGstPgsize:2 ; ///< + UINT32 L2aregHostPgsize:2 ; ///< + UINT32 Reserved_31_4:28; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x34_STRUCT; + +// **** D0F2xF4_x40 Register Definition **** +// Address +#define D0F2xF4_x40_ADDRESS 0x40 + +// Type +#define D0F2xF4_x40_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x40_L2PerfEvent4_OFFSET 0 +#define D0F2xF4_x40_L2PerfEvent4_WIDTH 8 +#define D0F2xF4_x40_L2PerfEvent4_MASK 0xff +#define D0F2xF4_x40_L2PerfEvent5_OFFSET 8 +#define D0F2xF4_x40_L2PerfEvent5_WIDTH 8 +#define D0F2xF4_x40_L2PerfEvent5_MASK 0xff00 +#define D0F2xF4_x40_L2PerfCountUpper4_OFFSET 16 +#define D0F2xF4_x40_L2PerfCountUpper4_WIDTH 8 +#define D0F2xF4_x40_L2PerfCountUpper4_MASK 0xff0000 +#define D0F2xF4_x40_L2PerfCountUpper5_OFFSET 24 +#define D0F2xF4_x40_L2PerfCountUpper5_WIDTH 8 +#define D0F2xF4_x40_L2PerfCountUpper5_MASK 0xff000000 + +/// D0F2xF4_x40 +typedef union { + struct { ///< + UINT32 L2PerfEvent4:8 ; ///< + UINT32 L2PerfEvent5:8 ; ///< + UINT32 L2PerfCountUpper4:8 ; ///< + UINT32 L2PerfCountUpper5:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x40_STRUCT; + +// **** D0F2xF4_x41 Register Definition **** +// Address +#define D0F2xF4_x41_ADDRESS 0x41 + +// Type +#define D0F2xF4_x41_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x41_L2PerfCount4_OFFSET 0 +#define D0F2xF4_x41_L2PerfCount4_WIDTH 32 +#define D0F2xF4_x41_L2PerfCount4_MASK 0xffffffff + +/// D0F2xF4_x41 +typedef union { + struct { ///< + UINT32 L2PerfCount4:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x41_STRUCT; + +// **** D0F2xF4_x42 Register Definition **** +// Address +#define D0F2xF4_x42_ADDRESS 0x42 + +// Type +#define D0F2xF4_x42_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x42_L2PerfCount5_OFFSET 0 +#define D0F2xF4_x42_L2PerfCount5_WIDTH 32 +#define D0F2xF4_x42_L2PerfCount5_MASK 0xffffffff + +/// D0F2xF4_x42 +typedef union { + struct { ///< + UINT32 L2PerfCount5:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x42_STRUCT; + +// **** D0F2xF4_x43 Register Definition **** +// Address +#define D0F2xF4_x43_ADDRESS 0x43 + +// Type +#define D0F2xF4_x43_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x43_L2PerfEvent6_OFFSET 0 +#define D0F2xF4_x43_L2PerfEvent6_WIDTH 8 +#define D0F2xF4_x43_L2PerfEvent6_MASK 0xff +#define D0F2xF4_x43_L2PerfEvent7_OFFSET 8 +#define D0F2xF4_x43_L2PerfEvent7_WIDTH 8 +#define D0F2xF4_x43_L2PerfEvent7_MASK 0xff00 +#define D0F2xF4_x43_L2PerfCountUpper6_OFFSET 16 +#define D0F2xF4_x43_L2PerfCountUpper6_WIDTH 8 +#define D0F2xF4_x43_L2PerfCountUpper6_MASK 0xff0000 +#define D0F2xF4_x43_L2PerfCountUpper7_OFFSET 24 +#define D0F2xF4_x43_L2PerfCountUpper7_WIDTH 8 +#define D0F2xF4_x43_L2PerfCountUpper7_MASK 0xff000000 + +/// D0F2xF4_x43 +typedef union { + struct { ///< + UINT32 L2PerfEvent6:8 ; ///< + UINT32 L2PerfEvent7:8 ; ///< + UINT32 L2PerfCountUpper6:8 ; ///< + UINT32 L2PerfCountUpper7:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x43_STRUCT; + +// **** D0F2xF4_x44 Register Definition **** +// Address +#define D0F2xF4_x44_ADDRESS 0x44 + +// Type +#define D0F2xF4_x44_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x44_L2PerfCount6_OFFSET 0 +#define D0F2xF4_x44_L2PerfCount6_WIDTH 32 +#define D0F2xF4_x44_L2PerfCount6_MASK 0xffffffff + +/// D0F2xF4_x44 +typedef union { + struct { ///< + UINT32 L2PerfCount6:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x44_STRUCT; + +// **** D0F2xF4_x45 Register Definition **** +// Address +#define D0F2xF4_x45_ADDRESS 0x45 + +// Type +#define D0F2xF4_x45_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x45_L2PerfCount7_OFFSET 0 +#define D0F2xF4_x45_L2PerfCount7_WIDTH 32 +#define D0F2xF4_x45_L2PerfCount7_MASK 0xffffffff + +/// D0F2xF4_x45 +typedef union { + struct { ///< + UINT32 L2PerfCount7:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x45_STRUCT; + +// **** D0F2xF4_x46 Register Definition **** +// Address +#define D0F2xF4_x46_ADDRESS 0x46 + +// Type +#define D0F2xF4_x46_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x46_L2DEBUG2_OFFSET 0 +#define D0F2xF4_x46_L2DEBUG2_WIDTH 32 +#define D0F2xF4_x46_L2DEBUG2_MASK 0xffffffff + +/// D0F2xF4_x46 +typedef union { + struct { ///< + UINT32 L2DEBUG2:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x46_STRUCT; + +// **** D0F2xF4_x47 Register Definition **** +// Address +#define D0F2xF4_x47_ADDRESS 0x47 + +// Type +#define D0F2xF4_x47_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x47_Reserved_0_0_OFFSET 0 +#define D0F2xF4_x47_Reserved_0_0_WIDTH 1 +#define D0F2xF4_x47_Reserved_0_0_MASK 0x1 +#define D0F2xF4_x47_TwNwEn_OFFSET 1 +#define D0F2xF4_x47_TwNwEn_WIDTH 1 +#define D0F2xF4_x47_TwNwEn_MASK 0x2 +#define D0F2xF4_x47_TwAtomicFilterEn_OFFSET 2 +#define D0F2xF4_x47_TwAtomicFilterEn_WIDTH 1 +#define D0F2xF4_x47_TwAtomicFilterEn_MASK 0x4 +#define D0F2xF4_x47_Reserved_31_3_OFFSET 3 +#define D0F2xF4_x47_Reserved_31_3_WIDTH 29 +#define D0F2xF4_x47_Reserved_31_3_MASK 0xfffffff8 + +/// D0F2xF4_x47 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 TwNwEn:1 ; ///< + UINT32 TwAtomicFilterEn:1 ; ///< + UINT32 Reserved_31_3:29; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x47_STRUCT; + +// **** D0F2xF4_x48 Register Definition **** +// Address +#define D0F2xF4_x48_ADDRESS 0x48 + +// Type +#define D0F2xF4_x48_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x48_L2STATUS1_OFFSET 0 +#define D0F2xF4_x48_L2STATUS1_WIDTH 32 +#define D0F2xF4_x48_L2STATUS1_MASK 0xffffffff + +/// D0F2xF4_x48 +typedef union { + struct { ///< + UINT32 L2STATUS1:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x48_STRUCT; + +// **** D0F2xF4_x4C Register Definition **** +// Address +#define D0F2xF4_x4C_ADDRESS 0x4c + +// Type +#define D0F2xF4_x4C_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x4C_QueueArbFBPri_OFFSET 0 +#define D0F2xF4_x4C_QueueArbFBPri_WIDTH 1 +#define D0F2xF4_x4C_QueueArbFBPri_MASK 0x1 +#define D0F2xF4_x4C_PTCAddrTransReqUpdate_OFFSET 1 +#define D0F2xF4_x4C_PTCAddrTransReqUpdate_WIDTH 1 +#define D0F2xF4_x4C_PTCAddrTransReqUpdate_MASK 0x2 +#define D0F2xF4_x4C_FC1Dis_OFFSET 2 +#define D0F2xF4_x4C_FC1Dis_WIDTH 1 +#define D0F2xF4_x4C_FC1Dis_MASK 0x4 +#define D0F2xF4_x4C_DTCUpdateVOneIVZero_OFFSET 3 +#define D0F2xF4_x4C_DTCUpdateVOneIVZero_WIDTH 1 +#define D0F2xF4_x4C_DTCUpdateVOneIVZero_MASK 0x8 +#define D0F2xF4_x4C_DTCUpdateVZeroIVOne_OFFSET 4 +#define D0F2xF4_x4C_DTCUpdateVZeroIVOne_WIDTH 1 +#define D0F2xF4_x4C_DTCUpdateVZeroIVOne_MASK 0x10 +#define D0F2xF4_x4C_FC2Dis_OFFSET 5 +#define D0F2xF4_x4C_FC2Dis_WIDTH 1 +#define D0F2xF4_x4C_FC2Dis_MASK 0x20 +#define D0F2xF4_x4C_FC3Dis_OFFSET 6 +#define D0F2xF4_x4C_FC3Dis_WIDTH 1 +#define D0F2xF4_x4C_FC3Dis_MASK 0x40 +#define D0F2xF4_x4C_FC2AltMode_OFFSET 7 +#define D0F2xF4_x4C_FC2AltMode_WIDTH 1 +#define D0F2xF4_x4C_FC2AltMode_MASK 0x80 +#define D0F2xF4_x4C_GstPartialPtcCntrl_OFFSET 8 +#define D0F2xF4_x4C_GstPartialPtcCntrl_WIDTH 2 +#define D0F2xF4_x4C_GstPartialPtcCntrl_MASK 0x300 +#define D0F2xF4_x4C_Reserved_31_10_OFFSET 10 +#define D0F2xF4_x4C_Reserved_31_10_WIDTH 22 +#define D0F2xF4_x4C_Reserved_31_10_MASK 0xfffffc00 + +/// D0F2xF4_x4C +typedef union { + struct { ///< + UINT32 QueueArbFBPri:1 ; ///< + UINT32 PTCAddrTransReqUpdate:1 ; ///< + UINT32 FC1Dis:1 ; ///< + UINT32 DTCUpdateVOneIVZero:1 ; ///< + UINT32 DTCUpdateVZeroIVOne:1 ; ///< + UINT32 FC2Dis:1 ; ///< + UINT32 FC3Dis:1 ; ///< + UINT32 FC2AltMode:1 ; ///< + UINT32 GstPartialPtcCntrl:2 ; ///< + UINT32 Reserved_31_10:22; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x4C_STRUCT; + +// **** D0F2xF4_x4D Register Definition **** +// Address +#define D0F2xF4_x4D_ADDRESS 0x4d + +// Type +#define D0F2xF4_x4D_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x4D_SeqInvBurstLimitInv_OFFSET 0 +#define D0F2xF4_x4D_SeqInvBurstLimitInv_WIDTH 8 +#define D0F2xF4_x4D_SeqInvBurstLimitInv_MASK 0xff +#define D0F2xF4_x4D_SeqInvBurstLimitPDCReq_OFFSET 8 +#define D0F2xF4_x4D_SeqInvBurstLimitPDCReq_WIDTH 8 +#define D0F2xF4_x4D_SeqInvBurstLimitPDCReq_MASK 0xff00 +#define D0F2xF4_x4D_SeqInvBurstLimitEn_OFFSET 16 +#define D0F2xF4_x4D_SeqInvBurstLimitEn_WIDTH 1 +#define D0F2xF4_x4D_SeqInvBurstLimitEn_MASK 0x10000 +#define D0F2xF4_x4D_Reserved_23_17_OFFSET 17 +#define D0F2xF4_x4D_Reserved_23_17_WIDTH 7 +#define D0F2xF4_x4D_Reserved_23_17_MASK 0xfe0000 +#define D0F2xF4_x4D_Perf2Threshold_OFFSET 24 +#define D0F2xF4_x4D_Perf2Threshold_WIDTH 8 +#define D0F2xF4_x4D_Perf2Threshold_MASK 0xff000000 + +/// D0F2xF4_x4D +typedef union { + struct { ///< + UINT32 SeqInvBurstLimitInv:8 ; ///< + UINT32 SeqInvBurstLimitPDCReq:8 ; ///< + UINT32 SeqInvBurstLimitEn:1 ; ///< + UINT32 Reserved_23_17:7 ; ///< + UINT32 Perf2Threshold:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x4D_STRUCT; + +// **** D0F2xF4_x50 Register Definition **** +// Address +#define D0F2xF4_x50_ADDRESS 0x50 + +// Type +#define D0F2xF4_x50_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x50_PDCReplacementSel_OFFSET 0 +#define D0F2xF4_x50_PDCReplacementSel_WIDTH 2 +#define D0F2xF4_x50_PDCReplacementSel_MASK 0x3 +#define D0F2xF4_x50_Reserved_2_2_OFFSET 2 +#define D0F2xF4_x50_Reserved_2_2_WIDTH 1 +#define D0F2xF4_x50_Reserved_2_2_MASK 0x4 +#define D0F2xF4_x50_PDCLRUUpdatePri_OFFSET 3 +#define D0F2xF4_x50_PDCLRUUpdatePri_WIDTH 1 +#define D0F2xF4_x50_PDCLRUUpdatePri_MASK 0x8 +#define D0F2xF4_x50_PDCParityEn_OFFSET 4 +#define D0F2xF4_x50_PDCParityEn_WIDTH 1 +#define D0F2xF4_x50_PDCParityEn_MASK 0x10 +#define D0F2xF4_x50_Reserved_7_5_OFFSET 5 +#define D0F2xF4_x50_Reserved_7_5_WIDTH 3 +#define D0F2xF4_x50_Reserved_7_5_MASK 0xe0 +#define D0F2xF4_x50_PDCInvalidationSel_OFFSET 8 +#define D0F2xF4_x50_PDCInvalidationSel_WIDTH 2 +#define D0F2xF4_x50_PDCInvalidationSel_MASK 0x300 +#define D0F2xF4_x50_PDCSoftInvalidate_OFFSET 10 +#define D0F2xF4_x50_PDCSoftInvalidate_WIDTH 1 +#define D0F2xF4_x50_PDCSoftInvalidate_MASK 0x400 +#define D0F2xF4_x50_Reserved_11_11_OFFSET 11 +#define D0F2xF4_x50_Reserved_11_11_WIDTH 1 +#define D0F2xF4_x50_Reserved_11_11_MASK 0x800 +#define D0F2xF4_x50_PDCSearchDirection_OFFSET 12 +#define D0F2xF4_x50_PDCSearchDirection_WIDTH 1 +#define D0F2xF4_x50_PDCSearchDirection_MASK 0x1000 +#define D0F2xF4_x50_PDCBypass_OFFSET 13 +#define D0F2xF4_x50_PDCBypass_WIDTH 1 +#define D0F2xF4_x50_PDCBypass_MASK 0x2000 +#define D0F2xF4_x50_Reserved_14_14_OFFSET 14 +#define D0F2xF4_x50_Reserved_14_14_WIDTH 1 +#define D0F2xF4_x50_Reserved_14_14_MASK 0x4000 +#define D0F2xF4_x50_PDCParitySupport_OFFSET 15 +#define D0F2xF4_x50_PDCParitySupport_WIDTH 1 +#define D0F2xF4_x50_PDCParitySupport_MASK 0x8000 +#define D0F2xF4_x50_PDCWays_OFFSET 16 +#define D0F2xF4_x50_PDCWays_WIDTH 8 +#define D0F2xF4_x50_PDCWays_MASK 0xff0000 +#define D0F2xF4_x50_Reserved_27_24_OFFSET 24 +#define D0F2xF4_x50_Reserved_27_24_WIDTH 4 +#define D0F2xF4_x50_Reserved_27_24_MASK 0xf000000 +#define D0F2xF4_x50_PDCEntries_OFFSET 28 +#define D0F2xF4_x50_PDCEntries_WIDTH 4 +#define D0F2xF4_x50_PDCEntries_MASK 0xf0000000 + +/// D0F2xF4_x50 +typedef union { + struct { ///< + UINT32 PDCReplacementSel:2 ; ///< + UINT32 Reserved_2_2:1 ; ///< + UINT32 PDCLRUUpdatePri:1 ; ///< + UINT32 PDCParityEn:1 ; ///< + UINT32 Reserved_7_5:3 ; ///< + UINT32 PDCInvalidationSel:2 ; ///< + UINT32 PDCSoftInvalidate:1 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 PDCSearchDirection:1 ; ///< + UINT32 PDCBypass:1 ; ///< + UINT32 Reserved_14_14:1 ; ///< + UINT32 PDCParitySupport:1 ; ///< + UINT32 PDCWays:8 ; ///< + UINT32 Reserved_27_24:4 ; ///< + UINT32 PDCEntries:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x50_STRUCT; + +// **** D0F2xF4_x51 Register Definition **** +// Address +#define D0F2xF4_x51_ADDRESS 0x51 + +// Type +#define D0F2xF4_x51_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x51_PDCDomainBits_OFFSET 0 +#define D0F2xF4_x51_PDCDomainBits_WIDTH 6 +#define D0F2xF4_x51_PDCDomainBits_MASK 0x3f +#define D0F2xF4_x51_Reserved_7_6_OFFSET 6 +#define D0F2xF4_x51_Reserved_7_6_WIDTH 2 +#define D0F2xF4_x51_Reserved_7_6_MASK 0xc0 +#define D0F2xF4_x51_PDCLvlHash_OFFSET 8 +#define D0F2xF4_x51_PDCLvlHash_WIDTH 1 +#define D0F2xF4_x51_PDCLvlHash_MASK 0x100 +#define D0F2xF4_x51_PDCUpperLvlAddrHash_OFFSET 9 +#define D0F2xF4_x51_PDCUpperLvlAddrHash_WIDTH 1 +#define D0F2xF4_x51_PDCUpperLvlAddrHash_MASK 0x200 +#define D0F2xF4_x51_PdcAltHashEn_OFFSET 10 +#define D0F2xF4_x51_PdcAltHashEn_WIDTH 1 +#define D0F2xF4_x51_PdcAltHashEn_MASK 0x400 +#define D0F2xF4_x51_Reserved_15_11_OFFSET 11 +#define D0F2xF4_x51_Reserved_15_11_WIDTH 5 +#define D0F2xF4_x51_Reserved_15_11_MASK 0xf800 +#define D0F2xF4_x51_PDCAddressMask_OFFSET 16 +#define D0F2xF4_x51_PDCAddressMask_WIDTH 16 +#define D0F2xF4_x51_PDCAddressMask_MASK 0xffff0000 + +/// D0F2xF4_x51 +typedef union { + struct { ///< + UINT32 PDCDomainBits:6 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 PDCLvlHash:1 ; ///< + UINT32 PDCUpperLvlAddrHash:1 ; ///< + UINT32 PdcAltHashEn:1 ; ///< + UINT32 Reserved_15_11:5 ; ///< + UINT32 PDCAddressMask:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x51_STRUCT; + +// **** D0F2xF4_x52 Register Definition **** +// Address +#define D0F2xF4_x52_ADDRESS 0x52 + +// Type +#define D0F2xF4_x52_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x52_PDCWayDisable_OFFSET 0 +#define D0F2xF4_x52_PDCWayDisable_WIDTH 16 +#define D0F2xF4_x52_PDCWayDisable_MASK 0xffff +#define D0F2xF4_x52_PDCWayAccessDisable_OFFSET 16 +#define D0F2xF4_x52_PDCWayAccessDisable_WIDTH 16 +#define D0F2xF4_x52_PDCWayAccessDisable_MASK 0xffff0000 + +/// D0F2xF4_x52 +typedef union { + struct { ///< + UINT32 PDCWayDisable:16; ///< + UINT32 PDCWayAccessDisable:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x52_STRUCT; + +// **** D0F2xF4_x53 Register Definition **** +// Address +#define D0F2xF4_x53_ADDRESS 0x53 + +// Type +#define D0F2xF4_x53_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x53_L2bUpdateFilterBypass_OFFSET 0 +#define D0F2xF4_x53_L2bUpdateFilterBypass_WIDTH 1 +#define D0F2xF4_x53_L2bUpdateFilterBypass_MASK 0x1 +#define D0F2xF4_x53_L2bUpdateFilterRdlatency_OFFSET 1 +#define D0F2xF4_x53_L2bUpdateFilterRdlatency_WIDTH 4 +#define D0F2xF4_x53_L2bUpdateFilterRdlatency_MASK 0x1e +#define D0F2xF4_x53_Reserved_31_5_OFFSET 5 +#define D0F2xF4_x53_Reserved_31_5_WIDTH 27 +#define D0F2xF4_x53_Reserved_31_5_MASK 0xffffffe0 + +/// D0F2xF4_x53 +typedef union { + struct { ///< + UINT32 L2bUpdateFilterBypass:1 ; ///< + UINT32 L2bUpdateFilterRdlatency:4 ; ///< + UINT32 Reserved_31_5:27; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x53_STRUCT; + +// **** D0F2xF4_x54 Register Definition **** +// Address +#define D0F2xF4_x54_ADDRESS 0x54 + +// Type +#define D0F2xF4_x54_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x54_TWQueueLimit_OFFSET 0 +#define D0F2xF4_x54_TWQueueLimit_WIDTH 6 +#define D0F2xF4_x54_TWQueueLimit_MASK 0x3f +#define D0F2xF4_x54_TWForceCoherent_OFFSET 6 +#define D0F2xF4_x54_TWForceCoherent_WIDTH 1 +#define D0F2xF4_x54_TWForceCoherent_MASK 0x40 +#define D0F2xF4_x54_Reserved_7_7_OFFSET 7 +#define D0F2xF4_x54_Reserved_7_7_WIDTH 1 +#define D0F2xF4_x54_Reserved_7_7_MASK 0x80 +#define D0F2xF4_x54_TWPrefetchEn_OFFSET 8 +#define D0F2xF4_x54_TWPrefetchEn_WIDTH 1 +#define D0F2xF4_x54_TWPrefetchEn_MASK 0x100 +#define D0F2xF4_x54_TWPrefetchOnly4KDis_OFFSET 9 +#define D0F2xF4_x54_TWPrefetchOnly4KDis_WIDTH 1 +#define D0F2xF4_x54_TWPrefetchOnly4KDis_MASK 0x200 +#define D0F2xF4_x54_TWPTEOnUntransExcl_OFFSET 10 +#define D0F2xF4_x54_TWPTEOnUntransExcl_WIDTH 1 +#define D0F2xF4_x54_TWPTEOnUntransExcl_MASK 0x400 +#define D0F2xF4_x54_TWPTEOnAddrTransExcl_OFFSET 11 +#define D0F2xF4_x54_TWPTEOnAddrTransExcl_WIDTH 1 +#define D0F2xF4_x54_TWPTEOnAddrTransExcl_MASK 0x800 +#define D0F2xF4_x54_TWPrefetchRange_OFFSET 12 +#define D0F2xF4_x54_TWPrefetchRange_WIDTH 3 +#define D0F2xF4_x54_TWPrefetchRange_MASK 0x7000 +#define D0F2xF4_x54_Reserved_15_15_OFFSET 15 +#define D0F2xF4_x54_Reserved_15_15_WIDTH 1 +#define D0F2xF4_x54_Reserved_15_15_MASK 0x8000 +#define D0F2xF4_x54_TwfilterDis_OFFSET 16 +#define D0F2xF4_x54_TwfilterDis_WIDTH 1 +#define D0F2xF4_x54_TwfilterDis_MASK 0x10000 +#define D0F2xF4_x54_Twfilter64bDis_OFFSET 17 +#define D0F2xF4_x54_Twfilter64bDis_WIDTH 1 +#define D0F2xF4_x54_Twfilter64bDis_MASK 0x20000 +#define D0F2xF4_x54_Reserved_31_18_OFFSET 18 +#define D0F2xF4_x54_Reserved_31_18_WIDTH 14 +#define D0F2xF4_x54_Reserved_31_18_MASK 0xfffc0000 + +/// D0F2xF4_x54 +typedef union { + struct { ///< + UINT32 TWQueueLimit:6 ; ///< + UINT32 TWForceCoherent:1 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 TWPrefetchEn:1 ; ///< + UINT32 TWPrefetchOnly4KDis:1 ; ///< + UINT32 TWPTEOnUntransExcl:1 ; ///< + UINT32 TWPTEOnAddrTransExcl:1 ; ///< + UINT32 TWPrefetchRange:3 ; ///< + UINT32 Reserved_15_15:1 ; ///< + UINT32 TwfilterDis:1 ; ///< + UINT32 Twfilter64bDis:1 ; ///< + UINT32 Reserved_31_18:14; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x54_STRUCT; + +// **** D0F2xF4_x56 Register Definition **** +// Address +#define D0F2xF4_x56_ADDRESS 0x56 + +// Type +#define D0F2xF4_x56_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x56_CPPrefetchDis_OFFSET 0 +#define D0F2xF4_x56_CPPrefetchDis_WIDTH 1 +#define D0F2xF4_x56_CPPrefetchDis_MASK 0x1 +#define D0F2xF4_x56_CPFlushOnWait_OFFSET 1 +#define D0F2xF4_x56_CPFlushOnWait_WIDTH 1 +#define D0F2xF4_x56_CPFlushOnWait_MASK 0x2 +#define D0F2xF4_x56_CPFlushOnInv_OFFSET 2 +#define D0F2xF4_x56_CPFlushOnInv_WIDTH 1 +#define D0F2xF4_x56_CPFlushOnInv_MASK 0x4 +#define D0F2xF4_x56_Reserved_15_3_OFFSET 3 +#define D0F2xF4_x56_Reserved_15_3_WIDTH 13 +#define D0F2xF4_x56_Reserved_15_3_MASK 0xfff8 +#define D0F2xF4_x56_CPRdDelay_OFFSET 16 +#define D0F2xF4_x56_CPRdDelay_WIDTH 16 +#define D0F2xF4_x56_CPRdDelay_MASK 0xffff0000 + +/// D0F2xF4_x56 +typedef union { + struct { ///< + UINT32 CPPrefetchDis:1 ; ///< + UINT32 CPFlushOnWait:1 ; ///< + UINT32 CPFlushOnInv:1 ; ///< + UINT32 Reserved_15_3:13; ///< + UINT32 CPRdDelay:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x56_STRUCT; + +// **** D0F2xF4_x57 Register Definition **** +// Address +#define D0F2xF4_x57_ADDRESS 0x57 + +// Type +#define D0F2xF4_x57_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x57_L1ImuPcieGfxDis_OFFSET 0 +#define D0F2xF4_x57_L1ImuPcieGfxDis_WIDTH 1 +#define D0F2xF4_x57_L1ImuPcieGfxDis_MASK 0x1 +#define D0F2xF4_x57_Reserved_1_1_OFFSET 1 +#define D0F2xF4_x57_Reserved_1_1_WIDTH 1 +#define D0F2xF4_x57_Reserved_1_1_MASK 0x2 +#define D0F2xF4_x57_L1ImuIntGfxDis_OFFSET 2 +#define D0F2xF4_x57_L1ImuIntGfxDis_WIDTH 1 +#define D0F2xF4_x57_L1ImuIntGfxDis_MASK 0x4 +#define D0F2xF4_x57_Reserved_31_3_OFFSET 3 +#define D0F2xF4_x57_Reserved_31_3_WIDTH 29 +#define D0F2xF4_x57_Reserved_31_3_MASK 0xfffffff8 + +/// D0F2xF4_x57 +typedef union { + struct { ///< + UINT32 L1ImuPcieGfxDis:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 L1ImuIntGfxDis:1 ; ///< + UINT32 Reserved_31_3:29; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x57_STRUCT; + +// **** D0F2xF4_x58 Register Definition **** +// Address +#define D0F2xF4_x58_ADDRESS 0x58 + +// Type +#define D0F2xF4_x58_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x58_IommuL2GuestAddrMask_OFFSET 0 +#define D0F2xF4_x58_IommuL2GuestAddrMask_WIDTH 24 +#define D0F2xF4_x58_IommuL2GuestAddrMask_MASK 0xffffff +#define D0F2xF4_x58_Reserved_31_24_OFFSET 24 +#define D0F2xF4_x58_Reserved_31_24_WIDTH 8 +#define D0F2xF4_x58_Reserved_31_24_MASK 0xff000000 + +/// D0F2xF4_x58 +typedef union { + struct { ///< + UINT32 IommuL2GuestAddrMask:24; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x58_STRUCT; + +// **** D0F2xF4_x60 Register Definition **** +// Address +#define D0F2xF4_x60_ADDRESS 0x60 + +// Type +#define D0F2xF4_x60_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x60_TWDebugEn_OFFSET 0 +#define D0F2xF4_x60_TWDebugEn_WIDTH 1 +#define D0F2xF4_x60_TWDebugEn_MASK 0x1 +#define D0F2xF4_x60_TWDebugNoWrap_OFFSET 1 +#define D0F2xF4_x60_TWDebugNoWrap_WIDTH 1 +#define D0F2xF4_x60_TWDebugNoWrap_MASK 0x2 +#define D0F2xF4_x60_TWDebugForceDisable_OFFSET 2 +#define D0F2xF4_x60_TWDebugForceDisable_WIDTH 1 +#define D0F2xF4_x60_TWDebugForceDisable_MASK 0x4 +#define D0F2xF4_x60_Reserved_14_3_OFFSET 3 +#define D0F2xF4_x60_Reserved_14_3_WIDTH 12 +#define D0F2xF4_x60_Reserved_14_3_MASK 0x7ff8 +#define D0F2xF4_x60_TWDebugMask_OFFSET 15 +#define D0F2xF4_x60_TWDebugMask_WIDTH 17 +#define D0F2xF4_x60_TWDebugMask_MASK 0xffff8000 + +/// D0F2xF4_x60 +typedef union { + struct { ///< + UINT32 TWDebugEn:1 ; ///< + UINT32 TWDebugNoWrap:1 ; ///< + UINT32 TWDebugForceDisable:1 ; ///< + UINT32 Reserved_14_3:12; ///< + UINT32 TWDebugMask:17; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x60_STRUCT; + +// **** D0F2xF4_x61 Register Definition **** +// Address +#define D0F2xF4_x61_ADDRESS 0x61 + +// Type +#define D0F2xF4_x61_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x61_Reserved_11_0_OFFSET 0 +#define D0F2xF4_x61_Reserved_11_0_WIDTH 12 +#define D0F2xF4_x61_Reserved_11_0_MASK 0xfff +#define D0F2xF4_x61_TWDebugAddrLo_OFFSET 12 +#define D0F2xF4_x61_TWDebugAddrLo_WIDTH 20 +#define D0F2xF4_x61_TWDebugAddrLo_MASK 0xfffff000 + +/// D0F2xF4_x61 +typedef union { + struct { ///< + UINT32 Reserved_11_0:12; ///< + UINT32 TWDebugAddrLo:20; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x61_STRUCT; + +// **** D0F2xF4_x62 Register Definition **** +// Address +#define D0F2xF4_x62_ADDRESS 0x62 + +// Type +#define D0F2xF4_x62_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x62_TWDebugAddrHi_OFFSET 0 +#define D0F2xF4_x62_TWDebugAddrHi_WIDTH 32 +#define D0F2xF4_x62_TWDebugAddrHi_MASK 0xffffffff + +/// D0F2xF4_x62 +typedef union { + struct { ///< + UINT32 TWDebugAddrHi:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x62_STRUCT; + +// **** D0F2xF4_x6A Register Definition **** +// Address +#define D0F2xF4_x6A_ADDRESS 0x6a + +// Type +#define D0F2xF4_x6A_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x6A_IntEventOrderEn_OFFSET 0 +#define D0F2xF4_x6A_IntEventOrderEn_WIDTH 1 +#define D0F2xF4_x6A_IntEventOrderEn_MASK 0x1 +#define D0F2xF4_x6A_IntCPOrderEn_OFFSET 1 +#define D0F2xF4_x6A_IntCPOrderEn_WIDTH 1 +#define D0F2xF4_x6A_IntCPOrderEn_MASK 0x2 +#define D0F2xF4_x6A_IntPPROrderEn_OFFSET 2 +#define D0F2xF4_x6A_IntPPROrderEn_WIDTH 1 +#define D0F2xF4_x6A_IntPPROrderEn_MASK 0x4 +#define D0F2xF4_x6A_Reserved_31_3_OFFSET 3 +#define D0F2xF4_x6A_Reserved_31_3_WIDTH 29 +#define D0F2xF4_x6A_Reserved_31_3_MASK 0xfffffff8 + +/// D0F2xF4_x6A +typedef union { + struct { ///< + UINT32 IntEventOrderEn:1 ; ///< + UINT32 IntCPOrderEn:1 ; ///< + UINT32 IntPPROrderEn:1 ; ///< + UINT32 Reserved_31_3:29; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x6A_STRUCT; + +// **** D0F2xF4_x70 Register Definition **** +// Address +#define D0F2xF4_x70_ADDRESS 0x70 + +// Type +#define D0F2xF4_x70_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x70_FC1Credits_OFFSET 0 +#define D0F2xF4_x70_FC1Credits_WIDTH 6 +#define D0F2xF4_x70_FC1Credits_MASK 0x3f +#define D0F2xF4_x70_Reserved_6_6_OFFSET 6 +#define D0F2xF4_x70_Reserved_6_6_WIDTH 1 +#define D0F2xF4_x70_Reserved_6_6_MASK 0x40 +#define D0F2xF4_x70_FC1Override_OFFSET 7 +#define D0F2xF4_x70_FC1Override_WIDTH 1 +#define D0F2xF4_x70_FC1Override_MASK 0x80 +#define D0F2xF4_x70_FC2Credits_OFFSET 8 +#define D0F2xF4_x70_FC2Credits_WIDTH 6 +#define D0F2xF4_x70_FC2Credits_MASK 0x3f00 +#define D0F2xF4_x70_Reserved_14_14_OFFSET 14 +#define D0F2xF4_x70_Reserved_14_14_WIDTH 1 +#define D0F2xF4_x70_Reserved_14_14_MASK 0x4000 +#define D0F2xF4_x70_FC2Override_OFFSET 15 +#define D0F2xF4_x70_FC2Override_WIDTH 1 +#define D0F2xF4_x70_FC2Override_MASK 0x8000 +#define D0F2xF4_x70_FC3Credits_OFFSET 16 +#define D0F2xF4_x70_FC3Credits_WIDTH 6 +#define D0F2xF4_x70_FC3Credits_MASK 0x3f0000 +#define D0F2xF4_x70_Reserved_22_22_OFFSET 22 +#define D0F2xF4_x70_Reserved_22_22_WIDTH 1 +#define D0F2xF4_x70_Reserved_22_22_MASK 0x400000 +#define D0F2xF4_x70_FC3Override_OFFSET 23 +#define D0F2xF4_x70_FC3Override_WIDTH 1 +#define D0F2xF4_x70_FC3Override_MASK 0x800000 +#define D0F2xF4_x70_DTECredits_OFFSET 24 +#define D0F2xF4_x70_DTECredits_WIDTH 6 +#define D0F2xF4_x70_DTECredits_MASK 0x3f000000 +#define D0F2xF4_x70_Reserved_30_30_OFFSET 30 +#define D0F2xF4_x70_Reserved_30_30_WIDTH 1 +#define D0F2xF4_x70_Reserved_30_30_MASK 0x40000000 +#define D0F2xF4_x70_DTEOverride_OFFSET 31 +#define D0F2xF4_x70_DTEOverride_WIDTH 1 +#define D0F2xF4_x70_DTEOverride_MASK 0x80000000 + +/// D0F2xF4_x70 +typedef union { + struct { ///< + UINT32 FC1Credits:6 ; ///< + UINT32 Reserved_6_6:1 ; ///< + UINT32 FC1Override:1 ; ///< + UINT32 FC2Credits:6 ; ///< + UINT32 Reserved_14_14:1 ; ///< + UINT32 FC2Override:1 ; ///< + UINT32 FC3Credits:6 ; ///< + UINT32 Reserved_22_22:1 ; ///< + UINT32 FC3Override:1 ; ///< + UINT32 DTECredits:6 ; ///< + UINT32 Reserved_30_30:1 ; ///< + UINT32 DTEOverride:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x70_STRUCT; + +// **** D0F2xF4_x71 Register Definition **** +// Address +#define D0F2xF4_x71_ADDRESS 0x71 + +// Type +#define D0F2xF4_x71_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x71_PDTIECredits_OFFSET 0 +#define D0F2xF4_x71_PDTIECredits_WIDTH 6 +#define D0F2xF4_x71_PDTIECredits_MASK 0x3f +#define D0F2xF4_x71_Reserved_6_6_OFFSET 6 +#define D0F2xF4_x71_Reserved_6_6_WIDTH 1 +#define D0F2xF4_x71_Reserved_6_6_MASK 0x40 +#define D0F2xF4_x71_PDTIEOverride_OFFSET 7 +#define D0F2xF4_x71_PDTIEOverride_WIDTH 1 +#define D0F2xF4_x71_PDTIEOverride_MASK 0x80 +#define D0F2xF4_x71_TWELCredits_OFFSET 8 +#define D0F2xF4_x71_TWELCredits_WIDTH 6 +#define D0F2xF4_x71_TWELCredits_MASK 0x3f00 +#define D0F2xF4_x71_Reserved_14_14_OFFSET 14 +#define D0F2xF4_x71_Reserved_14_14_WIDTH 1 +#define D0F2xF4_x71_Reserved_14_14_MASK 0x4000 +#define D0F2xF4_x71_TWELOverride_OFFSET 15 +#define D0F2xF4_x71_TWELOverride_WIDTH 1 +#define D0F2xF4_x71_TWELOverride_MASK 0x8000 +#define D0F2xF4_x71_CpPrefetchCredits_OFFSET 16 +#define D0F2xF4_x71_CpPrefetchCredits_WIDTH 4 +#define D0F2xF4_x71_CpPrefetchCredits_MASK 0xf0000 +#define D0F2xF4_x71_PprMcifCredits_OFFSET 20 +#define D0F2xF4_x71_PprMcifCredits_WIDTH 4 +#define D0F2xF4_x71_PprMcifCredits_MASK 0xf00000 +#define D0F2xF4_x71_Reserved_31_24_OFFSET 24 +#define D0F2xF4_x71_Reserved_31_24_WIDTH 8 +#define D0F2xF4_x71_Reserved_31_24_MASK 0xff000000 + +/// D0F2xF4_x71 +typedef union { + struct { ///< + UINT32 PDTIECredits:6 ; ///< + UINT32 Reserved_6_6:1 ; ///< + UINT32 PDTIEOverride:1 ; ///< + UINT32 TWELCredits:6 ; ///< + UINT32 Reserved_14_14:1 ; ///< + UINT32 TWELOverride:1 ; ///< + UINT32 CpPrefetchCredits:4 ; ///< + UINT32 PprMcifCredits:4 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x71_STRUCT; + +// **** D0F2xF4_x78 Register Definition **** +// Address +#define D0F2xF4_x78_ADDRESS 0x78 + +// Type +#define D0F2xF4_x78_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x78_MCIFBaseReadCredits_OFFSET 0 +#define D0F2xF4_x78_MCIFBaseReadCredits_WIDTH 5 +#define D0F2xF4_x78_MCIFBaseReadCredits_MASK 0x1f +#define D0F2xF4_x78_Reserved_7_5_OFFSET 5 +#define D0F2xF4_x78_Reserved_7_5_WIDTH 3 +#define D0F2xF4_x78_Reserved_7_5_MASK 0xe0 +#define D0F2xF4_x78_MCIFIsocReadCredits_OFFSET 8 +#define D0F2xF4_x78_MCIFIsocReadCredits_WIDTH 5 +#define D0F2xF4_x78_MCIFIsocReadCredits_MASK 0x1f00 +#define D0F2xF4_x78_Reserved_15_13_OFFSET 13 +#define D0F2xF4_x78_Reserved_15_13_WIDTH 3 +#define D0F2xF4_x78_Reserved_15_13_MASK 0xe000 +#define D0F2xF4_x78_MCIFBaseWriteHdrCredits_OFFSET 16 +#define D0F2xF4_x78_MCIFBaseWriteHdrCredits_WIDTH 5 +#define D0F2xF4_x78_MCIFBaseWriteHdrCredits_MASK 0x1f0000 +#define D0F2xF4_x78_Reserved_23_21_OFFSET 21 +#define D0F2xF4_x78_Reserved_23_21_WIDTH 3 +#define D0F2xF4_x78_Reserved_23_21_MASK 0xe00000 +#define D0F2xF4_x78_MCIFBaseWriteDataCredits_OFFSET 24 +#define D0F2xF4_x78_MCIFBaseWriteDataCredits_WIDTH 5 +#define D0F2xF4_x78_MCIFBaseWriteDataCredits_MASK 0x1f000000 +#define D0F2xF4_x78_Reserved_31_29_OFFSET 29 +#define D0F2xF4_x78_Reserved_31_29_WIDTH 3 +#define D0F2xF4_x78_Reserved_31_29_MASK 0xe0000000 + +/// D0F2xF4_x78 +typedef union { + struct { ///< + UINT32 MCIFBaseReadCredits:5 ; ///< + UINT32 Reserved_7_5:3 ; ///< + UINT32 MCIFIsocReadCredits:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 MCIFBaseWriteHdrCredits:5 ; ///< + UINT32 Reserved_23_21:3 ; ///< + UINT32 MCIFBaseWriteDataCredits:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x78_STRUCT; + + + + + + + +// **** D0F2xF4_x80 Register Definition **** +// Address +#define D0F2xF4_x80_ADDRESS 0x80 + +// Type +#define D0F2xF4_x80_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x80_ERRRuleLock0_OFFSET 0 +#define D0F2xF4_x80_ERRRuleLock0_WIDTH 1 +#define D0F2xF4_x80_ERRRuleLock0_MASK 0x1 +#define D0F2xF4_x80_Reserved_3_1_OFFSET 1 +#define D0F2xF4_x80_Reserved_3_1_WIDTH 3 +#define D0F2xF4_x80_Reserved_3_1_MASK 0xe +#define D0F2xF4_x80_ERRRuleDisable0_OFFSET 4 +#define D0F2xF4_x80_ERRRuleDisable0_WIDTH 28 +#define D0F2xF4_x80_ERRRuleDisable0_MASK 0xfffffff0 + +/// D0F2xF4_x80 +typedef union { + struct { ///< + UINT32 ERRRuleLock0:1 ; ///< + UINT32 Reserved_3_1:3 ; ///< + UINT32 ERRRuleDisable0:28; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x80_STRUCT; + +// **** D0F2xF4_x81 Register Definition **** +// Address +#define D0F2xF4_x81_ADDRESS 0x81 + +// Type +#define D0F2xF4_x81_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x81_ERRRuleDisable1_OFFSET 0 +#define D0F2xF4_x81_ERRRuleDisable1_WIDTH 32 +#define D0F2xF4_x81_ERRRuleDisable1_MASK 0xffffffff + +/// D0F2xF4_x81 +typedef union { + struct { ///< + UINT32 ERRRuleDisable1:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x81_STRUCT; + +// **** D0F2xF4_x82 Register Definition **** +// Address +#define D0F2xF4_x82_ADDRESS 0x82 + +// Type +#define D0F2xF4_x82_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x82_ERRRuleDisable2_OFFSET 0 +#define D0F2xF4_x82_ERRRuleDisable2_WIDTH 32 +#define D0F2xF4_x82_ERRRuleDisable2_MASK 0xffffffff + +/// D0F2xF4_x82 +typedef union { + struct { ///< + UINT32 ERRRuleDisable2:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x82_STRUCT; + +// **** D0F2xF4_x90 Register Definition **** +// Address +#define D0F2xF4_x90_ADDRESS 0x90 + +// Type +#define D0F2xF4_x90_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x90_CKGateL2BRegsDisable_OFFSET 0 +#define D0F2xF4_x90_CKGateL2BRegsDisable_WIDTH 1 +#define D0F2xF4_x90_CKGateL2BRegsDisable_MASK 0x1 +#define D0F2xF4_x90_CKGateL2BDynamicDisable_OFFSET 1 +#define D0F2xF4_x90_CKGateL2BDynamicDisable_WIDTH 1 +#define D0F2xF4_x90_CKGateL2BDynamicDisable_MASK 0x2 +#define D0F2xF4_x90_CKGateL2BMiscDisable_OFFSET 2 +#define D0F2xF4_x90_CKGateL2BMiscDisable_WIDTH 1 +#define D0F2xF4_x90_CKGateL2BMiscDisable_MASK 0x4 +#define D0F2xF4_x90_CKGateL2BCacheDisable_OFFSET 3 +#define D0F2xF4_x90_CKGateL2BCacheDisable_WIDTH 1 +#define D0F2xF4_x90_CKGateL2BCacheDisable_MASK 0x8 +#define D0F2xF4_x90_CKGateL2BLength_OFFSET 4 +#define D0F2xF4_x90_CKGateL2BLength_WIDTH 2 +#define D0F2xF4_x90_CKGateL2BLength_MASK 0x30 +#define D0F2xF4_x90_CKGateL2BStop_OFFSET 6 +#define D0F2xF4_x90_CKGateL2BStop_WIDTH 2 +#define D0F2xF4_x90_CKGateL2BStop_MASK 0xc0 +#define D0F2xF4_x90_Reserved_31_8_OFFSET 8 +#define D0F2xF4_x90_Reserved_31_8_WIDTH 24 +#define D0F2xF4_x90_Reserved_31_8_MASK 0xffffff00 + +/// D0F2xF4_x90 +typedef union { + struct { ///< + UINT32 CKGateL2BRegsDisable:1 ; ///< + UINT32 CKGateL2BDynamicDisable:1 ; ///< + UINT32 CKGateL2BMiscDisable:1 ; ///< + UINT32 CKGateL2BCacheDisable:1 ; ///< + UINT32 CKGateL2BLength:2 ; ///< + UINT32 CKGateL2BStop:2 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x90_STRUCT; + +// **** D0F2xF4_x92 Register Definition **** +// Address +#define D0F2xF4_x92_ADDRESS 0x92 + +// Type +#define D0F2xF4_x92_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x92_PprInttimedelay_OFFSET 0 +#define D0F2xF4_x92_PprInttimedelay_WIDTH 8 +#define D0F2xF4_x92_PprInttimedelay_MASK 0xff +#define D0F2xF4_x92_PprIntreqdelay_OFFSET 8 +#define D0F2xF4_x92_PprIntreqdelay_WIDTH 8 +#define D0F2xF4_x92_PprIntreqdelay_MASK 0xff00 +#define D0F2xF4_x92_PprIntcoallesceEn_OFFSET 16 +#define D0F2xF4_x92_PprIntcoallesceEn_WIDTH 1 +#define D0F2xF4_x92_PprIntcoallesceEn_MASK 0x10000 +#define D0F2xF4_x92_Reserved_31_17_OFFSET 17 +#define D0F2xF4_x92_Reserved_31_17_WIDTH 15 +#define D0F2xF4_x92_Reserved_31_17_MASK 0xfffe0000 + +/// D0F2xF4_x92 +typedef union { + struct { ///< + UINT32 PprInttimedelay:8 ; ///< + UINT32 PprIntreqdelay:8 ; ///< + UINT32 PprIntcoallesceEn:1 ; ///< + UINT32 Reserved_31_17:15; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x92_STRUCT; + +// **** D0F2xF4_x94 Register Definition **** +// Address +#define D0F2xF4_x94_ADDRESS 0x94 + +// Type +#define D0F2xF4_x94_TYPE TYPE_D0F2xF4 +// Field Data +#define D0F2xF4_x94_L2bregGstPgsize_OFFSET 0 +#define D0F2xF4_x94_L2bregGstPgsize_WIDTH 2 +#define D0F2xF4_x94_L2bregGstPgsize_MASK 0x3 +#define D0F2xF4_x94_L2bregHostPgsize_OFFSET 2 +#define D0F2xF4_x94_L2bregHostPgsize_WIDTH 2 +#define D0F2xF4_x94_L2bregHostPgsize_MASK 0xc +#define D0F2xF4_x94_Reserved_31_4_OFFSET 4 +#define D0F2xF4_x94_Reserved_31_4_WIDTH 28 +#define D0F2xF4_x94_Reserved_31_4_MASK 0xfffffff0 + +/// D0F2xF4_x94 +typedef union { + struct { ///< + UINT32 L2bregGstPgsize:2 ; ///< + UINT32 L2bregHostPgsize:2 ; ///< + UINT32 Reserved_31_4:28; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xF4_x94_STRUCT; + +// **** D0F2xFC_x32_L1 Register Definition **** +// Address +#define D0F2xFC_x32_L1_ADDRESS(Sel) ((Sel << 16) | 0x32) + +// Type +#define D0F2xFC_x32_L1_TYPE TYPE_D0F2xFC +// Field Data +#define D0F2xFC_x32_L1_AtsMultipleRespEn_OFFSET 0 +#define D0F2xFC_x32_L1_AtsMultipleRespEn_WIDTH 1 +#define D0F2xFC_x32_L1_AtsMultipleRespEn_MASK 0x1 +#define D0F2xFC_x32_L1_AtsMultipleL1toL2En_OFFSET 1 +#define D0F2xFC_x32_L1_AtsMultipleL1toL2En_WIDTH 1 +#define D0F2xFC_x32_L1_AtsMultipleL1toL2En_MASK 0x2 +#define D0F2xFC_x32_L1_TimeoutPulseExtEn_OFFSET 2 +#define D0F2xFC_x32_L1_TimeoutPulseExtEn_WIDTH 1 +#define D0F2xFC_x32_L1_TimeoutPulseExtEn_MASK 0x4 +#define D0F2xFC_x32_L1_TlpprefixerrEn_OFFSET 3 +#define D0F2xFC_x32_L1_TlpprefixerrEn_WIDTH 1 +#define D0F2xFC_x32_L1_TlpprefixerrEn_MASK 0x8 +#define D0F2xFC_x32_L1_Reserved_31_4_OFFSET 4 +#define D0F2xFC_x32_L1_Reserved_31_4_WIDTH 28 +#define D0F2xFC_x32_L1_Reserved_31_4_MASK 0xfffffff0 + +/// D0F2xFC_x32_L1 +typedef union { + struct { ///< + UINT32 AtsMultipleRespEn:1 ; ///< + UINT32 AtsMultipleL1toL2En:1 ; ///< + UINT32 TimeoutPulseExtEn:1 ; ///< + UINT32 TlpprefixerrEn:1 ; ///< + UINT32 Reserved_31_4:28; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xFC_x32_L1_STRUCT; + +// **** D0F2xFC_x11_L1 Register Definition **** +// Address +#define D0F2xFC_x11_L1_ADDRESS(Sel) ((Sel << 16) | 0x11) + +// Type +#define D0F2xFC_x11_L1_TYPE TYPE_D0F2xFC +// Field Data +#define D0F2xFC_x11_L1_L1cachelinedis0_OFFSET 0 +#define D0F2xFC_x11_L1_L1cachelinedis0_WIDTH 6 +#define D0F2xFC_x11_L1_L1cachelinedis0_MASK 0x3f +#define D0F2xFC_x11_L1_Reserved_7_6_OFFSET 6 +#define D0F2xFC_x11_L1_Reserved_7_6_WIDTH 2 +#define D0F2xFC_x11_L1_Reserved_7_6_MASK 0xc0 +#define D0F2xFC_x11_L1_L1cachelinedis1_OFFSET 8 +#define D0F2xFC_x11_L1_L1cachelinedis1_WIDTH 6 +#define D0F2xFC_x11_L1_L1cachelinedis1_MASK 0x3f00 +#define D0F2xFC_x11_L1_Reserved_31_14_OFFSET 14 +#define D0F2xFC_x11_L1_Reserved_31_14_WIDTH 18 +#define D0F2xFC_x11_L1_Reserved_31_14_MASK 0xffffc000 + +/// D0F2xFC_x11_L1 +typedef union { + struct { ///< + UINT32 L1cachelinedis0:6 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 L1cachelinedis1:6 ; ///< + UINT32 Reserved_31_14:18; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xFC_x11_L1_STRUCT; + +// **** D0F2xFC_x34_L1 Register Definition **** +// Address +#define D0F2xFC_x34_L1_ADDRESS(Sel) ((Sel << 16) | 0x34) + +// Type +#define D0F2xFC_x34_L1_TYPE TYPE_D0F2xFC +// Field Data +#define D0F2xFC_x34_L1_L1MempwrEn_OFFSET 0 +#define D0F2xFC_x34_L1_L1MempwrEn_WIDTH 1 +#define D0F2xFC_x34_L1_L1MempwrEn_MASK 0x1 +#define D0F2xFC_x34_L1_Reserved_7_1_OFFSET 1 +#define D0F2xFC_x34_L1_Reserved_7_1_WIDTH 7 +#define D0F2xFC_x34_L1_Reserved_7_1_MASK 0xfe +#define D0F2xFC_x34_L1_L1MempwrTimer0_OFFSET 8 +#define D0F2xFC_x34_L1_L1MempwrTimer0_WIDTH 8 +#define D0F2xFC_x34_L1_L1MempwrTimer0_MASK 0xff00 +#define D0F2xFC_x34_L1_L1MempwrTimer1_OFFSET 16 +#define D0F2xFC_x34_L1_L1MempwrTimer1_WIDTH 8 +#define D0F2xFC_x34_L1_L1MempwrTimer1_MASK 0xff0000 +#define D0F2xFC_x34_L1_L1MempwrTimer2_OFFSET 24 +#define D0F2xFC_x34_L1_L1MempwrTimer2_WIDTH 8 +#define D0F2xFC_x34_L1_L1MempwrTimer2_MASK 0xff000000 + +/// D0F2xFC_x34_L1 +typedef union { + struct { ///< + UINT32 L1MempwrEn:1 ; ///< + UINT32 Reserved_7_1:7 ; ///< + UINT32 L1MempwrTimer0:8 ; ///< + UINT32 L1MempwrTimer1:8 ; ///< + UINT32 L1MempwrTimer2:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xFC_x34_L1_STRUCT; + +// **** D0F2xFC_x0F_L1 Register Definition **** +// Address +#define D0F2xFC_x0F_L1_ADDRESS(Sel) ((Sel << 16) | 0x0F) + +// Type +#define D0F2xFC_x0F_L1_TYPE TYPE_D0F2xFC +// Field Data +#define D0F2xFC_x0F_L1_AtsTlbinvPulseWidth_OFFSET 0 +#define D0F2xFC_x0F_L1_AtsTlbinvPulseWidth_WIDTH 32 +#define D0F2xFC_x0F_L1_AtsTlbinvPulseWidth_MASK 0xffffffff + +/// D0F2xFC_x0F_L1 +typedef union { + struct { ///< + UINT32 AtsTlbinvPulseWidth:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xFC_x0F_L1_STRUCT; + +// **** D0F2xFC_x0E_L1 Register Definition **** +// Address +#define D0F2xFC_x0E_L1_ADDRESS(Sel) ((Sel << 16) | 0x0E) + +// Type +#define D0F2xFC_x0E_L1_TYPE TYPE_D0F2xFC +// Field Data +#define D0F2xFC_x0E_L1_Reserved_0_0_OFFSET 0 +#define D0F2xFC_x0E_L1_Reserved_0_0_WIDTH 1 +#define D0F2xFC_x0E_L1_Reserved_0_0_MASK 0x1 +#define D0F2xFC_x0E_L1_MsiToHtRemapDis_OFFSET 1 +#define D0F2xFC_x0E_L1_MsiToHtRemapDis_WIDTH 1 +#define D0F2xFC_x0E_L1_MsiToHtRemapDis_MASK 0x2 +#define D0F2xFC_x0E_L1_L1AbrtAtsDis_OFFSET 2 +#define D0F2xFC_x0E_L1_L1AbrtAtsDis_WIDTH 1 +#define D0F2xFC_x0E_L1_L1AbrtAtsDis_MASK 0x4 +#define D0F2xFC_x0E_L1_Reserved_5_3_OFFSET 3 +#define D0F2xFC_x0E_L1_Reserved_5_3_WIDTH 3 +#define D0F2xFC_x0E_L1_Reserved_5_3_MASK 0x38 +#define D0F2xFC_x0E_L1_MsiHtRsvIntMt_OFFSET 6 +#define D0F2xFC_x0E_L1_MsiHtRsvIntMt_WIDTH 3 +#define D0F2xFC_x0E_L1_MsiHtRsvIntMt_MASK 0x1c0 +#define D0F2xFC_x0E_L1_MsiHtRsvIntRqEio_OFFSET 9 +#define D0F2xFC_x0E_L1_MsiHtRsvIntRqEio_WIDTH 1 +#define D0F2xFC_x0E_L1_MsiHtRsvIntRqEio_MASK 0x200 +#define D0F2xFC_x0E_L1_MsiHtRsvIntDM_OFFSET 10 +#define D0F2xFC_x0E_L1_MsiHtRsvIntDM_WIDTH 1 +#define D0F2xFC_x0E_L1_MsiHtRsvIntDM_MASK 0x400 +#define D0F2xFC_x0E_L1_Reserved_11_11_OFFSET 11 +#define D0F2xFC_x0E_L1_Reserved_11_11_WIDTH 1 +#define D0F2xFC_x0E_L1_Reserved_11_11_MASK 0x800 +#define D0F2xFC_x0E_L1_MsiHtRsvIntDestination_OFFSET 12 +#define D0F2xFC_x0E_L1_MsiHtRsvIntDestination_WIDTH 8 +#define D0F2xFC_x0E_L1_MsiHtRsvIntDestination_MASK 0xff000 +#define D0F2xFC_x0E_L1_MsiHtRsvIntVector_OFFSET 20 +#define D0F2xFC_x0E_L1_MsiHtRsvIntVector_WIDTH 8 +#define D0F2xFC_x0E_L1_MsiHtRsvIntVector_MASK 0xff00000 +#define D0F2xFC_x0E_L1_Reserved_31_28_OFFSET 28 +#define D0F2xFC_x0E_L1_Reserved_31_28_WIDTH 4 +#define D0F2xFC_x0E_L1_Reserved_31_28_MASK 0xf0000000 + +/// D0F2xFC_x0E_L1 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 MsiToHtRemapDis:1 ; ///< + UINT32 L1AbrtAtsDis:1 ; ///< + UINT32 Reserved_5_3:3 ; ///< + UINT32 MsiHtRsvIntMt:3 ; ///< + UINT32 MsiHtRsvIntRqEio:1 ; ///< + UINT32 MsiHtRsvIntDM:1 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 MsiHtRsvIntDestination:8 ; ///< + UINT32 MsiHtRsvIntVector:8 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xFC_x0E_L1_STRUCT; + + +// **** D0F2xFC_x37_L1 Register Definition **** +// Address +#define D0F2xFC_x37_L1_ADDRESS(Sel) ((Sel << 16) | 0x37) + +// Type +#define D0F2xFC_x37_L1_TYPE TYPE_D0F2xFC +// Field Data +#define D0F2xFC_x37_L1_L1EfrSup_OFFSET 0 +#define D0F2xFC_x37_L1_L1EfrSup_WIDTH 1 +#define D0F2xFC_x37_L1_L1EfrSup_MASK 0x1 +#define D0F2xFC_x37_L1_L1PprSup_OFFSET 1 +#define D0F2xFC_x37_L1_L1PprSup_WIDTH 1 +#define D0F2xFC_x37_L1_L1PprSup_MASK 0x2 +#define D0F2xFC_x37_L1_Reserved_31_2_OFFSET 2 +#define D0F2xFC_x37_L1_Reserved_31_2_WIDTH 30 +#define D0F2xFC_x37_L1_Reserved_31_2_MASK 0xfffffffc + +/// D0F2xFC_x37_L1 +typedef union { + struct { ///< + UINT32 L1EfrSup:1 ; ///< + UINT32 L1PprSup:1 ; ///< + UINT32 Reserved_31_2:30; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xFC_x37_L1_STRUCT; + + +// **** D0F2xFC_x20_L1 Register Definition **** +// Address +#define D0F2xFC_x20_L1_ADDRESS(Sel) ((Sel << 16) | 0x20) + +// Type +#define D0F2xFC_x20_L1_TYPE TYPE_D0F2xFC +// Field Data +#define D0F2xFC_x20_L1_EntryStatus0_OFFSET 0 +#define D0F2xFC_x20_L1_EntryStatus0_WIDTH 3 +#define D0F2xFC_x20_L1_EntryStatus0_MASK 0x7 +#define D0F2xFC_x20_L1_EntryStatus1_OFFSET 3 +#define D0F2xFC_x20_L1_EntryStatus1_WIDTH 3 +#define D0F2xFC_x20_L1_EntryStatus1_MASK 0x38 +#define D0F2xFC_x20_L1_EntryStatus2_OFFSET 6 +#define D0F2xFC_x20_L1_EntryStatus2_WIDTH 3 +#define D0F2xFC_x20_L1_EntryStatus2_MASK 0x1c0 +#define D0F2xFC_x20_L1_EntryStatus3_OFFSET 9 +#define D0F2xFC_x20_L1_EntryStatus3_WIDTH 3 +#define D0F2xFC_x20_L1_EntryStatus3_MASK 0xe00 +#define D0F2xFC_x20_L1_EntryStatus4_OFFSET 12 +#define D0F2xFC_x20_L1_EntryStatus4_WIDTH 3 +#define D0F2xFC_x20_L1_EntryStatus4_MASK 0x7000 +#define D0F2xFC_x20_L1_EntryStatus5_OFFSET 15 +#define D0F2xFC_x20_L1_EntryStatus5_WIDTH 3 +#define D0F2xFC_x20_L1_EntryStatus5_MASK 0x38000 +#define D0F2xFC_x20_L1_EntryStatus6_OFFSET 18 +#define D0F2xFC_x20_L1_EntryStatus6_WIDTH 3 +#define D0F2xFC_x20_L1_EntryStatus6_MASK 0x1c0000 +#define D0F2xFC_x20_L1_EntryStatus7_OFFSET 21 +#define D0F2xFC_x20_L1_EntryStatus7_WIDTH 3 +#define D0F2xFC_x20_L1_EntryStatus7_MASK 0xe00000 +#define D0F2xFC_x20_L1_EntryStatus8_OFFSET 24 +#define D0F2xFC_x20_L1_EntryStatus8_WIDTH 3 +#define D0F2xFC_x20_L1_EntryStatus8_MASK 0x7000000 +#define D0F2xFC_x20_L1_EntryStatus9_OFFSET 27 +#define D0F2xFC_x20_L1_EntryStatus9_WIDTH 3 +#define D0F2xFC_x20_L1_EntryStatus9_MASK 0x38000000 +#define D0F2xFC_x20_L1_Reserved_31_30_OFFSET 30 +#define D0F2xFC_x20_L1_Reserved_31_30_WIDTH 2 +#define D0F2xFC_x20_L1_Reserved_31_30_MASK 0xc0000000 + +/// D0F2xFC_x20_L1 +typedef union { + struct { ///< + UINT32 EntryStatus0:3 ; ///< + UINT32 EntryStatus1:3 ; ///< + UINT32 EntryStatus2:3 ; ///< + UINT32 EntryStatus3:3 ; ///< + UINT32 EntryStatus4:3 ; ///< + UINT32 EntryStatus5:3 ; ///< + UINT32 EntryStatus6:3 ; ///< + UINT32 EntryStatus7:3 ; ///< + UINT32 EntryStatus8:3 ; ///< + UINT32 EntryStatus9:3 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xFC_x20_L1_STRUCT; + +// **** D0F2xFC_x35_L1 Register Definition **** +// Address +#define D0F2xFC_x35_L1_ADDRESS(Sel) ((Sel << 16) | 0x35) + +// Type +#define D0F2xFC_x35_L1_TYPE TYPE_D0F2xFC +// Field Data +#define D0F2xFC_x35_L1_L1MempwrTimer3_OFFSET 0 +#define D0F2xFC_x35_L1_L1MempwrTimer3_WIDTH 8 +#define D0F2xFC_x35_L1_L1MempwrTimer3_MASK 0xff +#define D0F2xFC_x35_L1_Reserved_31_8_OFFSET 8 +#define D0F2xFC_x35_L1_Reserved_31_8_WIDTH 24 +#define D0F2xFC_x35_L1_Reserved_31_8_MASK 0xffffff00 + +/// D0F2xFC_x35_L1 +typedef union { + struct { ///< + UINT32 L1MempwrTimer3:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xFC_x35_L1_STRUCT; + + +// **** D0F2xFC_x0C_L1 Register Definition **** +// Address +#define D0F2xFC_x0C_L1_ADDRESS(Sel) ((Sel << 16) | 0x0C) + +// Type +#define D0F2xFC_x0C_L1_TYPE TYPE_D0F2xFC +// Field Data +#define D0F2xFC_x0C_L1_UnfilterDis_OFFSET 0 +#define D0F2xFC_x0C_L1_UnfilterDis_WIDTH 1 +#define D0F2xFC_x0C_L1_UnfilterDis_MASK 0x1 +#define D0F2xFC_x0C_L1_FragmentDis_OFFSET 1 +#define D0F2xFC_x0C_L1_FragmentDis_WIDTH 1 +#define D0F2xFC_x0C_L1_FragmentDis_MASK 0x2 +#define D0F2xFC_x0C_L1_CacheirOnly_OFFSET 2 +#define D0F2xFC_x0C_L1_CacheirOnly_WIDTH 1 +#define D0F2xFC_x0C_L1_CacheirOnly_MASK 0x4 +#define D0F2xFC_x0C_L1_CacheiwOnly_OFFSET 3 +#define D0F2xFC_x0C_L1_CacheiwOnly_WIDTH 1 +#define D0F2xFC_x0C_L1_CacheiwOnly_MASK 0x8 +#define D0F2xFC_x0C_L1_Reserved0_OFFSET 4 +#define D0F2xFC_x0C_L1_Reserved0_WIDTH 1 +#define D0F2xFC_x0C_L1_Reserved0_MASK 0x10 +#define D0F2xFC_x0C_L1_ReplacementSel_OFFSET 5 +#define D0F2xFC_x0C_L1_ReplacementSel_WIDTH 1 +#define D0F2xFC_x0C_L1_ReplacementSel_MASK 0x20 +#define D0F2xFC_x0C_L1_Reserved_7_6_OFFSET 6 +#define D0F2xFC_x0C_L1_Reserved_7_6_WIDTH 2 +#define D0F2xFC_x0C_L1_Reserved_7_6_MASK 0xc0 +#define D0F2xFC_x0C_L1_L2Credits_OFFSET 8 +#define D0F2xFC_x0C_L1_L2Credits_WIDTH 6 +#define D0F2xFC_x0C_L1_L2Credits_MASK 0x3f00 +#define D0F2xFC_x0C_L1_Reserved1_OFFSET 14 +#define D0F2xFC_x0C_L1_Reserved1_WIDTH 6 +#define D0F2xFC_x0C_L1_Reserved1_MASK 0xfc000 +#define D0F2xFC_x0C_L1_L1Banks_OFFSET 20 +#define D0F2xFC_x0C_L1_L1Banks_WIDTH 2 +#define D0F2xFC_x0C_L1_L1Banks_MASK 0x300000 +#define D0F2xFC_x0C_L1_Reserved_23_22_OFFSET 22 +#define D0F2xFC_x0C_L1_Reserved_23_22_WIDTH 2 +#define D0F2xFC_x0C_L1_Reserved_23_22_MASK 0xc00000 +#define D0F2xFC_x0C_L1_L1Entries_OFFSET 24 +#define D0F2xFC_x0C_L1_L1Entries_WIDTH 4 +#define D0F2xFC_x0C_L1_L1Entries_MASK 0xf000000 +#define D0F2xFC_x0C_L1_L1VirtOrderQueues_OFFSET 28 +#define D0F2xFC_x0C_L1_L1VirtOrderQueues_WIDTH 3 +#define D0F2xFC_x0C_L1_L1VirtOrderQueues_MASK 0x70000000 +#define D0F2xFC_x0C_L1_Reserved_31_31_OFFSET 31 +#define D0F2xFC_x0C_L1_Reserved_31_31_WIDTH 1 +#define D0F2xFC_x0C_L1_Reserved_31_31_MASK 0x80000000 + +/// D0F2xFC_x0C_L1 +typedef union { + struct { ///< + UINT32 UnfilterDis:1 ; ///< + UINT32 FragmentDis:1 ; ///< + UINT32 CacheirOnly:1 ; ///< + UINT32 CacheiwOnly:1 ; ///< + UINT32 Reserved0:1 ; ///< + UINT32 ReplacementSel:1 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 L2Credits:6 ; ///< + UINT32 Reserved1:6 ; ///< + UINT32 L1Banks:2 ; ///< + UINT32 Reserved_23_22:2 ; ///< + UINT32 L1Entries:4 ; ///< + UINT32 L1VirtOrderQueues:3 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xFC_x0C_L1_STRUCT; + + +// **** D0F2xFC_x08_L1 Register Definition **** +// Address +#define D0F2xFC_x08_L1_ADDRESS(Sel) ((Sel << 16) | 0x08) + +// Type +#define D0F2xFC_x08_L1_TYPE TYPE_D0F2xFC +// Field Data +#define D0F2xFC_x08_L1_L1debugStatus_OFFSET 0 +#define D0F2xFC_x08_L1_L1debugStatus_WIDTH 32 +#define D0F2xFC_x08_L1_L1debugStatus_MASK 0xffffffff + +/// D0F2xFC_x08_L1 +typedef union { + struct { ///< + UINT32 L1debugStatus:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xFC_x08_L1_STRUCT; + + +// **** D0F2xFC_x10_L1 Register Definition **** +// Address +#define D0F2xFC_x10_L1_ADDRESS(Sel) ((Sel << 16) | 0x10) + +// Type +#define D0F2xFC_x10_L1_TYPE TYPE_D0F2xFC +// Field Data +#define D0F2xFC_x10_L1_L1cachebanksel0_OFFSET 0 +#define D0F2xFC_x10_L1_L1cachebanksel0_WIDTH 16 +#define D0F2xFC_x10_L1_L1cachebanksel0_MASK 0xffff +#define D0F2xFC_x10_L1_Reserved_31_16_OFFSET 16 +#define D0F2xFC_x10_L1_Reserved_31_16_WIDTH 16 +#define D0F2xFC_x10_L1_Reserved_31_16_MASK 0xffff0000 + +/// D0F2xFC_x10_L1 +typedef union { + struct { ///< + UINT32 L1cachebanksel0:16; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xFC_x10_L1_STRUCT; + +// **** D0F2xFC_x23_L1 Register Definition **** +// Address +#define D0F2xFC_x23_L1_ADDRESS(Sel) ((Sel << 16) | 0x23) + +// Type +#define D0F2xFC_x23_L1_TYPE TYPE_D0F2xFC +// Field Data +#define D0F2xFC_x23_L1_EntryStatus30_OFFSET 0 +#define D0F2xFC_x23_L1_EntryStatus30_WIDTH 3 +#define D0F2xFC_x23_L1_EntryStatus30_MASK 0x7 +#define D0F2xFC_x23_L1_EntryStatus31_OFFSET 3 +#define D0F2xFC_x23_L1_EntryStatus31_WIDTH 3 +#define D0F2xFC_x23_L1_EntryStatus31_MASK 0x38 +#define D0F2xFC_x23_L1_Reserved_7_6_OFFSET 6 +#define D0F2xFC_x23_L1_Reserved_7_6_WIDTH 2 +#define D0F2xFC_x23_L1_Reserved_7_6_MASK 0xc0 +#define D0F2xFC_x23_L1_InvalidationStatus_OFFSET 8 +#define D0F2xFC_x23_L1_InvalidationStatus_WIDTH 8 +#define D0F2xFC_x23_L1_InvalidationStatus_MASK 0xff00 +#define D0F2xFC_x23_L1_Reserved_31_16_OFFSET 16 +#define D0F2xFC_x23_L1_Reserved_31_16_WIDTH 16 +#define D0F2xFC_x23_L1_Reserved_31_16_MASK 0xffff0000 + +/// D0F2xFC_x23_L1 +typedef union { + struct { ///< + UINT32 EntryStatus30:3 ; ///< + UINT32 EntryStatus31:3 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 InvalidationStatus:8 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xFC_x23_L1_STRUCT; + +// **** D0F2xFC_x22_L1 Register Definition **** +// Address +#define D0F2xFC_x22_L1_ADDRESS(Sel) ((Sel << 16) | 0x22) + +// Type +#define D0F2xFC_x22_L1_TYPE TYPE_D0F2xFC +// Field Data +#define D0F2xFC_x22_L1_EntryStatus20_OFFSET 0 +#define D0F2xFC_x22_L1_EntryStatus20_WIDTH 3 +#define D0F2xFC_x22_L1_EntryStatus20_MASK 0x7 +#define D0F2xFC_x22_L1_EntryStatus21_OFFSET 3 +#define D0F2xFC_x22_L1_EntryStatus21_WIDTH 3 +#define D0F2xFC_x22_L1_EntryStatus21_MASK 0x38 +#define D0F2xFC_x22_L1_EntryStatus22_OFFSET 6 +#define D0F2xFC_x22_L1_EntryStatus22_WIDTH 3 +#define D0F2xFC_x22_L1_EntryStatus22_MASK 0x1c0 +#define D0F2xFC_x22_L1_EntryStatus23_OFFSET 9 +#define D0F2xFC_x22_L1_EntryStatus23_WIDTH 3 +#define D0F2xFC_x22_L1_EntryStatus23_MASK 0xe00 +#define D0F2xFC_x22_L1_EntryStatus24_OFFSET 12 +#define D0F2xFC_x22_L1_EntryStatus24_WIDTH 3 +#define D0F2xFC_x22_L1_EntryStatus24_MASK 0x7000 +#define D0F2xFC_x22_L1_EntryStatus25_OFFSET 15 +#define D0F2xFC_x22_L1_EntryStatus25_WIDTH 3 +#define D0F2xFC_x22_L1_EntryStatus25_MASK 0x38000 +#define D0F2xFC_x22_L1_EntryStatus26_OFFSET 18 +#define D0F2xFC_x22_L1_EntryStatus26_WIDTH 3 +#define D0F2xFC_x22_L1_EntryStatus26_MASK 0x1c0000 +#define D0F2xFC_x22_L1_EntryStatus27_OFFSET 21 +#define D0F2xFC_x22_L1_EntryStatus27_WIDTH 3 +#define D0F2xFC_x22_L1_EntryStatus27_MASK 0xe00000 +#define D0F2xFC_x22_L1_EntryStatus28_OFFSET 24 +#define D0F2xFC_x22_L1_EntryStatus28_WIDTH 3 +#define D0F2xFC_x22_L1_EntryStatus28_MASK 0x7000000 +#define D0F2xFC_x22_L1_EntryStatus29_OFFSET 27 +#define D0F2xFC_x22_L1_EntryStatus29_WIDTH 3 +#define D0F2xFC_x22_L1_EntryStatus29_MASK 0x38000000 +#define D0F2xFC_x22_L1_Reserved_31_30_OFFSET 30 +#define D0F2xFC_x22_L1_Reserved_31_30_WIDTH 2 +#define D0F2xFC_x22_L1_Reserved_31_30_MASK 0xc0000000 + +/// D0F2xFC_x22_L1 +typedef union { + struct { ///< + UINT32 EntryStatus20:3 ; ///< + UINT32 EntryStatus21:3 ; ///< + UINT32 EntryStatus22:3 ; ///< + UINT32 EntryStatus23:3 ; ///< + UINT32 EntryStatus24:3 ; ///< + UINT32 EntryStatus25:3 ; ///< + UINT32 EntryStatus26:3 ; ///< + UINT32 EntryStatus27:3 ; ///< + UINT32 EntryStatus28:3 ; ///< + UINT32 EntryStatus29:3 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xFC_x22_L1_STRUCT; + +// **** D0F2xFC_x01_L1 Register Definition **** +// Address +#define D0F2xFC_x01_L1_ADDRESS(Sel) ((Sel << 16) | 0x01) + +// Type +#define D0F2xFC_x01_L1_TYPE TYPE_D0F2xFC +// Field Data +#define D0F2xFC_x01_L1_L1PerfCount0_OFFSET 0 +#define D0F2xFC_x01_L1_L1PerfCount0_WIDTH 32 +#define D0F2xFC_x01_L1_L1PerfCount0_MASK 0xffffffff + +/// D0F2xFC_x01_L1 +typedef union { + struct { ///< + UINT32 L1PerfCount0:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xFC_x01_L1_STRUCT; + +// **** D0F2xFC_x36_L1 Register Definition **** +// Address +#define D0F2xFC_x36_L1_ADDRESS(Sel) ((Sel << 16) | 0x36) + +// Type +#define D0F2xFC_x36_L1_TYPE TYPE_D0F2xFC +// Field Data +#define D0F2xFC_x36_L1_L1CanonicalErrEn_OFFSET 0 +#define D0F2xFC_x36_L1_L1CanonicalErrEn_WIDTH 1 +#define D0F2xFC_x36_L1_L1CanonicalErrEn_MASK 0x1 +#define D0F2xFC_x36_L1_Reserved_7_1_OFFSET 1 +#define D0F2xFC_x36_L1_Reserved_7_1_WIDTH 7 +#define D0F2xFC_x36_L1_Reserved_7_1_MASK 0xfe +#define D0F2xFC_x36_L1_L1GuestAddrMsk_OFFSET 8 +#define D0F2xFC_x36_L1_L1GuestAddrMsk_WIDTH 24 +#define D0F2xFC_x36_L1_L1GuestAddrMsk_MASK 0xffffff00 + +/// D0F2xFC_x36_L1 +typedef union { + struct { ///< + UINT32 L1CanonicalErrEn:1 ; ///< + UINT32 Reserved_7_1:7 ; ///< + UINT32 L1GuestAddrMsk:24; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xFC_x36_L1_STRUCT; + +// **** D0F2xFC_x0D_L1 Register Definition **** +// Address +#define D0F2xFC_x0D_L1_ADDRESS(Sel) ((Sel << 16) | 0x0D) + +// Type +#define D0F2xFC_x0D_L1_TYPE TYPE_D0F2xFC +// Field Data +#define D0F2xFC_x0D_L1_VOQPortBits_OFFSET 0 +#define D0F2xFC_x0D_L1_VOQPortBits_WIDTH 3 +#define D0F2xFC_x0D_L1_VOQPortBits_MASK 0x7 +#define D0F2xFC_x0D_L1_Reserved_3_3_OFFSET 3 +#define D0F2xFC_x0D_L1_Reserved_3_3_WIDTH 1 +#define D0F2xFC_x0D_L1_Reserved_3_3_MASK 0x8 +#define D0F2xFC_x0D_L1_VOQFuncBits_OFFSET 4 +#define D0F2xFC_x0D_L1_VOQFuncBits_WIDTH 3 +#define D0F2xFC_x0D_L1_VOQFuncBits_MASK 0x70 +#define D0F2xFC_x0D_L1_Reserved_7_7_OFFSET 7 +#define D0F2xFC_x0D_L1_Reserved_7_7_WIDTH 1 +#define D0F2xFC_x0D_L1_Reserved_7_7_MASK 0x80 +#define D0F2xFC_x0D_L1_VOQXorMode_OFFSET 8 +#define D0F2xFC_x0D_L1_VOQXorMode_WIDTH 1 +#define D0F2xFC_x0D_L1_VOQXorMode_MASK 0x100 +#define D0F2xFC_x0D_L1_CacheByPass_OFFSET 9 +#define D0F2xFC_x0D_L1_CacheByPass_WIDTH 1 +#define D0F2xFC_x0D_L1_CacheByPass_MASK 0x200 +#define D0F2xFC_x0D_L1_L1CacheParityEn_OFFSET 10 +#define D0F2xFC_x0D_L1_L1CacheParityEn_WIDTH 1 +#define D0F2xFC_x0D_L1_L1CacheParityEn_MASK 0x400 +#define D0F2xFC_x0D_L1_L1ParityEn_OFFSET 11 +#define D0F2xFC_x0D_L1_L1ParityEn_WIDTH 1 +#define D0F2xFC_x0D_L1_L1ParityEn_MASK 0x800 +#define D0F2xFC_x0D_L1_L1DTEDis_OFFSET 12 +#define D0F2xFC_x0D_L1_L1DTEDis_WIDTH 1 +#define D0F2xFC_x0D_L1_L1DTEDis_MASK 0x1000 +#define D0F2xFC_x0D_L1_BlockL1Dis_OFFSET 13 +#define D0F2xFC_x0D_L1_BlockL1Dis_WIDTH 1 +#define D0F2xFC_x0D_L1_BlockL1Dis_MASK 0x2000 +#define D0F2xFC_x0D_L1_WqEntrydis_OFFSET 14 +#define D0F2xFC_x0D_L1_WqEntrydis_WIDTH 5 +#define D0F2xFC_x0D_L1_WqEntrydis_MASK 0x7c000 +#define D0F2xFC_x0D_L1_AtsNobufferInsert_OFFSET 19 +#define D0F2xFC_x0D_L1_AtsNobufferInsert_WIDTH 1 +#define D0F2xFC_x0D_L1_AtsNobufferInsert_MASK 0x80000 +#define D0F2xFC_x0D_L1_SndFilterDis_OFFSET 20 +#define D0F2xFC_x0D_L1_SndFilterDis_WIDTH 1 +#define D0F2xFC_x0D_L1_SndFilterDis_MASK 0x100000 +#define D0F2xFC_x0D_L1_L1orderEn_OFFSET 21 +#define D0F2xFC_x0D_L1_L1orderEn_WIDTH 1 +#define D0F2xFC_x0D_L1_L1orderEn_MASK 0x200000 +#define D0F2xFC_x0D_L1_L1CacheInvAllEn_OFFSET 22 +#define D0F2xFC_x0D_L1_L1CacheInvAllEn_WIDTH 1 +#define D0F2xFC_x0D_L1_L1CacheInvAllEn_MASK 0x400000 +#define D0F2xFC_x0D_L1_SelectTimeoutPulse_OFFSET 23 +#define D0F2xFC_x0D_L1_SelectTimeoutPulse_WIDTH 3 +#define D0F2xFC_x0D_L1_SelectTimeoutPulse_MASK 0x3800000 +#define D0F2xFC_x0D_L1_L1CacheSelReqid_OFFSET 26 +#define D0F2xFC_x0D_L1_L1CacheSelReqid_WIDTH 1 +#define D0F2xFC_x0D_L1_L1CacheSelReqid_MASK 0x4000000 +#define D0F2xFC_x0D_L1_L1CacheSelInterleave_OFFSET 27 +#define D0F2xFC_x0D_L1_L1CacheSelInterleave_WIDTH 1 +#define D0F2xFC_x0D_L1_L1CacheSelInterleave_MASK 0x8000000 +#define D0F2xFC_x0D_L1_PretransNovaFilteren_OFFSET 28 +#define D0F2xFC_x0D_L1_PretransNovaFilteren_WIDTH 1 +#define D0F2xFC_x0D_L1_PretransNovaFilteren_MASK 0x10000000 +#define D0F2xFC_x0D_L1_Untrans2mFilteren_OFFSET 29 +#define D0F2xFC_x0D_L1_Untrans2mFilteren_WIDTH 1 +#define D0F2xFC_x0D_L1_Untrans2mFilteren_MASK 0x20000000 +#define D0F2xFC_x0D_L1_L1DebugCntrMode_OFFSET 30 +#define D0F2xFC_x0D_L1_L1DebugCntrMode_WIDTH 1 +#define D0F2xFC_x0D_L1_L1DebugCntrMode_MASK 0x40000000 +#define D0F2xFC_x0D_L1_Reserved_31_31_OFFSET 31 +#define D0F2xFC_x0D_L1_Reserved_31_31_WIDTH 1 +#define D0F2xFC_x0D_L1_Reserved_31_31_MASK 0x80000000 + +/// D0F2xFC_x0D_L1 +typedef union { + struct { ///< + UINT32 VOQPortBits:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 VOQFuncBits:3 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 VOQXorMode:1 ; ///< + UINT32 CacheByPass:1 ; ///< + UINT32 L1CacheParityEn:1 ; ///< + UINT32 L1ParityEn:1 ; ///< + UINT32 L1DTEDis:1 ; ///< + UINT32 BlockL1Dis:1 ; ///< + UINT32 WqEntrydis:5 ; ///< + UINT32 AtsNobufferInsert:1 ; ///< + UINT32 SndFilterDis:1 ; ///< + UINT32 L1orderEn:1 ; ///< + UINT32 L1CacheInvAllEn:1 ; ///< + UINT32 SelectTimeoutPulse:3 ; ///< + UINT32 L1CacheSelReqid:1 ; ///< + UINT32 L1CacheSelInterleave:1 ; ///< + UINT32 PretransNovaFilteren:1 ; ///< + UINT32 Untrans2mFilteren:1 ; ///< + UINT32 L1DebugCntrMode:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xFC_x0D_L1_STRUCT; + +// **** D0F2xFC_x33_L1 Register Definition **** +// Address +#define D0F2xFC_x33_L1_ADDRESS(Sel) ((Sel << 16) | 0x33) + +// Type +#define D0F2xFC_x33_L1_TYPE TYPE_D0F2xFC +// Field Data +#define D0F2xFC_x33_L1_L1ClkgateLen_OFFSET 0 +#define D0F2xFC_x33_L1_L1ClkgateLen_WIDTH 2 +#define D0F2xFC_x33_L1_L1ClkgateLen_MASK 0x3 +#define D0F2xFC_x33_L1_Reserved_3_2_OFFSET 2 +#define D0F2xFC_x33_L1_Reserved_3_2_WIDTH 2 +#define D0F2xFC_x33_L1_Reserved_3_2_MASK 0xc +#define D0F2xFC_x33_L1_L1DmaClkgateEn_OFFSET 4 +#define D0F2xFC_x33_L1_L1DmaClkgateEn_WIDTH 1 +#define D0F2xFC_x33_L1_L1DmaClkgateEn_MASK 0x10 +#define D0F2xFC_x33_L1_L1CacheClkgateEn_OFFSET 5 +#define D0F2xFC_x33_L1_L1CacheClkgateEn_WIDTH 1 +#define D0F2xFC_x33_L1_L1CacheClkgateEn_MASK 0x20 +#define D0F2xFC_x33_L1_L1CpslvClkgateEn_OFFSET 6 +#define D0F2xFC_x33_L1_L1CpslvClkgateEn_WIDTH 1 +#define D0F2xFC_x33_L1_L1CpslvClkgateEn_MASK 0x40 +#define D0F2xFC_x33_L1_L1DmaInputClkgateEn_OFFSET 7 +#define D0F2xFC_x33_L1_L1DmaInputClkgateEn_WIDTH 1 +#define D0F2xFC_x33_L1_L1DmaInputClkgateEn_MASK 0x80 +#define D0F2xFC_x33_L1_L1PerfClkgateEn_OFFSET 8 +#define D0F2xFC_x33_L1_L1PerfClkgateEn_WIDTH 1 +#define D0F2xFC_x33_L1_L1PerfClkgateEn_MASK 0x100 +#define D0F2xFC_x33_L1_L1MemoryClkgateEn_OFFSET 9 +#define D0F2xFC_x33_L1_L1MemoryClkgateEn_WIDTH 1 +#define D0F2xFC_x33_L1_L1MemoryClkgateEn_MASK 0x200 +#define D0F2xFC_x33_L1_L1RegClkgateEn_OFFSET 10 +#define D0F2xFC_x33_L1_L1RegClkgateEn_WIDTH 1 +#define D0F2xFC_x33_L1_L1RegClkgateEn_MASK 0x400 +#define D0F2xFC_x33_L1_L1HostreqClkgateEn_OFFSET 11 +#define D0F2xFC_x33_L1_L1HostreqClkgateEn_WIDTH 1 +#define D0F2xFC_x33_L1_L1HostreqClkgateEn_MASK 0x800 +#define D0F2xFC_x33_L1_Reserved_30_12_OFFSET 12 +#define D0F2xFC_x33_L1_Reserved_30_12_WIDTH 19 +#define D0F2xFC_x33_L1_Reserved_30_12_MASK 0x7ffff000 +#define D0F2xFC_x33_L1_L1L2ClkgateEn_OFFSET 31 +#define D0F2xFC_x33_L1_L1L2ClkgateEn_WIDTH 1 +#define D0F2xFC_x33_L1_L1L2ClkgateEn_MASK 0x80000000 + +/// D0F2xFC_x33_L1 +typedef union { + struct { ///< + UINT32 L1ClkgateLen:2 ; ///< + UINT32 Reserved_3_2:2 ; ///< + UINT32 L1DmaClkgateEn:1 ; ///< + UINT32 L1CacheClkgateEn:1 ; ///< + UINT32 L1CpslvClkgateEn:1 ; ///< + UINT32 L1DmaInputClkgateEn:1 ; ///< + UINT32 L1PerfClkgateEn:1 ; ///< + UINT32 L1MemoryClkgateEn:1 ; ///< + UINT32 L1RegClkgateEn:1 ; ///< + UINT32 L1HostreqClkgateEn:1 ; ///< + UINT32 Reserved_30_12:19; ///< + UINT32 L1L2ClkgateEn:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xFC_x33_L1_STRUCT; + + +// **** D0F2xFC_x21_L1 Register Definition **** +// Address +#define D0F2xFC_x21_L1_ADDRESS(Sel) ((Sel << 16) | 0x21) + +// Type +#define D0F2xFC_x21_L1_TYPE TYPE_D0F2xFC +// Field Data +#define D0F2xFC_x21_L1_EntryStatus10_OFFSET 0 +#define D0F2xFC_x21_L1_EntryStatus10_WIDTH 3 +#define D0F2xFC_x21_L1_EntryStatus10_MASK 0x7 +#define D0F2xFC_x21_L1_EntryStatus11_OFFSET 3 +#define D0F2xFC_x21_L1_EntryStatus11_WIDTH 3 +#define D0F2xFC_x21_L1_EntryStatus11_MASK 0x38 +#define D0F2xFC_x21_L1_EntryStatus12_OFFSET 6 +#define D0F2xFC_x21_L1_EntryStatus12_WIDTH 3 +#define D0F2xFC_x21_L1_EntryStatus12_MASK 0x1c0 +#define D0F2xFC_x21_L1_EntryStatus13_OFFSET 9 +#define D0F2xFC_x21_L1_EntryStatus13_WIDTH 3 +#define D0F2xFC_x21_L1_EntryStatus13_MASK 0xe00 +#define D0F2xFC_x21_L1_EntryStatus14_OFFSET 12 +#define D0F2xFC_x21_L1_EntryStatus14_WIDTH 3 +#define D0F2xFC_x21_L1_EntryStatus14_MASK 0x7000 +#define D0F2xFC_x21_L1_EntryStatus15_OFFSET 15 +#define D0F2xFC_x21_L1_EntryStatus15_WIDTH 3 +#define D0F2xFC_x21_L1_EntryStatus15_MASK 0x38000 +#define D0F2xFC_x21_L1_EntryStatus16_OFFSET 18 +#define D0F2xFC_x21_L1_EntryStatus16_WIDTH 3 +#define D0F2xFC_x21_L1_EntryStatus16_MASK 0x1c0000 +#define D0F2xFC_x21_L1_EntryStatus17_OFFSET 21 +#define D0F2xFC_x21_L1_EntryStatus17_WIDTH 3 +#define D0F2xFC_x21_L1_EntryStatus17_MASK 0xe00000 +#define D0F2xFC_x21_L1_EntryStatus18_OFFSET 24 +#define D0F2xFC_x21_L1_EntryStatus18_WIDTH 3 +#define D0F2xFC_x21_L1_EntryStatus18_MASK 0x7000000 +#define D0F2xFC_x21_L1_EntryStatus19_OFFSET 27 +#define D0F2xFC_x21_L1_EntryStatus19_WIDTH 3 +#define D0F2xFC_x21_L1_EntryStatus19_MASK 0x38000000 +#define D0F2xFC_x21_L1_Reserved_31_30_OFFSET 30 +#define D0F2xFC_x21_L1_Reserved_31_30_WIDTH 2 +#define D0F2xFC_x21_L1_Reserved_31_30_MASK 0xc0000000 + +/// D0F2xFC_x21_L1 +typedef union { + struct { ///< + UINT32 EntryStatus10:3 ; ///< + UINT32 EntryStatus11:3 ; ///< + UINT32 EntryStatus12:3 ; ///< + UINT32 EntryStatus13:3 ; ///< + UINT32 EntryStatus14:3 ; ///< + UINT32 EntryStatus15:3 ; ///< + UINT32 EntryStatus16:3 ; ///< + UINT32 EntryStatus17:3 ; ///< + UINT32 EntryStatus18:3 ; ///< + UINT32 EntryStatus19:3 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xFC_x21_L1_STRUCT; + +// **** D0F2xFC_x00_L1 Register Definition **** +// Address +#define D0F2xFC_x00_L1_ADDRESS(Sel) ((Sel << 16) | 0x00) + +// Type +#define D0F2xFC_x00_L1_TYPE TYPE_D0F2xFC +// Field Data +#define D0F2xFC_x00_L1_L1PerfEvent0_OFFSET 0 +#define D0F2xFC_x00_L1_L1PerfEvent0_WIDTH 8 +#define D0F2xFC_x00_L1_L1PerfEvent0_MASK 0xff +#define D0F2xFC_x00_L1_L1PerfEvent1_OFFSET 8 +#define D0F2xFC_x00_L1_L1PerfEvent1_WIDTH 8 +#define D0F2xFC_x00_L1_L1PerfEvent1_MASK 0xff00 +#define D0F2xFC_x00_L1_L1PerfCountHi0_OFFSET 16 +#define D0F2xFC_x00_L1_L1PerfCountHi0_WIDTH 8 +#define D0F2xFC_x00_L1_L1PerfCountHi0_MASK 0xff0000 +#define D0F2xFC_x00_L1_L1PerfCountHi1_OFFSET 24 +#define D0F2xFC_x00_L1_L1PerfCountHi1_WIDTH 8 +#define D0F2xFC_x00_L1_L1PerfCountHi1_MASK 0xff000000 + +/// D0F2xFC_x00_L1 +typedef union { + struct { ///< + UINT32 L1PerfEvent0:8 ; ///< + UINT32 L1PerfEvent1:8 ; ///< + UINT32 L1PerfCountHi0:8 ; ///< + UINT32 L1PerfCountHi1:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xFC_x00_L1_STRUCT; + +// **** D0F2xFC_x02_L1 Register Definition **** +// Address +#define D0F2xFC_x02_L1_ADDRESS(Sel) ((Sel << 16) | 0x02) + +// Type +#define D0F2xFC_x02_L1_TYPE TYPE_D0F2xFC +// Field Data +#define D0F2xFC_x02_L1_L1PerfCount1_OFFSET 0 +#define D0F2xFC_x02_L1_L1PerfCount1_WIDTH 32 +#define D0F2xFC_x02_L1_L1PerfCount1_MASK 0xffffffff + +/// D0F2xFC_x02_L1 +typedef union { + struct { ///< + UINT32 L1PerfCount1:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xFC_x02_L1_STRUCT; + + + +// **** D0F2xFC_x07_L1 Register Definition **** +// Address +#define D0F2xFC_x07_L1_ADDRESS(Sel) ((Sel << 16) | 0x07) + +// Type +#define D0F2xFC_x07_L1_TYPE TYPE_D0F2xFC +// Field Data +#define D0F2xFC_x07_L1_PhantomFuncEn_OFFSET 0 +#define D0F2xFC_x07_L1_PhantomFuncEn_WIDTH 1 +#define D0F2xFC_x07_L1_PhantomFuncEn_MASK 0x1 +#define D0F2xFC_x07_L1_Reserved_10_1_OFFSET 1 +#define D0F2xFC_x07_L1_Reserved_10_1_WIDTH 10 +#define D0F2xFC_x07_L1_Reserved_10_1_MASK 0x7fe +#define D0F2xFC_x07_L1_SpecReqFilterEn_OFFSET 11 +#define D0F2xFC_x07_L1_SpecReqFilterEn_WIDTH 1 +#define D0F2xFC_x07_L1_SpecReqFilterEn_MASK 0x800 +#define D0F2xFC_x07_L1_AtsSeqNumEn_OFFSET 12 +#define D0F2xFC_x07_L1_AtsSeqNumEn_WIDTH 1 +#define D0F2xFC_x07_L1_AtsSeqNumEn_MASK 0x1000 +#define D0F2xFC_x07_L1_Reserved_13_13_OFFSET 13 +#define D0F2xFC_x07_L1_Reserved_13_13_WIDTH 1 +#define D0F2xFC_x07_L1_Reserved_13_13_MASK 0x2000 +#define D0F2xFC_x07_L1_AtsPhysPageOverlapDis_OFFSET 14 +#define D0F2xFC_x07_L1_AtsPhysPageOverlapDis_WIDTH 1 +#define D0F2xFC_x07_L1_AtsPhysPageOverlapDis_MASK 0x4000 +#define D0F2xFC_x07_L1_Reserved_16_15_OFFSET 15 +#define D0F2xFC_x07_L1_Reserved_16_15_WIDTH 2 +#define D0F2xFC_x07_L1_Reserved_16_15_MASK 0x18000 +#define D0F2xFC_x07_L1_L1NwEn_OFFSET 17 +#define D0F2xFC_x07_L1_L1NwEn_WIDTH 1 +#define D0F2xFC_x07_L1_L1NwEn_MASK 0x20000 +#define D0F2xFC_x07_L1_Reserved_31_18_OFFSET 18 +#define D0F2xFC_x07_L1_Reserved_31_18_WIDTH 14 +#define D0F2xFC_x07_L1_Reserved_31_18_MASK 0xfffc0000 + +/// D0F2xFC_x07_L1 +typedef union { + struct { ///< + UINT32 PhantomFuncEn:1 ; ///< + UINT32 Reserved_10_1:10; ///< + UINT32 SpecReqFilterEn:1 ; ///< + UINT32 AtsSeqNumEn:1 ; ///< + UINT32 Reserved_13_13:1 ; ///< + UINT32 AtsPhysPageOverlapDis:1 ; ///< + UINT32 Reserved_16_15:2 ; ///< + UINT32 L1NwEn:1 ; ///< + UINT32 Reserved_31_18:14; ///< + } Field; ///< + UINT32 Value; ///< +} D0F2xFC_x07_L1_STRUCT; + +// **** D18F2x9C_x0000_0000_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0000_dct1_mp0_ADDRESS 0x0 + +// Type +#define D18F2x9C_x0000_0000_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0000_dct1_mp0_CkeDrvStren_OFFSET 0 +#define D18F2x9C_x0000_0000_dct1_mp0_CkeDrvStren_WIDTH 3 +#define D18F2x9C_x0000_0000_dct1_mp0_CkeDrvStren_MASK 0x7 +#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_3_3_OFFSET 3 +#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_3_3_WIDTH 1 +#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_3_3_MASK 0x8 +#define D18F2x9C_x0000_0000_dct1_mp0_CsOdtDrvStren_OFFSET 4 +#define D18F2x9C_x0000_0000_dct1_mp0_CsOdtDrvStren_WIDTH 3 +#define D18F2x9C_x0000_0000_dct1_mp0_CsOdtDrvStren_MASK 0x70 +#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_7_7_OFFSET 7 +#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_7_7_WIDTH 1 +#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_7_7_MASK 0x80 +#define D18F2x9C_x0000_0000_dct1_mp0_AddrCmdDrvStren_OFFSET 8 +#define D18F2x9C_x0000_0000_dct1_mp0_AddrCmdDrvStren_WIDTH 3 +#define D18F2x9C_x0000_0000_dct1_mp0_AddrCmdDrvStren_MASK 0x700 +#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_11_11_OFFSET 11 +#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_11_11_WIDTH 1 +#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_11_11_MASK 0x800 +#define D18F2x9C_x0000_0000_dct1_mp0_ClkDrvStren_OFFSET 12 +#define D18F2x9C_x0000_0000_dct1_mp0_ClkDrvStren_WIDTH 3 +#define D18F2x9C_x0000_0000_dct1_mp0_ClkDrvStren_MASK 0x7000 +#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_15_15_OFFSET 15 +#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_15_15_WIDTH 1 +#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_15_15_MASK 0x8000 +#define D18F2x9C_x0000_0000_dct1_mp0_DataDrvStren_OFFSET 16 +#define D18F2x9C_x0000_0000_dct1_mp0_DataDrvStren_WIDTH 3 +#define D18F2x9C_x0000_0000_dct1_mp0_DataDrvStren_MASK 0x70000 +#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_19_19_OFFSET 19 +#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_19_19_WIDTH 1 +#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_19_19_MASK 0x80000 +#define D18F2x9C_x0000_0000_dct1_mp0_DqsDrvStren_OFFSET 20 +#define D18F2x9C_x0000_0000_dct1_mp0_DqsDrvStren_WIDTH 3 +#define D18F2x9C_x0000_0000_dct1_mp0_DqsDrvStren_MASK 0x700000 +#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_27_23_OFFSET 23 +#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_27_23_WIDTH 5 +#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_27_23_MASK 0xf800000 +#define D18F2x9C_x0000_0000_dct1_mp0_ProcOdt_OFFSET 28 +#define D18F2x9C_x0000_0000_dct1_mp0_ProcOdt_WIDTH 3 +#define D18F2x9C_x0000_0000_dct1_mp0_ProcOdt_MASK 0x70000000 +#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_31_31_OFFSET 31 +#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_31_31_WIDTH 1 +#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_31_31_MASK 0x80000000 + +/// D18F2x9C_x0000_0000_dct1_mp0 +typedef union { + struct { ///< + UINT32 CkeDrvStren:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 CsOdtDrvStren:3 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 AddrCmdDrvStren:3 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 ClkDrvStren:3 ; ///< + UINT32 Reserved_15_15:1 ; ///< + UINT32 DataDrvStren:3 ; ///< + UINT32 Reserved_19_19:1 ; ///< + UINT32 DqsDrvStren:3 ; ///< + UINT32 Reserved_27_23:5 ; ///< + UINT32 ProcOdt:3 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0000_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0000_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0000_dct0_mp0_ADDRESS 0x0 + +// Type +#define D18F2x9C_x0000_0000_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0000_dct0_mp0_CkeDrvStren_OFFSET 0 +#define D18F2x9C_x0000_0000_dct0_mp0_CkeDrvStren_WIDTH 3 +#define D18F2x9C_x0000_0000_dct0_mp0_CkeDrvStren_MASK 0x7 +#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_3_3_OFFSET 3 +#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_3_3_WIDTH 1 +#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_3_3_MASK 0x8 +#define D18F2x9C_x0000_0000_dct0_mp0_CsOdtDrvStren_OFFSET 4 +#define D18F2x9C_x0000_0000_dct0_mp0_CsOdtDrvStren_WIDTH 3 +#define D18F2x9C_x0000_0000_dct0_mp0_CsOdtDrvStren_MASK 0x70 +#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_7_7_OFFSET 7 +#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_7_7_WIDTH 1 +#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_7_7_MASK 0x80 +#define D18F2x9C_x0000_0000_dct0_mp0_AddrCmdDrvStren_OFFSET 8 +#define D18F2x9C_x0000_0000_dct0_mp0_AddrCmdDrvStren_WIDTH 3 +#define D18F2x9C_x0000_0000_dct0_mp0_AddrCmdDrvStren_MASK 0x700 +#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_11_11_OFFSET 11 +#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_11_11_WIDTH 1 +#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_11_11_MASK 0x800 +#define D18F2x9C_x0000_0000_dct0_mp0_ClkDrvStren_OFFSET 12 +#define D18F2x9C_x0000_0000_dct0_mp0_ClkDrvStren_WIDTH 3 +#define D18F2x9C_x0000_0000_dct0_mp0_ClkDrvStren_MASK 0x7000 +#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_15_15_OFFSET 15 +#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_15_15_WIDTH 1 +#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_15_15_MASK 0x8000 +#define D18F2x9C_x0000_0000_dct0_mp0_DataDrvStren_OFFSET 16 +#define D18F2x9C_x0000_0000_dct0_mp0_DataDrvStren_WIDTH 3 +#define D18F2x9C_x0000_0000_dct0_mp0_DataDrvStren_MASK 0x70000 +#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_19_19_OFFSET 19 +#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_19_19_WIDTH 1 +#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_19_19_MASK 0x80000 +#define D18F2x9C_x0000_0000_dct0_mp0_DqsDrvStren_OFFSET 20 +#define D18F2x9C_x0000_0000_dct0_mp0_DqsDrvStren_WIDTH 3 +#define D18F2x9C_x0000_0000_dct0_mp0_DqsDrvStren_MASK 0x700000 +#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_27_23_OFFSET 23 +#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_27_23_WIDTH 5 +#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_27_23_MASK 0xf800000 +#define D18F2x9C_x0000_0000_dct0_mp0_ProcOdt_OFFSET 28 +#define D18F2x9C_x0000_0000_dct0_mp0_ProcOdt_WIDTH 3 +#define D18F2x9C_x0000_0000_dct0_mp0_ProcOdt_MASK 0x70000000 +#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_31_31_OFFSET 31 +#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_31_31_WIDTH 1 +#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_31_31_MASK 0x80000000 + +/// D18F2x9C_x0000_0000_dct0_mp0 +typedef union { + struct { ///< + UINT32 CkeDrvStren:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 CsOdtDrvStren:3 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 AddrCmdDrvStren:3 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 ClkDrvStren:3 ; ///< + UINT32 Reserved_15_15:1 ; ///< + UINT32 DataDrvStren:3 ; ///< + UINT32 Reserved_19_19:1 ; ///< + UINT32 DqsDrvStren:3 ; ///< + UINT32 Reserved_27_23:5 ; ///< + UINT32 ProcOdt:3 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0000_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0000_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0000_dct1_mp1_ADDRESS 0x0 + +// Type +#define D18F2x9C_x0000_0000_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0000_dct1_mp1_CkeDrvStren_OFFSET 0 +#define D18F2x9C_x0000_0000_dct1_mp1_CkeDrvStren_WIDTH 3 +#define D18F2x9C_x0000_0000_dct1_mp1_CkeDrvStren_MASK 0x7 +#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_3_3_OFFSET 3 +#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_3_3_WIDTH 1 +#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_3_3_MASK 0x8 +#define D18F2x9C_x0000_0000_dct1_mp1_CsOdtDrvStren_OFFSET 4 +#define D18F2x9C_x0000_0000_dct1_mp1_CsOdtDrvStren_WIDTH 3 +#define D18F2x9C_x0000_0000_dct1_mp1_CsOdtDrvStren_MASK 0x70 +#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_7_7_OFFSET 7 +#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_7_7_WIDTH 1 +#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_7_7_MASK 0x80 +#define D18F2x9C_x0000_0000_dct1_mp1_AddrCmdDrvStren_OFFSET 8 +#define D18F2x9C_x0000_0000_dct1_mp1_AddrCmdDrvStren_WIDTH 3 +#define D18F2x9C_x0000_0000_dct1_mp1_AddrCmdDrvStren_MASK 0x700 +#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_11_11_OFFSET 11 +#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_11_11_WIDTH 1 +#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_11_11_MASK 0x800 +#define D18F2x9C_x0000_0000_dct1_mp1_ClkDrvStren_OFFSET 12 +#define D18F2x9C_x0000_0000_dct1_mp1_ClkDrvStren_WIDTH 3 +#define D18F2x9C_x0000_0000_dct1_mp1_ClkDrvStren_MASK 0x7000 +#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_15_15_OFFSET 15 +#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_15_15_WIDTH 1 +#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_15_15_MASK 0x8000 +#define D18F2x9C_x0000_0000_dct1_mp1_DataDrvStren_OFFSET 16 +#define D18F2x9C_x0000_0000_dct1_mp1_DataDrvStren_WIDTH 3 +#define D18F2x9C_x0000_0000_dct1_mp1_DataDrvStren_MASK 0x70000 +#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_19_19_OFFSET 19 +#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_19_19_WIDTH 1 +#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_19_19_MASK 0x80000 +#define D18F2x9C_x0000_0000_dct1_mp1_DqsDrvStren_OFFSET 20 +#define D18F2x9C_x0000_0000_dct1_mp1_DqsDrvStren_WIDTH 3 +#define D18F2x9C_x0000_0000_dct1_mp1_DqsDrvStren_MASK 0x700000 +#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_27_23_OFFSET 23 +#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_27_23_WIDTH 5 +#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_27_23_MASK 0xf800000 +#define D18F2x9C_x0000_0000_dct1_mp1_ProcOdt_OFFSET 28 +#define D18F2x9C_x0000_0000_dct1_mp1_ProcOdt_WIDTH 3 +#define D18F2x9C_x0000_0000_dct1_mp1_ProcOdt_MASK 0x70000000 +#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_31_31_OFFSET 31 +#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_31_31_WIDTH 1 +#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_31_31_MASK 0x80000000 + +/// D18F2x9C_x0000_0000_dct1_mp1 +typedef union { + struct { ///< + UINT32 CkeDrvStren:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 CsOdtDrvStren:3 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 AddrCmdDrvStren:3 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 ClkDrvStren:3 ; ///< + UINT32 Reserved_15_15:1 ; ///< + UINT32 DataDrvStren:3 ; ///< + UINT32 Reserved_19_19:1 ; ///< + UINT32 DqsDrvStren:3 ; ///< + UINT32 Reserved_27_23:5 ; ///< + UINT32 ProcOdt:3 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0000_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0000_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0000_dct0_mp1_ADDRESS 0x0 + +// Type +#define D18F2x9C_x0000_0000_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0000_dct0_mp1_CkeDrvStren_OFFSET 0 +#define D18F2x9C_x0000_0000_dct0_mp1_CkeDrvStren_WIDTH 3 +#define D18F2x9C_x0000_0000_dct0_mp1_CkeDrvStren_MASK 0x7 +#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_3_3_OFFSET 3 +#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_3_3_WIDTH 1 +#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_3_3_MASK 0x8 +#define D18F2x9C_x0000_0000_dct0_mp1_CsOdtDrvStren_OFFSET 4 +#define D18F2x9C_x0000_0000_dct0_mp1_CsOdtDrvStren_WIDTH 3 +#define D18F2x9C_x0000_0000_dct0_mp1_CsOdtDrvStren_MASK 0x70 +#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_7_7_OFFSET 7 +#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_7_7_WIDTH 1 +#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_7_7_MASK 0x80 +#define D18F2x9C_x0000_0000_dct0_mp1_AddrCmdDrvStren_OFFSET 8 +#define D18F2x9C_x0000_0000_dct0_mp1_AddrCmdDrvStren_WIDTH 3 +#define D18F2x9C_x0000_0000_dct0_mp1_AddrCmdDrvStren_MASK 0x700 +#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_11_11_OFFSET 11 +#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_11_11_WIDTH 1 +#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_11_11_MASK 0x800 +#define D18F2x9C_x0000_0000_dct0_mp1_ClkDrvStren_OFFSET 12 +#define D18F2x9C_x0000_0000_dct0_mp1_ClkDrvStren_WIDTH 3 +#define D18F2x9C_x0000_0000_dct0_mp1_ClkDrvStren_MASK 0x7000 +#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_15_15_OFFSET 15 +#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_15_15_WIDTH 1 +#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_15_15_MASK 0x8000 +#define D18F2x9C_x0000_0000_dct0_mp1_DataDrvStren_OFFSET 16 +#define D18F2x9C_x0000_0000_dct0_mp1_DataDrvStren_WIDTH 3 +#define D18F2x9C_x0000_0000_dct0_mp1_DataDrvStren_MASK 0x70000 +#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_19_19_OFFSET 19 +#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_19_19_WIDTH 1 +#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_19_19_MASK 0x80000 +#define D18F2x9C_x0000_0000_dct0_mp1_DqsDrvStren_OFFSET 20 +#define D18F2x9C_x0000_0000_dct0_mp1_DqsDrvStren_WIDTH 3 +#define D18F2x9C_x0000_0000_dct0_mp1_DqsDrvStren_MASK 0x700000 +#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_27_23_OFFSET 23 +#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_27_23_WIDTH 5 +#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_27_23_MASK 0xf800000 +#define D18F2x9C_x0000_0000_dct0_mp1_ProcOdt_OFFSET 28 +#define D18F2x9C_x0000_0000_dct0_mp1_ProcOdt_WIDTH 3 +#define D18F2x9C_x0000_0000_dct0_mp1_ProcOdt_MASK 0x70000000 +#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_31_31_OFFSET 31 +#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_31_31_WIDTH 1 +#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_31_31_MASK 0x80000000 + +/// D18F2x9C_x0000_0000_dct0_mp1 +typedef union { + struct { ///< + UINT32 CkeDrvStren:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 CsOdtDrvStren:3 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 AddrCmdDrvStren:3 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 ClkDrvStren:3 ; ///< + UINT32 Reserved_15_15:1 ; ///< + UINT32 DataDrvStren:3 ; ///< + UINT32 Reserved_19_19:1 ; ///< + UINT32 DqsDrvStren:3 ; ///< + UINT32 Reserved_27_23:5 ; ///< + UINT32 ProcOdt:3 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0000_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0001_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0001_dct1_mp0_ADDRESS 0x1 + +// Type +#define D18F2x9C_x0000_0001_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0001_dct1_mp0 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0001_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0001_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0001_dct0_mp0_ADDRESS 0x1 + +// Type +#define D18F2x9C_x0000_0001_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0001_dct0_mp0 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0001_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0001_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0001_dct1_mp1_ADDRESS 0x1 + +// Type +#define D18F2x9C_x0000_0001_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0001_dct1_mp1 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0001_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0001_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0001_dct0_mp1_ADDRESS 0x1 + +// Type +#define D18F2x9C_x0000_0001_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0001_dct0_mp1 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0001_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0002_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0002_dct1_mp1_ADDRESS 0x2 + +// Type +#define D18F2x9C_x0000_0002_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0002_dct1_mp1 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0002_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0002_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0002_dct1_mp0_ADDRESS 0x2 + +// Type +#define D18F2x9C_x0000_0002_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0002_dct1_mp0 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0002_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0002_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0002_dct0_mp1_ADDRESS 0x2 + +// Type +#define D18F2x9C_x0000_0002_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0002_dct0_mp1 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0002_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0002_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0002_dct0_mp0_ADDRESS 0x2 + +// Type +#define D18F2x9C_x0000_0002_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0002_dct0_mp0 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0002_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0004_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0004_dct1_mp1_ADDRESS 0x4 + +// Type +#define D18F2x9C_x0000_0004_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0004_dct1_mp1_CkeFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0004_dct1_mp1_CkeFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0004_dct1_mp1_CkeFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0004_dct1_mp1_CkeSetup_OFFSET 5 +#define D18F2x9C_x0000_0004_dct1_mp1_CkeSetup_WIDTH 1 +#define D18F2x9C_x0000_0004_dct1_mp1_CkeSetup_MASK 0x20 +#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_7_6_OFFSET 6 +#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_7_6_WIDTH 2 +#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_7_6_MASK 0xc0 +#define D18F2x9C_x0000_0004_dct1_mp1_CsOdtFineDelay_OFFSET 8 +#define D18F2x9C_x0000_0004_dct1_mp1_CsOdtFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0004_dct1_mp1_CsOdtFineDelay_MASK 0x1f00 +#define D18F2x9C_x0000_0004_dct1_mp1_CsOdtSetup_OFFSET 13 +#define D18F2x9C_x0000_0004_dct1_mp1_CsOdtSetup_WIDTH 1 +#define D18F2x9C_x0000_0004_dct1_mp1_CsOdtSetup_MASK 0x2000 +#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_15_14_OFFSET 14 +#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_15_14_WIDTH 2 +#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_15_14_MASK 0xc000 +#define D18F2x9C_x0000_0004_dct1_mp1_AddrCmdFineDelay_OFFSET 16 +#define D18F2x9C_x0000_0004_dct1_mp1_AddrCmdFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0004_dct1_mp1_AddrCmdFineDelay_MASK 0x1f0000 +#define D18F2x9C_x0000_0004_dct1_mp1_AddrCmdSetup_OFFSET 21 +#define D18F2x9C_x0000_0004_dct1_mp1_AddrCmdSetup_WIDTH 1 +#define D18F2x9C_x0000_0004_dct1_mp1_AddrCmdSetup_MASK 0x200000 +#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_31_22_OFFSET 22 +#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_31_22_WIDTH 10 +#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_31_22_MASK 0xffc00000 + +/// D18F2x9C_x0000_0004_dct1_mp1 +typedef union { + struct { ///< + UINT32 CkeFineDelay:5 ; ///< + UINT32 CkeSetup:1 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 CsOdtFineDelay:5 ; ///< + UINT32 CsOdtSetup:1 ; ///< + UINT32 Reserved_15_14:2 ; ///< + UINT32 AddrCmdFineDelay:5 ; ///< + UINT32 AddrCmdSetup:1 ; ///< + UINT32 Reserved_31_22:10; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0004_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0004_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0004_dct0_mp0_ADDRESS 0x4 + +// Type +#define D18F2x9C_x0000_0004_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0004_dct0_mp0_CkeFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0004_dct0_mp0_CkeFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0004_dct0_mp0_CkeFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0004_dct0_mp0_CkeSetup_OFFSET 5 +#define D18F2x9C_x0000_0004_dct0_mp0_CkeSetup_WIDTH 1 +#define D18F2x9C_x0000_0004_dct0_mp0_CkeSetup_MASK 0x20 +#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_7_6_OFFSET 6 +#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_7_6_WIDTH 2 +#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_7_6_MASK 0xc0 +#define D18F2x9C_x0000_0004_dct0_mp0_CsOdtFineDelay_OFFSET 8 +#define D18F2x9C_x0000_0004_dct0_mp0_CsOdtFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0004_dct0_mp0_CsOdtFineDelay_MASK 0x1f00 +#define D18F2x9C_x0000_0004_dct0_mp0_CsOdtSetup_OFFSET 13 +#define D18F2x9C_x0000_0004_dct0_mp0_CsOdtSetup_WIDTH 1 +#define D18F2x9C_x0000_0004_dct0_mp0_CsOdtSetup_MASK 0x2000 +#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_15_14_OFFSET 14 +#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_15_14_WIDTH 2 +#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_15_14_MASK 0xc000 +#define D18F2x9C_x0000_0004_dct0_mp0_AddrCmdFineDelay_OFFSET 16 +#define D18F2x9C_x0000_0004_dct0_mp0_AddrCmdFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0004_dct0_mp0_AddrCmdFineDelay_MASK 0x1f0000 +#define D18F2x9C_x0000_0004_dct0_mp0_AddrCmdSetup_OFFSET 21 +#define D18F2x9C_x0000_0004_dct0_mp0_AddrCmdSetup_WIDTH 1 +#define D18F2x9C_x0000_0004_dct0_mp0_AddrCmdSetup_MASK 0x200000 +#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_31_22_OFFSET 22 +#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_31_22_WIDTH 10 +#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_31_22_MASK 0xffc00000 + +/// D18F2x9C_x0000_0004_dct0_mp0 +typedef union { + struct { ///< + UINT32 CkeFineDelay:5 ; ///< + UINT32 CkeSetup:1 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 CsOdtFineDelay:5 ; ///< + UINT32 CsOdtSetup:1 ; ///< + UINT32 Reserved_15_14:2 ; ///< + UINT32 AddrCmdFineDelay:5 ; ///< + UINT32 AddrCmdSetup:1 ; ///< + UINT32 Reserved_31_22:10; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0004_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0004_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0004_dct0_mp1_ADDRESS 0x4 + +// Type +#define D18F2x9C_x0000_0004_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0004_dct0_mp1_CkeFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0004_dct0_mp1_CkeFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0004_dct0_mp1_CkeFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0004_dct0_mp1_CkeSetup_OFFSET 5 +#define D18F2x9C_x0000_0004_dct0_mp1_CkeSetup_WIDTH 1 +#define D18F2x9C_x0000_0004_dct0_mp1_CkeSetup_MASK 0x20 +#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_7_6_OFFSET 6 +#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_7_6_WIDTH 2 +#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_7_6_MASK 0xc0 +#define D18F2x9C_x0000_0004_dct0_mp1_CsOdtFineDelay_OFFSET 8 +#define D18F2x9C_x0000_0004_dct0_mp1_CsOdtFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0004_dct0_mp1_CsOdtFineDelay_MASK 0x1f00 +#define D18F2x9C_x0000_0004_dct0_mp1_CsOdtSetup_OFFSET 13 +#define D18F2x9C_x0000_0004_dct0_mp1_CsOdtSetup_WIDTH 1 +#define D18F2x9C_x0000_0004_dct0_mp1_CsOdtSetup_MASK 0x2000 +#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_15_14_OFFSET 14 +#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_15_14_WIDTH 2 +#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_15_14_MASK 0xc000 +#define D18F2x9C_x0000_0004_dct0_mp1_AddrCmdFineDelay_OFFSET 16 +#define D18F2x9C_x0000_0004_dct0_mp1_AddrCmdFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0004_dct0_mp1_AddrCmdFineDelay_MASK 0x1f0000 +#define D18F2x9C_x0000_0004_dct0_mp1_AddrCmdSetup_OFFSET 21 +#define D18F2x9C_x0000_0004_dct0_mp1_AddrCmdSetup_WIDTH 1 +#define D18F2x9C_x0000_0004_dct0_mp1_AddrCmdSetup_MASK 0x200000 +#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_31_22_OFFSET 22 +#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_31_22_WIDTH 10 +#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_31_22_MASK 0xffc00000 + +/// D18F2x9C_x0000_0004_dct0_mp1 +typedef union { + struct { ///< + UINT32 CkeFineDelay:5 ; ///< + UINT32 CkeSetup:1 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 CsOdtFineDelay:5 ; ///< + UINT32 CsOdtSetup:1 ; ///< + UINT32 Reserved_15_14:2 ; ///< + UINT32 AddrCmdFineDelay:5 ; ///< + UINT32 AddrCmdSetup:1 ; ///< + UINT32 Reserved_31_22:10; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0004_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0004_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0004_dct1_mp0_ADDRESS 0x4 + +// Type +#define D18F2x9C_x0000_0004_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0004_dct1_mp0_CkeFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0004_dct1_mp0_CkeFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0004_dct1_mp0_CkeFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0004_dct1_mp0_CkeSetup_OFFSET 5 +#define D18F2x9C_x0000_0004_dct1_mp0_CkeSetup_WIDTH 1 +#define D18F2x9C_x0000_0004_dct1_mp0_CkeSetup_MASK 0x20 +#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_7_6_OFFSET 6 +#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_7_6_WIDTH 2 +#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_7_6_MASK 0xc0 +#define D18F2x9C_x0000_0004_dct1_mp0_CsOdtFineDelay_OFFSET 8 +#define D18F2x9C_x0000_0004_dct1_mp0_CsOdtFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0004_dct1_mp0_CsOdtFineDelay_MASK 0x1f00 +#define D18F2x9C_x0000_0004_dct1_mp0_CsOdtSetup_OFFSET 13 +#define D18F2x9C_x0000_0004_dct1_mp0_CsOdtSetup_WIDTH 1 +#define D18F2x9C_x0000_0004_dct1_mp0_CsOdtSetup_MASK 0x2000 +#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_15_14_OFFSET 14 +#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_15_14_WIDTH 2 +#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_15_14_MASK 0xc000 +#define D18F2x9C_x0000_0004_dct1_mp0_AddrCmdFineDelay_OFFSET 16 +#define D18F2x9C_x0000_0004_dct1_mp0_AddrCmdFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0004_dct1_mp0_AddrCmdFineDelay_MASK 0x1f0000 +#define D18F2x9C_x0000_0004_dct1_mp0_AddrCmdSetup_OFFSET 21 +#define D18F2x9C_x0000_0004_dct1_mp0_AddrCmdSetup_WIDTH 1 +#define D18F2x9C_x0000_0004_dct1_mp0_AddrCmdSetup_MASK 0x200000 +#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_31_22_OFFSET 22 +#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_31_22_WIDTH 10 +#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_31_22_MASK 0xffc00000 + +/// D18F2x9C_x0000_0004_dct1_mp0 +typedef union { + struct { ///< + UINT32 CkeFineDelay:5 ; ///< + UINT32 CkeSetup:1 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 CsOdtFineDelay:5 ; ///< + UINT32 CsOdtSetup:1 ; ///< + UINT32 Reserved_15_14:2 ; ///< + UINT32 AddrCmdFineDelay:5 ; ///< + UINT32 AddrCmdSetup:1 ; ///< + UINT32 Reserved_31_22:10; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0004_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0005_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0005_dct0_mp0_ADDRESS 0x5 + +// Type +#define D18F2x9C_x0000_0005_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0005_dct0_mp0 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0005_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0005_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0005_dct1_mp0_ADDRESS 0x5 + +// Type +#define D18F2x9C_x0000_0005_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0005_dct1_mp0 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0005_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0005_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0005_dct1_mp1_ADDRESS 0x5 + +// Type +#define D18F2x9C_x0000_0005_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0005_dct1_mp1 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0005_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0005_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0005_dct0_mp1_ADDRESS 0x5 + +// Type +#define D18F2x9C_x0000_0005_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0005_dct0_mp1 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0005_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0006_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0006_dct1_mp0_ADDRESS 0x6 + +// Type +#define D18F2x9C_x0000_0006_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0006_dct1_mp0 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0006_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0006_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0006_dct0_mp1_ADDRESS 0x6 + +// Type +#define D18F2x9C_x0000_0006_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0006_dct0_mp1 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0006_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0006_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0006_dct1_mp1_ADDRESS 0x6 + +// Type +#define D18F2x9C_x0000_0006_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0006_dct1_mp1 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0006_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0006_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0006_dct0_mp0_ADDRESS 0x6 + +// Type +#define D18F2x9C_x0000_0006_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0006_dct0_mp0 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0006_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0008_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0008_dct0_mp1_ADDRESS 0x8 + +// Type +#define D18F2x9C_x0000_0008_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0008_dct0_mp1_WrtLvTrEn_OFFSET 0 +#define D18F2x9C_x0000_0008_dct0_mp1_WrtLvTrEn_WIDTH 1 +#define D18F2x9C_x0000_0008_dct0_mp1_WrtLvTrEn_MASK 0x1 +#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_1_1_OFFSET 1 +#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_1_1_WIDTH 1 +#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_1_1_MASK 0x2 +#define D18F2x9C_x0000_0008_dct0_mp1_TrNibbleSel_OFFSET 2 +#define D18F2x9C_x0000_0008_dct0_mp1_TrNibbleSel_WIDTH 1 +#define D18F2x9C_x0000_0008_dct0_mp1_TrNibbleSel_MASK 0x4 +#define D18F2x9C_x0000_0008_dct0_mp1_PhyFenceTrEn_OFFSET 3 +#define D18F2x9C_x0000_0008_dct0_mp1_PhyFenceTrEn_WIDTH 1 +#define D18F2x9C_x0000_0008_dct0_mp1_PhyFenceTrEn_MASK 0x8 +#define D18F2x9C_x0000_0008_dct0_mp1_TrChipSel_OFFSET 4 +#define D18F2x9C_x0000_0008_dct0_mp1_TrChipSel_WIDTH 2 +#define D18F2x9C_x0000_0008_dct0_mp1_TrChipSel_MASK 0x30 +#define D18F2x9C_x0000_0008_dct0_mp1_FenceTrSel_OFFSET 6 +#define D18F2x9C_x0000_0008_dct0_mp1_FenceTrSel_WIDTH 2 +#define D18F2x9C_x0000_0008_dct0_mp1_FenceTrSel_MASK 0xc0 +#define D18F2x9C_x0000_0008_dct0_mp1_WrLvOdt_OFFSET 8 +#define D18F2x9C_x0000_0008_dct0_mp1_WrLvOdt_WIDTH 4 +#define D18F2x9C_x0000_0008_dct0_mp1_WrLvOdt_MASK 0xf00 +#define D18F2x9C_x0000_0008_dct0_mp1_WrLvOdtEn_OFFSET 12 +#define D18F2x9C_x0000_0008_dct0_mp1_WrLvOdtEn_WIDTH 1 +#define D18F2x9C_x0000_0008_dct0_mp1_WrLvOdtEn_MASK 0x1000 +#define D18F2x9C_x0000_0008_dct0_mp1_DqsRcvTrEn_OFFSET 13 +#define D18F2x9C_x0000_0008_dct0_mp1_DqsRcvTrEn_WIDTH 1 +#define D18F2x9C_x0000_0008_dct0_mp1_DqsRcvTrEn_MASK 0x2000 +#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_28_14_OFFSET 14 +#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_28_14_WIDTH 15 +#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_28_14_MASK 0x1fffc000 +#define D18F2x9C_x0000_0008_dct0_mp1_DisablePredriverCal_OFFSET 29 +#define D18F2x9C_x0000_0008_dct0_mp1_DisablePredriverCal_WIDTH 1 +#define D18F2x9C_x0000_0008_dct0_mp1_DisablePredriverCal_MASK 0x20000000 +#define D18F2x9C_x0000_0008_dct0_mp1_DisAutoComp_OFFSET 30 +#define D18F2x9C_x0000_0008_dct0_mp1_DisAutoComp_WIDTH 1 +#define D18F2x9C_x0000_0008_dct0_mp1_DisAutoComp_MASK 0x40000000 +#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_31_31_OFFSET 31 +#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_31_31_WIDTH 1 +#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_31_31_MASK 0x80000000 + +/// D18F2x9C_x0000_0008_dct0_mp1 +typedef union { + struct { ///< + UINT32 WrtLvTrEn:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 TrNibbleSel:1 ; ///< + UINT32 PhyFenceTrEn:1 ; ///< + UINT32 TrChipSel:2 ; ///< + UINT32 FenceTrSel:2 ; ///< + UINT32 WrLvOdt:4 ; ///< + UINT32 WrLvOdtEn:1 ; ///< + UINT32 DqsRcvTrEn:1 ; ///< + UINT32 Reserved_28_14:15; ///< + UINT32 DisablePredriverCal:1 ; ///< + UINT32 DisAutoComp:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0008_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0008_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0008_dct0_mp0_ADDRESS 0x8 + +// Type +#define D18F2x9C_x0000_0008_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0008_dct0_mp0_WrtLvTrEn_OFFSET 0 +#define D18F2x9C_x0000_0008_dct0_mp0_WrtLvTrEn_WIDTH 1 +#define D18F2x9C_x0000_0008_dct0_mp0_WrtLvTrEn_MASK 0x1 +#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_1_1_OFFSET 1 +#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_1_1_WIDTH 1 +#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_1_1_MASK 0x2 +#define D18F2x9C_x0000_0008_dct0_mp0_TrNibbleSel_OFFSET 2 +#define D18F2x9C_x0000_0008_dct0_mp0_TrNibbleSel_WIDTH 1 +#define D18F2x9C_x0000_0008_dct0_mp0_TrNibbleSel_MASK 0x4 +#define D18F2x9C_x0000_0008_dct0_mp0_PhyFenceTrEn_OFFSET 3 +#define D18F2x9C_x0000_0008_dct0_mp0_PhyFenceTrEn_WIDTH 1 +#define D18F2x9C_x0000_0008_dct0_mp0_PhyFenceTrEn_MASK 0x8 +#define D18F2x9C_x0000_0008_dct0_mp0_TrChipSel_OFFSET 4 +#define D18F2x9C_x0000_0008_dct0_mp0_TrChipSel_WIDTH 2 +#define D18F2x9C_x0000_0008_dct0_mp0_TrChipSel_MASK 0x30 +#define D18F2x9C_x0000_0008_dct0_mp0_FenceTrSel_OFFSET 6 +#define D18F2x9C_x0000_0008_dct0_mp0_FenceTrSel_WIDTH 2 +#define D18F2x9C_x0000_0008_dct0_mp0_FenceTrSel_MASK 0xc0 +#define D18F2x9C_x0000_0008_dct0_mp0_WrLvOdt_OFFSET 8 +#define D18F2x9C_x0000_0008_dct0_mp0_WrLvOdt_WIDTH 4 +#define D18F2x9C_x0000_0008_dct0_mp0_WrLvOdt_MASK 0xf00 +#define D18F2x9C_x0000_0008_dct0_mp0_WrLvOdtEn_OFFSET 12 +#define D18F2x9C_x0000_0008_dct0_mp0_WrLvOdtEn_WIDTH 1 +#define D18F2x9C_x0000_0008_dct0_mp0_WrLvOdtEn_MASK 0x1000 +#define D18F2x9C_x0000_0008_dct0_mp0_DqsRcvTrEn_OFFSET 13 +#define D18F2x9C_x0000_0008_dct0_mp0_DqsRcvTrEn_WIDTH 1 +#define D18F2x9C_x0000_0008_dct0_mp0_DqsRcvTrEn_MASK 0x2000 +#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_28_14_OFFSET 14 +#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_28_14_WIDTH 15 +#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_28_14_MASK 0x1fffc000 +#define D18F2x9C_x0000_0008_dct0_mp0_DisablePredriverCal_OFFSET 29 +#define D18F2x9C_x0000_0008_dct0_mp0_DisablePredriverCal_WIDTH 1 +#define D18F2x9C_x0000_0008_dct0_mp0_DisablePredriverCal_MASK 0x20000000 +#define D18F2x9C_x0000_0008_dct0_mp0_DisAutoComp_OFFSET 30 +#define D18F2x9C_x0000_0008_dct0_mp0_DisAutoComp_WIDTH 1 +#define D18F2x9C_x0000_0008_dct0_mp0_DisAutoComp_MASK 0x40000000 +#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_31_31_OFFSET 31 +#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_31_31_WIDTH 1 +#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_31_31_MASK 0x80000000 + +/// D18F2x9C_x0000_0008_dct0_mp0 +typedef union { + struct { ///< + UINT32 WrtLvTrEn:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 TrNibbleSel:1 ; ///< + UINT32 PhyFenceTrEn:1 ; ///< + UINT32 TrChipSel:2 ; ///< + UINT32 FenceTrSel:2 ; ///< + UINT32 WrLvOdt:4 ; ///< + UINT32 WrLvOdtEn:1 ; ///< + UINT32 DqsRcvTrEn:1 ; ///< + UINT32 Reserved_28_14:15; ///< + UINT32 DisablePredriverCal:1 ; ///< + UINT32 DisAutoComp:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0008_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0008_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0008_dct1_mp0_ADDRESS 0x8 + +// Type +#define D18F2x9C_x0000_0008_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0008_dct1_mp0_WrtLvTrEn_OFFSET 0 +#define D18F2x9C_x0000_0008_dct1_mp0_WrtLvTrEn_WIDTH 1 +#define D18F2x9C_x0000_0008_dct1_mp0_WrtLvTrEn_MASK 0x1 +#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_1_1_OFFSET 1 +#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_1_1_WIDTH 1 +#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_1_1_MASK 0x2 +#define D18F2x9C_x0000_0008_dct1_mp0_TrNibbleSel_OFFSET 2 +#define D18F2x9C_x0000_0008_dct1_mp0_TrNibbleSel_WIDTH 1 +#define D18F2x9C_x0000_0008_dct1_mp0_TrNibbleSel_MASK 0x4 +#define D18F2x9C_x0000_0008_dct1_mp0_PhyFenceTrEn_OFFSET 3 +#define D18F2x9C_x0000_0008_dct1_mp0_PhyFenceTrEn_WIDTH 1 +#define D18F2x9C_x0000_0008_dct1_mp0_PhyFenceTrEn_MASK 0x8 +#define D18F2x9C_x0000_0008_dct1_mp0_TrChipSel_OFFSET 4 +#define D18F2x9C_x0000_0008_dct1_mp0_TrChipSel_WIDTH 2 +#define D18F2x9C_x0000_0008_dct1_mp0_TrChipSel_MASK 0x30 +#define D18F2x9C_x0000_0008_dct1_mp0_FenceTrSel_OFFSET 6 +#define D18F2x9C_x0000_0008_dct1_mp0_FenceTrSel_WIDTH 2 +#define D18F2x9C_x0000_0008_dct1_mp0_FenceTrSel_MASK 0xc0 +#define D18F2x9C_x0000_0008_dct1_mp0_WrLvOdt_OFFSET 8 +#define D18F2x9C_x0000_0008_dct1_mp0_WrLvOdt_WIDTH 4 +#define D18F2x9C_x0000_0008_dct1_mp0_WrLvOdt_MASK 0xf00 +#define D18F2x9C_x0000_0008_dct1_mp0_WrLvOdtEn_OFFSET 12 +#define D18F2x9C_x0000_0008_dct1_mp0_WrLvOdtEn_WIDTH 1 +#define D18F2x9C_x0000_0008_dct1_mp0_WrLvOdtEn_MASK 0x1000 +#define D18F2x9C_x0000_0008_dct1_mp0_DqsRcvTrEn_OFFSET 13 +#define D18F2x9C_x0000_0008_dct1_mp0_DqsRcvTrEn_WIDTH 1 +#define D18F2x9C_x0000_0008_dct1_mp0_DqsRcvTrEn_MASK 0x2000 +#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_28_14_OFFSET 14 +#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_28_14_WIDTH 15 +#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_28_14_MASK 0x1fffc000 +#define D18F2x9C_x0000_0008_dct1_mp0_DisablePredriverCal_OFFSET 29 +#define D18F2x9C_x0000_0008_dct1_mp0_DisablePredriverCal_WIDTH 1 +#define D18F2x9C_x0000_0008_dct1_mp0_DisablePredriverCal_MASK 0x20000000 +#define D18F2x9C_x0000_0008_dct1_mp0_DisAutoComp_OFFSET 30 +#define D18F2x9C_x0000_0008_dct1_mp0_DisAutoComp_WIDTH 1 +#define D18F2x9C_x0000_0008_dct1_mp0_DisAutoComp_MASK 0x40000000 +#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_31_31_OFFSET 31 +#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_31_31_WIDTH 1 +#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_31_31_MASK 0x80000000 + +/// D18F2x9C_x0000_0008_dct1_mp0 +typedef union { + struct { ///< + UINT32 WrtLvTrEn:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 TrNibbleSel:1 ; ///< + UINT32 PhyFenceTrEn:1 ; ///< + UINT32 TrChipSel:2 ; ///< + UINT32 FenceTrSel:2 ; ///< + UINT32 WrLvOdt:4 ; ///< + UINT32 WrLvOdtEn:1 ; ///< + UINT32 DqsRcvTrEn:1 ; ///< + UINT32 Reserved_28_14:15; ///< + UINT32 DisablePredriverCal:1 ; ///< + UINT32 DisAutoComp:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0008_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0008_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0008_dct1_mp1_ADDRESS 0x8 + +// Type +#define D18F2x9C_x0000_0008_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0008_dct1_mp1_WrtLvTrEn_OFFSET 0 +#define D18F2x9C_x0000_0008_dct1_mp1_WrtLvTrEn_WIDTH 1 +#define D18F2x9C_x0000_0008_dct1_mp1_WrtLvTrEn_MASK 0x1 +#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_1_1_OFFSET 1 +#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_1_1_WIDTH 1 +#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_1_1_MASK 0x2 +#define D18F2x9C_x0000_0008_dct1_mp1_TrNibbleSel_OFFSET 2 +#define D18F2x9C_x0000_0008_dct1_mp1_TrNibbleSel_WIDTH 1 +#define D18F2x9C_x0000_0008_dct1_mp1_TrNibbleSel_MASK 0x4 +#define D18F2x9C_x0000_0008_dct1_mp1_PhyFenceTrEn_OFFSET 3 +#define D18F2x9C_x0000_0008_dct1_mp1_PhyFenceTrEn_WIDTH 1 +#define D18F2x9C_x0000_0008_dct1_mp1_PhyFenceTrEn_MASK 0x8 +#define D18F2x9C_x0000_0008_dct1_mp1_TrChipSel_OFFSET 4 +#define D18F2x9C_x0000_0008_dct1_mp1_TrChipSel_WIDTH 2 +#define D18F2x9C_x0000_0008_dct1_mp1_TrChipSel_MASK 0x30 +#define D18F2x9C_x0000_0008_dct1_mp1_FenceTrSel_OFFSET 6 +#define D18F2x9C_x0000_0008_dct1_mp1_FenceTrSel_WIDTH 2 +#define D18F2x9C_x0000_0008_dct1_mp1_FenceTrSel_MASK 0xc0 +#define D18F2x9C_x0000_0008_dct1_mp1_WrLvOdt_OFFSET 8 +#define D18F2x9C_x0000_0008_dct1_mp1_WrLvOdt_WIDTH 4 +#define D18F2x9C_x0000_0008_dct1_mp1_WrLvOdt_MASK 0xf00 +#define D18F2x9C_x0000_0008_dct1_mp1_WrLvOdtEn_OFFSET 12 +#define D18F2x9C_x0000_0008_dct1_mp1_WrLvOdtEn_WIDTH 1 +#define D18F2x9C_x0000_0008_dct1_mp1_WrLvOdtEn_MASK 0x1000 +#define D18F2x9C_x0000_0008_dct1_mp1_DqsRcvTrEn_OFFSET 13 +#define D18F2x9C_x0000_0008_dct1_mp1_DqsRcvTrEn_WIDTH 1 +#define D18F2x9C_x0000_0008_dct1_mp1_DqsRcvTrEn_MASK 0x2000 +#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_28_14_OFFSET 14 +#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_28_14_WIDTH 15 +#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_28_14_MASK 0x1fffc000 +#define D18F2x9C_x0000_0008_dct1_mp1_DisablePredriverCal_OFFSET 29 +#define D18F2x9C_x0000_0008_dct1_mp1_DisablePredriverCal_WIDTH 1 +#define D18F2x9C_x0000_0008_dct1_mp1_DisablePredriverCal_MASK 0x20000000 +#define D18F2x9C_x0000_0008_dct1_mp1_DisAutoComp_OFFSET 30 +#define D18F2x9C_x0000_0008_dct1_mp1_DisAutoComp_WIDTH 1 +#define D18F2x9C_x0000_0008_dct1_mp1_DisAutoComp_MASK 0x40000000 +#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_31_31_OFFSET 31 +#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_31_31_WIDTH 1 +#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_31_31_MASK 0x80000000 + +/// D18F2x9C_x0000_0008_dct1_mp1 +typedef union { + struct { ///< + UINT32 WrtLvTrEn:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 TrNibbleSel:1 ; ///< + UINT32 PhyFenceTrEn:1 ; ///< + UINT32 TrChipSel:2 ; ///< + UINT32 FenceTrSel:2 ; ///< + UINT32 WrLvOdt:4 ; ///< + UINT32 WrLvOdtEn:1 ; ///< + UINT32 DqsRcvTrEn:1 ; ///< + UINT32 Reserved_28_14:15; ///< + UINT32 DisablePredriverCal:1 ; ///< + UINT32 DisAutoComp:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0008_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_000B_dct0 Register Definition **** +// Address +#define D18F2x9C_x0000_000B_dct0_ADDRESS 0xb + +// Type +#define D18F2x9C_x0000_000B_dct0_TYPE TYPE_D18F2x9C_dct0 +// Field Data +#define D18F2x9C_x0000_000B_dct0_Reserved_22_0_OFFSET 0 +#define D18F2x9C_x0000_000B_dct0_Reserved_22_0_WIDTH 23 +#define D18F2x9C_x0000_000B_dct0_Reserved_22_0_MASK 0x7fffff +#define D18F2x9C_x0000_000B_dct0_PhySelfRefreshMode_OFFSET 23 +#define D18F2x9C_x0000_000B_dct0_PhySelfRefreshMode_WIDTH 1 +#define D18F2x9C_x0000_000B_dct0_PhySelfRefreshMode_MASK 0x800000 +#define D18F2x9C_x0000_000B_dct0_Reserved_25_24_OFFSET 24 +#define D18F2x9C_x0000_000B_dct0_Reserved_25_24_WIDTH 2 +#define D18F2x9C_x0000_000B_dct0_Reserved_25_24_MASK 0x3000000 +#define D18F2x9C_x0000_000B_dct0_PhyPS_OFFSET 26 +#define D18F2x9C_x0000_000B_dct0_PhyPS_WIDTH 1 +#define D18F2x9C_x0000_000B_dct0_PhyPS_MASK 0x4000000 +#define D18F2x9C_x0000_000B_dct0_Reserved_29_27_OFFSET 27 +#define D18F2x9C_x0000_000B_dct0_Reserved_29_27_WIDTH 3 +#define D18F2x9C_x0000_000B_dct0_Reserved_29_27_MASK 0x38000000 +#define D18F2x9C_x0000_000B_dct0_PhyPSReq_OFFSET 30 +#define D18F2x9C_x0000_000B_dct0_PhyPSReq_WIDTH 1 +#define D18F2x9C_x0000_000B_dct0_PhyPSReq_MASK 0x40000000 +#define D18F2x9C_x0000_000B_dct0_DynModeChange_OFFSET 31 +#define D18F2x9C_x0000_000B_dct0_DynModeChange_WIDTH 1 +#define D18F2x9C_x0000_000B_dct0_DynModeChange_MASK 0x80000000 + +/// D18F2x9C_x0000_000B_dct0 +typedef union { + struct { ///< + UINT32 Reserved_22_0:23; ///< + UINT32 PhySelfRefreshMode:1 ; ///< + UINT32 Reserved_25_24:2 ; ///< + UINT32 PhyPS:1 ; ///< + UINT32 Reserved_29_27:3 ; ///< + UINT32 PhyPSReq:1 ; ///< + UINT32 DynModeChange:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_000B_dct0_STRUCT; + +// **** D18F2x9C_x0000_000B_dct1 Register Definition **** +// Address +#define D18F2x9C_x0000_000B_dct1_ADDRESS 0xb + +// Type +#define D18F2x9C_x0000_000B_dct1_TYPE TYPE_D18F2x9C_dct1 +// Field Data +#define D18F2x9C_x0000_000B_dct1_Reserved_22_0_OFFSET 0 +#define D18F2x9C_x0000_000B_dct1_Reserved_22_0_WIDTH 23 +#define D18F2x9C_x0000_000B_dct1_Reserved_22_0_MASK 0x7fffff +#define D18F2x9C_x0000_000B_dct1_PhySelfRefreshMode_OFFSET 23 +#define D18F2x9C_x0000_000B_dct1_PhySelfRefreshMode_WIDTH 1 +#define D18F2x9C_x0000_000B_dct1_PhySelfRefreshMode_MASK 0x800000 +#define D18F2x9C_x0000_000B_dct1_Reserved_25_24_OFFSET 24 +#define D18F2x9C_x0000_000B_dct1_Reserved_25_24_WIDTH 2 +#define D18F2x9C_x0000_000B_dct1_Reserved_25_24_MASK 0x3000000 +#define D18F2x9C_x0000_000B_dct1_PhyPS_OFFSET 26 +#define D18F2x9C_x0000_000B_dct1_PhyPS_WIDTH 1 +#define D18F2x9C_x0000_000B_dct1_PhyPS_MASK 0x4000000 +#define D18F2x9C_x0000_000B_dct1_Reserved_29_27_OFFSET 27 +#define D18F2x9C_x0000_000B_dct1_Reserved_29_27_WIDTH 3 +#define D18F2x9C_x0000_000B_dct1_Reserved_29_27_MASK 0x38000000 +#define D18F2x9C_x0000_000B_dct1_PhyPSReq_OFFSET 30 +#define D18F2x9C_x0000_000B_dct1_PhyPSReq_WIDTH 1 +#define D18F2x9C_x0000_000B_dct1_PhyPSReq_MASK 0x40000000 +#define D18F2x9C_x0000_000B_dct1_DynModeChange_OFFSET 31 +#define D18F2x9C_x0000_000B_dct1_DynModeChange_WIDTH 1 +#define D18F2x9C_x0000_000B_dct1_DynModeChange_MASK 0x80000000 + +/// D18F2x9C_x0000_000B_dct1 +typedef union { + struct { ///< + UINT32 Reserved_22_0:23; ///< + UINT32 PhySelfRefreshMode:1 ; ///< + UINT32 Reserved_25_24:2 ; ///< + UINT32 PhyPS:1 ; ///< + UINT32 Reserved_29_27:3 ; ///< + UINT32 PhyPSReq:1 ; ///< + UINT32 DynModeChange:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_000B_dct1_STRUCT; + +// **** D18F2x9C_x0000_000C_dct1 Register Definition **** +// Address +#define D18F2x9C_x0000_000C_dct1_ADDRESS 0xc + +// Type +#define D18F2x9C_x0000_000C_dct1_TYPE TYPE_D18F2x9C_dct1 +// Field Data +#define D18F2x9C_x0000_000C_dct1_ChipSelTri_OFFSET 0 +#define D18F2x9C_x0000_000C_dct1_ChipSelTri_WIDTH 8 +#define D18F2x9C_x0000_000C_dct1_ChipSelTri_MASK 0xff +#define D18F2x9C_x0000_000C_dct1_ODTTri_OFFSET 8 +#define D18F2x9C_x0000_000C_dct1_ODTTri_WIDTH 4 +#define D18F2x9C_x0000_000C_dct1_ODTTri_MASK 0xf00 +#define D18F2x9C_x0000_000C_dct1_CKETri_OFFSET 12 +#define D18F2x9C_x0000_000C_dct1_CKETri_WIDTH 4 +#define D18F2x9C_x0000_000C_dct1_CKETri_MASK 0xf000 +#define D18F2x9C_x0000_000C_dct1_FenceThresholdTxPad_OFFSET 16 +#define D18F2x9C_x0000_000C_dct1_FenceThresholdTxPad_WIDTH 5 +#define D18F2x9C_x0000_000C_dct1_FenceThresholdTxPad_MASK 0x1f0000 +#define D18F2x9C_x0000_000C_dct1_FenceThresholdRxDll_OFFSET 21 +#define D18F2x9C_x0000_000C_dct1_FenceThresholdRxDll_WIDTH 5 +#define D18F2x9C_x0000_000C_dct1_FenceThresholdRxDll_MASK 0x3e00000 +#define D18F2x9C_x0000_000C_dct1_FenceThresholdTxDll_OFFSET 26 +#define D18F2x9C_x0000_000C_dct1_FenceThresholdTxDll_WIDTH 5 +#define D18F2x9C_x0000_000C_dct1_FenceThresholdTxDll_MASK 0x7c000000 +#define D18F2x9C_x0000_000C_dct1_Reserved_31_31_OFFSET 31 +#define D18F2x9C_x0000_000C_dct1_Reserved_31_31_WIDTH 1 +#define D18F2x9C_x0000_000C_dct1_Reserved_31_31_MASK 0x80000000 + +/// D18F2x9C_x0000_000C_dct1 +typedef union { + struct { ///< + UINT32 ChipSelTri:8 ; ///< + UINT32 ODTTri:4 ; ///< + UINT32 CKETri:4 ; ///< + UINT32 FenceThresholdTxPad:5 ; ///< + UINT32 FenceThresholdRxDll:5 ; ///< + UINT32 FenceThresholdTxDll:5 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_000C_dct1_STRUCT; + +// **** D18F2x9C_x0000_000C_dct0 Register Definition **** +// Address +#define D18F2x9C_x0000_000C_dct0_ADDRESS 0xc + +// Type +#define D18F2x9C_x0000_000C_dct0_TYPE TYPE_D18F2x9C_dct0 +// Field Data +#define D18F2x9C_x0000_000C_dct0_ChipSelTri_OFFSET 0 +#define D18F2x9C_x0000_000C_dct0_ChipSelTri_WIDTH 8 +#define D18F2x9C_x0000_000C_dct0_ChipSelTri_MASK 0xff +#define D18F2x9C_x0000_000C_dct0_ODTTri_OFFSET 8 +#define D18F2x9C_x0000_000C_dct0_ODTTri_WIDTH 4 +#define D18F2x9C_x0000_000C_dct0_ODTTri_MASK 0xf00 +#define D18F2x9C_x0000_000C_dct0_CKETri_OFFSET 12 +#define D18F2x9C_x0000_000C_dct0_CKETri_WIDTH 4 +#define D18F2x9C_x0000_000C_dct0_CKETri_MASK 0xf000 +#define D18F2x9C_x0000_000C_dct0_FenceThresholdTxPad_OFFSET 16 +#define D18F2x9C_x0000_000C_dct0_FenceThresholdTxPad_WIDTH 5 +#define D18F2x9C_x0000_000C_dct0_FenceThresholdTxPad_MASK 0x1f0000 +#define D18F2x9C_x0000_000C_dct0_FenceThresholdRxDll_OFFSET 21 +#define D18F2x9C_x0000_000C_dct0_FenceThresholdRxDll_WIDTH 5 +#define D18F2x9C_x0000_000C_dct0_FenceThresholdRxDll_MASK 0x3e00000 +#define D18F2x9C_x0000_000C_dct0_FenceThresholdTxDll_OFFSET 26 +#define D18F2x9C_x0000_000C_dct0_FenceThresholdTxDll_WIDTH 5 +#define D18F2x9C_x0000_000C_dct0_FenceThresholdTxDll_MASK 0x7c000000 +#define D18F2x9C_x0000_000C_dct0_Reserved_31_31_OFFSET 31 +#define D18F2x9C_x0000_000C_dct0_Reserved_31_31_WIDTH 1 +#define D18F2x9C_x0000_000C_dct0_Reserved_31_31_MASK 0x80000000 + +/// D18F2x9C_x0000_000C_dct0 +typedef union { + struct { ///< + UINT32 ChipSelTri:8 ; ///< + UINT32 ODTTri:4 ; ///< + UINT32 CKETri:4 ; ///< + UINT32 FenceThresholdTxPad:5 ; ///< + UINT32 FenceThresholdRxDll:5 ; ///< + UINT32 FenceThresholdTxDll:5 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_000C_dct0_STRUCT; + +// **** D18F2x9C_x0000_000D_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_000D_dct0_mp1_ADDRESS 0xd + +// Type +#define D18F2x9C_x0000_000D_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_000D_dct0_mp1_TxMaxDurDllNoLock_OFFSET 0 +#define D18F2x9C_x0000_000D_dct0_mp1_TxMaxDurDllNoLock_WIDTH 4 +#define D18F2x9C_x0000_000D_dct0_mp1_TxMaxDurDllNoLock_MASK 0xf +#define D18F2x9C_x0000_000D_dct0_mp1_TxCPUpdPeriod_OFFSET 4 +#define D18F2x9C_x0000_000D_dct0_mp1_TxCPUpdPeriod_WIDTH 3 +#define D18F2x9C_x0000_000D_dct0_mp1_TxCPUpdPeriod_MASK 0x70 +#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_7_7_OFFSET 7 +#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_7_7_WIDTH 1 +#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_7_7_MASK 0x80 +#define D18F2x9C_x0000_000D_dct0_mp1_TxDLLWakeupTime_OFFSET 8 +#define D18F2x9C_x0000_000D_dct0_mp1_TxDLLWakeupTime_WIDTH 2 +#define D18F2x9C_x0000_000D_dct0_mp1_TxDLLWakeupTime_MASK 0x300 +#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_000D_dct0_mp1_RxMaxDurDllNoLock_OFFSET 16 +#define D18F2x9C_x0000_000D_dct0_mp1_RxMaxDurDllNoLock_WIDTH 4 +#define D18F2x9C_x0000_000D_dct0_mp1_RxMaxDurDllNoLock_MASK 0xf0000 +#define D18F2x9C_x0000_000D_dct0_mp1_RxCPUpdPeriod_OFFSET 20 +#define D18F2x9C_x0000_000D_dct0_mp1_RxCPUpdPeriod_WIDTH 3 +#define D18F2x9C_x0000_000D_dct0_mp1_RxCPUpdPeriod_MASK 0x700000 +#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_23_23_OFFSET 23 +#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_23_23_WIDTH 1 +#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_23_23_MASK 0x800000 +#define D18F2x9C_x0000_000D_dct0_mp1_RxDLLWakeupTime_OFFSET 24 +#define D18F2x9C_x0000_000D_dct0_mp1_RxDLLWakeupTime_WIDTH 2 +#define D18F2x9C_x0000_000D_dct0_mp1_RxDLLWakeupTime_MASK 0x3000000 +#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_000D_dct0_mp1 +typedef union { + struct { ///< + UINT32 TxMaxDurDllNoLock:4 ; ///< + UINT32 TxCPUpdPeriod:3 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 TxDLLWakeupTime:2 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 RxMaxDurDllNoLock:4 ; ///< + UINT32 RxCPUpdPeriod:3 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 RxDLLWakeupTime:2 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_000D_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_000D_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_000D_dct1_mp1_ADDRESS 0xd + +// Type +#define D18F2x9C_x0000_000D_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_000D_dct1_mp1_TxMaxDurDllNoLock_OFFSET 0 +#define D18F2x9C_x0000_000D_dct1_mp1_TxMaxDurDllNoLock_WIDTH 4 +#define D18F2x9C_x0000_000D_dct1_mp1_TxMaxDurDllNoLock_MASK 0xf +#define D18F2x9C_x0000_000D_dct1_mp1_TxCPUpdPeriod_OFFSET 4 +#define D18F2x9C_x0000_000D_dct1_mp1_TxCPUpdPeriod_WIDTH 3 +#define D18F2x9C_x0000_000D_dct1_mp1_TxCPUpdPeriod_MASK 0x70 +#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_7_7_OFFSET 7 +#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_7_7_WIDTH 1 +#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_7_7_MASK 0x80 +#define D18F2x9C_x0000_000D_dct1_mp1_TxDLLWakeupTime_OFFSET 8 +#define D18F2x9C_x0000_000D_dct1_mp1_TxDLLWakeupTime_WIDTH 2 +#define D18F2x9C_x0000_000D_dct1_mp1_TxDLLWakeupTime_MASK 0x300 +#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_000D_dct1_mp1_RxMaxDurDllNoLock_OFFSET 16 +#define D18F2x9C_x0000_000D_dct1_mp1_RxMaxDurDllNoLock_WIDTH 4 +#define D18F2x9C_x0000_000D_dct1_mp1_RxMaxDurDllNoLock_MASK 0xf0000 +#define D18F2x9C_x0000_000D_dct1_mp1_RxCPUpdPeriod_OFFSET 20 +#define D18F2x9C_x0000_000D_dct1_mp1_RxCPUpdPeriod_WIDTH 3 +#define D18F2x9C_x0000_000D_dct1_mp1_RxCPUpdPeriod_MASK 0x700000 +#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_23_23_OFFSET 23 +#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_23_23_WIDTH 1 +#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_23_23_MASK 0x800000 +#define D18F2x9C_x0000_000D_dct1_mp1_RxDLLWakeupTime_OFFSET 24 +#define D18F2x9C_x0000_000D_dct1_mp1_RxDLLWakeupTime_WIDTH 2 +#define D18F2x9C_x0000_000D_dct1_mp1_RxDLLWakeupTime_MASK 0x3000000 +#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_000D_dct1_mp1 +typedef union { + struct { ///< + UINT32 TxMaxDurDllNoLock:4 ; ///< + UINT32 TxCPUpdPeriod:3 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 TxDLLWakeupTime:2 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 RxMaxDurDllNoLock:4 ; ///< + UINT32 RxCPUpdPeriod:3 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 RxDLLWakeupTime:2 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_000D_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_000D_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_000D_dct0_mp0_ADDRESS 0xd + +// Type +#define D18F2x9C_x0000_000D_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_000D_dct0_mp0_TxMaxDurDllNoLock_OFFSET 0 +#define D18F2x9C_x0000_000D_dct0_mp0_TxMaxDurDllNoLock_WIDTH 4 +#define D18F2x9C_x0000_000D_dct0_mp0_TxMaxDurDllNoLock_MASK 0xf +#define D18F2x9C_x0000_000D_dct0_mp0_TxCPUpdPeriod_OFFSET 4 +#define D18F2x9C_x0000_000D_dct0_mp0_TxCPUpdPeriod_WIDTH 3 +#define D18F2x9C_x0000_000D_dct0_mp0_TxCPUpdPeriod_MASK 0x70 +#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_7_7_OFFSET 7 +#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_7_7_WIDTH 1 +#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_7_7_MASK 0x80 +#define D18F2x9C_x0000_000D_dct0_mp0_TxDLLWakeupTime_OFFSET 8 +#define D18F2x9C_x0000_000D_dct0_mp0_TxDLLWakeupTime_WIDTH 2 +#define D18F2x9C_x0000_000D_dct0_mp0_TxDLLWakeupTime_MASK 0x300 +#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_000D_dct0_mp0_RxMaxDurDllNoLock_OFFSET 16 +#define D18F2x9C_x0000_000D_dct0_mp0_RxMaxDurDllNoLock_WIDTH 4 +#define D18F2x9C_x0000_000D_dct0_mp0_RxMaxDurDllNoLock_MASK 0xf0000 +#define D18F2x9C_x0000_000D_dct0_mp0_RxCPUpdPeriod_OFFSET 20 +#define D18F2x9C_x0000_000D_dct0_mp0_RxCPUpdPeriod_WIDTH 3 +#define D18F2x9C_x0000_000D_dct0_mp0_RxCPUpdPeriod_MASK 0x700000 +#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_23_23_OFFSET 23 +#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_23_23_WIDTH 1 +#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_23_23_MASK 0x800000 +#define D18F2x9C_x0000_000D_dct0_mp0_RxDLLWakeupTime_OFFSET 24 +#define D18F2x9C_x0000_000D_dct0_mp0_RxDLLWakeupTime_WIDTH 2 +#define D18F2x9C_x0000_000D_dct0_mp0_RxDLLWakeupTime_MASK 0x3000000 +#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_000D_dct0_mp0 +typedef union { + struct { ///< + UINT32 TxMaxDurDllNoLock:4 ; ///< + UINT32 TxCPUpdPeriod:3 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 TxDLLWakeupTime:2 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 RxMaxDurDllNoLock:4 ; ///< + UINT32 RxCPUpdPeriod:3 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 RxDLLWakeupTime:2 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_000D_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_000D_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_000D_dct1_mp0_ADDRESS 0xd + +// Type +#define D18F2x9C_x0000_000D_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_000D_dct1_mp0_TxMaxDurDllNoLock_OFFSET 0 +#define D18F2x9C_x0000_000D_dct1_mp0_TxMaxDurDllNoLock_WIDTH 4 +#define D18F2x9C_x0000_000D_dct1_mp0_TxMaxDurDllNoLock_MASK 0xf +#define D18F2x9C_x0000_000D_dct1_mp0_TxCPUpdPeriod_OFFSET 4 +#define D18F2x9C_x0000_000D_dct1_mp0_TxCPUpdPeriod_WIDTH 3 +#define D18F2x9C_x0000_000D_dct1_mp0_TxCPUpdPeriod_MASK 0x70 +#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_7_7_OFFSET 7 +#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_7_7_WIDTH 1 +#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_7_7_MASK 0x80 +#define D18F2x9C_x0000_000D_dct1_mp0_TxDLLWakeupTime_OFFSET 8 +#define D18F2x9C_x0000_000D_dct1_mp0_TxDLLWakeupTime_WIDTH 2 +#define D18F2x9C_x0000_000D_dct1_mp0_TxDLLWakeupTime_MASK 0x300 +#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_000D_dct1_mp0_RxMaxDurDllNoLock_OFFSET 16 +#define D18F2x9C_x0000_000D_dct1_mp0_RxMaxDurDllNoLock_WIDTH 4 +#define D18F2x9C_x0000_000D_dct1_mp0_RxMaxDurDllNoLock_MASK 0xf0000 +#define D18F2x9C_x0000_000D_dct1_mp0_RxCPUpdPeriod_OFFSET 20 +#define D18F2x9C_x0000_000D_dct1_mp0_RxCPUpdPeriod_WIDTH 3 +#define D18F2x9C_x0000_000D_dct1_mp0_RxCPUpdPeriod_MASK 0x700000 +#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_23_23_OFFSET 23 +#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_23_23_WIDTH 1 +#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_23_23_MASK 0x800000 +#define D18F2x9C_x0000_000D_dct1_mp0_RxDLLWakeupTime_OFFSET 24 +#define D18F2x9C_x0000_000D_dct1_mp0_RxDLLWakeupTime_WIDTH 2 +#define D18F2x9C_x0000_000D_dct1_mp0_RxDLLWakeupTime_MASK 0x3000000 +#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_000D_dct1_mp0 +typedef union { + struct { ///< + UINT32 TxMaxDurDllNoLock:4 ; ///< + UINT32 TxCPUpdPeriod:3 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 TxDLLWakeupTime:2 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 RxMaxDurDllNoLock:4 ; ///< + UINT32 RxCPUpdPeriod:3 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 RxDLLWakeupTime:2 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_000D_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0010_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0010_dct0_mp1_ADDRESS 0x10 + +// Type +#define D18F2x9C_x0000_0010_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0010_dct0_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0010_dct0_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0010_dct0_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0010_dct0_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0010_dct0_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0010_dct0_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0010_dct0_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0010_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0010_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0010_dct1_mp0_ADDRESS 0x10 + +// Type +#define D18F2x9C_x0000_0010_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0010_dct1_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0010_dct1_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0010_dct1_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0010_dct1_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0010_dct1_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0010_dct1_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0010_dct1_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0010_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0010_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0010_dct0_mp0_ADDRESS 0x10 + +// Type +#define D18F2x9C_x0000_0010_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0010_dct0_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0010_dct0_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0010_dct0_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0010_dct0_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0010_dct0_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0010_dct0_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0010_dct0_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0010_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0010_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0010_dct1_mp1_ADDRESS 0x10 + +// Type +#define D18F2x9C_x0000_0010_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0010_dct1_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0010_dct1_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0010_dct1_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0010_dct1_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0010_dct1_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0010_dct1_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0010_dct1_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0010_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0011_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0011_dct1_mp0_ADDRESS 0x11 + +// Type +#define D18F2x9C_x0000_0011_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0011_dct1_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0011_dct1_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0011_dct1_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0011_dct1_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0011_dct1_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0011_dct1_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0011_dct1_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0011_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0011_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0011_dct1_mp1_ADDRESS 0x11 + +// Type +#define D18F2x9C_x0000_0011_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0011_dct1_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0011_dct1_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0011_dct1_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0011_dct1_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0011_dct1_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0011_dct1_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0011_dct1_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0011_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0011_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0011_dct0_mp0_ADDRESS 0x11 + +// Type +#define D18F2x9C_x0000_0011_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0011_dct0_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0011_dct0_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0011_dct0_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0011_dct0_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0011_dct0_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0011_dct0_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0011_dct0_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0011_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0011_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0011_dct0_mp1_ADDRESS 0x11 + +// Type +#define D18F2x9C_x0000_0011_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0011_dct0_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0011_dct0_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0011_dct0_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0011_dct0_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0011_dct0_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0011_dct0_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0011_dct0_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0011_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0013_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0013_dct1_mp1_ADDRESS 0x13 + +// Type +#define D18F2x9C_x0000_0013_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0013_dct1_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0013_dct1_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0013_dct1_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0013_dct1_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0013_dct1_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0013_dct1_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0013_dct1_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0013_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0013_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0013_dct1_mp0_ADDRESS 0x13 + +// Type +#define D18F2x9C_x0000_0013_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0013_dct1_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0013_dct1_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0013_dct1_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0013_dct1_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0013_dct1_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0013_dct1_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0013_dct1_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0013_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0013_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0013_dct0_mp0_ADDRESS 0x13 + +// Type +#define D18F2x9C_x0000_0013_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0013_dct0_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0013_dct0_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0013_dct0_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0013_dct0_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0013_dct0_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0013_dct0_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0013_dct0_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0013_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0013_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0013_dct0_mp1_ADDRESS 0x13 + +// Type +#define D18F2x9C_x0000_0013_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0013_dct0_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0013_dct0_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0013_dct0_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0013_dct0_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0013_dct0_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0013_dct0_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0013_dct0_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0013_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0014_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0014_dct1_mp0_ADDRESS 0x14 + +// Type +#define D18F2x9C_x0000_0014_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0014_dct1_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0014_dct1_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0014_dct1_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0014_dct1_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0014_dct1_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0014_dct1_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0014_dct1_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0014_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0014_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0014_dct0_mp1_ADDRESS 0x14 + +// Type +#define D18F2x9C_x0000_0014_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0014_dct0_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0014_dct0_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0014_dct0_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0014_dct0_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0014_dct0_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0014_dct0_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0014_dct0_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0014_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0014_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0014_dct0_mp0_ADDRESS 0x14 + +// Type +#define D18F2x9C_x0000_0014_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0014_dct0_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0014_dct0_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0014_dct0_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0014_dct0_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0014_dct0_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0014_dct0_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0014_dct0_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0014_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0014_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0014_dct1_mp1_ADDRESS 0x14 + +// Type +#define D18F2x9C_x0000_0014_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0014_dct1_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0014_dct1_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0014_dct1_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0014_dct1_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0014_dct1_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0014_dct1_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0014_dct1_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0014_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0016_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0016_dct0_mp0_ADDRESS 0x16 + +// Type +#define D18F2x9C_x0000_0016_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0016_dct0_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0016_dct0_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0016_dct0_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0016_dct0_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0016_dct0_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0016_dct0_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0016_dct0_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0016_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0016_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0016_dct1_mp1_ADDRESS 0x16 + +// Type +#define D18F2x9C_x0000_0016_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0016_dct1_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0016_dct1_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0016_dct1_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0016_dct1_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0016_dct1_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0016_dct1_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0016_dct1_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0016_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0016_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0016_dct1_mp0_ADDRESS 0x16 + +// Type +#define D18F2x9C_x0000_0016_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0016_dct1_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0016_dct1_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0016_dct1_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0016_dct1_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0016_dct1_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0016_dct1_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0016_dct1_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0016_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0016_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0016_dct0_mp1_ADDRESS 0x16 + +// Type +#define D18F2x9C_x0000_0016_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0016_dct0_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0016_dct0_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0016_dct0_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0016_dct0_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0016_dct0_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0016_dct0_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0016_dct0_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0016_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0017_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0017_dct0_mp1_ADDRESS 0x17 + +// Type +#define D18F2x9C_x0000_0017_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0017_dct0_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0017_dct0_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0017_dct0_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0017_dct0_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0017_dct0_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0017_dct0_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0017_dct0_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0017_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0017_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0017_dct0_mp0_ADDRESS 0x17 + +// Type +#define D18F2x9C_x0000_0017_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0017_dct0_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0017_dct0_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0017_dct0_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0017_dct0_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0017_dct0_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0017_dct0_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0017_dct0_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0017_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0017_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0017_dct1_mp1_ADDRESS 0x17 + +// Type +#define D18F2x9C_x0000_0017_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0017_dct1_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0017_dct1_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0017_dct1_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0017_dct1_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0017_dct1_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0017_dct1_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0017_dct1_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0017_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0017_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0017_dct1_mp0_ADDRESS 0x17 + +// Type +#define D18F2x9C_x0000_0017_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0017_dct1_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0017_dct1_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0017_dct1_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0017_dct1_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0017_dct1_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0017_dct1_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0017_dct1_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0017_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0019_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0019_dct1_mp0_ADDRESS 0x19 + +// Type +#define D18F2x9C_x0000_0019_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0019_dct1_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0019_dct1_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0019_dct1_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0019_dct1_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0019_dct1_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0019_dct1_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0019_dct1_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0019_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0019_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0019_dct0_mp0_ADDRESS 0x19 + +// Type +#define D18F2x9C_x0000_0019_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0019_dct0_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0019_dct0_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0019_dct0_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0019_dct0_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0019_dct0_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0019_dct0_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0019_dct0_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0019_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0019_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0019_dct0_mp1_ADDRESS 0x19 + +// Type +#define D18F2x9C_x0000_0019_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0019_dct0_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0019_dct0_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0019_dct0_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0019_dct0_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0019_dct0_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0019_dct0_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0019_dct0_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0019_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0019_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0019_dct1_mp1_ADDRESS 0x19 + +// Type +#define D18F2x9C_x0000_0019_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0019_dct1_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0019_dct1_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0019_dct1_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0019_dct1_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0019_dct1_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0019_dct1_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0019_dct1_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0019_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_001A_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_001A_dct1_mp1_ADDRESS 0x1a + +// Type +#define D18F2x9C_x0000_001A_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_001A_dct1_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_001A_dct1_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_001A_dct1_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_001A_dct1_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_001A_dct1_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_001A_dct1_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_001A_dct1_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_001A_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_001A_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_001A_dct1_mp0_ADDRESS 0x1a + +// Type +#define D18F2x9C_x0000_001A_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_001A_dct1_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_001A_dct1_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_001A_dct1_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_001A_dct1_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_001A_dct1_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_001A_dct1_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_001A_dct1_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_001A_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_001A_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_001A_dct0_mp1_ADDRESS 0x1a + +// Type +#define D18F2x9C_x0000_001A_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_001A_dct0_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_001A_dct0_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_001A_dct0_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_001A_dct0_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_001A_dct0_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_001A_dct0_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_001A_dct0_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_001A_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_001A_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_001A_dct0_mp0_ADDRESS 0x1a + +// Type +#define D18F2x9C_x0000_001A_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_001A_dct0_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_001A_dct0_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_001A_dct0_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_001A_dct0_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_001A_dct0_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_001A_dct0_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_001A_dct0_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_001A_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0020_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0020_dct0_mp1_ADDRESS 0x20 + +// Type +#define D18F2x9C_x0000_0020_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0020_dct0_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0020_dct0_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0020_dct0_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0020_dct0_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0020_dct0_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0020_dct0_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0020_dct0_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0020_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0020_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0020_dct1_mp0_ADDRESS 0x20 + +// Type +#define D18F2x9C_x0000_0020_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0020_dct1_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0020_dct1_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0020_dct1_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0020_dct1_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0020_dct1_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0020_dct1_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0020_dct1_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0020_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0020_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0020_dct1_mp1_ADDRESS 0x20 + +// Type +#define D18F2x9C_x0000_0020_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0020_dct1_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0020_dct1_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0020_dct1_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0020_dct1_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0020_dct1_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0020_dct1_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0020_dct1_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0020_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0020_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0020_dct0_mp0_ADDRESS 0x20 + +// Type +#define D18F2x9C_x0000_0020_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0020_dct0_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0020_dct0_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0020_dct0_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0020_dct0_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0020_dct0_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0020_dct0_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0020_dct0_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0020_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0021_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0021_dct0_mp1_ADDRESS 0x21 + +// Type +#define D18F2x9C_x0000_0021_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0021_dct0_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0021_dct0_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0021_dct0_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0021_dct0_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0021_dct0_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0021_dct0_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0021_dct0_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0021_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0021_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0021_dct1_mp0_ADDRESS 0x21 + +// Type +#define D18F2x9C_x0000_0021_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0021_dct1_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0021_dct1_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0021_dct1_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0021_dct1_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0021_dct1_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0021_dct1_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0021_dct1_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0021_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0021_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0021_dct1_mp1_ADDRESS 0x21 + +// Type +#define D18F2x9C_x0000_0021_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0021_dct1_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0021_dct1_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0021_dct1_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0021_dct1_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0021_dct1_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0021_dct1_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0021_dct1_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0021_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0021_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0021_dct0_mp0_ADDRESS 0x21 + +// Type +#define D18F2x9C_x0000_0021_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0021_dct0_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0021_dct0_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0021_dct0_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0021_dct0_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0021_dct0_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0021_dct0_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0021_dct0_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0021_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0023_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0023_dct0_mp1_ADDRESS 0x23 + +// Type +#define D18F2x9C_x0000_0023_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0023_dct0_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0023_dct0_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0023_dct0_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0023_dct0_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0023_dct0_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0023_dct0_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0023_dct0_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0023_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0023_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0023_dct1_mp0_ADDRESS 0x23 + +// Type +#define D18F2x9C_x0000_0023_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0023_dct1_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0023_dct1_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0023_dct1_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0023_dct1_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0023_dct1_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0023_dct1_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0023_dct1_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0023_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0023_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0023_dct1_mp1_ADDRESS 0x23 + +// Type +#define D18F2x9C_x0000_0023_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0023_dct1_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0023_dct1_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0023_dct1_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0023_dct1_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0023_dct1_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0023_dct1_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0023_dct1_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0023_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0023_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0023_dct0_mp0_ADDRESS 0x23 + +// Type +#define D18F2x9C_x0000_0023_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0023_dct0_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0023_dct0_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0023_dct0_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0023_dct0_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0023_dct0_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0023_dct0_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0023_dct0_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0023_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0024_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0024_dct1_mp1_ADDRESS 0x24 + +// Type +#define D18F2x9C_x0000_0024_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0024_dct1_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0024_dct1_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0024_dct1_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0024_dct1_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0024_dct1_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0024_dct1_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0024_dct1_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0024_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0024_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0024_dct1_mp0_ADDRESS 0x24 + +// Type +#define D18F2x9C_x0000_0024_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0024_dct1_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0024_dct1_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0024_dct1_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0024_dct1_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0024_dct1_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0024_dct1_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0024_dct1_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0024_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0024_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0024_dct0_mp1_ADDRESS 0x24 + +// Type +#define D18F2x9C_x0000_0024_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0024_dct0_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0024_dct0_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0024_dct0_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0024_dct0_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0024_dct0_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0024_dct0_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0024_dct0_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0024_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0024_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0024_dct0_mp0_ADDRESS 0x24 + +// Type +#define D18F2x9C_x0000_0024_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0024_dct0_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0024_dct0_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0024_dct0_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0024_dct0_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0024_dct0_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0024_dct0_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0024_dct0_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0024_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0026_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0026_dct1_mp0_ADDRESS 0x26 + +// Type +#define D18F2x9C_x0000_0026_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0026_dct1_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0026_dct1_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0026_dct1_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0026_dct1_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0026_dct1_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0026_dct1_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0026_dct1_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0026_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0026_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0026_dct0_mp0_ADDRESS 0x26 + +// Type +#define D18F2x9C_x0000_0026_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0026_dct0_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0026_dct0_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0026_dct0_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0026_dct0_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0026_dct0_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0026_dct0_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0026_dct0_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0026_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0026_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0026_dct1_mp1_ADDRESS 0x26 + +// Type +#define D18F2x9C_x0000_0026_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0026_dct1_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0026_dct1_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0026_dct1_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0026_dct1_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0026_dct1_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0026_dct1_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0026_dct1_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0026_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0026_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0026_dct0_mp1_ADDRESS 0x26 + +// Type +#define D18F2x9C_x0000_0026_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0026_dct0_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0026_dct0_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0026_dct0_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0026_dct0_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0026_dct0_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0026_dct0_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0026_dct0_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0026_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0027_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0027_dct0_mp1_ADDRESS 0x27 + +// Type +#define D18F2x9C_x0000_0027_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0027_dct0_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0027_dct0_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0027_dct0_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0027_dct0_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0027_dct0_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0027_dct0_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0027_dct0_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0027_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0027_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0027_dct1_mp0_ADDRESS 0x27 + +// Type +#define D18F2x9C_x0000_0027_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0027_dct1_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0027_dct1_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0027_dct1_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0027_dct1_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0027_dct1_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0027_dct1_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0027_dct1_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0027_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0027_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0027_dct0_mp0_ADDRESS 0x27 + +// Type +#define D18F2x9C_x0000_0027_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0027_dct0_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0027_dct0_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0027_dct0_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0027_dct0_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0027_dct0_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0027_dct0_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0027_dct0_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0027_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0027_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0027_dct1_mp1_ADDRESS 0x27 + +// Type +#define D18F2x9C_x0000_0027_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0027_dct1_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0027_dct1_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0027_dct1_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0027_dct1_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0027_dct1_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0027_dct1_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0027_dct1_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0027_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0029_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0029_dct0_mp0_ADDRESS 0x29 + +// Type +#define D18F2x9C_x0000_0029_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0029_dct0_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0029_dct0_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0029_dct0_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0029_dct0_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0029_dct0_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0029_dct0_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0029_dct0_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0029_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0029_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0029_dct0_mp1_ADDRESS 0x29 + +// Type +#define D18F2x9C_x0000_0029_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0029_dct0_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0029_dct0_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0029_dct0_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0029_dct0_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0029_dct0_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0029_dct0_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0029_dct0_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0029_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0029_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0029_dct1_mp0_ADDRESS 0x29 + +// Type +#define D18F2x9C_x0000_0029_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0029_dct1_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0029_dct1_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0029_dct1_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0029_dct1_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0029_dct1_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0029_dct1_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0029_dct1_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0029_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0029_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0029_dct1_mp1_ADDRESS 0x29 + +// Type +#define D18F2x9C_x0000_0029_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_0029_dct1_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_0029_dct1_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_0029_dct1_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_0029_dct1_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_0029_dct1_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_0029_dct1_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_0029_dct1_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0029_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_002A_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_002A_dct1_mp1_ADDRESS 0x2a + +// Type +#define D18F2x9C_x0000_002A_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_002A_dct1_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_002A_dct1_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_002A_dct1_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_002A_dct1_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_002A_dct1_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_002A_dct1_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_002A_dct1_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_002A_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_002A_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_002A_dct0_mp0_ADDRESS 0x2a + +// Type +#define D18F2x9C_x0000_002A_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_002A_dct0_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_002A_dct0_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_002A_dct0_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_002A_dct0_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_002A_dct0_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_002A_dct0_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_002A_dct0_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_002A_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_002A_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_002A_dct1_mp0_ADDRESS 0x2a + +// Type +#define D18F2x9C_x0000_002A_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_002A_dct1_mp0_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_002A_dct1_mp0_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_002A_dct1_mp0_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_002A_dct1_mp0_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_002A_dct1_mp0_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_002A_dct1_mp0_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_002A_dct1_mp0 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_002A_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_002A_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_002A_dct0_mp1_ADDRESS 0x2a + +// Type +#define D18F2x9C_x0000_002A_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnFineDelay_OFFSET 0 +#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnFineDelay_WIDTH 5 +#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnFineDelay_MASK 0x1f +#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnGrossDelay_OFFSET 5 +#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnGrossDelay_WIDTH 5 +#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnGrossDelay_MASK 0x3e0 +#define D18F2x9C_x0000_002A_dct0_mp1_Reserved_15_10_OFFSET 10 +#define D18F2x9C_x0000_002A_dct0_mp1_Reserved_15_10_WIDTH 6 +#define D18F2x9C_x0000_002A_dct0_mp1_Reserved_15_10_MASK 0xfc00 +#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnFineDelay1_OFFSET 16 +#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnFineDelay1_WIDTH 5 +#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnFineDelay1_MASK 0x1f0000 +#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21 +#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH 5 +#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnGrossDelay1_MASK 0x3e00000 +#define D18F2x9C_x0000_002A_dct0_mp1_Reserved_31_26_OFFSET 26 +#define D18F2x9C_x0000_002A_dct0_mp1_Reserved_31_26_WIDTH 6 +#define D18F2x9C_x0000_002A_dct0_mp1_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x9C_x0000_002A_dct0_mp1 +typedef union { + struct { ///< + UINT32 DqsRcvEnFineDelay:5 ; ///< + UINT32 DqsRcvEnGrossDelay:5 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 DqsRcvEnFineDelay1:5 ; ///< + UINT32 DqsRcvEnGrossDelay1:5 ; ///< + UINT32 Reserved_31_26:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_002A_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0030_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0030_dct1_mp1_ADDRESS 0x30 + +// Type +#define D18F2x9C_x0000_0030_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0030_dct1_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0030_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0030_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0030_dct0_mp1_ADDRESS 0x30 + +// Type +#define D18F2x9C_x0000_0030_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0030_dct0_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0030_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0030_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0030_dct0_mp0_ADDRESS 0x30 + +// Type +#define D18F2x9C_x0000_0030_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0030_dct0_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0030_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0030_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0030_dct1_mp0_ADDRESS 0x30 + +// Type +#define D18F2x9C_x0000_0030_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0030_dct1_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0030_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0031_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0031_dct0_mp0_ADDRESS 0x31 + +// Type +#define D18F2x9C_x0000_0031_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0031_dct0_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0031_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0031_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0031_dct0_mp1_ADDRESS 0x31 + +// Type +#define D18F2x9C_x0000_0031_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0031_dct0_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0031_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0031_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0031_dct1_mp0_ADDRESS 0x31 + +// Type +#define D18F2x9C_x0000_0031_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0031_dct1_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0031_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0031_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0031_dct1_mp1_ADDRESS 0x31 + +// Type +#define D18F2x9C_x0000_0031_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0031_dct1_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0031_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0033_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0033_dct1_mp1_ADDRESS 0x33 + +// Type +#define D18F2x9C_x0000_0033_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0033_dct1_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0033_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0033_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0033_dct1_mp0_ADDRESS 0x33 + +// Type +#define D18F2x9C_x0000_0033_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0033_dct1_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0033_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0033_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0033_dct0_mp0_ADDRESS 0x33 + +// Type +#define D18F2x9C_x0000_0033_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0033_dct0_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0033_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0033_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0033_dct0_mp1_ADDRESS 0x33 + +// Type +#define D18F2x9C_x0000_0033_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0033_dct0_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0033_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0034_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0034_dct0_mp0_ADDRESS 0x34 + +// Type +#define D18F2x9C_x0000_0034_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0034_dct0_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0034_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0034_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0034_dct1_mp1_ADDRESS 0x34 + +// Type +#define D18F2x9C_x0000_0034_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0034_dct1_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0034_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0034_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0034_dct1_mp0_ADDRESS 0x34 + +// Type +#define D18F2x9C_x0000_0034_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0034_dct1_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0034_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0034_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0034_dct0_mp1_ADDRESS 0x34 + +// Type +#define D18F2x9C_x0000_0034_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0034_dct0_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0034_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0036_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0036_dct1_mp1_ADDRESS 0x36 + +// Type +#define D18F2x9C_x0000_0036_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0036_dct1_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0036_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0036_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0036_dct0_mp1_ADDRESS 0x36 + +// Type +#define D18F2x9C_x0000_0036_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0036_dct0_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0036_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0036_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0036_dct1_mp0_ADDRESS 0x36 + +// Type +#define D18F2x9C_x0000_0036_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0036_dct1_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0036_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0036_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0036_dct0_mp0_ADDRESS 0x36 + +// Type +#define D18F2x9C_x0000_0036_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0036_dct0_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0036_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0037_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0037_dct1_mp1_ADDRESS 0x37 + +// Type +#define D18F2x9C_x0000_0037_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0037_dct1_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0037_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0037_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0037_dct0_mp1_ADDRESS 0x37 + +// Type +#define D18F2x9C_x0000_0037_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0037_dct0_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0037_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0037_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0037_dct0_mp0_ADDRESS 0x37 + +// Type +#define D18F2x9C_x0000_0037_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0037_dct0_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0037_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0037_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0037_dct1_mp0_ADDRESS 0x37 + +// Type +#define D18F2x9C_x0000_0037_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0037_dct1_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0037_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0039_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0039_dct0_mp1_ADDRESS 0x39 + +// Type +#define D18F2x9C_x0000_0039_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0039_dct0_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0039_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0039_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0039_dct0_mp0_ADDRESS 0x39 + +// Type +#define D18F2x9C_x0000_0039_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0039_dct0_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0039_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0039_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0039_dct1_mp0_ADDRESS 0x39 + +// Type +#define D18F2x9C_x0000_0039_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0039_dct1_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0039_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0039_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0039_dct1_mp1_ADDRESS 0x39 + +// Type +#define D18F2x9C_x0000_0039_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0039_dct1_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0039_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_003A_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_003A_dct1_mp0_ADDRESS 0x3a + +// Type +#define D18F2x9C_x0000_003A_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_003A_dct1_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_003A_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_003A_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_003A_dct0_mp1_ADDRESS 0x3a + +// Type +#define D18F2x9C_x0000_003A_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_003A_dct0_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_003A_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_003A_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_003A_dct0_mp0_ADDRESS 0x3a + +// Type +#define D18F2x9C_x0000_003A_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_003A_dct0_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_003A_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_003A_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_003A_dct1_mp1_ADDRESS 0x3a + +// Type +#define D18F2x9C_x0000_003A_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_003A_dct1_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_003A_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0040_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0040_dct0_mp1_ADDRESS 0x40 + +// Type +#define D18F2x9C_x0000_0040_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0040_dct0_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0040_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0040_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0040_dct1_mp1_ADDRESS 0x40 + +// Type +#define D18F2x9C_x0000_0040_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0040_dct1_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0040_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0040_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0040_dct1_mp0_ADDRESS 0x40 + +// Type +#define D18F2x9C_x0000_0040_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0040_dct1_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0040_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0040_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0040_dct0_mp0_ADDRESS 0x40 + +// Type +#define D18F2x9C_x0000_0040_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0040_dct0_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0040_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0041_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0041_dct1_mp1_ADDRESS 0x41 + +// Type +#define D18F2x9C_x0000_0041_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0041_dct1_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0041_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0041_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0041_dct0_mp0_ADDRESS 0x41 + +// Type +#define D18F2x9C_x0000_0041_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0041_dct0_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0041_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0041_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0041_dct1_mp0_ADDRESS 0x41 + +// Type +#define D18F2x9C_x0000_0041_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0041_dct1_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0041_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0041_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0041_dct0_mp1_ADDRESS 0x41 + +// Type +#define D18F2x9C_x0000_0041_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0041_dct0_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0041_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0043_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0043_dct1_mp0_ADDRESS 0x43 + +// Type +#define D18F2x9C_x0000_0043_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0043_dct1_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0043_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0043_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0043_dct0_mp1_ADDRESS 0x43 + +// Type +#define D18F2x9C_x0000_0043_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0043_dct0_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0043_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0043_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0043_dct1_mp1_ADDRESS 0x43 + +// Type +#define D18F2x9C_x0000_0043_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0043_dct1_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0043_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0043_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0043_dct0_mp0_ADDRESS 0x43 + +// Type +#define D18F2x9C_x0000_0043_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0043_dct0_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0043_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0044_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0044_dct0_mp0_ADDRESS 0x44 + +// Type +#define D18F2x9C_x0000_0044_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0044_dct0_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0044_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0044_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0044_dct1_mp0_ADDRESS 0x44 + +// Type +#define D18F2x9C_x0000_0044_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0044_dct1_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0044_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0044_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0044_dct1_mp1_ADDRESS 0x44 + +// Type +#define D18F2x9C_x0000_0044_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0044_dct1_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0044_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0044_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0044_dct0_mp1_ADDRESS 0x44 + +// Type +#define D18F2x9C_x0000_0044_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0044_dct0_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0044_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0046_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0046_dct1_mp1_ADDRESS 0x46 + +// Type +#define D18F2x9C_x0000_0046_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0046_dct1_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0046_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0046_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0046_dct1_mp0_ADDRESS 0x46 + +// Type +#define D18F2x9C_x0000_0046_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0046_dct1_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0046_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0046_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0046_dct0_mp1_ADDRESS 0x46 + +// Type +#define D18F2x9C_x0000_0046_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0046_dct0_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0046_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0046_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0046_dct0_mp0_ADDRESS 0x46 + +// Type +#define D18F2x9C_x0000_0046_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0046_dct0_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0046_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0047_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0047_dct1_mp1_ADDRESS 0x47 + +// Type +#define D18F2x9C_x0000_0047_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0047_dct1_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0047_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0047_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0047_dct1_mp0_ADDRESS 0x47 + +// Type +#define D18F2x9C_x0000_0047_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0047_dct1_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0047_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0047_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0047_dct0_mp1_ADDRESS 0x47 + +// Type +#define D18F2x9C_x0000_0047_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0047_dct0_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0047_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0047_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0047_dct0_mp0_ADDRESS 0x47 + +// Type +#define D18F2x9C_x0000_0047_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0047_dct0_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0047_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0049_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0049_dct0_mp1_ADDRESS 0x49 + +// Type +#define D18F2x9C_x0000_0049_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0049_dct0_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0049_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0049_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0049_dct0_mp0_ADDRESS 0x49 + +// Type +#define D18F2x9C_x0000_0049_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0049_dct0_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0049_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0049_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0049_dct1_mp1_ADDRESS 0x49 + +// Type +#define D18F2x9C_x0000_0049_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0049_dct1_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0049_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0049_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0049_dct1_mp0_ADDRESS 0x49 + +// Type +#define D18F2x9C_x0000_0049_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_0049_dct1_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0049_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_004A_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_004A_dct0_mp0_ADDRESS 0x4a + +// Type +#define D18F2x9C_x0000_004A_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_004A_dct0_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_004A_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_004A_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_004A_dct1_mp1_ADDRESS 0x4a + +// Type +#define D18F2x9C_x0000_004A_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_004A_dct1_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_004A_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_004A_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_004A_dct1_mp0_ADDRESS 0x4a + +// Type +#define D18F2x9C_x0000_004A_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_004A_dct1_mp0 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_004A_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_004A_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_004A_dct0_mp1_ADDRESS 0x4a + +// Type +#define D18F2x9C_x0000_004A_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsFineDly_OFFSET 0 +#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsFineDly_WIDTH 5 +#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsFineDly_MASK 0x1f +#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsGrossDly_OFFSET 5 +#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsGrossDly_WIDTH 3 +#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_12_8_OFFSET 8 +#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_12_8_WIDTH 5 +#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_12_8_MASK 0x1f00 +#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_15_13_OFFSET 13 +#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_15_13_WIDTH 3 +#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_15_13_MASK 0xe000 +#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsFineDly1_OFFSET 16 +#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsFineDly1_WIDTH 5 +#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsFineDly1_MASK 0x1f0000 +#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsGrossDly1_OFFSET 21 +#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsGrossDly1_MASK 0xe00000 +#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_28_24_OFFSET 24 +#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_28_24_WIDTH 5 +#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_28_24_MASK 0x1f000000 +#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_31_29_OFFSET 29 +#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_31_29_WIDTH 3 +#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_31_29_MASK 0xe0000000 + +/// D18F2x9C_x0000_004A_dct0_mp1 +typedef union { + struct { ///< + UINT32 WrDqsFineDly:5 ; ///< + UINT32 WrDqsGrossDly:3 ; ///< + UINT32 Reserved_12_8:5 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 WrDqsFineDly1:5 ; ///< + UINT32 WrDqsGrossDly1:3 ; ///< + UINT32 Reserved_28_24:5 ; ///< + UINT32 Reserved_31_29:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_004A_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0050_dct0 Register Definition **** +// Address +#define D18F2x9C_x0000_0050_dct0_ADDRESS 0x50 + +// Type +#define D18F2x9C_x0000_0050_dct0_TYPE TYPE_D18F2x9C_dct0 +// Field Data +#define D18F2x9C_x0000_0050_dct0_PhRecFineDly_OFFSET 0 +#define D18F2x9C_x0000_0050_dct0_PhRecFineDly_WIDTH 5 +#define D18F2x9C_x0000_0050_dct0_PhRecFineDly_MASK 0x1f +#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly_WIDTH 2 +#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly_MASK 0x60 +#define D18F2x9C_x0000_0050_dct0_Reserved_7_7_OFFSET 7 +#define D18F2x9C_x0000_0050_dct0_Reserved_7_7_WIDTH 1 +#define D18F2x9C_x0000_0050_dct0_Reserved_7_7_MASK 0x80 +#define D18F2x9C_x0000_0050_dct0_PhRecFineDly8_12_OFFSET 8 +#define D18F2x9C_x0000_0050_dct0_PhRecFineDly8_12_WIDTH 5 +#define D18F2x9C_x0000_0050_dct0_PhRecFineDly8_12_MASK 0x1f00 +#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly13_14_OFFSET 13 +#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly13_14_WIDTH 2 +#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly13_14_MASK 0x6000 +#define D18F2x9C_x0000_0050_dct0_Reserved_15_15_OFFSET 15 +#define D18F2x9C_x0000_0050_dct0_Reserved_15_15_WIDTH 1 +#define D18F2x9C_x0000_0050_dct0_Reserved_15_15_MASK 0x8000 +#define D18F2x9C_x0000_0050_dct0_PhRecFineDly16_20_OFFSET 16 +#define D18F2x9C_x0000_0050_dct0_PhRecFineDly16_20_WIDTH 5 +#define D18F2x9C_x0000_0050_dct0_PhRecFineDly16_20_MASK 0x1f0000 +#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly21_22_OFFSET 21 +#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly21_22_WIDTH 2 +#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly21_22_MASK 0x600000 +#define D18F2x9C_x0000_0050_dct0_Reserved_23_23_OFFSET 23 +#define D18F2x9C_x0000_0050_dct0_Reserved_23_23_WIDTH 1 +#define D18F2x9C_x0000_0050_dct0_Reserved_23_23_MASK 0x800000 +#define D18F2x9C_x0000_0050_dct0_PhRecFineDly24_28_OFFSET 24 +#define D18F2x9C_x0000_0050_dct0_PhRecFineDly24_28_WIDTH 5 +#define D18F2x9C_x0000_0050_dct0_PhRecFineDly24_28_MASK 0x1f000000 +#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly29_30_OFFSET 29 +#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly29_30_WIDTH 2 +#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly29_30_MASK 0x60000000 +#define D18F2x9C_x0000_0050_dct0_Reserved_31_31_OFFSET 31 +#define D18F2x9C_x0000_0050_dct0_Reserved_31_31_WIDTH 1 +#define D18F2x9C_x0000_0050_dct0_Reserved_31_31_MASK 0x80000000 + +/// D18F2x9C_x0000_0050_dct0 +typedef union { + struct { ///< + UINT32 PhRecFineDly:5 ; ///< + UINT32 PhRecGrossDly:2 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 PhRecFineDly8_12:5 ; ///< + UINT32 PhRecGrossDly13_14:2 ; ///< + UINT32 Reserved_15_15:1 ; ///< + UINT32 PhRecFineDly16_20:5 ; ///< + UINT32 PhRecGrossDly21_22:2 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 PhRecFineDly24_28:5 ; ///< + UINT32 PhRecGrossDly29_30:2 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0050_dct0_STRUCT; + +// **** D18F2x9C_x0000_0050_dct1 Register Definition **** +// Address +#define D18F2x9C_x0000_0050_dct1_ADDRESS 0x50 + +// Type +#define D18F2x9C_x0000_0050_dct1_TYPE TYPE_D18F2x9C_dct1 +// Field Data +#define D18F2x9C_x0000_0050_dct1_PhRecFineDly_OFFSET 0 +#define D18F2x9C_x0000_0050_dct1_PhRecFineDly_WIDTH 5 +#define D18F2x9C_x0000_0050_dct1_PhRecFineDly_MASK 0x1f +#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly_WIDTH 2 +#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly_MASK 0x60 +#define D18F2x9C_x0000_0050_dct1_Reserved_7_7_OFFSET 7 +#define D18F2x9C_x0000_0050_dct1_Reserved_7_7_WIDTH 1 +#define D18F2x9C_x0000_0050_dct1_Reserved_7_7_MASK 0x80 +#define D18F2x9C_x0000_0050_dct1_PhRecFineDly8_12_OFFSET 8 +#define D18F2x9C_x0000_0050_dct1_PhRecFineDly8_12_WIDTH 5 +#define D18F2x9C_x0000_0050_dct1_PhRecFineDly8_12_MASK 0x1f00 +#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly13_14_OFFSET 13 +#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly13_14_WIDTH 2 +#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly13_14_MASK 0x6000 +#define D18F2x9C_x0000_0050_dct1_Reserved_15_15_OFFSET 15 +#define D18F2x9C_x0000_0050_dct1_Reserved_15_15_WIDTH 1 +#define D18F2x9C_x0000_0050_dct1_Reserved_15_15_MASK 0x8000 +#define D18F2x9C_x0000_0050_dct1_PhRecFineDly16_20_OFFSET 16 +#define D18F2x9C_x0000_0050_dct1_PhRecFineDly16_20_WIDTH 5 +#define D18F2x9C_x0000_0050_dct1_PhRecFineDly16_20_MASK 0x1f0000 +#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly21_22_OFFSET 21 +#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly21_22_WIDTH 2 +#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly21_22_MASK 0x600000 +#define D18F2x9C_x0000_0050_dct1_Reserved_23_23_OFFSET 23 +#define D18F2x9C_x0000_0050_dct1_Reserved_23_23_WIDTH 1 +#define D18F2x9C_x0000_0050_dct1_Reserved_23_23_MASK 0x800000 +#define D18F2x9C_x0000_0050_dct1_PhRecFineDly24_28_OFFSET 24 +#define D18F2x9C_x0000_0050_dct1_PhRecFineDly24_28_WIDTH 5 +#define D18F2x9C_x0000_0050_dct1_PhRecFineDly24_28_MASK 0x1f000000 +#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly29_30_OFFSET 29 +#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly29_30_WIDTH 2 +#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly29_30_MASK 0x60000000 +#define D18F2x9C_x0000_0050_dct1_Reserved_31_31_OFFSET 31 +#define D18F2x9C_x0000_0050_dct1_Reserved_31_31_WIDTH 1 +#define D18F2x9C_x0000_0050_dct1_Reserved_31_31_MASK 0x80000000 + +/// D18F2x9C_x0000_0050_dct1 +typedef union { + struct { ///< + UINT32 PhRecFineDly:5 ; ///< + UINT32 PhRecGrossDly:2 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 PhRecFineDly8_12:5 ; ///< + UINT32 PhRecGrossDly13_14:2 ; ///< + UINT32 Reserved_15_15:1 ; ///< + UINT32 PhRecFineDly16_20:5 ; ///< + UINT32 PhRecGrossDly21_22:2 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 PhRecFineDly24_28:5 ; ///< + UINT32 PhRecGrossDly29_30:2 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0050_dct1_STRUCT; + +// **** D18F2x9C_x0000_0051_dct1 Register Definition **** +// Address +#define D18F2x9C_x0000_0051_dct1_ADDRESS 0x51 + +// Type +#define D18F2x9C_x0000_0051_dct1_TYPE TYPE_D18F2x9C_dct1 +// Field Data +#define D18F2x9C_x0000_0051_dct1_PhRecFineDly_OFFSET 0 +#define D18F2x9C_x0000_0051_dct1_PhRecFineDly_WIDTH 5 +#define D18F2x9C_x0000_0051_dct1_PhRecFineDly_MASK 0x1f +#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly_WIDTH 2 +#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly_MASK 0x60 +#define D18F2x9C_x0000_0051_dct1_Reserved_7_7_OFFSET 7 +#define D18F2x9C_x0000_0051_dct1_Reserved_7_7_WIDTH 1 +#define D18F2x9C_x0000_0051_dct1_Reserved_7_7_MASK 0x80 +#define D18F2x9C_x0000_0051_dct1_PhRecFineDly8_12_OFFSET 8 +#define D18F2x9C_x0000_0051_dct1_PhRecFineDly8_12_WIDTH 5 +#define D18F2x9C_x0000_0051_dct1_PhRecFineDly8_12_MASK 0x1f00 +#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly13_14_OFFSET 13 +#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly13_14_WIDTH 2 +#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly13_14_MASK 0x6000 +#define D18F2x9C_x0000_0051_dct1_Reserved_15_15_OFFSET 15 +#define D18F2x9C_x0000_0051_dct1_Reserved_15_15_WIDTH 1 +#define D18F2x9C_x0000_0051_dct1_Reserved_15_15_MASK 0x8000 +#define D18F2x9C_x0000_0051_dct1_PhRecFineDly16_20_OFFSET 16 +#define D18F2x9C_x0000_0051_dct1_PhRecFineDly16_20_WIDTH 5 +#define D18F2x9C_x0000_0051_dct1_PhRecFineDly16_20_MASK 0x1f0000 +#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly21_22_OFFSET 21 +#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly21_22_WIDTH 2 +#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly21_22_MASK 0x600000 +#define D18F2x9C_x0000_0051_dct1_Reserved_23_23_OFFSET 23 +#define D18F2x9C_x0000_0051_dct1_Reserved_23_23_WIDTH 1 +#define D18F2x9C_x0000_0051_dct1_Reserved_23_23_MASK 0x800000 +#define D18F2x9C_x0000_0051_dct1_PhRecFineDly24_28_OFFSET 24 +#define D18F2x9C_x0000_0051_dct1_PhRecFineDly24_28_WIDTH 5 +#define D18F2x9C_x0000_0051_dct1_PhRecFineDly24_28_MASK 0x1f000000 +#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly29_30_OFFSET 29 +#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly29_30_WIDTH 2 +#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly29_30_MASK 0x60000000 +#define D18F2x9C_x0000_0051_dct1_Reserved_31_31_OFFSET 31 +#define D18F2x9C_x0000_0051_dct1_Reserved_31_31_WIDTH 1 +#define D18F2x9C_x0000_0051_dct1_Reserved_31_31_MASK 0x80000000 + +/// D18F2x9C_x0000_0051_dct1 +typedef union { + struct { ///< + UINT32 PhRecFineDly:5 ; ///< + UINT32 PhRecGrossDly:2 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 PhRecFineDly8_12:5 ; ///< + UINT32 PhRecGrossDly13_14:2 ; ///< + UINT32 Reserved_15_15:1 ; ///< + UINT32 PhRecFineDly16_20:5 ; ///< + UINT32 PhRecGrossDly21_22:2 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 PhRecFineDly24_28:5 ; ///< + UINT32 PhRecGrossDly29_30:2 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0051_dct1_STRUCT; + +// **** D18F2x9C_x0000_0051_dct0 Register Definition **** +// Address +#define D18F2x9C_x0000_0051_dct0_ADDRESS 0x51 + +// Type +#define D18F2x9C_x0000_0051_dct0_TYPE TYPE_D18F2x9C_dct0 +// Field Data +#define D18F2x9C_x0000_0051_dct0_PhRecFineDly_OFFSET 0 +#define D18F2x9C_x0000_0051_dct0_PhRecFineDly_WIDTH 5 +#define D18F2x9C_x0000_0051_dct0_PhRecFineDly_MASK 0x1f +#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly_WIDTH 2 +#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly_MASK 0x60 +#define D18F2x9C_x0000_0051_dct0_Reserved_7_7_OFFSET 7 +#define D18F2x9C_x0000_0051_dct0_Reserved_7_7_WIDTH 1 +#define D18F2x9C_x0000_0051_dct0_Reserved_7_7_MASK 0x80 +#define D18F2x9C_x0000_0051_dct0_PhRecFineDly8_12_OFFSET 8 +#define D18F2x9C_x0000_0051_dct0_PhRecFineDly8_12_WIDTH 5 +#define D18F2x9C_x0000_0051_dct0_PhRecFineDly8_12_MASK 0x1f00 +#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly13_14_OFFSET 13 +#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly13_14_WIDTH 2 +#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly13_14_MASK 0x6000 +#define D18F2x9C_x0000_0051_dct0_Reserved_15_15_OFFSET 15 +#define D18F2x9C_x0000_0051_dct0_Reserved_15_15_WIDTH 1 +#define D18F2x9C_x0000_0051_dct0_Reserved_15_15_MASK 0x8000 +#define D18F2x9C_x0000_0051_dct0_PhRecFineDly16_20_OFFSET 16 +#define D18F2x9C_x0000_0051_dct0_PhRecFineDly16_20_WIDTH 5 +#define D18F2x9C_x0000_0051_dct0_PhRecFineDly16_20_MASK 0x1f0000 +#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly21_22_OFFSET 21 +#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly21_22_WIDTH 2 +#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly21_22_MASK 0x600000 +#define D18F2x9C_x0000_0051_dct0_Reserved_23_23_OFFSET 23 +#define D18F2x9C_x0000_0051_dct0_Reserved_23_23_WIDTH 1 +#define D18F2x9C_x0000_0051_dct0_Reserved_23_23_MASK 0x800000 +#define D18F2x9C_x0000_0051_dct0_PhRecFineDly24_28_OFFSET 24 +#define D18F2x9C_x0000_0051_dct0_PhRecFineDly24_28_WIDTH 5 +#define D18F2x9C_x0000_0051_dct0_PhRecFineDly24_28_MASK 0x1f000000 +#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly29_30_OFFSET 29 +#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly29_30_WIDTH 2 +#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly29_30_MASK 0x60000000 +#define D18F2x9C_x0000_0051_dct0_Reserved_31_31_OFFSET 31 +#define D18F2x9C_x0000_0051_dct0_Reserved_31_31_WIDTH 1 +#define D18F2x9C_x0000_0051_dct0_Reserved_31_31_MASK 0x80000000 + +/// D18F2x9C_x0000_0051_dct0 +typedef union { + struct { ///< + UINT32 PhRecFineDly:5 ; ///< + UINT32 PhRecGrossDly:2 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 PhRecFineDly8_12:5 ; ///< + UINT32 PhRecGrossDly13_14:2 ; ///< + UINT32 Reserved_15_15:1 ; ///< + UINT32 PhRecFineDly16_20:5 ; ///< + UINT32 PhRecGrossDly21_22:2 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 PhRecFineDly24_28:5 ; ///< + UINT32 PhRecGrossDly29_30:2 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0051_dct0_STRUCT; + +// **** D18F2x9C_x0000_0101_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0101_dct0_mp1_ADDRESS 0x101 + +// Type +#define D18F2x9C_x0000_0101_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0101_dct0_mp1 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0101_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0101_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0101_dct1_mp1_ADDRESS 0x101 + +// Type +#define D18F2x9C_x0000_0101_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0101_dct1_mp1 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0101_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0101_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0101_dct1_mp0_ADDRESS 0x101 + +// Type +#define D18F2x9C_x0000_0101_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0101_dct1_mp0 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0101_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0101_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0101_dct0_mp0_ADDRESS 0x101 + +// Type +#define D18F2x9C_x0000_0101_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0101_dct0_mp0 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0101_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0102_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0102_dct1_mp1_ADDRESS 0x102 + +// Type +#define D18F2x9C_x0000_0102_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0102_dct1_mp1 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0102_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0102_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0102_dct1_mp0_ADDRESS 0x102 + +// Type +#define D18F2x9C_x0000_0102_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0102_dct1_mp0 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0102_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0102_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0102_dct0_mp0_ADDRESS 0x102 + +// Type +#define D18F2x9C_x0000_0102_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0102_dct0_mp0 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0102_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0102_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0102_dct0_mp1_ADDRESS 0x102 + +// Type +#define D18F2x9C_x0000_0102_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0102_dct0_mp1 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0102_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0105_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0105_dct1_mp1_ADDRESS 0x105 + +// Type +#define D18F2x9C_x0000_0105_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0105_dct1_mp1 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0105_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0105_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0105_dct0_mp1_ADDRESS 0x105 + +// Type +#define D18F2x9C_x0000_0105_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0105_dct0_mp1 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0105_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0105_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0105_dct0_mp0_ADDRESS 0x105 + +// Type +#define D18F2x9C_x0000_0105_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0105_dct0_mp0 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0105_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0105_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0105_dct1_mp0_ADDRESS 0x105 + +// Type +#define D18F2x9C_x0000_0105_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0105_dct1_mp0 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0105_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0106_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0106_dct0_mp1_ADDRESS 0x106 + +// Type +#define D18F2x9C_x0000_0106_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0106_dct0_mp1 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0106_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0106_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0106_dct1_mp0_ADDRESS 0x106 + +// Type +#define D18F2x9C_x0000_0106_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0106_dct1_mp0 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0106_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0106_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0106_dct0_mp0_ADDRESS 0x106 + +// Type +#define D18F2x9C_x0000_0106_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0106_dct0_mp0 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0106_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0106_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0106_dct1_mp1_ADDRESS 0x106 + +// Type +#define D18F2x9C_x0000_0106_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0106_dct1_mp1 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0106_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0201_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0201_dct0_mp1_ADDRESS 0x201 + +// Type +#define D18F2x9C_x0000_0201_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0201_dct0_mp1 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0201_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0201_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0201_dct1_mp0_ADDRESS 0x201 + +// Type +#define D18F2x9C_x0000_0201_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0201_dct1_mp0 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0201_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0201_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0201_dct1_mp1_ADDRESS 0x201 + +// Type +#define D18F2x9C_x0000_0201_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0201_dct1_mp1 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0201_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0201_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0201_dct0_mp0_ADDRESS 0x201 + +// Type +#define D18F2x9C_x0000_0201_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0201_dct0_mp0 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0201_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0202_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0202_dct1_mp1_ADDRESS 0x202 + +// Type +#define D18F2x9C_x0000_0202_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0202_dct1_mp1 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0202_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0202_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0202_dct1_mp0_ADDRESS 0x202 + +// Type +#define D18F2x9C_x0000_0202_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0202_dct1_mp0 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0202_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0202_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0202_dct0_mp1_ADDRESS 0x202 + +// Type +#define D18F2x9C_x0000_0202_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0202_dct0_mp1 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0202_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0202_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0202_dct0_mp0_ADDRESS 0x202 + +// Type +#define D18F2x9C_x0000_0202_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0202_dct0_mp0 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0202_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0205_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0205_dct1_mp1_ADDRESS 0x205 + +// Type +#define D18F2x9C_x0000_0205_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0205_dct1_mp1 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0205_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0205_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0205_dct1_mp0_ADDRESS 0x205 + +// Type +#define D18F2x9C_x0000_0205_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0205_dct1_mp0 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0205_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0205_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0205_dct0_mp1_ADDRESS 0x205 + +// Type +#define D18F2x9C_x0000_0205_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0205_dct0_mp1 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0205_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0205_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0205_dct0_mp0_ADDRESS 0x205 + +// Type +#define D18F2x9C_x0000_0205_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0205_dct0_mp0 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0205_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0206_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0206_dct0_mp0_ADDRESS 0x206 + +// Type +#define D18F2x9C_x0000_0206_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0206_dct0_mp0 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0206_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0206_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0206_dct1_mp0_ADDRESS 0x206 + +// Type +#define D18F2x9C_x0000_0206_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0206_dct1_mp0 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0206_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0206_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0206_dct0_mp1_ADDRESS 0x206 + +// Type +#define D18F2x9C_x0000_0206_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0206_dct0_mp1 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0206_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0206_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0206_dct1_mp1_ADDRESS 0x206 + +// Type +#define D18F2x9C_x0000_0206_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0206_dct1_mp1 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0206_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0301_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0301_dct1_mp0_ADDRESS 0x301 + +// Type +#define D18F2x9C_x0000_0301_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0301_dct1_mp0 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0301_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0301_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0301_dct1_mp1_ADDRESS 0x301 + +// Type +#define D18F2x9C_x0000_0301_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0301_dct1_mp1 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0301_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0301_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0301_dct0_mp0_ADDRESS 0x301 + +// Type +#define D18F2x9C_x0000_0301_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0301_dct0_mp0 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0301_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0301_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0301_dct0_mp1_ADDRESS 0x301 + +// Type +#define D18F2x9C_x0000_0301_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0301_dct0_mp1 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0301_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0302_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0302_dct1_mp1_ADDRESS 0x302 + +// Type +#define D18F2x9C_x0000_0302_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0302_dct1_mp1 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0302_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0302_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0302_dct0_mp1_ADDRESS 0x302 + +// Type +#define D18F2x9C_x0000_0302_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0302_dct0_mp1 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0302_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0302_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0302_dct1_mp0_ADDRESS 0x302 + +// Type +#define D18F2x9C_x0000_0302_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0302_dct1_mp0 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0302_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0302_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0302_dct0_mp0_ADDRESS 0x302 + +// Type +#define D18F2x9C_x0000_0302_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly_OFFSET 0 +#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly_WIDTH 5 +#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly_MASK 0x1f +#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly_OFFSET 5 +#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly_WIDTH 3 +#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly_MASK 0xe0 +#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly1_OFFSET 8 +#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly1_WIDTH 5 +#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly1_MASK 0x1f00 +#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly1_OFFSET 13 +#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly1_WIDTH 3 +#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly1_MASK 0xe000 +#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly2_OFFSET 16 +#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly2_WIDTH 5 +#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly2_MASK 0x1f0000 +#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly2_OFFSET 21 +#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly2_WIDTH 3 +#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly2_MASK 0xe00000 +#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly3_OFFSET 24 +#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly3_WIDTH 5 +#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly3_MASK 0x1f000000 +#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly3_OFFSET 29 +#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly3_WIDTH 3 +#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly3_MASK 0xe0000000 + +/// D18F2x9C_x0000_0302_dct0_mp0 +typedef union { + struct { ///< + UINT32 WrDatFineDly:5 ; ///< + UINT32 WrDatGrossDly:3 ; ///< + UINT32 WrDatFineDly1:5 ; ///< + UINT32 WrDatGrossDly1:3 ; ///< + UINT32 WrDatFineDly2:5 ; ///< + UINT32 WrDatGrossDly2:3 ; ///< + UINT32 WrDatFineDly3:5 ; ///< + UINT32 WrDatGrossDly3:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0302_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0305_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0305_dct0_mp0_ADDRESS 0x305 + +// Type +#define D18F2x9C_x0000_0305_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0305_dct0_mp0 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0305_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0305_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0305_dct1_mp1_ADDRESS 0x305 + +// Type +#define D18F2x9C_x0000_0305_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0305_dct1_mp1 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0305_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0000_0305_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0305_dct0_mp1_ADDRESS 0x305 + +// Type +#define D18F2x9C_x0000_0305_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0305_dct0_mp1 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0305_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0305_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0305_dct1_mp0_ADDRESS 0x305 + +// Type +#define D18F2x9C_x0000_0305_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0305_dct1_mp0 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0305_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0306_dct0_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0306_dct0_mp0_ADDRESS 0x306 + +// Type +#define D18F2x9C_x0000_0306_dct0_mp0_TYPE TYPE_D18F2x9C_dct0_mp0 +// Field Data +#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0306_dct0_mp0 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0306_dct0_mp0_STRUCT; + +// **** D18F2x9C_x0000_0306_dct0_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0306_dct0_mp1_ADDRESS 0x306 + +// Type +#define D18F2x9C_x0000_0306_dct0_mp1_TYPE TYPE_D18F2x9C_dct0_mp1 +// Field Data +#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0306_dct0_mp1 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0306_dct0_mp1_STRUCT; + +// **** D18F2x9C_x0000_0306_dct1_mp0 Register Definition **** +// Address +#define D18F2x9C_x0000_0306_dct1_mp0_ADDRESS 0x306 + +// Type +#define D18F2x9C_x0000_0306_dct1_mp0_TYPE TYPE_D18F2x9C_dct1_mp0 +// Field Data +#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0306_dct1_mp0 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0306_dct1_mp0_STRUCT; + +// **** D18F2x9C_x0000_0306_dct1_mp1 Register Definition **** +// Address +#define D18F2x9C_x0000_0306_dct1_mp1_ADDRESS 0x306 + +// Type +#define D18F2x9C_x0000_0306_dct1_mp1_TYPE TYPE_D18F2x9C_dct1_mp1 +// Field Data +#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_0_0_OFFSET 0 +#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_0_0_WIDTH 1 +#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_0_0_MASK 0x1 +#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime_OFFSET 1 +#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime_WIDTH 5 +#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime_MASK 0x3e +#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_8_6_OFFSET 6 +#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_8_6_WIDTH 3 +#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_8_6_MASK 0x1c0 +#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime1_OFFSET 9 +#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime1_WIDTH 5 +#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime1_MASK 0x3e00 +#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_16_14_OFFSET 14 +#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_16_14_WIDTH 3 +#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_16_14_MASK 0x1c000 +#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime2_OFFSET 17 +#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime2_WIDTH 5 +#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime2_MASK 0x3e0000 +#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_24_22_OFFSET 22 +#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_24_22_WIDTH 3 +#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_24_22_MASK 0x1c00000 +#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime3_OFFSET 25 +#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime3_WIDTH 5 +#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime3_MASK 0x3e000000 +#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_31_30_OFFSET 30 +#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_31_30_WIDTH 2 +#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x9C_x0000_0306_dct1_mp1 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 RdDqsTime:5 ; ///< + UINT32 Reserved_8_6:3 ; ///< + UINT32 RdDqsTime1:5 ; ///< + UINT32 Reserved_16_14:3 ; ///< + UINT32 RdDqsTime2:5 ; ///< + UINT32 Reserved_24_22:3 ; ///< + UINT32 RdDqsTime3:5 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0000_0306_dct1_mp1_STRUCT; + +// **** D18F2x9C_x0D0F_E00A_dct0 Register Definition **** +// Address +#define D18F2x9C_x0D0F_E00A_dct0_ADDRESS 0x0d0fe00a + +// Type +#define D18F2x9C_x0D0F_E00A_dct0_TYPE TYPE_D18F2x9C_dct0 +// Field Data +#define D18F2x9C_x0D0F_E00A_dct0_Reserved_3_0_OFFSET 0 +#define D18F2x9C_x0D0F_E00A_dct0_Reserved_3_0_WIDTH 4 +#define D18F2x9C_x0D0F_E00A_dct0_Reserved_3_0_MASK 0xf +#define D18F2x9C_x0D0F_E00A_dct0_SkewMemClk_OFFSET 4 +#define D18F2x9C_x0D0F_E00A_dct0_SkewMemClk_WIDTH 1 +#define D18F2x9C_x0D0F_E00A_dct0_SkewMemClk_MASK 0x10 +#define D18F2x9C_x0D0F_E00A_dct0_Reserved_11_5_OFFSET 5 +#define D18F2x9C_x0D0F_E00A_dct0_Reserved_11_5_WIDTH 7 +#define D18F2x9C_x0D0F_E00A_dct0_Reserved_11_5_MASK 0xfe0 +#define D18F2x9C_x0D0F_E00A_dct0_Reserved_31_15_OFFSET 15 +#define D18F2x9C_x0D0F_E00A_dct0_Reserved_31_15_WIDTH 17 +#define D18F2x9C_x0D0F_E00A_dct0_Reserved_31_15_MASK 0xffff8000 + +/// D18F2x9C_x0D0F_E00A_dct0 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 SkewMemClk:1 ; ///< + UINT32 Reserved_11_5:7 ; ///< + UINT32 :2 ; ///< + UINT32 :1 ; ///< + UINT32 Reserved_31_15:17 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0D0F_E00A_dct0_STRUCT; + +// **** D18F2x9C_x0D0F_E00A_dct1 Register Definition **** +// Address +#define D18F2x9C_x0D0F_E00A_dct1_ADDRESS 0x0d0fe00a + +// Type +#define D18F2x9C_x0D0F_E00A_dct1_TYPE TYPE_D18F2x9C_dct1 +// Field Data +#define D18F2x9C_x0D0F_E00A_dct1_Reserved_3_0_OFFSET 0 +#define D18F2x9C_x0D0F_E00A_dct1_Reserved_3_0_WIDTH 4 +#define D18F2x9C_x0D0F_E00A_dct1_Reserved_3_0_MASK 0xf +#define D18F2x9C_x0D0F_E00A_dct1_SkewMemClk_OFFSET 4 +#define D18F2x9C_x0D0F_E00A_dct1_SkewMemClk_WIDTH 1 +#define D18F2x9C_x0D0F_E00A_dct1_SkewMemClk_MASK 0x10 +#define D18F2x9C_x0D0F_E00A_dct1_Reserved_11_5_OFFSET 5 +#define D18F2x9C_x0D0F_E00A_dct1_Reserved_11_5_WIDTH 7 +#define D18F2x9C_x0D0F_E00A_dct1_Reserved_11_5_MASK 0xfe0 +#define D18F2x9C_x0D0F_E00A_dct1_Reserved_31_15_OFFSET 15 +#define D18F2x9C_x0D0F_E00A_dct1_Reserved_31_15_WIDTH 17 +#define D18F2x9C_x0D0F_E00A_dct1_Reserved_31_15_MASK 0xffff8000 + +/// D18F2x9C_x0D0F_E00A_dct1 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 SkewMemClk:1 ; ///< + UINT32 Reserved_11_5:7 ; ///< + UINT32 :2 ; ///< + UINT32 :1 ; ///< + UINT32 Reserved_31_15:17 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_x0D0F_E00A_dct1_STRUCT; + + +// **** DxF0xE4_x01 Register Definition **** +// Address +#define DxF0xE4_x01_ADDRESS 0x1 + +// Type +#define DxF0xE4_x01_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_x01_Scratch_OFFSET 0 +#define DxF0xE4_x01_Scratch_WIDTH 32 +#define DxF0xE4_x01_Scratch_MASK 0xffffffff + +/// DxF0xE4_x01 +typedef union { + struct { ///< + UINT32 Scratch:32; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_x01_STRUCT; + +// **** DxF0xE4_x02 Register Definition **** +// Address +#define DxF0xE4_x02_ADDRESS 0x2 + +// Type +#define DxF0xE4_x02_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_x02_Reserved_14_0_OFFSET 0 +#define DxF0xE4_x02_Reserved_14_0_WIDTH 15 +#define DxF0xE4_x02_Reserved_14_0_MASK 0x7fff +#define DxF0xE4_x02_RegsLcAllowTxL1Control_OFFSET 15 +#define DxF0xE4_x02_RegsLcAllowTxL1Control_WIDTH 1 +#define DxF0xE4_x02_RegsLcAllowTxL1Control_MASK 0x8000 +#define DxF0xE4_x02_Reserved_31_16_OFFSET 16 +#define DxF0xE4_x02_Reserved_31_16_WIDTH 16 +#define DxF0xE4_x02_Reserved_31_16_MASK 0xffff0000 + +/// DxF0xE4_x02 +typedef union { + struct { ///< + UINT32 Reserved_14_0:15; ///< + UINT32 RegsLcAllowTxL1Control:1 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_x02_STRUCT; + +// **** DxF0xE4_x50 Register Definition **** +// Address +#define DxF0xE4_x50_ADDRESS 0x50 + +// Type +#define DxF0xE4_x50_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_x50_PortLaneReversal_OFFSET 0 +#define DxF0xE4_x50_PortLaneReversal_WIDTH 1 +#define DxF0xE4_x50_PortLaneReversal_MASK 0x1 +#define DxF0xE4_x50_PhyLinkWidth_OFFSET 1 +#define DxF0xE4_x50_PhyLinkWidth_WIDTH 6 +#define DxF0xE4_x50_PhyLinkWidth_MASK 0x7e +#define DxF0xE4_x50_Reserved_31_7_OFFSET 7 +#define DxF0xE4_x50_Reserved_31_7_WIDTH 25 +#define DxF0xE4_x50_Reserved_31_7_MASK 0xffffff80 + +/// DxF0xE4_x50 +typedef union { + struct { ///< + UINT32 PortLaneReversal:1 ; ///< + UINT32 PhyLinkWidth:6 ; ///< + UINT32 Reserved_31_7:25; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_x50_STRUCT; + +// **** DxF0xE4_x70 Register Definition **** +// Address +#define DxF0xE4_x70_ADDRESS 0x70 + +// Type +#define DxF0xE4_x70_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_x70_Reserved_15_0_OFFSET 0 +#define DxF0xE4_x70_Reserved_15_0_WIDTH 16 +#define DxF0xE4_x70_Reserved_15_0_MASK 0xffff +#define DxF0xE4_x70_RxRcbCplTimeout_OFFSET 16 +#define DxF0xE4_x70_RxRcbCplTimeout_WIDTH 3 +#define DxF0xE4_x70_RxRcbCplTimeout_MASK 0x70000 +#define DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET 19 +#define DxF0xE4_x70_RxRcbCplTimeoutMode_WIDTH 1 +#define DxF0xE4_x70_RxRcbCplTimeoutMode_MASK 0x80000 +#define DxF0xE4_x70_Reserved_31_20_OFFSET 20 +#define DxF0xE4_x70_Reserved_31_20_WIDTH 12 +#define DxF0xE4_x70_Reserved_31_20_MASK 0xfff00000 + +/// DxF0xE4_x70 +typedef union { + struct { ///< + UINT32 Reserved_15_0:16; ///< + UINT32 RxRcbCplTimeout:3 ; ///< + UINT32 RxRcbCplTimeoutMode:1 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_x70_STRUCT; + +// **** DxF0xE4_xA0 Register Definition **** +// Address +#define DxF0xE4_xA0_ADDRESS 0xa0 + +// Type +#define DxF0xE4_xA0_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_xA0_Reserved_3_0_OFFSET 0 +#define DxF0xE4_xA0_Reserved_3_0_WIDTH 4 +#define DxF0xE4_xA0_Reserved_3_0_MASK 0xf +#define DxF0xE4_xA0_Lc16xClearTxPipe_OFFSET 4 +#define DxF0xE4_xA0_Lc16xClearTxPipe_WIDTH 4 +#define DxF0xE4_xA0_Lc16xClearTxPipe_MASK 0xf0 +#define DxF0xE4_xA0_LcL0sInactivity_OFFSET 8 +#define DxF0xE4_xA0_LcL0sInactivity_WIDTH 4 +#define DxF0xE4_xA0_LcL0sInactivity_MASK 0xf00 +#define DxF0xE4_xA0_LcL1Inactivity_OFFSET 12 +#define DxF0xE4_xA0_LcL1Inactivity_WIDTH 4 +#define DxF0xE4_xA0_LcL1Inactivity_MASK 0xf000 +#define DxF0xE4_xA0_Reserved_22_16_OFFSET 16 +#define DxF0xE4_xA0_Reserved_22_16_WIDTH 7 +#define DxF0xE4_xA0_Reserved_22_16_MASK 0x7f0000 +#define DxF0xE4_xA0_LcL1ImmediateAck_OFFSET 23 +#define DxF0xE4_xA0_LcL1ImmediateAck_WIDTH 1 +#define DxF0xE4_xA0_LcL1ImmediateAck_MASK 0x800000 +#define DxF0xE4_xA0_Reserved_31_24_OFFSET 24 +#define DxF0xE4_xA0_Reserved_31_24_WIDTH 8 +#define DxF0xE4_xA0_Reserved_31_24_MASK 0xff000000 + +/// DxF0xE4_xA0 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 Lc16xClearTxPipe:4 ; ///< + UINT32 LcL0sInactivity:4 ; ///< + UINT32 LcL1Inactivity:4 ; ///< + UINT32 Reserved_22_16:7 ; ///< + UINT32 LcL1ImmediateAck:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_xA0_STRUCT; + +// **** DxF0xE4_xA1 Register Definition **** +// Address +#define DxF0xE4_xA1_ADDRESS 0xa1 + +// Type +#define DxF0xE4_xA1_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_xA1_Reserved_10_0_OFFSET 0 +#define DxF0xE4_xA1_Reserved_10_0_WIDTH 11 +#define DxF0xE4_xA1_Reserved_10_0_MASK 0x7ff +#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_OFFSET 11 +#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_WIDTH 1 +#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_MASK 0x800 +#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_OFFSET 12 +#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_WIDTH 1 +#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_MASK 0x1000 +#define DxF0xE4_xA1_Reserved_31_13_OFFSET 13 +#define DxF0xE4_xA1_Reserved_31_13_WIDTH 19 +#define DxF0xE4_xA1_Reserved_31_13_MASK 0xffffe000 + +/// DxF0xE4_xA1 +typedef union { + struct { ///< + UINT32 Reserved_10_0:11; ///< + UINT32 LcDontGotoL0sifL1Armed:1 ; ///< + UINT32 LcInitSpdChgWithCsrEn:1 ; ///< + UINT32 Reserved_31_13:19; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_xA1_STRUCT; + +// **** DxF0xE4_xA2 Register Definition **** +// Address +#define DxF0xE4_xA2_ADDRESS 0xa2 + +// Type +#define DxF0xE4_xA2_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_xA2_LcLinkWidth_OFFSET 0 +#define DxF0xE4_xA2_LcLinkWidth_WIDTH 3 +#define DxF0xE4_xA2_LcLinkWidth_MASK 0x7 +#define DxF0xE4_xA2_Reserved_3_3_OFFSET 3 +#define DxF0xE4_xA2_Reserved_3_3_WIDTH 1 +#define DxF0xE4_xA2_Reserved_3_3_MASK 0x8 +#define DxF0xE4_xA2_LcLinkWidthRd_OFFSET 4 +#define DxF0xE4_xA2_LcLinkWidthRd_WIDTH 3 +#define DxF0xE4_xA2_LcLinkWidthRd_MASK 0x70 +#define DxF0xE4_xA2_LcReconfigArcMissingEscape_OFFSET 7 +#define DxF0xE4_xA2_LcReconfigArcMissingEscape_WIDTH 1 +#define DxF0xE4_xA2_LcReconfigArcMissingEscape_MASK 0x80 +#define DxF0xE4_xA2_LcReconfigNow_OFFSET 8 +#define DxF0xE4_xA2_LcReconfigNow_WIDTH 1 +#define DxF0xE4_xA2_LcReconfigNow_MASK 0x100 +#define DxF0xE4_xA2_LcRenegotiationSupport_OFFSET 9 +#define DxF0xE4_xA2_LcRenegotiationSupport_WIDTH 1 +#define DxF0xE4_xA2_LcRenegotiationSupport_MASK 0x200 +#define DxF0xE4_xA2_LcRenegotiateEn_OFFSET 10 +#define DxF0xE4_xA2_LcRenegotiateEn_WIDTH 1 +#define DxF0xE4_xA2_LcRenegotiateEn_MASK 0x400 +#define DxF0xE4_xA2_LcShortReconfigEn_OFFSET 11 +#define DxF0xE4_xA2_LcShortReconfigEn_WIDTH 1 +#define DxF0xE4_xA2_LcShortReconfigEn_MASK 0x800 +#define DxF0xE4_xA2_LcUpconfigureSupport_OFFSET 12 +#define DxF0xE4_xA2_LcUpconfigureSupport_WIDTH 1 +#define DxF0xE4_xA2_LcUpconfigureSupport_MASK 0x1000 +#define DxF0xE4_xA2_LcUpconfigureDis_OFFSET 13 +#define DxF0xE4_xA2_LcUpconfigureDis_WIDTH 1 +#define DxF0xE4_xA2_LcUpconfigureDis_MASK 0x2000 +#define DxF0xE4_xA2_Reserved_19_14_OFFSET 14 +#define DxF0xE4_xA2_Reserved_19_14_WIDTH 6 +#define DxF0xE4_xA2_Reserved_19_14_MASK 0xfc000 +#define DxF0xE4_xA2_LcUpconfigCapable_OFFSET 20 +#define DxF0xE4_xA2_LcUpconfigCapable_WIDTH 1 +#define DxF0xE4_xA2_LcUpconfigCapable_MASK 0x100000 +#define DxF0xE4_xA2_LcDynLanesPwrState_OFFSET 21 +#define DxF0xE4_xA2_LcDynLanesPwrState_WIDTH 2 +#define DxF0xE4_xA2_LcDynLanesPwrState_MASK 0x600000 +#define DxF0xE4_xA2_Reserved_31_23_OFFSET 23 +#define DxF0xE4_xA2_Reserved_31_23_WIDTH 9 +#define DxF0xE4_xA2_Reserved_31_23_MASK 0xff800000 + +/// DxF0xE4_xA2 +typedef union { + struct { ///< + UINT32 LcLinkWidth:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 LcLinkWidthRd:3 ; ///< + UINT32 LcReconfigArcMissingEscape:1 ; ///< + UINT32 LcReconfigNow:1 ; ///< + UINT32 LcRenegotiationSupport:1 ; ///< + UINT32 LcRenegotiateEn:1 ; ///< + UINT32 LcShortReconfigEn:1 ; ///< + UINT32 LcUpconfigureSupport:1 ; ///< + UINT32 LcUpconfigureDis:1 ; ///< + UINT32 Reserved_19_14:6 ; ///< + UINT32 LcUpconfigCapable:1 ; ///< + UINT32 LcDynLanesPwrState:2 ; ///< + UINT32 Reserved_31_23:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_xA2_STRUCT; + +// **** DxF0xE4_xA3 Register Definition **** +// Address +#define DxF0xE4_xA3_ADDRESS 0xa3 + +// Type +#define DxF0xE4_xA3_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_xA3_Reserved_8_0_OFFSET 0 +#define DxF0xE4_xA3_Reserved_8_0_WIDTH 9 +#define DxF0xE4_xA3_Reserved_8_0_MASK 0x1ff +#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_OFFSET 9 +#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_WIDTH 1 +#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_MASK 0x200 +#define DxF0xE4_xA3_Reserved_31_10_OFFSET 10 +#define DxF0xE4_xA3_Reserved_31_10_WIDTH 22 +#define DxF0xE4_xA3_Reserved_31_10_MASK 0xfffffc00 + +/// DxF0xE4_xA3 +typedef union { + struct { ///< + UINT32 Reserved_8_0:9 ; ///< + UINT32 LcXmitFtsBeforeRecovery:1 ; ///< + UINT32 Reserved_31_10:22; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_xA3_STRUCT; + +// **** DxF0xE4_xA4 Register Definition **** +// Address +#define DxF0xE4_xA4_ADDRESS 0xa4 + +// Type +#define DxF0xE4_xA4_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_xA4_LcGen2EnStrap_OFFSET 0 +#define DxF0xE4_xA4_LcGen2EnStrap_WIDTH 1 +#define DxF0xE4_xA4_LcGen2EnStrap_MASK 0x1 +#define DxF0xE4_xA4_Reserved_5_1_OFFSET 1 +#define DxF0xE4_xA4_Reserved_5_1_WIDTH 5 +#define DxF0xE4_xA4_Reserved_5_1_MASK 0x3e +#define DxF0xE4_xA4_LcForceDisSwSpeedChange_OFFSET 6 +#define DxF0xE4_xA4_LcForceDisSwSpeedChange_WIDTH 1 +#define DxF0xE4_xA4_LcForceDisSwSpeedChange_MASK 0x40 +#define DxF0xE4_xA4_Reserved_8_7_OFFSET 7 +#define DxF0xE4_xA4_Reserved_8_7_WIDTH 2 +#define DxF0xE4_xA4_Reserved_8_7_MASK 0x180 +#define DxF0xE4_xA4_LcInitiateLinkSpeedChange_OFFSET 9 +#define DxF0xE4_xA4_LcInitiateLinkSpeedChange_WIDTH 1 +#define DxF0xE4_xA4_LcInitiateLinkSpeedChange_MASK 0x200 +#define DxF0xE4_xA4_Reserved_11_10_OFFSET 10 +#define DxF0xE4_xA4_Reserved_11_10_WIDTH 2 +#define DxF0xE4_xA4_Reserved_11_10_MASK 0xc00 +#define DxF0xE4_xA4_LcSpeedChangeAttemptFailed_OFFSET 12 +#define DxF0xE4_xA4_LcSpeedChangeAttemptFailed_WIDTH 1 +#define DxF0xE4_xA4_LcSpeedChangeAttemptFailed_MASK 0x1000 +#define DxF0xE4_xA4_Reserved_18_13_OFFSET 13 +#define DxF0xE4_xA4_Reserved_18_13_WIDTH 6 +#define DxF0xE4_xA4_Reserved_18_13_MASK 0x7e000 +#define DxF0xE4_xA4_LcOtherSideSupportsGen2_OFFSET 19 +#define DxF0xE4_xA4_LcOtherSideSupportsGen2_WIDTH 1 +#define DxF0xE4_xA4_LcOtherSideSupportsGen2_MASK 0x80000 +#define DxF0xE4_xA4_Reserved_26_20_OFFSET 20 +#define DxF0xE4_xA4_Reserved_26_20_WIDTH 7 +#define DxF0xE4_xA4_Reserved_26_20_MASK 0x7f00000 +#define DxF0xE4_xA4_LcMultUpstreamAutoSpdChngEn_OFFSET 27 +#define DxF0xE4_xA4_LcMultUpstreamAutoSpdChngEn_WIDTH 1 +#define DxF0xE4_xA4_LcMultUpstreamAutoSpdChngEn_MASK 0x8000000 +#define DxF0xE4_xA4_Reserved_31_28_OFFSET 28 +#define DxF0xE4_xA4_Reserved_31_28_WIDTH 4 +#define DxF0xE4_xA4_Reserved_31_28_MASK 0xf0000000 + +/// DxF0xE4_xA4 +typedef union { + struct { ///< + UINT32 LcGen2EnStrap:1 ; ///< + UINT32 Reserved_5_1:5 ; ///< + UINT32 LcForceDisSwSpeedChange:1 ; ///< + UINT32 Reserved_8_7:2 ; ///< + UINT32 LcInitiateLinkSpeedChange:1 ; ///< + UINT32 Reserved_11_10:2 ; ///< + UINT32 LcSpeedChangeAttemptFailed:1 ; ///< + UINT32 Reserved_18_13:6 ; ///< + UINT32 LcOtherSideSupportsGen2:1 ; ///< + UINT32 Reserved_26_20:7 ; ///< + UINT32 LcMultUpstreamAutoSpdChngEn:1 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_xA4_STRUCT; + +// **** DxF0xE4_xA5 Register Definition **** +// Address +#define DxF0xE4_xA5_ADDRESS 0xa5 + +// Type +#define DxF0xE4_xA5_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_xA5_LcCurrentState_OFFSET 0 +#define DxF0xE4_xA5_LcCurrentState_WIDTH 6 +#define DxF0xE4_xA5_LcCurrentState_MASK 0x3f +#define DxF0xE4_xA5_Reserved_7_6_OFFSET 6 +#define DxF0xE4_xA5_Reserved_7_6_WIDTH 2 +#define DxF0xE4_xA5_Reserved_7_6_MASK 0xc0 +#define DxF0xE4_xA5_LcPrevState1_OFFSET 8 +#define DxF0xE4_xA5_LcPrevState1_WIDTH 6 +#define DxF0xE4_xA5_LcPrevState1_MASK 0x3f00 +#define DxF0xE4_xA5_Reserved_15_14_OFFSET 14 +#define DxF0xE4_xA5_Reserved_15_14_WIDTH 2 +#define DxF0xE4_xA5_Reserved_15_14_MASK 0xc000 +#define DxF0xE4_xA5_LcPrevState2_OFFSET 16 +#define DxF0xE4_xA5_LcPrevState2_WIDTH 6 +#define DxF0xE4_xA5_LcPrevState2_MASK 0x3f0000 +#define DxF0xE4_xA5_Reserved_23_22_OFFSET 22 +#define DxF0xE4_xA5_Reserved_23_22_WIDTH 2 +#define DxF0xE4_xA5_Reserved_23_22_MASK 0xc00000 +#define DxF0xE4_xA5_LcPrevState3_OFFSET 24 +#define DxF0xE4_xA5_LcPrevState3_WIDTH 6 +#define DxF0xE4_xA5_LcPrevState3_MASK 0x3f000000 +#define DxF0xE4_xA5_Reserved_31_30_OFFSET 30 +#define DxF0xE4_xA5_Reserved_31_30_WIDTH 2 +#define DxF0xE4_xA5_Reserved_31_30_MASK 0xc0000000 + +/// DxF0xE4_xA5 +typedef union { + struct { ///< + UINT32 LcCurrentState:6 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 LcPrevState1:6 ; ///< + UINT32 Reserved_15_14:2 ; ///< + UINT32 LcPrevState2:6 ; ///< + UINT32 Reserved_23_22:2 ; ///< + UINT32 LcPrevState3:6 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_xA5_STRUCT; + +// **** DxF0xE4_xB1 Register Definition **** +// Address +#define DxF0xE4_xB1_ADDRESS 0xb1 + +// Type +#define DxF0xE4_xB1_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_xB1_Reserved_18_0_OFFSET 0 +#define DxF0xE4_xB1_Reserved_18_0_WIDTH 19 +#define DxF0xE4_xB1_Reserved_18_0_MASK 0x7ffff +#define DxF0xE4_xB1_LcDeassertRxEnInL0s_OFFSET 19 +#define DxF0xE4_xB1_LcDeassertRxEnInL0s_WIDTH 1 +#define DxF0xE4_xB1_LcDeassertRxEnInL0s_MASK 0x80000 +#define DxF0xE4_xB1_LcBlockElIdleinL0_OFFSET 20 +#define DxF0xE4_xB1_LcBlockElIdleinL0_WIDTH 1 +#define DxF0xE4_xB1_LcBlockElIdleinL0_MASK 0x100000 +#define DxF0xE4_xB1_Reserved_31_21_OFFSET 21 +#define DxF0xE4_xB1_Reserved_31_21_WIDTH 11 +#define DxF0xE4_xB1_Reserved_31_21_MASK 0xffe00000 + +/// DxF0xE4_xB1 +typedef union { + struct { ///< + UINT32 Reserved_18_0:19; ///< + UINT32 LcDeassertRxEnInL0s:1 ; ///< + UINT32 LcBlockElIdleinL0:1 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_xB1_STRUCT; + +// **** DxF0xE4_xB5 Register Definition **** +// Address +#define DxF0xE4_xB5_ADDRESS 0xb5 + +// Type +#define DxF0xE4_xB5_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_xB5_LcSelectDeemphasis_OFFSET 0 +#define DxF0xE4_xB5_LcSelectDeemphasis_WIDTH 1 +#define DxF0xE4_xB5_LcSelectDeemphasis_MASK 0x1 +#define DxF0xE4_xB5_LcSelectDeemphasisCntl_OFFSET 1 +#define DxF0xE4_xB5_LcSelectDeemphasisCntl_WIDTH 2 +#define DxF0xE4_xB5_LcSelectDeemphasisCntl_MASK 0x6 +#define DxF0xE4_xB5_LcRcvdDeemphasis_OFFSET 3 +#define DxF0xE4_xB5_LcRcvdDeemphasis_WIDTH 1 +#define DxF0xE4_xB5_LcRcvdDeemphasis_MASK 0x8 +#define DxF0xE4_xB5_Reserved_29_4_OFFSET 4 +#define DxF0xE4_xB5_Reserved_29_4_WIDTH 26 +#define DxF0xE4_xB5_Reserved_29_4_MASK 0x3ffffff0 +#define DxF0xE4_xB5_LcGoToRecovery_OFFSET 30 +#define DxF0xE4_xB5_LcGoToRecovery_WIDTH 1 +#define DxF0xE4_xB5_LcGoToRecovery_MASK 0x40000000 +#define DxF0xE4_xB5_Reserved_31_31_OFFSET 31 +#define DxF0xE4_xB5_Reserved_31_31_WIDTH 1 +#define DxF0xE4_xB5_Reserved_31_31_MASK 0x80000000 + +/// DxF0xE4_xB5 +typedef union { + struct { ///< + UINT32 LcSelectDeemphasis:1 ; ///< + UINT32 LcSelectDeemphasisCntl:2 ; ///< + UINT32 LcRcvdDeemphasis:1 ; ///< + UINT32 Reserved_29_4:26; ///< + UINT32 LcGoToRecovery:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_xB5_STRUCT; + +// **** DxF0xE4_xC0 Register Definition **** +// Address +#define DxF0xE4_xC0_ADDRESS 0xc0 + +// Type +#define DxF0xE4_xC0_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_xC0_Reserved_12_0_OFFSET 0 +#define DxF0xE4_xC0_Reserved_12_0_WIDTH 13 +#define DxF0xE4_xC0_Reserved_12_0_MASK 0x1fff +#define DxF0xE4_xC0_StrapForceCompliance_OFFSET 13 +#define DxF0xE4_xC0_StrapForceCompliance_WIDTH 1 +#define DxF0xE4_xC0_StrapForceCompliance_MASK 0x2000 +#define DxF0xE4_xC0_Reserved_14_14_OFFSET 14 +#define DxF0xE4_xC0_Reserved_14_14_WIDTH 1 +#define DxF0xE4_xC0_Reserved_14_14_MASK 0x4000 +#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET 15 +#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_WIDTH 1 +#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK 0x8000 +#define DxF0xE4_xC0_Reserved_31_16_OFFSET 16 +#define DxF0xE4_xC0_Reserved_31_16_WIDTH 16 +#define DxF0xE4_xC0_Reserved_31_16_MASK 0xffff0000 + +/// DxF0xE4_xC0 +typedef union { + struct { ///< + UINT32 Reserved_12_0:13; ///< + UINT32 StrapForceCompliance:1 ; ///< + UINT32 Reserved_14_14:1 ; ///< + UINT32 StrapAutoRcSpeedNegotiationDis:1 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_xC0_STRUCT; + +// **** DxF0xE4_xC1 Register Definition **** +// Address +#define DxF0xE4_xC1_ADDRESS 0xc1 + +// Type +#define DxF0xE4_xC1_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_xC1_StrapReverseLanes_OFFSET 0 +#define DxF0xE4_xC1_StrapReverseLanes_WIDTH 1 +#define DxF0xE4_xC1_StrapReverseLanes_MASK 0x1 +#define DxF0xE4_xC1_StrapE2EPrefixEn_OFFSET 1 +#define DxF0xE4_xC1_StrapE2EPrefixEn_WIDTH 1 +#define DxF0xE4_xC1_StrapE2EPrefixEn_MASK 0x2 +#define DxF0xE4_xC1_StrapExtendedFmtSupported_OFFSET 2 +#define DxF0xE4_xC1_StrapExtendedFmtSupported_WIDTH 1 +#define DxF0xE4_xC1_StrapExtendedFmtSupported_MASK 0x4 +#define DxF0xE4_xC1_Reserved_31_3_OFFSET 3 +#define DxF0xE4_xC1_Reserved_31_3_WIDTH 29 +#define DxF0xE4_xC1_Reserved_31_3_MASK 0xfffffff8 + +/// DxF0xE4_xC1 +typedef union { + struct { ///< + UINT32 StrapReverseLanes:1 ; ///< + UINT32 StrapE2EPrefixEn:1 ; ///< + UINT32 StrapExtendedFmtSupported:1 ; ///< + UINT32 Reserved_31_3:29; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_xC1_STRUCT; + +// **** GMMx00 Register Definition **** +// Address +#define GMMx00_ADDRESS 0x0 + +// Type +#define GMMx00_TYPE TYPE_GMM +// Field Data +#define GMMx00_MM_OFFSET_OFFSET 0 +#define GMMx00_MM_OFFSET_WIDTH 31 +#define GMMx00_MM_OFFSET_MASK 0x7fffffff +#define GMMx00_MM_APER_OFFSET 31 +#define GMMx00_MM_APER_WIDTH 1 +#define GMMx00_MM_APER_MASK 0x80000000 + +/// GMMx00 +typedef union { + struct { ///< + UINT32 MM_OFFSET:31; ///< + UINT32 MM_APER:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx00_STRUCT; + +// **** GMMx04 Register Definition **** +// Address +#define GMMx04_ADDRESS 0x4 + +// Type +#define GMMx04_TYPE TYPE_GMM +// Field Data +#define GMMx04_MM_DATA_OFFSET 0 +#define GMMx04_MM_DATA_WIDTH 32 +#define GMMx04_MM_DATA_MASK 0xffffffff + +/// GMMx04 +typedef union { + struct { ///< + UINT32 MM_DATA:32; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx04_STRUCT; + +// **** GMMx63C Register Definition **** +// Address +#define GMMx63C_ADDRESS 0x63c + +// Type +#define GMMx63C_TYPE TYPE_GMM +// Field Data +#define GMMx63C_VoltageForceEn_OFFSET 0 +#define GMMx63C_VoltageForceEn_WIDTH 1 +#define GMMx63C_VoltageForceEn_MASK 0x1 +#define GMMx63C_VoltageChangeEn_OFFSET 1 +#define GMMx63C_VoltageChangeEn_WIDTH 1 +#define GMMx63C_VoltageChangeEn_MASK 0x2 +#define GMMx63C_VoltageChangeReq_OFFSET 2 +#define GMMx63C_VoltageChangeReq_WIDTH 1 +#define GMMx63C_VoltageChangeReq_MASK 0x4 +#define GMMx63C_Reserved_7_3_OFFSET 3 +#define GMMx63C_Reserved_7_3_WIDTH 5 +#define GMMx63C_Reserved_7_3_MASK 0xf8 +#define GMMx63C_VoltageLevel_OFFSET 8 +#define GMMx63C_VoltageLevel_WIDTH 8 +#define GMMx63C_VoltageLevel_MASK 0xff00 +#define GMMx63C_Reserved_31_16_OFFSET 16 +#define GMMx63C_Reserved_31_16_WIDTH 16 +#define GMMx63C_Reserved_31_16_MASK 0xffff0000 + +/// GMMx63C +typedef union { + struct { ///< + UINT32 VoltageForceEn:1 ; ///< + UINT32 VoltageChangeEn:1 ; ///< + UINT32 VoltageChangeReq:1 ; ///< + UINT32 Reserved_7_3:5 ; ///< + UINT32 VoltageLevel:8 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx63C_STRUCT; + +// **** GMMx640 Register Definition **** +// Address +#define GMMx640_ADDRESS 0x640 + +// Type +#define GMMx640_TYPE TYPE_GMM +// Field Data +#define GMMx640_VoltageChangeAck_OFFSET 0 +#define GMMx640_VoltageChangeAck_WIDTH 1 +#define GMMx640_VoltageChangeAck_MASK 0x1 +#define GMMx640_CurrentVoltageLevel_OFFSET 1 +#define GMMx640_CurrentVoltageLevel_WIDTH 8 +#define GMMx640_CurrentVoltageLevel_MASK 0x1fe +#define GMMx640_Reserved_31_9_OFFSET 9 +#define GMMx640_Reserved_31_9_WIDTH 23 +#define GMMx640_Reserved_31_9_MASK 0xfffffe00 + +/// GMMx640 +typedef union { + struct { ///< + UINT32 VoltageChangeAck:1 ; ///< + UINT32 CurrentVoltageLevel:8 ; ///< + UINT32 Reserved_31_9:23; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx640_STRUCT; + + + +// **** GMMx770 Register Definition **** +// Address +#define GMMx770_ADDRESS 0x770 + +// Type +#define GMMx770_TYPE TYPE_GMM +// Field Data +#define GMMx770_VoltageChangeReq_OFFSET 0 +#define GMMx770_VoltageChangeReq_WIDTH 1 +#define GMMx770_VoltageChangeReq_MASK 0x1 +#define GMMx770_VoltageLevel_OFFSET 1 +#define GMMx770_VoltageLevel_WIDTH 8 +#define GMMx770_VoltageLevel_MASK 0x1fe +#define GMMx770_VoltageChangeEn_OFFSET 9 +#define GMMx770_VoltageChangeEn_WIDTH 1 +#define GMMx770_VoltageChangeEn_MASK 0x200 +#define GMMx770_VoltageForceEn_OFFSET 10 +#define GMMx770_VoltageForceEn_WIDTH 1 +#define GMMx770_VoltageForceEn_MASK 0x400 +#define GMMx770_Reserved_31_11_OFFSET 11 +#define GMMx770_Reserved_31_11_WIDTH 21 +#define GMMx770_Reserved_31_11_MASK 0xfffff800 + +/// GMMx770 +typedef union { + struct { ///< + UINT32 VoltageChangeReq:1 ; ///< + UINT32 VoltageLevel:8 ; ///< + UINT32 VoltageChangeEn:1 ; ///< + UINT32 VoltageForceEn:1 ; ///< + UINT32 Reserved_31_11:21; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx770_STRUCT; + +// **** GMMx774 Register Definition **** +// Address +#define GMMx774_ADDRESS 0x774 + +// Type +#define GMMx774_TYPE TYPE_GMM +// Field Data +#define GMMx774_VoltageChangeAck_OFFSET 0 +#define GMMx774_VoltageChangeAck_WIDTH 1 +#define GMMx774_VoltageChangeAck_MASK 0x1 +#define GMMx774_CurrentVoltageLevel_OFFSET 1 +#define GMMx774_CurrentVoltageLevel_WIDTH 8 +#define GMMx774_CurrentVoltageLevel_MASK 0x1fe +#define GMMx774_Reserved_31_9_OFFSET 9 +#define GMMx774_Reserved_31_9_WIDTH 23 +#define GMMx774_Reserved_31_9_MASK 0xfffffe00 + +/// GMMx774 +typedef union { + struct { ///< + UINT32 VoltageChangeAck:1 ; ///< + UINT32 CurrentVoltageLevel:8 ; ///< + UINT32 Reserved_31_9:23; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx774_STRUCT; + +// **** GMMx7A0 Register Definition **** +// Address +#define GMMx7A0_ADDRESS 0x7a0 + +// Type +#define GMMx7A0_TYPE TYPE_GMM +// Field Data +#define GMMx7A0_DivId_OFFSET 0 +#define GMMx7A0_DivId_WIDTH 3 +#define GMMx7A0_DivId_MASK 0x7 +#define GMMx7A0_RampDis_OFFSET 3 +#define GMMx7A0_RampDis_WIDTH 1 +#define GMMx7A0_RampDis_MASK 0x8 +#define GMMx7A0_Hysteresis_OFFSET 4 +#define GMMx7A0_Hysteresis_WIDTH 12 +#define GMMx7A0_Hysteresis_MASK 0xfff0 +#define GMMx7A0_SclkRunningMask_OFFSET 16 +#define GMMx7A0_SclkRunningMask_WIDTH 1 +#define GMMx7A0_SclkRunningMask_MASK 0x10000 +#define GMMx7A0_SmuBusyMask_OFFSET 17 +#define GMMx7A0_SmuBusyMask_WIDTH 1 +#define GMMx7A0_SmuBusyMask_MASK 0x20000 +#define GMMx7A0_PcieLclkIdle1Mask_OFFSET 18 +#define GMMx7A0_PcieLclkIdle1Mask_WIDTH 1 +#define GMMx7A0_PcieLclkIdle1Mask_MASK 0x40000 +#define GMMx7A0_PcieLclkIdle2Mask_OFFSET 19 +#define GMMx7A0_PcieLclkIdle2Mask_WIDTH 1 +#define GMMx7A0_PcieLclkIdle2Mask_MASK 0x80000 +#define GMMx7A0_L1imugfxIdleMask_OFFSET 20 +#define GMMx7A0_L1imugfxIdleMask_WIDTH 1 +#define GMMx7A0_L1imugfxIdleMask_MASK 0x100000 +#define GMMx7A0_L1imugppsbIdleMask_OFFSET 21 +#define GMMx7A0_L1imugppsbIdleMask_WIDTH 1 +#define GMMx7A0_L1imugppsbIdleMask_MASK 0x200000 +#define GMMx7A0_L1imubifIdleMask_OFFSET 22 +#define GMMx7A0_L1imubifIdleMask_WIDTH 1 +#define GMMx7A0_L1imubifIdleMask_MASK 0x400000 +#define GMMx7A0_L1imuintgenIdleMask_OFFSET 23 +#define GMMx7A0_L1imuintgenIdleMask_WIDTH 1 +#define GMMx7A0_L1imuintgenIdleMask_MASK 0x800000 +#define GMMx7A0_L2imuIdleMask_OFFSET 24 +#define GMMx7A0_L2imuIdleMask_WIDTH 1 +#define GMMx7A0_L2imuIdleMask_MASK 0x1000000 +#define GMMx7A0_OrbIdleMask_OFFSET 25 +#define GMMx7A0_OrbIdleMask_WIDTH 1 +#define GMMx7A0_OrbIdleMask_MASK 0x2000000 +#define GMMx7A0_OnInbWakeMask_OFFSET 26 +#define GMMx7A0_OnInbWakeMask_WIDTH 1 +#define GMMx7A0_OnInbWakeMask_MASK 0x4000000 +#define GMMx7A0_OnInbWakeAckMask_OFFSET 27 +#define GMMx7A0_OnInbWakeAckMask_WIDTH 1 +#define GMMx7A0_OnInbWakeAckMask_MASK 0x8000000 +#define GMMx7A0_OnOutbWakeMask_OFFSET 28 +#define GMMx7A0_OnOutbWakeMask_WIDTH 1 +#define GMMx7A0_OnOutbWakeMask_MASK 0x10000000 +#define GMMx7A0_OnOutbWakeAckMask_OFFSET 29 +#define GMMx7A0_OnOutbWakeAckMask_WIDTH 1 +#define GMMx7A0_OnOutbWakeAckMask_MASK 0x20000000 +#define GMMx7A0_DmaactiveMask_OFFSET 30 +#define GMMx7A0_DmaactiveMask_WIDTH 1 +#define GMMx7A0_DmaactiveMask_MASK 0x40000000 +#define GMMx7A0_EnableDs_OFFSET 31 +#define GMMx7A0_EnableDs_WIDTH 1 +#define GMMx7A0_EnableDs_MASK 0x80000000 + +/// GMMx7A0 +typedef union { + struct { ///< + UINT32 DivId:3 ; ///< + UINT32 RampDis:1 ; ///< + UINT32 Hysteresis:12; ///< + UINT32 SclkRunningMask:1 ; ///< + UINT32 SmuBusyMask:1 ; ///< + UINT32 PcieLclkIdle1Mask:1 ; ///< + UINT32 PcieLclkIdle2Mask:1 ; ///< + UINT32 L1imugfxIdleMask:1 ; ///< + UINT32 L1imugppsbIdleMask:1 ; ///< + UINT32 L1imubifIdleMask:1 ; ///< + UINT32 L1imuintgenIdleMask:1 ; ///< + UINT32 L2imuIdleMask:1 ; ///< + UINT32 OrbIdleMask:1 ; ///< + UINT32 OnInbWakeMask:1 ; ///< + UINT32 OnInbWakeAckMask:1 ; ///< + UINT32 OnOutbWakeMask:1 ; ///< + UINT32 OnOutbWakeAckMask:1 ; ///< + UINT32 DmaactiveMask:1 ; ///< + UINT32 EnableDs:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx7A0_STRUCT; + +// **** GMMx7B0 Register Definition **** +// Address +#define GMMx7B0_ADDRESS 0x7b0 + +// Type +#define GMMx7B0_TYPE TYPE_GMM +// Field Data +#define GMMx7B0_SMU_VOLTAGE_EN_OFFSET 0 +#define GMMx7B0_SMU_VOLTAGE_EN_WIDTH 1 +#define GMMx7B0_SMU_VOLTAGE_EN_MASK 0x1 +#define GMMx7B0_SMU_VOLTAGE_LEVEL_OFFSET 1 +#define GMMx7B0_SMU_VOLTAGE_LEVEL_WIDTH 8 +#define GMMx7B0_SMU_VOLTAGE_LEVEL_MASK 0x1fe +#define GMMx7B0_Reserved_OFFSET 9 +#define GMMx7B0_Reserved_WIDTH 23 +#define GMMx7B0_Reserved_MASK 0xfffffe00 + +/// GMMx7B0 +typedef union { + struct { ///< + UINT32 SMU_VOLTAGE_EN:1 ; ///< + UINT32 SMU_VOLTAGE_LEVEL:8 ; ///< + UINT32 Reserved:23; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx7B0_STRUCT; + +// **** GMMx898 Register Definition **** +// Address +#define GMMx898_ADDRESS 0x898 + +// Type +#define GMMx898_TYPE TYPE_GMM +// Field Data +#define GMMx898_Threshold_OFFSET 0 +#define GMMx898_Threshold_WIDTH 8 +#define GMMx898_Threshold_MASK 0xff +#define GMMx898_Reserved_31_8_OFFSET 8 +#define GMMx898_Reserved_31_8_WIDTH 24 +#define GMMx898_Reserved_31_8_MASK 0xffffff00 + +/// GMMx898 +typedef union { + struct { ///< + UINT32 Threshold:8 ; ///< + UINT32 Reserved_31_8:24; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx898_STRUCT; + +// **** GMMxC64 Register Definition **** +// Address +#define GMMxC64_ADDRESS 0xc64 + +// Type +#define GMMxC64_TYPE TYPE_GMM +// Field Data +#define GMMxC64_MCIFMEM_CACHE_MODE_DIS_OFFSET 0 +#define GMMxC64_MCIFMEM_CACHE_MODE_DIS_WIDTH 1 +#define GMMxC64_MCIFMEM_CACHE_MODE_DIS_MASK 0x1 +#define GMMxC64_Reserved_OFFSET 1 +#define GMMxC64_Reserved_WIDTH 31 +#define GMMxC64_Reserved_MASK 0xfffffffe + +/// GMMxC64 +typedef union { + struct { ///< + UINT32 MCIFMEM_CACHE_MODE_DIS:1 ; ///< + UINT32 Reserved:31; ///< + } Field; ///< + UINT32 Value; ///< +} GMMxC64_STRUCT; + + +typedef union { + struct { ///< + UINT32 CHAN0:4 ; ///< + UINT32 CHAN1:4 ; ///< + UINT32 CHAN2:4 ; ///< + UINT32 NOOFCHAN:2 ; ///< + UINT32 Reserved:18; ///< + } Field; ///< + UINT32 Value; ///< +} ex1012_STRUCT; + + + + + +// **** GMMx2024 Register Definition **** +// Address +#define GMMx2024_ADDRESS 0x2024 + +// Type +#define GMMx2024_TYPE TYPE_GMM +// Field Data +#define GMMx2024_FB_BASE_OFFSET 0 +#define GMMx2024_FB_BASE_WIDTH 16 +#define GMMx2024_FB_BASE_MASK 0xffff +#define GMMx2024_FB_TOP_OFFSET 16 +#define GMMx2024_FB_TOP_WIDTH 16 +#define GMMx2024_FB_TOP_MASK 0xffff0000 + +/// GMMx2024 +typedef union { + struct { ///< + UINT32 FB_BASE:16; ///< + UINT32 FB_TOP:16; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2024_STRUCT; + +// **** GMMx2068 Register Definition **** +// Address +#define GMMx2068_ADDRESS 0x2068 + +// Type +#define GMMx2068_TYPE TYPE_GMM +// Field Data +#define GMMx2068_FB_OFFSET_OFFSET 0 +#define GMMx2068_FB_OFFSET_WIDTH 18 +#define GMMx2068_FB_OFFSET_MASK 0x3ffff +#define GMMx2068_Reserved_OFFSET 18 +#define GMMx2068_Reserved_WIDTH 14 +#define GMMx2068_Reserved_MASK 0xfffc0000 + +/// GMMx2068 +typedef union { + struct { ///< + UINT32 FB_OFFSET:18; ///< + UINT32 Reserved:14; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2068_STRUCT; + +typedef union { + struct { ///< + UINT32 DEFAULT_STEERING:2 ; ///< + UINT32 CLIENT_STEERING:2 ; ///< + UINT32 Reserved:28; ///< + } Field; ///< + UINT32 Value; ///< +} ex1017_STRUCT; + + + + + + + +// **** GMMx20EC Register Definition **** +// Address + +// **** GMMx2114 Register Definition **** +// Address +#define GMMx2114_ADDRESS 0x2114 + +// Type +#define GMMx2114_TYPE TYPE_GMM +// Field Data +#define GMMx2114_STOR1_PRI_OFFSET 0 +#define GMMx2114_STOR1_PRI_WIDTH 8 +#define GMMx2114_STOR1_PRI_MASK 0xff +#define GMMx2114_Reserved_OFFSET 8 +#define GMMx2114_Reserved_WIDTH 24 +#define GMMx2114_Reserved_MASK 0xffffff00 + +/// GMMx2114 +typedef union { + struct { ///< + UINT32 STOR1_PRI:8 ; ///< + UINT32 Reserved:24; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2114_STRUCT; + + +// **** GMMx2188 Register Definition **** +// Address +#define GMMx2188_ADDRESS 0x2188 + +// Type +#define GMMx2188_TYPE TYPE_GMM +// Field Data +#define GMMx2188_ENABLE_OFFSET 0 +#define GMMx2188_ENABLE_WIDTH 1 +#define GMMx2188_ENABLE_MASK 0x1 +#define GMMx2188_PRESCALE_OFFSET 1 +#define GMMx2188_PRESCALE_WIDTH 2 +#define GMMx2188_PRESCALE_MASK 0x6 +#define GMMx2188_BLACKOUT_EXEMPT_OFFSET 3 +#define GMMx2188_BLACKOUT_EXEMPT_WIDTH 1 +#define GMMx2188_BLACKOUT_EXEMPT_MASK 0x8 +#define GMMx2188_STALL_MODE_OFFSET 4 +#define GMMx2188_STALL_MODE_WIDTH 2 +#define GMMx2188_STALL_MODE_MASK 0x30 +#define GMMx2188_STALL_OVERRIDE_OFFSET 6 +#define GMMx2188_STALL_OVERRIDE_WIDTH 1 +#define GMMx2188_STALL_OVERRIDE_MASK 0x40 +#define GMMx2188_MAXBURST_OFFSET 7 +#define GMMx2188_MAXBURST_WIDTH 4 +#define GMMx2188_MAXBURST_MASK 0x780 +#define GMMx2188_LAZY_TIMER_OFFSET 11 +#define GMMx2188_LAZY_TIMER_WIDTH 4 +#define GMMx2188_LAZY_TIMER_MASK 0x7800 +#define GMMx2188_STALL_OVERRIDE_WTM_OFFSET 15 +#define GMMx2188_STALL_OVERRIDE_WTM_WIDTH 1 +#define GMMx2188_STALL_OVERRIDE_WTM_MASK 0x8000 +#define GMMx2188_Reserved_OFFSET 16 +#define GMMx2188_Reserved_WIDTH 16 +#define GMMx2188_Reserved_MASK 0xffff0000 + +/// GMMx2188 +typedef union { + struct { ///< + UINT32 ENABLE:1 ; ///< + UINT32 PRESCALE:2 ; ///< + UINT32 BLACKOUT_EXEMPT:1 ; ///< + UINT32 STALL_MODE:2 ; ///< + UINT32 STALL_OVERRIDE:1 ; ///< + UINT32 MAXBURST:4 ; ///< + UINT32 LAZY_TIMER:4 ; ///< + UINT32 STALL_OVERRIDE_WTM:1 ; ///< + UINT32 Reserved:16; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2188_STRUCT; + + + + +#define GMMx21F4_STALL_OVERRIDE_OFFSET 6 +typedef union { + struct { ///< + UINT32 UVD_OPTIMIZE:1 ; ///< + UINT32 VCE_OPTIMIZE:1 ; ///< + UINT32 XB_UVD_OPTIMIZE:1 ; ///< + UINT32 XB_VCE_OPTIMIZE:1 ; ///< + UINT32 CITF_UVD_OPPOSITE_CHAN:1 ; ///< + UINT32 CITF_UMC_OPPOSITE_CHAN:1 ; ///< + UINT32 CITF_VCE_OPPOSITE_CHAN:1 ; ///< + UINT32 CITF_VCEU_OPPOSITE_CHAN:1 ; ///< + UINT32 Reserved:24; ///< + } Field; ///< + UINT32 Value; ///< +} ex1034_STRUCT; + + +// **** GMMx25C0 Register Definition **** +// Address +#define GMMx25C0_ADDRESS 0x25c0 + +// Type +#define GMMx25C0_TYPE TYPE_GMM +// Field Data +#define GMMx25C0_Reserved_OFFSET 0 +#define GMMx25C0_Reserved_WIDTH 2 +#define GMMx25C0_Reserved_MASK 0x3 +#define GMMx25C0_IGNOREPM_OFFSET 2 +#define GMMx25C0_IGNOREPM_WIDTH 1 +#define GMMx25C0_IGNOREPM_MASK 0x4 +#define GMMx25C0_EXEMPTPM_OFFSET 3 +#define GMMx25C0_EXEMPTPM_WIDTH 1 +#define GMMx25C0_EXEMPTPM_MASK 0x8 +#define GMMx25C0_GFX_IDLE_OVERRIDE_OFFSET 4 +#define GMMx25C0_GFX_IDLE_OVERRIDE_WIDTH 2 +#define GMMx25C0_GFX_IDLE_OVERRIDE_MASK 0x30 +#define GMMx25C0_MCD_SRBM_MASK_ENABLE_OFFSET 6 +#define GMMx25C0_MCD_SRBM_MASK_ENABLE_WIDTH 1 +#define GMMx25C0_MCD_SRBM_MASK_ENABLE_MASK 0x40 +#define GMMx25C0_DUMMY_OFFSET 7 +#define GMMx25C0_DUMMY_WIDTH 7 +#define GMMx25C0_DUMMY_MASK 0x3f80 +#define GMMx25C0_Reserved14_31_OFFSET 14 +#define GMMx25C0_Reserved14_31_WIDTH 18 +#define GMMx25C0_Reserved14_31_MASK 0xffffc000 + +/// GMMx25C0 +typedef union { + struct { ///< + UINT32 Reserved:2 ; ///< + UINT32 IGNOREPM:1 ; ///< + UINT32 EXEMPTPM:1 ; ///< + UINT32 GFX_IDLE_OVERRIDE:2 ; ///< + UINT32 MCD_SRBM_MASK_ENABLE:1 ; ///< + UINT32 DUMMY:7 ; ///< + UINT32 Reserved14_31:18; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx25C0_STRUCT; + +// **** GMMx25C8 Register Definition **** +// Address +#define GMMx25C8_ADDRESS 0x25c8 + +// Type +#define GMMx25C8_TYPE TYPE_GMM +// Field Data +#define GMMx25C8_READ_LCL_OFFSET 0 +#define GMMx25C8_READ_LCL_WIDTH 8 +#define GMMx25C8_READ_LCL_MASK 0xff +#define GMMx25C8_READ_HUB_OFFSET 8 +#define GMMx25C8_READ_HUB_WIDTH 8 +#define GMMx25C8_READ_HUB_MASK 0xff00 +#define GMMx25C8_READ_PRI_OFFSET 16 +#define GMMx25C8_READ_PRI_WIDTH 8 +#define GMMx25C8_READ_PRI_MASK 0xff0000 +#define GMMx25C8_LCL_PRI_OFFSET 24 +#define GMMx25C8_LCL_PRI_WIDTH 1 +#define GMMx25C8_LCL_PRI_MASK 0x1000000 +#define GMMx25C8_HUB_PRI_OFFSET 25 +#define GMMx25C8_HUB_PRI_WIDTH 1 +#define GMMx25C8_HUB_PRI_MASK 0x2000000 +#define GMMx25C8_Reserved_OFFSET 26 +#define GMMx25C8_Reserved_WIDTH 6 +#define GMMx25C8_Reserved_MASK 0xfc000000 + +/// GMMx25C8 +typedef union { + struct { ///< + UINT32 READ_LCL:8 ; ///< + UINT32 READ_HUB:8 ; ///< + UINT32 READ_PRI:8 ; ///< + UINT32 LCL_PRI:1 ; ///< + UINT32 HUB_PRI:1 ; ///< + UINT32 Reserved:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx25C8_STRUCT; + +typedef union { + struct { ///< + UINT32 ex1047_0:8; + UINT32 ex1047_1:8; + UINT32 ex1047_2:8; + UINT32 ex1047_3:8; + } Field; ///< + UINT32 Value; ///< +} ex1047_STRUCT; + +typedef union { + struct { ///< + UINT32 ex1048_0:8; + UINT32 ex1048_1:8; + UINT32 ex1048_2:8; + UINT32 ex1048_3:5; + UINT32 Reserved:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} ex1048_STRUCT; + +typedef union { + struct { ///< + UINT32 ex1060_0:8; + UINT32 ex1060_1:8; + UINT32 ex1060_2:8; + UINT32 ex1060_3:8; + } Field; ///< + UINT32 Value; ///< +} ex1060_STRUCT; + +typedef union { + struct { ///< + UINT32 ex1061_0:8; + UINT32 ex1061_1:8; + UINT32 ex1061_2:8; + UINT32 ex1061_3:5; + UINT32 Reserved:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} ex1061_STRUCT; + +typedef union { + struct { ///< + UINT32 ex1062_0:5; + UINT32 ex1062_1:5; + UINT32 STATE2:5 ; ///< + UINT32 STATE3:5 ; ///< + UINT32 Reserved:12; ///< + } Field; ///< + UINT32 Value; ///< +} ex1062_STRUCT; + +// **** GMMx2814 Register Definition **** +// Address +#define GMMx2814_ADDRESS 0x2814 + +// Type +#define GMMx2814_TYPE TYPE_GMM +// Field Data +#define GMMx2814_CSENABLE_OFFSET 0 +#define GMMx2814_CSENABLE_WIDTH 1 +#define GMMx2814_CSENABLE_MASK 0x1 +#define GMMx2814_Reserved_OFFSET 1 +#define GMMx2814_Reserved_WIDTH 4 +#define GMMx2814_Reserved_MASK 0x1e +#define GMMx2814_BASEADDR21_11_OFFSET 5 +#define GMMx2814_BASEADDR21_11_WIDTH 11 +#define GMMx2814_BASEADDR21_11_MASK 0xffe0 +#define GMMx2814_Reserved16_18_OFFSET 16 +#define GMMx2814_Reserved16_18_WIDTH 3 +#define GMMx2814_Reserved16_18_MASK 0x70000 +#define GMMx2814_BASEADDR38_27_OFFSET 19 +#define GMMx2814_BASEADDR38_27_WIDTH 12 +#define GMMx2814_BASEADDR38_27_MASK 0x7ff80000 +#define GMMx2814_Reserved31_31_OFFSET 31 +#define GMMx2814_Reserved31_31_WIDTH 1 +#define GMMx2814_Reserved31_31_MASK 0x80000000 + +/// GMMx2814 +typedef union { + struct { ///< + UINT32 CSENABLE:1 ; ///< + UINT32 Reserved:4 ; ///< + UINT32 BASEADDR21_11:11; ///< + UINT32 Reserved16_18:3 ; ///< + UINT32 BASEADDR38_27:12; ///< + UINT32 Reserved31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2814_STRUCT; + +// **** GMMx2818 Register Definition **** +// Address +#define GMMx2818_ADDRESS 0x2818 + +// Type +#define GMMx2818_TYPE TYPE_GMM +// Field Data +#define GMMx2818_CSENABLE_OFFSET 0 +#define GMMx2818_CSENABLE_WIDTH 1 +#define GMMx2818_CSENABLE_MASK 0x1 +#define GMMx2818_Reserved_OFFSET 1 +#define GMMx2818_Reserved_WIDTH 4 +#define GMMx2818_Reserved_MASK 0x1e +#define GMMx2818_BASEADDR21_11_OFFSET 5 +#define GMMx2818_BASEADDR21_11_WIDTH 11 +#define GMMx2818_BASEADDR21_11_MASK 0xffe0 +#define GMMx2818_Reserved16_18_OFFSET 16 +#define GMMx2818_Reserved16_18_WIDTH 3 +#define GMMx2818_Reserved16_18_MASK 0x70000 +#define GMMx2818_BASEADDR38_27_OFFSET 19 +#define GMMx2818_BASEADDR38_27_WIDTH 12 +#define GMMx2818_BASEADDR38_27_MASK 0x7ff80000 +#define GMMx2818_Reserved31_31_OFFSET 31 +#define GMMx2818_Reserved31_31_WIDTH 1 +#define GMMx2818_Reserved31_31_MASK 0x80000000 + +/// GMMx2818 +typedef union { + struct { ///< + UINT32 CSENABLE:1 ; ///< + UINT32 Reserved:4 ; ///< + UINT32 BASEADDR21_11:11; ///< + UINT32 Reserved16_18:3 ; ///< + UINT32 BASEADDR38_27:12; ///< + UINT32 Reserved31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2818_STRUCT; + +// **** GMMx281C Register Definition **** +// Address +#define GMMx281C_ADDRESS 0x281c + +// Type +#define GMMx281C_TYPE TYPE_GMM +// Field Data +#define GMMx281C_CSENABLE_OFFSET 0 +#define GMMx281C_CSENABLE_WIDTH 1 +#define GMMx281C_CSENABLE_MASK 0x1 +#define GMMx281C_Reserved_OFFSET 1 +#define GMMx281C_Reserved_WIDTH 4 +#define GMMx281C_Reserved_MASK 0x1e +#define GMMx281C_BASEADDR21_11_OFFSET 5 +#define GMMx281C_BASEADDR21_11_WIDTH 11 +#define GMMx281C_BASEADDR21_11_MASK 0xffe0 +#define GMMx281C_Reserved16_18_OFFSET 16 +#define GMMx281C_Reserved16_18_WIDTH 3 +#define GMMx281C_Reserved16_18_MASK 0x70000 +#define GMMx281C_BASEADDR38_27_OFFSET 19 +#define GMMx281C_BASEADDR38_27_WIDTH 12 +#define GMMx281C_BASEADDR38_27_MASK 0x7ff80000 +#define GMMx281C_Reserved31_31_OFFSET 31 +#define GMMx281C_Reserved31_31_WIDTH 1 +#define GMMx281C_Reserved31_31_MASK 0x80000000 + +/// GMMx281C +typedef union { + struct { ///< + UINT32 CSENABLE:1 ; ///< + UINT32 Reserved:4 ; ///< + UINT32 BASEADDR21_11:11; ///< + UINT32 Reserved16_18:3 ; ///< + UINT32 BASEADDR38_27:12; ///< + UINT32 Reserved31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx281C_STRUCT; + +// **** GMMx2820 Register Definition **** +// Address +#define GMMx2820_ADDRESS 0x2820 + +// Type +#define GMMx2820_TYPE TYPE_GMM +// Field Data +#define GMMx2820_CSENABLE_OFFSET 0 +#define GMMx2820_CSENABLE_WIDTH 1 +#define GMMx2820_CSENABLE_MASK 0x1 +#define GMMx2820_Reserved_OFFSET 1 +#define GMMx2820_Reserved_WIDTH 4 +#define GMMx2820_Reserved_MASK 0x1e +#define GMMx2820_BASEADDR21_11_OFFSET 5 +#define GMMx2820_BASEADDR21_11_WIDTH 11 +#define GMMx2820_BASEADDR21_11_MASK 0xffe0 +#define GMMx2820_Reserved16_18_OFFSET 16 +#define GMMx2820_Reserved16_18_WIDTH 3 +#define GMMx2820_Reserved16_18_MASK 0x70000 +#define GMMx2820_BASEADDR38_27_OFFSET 19 +#define GMMx2820_BASEADDR38_27_WIDTH 12 +#define GMMx2820_BASEADDR38_27_MASK 0x7ff80000 +#define GMMx2820_Reserved31_31_OFFSET 31 +#define GMMx2820_Reserved31_31_WIDTH 1 +#define GMMx2820_Reserved31_31_MASK 0x80000000 + +/// GMMx2820 +typedef union { + struct { ///< + UINT32 CSENABLE:1 ; ///< + UINT32 Reserved:4 ; ///< + UINT32 BASEADDR21_11:11; ///< + UINT32 Reserved16_18:3 ; ///< + UINT32 BASEADDR38_27:12; ///< + UINT32 Reserved31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2820_STRUCT; + +// **** GMMx2824 Register Definition **** +// Address +#define GMMx2824_ADDRESS 0x2824 + +// Type +#define GMMx2824_TYPE TYPE_GMM +// Field Data +#define GMMx2824_CSENABLE_OFFSET 0 +#define GMMx2824_CSENABLE_WIDTH 1 +#define GMMx2824_CSENABLE_MASK 0x1 +#define GMMx2824_Reserved_OFFSET 1 +#define GMMx2824_Reserved_WIDTH 4 +#define GMMx2824_Reserved_MASK 0x1e +#define GMMx2824_BASEADDR21_11_OFFSET 5 +#define GMMx2824_BASEADDR21_11_WIDTH 11 +#define GMMx2824_BASEADDR21_11_MASK 0xffe0 +#define GMMx2824_Reserved16_18_OFFSET 16 +#define GMMx2824_Reserved16_18_WIDTH 3 +#define GMMx2824_Reserved16_18_MASK 0x70000 +#define GMMx2824_BASEADDR38_27_OFFSET 19 +#define GMMx2824_BASEADDR38_27_WIDTH 12 +#define GMMx2824_BASEADDR38_27_MASK 0x7ff80000 +#define GMMx2824_Reserved31_31_OFFSET 31 +#define GMMx2824_Reserved31_31_WIDTH 1 +#define GMMx2824_Reserved31_31_MASK 0x80000000 + +/// GMMx2824 +typedef union { + struct { ///< + UINT32 CSENABLE:1 ; ///< + UINT32 Reserved:4 ; ///< + UINT32 BASEADDR21_11:11; ///< + UINT32 Reserved16_18:3 ; ///< + UINT32 BASEADDR38_27:12; ///< + UINT32 Reserved31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2824_STRUCT; + +// **** GMMx2828 Register Definition **** +// Address +#define GMMx2828_ADDRESS 0x2828 + +// Type +#define GMMx2828_TYPE TYPE_GMM +// Field Data +#define GMMx2828_CSENABLE_OFFSET 0 +#define GMMx2828_CSENABLE_WIDTH 1 +#define GMMx2828_CSENABLE_MASK 0x1 +#define GMMx2828_Reserved_OFFSET 1 +#define GMMx2828_Reserved_WIDTH 4 +#define GMMx2828_Reserved_MASK 0x1e +#define GMMx2828_BASEADDR21_11_OFFSET 5 +#define GMMx2828_BASEADDR21_11_WIDTH 11 +#define GMMx2828_BASEADDR21_11_MASK 0xffe0 +#define GMMx2828_Reserved16_18_OFFSET 16 +#define GMMx2828_Reserved16_18_WIDTH 3 +#define GMMx2828_Reserved16_18_MASK 0x70000 +#define GMMx2828_BASEADDR38_27_OFFSET 19 +#define GMMx2828_BASEADDR38_27_WIDTH 12 +#define GMMx2828_BASEADDR38_27_MASK 0x7ff80000 +#define GMMx2828_Reserved31_31_OFFSET 31 +#define GMMx2828_Reserved31_31_WIDTH 1 +#define GMMx2828_Reserved31_31_MASK 0x80000000 + +/// GMMx2828 +typedef union { + struct { ///< + UINT32 CSENABLE:1 ; ///< + UINT32 Reserved:4 ; ///< + UINT32 BASEADDR21_11:11; ///< + UINT32 Reserved16_18:3 ; ///< + UINT32 BASEADDR38_27:12; ///< + UINT32 Reserved31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2828_STRUCT; + +// **** GMMx282C Register Definition **** +// Address +#define GMMx282C_ADDRESS 0x282c + +// Type +#define GMMx282C_TYPE TYPE_GMM +// Field Data +#define GMMx282C_CSENABLE_OFFSET 0 +#define GMMx282C_CSENABLE_WIDTH 1 +#define GMMx282C_CSENABLE_MASK 0x1 +#define GMMx282C_Reserved_OFFSET 1 +#define GMMx282C_Reserved_WIDTH 4 +#define GMMx282C_Reserved_MASK 0x1e +#define GMMx282C_BASEADDR21_11_OFFSET 5 +#define GMMx282C_BASEADDR21_11_WIDTH 11 +#define GMMx282C_BASEADDR21_11_MASK 0xffe0 +#define GMMx282C_Reserved16_18_OFFSET 16 +#define GMMx282C_Reserved16_18_WIDTH 3 +#define GMMx282C_Reserved16_18_MASK 0x70000 +#define GMMx282C_BASEADDR38_27_OFFSET 19 +#define GMMx282C_BASEADDR38_27_WIDTH 12 +#define GMMx282C_BASEADDR38_27_MASK 0x7ff80000 +#define GMMx282C_Reserved31_31_OFFSET 31 +#define GMMx282C_Reserved31_31_WIDTH 1 +#define GMMx282C_Reserved31_31_MASK 0x80000000 + +/// GMMx282C +typedef union { + struct { ///< + UINT32 CSENABLE:1 ; ///< + UINT32 Reserved:4 ; ///< + UINT32 BASEADDR21_11:11; ///< + UINT32 Reserved16_18:3 ; ///< + UINT32 BASEADDR38_27:12; ///< + UINT32 Reserved31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx282C_STRUCT; + +// **** GMMx2830 Register Definition **** +// Address +#define GMMx2830_ADDRESS 0x2830 + +// Type +#define GMMx2830_TYPE TYPE_GMM +// Field Data +#define GMMx2830_CSENABLE_OFFSET 0 +#define GMMx2830_CSENABLE_WIDTH 1 +#define GMMx2830_CSENABLE_MASK 0x1 +#define GMMx2830_Reserved_OFFSET 1 +#define GMMx2830_Reserved_WIDTH 4 +#define GMMx2830_Reserved_MASK 0x1e +#define GMMx2830_BASEADDR21_11_OFFSET 5 +#define GMMx2830_BASEADDR21_11_WIDTH 11 +#define GMMx2830_BASEADDR21_11_MASK 0xffe0 +#define GMMx2830_Reserved16_18_OFFSET 16 +#define GMMx2830_Reserved16_18_WIDTH 3 +#define GMMx2830_Reserved16_18_MASK 0x70000 +#define GMMx2830_BASEADDR38_27_OFFSET 19 +#define GMMx2830_BASEADDR38_27_WIDTH 12 +#define GMMx2830_BASEADDR38_27_MASK 0x7ff80000 +#define GMMx2830_Reserved31_31_OFFSET 31 +#define GMMx2830_Reserved31_31_WIDTH 1 +#define GMMx2830_Reserved31_31_MASK 0x80000000 + +/// GMMx2830 +typedef union { + struct { ///< + UINT32 CSENABLE:1 ; ///< + UINT32 Reserved:4 ; ///< + UINT32 BASEADDR21_11:11; ///< + UINT32 Reserved16_18:3 ; ///< + UINT32 BASEADDR38_27:12; ///< + UINT32 Reserved31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2830_STRUCT; + +// **** GMMx2834 Register Definition **** +// Address +#define GMMx2834_ADDRESS 0x2834 + +// Type +#define GMMx2834_TYPE TYPE_GMM +// Field Data +#define GMMx2834_Reserved_OFFSET 0 +#define GMMx2834_Reserved_WIDTH 5 +#define GMMx2834_Reserved_MASK 0x1f +#define GMMx2834_ADDRMASK21_11_OFFSET 5 +#define GMMx2834_ADDRMASK21_11_WIDTH 11 +#define GMMx2834_ADDRMASK21_11_MASK 0xffe0 +#define GMMx2834_Reserved16_18_OFFSET 16 +#define GMMx2834_Reserved16_18_WIDTH 3 +#define GMMx2834_Reserved16_18_MASK 0x70000 +#define GMMx2834_ADDRMASK38_27_OFFSET 19 +#define GMMx2834_ADDRMASK38_27_WIDTH 12 +#define GMMx2834_ADDRMASK38_27_MASK 0x7ff80000 +#define GMMx2834_Reserved31_31_OFFSET 31 +#define GMMx2834_Reserved31_31_WIDTH 1 +#define GMMx2834_Reserved31_31_MASK 0x80000000 + +/// GMMx2834 +typedef union { + struct { ///< + UINT32 Reserved:5 ; ///< + UINT32 ADDRMASK21_11:11; ///< + UINT32 Reserved16_18:3 ; ///< + UINT32 ADDRMASK38_27:12; ///< + UINT32 Reserved31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2834_STRUCT; + +// **** GMMx2838 Register Definition **** +// Address +#define GMMx2838_ADDRESS 0x2838 + +// Type +#define GMMx2838_TYPE TYPE_GMM +// Field Data +#define GMMx2838_Reserved_OFFSET 0 +#define GMMx2838_Reserved_WIDTH 5 +#define GMMx2838_Reserved_MASK 0x1f +#define GMMx2838_ADDRMASK21_11_OFFSET 5 +#define GMMx2838_ADDRMASK21_11_WIDTH 11 +#define GMMx2838_ADDRMASK21_11_MASK 0xffe0 +#define GMMx2838_Reserved16_18_OFFSET 16 +#define GMMx2838_Reserved16_18_WIDTH 3 +#define GMMx2838_Reserved16_18_MASK 0x70000 +#define GMMx2838_ADDRMASK38_27_OFFSET 19 +#define GMMx2838_ADDRMASK38_27_WIDTH 12 +#define GMMx2838_ADDRMASK38_27_MASK 0x7ff80000 +#define GMMx2838_Reserved31_31_OFFSET 31 +#define GMMx2838_Reserved31_31_WIDTH 1 +#define GMMx2838_Reserved31_31_MASK 0x80000000 + +/// GMMx2838 +typedef union { + struct { ///< + UINT32 Reserved:5 ; ///< + UINT32 ADDRMASK21_11:11; ///< + UINT32 Reserved16_18:3 ; ///< + UINT32 ADDRMASK38_27:12; ///< + UINT32 Reserved31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2838_STRUCT; + +// **** GMMx283C Register Definition **** +// Address +#define GMMx283C_ADDRESS 0x283c + +// Type +#define GMMx283C_TYPE TYPE_GMM +// Field Data +#define GMMx283C_Reserved_OFFSET 0 +#define GMMx283C_Reserved_WIDTH 5 +#define GMMx283C_Reserved_MASK 0x1f +#define GMMx283C_ADDRMASK21_11_OFFSET 5 +#define GMMx283C_ADDRMASK21_11_WIDTH 11 +#define GMMx283C_ADDRMASK21_11_MASK 0xffe0 +#define GMMx283C_Reserved16_18_OFFSET 16 +#define GMMx283C_Reserved16_18_WIDTH 3 +#define GMMx283C_Reserved16_18_MASK 0x70000 +#define GMMx283C_ADDRMASK38_27_OFFSET 19 +#define GMMx283C_ADDRMASK38_27_WIDTH 12 +#define GMMx283C_ADDRMASK38_27_MASK 0x7ff80000 +#define GMMx283C_Reserved31_31_OFFSET 31 +#define GMMx283C_Reserved31_31_WIDTH 1 +#define GMMx283C_Reserved31_31_MASK 0x80000000 + +/// GMMx283C +typedef union { + struct { ///< + UINT32 Reserved:5 ; ///< + UINT32 ADDRMASK21_11:11; ///< + UINT32 Reserved16_18:3 ; ///< + UINT32 ADDRMASK38_27:12; ///< + UINT32 Reserved31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx283C_STRUCT; + +// **** GMMx2840 Register Definition **** +// Address +#define GMMx2840_ADDRESS 0x2840 + +// Type +#define GMMx2840_TYPE TYPE_GMM +// Field Data +#define GMMx2840_Reserved_OFFSET 0 +#define GMMx2840_Reserved_WIDTH 5 +#define GMMx2840_Reserved_MASK 0x1f +#define GMMx2840_ADDRMASK21_11_OFFSET 5 +#define GMMx2840_ADDRMASK21_11_WIDTH 11 +#define GMMx2840_ADDRMASK21_11_MASK 0xffe0 +#define GMMx2840_Reserved16_18_OFFSET 16 +#define GMMx2840_Reserved16_18_WIDTH 3 +#define GMMx2840_Reserved16_18_MASK 0x70000 +#define GMMx2840_ADDRMASK38_27_OFFSET 19 +#define GMMx2840_ADDRMASK38_27_WIDTH 12 +#define GMMx2840_ADDRMASK38_27_MASK 0x7ff80000 +#define GMMx2840_Reserved31_31_OFFSET 31 +#define GMMx2840_Reserved31_31_WIDTH 1 +#define GMMx2840_Reserved31_31_MASK 0x80000000 + +/// GMMx2840 +typedef union { + struct { ///< + UINT32 Reserved:5 ; ///< + UINT32 ADDRMASK21_11:11; ///< + UINT32 Reserved16_18:3 ; ///< + UINT32 ADDRMASK38_27:12; ///< + UINT32 Reserved31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2840_STRUCT; + +// **** GMMx2844 Register Definition **** +// Address +#define GMMx2844_ADDRESS 0x2844 + +// Type +#define GMMx2844_TYPE TYPE_GMM +// Field Data +#define GMMx2844_DIMM0ADDRMAP_OFFSET 0 +#define GMMx2844_DIMM0ADDRMAP_WIDTH 4 +#define GMMx2844_DIMM0ADDRMAP_MASK 0xf +#define GMMx2844_DIMM1ADDRMAP_OFFSET 4 +#define GMMx2844_DIMM1ADDRMAP_WIDTH 4 +#define GMMx2844_DIMM1ADDRMAP_MASK 0xf0 +#define GMMx2844_Reserved_OFFSET 8 +#define GMMx2844_Reserved_WIDTH 8 +#define GMMx2844_Reserved_MASK 0xff00 +#define GMMx2844_BANKSWIZZLEMODE_OFFSET 16 +#define GMMx2844_BANKSWIZZLEMODE_WIDTH 1 +#define GMMx2844_BANKSWIZZLEMODE_MASK 0x10000 +#define GMMx2844_DDR3MODE_OFFSET 17 +#define GMMx2844_DDR3MODE_WIDTH 1 +#define GMMx2844_DDR3MODE_MASK 0x20000 +#define GMMx2844_BURSTLENGTH32_OFFSET 18 +#define GMMx2844_BURSTLENGTH32_WIDTH 1 +#define GMMx2844_BURSTLENGTH32_MASK 0x40000 +#define GMMx2844_BANKSWAP_OFFSET 19 +#define GMMx2844_BANKSWAP_WIDTH 1 +#define GMMx2844_BANKSWAP_MASK 0x80000 +#define GMMx2844_Reserved20_31_OFFSET 20 +#define GMMx2844_Reserved20_31_WIDTH 12 +#define GMMx2844_Reserved20_31_MASK 0xfff00000 + +/// GMMx2844 +typedef union { + struct { ///< + UINT32 DIMM0ADDRMAP:4 ; ///< + UINT32 DIMM1ADDRMAP:4 ; ///< + UINT32 Reserved:8 ; ///< + UINT32 BANKSWIZZLEMODE:1 ; ///< + UINT32 DDR3MODE:1 ; ///< + UINT32 BURSTLENGTH32:1 ; ///< + UINT32 BANKSWAP:1 ; ///< + UINT32 Reserved20_31:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2844_STRUCT; + +// **** GMMx2848 Register Definition **** +// Address +#define GMMx2848_ADDRESS 0x2848 + +// Type +#define GMMx2848_TYPE TYPE_GMM +// Field Data +#define GMMx2848_DIMM0ADDRMAP_OFFSET 0 +#define GMMx2848_DIMM0ADDRMAP_WIDTH 4 +#define GMMx2848_DIMM0ADDRMAP_MASK 0xf +#define GMMx2848_DIMM1ADDRMAP_OFFSET 4 +#define GMMx2848_DIMM1ADDRMAP_WIDTH 4 +#define GMMx2848_DIMM1ADDRMAP_MASK 0xf0 +#define GMMx2848_Reserved_OFFSET 8 +#define GMMx2848_Reserved_WIDTH 8 +#define GMMx2848_Reserved_MASK 0xff00 +#define GMMx2848_BANKSWIZZLEMODE_OFFSET 16 +#define GMMx2848_BANKSWIZZLEMODE_WIDTH 1 +#define GMMx2848_BANKSWIZZLEMODE_MASK 0x10000 +#define GMMx2848_DDR3MODE_OFFSET 17 +#define GMMx2848_DDR3MODE_WIDTH 1 +#define GMMx2848_DDR3MODE_MASK 0x20000 +#define GMMx2848_BURSTLENGTH32_OFFSET 18 +#define GMMx2848_BURSTLENGTH32_WIDTH 1 +#define GMMx2848_BURSTLENGTH32_MASK 0x40000 +#define GMMx2848_BANKSWAP_OFFSET 19 +#define GMMx2848_BANKSWAP_WIDTH 1 +#define GMMx2848_BANKSWAP_MASK 0x80000 +#define GMMx2848_Reserved20_31_OFFSET 20 +#define GMMx2848_Reserved20_31_WIDTH 12 +#define GMMx2848_Reserved20_31_MASK 0xfff00000 + +/// GMMx2848 +typedef union { + struct { ///< + UINT32 DIMM0ADDRMAP:4 ; ///< + UINT32 DIMM1ADDRMAP:4 ; ///< + UINT32 Reserved:8 ; ///< + UINT32 BANKSWIZZLEMODE:1 ; ///< + UINT32 DDR3MODE:1 ; ///< + UINT32 BURSTLENGTH32:1 ; ///< + UINT32 BANKSWAP:1 ; ///< + UINT32 Reserved20_31:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2848_STRUCT; + +// **** GMMx284C Register Definition **** +// Address +#define GMMx284C_ADDRESS 0x284c + +// Type +#define GMMx284C_TYPE TYPE_GMM +// Field Data +#define GMMx284C_DCTSELHIRNGEN_OFFSET 0 +#define GMMx284C_DCTSELHIRNGEN_WIDTH 1 +#define GMMx284C_DCTSELHIRNGEN_MASK 0x1 +#define GMMx284C_DCTSELHI_OFFSET 1 +#define GMMx284C_DCTSELHI_WIDTH 1 +#define GMMx284C_DCTSELHI_MASK 0x2 +#define GMMx284C_DCTSELINTLVEN_OFFSET 2 +#define GMMx284C_DCTSELINTLVEN_WIDTH 1 +#define GMMx284C_DCTSELINTLVEN_MASK 0x4 +#define GMMx284C_Reserved_OFFSET 3 +#define GMMx284C_Reserved_WIDTH 3 +#define GMMx284C_Reserved_MASK 0x38 +#define GMMx284C_DCTSELINTLVADDR_1_0_OFFSET 6 +#define GMMx284C_DCTSELINTLVADDR_1_0_WIDTH 2 +#define GMMx284C_DCTSELINTLVADDR_1_0_MASK 0xc0 +#define GMMx284C_Reserved8_10_OFFSET 8 +#define GMMx284C_Reserved8_10_WIDTH 3 +#define GMMx284C_Reserved8_10_MASK 0x700 +#define GMMx284C_DCTSELBASEADDR39_27_OFFSET 11 +#define GMMx284C_DCTSELBASEADDR39_27_WIDTH 13 +#define GMMx284C_DCTSELBASEADDR39_27_MASK 0xfff800 +#define GMMx284C_Reserved24_31_OFFSET 24 +#define GMMx284C_Reserved24_31_WIDTH 8 +#define GMMx284C_Reserved24_31_MASK 0xff000000 + +/// GMMx284C +typedef union { + struct { ///< + UINT32 DCTSELHIRNGEN:1 ; ///< + UINT32 DCTSELHI:1 ; ///< + UINT32 DCTSELINTLVEN:1 ; ///< + UINT32 Reserved:3 ; ///< + UINT32 DCTSELINTLVADDR_1_0:2 ; ///< + UINT32 Reserved8_10:3 ; ///< + UINT32 DCTSELBASEADDR39_27:13; ///< + UINT32 Reserved24_31:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx284C_STRUCT; + +// **** GMMx2850 Register Definition **** +// Address +#define GMMx2850_ADDRESS 0x2850 + +// Type +#define GMMx2850_TYPE TYPE_GMM +// Field Data +#define GMMx2850_Reserved_OFFSET 0 +#define GMMx2850_Reserved_WIDTH 9 +#define GMMx2850_Reserved_MASK 0x1ff +#define GMMx2850_DCTSELINTLVADDR_2_OFFSET 9 +#define GMMx2850_DCTSELINTLVADDR_2_WIDTH 1 +#define GMMx2850_DCTSELINTLVADDR_2_MASK 0x200 +#define GMMx2850_DCTSELBASEOFFSET_39_26_OFFSET 10 +#define GMMx2850_DCTSELBASEOFFSET_39_26_WIDTH 14 +#define GMMx2850_DCTSELBASEOFFSET_39_26_MASK 0xfffc00 +#define GMMx2850_Reserved24_31_OFFSET 24 +#define GMMx2850_Reserved24_31_WIDTH 8 +#define GMMx2850_Reserved24_31_MASK 0xff000000 + +/// GMMx2850 +typedef union { + struct { ///< + UINT32 Reserved:9 ; ///< + UINT32 DCTSELINTLVADDR_2:1 ; ///< + UINT32 DCTSELBASEOFFSET_39_26:14; ///< + UINT32 Reserved24_31:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2850_STRUCT; + +// **** GMMx2854 Register Definition **** +// Address +#define GMMx2854_ADDRESS 0x2854 + +// Type +#define GMMx2854_TYPE TYPE_GMM +// Field Data +#define GMMx2854_DRAMHOLEVALID_OFFSET 0 +#define GMMx2854_DRAMHOLEVALID_WIDTH 1 +#define GMMx2854_DRAMHOLEVALID_MASK 0x1 +#define GMMx2854_Reserved_OFFSET 1 +#define GMMx2854_Reserved_WIDTH 1 +#define GMMx2854_Reserved_MASK 0x2 +#define GMMx2854_DRAMHTHOLEVALID_OFFSET 2 +#define GMMx2854_DRAMHTHOLEVALID_WIDTH 1 +#define GMMx2854_DRAMHTHOLEVALID_MASK 0x4 +#define GMMx2854_Reserved3_6_OFFSET 3 +#define GMMx2854_Reserved3_6_WIDTH 4 +#define GMMx2854_Reserved3_6_MASK 0x78 +#define GMMx2854_DRAMHOLEOFFSET31_23_OFFSET 7 +#define GMMx2854_DRAMHOLEOFFSET31_23_WIDTH 9 +#define GMMx2854_DRAMHOLEOFFSET31_23_MASK 0xff80 +#define GMMx2854_Reserved16_23_OFFSET 16 +#define GMMx2854_Reserved16_23_WIDTH 8 +#define GMMx2854_Reserved16_23_MASK 0xff0000 +#define GMMx2854_DRAMHOLEBASE31_24_OFFSET 24 +#define GMMx2854_DRAMHOLEBASE31_24_WIDTH 8 +#define GMMx2854_DRAMHOLEBASE31_24_MASK 0xff000000 + +/// GMMx2854 +typedef union { + struct { ///< + UINT32 DRAMHOLEVALID:1 ; ///< + UINT32 Reserved:1 ; ///< + UINT32 DRAMHTHOLEVALID:1 ; ///< + UINT32 Reserved3_6:4 ; ///< + UINT32 DRAMHOLEOFFSET31_23:9 ; ///< + UINT32 Reserved16_23:8 ; ///< + UINT32 DRAMHOLEBASE31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2854_STRUCT; + +// **** GMMx285C Register Definition **** +// Address +#define GMMx285C_ADDRESS 0x285c + +// Type +#define GMMx285C_TYPE TYPE_GMM +// Field Data +#define GMMx285C_INTLVRGNSWAPEN_OFFSET 0 +#define GMMx285C_INTLVRGNSWAPEN_WIDTH 1 +#define GMMx285C_INTLVRGNSWAPEN_MASK 0x1 +#define GMMx285C_Reserved_OFFSET 1 +#define GMMx285C_Reserved_WIDTH 2 +#define GMMx285C_Reserved_MASK 0x6 +#define GMMx285C_INTLVRGNBASEADDR33_27_OFFSET 3 +#define GMMx285C_INTLVRGNBASEADDR33_27_WIDTH 7 +#define GMMx285C_INTLVRGNBASEADDR33_27_MASK 0x3f8 +#define GMMx285C_Reserved10_10_OFFSET 10 +#define GMMx285C_Reserved10_10_WIDTH 1 +#define GMMx285C_Reserved10_10_MASK 0x400 +#define GMMx285C_INTLVRGNLMTADDR33_27_OFFSET 11 +#define GMMx285C_INTLVRGNLMTADDR33_27_WIDTH 7 +#define GMMx285C_INTLVRGNLMTADDR33_27_MASK 0x3f800 +#define GMMx285C_Reserved18_19_OFFSET 18 +#define GMMx285C_Reserved18_19_WIDTH 2 +#define GMMx285C_Reserved18_19_MASK 0xc0000 +#define GMMx285C_INTLVRGNSIZE33_27_OFFSET 20 +#define GMMx285C_INTLVRGNSIZE33_27_WIDTH 7 +#define GMMx285C_INTLVRGNSIZE33_27_MASK 0x7f00000 +#define GMMx285C_Reserved27_31_OFFSET 27 +#define GMMx285C_Reserved27_31_WIDTH 5 +#define GMMx285C_Reserved27_31_MASK 0xf8000000 + +/// GMMx285C +typedef union { + struct { ///< + UINT32 INTLVRGNSWAPEN:1 ; ///< + UINT32 Reserved:2 ; ///< + UINT32 INTLVRGNBASEADDR33_27:7 ; ///< + UINT32 Reserved10_10:1 ; ///< + UINT32 INTLVRGNLMTADDR33_27:7 ; ///< + UINT32 Reserved18_19:2 ; ///< + UINT32 INTLVRGNSIZE33_27:7 ; ///< + UINT32 Reserved27_31:5 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx285C_STRUCT; + +typedef union { + struct { ///< + UINT32 BASE:20; ///< + UINT32 Reserved:12; ///< + } Field; ///< + UINT32 Value; ///< +} ex1064_STRUCT; + +typedef union { + struct { ///< + UINT32 TOP:20; ///< + UINT32 Reserved:12; ///< + } Field; ///< + UINT32 Value; ///< +} ex1065_STRUCT; + +// **** GMMx2870 Register Definition **** +// Address +#define GMMx2870_ADDRESS 0x2870 + +// Type +#define GMMx2870_TYPE TYPE_GMM +// Field Data +#define GMMx2870_BASE_OFFSET 0 +#define GMMx2870_BASE_WIDTH 20 +#define GMMx2870_BASE_MASK 0xfffff +#define GMMx2870_Reserved_OFFSET 20 +#define GMMx2870_Reserved_WIDTH 12 +#define GMMx2870_Reserved_MASK 0xfff00000 + +/// GMMx2870 +typedef union { + struct { ///< + UINT32 BASE:20; ///< + UINT32 Reserved:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2870_STRUCT; + +// **** GMMx2874 Register Definition **** +// Address +#define GMMx2874_ADDRESS 0x2874 + +// Type +#define GMMx2874_TYPE TYPE_GMM +// Field Data +#define GMMx2874_TOP_OFFSET 0 +#define GMMx2874_TOP_WIDTH 20 +#define GMMx2874_TOP_MASK 0xfffff +#define GMMx2874_Reserved_OFFSET 20 +#define GMMx2874_Reserved_WIDTH 12 +#define GMMx2874_Reserved_MASK 0xfff00000 + +/// GMMx2874 +typedef union { + struct { ///< + UINT32 TOP:20; ///< + UINT32 Reserved:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2874_STRUCT; + + +// **** GMMx287C Register Definition **** +// Address +#define GMMx287C_ADDRESS 0x287c + +// Type +#define GMMx287C_TYPE TYPE_GMM +// Field Data +#define GMMx287C_DEF_OFFSET 0 +#define GMMx287C_DEF_WIDTH 28 +#define GMMx287C_DEF_MASK 0xfffffff +#define GMMx287C_Reserved_OFFSET 28 +#define GMMx287C_Reserved_WIDTH 4 +#define GMMx287C_Reserved_MASK 0xf0000000 + +/// GMMx287C +typedef union { + struct { ///< + UINT32 DEF:28; ///< + UINT32 Reserved:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx287C_STRUCT; + +// **** GMMx2888 Register Definition **** +// Address +#define GMMx2888_ADDRESS 0x2888 + +// Type +#define GMMx2888_TYPE TYPE_GMM +// Field Data +#define GMMx2888_NO_XBAR_OFFSET 0 +#define GMMx2888_NO_XBAR_WIDTH 1 +#define GMMx2888_NO_XBAR_MASK 0x1 +#define GMMx2888_XBAR_UVD_HP_RD_OFFSET 1 +#define GMMx2888_XBAR_UVD_HP_RD_WIDTH 1 +#define GMMx2888_XBAR_UVD_HP_RD_MASK 0x2 +#define GMMx2888_XBAR_UMC_HP_RD_OFFSET 2 +#define GMMx2888_XBAR_UMC_HP_RD_WIDTH 1 +#define GMMx2888_XBAR_UMC_HP_RD_MASK 0x4 +#define GMMx2888_XBAR_VCE_HP_RD_OFFSET 3 +#define GMMx2888_XBAR_VCE_HP_RD_WIDTH 1 +#define GMMx2888_XBAR_VCE_HP_RD_MASK 0x8 +#define GMMx2888_XBAR_VCEU_HP_RD_OFFSET 4 +#define GMMx2888_XBAR_VCEU_HP_RD_WIDTH 1 +#define GMMx2888_XBAR_VCEU_HP_RD_MASK 0x10 +#define GMMx2888_XBAR_VMC_HP_RD_OFFSET 5 +#define GMMx2888_XBAR_VMC_HP_RD_WIDTH 1 +#define GMMx2888_XBAR_VMC_HP_RD_MASK 0x20 +#define GMMx2888_XBAR_DMIF_HP_RD_OFFSET 6 +#define GMMx2888_XBAR_DMIF_HP_RD_WIDTH 1 +#define GMMx2888_XBAR_DMIF_HP_RD_MASK 0x40 +#define GMMx2888_XBAR_UVD_HP_WR_OFFSET 7 +#define GMMx2888_XBAR_UVD_HP_WR_WIDTH 1 +#define GMMx2888_XBAR_UVD_HP_WR_MASK 0x80 +#define GMMx2888_XBAR_UMC_HP_WR_OFFSET 8 +#define GMMx2888_XBAR_UMC_HP_WR_WIDTH 1 +#define GMMx2888_XBAR_UMC_HP_WR_MASK 0x100 +#define GMMx2888_XBAR_VCE_HP_WR_OFFSET 9 +#define GMMx2888_XBAR_VCE_HP_WR_WIDTH 1 +#define GMMx2888_XBAR_VCE_HP_WR_MASK 0x200 +#define GMMx2888_XBAR_VCEU_HP_WR_OFFSET 10 +#define GMMx2888_XBAR_VCEU_HP_WR_WIDTH 1 +#define GMMx2888_XBAR_VCEU_HP_WR_MASK 0x400 +#define GMMx2888_Reserved_OFFSET 11 +#define GMMx2888_Reserved_WIDTH 21 +#define GMMx2888_Reserved_MASK 0xfffff800 + +/// GMMx2888 +typedef union { + struct { ///< + UINT32 NO_XBAR:1 ; ///< + UINT32 XBAR_UVD_HP_RD:1 ; ///< + UINT32 XBAR_UMC_HP_RD:1 ; ///< + UINT32 XBAR_VCE_HP_RD:1 ; ///< + UINT32 XBAR_VCEU_HP_RD:1 ; ///< + UINT32 XBAR_VMC_HP_RD:1 ; ///< + UINT32 XBAR_DMIF_HP_RD:1 ; ///< + UINT32 XBAR_UVD_HP_WR:1 ; ///< + UINT32 XBAR_UMC_HP_WR:1 ; ///< + UINT32 XBAR_VCE_HP_WR:1 ; ///< + UINT32 XBAR_VCEU_HP_WR:1 ; ///< + UINT32 Reserved:21; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2888_STRUCT; + + +// **** GMMx28D4 Register Definition **** +// Address +#define GMMx28D4_ADDRESS 0x28d4 + +// Type +#define GMMx28D4_TYPE TYPE_GMM +// Field Data +#define GMMx28D4_RENG_EXECUTE_ON_PWR_UP_OFFSET 0 +#define GMMx28D4_RENG_EXECUTE_ON_PWR_UP_WIDTH 1 +#define GMMx28D4_RENG_EXECUTE_ON_PWR_UP_MASK 0x1 +#define GMMx28D4_RENG_EXECUTE_NOW_OFFSET 1 +#define GMMx28D4_RENG_EXECUTE_NOW_WIDTH 1 +#define GMMx28D4_RENG_EXECUTE_NOW_MASK 0x2 +#define GMMx28D4_RENG_EXECUTE_NOW_START_PTR_OFFSET 2 +#define GMMx28D4_RENG_EXECUTE_NOW_START_PTR_WIDTH 10 +#define GMMx28D4_RENG_EXECUTE_NOW_START_PTR_MASK 0xffc +#define GMMx28D4_RENG_EXECUTE_DSP_END_PTR_OFFSET 12 +#define GMMx28D4_RENG_EXECUTE_DSP_END_PTR_WIDTH 10 +#define GMMx28D4_RENG_EXECUTE_DSP_END_PTR_MASK 0x3ff000 +#define GMMx28D4_RENG_EXECUTE_END_PTR_OFFSET 22 +#define GMMx28D4_RENG_EXECUTE_END_PTR_WIDTH 10 +#define GMMx28D4_RENG_EXECUTE_END_PTR_MASK 0xffc00000 + +/// GMMx28D4 +typedef union { + struct { ///< + UINT32 RENG_EXECUTE_ON_PWR_UP:1 ; ///< + UINT32 RENG_EXECUTE_NOW:1 ; ///< + UINT32 RENG_EXECUTE_NOW_START_PTR:10; ///< + UINT32 RENG_EXECUTE_DSP_END_PTR:10; ///< + UINT32 RENG_EXECUTE_END_PTR:10; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx28D4_STRUCT; + +// **** GMMx28D8 Register Definition **** +// Address +#define GMMx28D8_ADDRESS 0x28d8 + +// Type +#define GMMx28D8_TYPE TYPE_GMM +// Field Data +#define GMMx28D8_RENG_EXECUTE_NONSECURE_START_PTR_OFFSET 0 +#define GMMx28D8_RENG_EXECUTE_NONSECURE_START_PTR_WIDTH 10 +#define GMMx28D8_RENG_EXECUTE_NONSECURE_START_PTR_MASK 0x3ff +#define GMMx28D8_RENG_EXECUTE_NOW_MODE_OFFSET 10 +#define GMMx28D8_RENG_EXECUTE_NOW_MODE_WIDTH 1 +#define GMMx28D8_RENG_EXECUTE_NOW_MODE_MASK 0x400 +#define GMMx28D8_RENG_EXECUTE_ON_REG_UPDATE_OFFSET 11 +#define GMMx28D8_RENG_EXECUTE_ON_REG_UPDATE_WIDTH 1 +#define GMMx28D8_RENG_EXECUTE_ON_REG_UPDATE_MASK 0x800 +#define GMMx28D8_RENG_SRBM_CREDITS_MCD_OFFSET 12 +#define GMMx28D8_RENG_SRBM_CREDITS_MCD_WIDTH 4 +#define GMMx28D8_RENG_SRBM_CREDITS_MCD_MASK 0xf000 +#define GMMx28D8_STCTRL_STUTTER_EN_OFFSET 16 +#define GMMx28D8_STCTRL_STUTTER_EN_WIDTH 1 +#define GMMx28D8_STCTRL_STUTTER_EN_MASK 0x10000 +#define GMMx28D8_STCTRL_GMC_IDLE_THRESHOLD_OFFSET 17 +#define GMMx28D8_STCTRL_GMC_IDLE_THRESHOLD_WIDTH 2 +#define GMMx28D8_STCTRL_GMC_IDLE_THRESHOLD_MASK 0x60000 +#define GMMx28D8_STCTRL_SRBM_IDLE_THRESHOLD_OFFSET 19 +#define GMMx28D8_STCTRL_SRBM_IDLE_THRESHOLD_WIDTH 2 +#define GMMx28D8_STCTRL_SRBM_IDLE_THRESHOLD_MASK 0x180000 +#define GMMx28D8_STCTRL_IGNORE_PRE_SR_OFFSET 21 +#define GMMx28D8_STCTRL_IGNORE_PRE_SR_WIDTH 1 +#define GMMx28D8_STCTRL_IGNORE_PRE_SR_MASK 0x200000 +#define GMMx28D8_STCTRL_IGNORE_ALLOW_STOP_OFFSET 22 +#define GMMx28D8_STCTRL_IGNORE_ALLOW_STOP_WIDTH 1 +#define GMMx28D8_STCTRL_IGNORE_ALLOW_STOP_MASK 0x400000 +#define GMMx28D8_STCTRL_IGNORE_SR_COMMIT_OFFSET 23 +#define GMMx28D8_STCTRL_IGNORE_SR_COMMIT_WIDTH 1 +#define GMMx28D8_STCTRL_IGNORE_SR_COMMIT_MASK 0x800000 +#define GMMx28D8_STCTRL_IGNORE_PROTECTION_FAULT_OFFSET 24 +#define GMMx28D8_STCTRL_IGNORE_PROTECTION_FAULT_WIDTH 1 +#define GMMx28D8_STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x1000000 +#define GMMx28D8_STCTRL_DISABLE_ALLOW_SR_OFFSET 25 +#define GMMx28D8_STCTRL_DISABLE_ALLOW_SR_WIDTH 1 +#define GMMx28D8_STCTRL_DISABLE_ALLOW_SR_MASK 0x2000000 +#define GMMx28D8_STCTRL_DISABLE_GMC_OFFLINE_OFFSET 26 +#define GMMx28D8_STCTRL_DISABLE_GMC_OFFLINE_WIDTH 1 +#define GMMx28D8_STCTRL_DISABLE_GMC_OFFLINE_MASK 0x4000000 +#define GMMx28D8_CRITICAL_REGS_LOCK_OFFSET 27 +#define GMMx28D8_CRITICAL_REGS_LOCK_WIDTH 1 +#define GMMx28D8_CRITICAL_REGS_LOCK_MASK 0x8000000 +#define GMMx28D8_ALLOW_DEEP_SLEEP_MODE_OFFSET 28 +#define GMMx28D8_ALLOW_DEEP_SLEEP_MODE_WIDTH 2 +#define GMMx28D8_ALLOW_DEEP_SLEEP_MODE_MASK 0x30000000 +#define GMMx28D8_STCTRL_FORCE_ALLOW_SR_OFFSET 30 +#define GMMx28D8_STCTRL_FORCE_ALLOW_SR_WIDTH 1 +#define GMMx28D8_STCTRL_FORCE_ALLOW_SR_MASK 0x40000000 +#define GMMx28D8_Reserved_OFFSET 31 +#define GMMx28D8_Reserved_WIDTH 1 +#define GMMx28D8_Reserved_MASK 0x80000000 + +/// GMMx28D8 +typedef union { + struct { ///< + UINT32 RENG_EXECUTE_NONSECURE_START_PTR:10; ///< + UINT32 RENG_EXECUTE_NOW_MODE:1 ; ///< + UINT32 RENG_EXECUTE_ON_REG_UPDATE:1 ; ///< + UINT32 RENG_SRBM_CREDITS_MCD:4 ; ///< + UINT32 STCTRL_STUTTER_EN:1 ; ///< + UINT32 STCTRL_GMC_IDLE_THRESHOLD:2 ; ///< + UINT32 STCTRL_SRBM_IDLE_THRESHOLD:2 ; ///< + UINT32 STCTRL_IGNORE_PRE_SR:1 ; ///< + UINT32 STCTRL_IGNORE_ALLOW_STOP:1 ; ///< + UINT32 STCTRL_IGNORE_SR_COMMIT:1 ; ///< + UINT32 STCTRL_IGNORE_PROTECTION_FAULT:1 ; ///< + UINT32 STCTRL_DISABLE_ALLOW_SR:1 ; ///< + UINT32 STCTRL_DISABLE_GMC_OFFLINE:1 ; ///< + UINT32 CRITICAL_REGS_LOCK:1 ; ///< + UINT32 ALLOW_DEEP_SLEEP_MODE:2 ; ///< + UINT32 STCTRL_FORCE_ALLOW_SR:1 ; ///< + UINT32 Reserved:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx28D8_STRUCT; + +// **** GMMx2C04 Register Definition **** +// Address +#define GMMx2C04_ADDRESS 0x2c04 + +// Type +#define GMMx2C04_TYPE TYPE_GMM +// Field Data +#define GMMx2C04_NONSURF_BASE_OFFSET 0 +#define GMMx2C04_NONSURF_BASE_WIDTH 32 +#define GMMx2C04_NONSURF_BASE_MASK 0xffffffff + +/// GMMx2C04 +typedef union { + struct { ///< + UINT32 NONSURF_BASE:32; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2C04_STRUCT; + +// **** GMMx5428 Register Definition **** +// Address +#define GMMx5428_ADDRESS 0x5428 + +// Type +#define GMMx5428_TYPE TYPE_GMM +// Field Data +#define GMMx5428_CONFIG_MEMSIZE_OFFSET 0 +#define GMMx5428_CONFIG_MEMSIZE_WIDTH 32 +#define GMMx5428_CONFIG_MEMSIZE_MASK 0xffffffff + +/// GMMx5428 +typedef union { + struct { ///< + UINT32 CONFIG_MEMSIZE:32; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx5428_STRUCT; + +// **** GMMx5490 Register Definition **** +// Address +#define GMMx5490_ADDRESS 0x5490 + +// Type +#define GMMx5490_TYPE TYPE_GMM +// Field Data +#define GMMx5490_FB_READ_EN_OFFSET 0 +#define GMMx5490_FB_READ_EN_WIDTH 1 +#define GMMx5490_FB_READ_EN_MASK 0x1 +#define GMMx5490_FB_WRITE_EN_OFFSET 1 +#define GMMx5490_FB_WRITE_EN_WIDTH 1 +#define GMMx5490_FB_WRITE_EN_MASK 0x2 +#define GMMx5490_Reserved_OFFSET 2 +#define GMMx5490_Reserved_WIDTH 30 +#define GMMx5490_Reserved_MASK 0xfffffffc + +/// GMMx5490 +typedef union { + struct { ///< + UINT32 FB_READ_EN:1 ; ///< + UINT32 FB_WRITE_EN:1 ; ///< + UINT32 Reserved:30; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx5490_STRUCT; + +// **** MSRC001_0010 Register Definition **** +// Address +#define MSRC001_0010_ADDRESS 0xc0010010 + +// Type +#define MSRC001_0010_TYPE TYPE_MSR +// Field Data +#define MSRC001_0010_Reserved_15_0_OFFSET 0 +#define MSRC001_0010_Reserved_15_0_WIDTH 16 +#define MSRC001_0010_Reserved_15_0_MASK 0xffff +#define MSRC001_0010_ChgToDirtyDis_OFFSET 16 +#define MSRC001_0010_ChgToDirtyDis_WIDTH 1 +#define MSRC001_0010_ChgToDirtyDis_MASK 0x10000 +#define MSRC001_0010_Reserved_17_17_OFFSET 17 +#define MSRC001_0010_Reserved_17_17_WIDTH 1 +#define MSRC001_0010_Reserved_17_17_MASK 0x20000 +#define MSRC001_0010_MtrrFixDramEn_OFFSET 18 +#define MSRC001_0010_MtrrFixDramEn_WIDTH 1 +#define MSRC001_0010_MtrrFixDramEn_MASK 0x40000 +#define MSRC001_0010_MtrrFixDramModEn_OFFSET 19 +#define MSRC001_0010_MtrrFixDramModEn_WIDTH 1 +#define MSRC001_0010_MtrrFixDramModEn_MASK 0x80000 +#define MSRC001_0010_MtrrVarDramEn_OFFSET 20 +#define MSRC001_0010_MtrrVarDramEn_WIDTH 1 +#define MSRC001_0010_MtrrVarDramEn_MASK 0x100000 +#define MSRC001_0010_MtrrTom2En_OFFSET 21 +#define MSRC001_0010_MtrrTom2En_WIDTH 1 +#define MSRC001_0010_MtrrTom2En_MASK 0x200000 +#define MSRC001_0010_Tom2ForceMemTypeWB_OFFSET 22 +#define MSRC001_0010_Tom2ForceMemTypeWB_WIDTH 1 +#define MSRC001_0010_Tom2ForceMemTypeWB_MASK 0x400000 +#define MSRC001_0010_Reserved_63_23_OFFSET 23 +#define MSRC001_0010_Reserved_63_23_WIDTH 41 +#define MSRC001_0010_Reserved_63_23_MASK 0xffffffffff800000 + +/// MSRC001_0010 +typedef union { + struct { ///< + UINT64 Reserved_15_0:16; ///< + UINT64 ChgToDirtyDis:1 ; ///< + UINT64 Reserved_17_17:1 ; ///< + UINT64 MtrrFixDramEn:1 ; ///< + UINT64 MtrrFixDramModEn:1 ; ///< + UINT64 MtrrVarDramEn:1 ; ///< + UINT64 MtrrTom2En:1 ; ///< + UINT64 Tom2ForceMemTypeWB:1 ; ///< + UINT64 Reserved_63_23:41; ///< + } Field; ///< + UINT64 Value; ///< +} MSRC001_0010_STRUCT; + +// **** MSRC001_001A Register Definition **** +// Address +#define MSRC001_001A_ADDRESS 0xc001001a + +// Type +#define MSRC001_001A_TYPE TYPE_MSR +// Field Data +#define MSRC001_001A_RAZ_22_0_OFFSET 0 +#define MSRC001_001A_RAZ_22_0_WIDTH 23 +#define MSRC001_001A_RAZ_22_0_MASK 0x7fffff +#define MSRC001_001A_TOM_47_23__OFFSET 23 +#define MSRC001_001A_TOM_47_23__WIDTH 25 +#define MSRC001_001A_TOM_47_23__MASK 0xffffff800000 +#define MSRC001_001A_RAZ_63_48_OFFSET 48 +#define MSRC001_001A_RAZ_63_48_WIDTH 16 +#define MSRC001_001A_RAZ_63_48_MASK 0xffff000000000000 + +/// MSRC001_001A +typedef union { + struct { ///< + UINT64 RAZ_22_0:23; ///< + UINT64 TOM_47_23_:25; ///< + UINT64 RAZ_63_48:16; ///< + } Field; ///< + UINT64 Value; ///< +} MSRC001_001A_STRUCT; + +// **** MSRC001_001D Register Definition **** +// Address +#define MSRC001_001D_ADDRESS 0xc001001d + +// Type +#define MSRC001_001D_TYPE TYPE_MSR +// Field Data +#define MSRC001_001D_RAZ_22_0_OFFSET 0 +#define MSRC001_001D_RAZ_22_0_WIDTH 23 +#define MSRC001_001D_RAZ_22_0_MASK 0x7fffff +#define MSRC001_001D_TOM2_47_23__OFFSET 23 +#define MSRC001_001D_TOM2_47_23__WIDTH 25 +#define MSRC001_001D_TOM2_47_23__MASK 0xffffff800000 +#define MSRC001_001D_RAZ_63_48_OFFSET 48 +#define MSRC001_001D_RAZ_63_48_WIDTH 16 +#define MSRC001_001D_RAZ_63_48_MASK 0xffff000000000000 + +/// MSRC001_001D +typedef union { + struct { ///< + UINT64 RAZ_22_0:23; ///< + UINT64 TOM2_47_23_:25; ///< + UINT64 RAZ_63_48:16; ///< + } Field; ///< + UINT64 Value; ///< +} MSRC001_001D_STRUCT; + +// **** D0F0xBC_xE01040A8 Field Definition **** +// Address +#define D0F0xBC_xE01040A8_ADDRESS 0xe01040a8 + +// Type +#define D0F0xBC_xE01040A8_TYPE TYPE_D0F0xBC +#define D0F0xBC_xE01040A8_Reserved0_14_OFFSET 0 +#define D0F0xBC_xE01040A8_Reserved0_14_WIDTH 15 +#define D0F0xBC_xE01040A8_Reserved0_14_MASK 0x7fff +#define D0F0xBC_xE01040A8_SviLoadLineVdd_OFFSET 15 +#define D0F0xBC_xE01040A8_SviLoadLineVdd_WIDTH 7 +#define D0F0xBC_xE01040A8_SviLoadLineVdd_MASK 0x3f8000 +#define D0F0xBC_xE01040A8_SviLoadLineVddNb_OFFSET 22 +#define D0F0xBC_xE01040A8_SviLoadLineVddNb_WIDTH 7 +#define D0F0xBC_xE01040A8_SviLoadLineVddNb_MASK 0x1fc00000 +#define D0F0xBC_xE01040A8_Reserved29_31_OFFSET 29 +#define D0F0xBC_xE01040A8_Reserved29_31_WIDTH 3 +#define D0F0xBC_xE01040A8_Reserved29_31_MASK 0xe0000000 + +/// D0F0xBC_xE01040A8 +typedef union { + struct { ///< + UINT32 Reserved0_14:15; ///< + UINT32 SviLoadLineVdd:7 ; ///< + UINT32 SviLoadLineVddNb:7 ; ///< + UINT32 Reserved29_31:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE01040A8_STRUCT; + +// **** D0F0xBC_xE0104158 Field Definition **** +// Address +#define D0F0xBC_xE0104158_ADDRESS 0xe0104158 + +// Type +#define D0F0xBC_xE0104158_TYPE TYPE_D0F0xBC +#define D0F0xBC_xE0104158_Reserved0_9_OFFSET 0 +#define D0F0xBC_xE0104158_Reserved0_9_WIDTH 10 +#define D0F0xBC_xE0104158_Reserved0_9_MASK 0x3ff +#define D0F0xBC_xE0104158_EClkDid0_OFFSET 10 +#define D0F0xBC_xE0104158_EClkDid0_WIDTH 7 +#define D0F0xBC_xE0104158_EClkDid0_MASK 0x1fc00 +#define D0F0xBC_xE0104158_EClkDid1_OFFSET 17 +#define D0F0xBC_xE0104158_EClkDid1_WIDTH 7 +#define D0F0xBC_xE0104158_EClkDid1_MASK 0xfe0000 +#define D0F0xBC_xE0104158_EClkDid2_OFFSET 24 +#define D0F0xBC_xE0104158_EClkDid2_WIDTH 7 +#define D0F0xBC_xE0104158_EClkDid2_MASK 0x7f000000 +#define D0F0xBC_xE0104158_Reserved31_31_OFFSET 31 +#define D0F0xBC_xE0104158_Reserved31_31_WIDTH 1 +#define D0F0xBC_xE0104158_Reserved31_31_MASK 0x80000000 + +/// D0F0xBC_xE0104158 +typedef union { + struct { ///< + UINT32 Reserved0_9:10; ///< + UINT32 EClkDid0:7 ; ///< + UINT32 EClkDid1:7 ; ///< + UINT32 EClkDid2:7 ; ///< + UINT32 Reserved31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0104158_STRUCT; + +// **** D0F0xBC_xE010415B Field Definition **** +// Address +#define D0F0xBC_xE010415B_ADDRESS 0xe010415b + +// Type +#define D0F0xBC_xE010415B_TYPE TYPE_D0F0xBC +#define D0F0xBC_xE010415B_Reserved0_6_OFFSET 0 +#define D0F0xBC_xE010415B_Reserved0_6_WIDTH 7 +#define D0F0xBC_xE010415B_Reserved0_6_MASK 0x7f +#define D0F0xBC_xE010415B_EClkDid3_OFFSET 7 +#define D0F0xBC_xE010415B_EClkDid3_WIDTH 7 +#define D0F0xBC_xE010415B_EClkDid3_MASK 0x3f80 +#define D0F0xBC_xE010415B_Reserved14_31_OFFSET 14 +#define D0F0xBC_xE010415B_Reserved14_31_WIDTH 18 +#define D0F0xBC_xE010415B_Reserved14_31_MASK 0xffffc000 + +/// D0F0xBC_xE010415B +typedef union { + struct { ///< + UINT32 Reserved0_6:7 ; ///< + UINT32 EClkDid3:7 ; ///< + UINT32 Reserved14_31:18; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE010415B_STRUCT; + +// **** D0F0xBC_xE0104184 Field Definition **** +// Address +#define D0F0xBC_xE0104184_ADDRESS 0xe0104184 + +// Type +#define D0F0xBC_xE0104184_TYPE TYPE_D0F0xBC +#define D0F0xBC_xE0104184_SviLoadLineTrimVdd_OFFSET 0 +#define D0F0xBC_xE0104184_SviLoadLineTrimVdd_WIDTH 3 +#define D0F0xBC_xE0104184_SviLoadLineTrimVdd_MASK 0x7 +#define D0F0xBC_xE0104184_SviLoadLineTrimVddNb_OFFSET 3 +#define D0F0xBC_xE0104184_SviLoadLineTrimVddNb_WIDTH 3 +#define D0F0xBC_xE0104184_SviLoadLineTrimVddNb_MASK 0x38 +#define D0F0xBC_xE0104184_SviLoadLineOffsetVdd_OFFSET 6 +#define D0F0xBC_xE0104184_SviLoadLineOffsetVdd_WIDTH 2 +#define D0F0xBC_xE0104184_SviLoadLineOffsetVdd_MASK 0xc0 +#define D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_OFFSET 8 +#define D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_WIDTH 2 +#define D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_MASK 0x300 +#define D0F0xBC_xE0104184_VCEFlag0_OFFSET 10 +#define D0F0xBC_xE0104184_VCEFlag0_WIDTH 8 +#define D0F0xBC_xE0104184_VCEFlag0_MASK 0x3fc00 +#define D0F0xBC_xE0104184_VCEFlag1_OFFSET 18 +#define D0F0xBC_xE0104184_VCEFlag1_WIDTH 8 +#define D0F0xBC_xE0104184_VCEFlag1_MASK 0x3fc0000 +#define D0F0xBC_xE0104184_Reserved26_31_OFFSET 26 +#define D0F0xBC_xE0104184_Reserved26_31_WIDTH 6 +#define D0F0xBC_xE0104184_Reserved26_31_MASK 0xfc000000 + +/// D0F0xBC_xE0104184 +typedef union { + struct { ///< + UINT32 SviLoadLineTrimVdd:3 ; ///< + UINT32 SviLoadLineTrimVddNb:3 ; ///< + UINT32 SviLoadLineOffsetVdd:2 ; ///< + UINT32 SviLoadLineOffsetVddNb:2 ; ///< + UINT32 VCEFlag0:8 ; ///< + UINT32 VCEFlag1:8 ; ///< + UINT32 Reserved26_31:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0104184_STRUCT; + +// **** D0F0xBC_xE0104187 Field Definition **** +// Address +#define D0F0xBC_xE0104187_ADDRESS 0xe0104187 + +// Type +#define D0F0xBC_xE0104187_TYPE TYPE_D0F0xBC +#define D0F0xBC_xE0104187_Reserved0_1_OFFSET 0 +#define D0F0xBC_xE0104187_Reserved0_1_WIDTH 2 +#define D0F0xBC_xE0104187_Reserved0_1_MASK 0x3 +#define D0F0xBC_xE0104187_VCEFlag2_OFFSET 2 +#define D0F0xBC_xE0104187_VCEFlag2_WIDTH 8 +#define D0F0xBC_xE0104187_VCEFlag2_MASK 0x3fc +#define D0F0xBC_xE0104187_Reserved10_31_OFFSET 10 +#define D0F0xBC_xE0104187_Reserved10_31_WIDTH 22 +#define D0F0xBC_xE0104187_Reserved10_31_MASK 0xfffffc00 + +/// D0F0xBC_xE0104187 +typedef union { + struct { ///< + UINT32 Reserved0_1:2 ; ///< + UINT32 VCEFlag2:8 ; ///< + UINT32 Reserved10_31:22; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0104187_STRUCT; + +// **** D0F0xBC_xE0104188 Field Definition **** +// Address +#define D0F0xBC_xE0104188_ADDRESS 0xe0104188 + +// Type +#define D0F0xBC_xE0104188_TYPE TYPE_D0F0xBC +#define D0F0xBC_xE0104188_Reserved0_1_OFFSET 0 +#define D0F0xBC_xE0104188_Reserved0_1_WIDTH 2 +#define D0F0xBC_xE0104188_Reserved0_1_MASK 0x3 +#define D0F0xBC_xE0104188_VCEFlag3_OFFSET 2 +#define D0F0xBC_xE0104188_VCEFlag3_WIDTH 8 +#define D0F0xBC_xE0104188_VCEFlag3_MASK 0x3fc +#define D0F0xBC_xE0104188_ReqSclkSel0_OFFSET 10 +#define D0F0xBC_xE0104188_ReqSclkSel0_WIDTH 3 +#define D0F0xBC_xE0104188_ReqSclkSel0_MASK 0x1c00 +#define D0F0xBC_xE0104188_ReqSclkSel1_OFFSET 13 +#define D0F0xBC_xE0104188_ReqSclkSel1_WIDTH 3 +#define D0F0xBC_xE0104188_ReqSclkSel1_MASK 0xe000 +#define D0F0xBC_xE0104188_ReqSclkSel2_OFFSET 16 +#define D0F0xBC_xE0104188_ReqSclkSel2_WIDTH 3 +#define D0F0xBC_xE0104188_ReqSclkSel2_MASK 0x70000 +#define D0F0xBC_xE0104188_ReqSclkSel3_OFFSET 19 +#define D0F0xBC_xE0104188_ReqSclkSel3_WIDTH 3 +#define D0F0xBC_xE0104188_ReqSclkSel3_MASK 0x380000 +#define D0F0xBC_xE0104188_VCEMclk_OFFSET 22 +#define D0F0xBC_xE0104188_VCEMclk_WIDTH 4 +#define D0F0xBC_xE0104188_VCEMclk_MASK 0x3c00000 +#define D0F0xBC_xE0104188_LhtcPstateLimit_OFFSET 26 +#define D0F0xBC_xE0104188_LhtcPstateLimit_WIDTH 3 +#define D0F0xBC_xE0104188_LhtcPstateLimit_MASK 0x1c000000 +#define D0F0xBC_xE0104188_BapmMeasuredTemp_OFFSET 29 +#define D0F0xBC_xE0104188_BapmMeasuredTemp_WIDTH 1 +#define D0F0xBC_xE0104188_BapmMeasuredTemp_MASK 0x20000000 +#define D0F0xBC_xE0104188_BapmDisable_OFFSET 30 +#define D0F0xBC_xE0104188_BapmDisable_WIDTH 1 +#define D0F0xBC_xE0104188_BapmDisable_MASK 0x40000000 +#define D0F0xBC_xE0104188_Reserved31_31_OFFSET 31 +#define D0F0xBC_xE0104188_Reserved31_31_WIDTH 1 +#define D0F0xBC_xE0104188_Reserved31_31_MASK 0x80000000 + +/// D0F0xBC_xE0104188 +typedef union { + struct { ///< + UINT32 Reserved0_1:2 ; ///< + UINT32 VCEFlag3:8 ; ///< + UINT32 ReqSclkSel0:3 ; ///< + UINT32 ReqSclkSel1:3 ; ///< + UINT32 ReqSclkSel2:3 ; ///< + UINT32 ReqSclkSel3:3 ; ///< + UINT32 VCEMclk:4 ; ///< + UINT32 LhtcPstateLimit:3 ; ///< + UINT32 BapmMeasuredTemp:1 ; ///< + UINT32 BapmDisable:1 ; ///< + UINT32 Reserved31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0104188_STRUCT; + +// **** D0F0xBC_xE0106020 Field Definition **** +// Address +#define D0F0xBC_xE0106020_ADDRESS 0xe0106020 + +// Type +#define D0F0xBC_xE0106020_TYPE TYPE_D0F0xBC +#define D0F0xBC_xE0106020_Reserved0_24_OFFSET 0 +#define D0F0xBC_xE0106020_Reserved0_24_WIDTH 25 +#define D0F0xBC_xE0106020_Reserved0_24_MASK 0x1ffffff +#define D0F0xBC_xE0106020_PowerplayDClkVClkSel0_OFFSET 25 +#define D0F0xBC_xE0106020_PowerplayDClkVClkSel0_WIDTH 2 +#define D0F0xBC_xE0106020_PowerplayDClkVClkSel0_MASK 0x6000000 +#define D0F0xBC_xE0106020_PowerplayDClkVClkSel1_OFFSET 27 +#define D0F0xBC_xE0106020_PowerplayDClkVClkSel1_WIDTH 2 +#define D0F0xBC_xE0106020_PowerplayDClkVClkSel1_MASK 0x18000000 +#define D0F0xBC_xE0106020_PowerplayDClkVClkSel2_OFFSET 29 +#define D0F0xBC_xE0106020_PowerplayDClkVClkSel2_WIDTH 2 +#define D0F0xBC_xE0106020_PowerplayDClkVClkSel2_MASK 0x60000000 +#define D0F0xBC_xE0106020_Reserved31_31_OFFSET 31 +#define D0F0xBC_xE0106020_Reserved31_31_WIDTH 1 +#define D0F0xBC_xE0106020_Reserved31_31_MASK 0x80000000 + +/// D0F0xBC_xE0106020 +typedef union { + struct { ///< + UINT32 Reserved0_24:25; ///< + UINT32 PowerplayDClkVClkSel0:2 ; ///< + UINT32 PowerplayDClkVClkSel1:2 ; ///< + UINT32 PowerplayDClkVClkSel2:2 ; ///< + UINT32 Reserved31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0106020_STRUCT; + +// **** D0F0xBC_xE0106023 Field Definition **** +// Address +#define D0F0xBC_xE0106023_ADDRESS 0xe0106023 + +// Type +#define D0F0xBC_xE0106023_TYPE TYPE_D0F0xBC +#define D0F0xBC_xE0106023_Reserved0_6_OFFSET 0 +#define D0F0xBC_xE0106023_Reserved0_6_WIDTH 7 +#define D0F0xBC_xE0106023_Reserved0_6_MASK 0x7f +#define D0F0xBC_xE0106023_PowerplayDClkVClkSel3_OFFSET 7 +#define D0F0xBC_xE0106023_PowerplayDClkVClkSel3_WIDTH 2 +#define D0F0xBC_xE0106023_PowerplayDClkVClkSel3_MASK 0x180 +#define D0F0xBC_xE0106023_Reserved9_31_OFFSET 9 +#define D0F0xBC_xE0106023_Reserved9_31_WIDTH 23 +#define D0F0xBC_xE0106023_Reserved9_31_MASK 0xfffffe00 + +/// D0F0xBC_xE0106023 +typedef union { + struct { ///< + UINT32 Reserved0_6:7 ; ///< + UINT32 PowerplayDClkVClkSel3:2 ; ///< + UINT32 Reserved9_31:23; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0106023_STRUCT; + +// **** D0F0xBC_xE0106024 Field Definition **** +// Address +#define D0F0xBC_xE0106024_ADDRESS 0xe0106024 + +// Type +#define D0F0xBC_xE0106024_TYPE TYPE_D0F0xBC +#define D0F0xBC_xE0106024_Reserved0_0_OFFSET 0 +#define D0F0xBC_xE0106024_Reserved0_0_WIDTH 1 +#define D0F0xBC_xE0106024_Reserved0_0_MASK 0x1 +#define D0F0xBC_xE0106024_PowerplayDClkVClkSel4_OFFSET 1 +#define D0F0xBC_xE0106024_PowerplayDClkVClkSel4_WIDTH 2 +#define D0F0xBC_xE0106024_PowerplayDClkVClkSel4_MASK 0x6 +#define D0F0xBC_xE0106024_PowerplayDClkVClkSel5_OFFSET 3 +#define D0F0xBC_xE0106024_PowerplayDClkVClkSel5_WIDTH 2 +#define D0F0xBC_xE0106024_PowerplayDClkVClkSel5_MASK 0x18 +#define D0F0xBC_xE0106024_Reserved5_31_OFFSET 5 +#define D0F0xBC_xE0106024_Reserved5_31_WIDTH 27 +#define D0F0xBC_xE0106024_Reserved5_31_MASK 0xffffffe0 + +/// D0F0xBC_xE0106024 +typedef union { + struct { ///< + UINT32 Reserved0_0:1 ; ///< + UINT32 PowerplayDClkVClkSel4:2 ; ///< + UINT32 PowerplayDClkVClkSel5:2 ; ///< + UINT32 Reserved5_31:27; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0106024_STRUCT; + + +// **** D0F0xBC_xE010705C Field Definition **** +// Address +#define D0F0xBC_xE010705C_ADDRESS 0xe010705c + +// Type +#define D0F0xBC_xE010705C_TYPE TYPE_D0F0xBC +#define D0F0xBC_xE010705C_Reserved0_17_OFFSET 0 +#define D0F0xBC_xE010705C_Reserved0_17_WIDTH 18 +#define D0F0xBC_xE010705C_Reserved0_17_MASK 0x3ffff +#define D0F0xBC_xE010705C_PowerplayTableRev_OFFSET 18 +#define D0F0xBC_xE010705C_PowerplayTableRev_WIDTH 4 +#define D0F0xBC_xE010705C_PowerplayTableRev_MASK 0x3c0000 +#define D0F0xBC_xE010705C_SClkThermDid_OFFSET 22 +#define D0F0xBC_xE010705C_SClkThermDid_WIDTH 7 +#define D0F0xBC_xE010705C_SClkThermDid_MASK 0x1fc00000 +#define D0F0xBC_xE010705C_PcieGen2Vid_OFFSET 29 +#define D0F0xBC_xE010705C_PcieGen2Vid_WIDTH 2 +#define D0F0xBC_xE010705C_PcieGen2Vid_MASK 0x60000000 +#define D0F0xBC_xE010705C_Reserved31_31_OFFSET 31 +#define D0F0xBC_xE010705C_Reserved31_31_WIDTH 1 +#define D0F0xBC_xE010705C_Reserved31_31_MASK 0x80000000 + +/// D0F0xBC_xE010705C +typedef union { + struct { ///< + UINT32 Reserved0_17:18; ///< + UINT32 PowerplayTableRev:4 ; ///< + UINT32 SClkThermDid:7 ; ///< + UINT32 PcieGen2Vid:2 ; ///< + UINT32 Reserved31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE010705C_STRUCT; + +// **** D0F0xBC_xE010705F Field Definition **** +// Address +#define D0F0xBC_xE010705F_ADDRESS 0xe010705f + +// Type +#define D0F0xBC_xE010705F_TYPE TYPE_D0F0xBC +#define D0F0xBC_xE010705F_Reserved0_6_OFFSET 0 +#define D0F0xBC_xE010705F_Reserved0_6_WIDTH 7 +#define D0F0xBC_xE010705F_Reserved0_6_MASK 0x7f +#define D0F0xBC_xE010705F_SClkDpmVid0_OFFSET 7 +#define D0F0xBC_xE010705F_SClkDpmVid0_WIDTH 2 +#define D0F0xBC_xE010705F_SClkDpmVid0_MASK 0x180 +#define D0F0xBC_xE010705F_Reserved9_31_OFFSET 9 +#define D0F0xBC_xE010705F_Reserved9_31_WIDTH 23 +#define D0F0xBC_xE010705F_Reserved9_31_MASK 0xfffffe00 + +/// D0F0xBC_xE010705F +typedef union { + struct { ///< + UINT32 Reserved0_6:7 ; ///< + UINT32 SClkDpmVid0:2 ; ///< + UINT32 Reserved9_31:23; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE010705F_STRUCT; + +// **** D0F0xBC_xE0107060 Field Definition **** +// Address +#define D0F0xBC_xE0107060_ADDRESS 0xe0107060 + +// Type +#define D0F0xBC_xE0107060_TYPE TYPE_D0F0xBC +#define D0F0xBC_xE0107060_Reserved0_0_OFFSET 0 +#define D0F0xBC_xE0107060_Reserved0_0_WIDTH 1 +#define D0F0xBC_xE0107060_Reserved0_0_MASK 0x1 +#define D0F0xBC_xE0107060_SClkDpmVid1_OFFSET 1 +#define D0F0xBC_xE0107060_SClkDpmVid1_WIDTH 2 +#define D0F0xBC_xE0107060_SClkDpmVid1_MASK 0x6 +#define D0F0xBC_xE0107060_SClkDpmVid2_OFFSET 3 +#define D0F0xBC_xE0107060_SClkDpmVid2_WIDTH 2 +#define D0F0xBC_xE0107060_SClkDpmVid2_MASK 0x18 +#define D0F0xBC_xE0107060_SClkDpmVid3_OFFSET 5 +#define D0F0xBC_xE0107060_SClkDpmVid3_WIDTH 2 +#define D0F0xBC_xE0107060_SClkDpmVid3_MASK 0x60 +#define D0F0xBC_xE0107060_SClkDpmVid4_OFFSET 7 +#define D0F0xBC_xE0107060_SClkDpmVid4_WIDTH 2 +#define D0F0xBC_xE0107060_SClkDpmVid4_MASK 0x180 +#define D0F0xBC_xE0107060_SClkDpmDid0_OFFSET 9 +#define D0F0xBC_xE0107060_SClkDpmDid0_WIDTH 7 +#define D0F0xBC_xE0107060_SClkDpmDid0_MASK 0xfe00 +#define D0F0xBC_xE0107060_SClkDpmDid1_OFFSET 16 +#define D0F0xBC_xE0107060_SClkDpmDid1_WIDTH 7 +#define D0F0xBC_xE0107060_SClkDpmDid1_MASK 0x7f0000 +#define D0F0xBC_xE0107060_SClkDpmDid2_OFFSET 23 +#define D0F0xBC_xE0107060_SClkDpmDid2_WIDTH 7 +#define D0F0xBC_xE0107060_SClkDpmDid2_MASK 0x3f800000 +#define D0F0xBC_xE0107060_Reserved30_31_OFFSET 30 +#define D0F0xBC_xE0107060_Reserved30_31_WIDTH 2 +#define D0F0xBC_xE0107060_Reserved30_31_MASK 0xc0000000 + +/// D0F0xBC_xE0107060 +typedef union { + struct { ///< + UINT32 Reserved0_0:1 ; ///< + UINT32 SClkDpmVid1:2 ; ///< + UINT32 SClkDpmVid2:2 ; ///< + UINT32 SClkDpmVid3:2 ; ///< + UINT32 SClkDpmVid4:2 ; ///< + UINT32 SClkDpmDid0:7 ; ///< + UINT32 SClkDpmDid1:7 ; ///< + UINT32 SClkDpmDid2:7 ; ///< + UINT32 Reserved30_31:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0107060_STRUCT; + +// **** D0F0xBC_xE0107063 Field Definition **** +// Address +#define D0F0xBC_xE0107063_ADDRESS 0xe0107063 + +// Type +#define D0F0xBC_xE0107063_TYPE TYPE_D0F0xBC +#define D0F0xBC_xE0107063_Reserved0_5_OFFSET 0 +#define D0F0xBC_xE0107063_Reserved0_5_WIDTH 6 +#define D0F0xBC_xE0107063_Reserved0_5_MASK 0x3f +#define D0F0xBC_xE0107063_SClkDpmDid3_OFFSET 6 +#define D0F0xBC_xE0107063_SClkDpmDid3_WIDTH 7 +#define D0F0xBC_xE0107063_SClkDpmDid3_MASK 0x1fc0 +#define D0F0xBC_xE0107063_Reserved13_31_OFFSET 13 +#define D0F0xBC_xE0107063_Reserved13_31_WIDTH 19 +#define D0F0xBC_xE0107063_Reserved13_31_MASK 0xffffe000 + +/// D0F0xBC_xE0107063 +typedef union { + struct { ///< + UINT32 Reserved0_5:6 ; ///< + UINT32 SClkDpmDid3:7 ; ///< + UINT32 Reserved13_31:19; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0107063_STRUCT; + +// **** D0F0xBC_xE0107064 Field Definition **** +// Address +#define D0F0xBC_xE0107064_ADDRESS 0xe0107064 + +// Type +#define D0F0xBC_xE0107064_TYPE TYPE_D0F0xBC +#define D0F0xBC_xE0107064_Reserved0_4_OFFSET 0 +#define D0F0xBC_xE0107064_Reserved0_4_WIDTH 5 +#define D0F0xBC_xE0107064_Reserved0_4_MASK 0x1f +#define D0F0xBC_xE0107064_SClkDpmDid4_OFFSET 5 +#define D0F0xBC_xE0107064_SClkDpmDid4_WIDTH 7 +#define D0F0xBC_xE0107064_SClkDpmDid4_MASK 0xfe0 +#define D0F0xBC_xE0107064_Reserved12_31_OFFSET 12 +#define D0F0xBC_xE0107064_Reserved12_31_WIDTH 20 +#define D0F0xBC_xE0107064_Reserved12_31_MASK 0xfffff000 + +/// D0F0xBC_xE0107064 +typedef union { + struct { ///< + UINT32 Reserved0_4:5 ; ///< + UINT32 SClkDpmDid4:7 ; ///< + UINT32 Reserved12_31:20; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0107064_STRUCT; + +// **** D0F0xBC_xE0107067 Field Definition **** +// Address +#define D0F0xBC_xE0107067_ADDRESS 0xe0107067 + +// Type +#define D0F0xBC_xE0107067_TYPE TYPE_D0F0xBC +#define D0F0xBC_xE0107067_Reserved0_3_OFFSET 0 +#define D0F0xBC_xE0107067_Reserved0_3_WIDTH 4 +#define D0F0xBC_xE0107067_Reserved0_3_MASK 0xf +#define D0F0xBC_xE0107067_DispClkDid0_OFFSET 4 +#define D0F0xBC_xE0107067_DispClkDid0_WIDTH 7 +#define D0F0xBC_xE0107067_DispClkDid0_MASK 0x7f0 +#define D0F0xBC_xE0107067_Reserved11_31_OFFSET 11 +#define D0F0xBC_xE0107067_Reserved11_31_WIDTH 21 +#define D0F0xBC_xE0107067_Reserved11_31_MASK 0xfffff800 + +/// D0F0xBC_xE0107067 +typedef union { + struct { ///< + UINT32 Reserved0_3:4 ; ///< + UINT32 DispClkDid0:7 ; ///< + UINT32 Reserved11_31:21; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0107067_STRUCT; + +// **** D0F0xBC_xE0107068 Field Definition **** +// Address +#define D0F0xBC_xE0107068_ADDRESS 0xe0107068 + +// Type +#define D0F0xBC_xE0107068_TYPE TYPE_D0F0xBC +#define D0F0xBC_xE0107068_Reserved0_2_OFFSET 0 +#define D0F0xBC_xE0107068_Reserved0_2_WIDTH 3 +#define D0F0xBC_xE0107068_Reserved0_2_MASK 0x7 +#define D0F0xBC_xE0107068_DispClkDid1_OFFSET 3 +#define D0F0xBC_xE0107068_DispClkDid1_WIDTH 7 +#define D0F0xBC_xE0107068_DispClkDid1_MASK 0x3f8 +#define D0F0xBC_xE0107068_DispClkDid2_OFFSET 10 +#define D0F0xBC_xE0107068_DispClkDid2_WIDTH 7 +#define D0F0xBC_xE0107068_DispClkDid2_MASK 0x1fc00 +#define D0F0xBC_xE0107068_DispClkDid3_OFFSET 17 +#define D0F0xBC_xE0107068_DispClkDid3_WIDTH 7 +#define D0F0xBC_xE0107068_DispClkDid3_MASK 0xfe0000 +#define D0F0xBC_xE0107068_LClkDpmDid0_OFFSET 24 +#define D0F0xBC_xE0107068_LClkDpmDid0_WIDTH 7 +#define D0F0xBC_xE0107068_LClkDpmDid0_MASK 0x7f000000 +#define D0F0xBC_xE0107068_Reserved31_31_OFFSET 31 +#define D0F0xBC_xE0107068_Reserved31_31_WIDTH 1 +#define D0F0xBC_xE0107068_Reserved31_31_MASK 0x80000000 + +/// D0F0xBC_xE0107068 +typedef union { + struct { ///< + UINT32 Reserved0_2:3 ; ///< + UINT32 DispClkDid1:7 ; ///< + UINT32 DispClkDid2:7 ; ///< + UINT32 DispClkDid3:7 ; ///< + UINT32 LClkDpmDid0:7 ; ///< + UINT32 Reserved31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0107068_STRUCT; + +// **** D0F0xBC_xE010706B Field Definition **** +// Address +#define D0F0xBC_xE010706B_ADDRESS 0xe010706b + +// Type +#define D0F0xBC_xE010706B_TYPE TYPE_D0F0xBC +#define D0F0xBC_xE010706B_Reserved0_6_OFFSET 0 +#define D0F0xBC_xE010706B_Reserved0_6_WIDTH 7 +#define D0F0xBC_xE010706B_Reserved0_6_MASK 0x7f +#define D0F0xBC_xE010706B_LClkDpmDid1_OFFSET 7 +#define D0F0xBC_xE010706B_LClkDpmDid1_WIDTH 7 +#define D0F0xBC_xE010706B_LClkDpmDid1_MASK 0x3f80 +#define D0F0xBC_xE010706B_Reserved14_31_OFFSET 14 +#define D0F0xBC_xE010706B_Reserved14_31_WIDTH 18 +#define D0F0xBC_xE010706B_Reserved14_31_MASK 0xffffc000 + +/// D0F0xBC_xE010706B +typedef union { + struct { ///< + UINT32 Reserved0_6:7 ; ///< + UINT32 LClkDpmDid1:7 ; ///< + UINT32 Reserved14_31:18; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE010706B_STRUCT; + +// **** D0F0xBC_xE010706C Field Definition **** +// Address +#define D0F0xBC_xE010706C_ADDRESS 0xe010706c + +// Type +#define D0F0xBC_xE010706C_TYPE TYPE_D0F0xBC +#define D0F0xBC_xE010706C_Reserved0_5_OFFSET 0 +#define D0F0xBC_xE010706C_Reserved0_5_WIDTH 6 +#define D0F0xBC_xE010706C_Reserved0_5_MASK 0x3f +#define D0F0xBC_xE010706C_LClkDpmDid2_OFFSET 6 +#define D0F0xBC_xE010706C_LClkDpmDid2_WIDTH 7 +#define D0F0xBC_xE010706C_LClkDpmDid2_MASK 0x1fc0 +#define D0F0xBC_xE010706C_LClkDpmDid3_OFFSET 13 +#define D0F0xBC_xE010706C_LClkDpmDid3_WIDTH 7 +#define D0F0xBC_xE010706C_LClkDpmDid3_MASK 0xfe000 +#define D0F0xBC_xE010706C_LClkDpmValid_OFFSET 20 +#define D0F0xBC_xE010706C_LClkDpmValid_WIDTH 4 +#define D0F0xBC_xE010706C_LClkDpmValid_MASK 0xf00000 +#define D0F0xBC_xE010706C_DClkDid0_OFFSET 24 +#define D0F0xBC_xE010706C_DClkDid0_WIDTH 7 +#define D0F0xBC_xE010706C_DClkDid0_MASK 0x7f000000 +#define D0F0xBC_xE010706C_Reserved31_31_OFFSET 31 +#define D0F0xBC_xE010706C_Reserved31_31_WIDTH 1 +#define D0F0xBC_xE010706C_Reserved31_31_MASK 0x80000000 + +/// D0F0xBC_xE010706C +typedef union { + struct { ///< + UINT32 Reserved0_5:6 ; ///< + UINT32 LClkDpmDid2:7 ; ///< + UINT32 LClkDpmDid3:7 ; ///< + UINT32 LClkDpmValid:4 ; ///< + UINT32 DClkDid0:7 ; ///< + UINT32 Reserved31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE010706C_STRUCT; + +// **** D0F0xBC_xE010706F Field Definition **** +// Address +#define D0F0xBC_xE010706F_ADDRESS 0xe010706f + +// Type +#define D0F0xBC_xE010706F_TYPE TYPE_D0F0xBC +#define D0F0xBC_xE010706F_Reserved0_6_OFFSET 0 +#define D0F0xBC_xE010706F_Reserved0_6_WIDTH 7 +#define D0F0xBC_xE010706F_Reserved0_6_MASK 0x7f +#define D0F0xBC_xE010706F_DClkDid1_OFFSET 7 +#define D0F0xBC_xE010706F_DClkDid1_WIDTH 7 +#define D0F0xBC_xE010706F_DClkDid1_MASK 0x3f80 +#define D0F0xBC_xE010706F_Reserved14_31_OFFSET 14 +#define D0F0xBC_xE010706F_Reserved14_31_WIDTH 18 +#define D0F0xBC_xE010706F_Reserved14_31_MASK 0xffffc000 + +/// D0F0xBC_xE010706F +typedef union { + struct { ///< + UINT32 Reserved0_6:7 ; ///< + UINT32 DClkDid1:7 ; ///< + UINT32 Reserved14_31:18; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE010706F_STRUCT; + +// **** D0F0xBC_xE0107070 Field Definition **** +// Address +#define D0F0xBC_xE0107070_ADDRESS 0xe0107070 + +// Type +#define D0F0xBC_xE0107070_TYPE TYPE_D0F0xBC +#define D0F0xBC_xE0107070_Reserved0_5_OFFSET 0 +#define D0F0xBC_xE0107070_Reserved0_5_WIDTH 6 +#define D0F0xBC_xE0107070_Reserved0_5_MASK 0x3f +#define D0F0xBC_xE0107070_DClkDid2_OFFSET 6 +#define D0F0xBC_xE0107070_DClkDid2_WIDTH 7 +#define D0F0xBC_xE0107070_DClkDid2_MASK 0x1fc0 +#define D0F0xBC_xE0107070_DClkDid3_OFFSET 13 +#define D0F0xBC_xE0107070_DClkDid3_WIDTH 7 +#define D0F0xBC_xE0107070_DClkDid3_MASK 0xfe000 +#define D0F0xBC_xE0107070_VClkDid0_OFFSET 20 +#define D0F0xBC_xE0107070_VClkDid0_WIDTH 7 +#define D0F0xBC_xE0107070_VClkDid0_MASK 0x7f00000 +#define D0F0xBC_xE0107070_Reserved27_31_OFFSET 27 +#define D0F0xBC_xE0107070_Reserved27_31_WIDTH 5 +#define D0F0xBC_xE0107070_Reserved27_31_MASK 0xf8000000 + +/// D0F0xBC_xE0107070 +typedef union { + struct { ///< + UINT32 Reserved0_5:6 ; ///< + UINT32 DClkDid2:7 ; ///< + UINT32 DClkDid3:7 ; ///< + UINT32 VClkDid0:7 ; ///< + UINT32 Reserved27_31:5 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0107070_STRUCT; + +// **** D0F0xBC_xE0107073 Field Definition **** +// Address +#define D0F0xBC_xE0107073_ADDRESS 0xe0107073 + +// Type +#define D0F0xBC_xE0107073_TYPE TYPE_D0F0xBC +#define D0F0xBC_xE0107073_Reserved0_2_OFFSET 0 +#define D0F0xBC_xE0107073_Reserved0_2_WIDTH 3 +#define D0F0xBC_xE0107073_Reserved0_2_MASK 0x7 +#define D0F0xBC_xE0107073_VClkDid1_OFFSET 3 +#define D0F0xBC_xE0107073_VClkDid1_WIDTH 7 +#define D0F0xBC_xE0107073_VClkDid1_MASK 0x3f8 +#define D0F0xBC_xE0107073_Reserved10_31_OFFSET 10 +#define D0F0xBC_xE0107073_Reserved10_31_WIDTH 22 +#define D0F0xBC_xE0107073_Reserved10_31_MASK 0xfffffc00 + +/// D0F0xBC_xE0107073 +typedef union { + struct { ///< + UINT32 Reserved0_2:3 ; ///< + UINT32 VClkDid1:7 ; ///< + UINT32 Reserved10_31:22; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0107073_STRUCT; + +// **** D0F0xBC_xE0107074 Field Definition **** +// Address +#define D0F0xBC_xE0107074_ADDRESS 0xe0107074 + +// Type +#define D0F0xBC_xE0107074_TYPE TYPE_D0F0xBC +#define D0F0xBC_xE0107074_Reserved0_1_OFFSET 0 +#define D0F0xBC_xE0107074_Reserved0_1_WIDTH 2 +#define D0F0xBC_xE0107074_Reserved0_1_MASK 0x3 +#define D0F0xBC_xE0107074_VClkDid2_OFFSET 2 +#define D0F0xBC_xE0107074_VClkDid2_WIDTH 7 +#define D0F0xBC_xE0107074_VClkDid2_MASK 0x1fc +#define D0F0xBC_xE0107074_VClkDid3_OFFSET 9 +#define D0F0xBC_xE0107074_VClkDid3_WIDTH 7 +#define D0F0xBC_xE0107074_VClkDid3_MASK 0xfe00 +#define D0F0xBC_xE0107074_PowerplaySclkDpmValid0_OFFSET 16 +#define D0F0xBC_xE0107074_PowerplaySclkDpmValid0_WIDTH 5 +#define D0F0xBC_xE0107074_PowerplaySclkDpmValid0_MASK 0x1f0000 +#define D0F0xBC_xE0107074_PowerplaySclkDpmValid1_OFFSET 21 +#define D0F0xBC_xE0107074_PowerplaySclkDpmValid1_WIDTH 5 +#define D0F0xBC_xE0107074_PowerplaySclkDpmValid1_MASK 0x3e00000 +#define D0F0xBC_xE0107074_PowerplaySclkDpmValid2_OFFSET 26 +#define D0F0xBC_xE0107074_PowerplaySclkDpmValid2_WIDTH 5 +#define D0F0xBC_xE0107074_PowerplaySclkDpmValid2_MASK 0x7c000000 +#define D0F0xBC_xE0107074_Reserved31_31_OFFSET 31 +#define D0F0xBC_xE0107074_Reserved31_31_WIDTH 1 +#define D0F0xBC_xE0107074_Reserved31_31_MASK 0x80000000 + +/// D0F0xBC_xE0107074 +typedef union { + struct { ///< + UINT32 Reserved0_1:2 ; ///< + UINT32 VClkDid2:7 ; ///< + UINT32 VClkDid3:7 ; ///< + UINT32 PowerplaySclkDpmValid0:5 ; ///< + UINT32 PowerplaySclkDpmValid1:5 ; ///< + UINT32 PowerplaySclkDpmValid2:5 ; ///< + UINT32 Reserved31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0107074_STRUCT; + +// **** D0F0xBC_xE0107077 Field Definition **** +// Address +#define D0F0xBC_xE0107077_ADDRESS 0xe0107077 + +// Type +#define D0F0xBC_xE0107077_TYPE TYPE_D0F0xBC +#define D0F0xBC_xE0107077_Reserved0_6_OFFSET 0 +#define D0F0xBC_xE0107077_Reserved0_6_WIDTH 7 +#define D0F0xBC_xE0107077_Reserved0_6_MASK 0x7f +#define D0F0xBC_xE0107077_PowerplaySclkDpmValid3_OFFSET 7 +#define D0F0xBC_xE0107077_PowerplaySclkDpmValid3_WIDTH 5 +#define D0F0xBC_xE0107077_PowerplaySclkDpmValid3_MASK 0xf80 +#define D0F0xBC_xE0107077_Reserved12_31_OFFSET 12 +#define D0F0xBC_xE0107077_Reserved12_31_WIDTH 20 +#define D0F0xBC_xE0107077_Reserved12_31_MASK 0xfffff000 + +/// D0F0xBC_xE0107077 +typedef union { + struct { ///< + UINT32 Reserved0_6:7 ; ///< + UINT32 PowerplaySclkDpmValid3:5 ; ///< + UINT32 Reserved12_31:20; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0107077_STRUCT; + +// **** D0F0xBC_xE0107078 Field Definition **** +// Address +#define D0F0xBC_xE0107078_ADDRESS 0xe0107078 + +// Type +#define D0F0xBC_xE0107078_TYPE TYPE_D0F0xBC +#define D0F0xBC_xE0107078_Reserved0_3_OFFSET 0 +#define D0F0xBC_xE0107078_Reserved0_3_WIDTH 4 +#define D0F0xBC_xE0107078_Reserved0_3_MASK 0xf +#define D0F0xBC_xE0107078_PowerplaySclkDpmValid4_OFFSET 4 +#define D0F0xBC_xE0107078_PowerplaySclkDpmValid4_WIDTH 5 +#define D0F0xBC_xE0107078_PowerplaySclkDpmValid4_MASK 0x1f0 +#define D0F0xBC_xE0107078_PowerplaySclkDpmValid5_OFFSET 9 +#define D0F0xBC_xE0107078_PowerplaySclkDpmValid5_WIDTH 5 +#define D0F0xBC_xE0107078_PowerplaySclkDpmValid5_MASK 0x3e00 +#define D0F0xBC_xE0107078_PowerplayPolicyLabel0_OFFSET 14 +#define D0F0xBC_xE0107078_PowerplayPolicyLabel0_WIDTH 2 +#define D0F0xBC_xE0107078_PowerplayPolicyLabel0_MASK 0xc000 +#define D0F0xBC_xE0107078_PowerplayPolicyLabel1_OFFSET 16 +#define D0F0xBC_xE0107078_PowerplayPolicyLabel1_WIDTH 2 +#define D0F0xBC_xE0107078_PowerplayPolicyLabel1_MASK 0x30000 +#define D0F0xBC_xE0107078_PowerplayPolicyLabel2_OFFSET 18 +#define D0F0xBC_xE0107078_PowerplayPolicyLabel2_WIDTH 2 +#define D0F0xBC_xE0107078_PowerplayPolicyLabel2_MASK 0xc0000 +#define D0F0xBC_xE0107078_PowerplayPolicyLabel3_OFFSET 20 +#define D0F0xBC_xE0107078_PowerplayPolicyLabel3_WIDTH 2 +#define D0F0xBC_xE0107078_PowerplayPolicyLabel3_MASK 0x300000 +#define D0F0xBC_xE0107078_PowerplayPolicyLabel4_OFFSET 22 +#define D0F0xBC_xE0107078_PowerplayPolicyLabel4_WIDTH 2 +#define D0F0xBC_xE0107078_PowerplayPolicyLabel4_MASK 0xc00000 +#define D0F0xBC_xE0107078_PowerplayPolicyLabel5_OFFSET 24 +#define D0F0xBC_xE0107078_PowerplayPolicyLabel5_WIDTH 2 +#define D0F0xBC_xE0107078_PowerplayPolicyLabel5_MASK 0x3000000 +#define D0F0xBC_xE0107078_Reserved26_31_OFFSET 26 +#define D0F0xBC_xE0107078_Reserved26_31_WIDTH 6 +#define D0F0xBC_xE0107078_Reserved26_31_MASK 0xfc000000 + +/// D0F0xBC_xE0107078 +typedef union { + struct { ///< + UINT32 Reserved0_3:4 ; ///< + UINT32 PowerplaySclkDpmValid4:5 ; ///< + UINT32 PowerplaySclkDpmValid5:5 ; ///< + UINT32 PowerplayPolicyLabel0:2 ; ///< + UINT32 PowerplayPolicyLabel1:2 ; ///< + UINT32 PowerplayPolicyLabel2:2 ; ///< + UINT32 PowerplayPolicyLabel3:2 ; ///< + UINT32 PowerplayPolicyLabel4:2 ; ///< + UINT32 PowerplayPolicyLabel5:2 ; ///< + UINT32 Reserved26_31:6 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE0107078_STRUCT; + +// **** D0F0xBC_xE010707B Field Definition **** +// Address +#define D0F0xBC_xE010707B_ADDRESS 0xe010707b + +// Type +#define D0F0xBC_xE010707B_TYPE TYPE_D0F0xBC +#define D0F0xBC_xE010707B_Reserved0_1_OFFSET 0 +#define D0F0xBC_xE010707B_Reserved0_1_WIDTH 2 +#define D0F0xBC_xE010707B_Reserved0_1_MASK 0x3 +#define D0F0xBC_xE010707B_PowerplayStateFlag0_OFFSET 2 +#define D0F0xBC_xE010707B_PowerplayStateFlag0_WIDTH 7 +#define D0F0xBC_xE010707B_PowerplayStateFlag0_MASK 0x1fc +#define D0F0xBC_xE010707B_Reserved9_31_OFFSET 9 +#define D0F0xBC_xE010707B_Reserved9_31_WIDTH 23 +#define D0F0xBC_xE010707B_Reserved9_31_MASK 0xfffffe00 + +/// D0F0xBC_xE010707B +typedef union { + struct { ///< + UINT32 Reserved0_1:2 ; ///< + UINT32 PowerplayStateFlag0:7 ; ///< + UINT32 Reserved9_31:23; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE010707B_STRUCT; + +// **** D0F0xBC_xE010707C Field Definition **** +// Address +#define D0F0xBC_xE010707C_ADDRESS 0xe010707c + +// Type +#define D0F0xBC_xE010707C_TYPE TYPE_D0F0xBC +#define D0F0xBC_xE010707C_Reserved0_0_OFFSET 0 +#define D0F0xBC_xE010707C_Reserved0_0_WIDTH 1 +#define D0F0xBC_xE010707C_Reserved0_0_MASK 0x1 +#define D0F0xBC_xE010707C_PowerplayStateFlag1_OFFSET 1 +#define D0F0xBC_xE010707C_PowerplayStateFlag1_WIDTH 7 +#define D0F0xBC_xE010707C_PowerplayStateFlag1_MASK 0xfe +#define D0F0xBC_xE010707C_PowerplayStateFlag2_OFFSET 8 +#define D0F0xBC_xE010707C_PowerplayStateFlag2_WIDTH 7 +#define D0F0xBC_xE010707C_PowerplayStateFlag2_MASK 0x7f00 +#define D0F0xBC_xE010707C_PowerplayStateFlag3_OFFSET 15 +#define D0F0xBC_xE010707C_PowerplayStateFlag3_WIDTH 7 +#define D0F0xBC_xE010707C_PowerplayStateFlag3_MASK 0x3f8000 +#define D0F0xBC_xE010707C_PowerplayStateFlag4_OFFSET 22 +#define D0F0xBC_xE010707C_PowerplayStateFlag4_WIDTH 7 +#define D0F0xBC_xE010707C_PowerplayStateFlag4_MASK 0x1fc00000 +#define D0F0xBC_xE010707C_Reserved29_31_OFFSET 29 +#define D0F0xBC_xE010707C_Reserved29_31_WIDTH 3 +#define D0F0xBC_xE010707C_Reserved29_31_MASK 0xe0000000 + +/// D0F0xBC_xE010707C +typedef union { + struct { ///< + UINT32 Reserved0_0:1 ; ///< + UINT32 PowerplayStateFlag1:7 ; ///< + UINT32 PowerplayStateFlag2:7 ; ///< + UINT32 PowerplayStateFlag3:7 ; ///< + UINT32 PowerplayStateFlag4:7 ; ///< + UINT32 Reserved29_31:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE010707C_STRUCT; + +// **** D0F0xBC_xE010707F Field Definition **** +// Address +#define D0F0xBC_xE010707F_ADDRESS 0xe010707f + +// Type +#define D0F0xBC_xE010707F_TYPE TYPE_D0F0xBC +#define D0F0xBC_xE010707F_Reserved0_4_OFFSET 0 +#define D0F0xBC_xE010707F_Reserved0_4_WIDTH 5 +#define D0F0xBC_xE010707F_Reserved0_4_MASK 0x1f +#define D0F0xBC_xE010707F_PowerplayStateFlag5_OFFSET 5 +#define D0F0xBC_xE010707F_PowerplayStateFlag5_WIDTH 7 +#define D0F0xBC_xE010707F_PowerplayStateFlag5_MASK 0xfe0 +#define D0F0xBC_xE010707F_Reserved12_31_OFFSET 12 +#define D0F0xBC_xE010707F_Reserved12_31_WIDTH 20 +#define D0F0xBC_xE010707F_Reserved12_31_MASK 0xfffff000 + +/// D0F0xBC_xE010707F +typedef union { + struct { ///< + UINT32 Reserved0_4:5 ; ///< + UINT32 PowerplayStateFlag5:7 ; ///< + UINT32 Reserved12_31:20; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE010707F_STRUCT; + +// **** D0F0xBC_x1F630 Register Definition **** +// Address +#define D0F0xBC_x1F630_ADDRESS 0x1f630 + +// Type +#define D0F0xBC_x1F630_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F630_RECONF_WAIT_OFFSET 0 +#define D0F0xBC_x1F630_RECONF_WAIT_WIDTH 8 +#define D0F0xBC_x1F630_RECONF_WAIT_MASK 0xff +#define D0F0xBC_x1F630_RECONF_WRAPPER_OFFSET 8 +#define D0F0xBC_x1F630_RECONF_WRAPPER_WIDTH 8 +#define D0F0xBC_x1F630_RECONF_WRAPPER_MASK 0x00ff00 + +/// D0F0xBC_x1F630 +typedef union { + struct { ///< + UINT32 RECONF_WAIT:8; ///< + UINT32 RECONF_WRAPPER:8; ///< + UINT32 Reserved:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F630_STRUCT; + +// **** D0F0xE4_WRAP_8012 Register Definition **** +// Address +#define D0F0xE4_WRAP_8012_ADDRESS 0x8012 + +// Type +#define D0F0xE4_WRAP_8012_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_OFFSET 0 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_MASK 0x3f +#define D0F0xE4_WRAP_8012_Reserved_6_6_OFFSET 6 +#define D0F0xE4_WRAP_8012_Reserved_6_6_WIDTH 1 +#define D0F0xE4_WRAP_8012_Reserved_6_6_MASK 0x40 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_OFFSET 7 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_MASK 0x80 +#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_OFFSET 8 +#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_WIDTH 6 +#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_MASK 0x3f00 +#define D0F0xE4_WRAP_8012_Reserved_15_14_OFFSET 14 +#define D0F0xE4_WRAP_8012_Reserved_15_14_WIDTH 2 +#define D0F0xE4_WRAP_8012_Reserved_15_14_MASK 0xc000 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_OFFSET 16 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_MASK 0x3f0000 +#define D0F0xE4_WRAP_8012_Reserved_22_22_OFFSET 22 +#define D0F0xE4_WRAP_8012_Reserved_22_22_WIDTH 1 +#define D0F0xE4_WRAP_8012_Reserved_22_22_MASK 0x400000 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_OFFSET 23 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_MASK 0x800000 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_OFFSET 24 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_WIDTH 6 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_MASK 0x3f000000 +#define D0F0xE4_WRAP_8012_Reserved_31_30_OFFSET 30 +#define D0F0xE4_WRAP_8012_Reserved_31_30_WIDTH 2 +#define D0F0xE4_WRAP_8012_Reserved_31_30_MASK 0xc0000000 + +/// D0F0xE4_WRAP_8012 +typedef union { + struct { ///< + UINT32 Pif1xIdleGateLatency:6 ; ///< + UINT32 Reserved_6_6:1 ; ///< + UINT32 Pif1xIdleGateEnable:1 ; ///< + UINT32 Pif1xIdleResumeLatency:6 ; ///< + UINT32 Reserved_15_14:2 ; ///< + UINT32 Pif2p5xIdleGateLatency:6 ; ///< + UINT32 Reserved_22_22:1 ; ///< + UINT32 Pif2p5xIdleGateEnable:1 ; ///< + UINT32 Pif2p5xIdleResumeLatency:6 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8012_STRUCT; + +// **** D0F0xE4_WRAP_8014 Register Definition **** +// Address +#define D0F0xE4_WRAP_8014_ADDRESS 0x8014 + +// Type +#define D0F0xE4_WRAP_8014_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_OFFSET 0 +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_MASK 0x1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_OFFSET 1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_MASK 0x2 +#define D0F0xE4_WRAP_8014_DdiGatePifA1xEnable_OFFSET 2 +#define D0F0xE4_WRAP_8014_DdiGatePifA1xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_DdiGatePifA1xEnable_MASK 0x4 +#define D0F0xE4_WRAP_8014_DdiGatePifB1xEnable_OFFSET 3 +#define D0F0xE4_WRAP_8014_DdiGatePifB1xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_DdiGatePifB1xEnable_MASK 0x8 +#define D0F0xE4_WRAP_8014_DdiGatePifC1xEnable_OFFSET 4 +#define D0F0xE4_WRAP_8014_DdiGatePifC1xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_DdiGatePifC1xEnable_MASK 0x10 +#define D0F0xE4_WRAP_8014_DdiGatePifD1xEnable_OFFSET 5 +#define D0F0xE4_WRAP_8014_DdiGatePifD1xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_DdiGatePifD1xEnable_MASK 0x20 +#define D0F0xE4_WRAP_8014_Reserved_7_6_OFFSET 6 +#define D0F0xE4_WRAP_8014_Reserved_7_6_WIDTH 2 +#define D0F0xE4_WRAP_8014_Reserved_7_6_MASK 0xc0 +#define D0F0xE4_WRAP_8014_DdiGatePifA2p5xEnable_OFFSET 8 +#define D0F0xE4_WRAP_8014_DdiGatePifA2p5xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_DdiGatePifA2p5xEnable_MASK 0x100 +#define D0F0xE4_WRAP_8014_DdiGatePifB2p5xEnable_OFFSET 9 +#define D0F0xE4_WRAP_8014_DdiGatePifB2p5xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_DdiGatePifB2p5xEnable_MASK 0x200 +#define D0F0xE4_WRAP_8014_DdiGatePifC2p5xEnable_OFFSET 10 +#define D0F0xE4_WRAP_8014_DdiGatePifC2p5xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_DdiGatePifC2p5xEnable_MASK 0x400 +#define D0F0xE4_WRAP_8014_DdiGatePifD2p5xEnable_OFFSET 11 +#define D0F0xE4_WRAP_8014_DdiGatePifD2p5xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_DdiGatePifD2p5xEnable_MASK 0x800 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_OFFSET 12 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_MASK 0x1000 +#define D0F0xE4_WRAP_8014_PcieGatePifB1xEnable_OFFSET 13 +#define D0F0xE4_WRAP_8014_PcieGatePifB1xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifB1xEnable_MASK 0x2000 +#define D0F0xE4_WRAP_8014_PcieGatePifC1xEnable_OFFSET 14 +#define D0F0xE4_WRAP_8014_PcieGatePifC1xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifC1xEnable_MASK 0x4000 +#define D0F0xE4_WRAP_8014_PcieGatePifD1xEnable_OFFSET 15 +#define D0F0xE4_WRAP_8014_PcieGatePifD1xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifD1xEnable_MASK 0x8000 +#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_OFFSET 16 +#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_MASK 0x10000 +#define D0F0xE4_WRAP_8014_PcieGatePifB2p5xEnable_OFFSET 17 +#define D0F0xE4_WRAP_8014_PcieGatePifB2p5xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifB2p5xEnable_MASK 0x20000 +#define D0F0xE4_WRAP_8014_PcieGatePifC2p5xEnable_OFFSET 18 +#define D0F0xE4_WRAP_8014_PcieGatePifC2p5xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifC2p5xEnable_MASK 0x40000 +#define D0F0xE4_WRAP_8014_PcieGatePifD2p5xEnable_OFFSET 19 +#define D0F0xE4_WRAP_8014_PcieGatePifD2p5xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifD2p5xEnable_MASK 0x80000 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_OFFSET 20 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_MASK 0x100000 +#define D0F0xE4_WRAP_8014_Reserved_23_21_OFFSET 21 +#define D0F0xE4_WRAP_8014_Reserved_23_21_WIDTH 3 +#define D0F0xE4_WRAP_8014_Reserved_23_21_MASK 0xe00000 +#define D0F0xE4_WRAP_8014_DdiGateDigAEnable_OFFSET 24 +#define D0F0xE4_WRAP_8014_DdiGateDigAEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_DdiGateDigAEnable_MASK 0x1000000 +#define D0F0xE4_WRAP_8014_DdiGateDigBEnable_OFFSET 25 +#define D0F0xE4_WRAP_8014_DdiGateDigBEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_DdiGateDigBEnable_MASK 0x2000000 +#define D0F0xE4_WRAP_8014_DdiGateDigCEnable_OFFSET 26 +#define D0F0xE4_WRAP_8014_DdiGateDigCEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_DdiGateDigCEnable_MASK 0x4000000 +#define D0F0xE4_WRAP_8014_DdiGateDigDEnable_OFFSET 27 +#define D0F0xE4_WRAP_8014_DdiGateDigDEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_DdiGateDigDEnable_MASK 0x8000000 +#define D0F0xE4_WRAP_8014_SpareRegRw_OFFSET 28 +#define D0F0xE4_WRAP_8014_SpareRegRw_WIDTH 4 +#define D0F0xE4_WRAP_8014_SpareRegRw_MASK 0xf0000000 + +/// D0F0xE4_WRAP_8014 +typedef union { + struct { ///< + UINT32 TxclkPermGateEnable:1 ; ///< + UINT32 TxclkPrbsGateEnable:1 ; ///< + UINT32 DdiGatePifA1xEnable:1 ; ///< + UINT32 DdiGatePifB1xEnable:1 ; ///< + UINT32 DdiGatePifC1xEnable:1 ; ///< + UINT32 DdiGatePifD1xEnable:1 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 DdiGatePifA2p5xEnable:1 ; ///< + UINT32 DdiGatePifB2p5xEnable:1 ; ///< + UINT32 DdiGatePifC2p5xEnable:1 ; ///< + UINT32 DdiGatePifD2p5xEnable:1 ; ///< + UINT32 PcieGatePifA1xEnable:1 ; ///< + UINT32 PcieGatePifB1xEnable:1 ; ///< + UINT32 PcieGatePifC1xEnable:1 ; ///< + UINT32 PcieGatePifD1xEnable:1 ; ///< + UINT32 PcieGatePifA2p5xEnable:1 ; ///< + UINT32 PcieGatePifB2p5xEnable:1 ; ///< + UINT32 PcieGatePifC2p5xEnable:1 ; ///< + UINT32 PcieGatePifD2p5xEnable:1 ; ///< + UINT32 TxclkPermGateOnlyWhenPllPwrDn:1 ; ///< + UINT32 Reserved_23_21:3 ; ///< + UINT32 DdiGateDigAEnable:1 ; ///< + UINT32 DdiGateDigBEnable:1 ; ///< + UINT32 DdiGateDigCEnable:1 ; ///< + UINT32 DdiGateDigDEnable:1 ; ///< + UINT32 SpareRegRw:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8014_STRUCT; + +// **** D0F0xE4_WRAP_8015 Register Definition **** +// Address +#define D0F0xE4_WRAP_8015_ADDRESS 0x8015 + +// Type +#define D0F0xE4_WRAP_8015_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_OFFSET 16 +#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_MASK 0x3f0000 +#define D0F0xE4_WRAP_8015_Reserved_22_22_OFFSET 22 +#define D0F0xE4_WRAP_8015_Reserved_22_22_WIDTH 1 +#define D0F0xE4_WRAP_8015_Reserved_22_22_MASK 0x400000 +#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_OFFSET 23 +#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_MASK 0x800000 +#define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_OFFSET 24 +#define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_MASK 0x3f000000 +#define D0F0xE4_WRAP_8015_Reserved_30_30_OFFSET 30 +#define D0F0xE4_WRAP_8015_Reserved_30_30_WIDTH 1 +#define D0F0xE4_WRAP_8015_Reserved_30_30_MASK 0x40000000 +#define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_OFFSET 31 +#define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_MASK 0x80000000 + +/// D0F0xE4_WRAP_8015 +typedef union { + struct { ///< + UINT32 /* EnableD0StateReport*/:1 ; ///< + UINT32 /* Reserved_1_1*/:1 ; ///< + UINT32 line477/* SlowRefclkThroughTxclk2p5x*/:1 ; ///< + UINT32 line478/* SlowRefclkEnableTxclk2p5x*/:1 ; ///< + UINT32 line479/* SlowRefclkDivideTxclk2p5x*/:2 ; ///< + UINT32 line480/* SlowRefclkBurstTxclk2p5x*/:2 ; ///< + UINT32 /* Reserved_8_8*/:1 ; ///< + UINT32 line482/* SlowRefclkLcntGateForce*/:1 ; ///< + UINT32 line483/* SlowRefclkThroughTxclk1x*/:1 ; ///< + UINT32 line484/* SlowRefclkEnableTxclk1x*/:1 ; ///< + UINT32 line485/* SlowRefclkDivideTxclk1x*/:2 ; ///< + UINT32 line486/* SlowRefclkBurstTxclk1x*/:2 ; ///< + UINT32 RefclkRegsGateLatency:6 ; ///< + UINT32 Reserved_22_22:1 ; ///< + UINT32 RefclkRegsGateEnable:1 ; ///< + UINT32 RefclkBphyGateLatency:6 ; ///< + UINT32 Reserved_30_30:1 ; ///< + UINT32 RefclkBphyGateEnable:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8015_STRUCT; + +// **** PGFSM_Delay_Reg_0 Register Definition **** +// Address + +// **** GMMx670 Register Definition **** +// Address +#define GMMx670_ADDRESS 0x670 + +// Type +#define GMMx670_TYPE TYPE_GMM + +typedef union { + struct { ///< + UINT32 ex1071_0:1; + UINT32 Reserved_7_1:7 ; ///< + UINT32 TdpClampMode:8 ; ///< + UINT32 ex1071_3:8; + UINT32 ex1071_4:8; + } Field; ///< + UINT32 Value; ///< +} ex1071_STRUCT; + + + +// **** GMMx600 Register Definition **** +// Address +#define GMMx600_ADDRESS 0x600 + +// Type +#define GMMx600_TYPE TYPE_GMM +// Field Data +#define GMMx600_IndClkDiv_OFFSET 0 +#define GMMx600_IndClkDiv_WIDTH 7 +#define GMMx600_IndClkDiv_MASK 0x7f +#define GMMx600_Reserved_7_7_OFFSET 7 +#define GMMx600_Reserved_7_7_WIDTH 1 +#define GMMx600_Reserved_7_7_MASK 0x80 +#define GMMx600_ClkDirCntlEn_OFFSET 8 +#define GMMx600_ClkDirCntlEn_WIDTH 1 +#define GMMx600_ClkDirCntlEn_MASK 0x100 +#define GMMx600_ClkDirCntlTog_OFFSET 9 +#define GMMx600_ClkDirCntlTog_WIDTH 1 +#define GMMx600_ClkDirCntlTog_MASK 0x200 +#define GMMx600_ClkDirCntlDiv_OFFSET 10 +#define GMMx600_ClkDirCntlDiv_WIDTH 7 +#define GMMx600_ClkDirCntlDiv_MASK 0x1fc00 +#define GMMx600_Reserved_31_17_OFFSET 17 +#define GMMx600_Reserved_31_17_WIDTH 15 +#define GMMx600_Reserved_31_17_MASK 0xfffe0000 + +/// GMMx600 +typedef union { + struct { ///< + UINT32 IndClkDiv:7 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 ClkDirCntlEn:1 ; ///< + UINT32 ClkDirCntlTog:1 ; ///< + UINT32 ClkDirCntlDiv:7 ; ///< + UINT32 Reserved_31_17:15; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx600_STRUCT; + +// **** GMMx604 Register Definition **** +// Address +#define GMMx604_ADDRESS 0x604 + +// Type +#define GMMx604_TYPE TYPE_GMM +// Field Data +#define GMMx604_SclkStatus_OFFSET 0 +#define GMMx604_SclkStatus_WIDTH 1 +#define GMMx604_SclkStatus_MASK 0x1 +#define GMMx604_SclkForceStatus_OFFSET 1 +#define GMMx604_SclkForceStatus_WIDTH 1 +#define GMMx604_SclkForceStatus_MASK 0x2 +#define GMMx604_SclkOverclkDetect_OFFSET 2 +#define GMMx604_SclkOverclkDetect_WIDTH 1 +#define GMMx604_SclkOverclkDetect_MASK 0x4 +#define GMMx604_SclkDirCntlTogDone_OFFSET 3 +#define GMMx604_SclkDirCntlTogDone_WIDTH 1 +#define GMMx604_SclkDirCntlTogDone_MASK 0x8 +#define GMMx604_Reserved_31_4_OFFSET 4 +#define GMMx604_Reserved_31_4_WIDTH 28 +#define GMMx604_Reserved_31_4_MASK 0xfffffff0 + +/// GMMx604 +typedef union { + struct { ///< + UINT64 SclkStatus:1 ; ///< + UINT64 SclkForceStatus:1 ; ///< + UINT64 SclkOverclkDetect:1 ; ///< + UINT64 SclkDirCntlTogDone:1 ; ///< + UINT64 Reserved_31_4:28; ///< + } Field; ///< + UINT64 Value; ///< +} GMMx604_STRUCT; + +// **** GMMx5F50 Register Definition **** +// Address +#define GMMx5F50_ADDRESS 0x5F50 + +// Type +#define GMMx5F50_TYPE TYPE_GMM +// Field Data +#define GMMx5F50_PortConnectivity_OFFSET 0 +#define GMMx5F50_PortConnectivity_WIDTH 3 +#define GMMx5F50_PortConnectivity_MASK 0x7 +#define GMMx5F50_Reserved_3_3_OFFSET 3 +#define GMMx5F50_Reserved_3_3_WIDTH 1 +#define GMMx5F50_Reserved_3_3_MASK 0x8 +#define GMMx5F50_PortConnectivityOverrideEnable_OFFSET 4 +#define GMMx5F50_PortConnectivityOverrideEnable_WIDTH 1 +#define GMMx5F50_PortConnectivityOverrideEnable_MASK 0x10 +#define GMMx5F50_Reserved_31_5_OFFSET 5 +#define GMMx5F50_Reserved_31_5_WIDTH 27 +#define GMMx5F50_Reserved_31_5_MASK 0xffffffe0 + +/// GMMx5F50 +typedef union { + struct { ///< + UINT32 PortConnectivity:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 PortConnectivityOverrideEnable:1 ; ///< + UINT32 Reserved_31_5:27; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx5F50_STRUCT; + +// **** D0F0xE4_WRAP_8020 Register Definition **** +// Address +#define D0F0xE4_WRAP_8020_ADDRESS 0x8020 + +// Type +#define D0F0xE4_WRAP_8020_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8020_Reserved_0_0_OFFSET 0 +#define D0F0xE4_WRAP_8020_Reserved_0_0_WIDTH 1 +#define D0F0xE4_WRAP_8020_Reserved_0_0_MASK 0x1 +#define D0F0xE4_WRAP_8020_PrbsPcieLbSelect_OFFSET 3 +#define D0F0xE4_WRAP_8020_PrbsPcieLbSelect_WIDTH 1 +#define D0F0xE4_WRAP_8020_PrbsPcieLbSelect_MASK 0x8 +#define D0F0xE4_WRAP_8020_Reserved_31_5_OFFSET 5 +#define D0F0xE4_WRAP_8020_Reserved_31_5_WIDTH 27 +#define D0F0xE4_WRAP_8020_Reserved_31_5_MASK 0xffffffe0 + +/// D0F0xE4_WRAP_8020 +typedef union { + struct { ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 :2 ; ///< + UINT32 PrbsPcieLbSelect:1 ; ///< + UINT32 :1 ; ///< + UINT32 Reserved_31_5:27; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8020_STRUCT; + +// **** D0F0xE4_WRAP_8025 Register Definition **** +// Address +#define D0F0xE4_WRAP_8025_ADDRESS 0x8025 + +// Type +#define D0F0xE4_WRAP_8025_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_OFFSET 0 +#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_WIDTH 3 +#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_MASK 0x7 +#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_OFFSET 3 +#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_WIDTH 2 +#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_MASK 0x18 +#define D0F0xE4_WRAP_8025_LMLinkSpeed0_OFFSET 5 +#define D0F0xE4_WRAP_8025_LMLinkSpeed0_WIDTH 1 +#define D0F0xE4_WRAP_8025_LMLinkSpeed0_MASK 0x20 +#define D0F0xE4_WRAP_8025_Reserved_7_6_OFFSET 6 +#define D0F0xE4_WRAP_8025_Reserved_7_6_WIDTH 2 +#define D0F0xE4_WRAP_8025_Reserved_7_6_MASK 0xc0 +#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_OFFSET 8 +#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_WIDTH 3 +#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_MASK 0x700 +#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_OFFSET 11 +#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_WIDTH 2 +#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_MASK 0x1800 +#define D0F0xE4_WRAP_8025_LMLinkSpeed1_OFFSET 13 +#define D0F0xE4_WRAP_8025_LMLinkSpeed1_WIDTH 1 +#define D0F0xE4_WRAP_8025_LMLinkSpeed1_MASK 0x2000 +#define D0F0xE4_WRAP_8025_Reserved_15_14_OFFSET 14 +#define D0F0xE4_WRAP_8025_Reserved_15_14_WIDTH 2 +#define D0F0xE4_WRAP_8025_Reserved_15_14_MASK 0xc000 +#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_OFFSET 16 +#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_WIDTH 3 +#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_MASK 0x70000 +#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_OFFSET 19 +#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_WIDTH 2 +#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_MASK 0x180000 +#define D0F0xE4_WRAP_8025_LMLinkSpeed2_OFFSET 21 +#define D0F0xE4_WRAP_8025_LMLinkSpeed2_WIDTH 1 +#define D0F0xE4_WRAP_8025_LMLinkSpeed2_MASK 0x200000 +#define D0F0xE4_WRAP_8025_Reserved_23_22_OFFSET 22 +#define D0F0xE4_WRAP_8025_Reserved_23_22_WIDTH 2 +#define D0F0xE4_WRAP_8025_Reserved_23_22_MASK 0xc00000 +#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_OFFSET 24 +#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_WIDTH 3 +#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_MASK 0x7000000 +#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_OFFSET 27 +#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_WIDTH 2 +#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_MASK 0x18000000 +#define D0F0xE4_WRAP_8025_LMLinkSpeed3_OFFSET 29 +#define D0F0xE4_WRAP_8025_LMLinkSpeed3_WIDTH 1 +#define D0F0xE4_WRAP_8025_LMLinkSpeed3_MASK 0x20000000 +#define D0F0xE4_WRAP_8025_Reserved_31_30_OFFSET 30 +#define D0F0xE4_WRAP_8025_Reserved_31_30_WIDTH 2 +#define D0F0xE4_WRAP_8025_Reserved_31_30_MASK 0xc0000000 + +/// D0F0xE4_WRAP_8025 +typedef union { + struct { ///< + UINT32 LMTxPhyCmd0:3 ; ///< + UINT32 LMRxPhyCmd0:2 ; ///< + UINT32 LMLinkSpeed0:1 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 LMTxPhyCmd1:3 ; ///< + UINT32 LMRxPhyCmd1:2 ; ///< + UINT32 LMLinkSpeed1:1 ; ///< + UINT32 Reserved_15_14:2 ; ///< + UINT32 LMTxPhyCmd2:3 ; ///< + UINT32 LMRxPhyCmd2:2 ; ///< + UINT32 LMLinkSpeed2:1 ; ///< + UINT32 Reserved_23_22:2 ; ///< + UINT32 LMTxPhyCmd3:3 ; ///< + UINT32 LMRxPhyCmd3:2 ; ///< + UINT32 LMLinkSpeed3:1 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8025_STRUCT; +typedef union { + struct { ///< + UINT32 ex1072_0:8; + UINT32 NumDropLsb:8 ; ///< + UINT32 ex1072_2:16; + } Field; ///< + UINT32 Value; ///< +} ex1072_STRUCT; + +// **** D0F0xBC_x1F840 Register Definition **** +// Address +#define D0F0xBC_x1F840_ADDRESS 0x1f840 + +// Type +#define D0F0xBC_x1F840_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_x1F840_IddspikeOCP_OFFSET 0 +#define D0F0xBC_x1F840_IddspikeOCP_WIDTH 16 +#define D0F0xBC_x1F840_IddspikeOCP_MASK 0xffff +#define D0F0xBC_x1F840_IddNbspikeOCP_OFFSET 16 +#define D0F0xBC_x1F840_IddNbspikeOCP_WIDTH 16 +#define D0F0xBC_x1F840_IddNbspikeOCP_MASK 0xffff0000 + +/// D0F0xBC_x1F840 +typedef union { + struct { ///< + UINT32 IddspikeOCP:16; ///< + UINT32 IddNbspikeOCP:16; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_x1F840_STRUCT; + +typedef union { + struct { ///< + UINT32 ex1073_0:32; + } Field; ///< + UINT32 Value; ///< +} ex1073_STRUCT; + +// **** D0F0xBC_xE010703C Register Definition **** +// Address +#define D0F0xBC_xE010703C_ADDRESS 0xe010703c + +// Type +#define D0F0xBC_xE010703C_TYPE TYPE_D0F0xBC +// Field Data +#define D0F0xBC_xE010703C_Reserved_2_0_OFFSET 0 +#define D0F0xBC_xE010703C_Reserved_2_0_WIDTH 3 +#define D0F0xBC_xE010703C_Reserved_2_0_MASK 0x7 +#define D0F0xBC_xE010703C_NbPstateHi_OFFSET 3 +#define D0F0xBC_xE010703C_NbPstateHi_WIDTH 2 +#define D0F0xBC_xE010703C_NbPstateHi_MASK 0x18 +#define D0F0xBC_xE010703C_NbPstateLo_OFFSET 5 +#define D0F0xBC_xE010703C_NbPstateLo_WIDTH 2 +#define D0F0xBC_xE010703C_NbPstateLo_MASK 0x60 +#define D0F0xBC_xE010703C_Reserved_31_7_OFFSET 7 +#define D0F0xBC_xE010703C_Reserved_31_7_WIDTH 25 +#define D0F0xBC_xE010703C_Reserved_31_7_MASK 0xffffff80 + +/// D0F0xBC_xE010703C +typedef union { + struct { ///< + UINT32 Reserved_2_0:3 ; ///< + UINT32 NbPstateHi:2 ; ///< + UINT32 NbPstateLo:2 ; ///< + UINT32 Reserved_31_7:25; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xBC_xE010703C_STRUCT; + + + +typedef union { + struct { ///< + UINT32 ex1075_0:11; + UINT32 Reserved_31_11:21 ; ///< + } Field; ///< + UINT32 Value; ///< +} ex1075_STRUCT; + + + +// Address +#define D0F0xBC_x1F480_ADDRESS 0x1f480 + +// Type +#define D0F0xBC_x1F480_TYPE TYPE_D0F0xBC + +#endif + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtEarly.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtEarly.c new file mode 100644 index 0000000..2fb8100 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtEarly.c @@ -0,0 +1,153 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB early init interface + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "OptionGnb.h" +#include "GnbLibFeatures.h" +#include "GeneralServices.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_GNBINITATEARLY_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern OPTION_GNB_CONFIGURATION GnbEarlyFeatureTable[]; +extern OPTION_GNB_CONFIGURATION GnbEarlierFeatureTable[]; +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GnbInitAtEarly ( + IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr + ); + +AGESA_STATUS +GnbInitAtEarlier ( + IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr + ); +/*----------------------------------------------------------------------------------------*/ +/** + * Init GNB at Early + * + * + * + * @param[in,out] EarlyParamsPtr Pointer to early configuration params. + * @retval Initialization status. + */ +AGESA_STATUS +GnbInitAtEarly ( + IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr + ) +{ + AGESA_STATUS Status; + Status = GnbLibDispatchFeatures (&GnbEarlyFeatureTable[0], &EarlyParamsPtr->StdHeader); + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GNB at Early before CPU + * + * + * + * @param[in,out] EarlyParamsPtr Pointer to early configuration params. + * @retval Initialization status. + */ +AGESA_STATUS +GnbInitAtEarlier ( + IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr + ) +{ + AGESA_STATUS Status; + + // Only run code on BSP + if (IsBsp (&EarlyParamsPtr->StdHeader, &Status)) { + Status = GnbLibDispatchFeatures (&GnbEarlierFeatureTable[0], &EarlyParamsPtr->StdHeader); + } + + return Status; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtEnv.c new file mode 100644 index 0000000..3b0366a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtEnv.c @@ -0,0 +1,164 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB env init interface + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "OptionGnb.h" +#include "GnbLibFeatures.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_GNBINITATENV_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern OPTION_GNB_CONFIGURATION GnbEnvFeatureTable[]; +extern BUILD_OPT_CFG UserOptions; +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GnbInitAtEnv ( + IN AMD_ENV_PARAMS *EnvParamsPtr + ); + +VOID +GnbInitDataStructAtEnvDef ( + IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr, + IN AMD_ENV_PARAMS *EnvParamsPtr + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Default constructor of GNB configuration at Env + * + * + * + * @param[in] GnbEnvConfigPtr Pointer to gnb env configuration params. + * @param[in] EnvParamsPtr Pointer to env configuration params. + */ +VOID +GnbInitDataStructAtEnvDef ( + IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr, + IN AMD_ENV_PARAMS *EnvParamsPtr + ) +{ + GnbEnvConfigPtr->Gnb3dStereoPinIndex = UserOptions.CfgGnb3dStereoPinIndex; + GnbEnvConfigPtr->IommuSupport = UserOptions.CfgIommuSupport; + GnbEnvConfigPtr->LvdsSpreadSpectrum = UserOptions.CfgLvdsSpreadSpectrum; + GnbEnvConfigPtr->LvdsSpreadSpectrumRate = UserOptions.CfgLvdsSpreadSpectrumRate; + GnbEnvConfigPtr->LvdsPowerOnSeqDigonToDe = UserOptions.CfgLvdsPowerOnSeqDigonToDe; + GnbEnvConfigPtr->LvdsPowerOnSeqDeToVaryBl = UserOptions.CfgLvdsPowerOnSeqDeToVaryBl; + GnbEnvConfigPtr->LvdsPowerOnSeqDeToDigon = UserOptions.CfgLvdsPowerOnSeqDeToDigon; + GnbEnvConfigPtr->LvdsPowerOnSeqVaryBlToDe = UserOptions.CfgLvdsPowerOnSeqVaryBlToDe; + GnbEnvConfigPtr->LvdsPowerOnSeqOnToOffDelay = UserOptions.CfgLvdsPowerOnSeqOnToOffDelay; + GnbEnvConfigPtr->LvdsPowerOnSeqVaryBlToBlon = UserOptions.CfgLvdsPowerOnSeqVaryBlToBlon; + GnbEnvConfigPtr->LvdsPowerOnSeqBlonToVaryBl = UserOptions.CfgLvdsPowerOnSeqBlonToVaryBl; + GnbEnvConfigPtr->LvdsMaxPixelClockFreq = UserOptions.CfgLvdsMaxPixelClockFreq; + GnbEnvConfigPtr->LcdBitDepthControlValue = UserOptions.CfgLcdBitDepthControlValue; + GnbEnvConfigPtr->Lvds24bbpPanelMode = UserOptions.CfgLvds24bbpPanelMode; + GnbEnvConfigPtr->LvdsMiscControl.Value = 0; + GnbEnvConfigPtr->LvdsMiscControl.Value = UserOptions.CfgLvdsMiscControl.Value; + GnbEnvConfigPtr->PcieRefClkSpreadSpectrum = UserOptions.CfgPcieRefClkSpreadSpectrum; + GnbEnvConfigPtr->GnbRemoteDisplaySupport = UserOptions.CfgGnbRemoteDisplaySupport; + GnbEnvConfigPtr->LvdsMiscVoltAdjustment = UserOptions.CfgLvdsMiscVoltAdjustment; + GnbEnvConfigPtr->DisplayMiscControl.Value = UserOptions.CfgDisplayMiscControl.Value; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GNB at Env + * + * + * + * @param[in] EnvParamsPtr Pointer to env configuration params. + * @retval Initialization status. + */ + +AGESA_STATUS +GnbInitAtEnv ( + IN AMD_ENV_PARAMS *EnvParamsPtr + ) +{ + AGESA_STATUS Status; + Status = GnbLibDispatchFeatures (&GnbEnvFeatureTable[0], &EnvParamsPtr->StdHeader); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtLate.c new file mode 100644 index 0000000..0e1a7c3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtLate.c @@ -0,0 +1,121 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB late init interface + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "OptionGnb.h" +#include "GnbLibFeatures.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_GNBINITATLATE_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern OPTION_GNB_CONFIGURATION GnbLateFeatureTable[]; +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GnbInitAtLate ( + IN OUT AMD_LATE_PARAMS *LateParamsPtr + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GNB at Late post + * + * + * + * @param[in,out] LateParamsPtr Pointer to late configuration params. + * @retval Initialization status. + */ + +AGESA_STATUS +GnbInitAtLate ( + IN OUT AMD_LATE_PARAMS *LateParamsPtr + ) +{ + AGESA_STATUS Status; + Status = GnbLibDispatchFeatures (&GnbLateFeatureTable[0], &LateParamsPtr->StdHeader); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtMid.c new file mode 100644 index 0000000..cae5ff7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtMid.c @@ -0,0 +1,121 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB mid init interface + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "OptionGnb.h" +#include "GnbLibFeatures.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_GNBINITATMID_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern OPTION_GNB_CONFIGURATION GnbMidFeatureTable[]; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GnbInitAtMid ( + IN OUT AMD_MID_PARAMS *MidParamsPtr + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GNB at Mid post + * + * + * + * @param[in,out] MidParamsPtr Pointer to mid configuration params. + * @retval Initialization status. + */ + +AGESA_STATUS +GnbInitAtMid ( + IN OUT AMD_MID_PARAMS *MidParamsPtr + ) +{ + AGESA_STATUS Status; + Status = GnbLibDispatchFeatures (&GnbMidFeatureTable[0], &MidParamsPtr->StdHeader); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtPost.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtPost.c new file mode 100644 index 0000000..a0cf40b --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtPost.c @@ -0,0 +1,176 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB POST init interface + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Gnb.h" +#include "OptionGnb.h" +#include "Ids.h" +#include "GnbLibFeatures.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_GNBINITATPOST_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern OPTION_GNB_CONFIGURATION GnbPostFeatureTable[]; +extern OPTION_GNB_CONFIGURATION GnbPostAfterDramFeatureTable[]; +extern BUILD_OPT_CFG UserOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GnbInitAtPost ( + IN OUT AMD_POST_PARAMS *PostParamsPtr + ); + +VOID +GnbInitDataStructAtPostDef ( + IN OUT GNB_POST_CONFIGURATION *GnbPostConfigPtr, + IN AMD_POST_PARAMS *PostParamsPtr + ); + +AGESA_STATUS +GnbInitAtPostAfterDram ( + IN OUT AMD_POST_PARAMS *PostParamsPtr + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Default constructor of GNB configuration at Env + * + * + * + * @param[in] GnbPostConfigPtr Pointer to GNB POST configuration params. + * @param[in] PostParamsPtr Pointer to POST configuration params. + */ +VOID +GnbInitDataStructAtPostDef ( + IN OUT GNB_POST_CONFIGURATION *GnbPostConfigPtr, + IN AMD_POST_PARAMS *PostParamsPtr + ) +{ + GnbPostConfigPtr->IgpuEnableDisablePolicy = UserOptions.CfgIgpuEnableDisablePolicy; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GNB at Post + * + * + * + * @param[in] PostParamsPtr Pointer to post configuration parameters + * @retval Initialization status. + */ + +AGESA_STATUS +GnbInitAtPost ( + IN OUT AMD_POST_PARAMS *PostParamsPtr + ) +{ + AGESA_STATUS Status; + Status = GnbLibDispatchFeatures (&GnbPostFeatureTable[0], &PostParamsPtr->StdHeader); + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GNB at Post after DRAM init + * + * + * + * @param[in] PostParamsPtr Pointer to post configuration parameters + * @retval Initialization status. + */ + +AGESA_STATUS +GnbInitAtPostAfterDram ( + IN OUT AMD_POST_PARAMS *PostParamsPtr + ) +{ + AGESA_STATUS Status; + Status = GnbLibDispatchFeatures (&GnbPostAfterDramFeatureTable[0], &PostParamsPtr->StdHeader); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtReset.c new file mode 100644 index 0000000..6949cb4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtReset.c @@ -0,0 +1,120 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB reset init interface + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_GNBINITATRESET_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GnbInitAtReset ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GNB at Reset + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GnbInitAtReset ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + + return Status; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtS3Save.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtS3Save.c new file mode 100644 index 0000000..01bb2ce --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtS3Save.c @@ -0,0 +1,121 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB late init interface + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "OptionGnb.h" +#include "GnbLibFeatures.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_GNBINITATS3SAVE_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern OPTION_GNB_CONFIGURATION GnbS3SaveFeatureTable[]; +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GnbInitAtS3Save ( + IN OUT AMD_S3SAVE_PARAMS *AmdS3SaveParams + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GNB at S3 save + * + * + * + * @param[in,out] AmdS3SaveParams Pointer to AMD_S3SAVE_PARAMS. + * @retval Initialization status. + */ + +AGESA_STATUS +GnbInitAtS3Save ( + IN OUT AMD_S3SAVE_PARAMS *AmdS3SaveParams + ) +{ + AGESA_STATUS Status; + Status = GnbLibDispatchFeatures (&GnbS3SaveFeatureTable[0], &AmdS3SaveParams->StdHeader); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Include/Library/GnbTimerLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Include/Library/GnbTimerLib.h new file mode 100644 index 0000000..a212096 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Include/Library/GnbTimerLib.h @@ -0,0 +1,94 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Various PCI service routines. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _GNBTIMERLIB_H_ +#define _GNBTIMERLIB_H_ + +VOID +GnbLibStallS3Save ( + IN UINT32 Microsecond, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbLibStall ( + IN UINT32 Microsecond, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +GnbLibTimeStamp ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Library/GnbTimerLibWrap0/GnbTimerLibWrap0.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Library/GnbTimerLibWrap0/GnbTimerLibWrap0.c new file mode 100644 index 0000000..c1f3023 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Library/GnbTimerLibWrap0/GnbTimerLibWrap0.c @@ -0,0 +1,184 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Various Timer services. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + +#include "AGESA.h" +#include "amdlib.h" +#include "S3SaveState.h" +#include "Gnb.h" +#include "GnbLib.h" +#include "GnbTimerLib.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_LIBRARY_GNBTIMERLIBWRAP0_GNBTIMERLIBWRAP0_FILECODE + + +VOID +GnbLibStallS3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID* Context + ); + +/*----------------------------------------------------------------------------------------*/ +/* + * Stall and save to script table + * + * + * + * @param[in] Microsecond Stall time + * @param[in] StdHeader Standard configuration header + */ + +VOID +GnbLibStallS3Save ( + IN UINT32 Microsecond, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + S3_SAVE_DISPATCH (StdHeader, GnbLibStallS3Script_ID, sizeof (Microsecond), &Microsecond); + GnbLibStall (Microsecond, StdHeader); +} + + +/*----------------------------------------------------------------------------------------*/ +/* + * Stall + * + * + * + * @param[in] Microsecond Stall time + * @param[in] StdHeader Standard configuration header + */ + +VOID +GnbLibStall ( + IN UINT32 Microsecond, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TimeStampStart; + UINT32 TimeStampDelta; + UINT32 TimeStampCurrent; + + TimeStampStart = GnbLibTimeStamp (StdHeader); + do { + TimeStampCurrent = GnbLibTimeStamp (StdHeader); + TimeStampDelta = ((TimeStampCurrent > TimeStampStart) ? (TimeStampCurrent - TimeStampStart) : (0xffffffffull - TimeStampStart + TimeStampCurrent)); + } while (TimeStampDelta < Microsecond); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Stall S3 script + * + * + * + * @param[in] StdHeader Standard configuration header + * @param[in] ContextLength Context Length (not used) + * @param[in] Context pointer to UINT32 number of us + */ +VOID +GnbLibStallS3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID* Context + ) +{ + GnbLibStall (* ((UINT32*) Context), StdHeader); +} +/*----------------------------------------------------------------------------------------*/ +/* + * Time stamp in us + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval TRUE Device is a bridge + * @retval FALSE Device is not a bridge + */ + +UINT32 +GnbLibTimeStamp ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TimeStamp; + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 0, 0xE0), + 0x13080F0, + AccessWidth32, + &TimeStamp, + StdHeader + ); + return TimeStamp; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h new file mode 100644 index 0000000..82842b5 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h @@ -0,0 +1,83 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB register access services. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBCOMMONLIB_H_ +#define _GNBCOMMONLIB_H_ + +#include "GnbLib.h" +#include "GnbLibCpuAcc.h" +#include "GnbLibHeap.h" +#include "GnbLibIoAcc.h" +#include "GnbLibMemAcc.h" +#include "GnbLibPci.h" +#include "GnbLibPciAcc.h" + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c new file mode 100644 index 0000000..e79dfb7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c @@ -0,0 +1,548 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB register access services. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "cpuFamilyTranslation.h" +#include "cpuServices.h" +#include "Gnb.h" +#include "GnbLib.h" +#include "GnbLibIoAcc.h" +#include "GnbLibPciAcc.h" +#include "GnbLibMemAcc.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_SERVICE *ServiceTable; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Read GNB indirect registers + * + * + * + * @param[in] Address PCI address of indirect register + * @param[in] IndirectAddress Offset of indirect register + * @param[in] Width Width + * @param[out] Value Pointer to value + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibPciIndirectRead ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN ACCESS_WIDTH Width, + OUT VOID *Value, + IN VOID *Config + ) +{ + UINT32 IndexOffset; + IndexOffset = LibAmdAccessWidth (Width); + GnbLibPciWrite (Address, Width, &IndirectAddress, Config); + GnbLibPciRead (Address + IndexOffset, Width, Value, Config); +} +/*----------------------------------------------------------------------------------------*/ +/** + * Read GNB indirect registers field + * + * + * + * @param[in] Address PCI address of indirect register + * @param[in] IndirectAddress Offset of indirect register + * @param[in] FieldOffset Field offset + * @param[in] FieldWidth Field width + * @param[out] Value Pointer to value + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibPciIndirectReadField ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + OUT UINT32 *Value, + IN VOID *Config + ) +{ + UINT32 Mask; + GnbLibPciIndirectRead (Address, IndirectAddress, AccessWidth32, Value, Config); + Mask = (1 << FieldWidth) - 1; + *Value = (*Value >> FieldOffset) & Mask; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Write GNB indirect registers + * + * + * + * @param[in] Address PCI address of indirect register + * @param[in] IndirectAddress Offset of indirect register + * @param[in] Width Width + * @param[in] Value Pointer to value + * @param[in] Config Pointer to standard header + */ + +VOID +GnbLibPciIndirectWrite ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN VOID *Config + ) +{ + UINT32 IndexOffset; + IndexOffset = LibAmdAccessWidth (Width); + GnbLibPciWrite (Address, Width, &IndirectAddress, Config); + GnbLibPciWrite (Address + IndexOffset, Width, Value, Config); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Write GNB indirect registers field + * + * + * + * @param[in] Address PCI address of indirect register + * @param[in] IndirectAddress Offset of indirect register + * @param[in] FieldOffset Field offset + * @param[in] FieldWidth Field width + * @param[in] Value Pointer to value + * @param[in] S3Save Save for S3 (TRUE/FALSE) + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibPciIndirectWriteField ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + IN UINT32 Value, + IN BOOLEAN S3Save, + IN VOID *Config + ) +{ + UINT32 Data; + UINT32 Mask; + GnbLibPciIndirectRead (Address, IndirectAddress, AccessWidth32, &Data, Config); + Mask = (1 << FieldWidth) - 1; + Data &= (~(Mask << FieldOffset)); + Data |= ((Value & Mask) << FieldOffset); + GnbLibPciIndirectWrite (Address, IndirectAddress, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Data, Config); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Read/Modify/Write GNB indirect registers field + * + * + * + * @param[in] Address PCI address of indirect register + * @param[in] IndirectAddress Offset of indirect register + * @param[in] Width Width + * @param[in] Mask And Mask + * @param[in] Value Or Value + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibPciIndirectRMW ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN ACCESS_WIDTH Width, + IN UINT32 Mask, + IN UINT32 Value, + IN VOID *Config + ) +{ + UINT32 Data; + GnbLibPciIndirectRead ( + Address, + IndirectAddress, + (Width >= AccessS3SaveWidth8) ? (Width - (AccessS3SaveWidth8 - AccessWidth8)) : Width, + &Data, + Config + ); + Data = (Data & Mask) | Value; + GnbLibPciIndirectWrite (Address, IndirectAddress, Width, &Data, Config); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Read/Modify/Write PCI registers + * + * + * + * @param[in] Address PCI address + * @param[in] Width Access width + * @param[in] Mask AND Mask + * @param[in] Value OR Value + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibPciRMW ( + IN UINT32 Address, + IN ACCESS_WIDTH Width, + IN UINT32 Mask, + IN UINT32 Value, + IN VOID *Config + ) +{ + UINT32 Data; + GnbLibPciRead (Address, Width, &Data, Config); + Data = (Data & Mask) | Value; + GnbLibPciWrite (Address, Width, &Data, Config); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Read/Modify/Write I/O registers + * + * + * + * @param[in] Address I/O Port + * @param[in] Width Access width + * @param[in] Mask AND Mask + * @param[in] Value OR Mask + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibIoRMW ( + IN UINT16 Address, + IN ACCESS_WIDTH Width, + IN UINT32 Mask, + IN UINT32 Value, + IN VOID *Config + ) +{ + UINT32 Data; + GnbLibIoRead (Address, Width, &Data, Config); + Data = (Data & Mask) | Value; + GnbLibIoWrite (Address, Width, &Data, Config); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Indirect IO block read + * + * + * + * @param[in] IndexPort Index Port + * @param[in] DataPort Data Port + * @param[in] Width Access width + * @param[in] IndexAddress Index Address + * @param[in] Count Count + * @param[in] Buffer Buffer + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibIndirectIoBlockRead ( + IN UINT16 IndexPort, + IN UINT16 DataPort, + IN ACCESS_WIDTH Width, + IN UINT32 IndexAddress, + IN UINT32 Count, + IN VOID *Buffer, + IN VOID *Config + ) +{ + UINT32 Index; + + for (Index = IndexAddress; Index < (IndexAddress + Count); Index++) { + GnbLibIoWrite (IndexPort, Width, &Index, Config); + GnbLibIoRead (DataPort, Width, Buffer, Config); + Buffer = (VOID *) ((UINT8 *) Buffer + LibAmdAccessWidth (Width)); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get IOAPIC ID + * + * + * + * @param[in] IoApicBaseAddress IO APIC base address + * @param[in] Config Pointer to standard header + */ +UINT8 +GnbLiGetIoapicId ( + IN UINT64 IoApicBaseAddress, + IN VOID *Config + ) +{ + UINT32 Value; + Value = 0x0; + GnbLibMemWrite (IoApicBaseAddress, AccessWidth32, &Value, Config); + GnbLibMemRead (IoApicBaseAddress + 0x10, AccessWidth32, &Value, Config); + return (UINT8) (Value >> 24); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Read/Modify/Write MMIO registers + * + * + * + * @param[in] Address Physical address + * @param[in] Width Access width + * @param[in] Mask AND Mask + * @param[in] Value OR Value + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibMemRMW ( + IN UINT64 Address, + IN ACCESS_WIDTH Width, + IN UINT32 Mask, + IN UINT32 Value, + IN VOID *Config + ) +{ + UINT32 Data; + GnbLibMemRead (Address, Width, &Data, Config); + Data = (Data & Mask) | Value; + GnbLibMemWrite (Address, Width, &Data, Config); +} + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Claculate power of number + * + * + * + * @param[in] Value Number + * @param[in] Power Power + */ + +UINT32 +GnbLibPowerOf ( + IN UINT32 Value, + IN UINT32 Power + ) +{ + UINT32 Result; + if (Power == 0) { + return 1; + } + Result = Value; + while ((--Power) > 0) { + Result *= Value; + } + return Result; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Search buffer for pattern + * + * + * @param[in] Buf1 Pointer to source buffer which will be subject of search + * @param[in] Buf1Length Length of the source buffer + * @param[in] Buf2 Pointer to pattern buffer + * @param[in] Buf2Length Length of the pattern buffer + * @retval Pointer on first accurance of Buf2 in Buf1 or NULL + */ + +VOID* +GnbLibFind ( + IN UINT8 *Buf1, + IN UINTN Buf1Length, + IN UINT8 *Buf2, + IN UINTN Buf2Length + ) +{ + UINT8 *CurrentBuf1Ptr; + CurrentBuf1Ptr = Buf1; + while (CurrentBuf1Ptr < (Buf1 + Buf1Length - Buf2Length)) { + UINT8 *SourceBufPtr; + UINT8 *PatternBufPtr; + UINTN PatternBufLength; + SourceBufPtr = CurrentBuf1Ptr; + PatternBufPtr = Buf2; + PatternBufLength = Buf2Length; + while ((*SourceBufPtr++ == *PatternBufPtr++) && (PatternBufLength-- != 0)); + if (PatternBufLength == 0) { + return CurrentBuf1Ptr; + } + CurrentBuf1Ptr++; + } + return NULL; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Dump buffer to HDTOUT + * + * + * @param[in] Buffer Buffer pointer + * @param[in] Count Count of data elements + * @param[in] DataWidth DataWidth 1 - Byte; 2 - Word; 3 - DWORD; 4 - QWORD + * @param[in] LineWidth Number of data item per line + */ +VOID +GnbLibDebugDumpBuffer ( + IN VOID *Buffer, + IN UINT32 Count, + IN UINT8 DataWidth, + IN UINT8 LineWidth + ) +{ + UINT32 Index; + UINT32 DataItemCount; + ASSERT (LineWidth != 0); + ASSERT (DataWidth >= 1 && DataWidth <= 4); + DataItemCount = 0; + for (Index = 0; Index < Count; ) { + switch (DataWidth) { + case 1: + IDS_HDT_CONSOLE (GNB_TRACE, "%02x ", *((UINT8 *) Buffer + Index)); + Index += 1; + break; + case 2: + IDS_HDT_CONSOLE (GNB_TRACE, "%04x ", *(UINT16 *) ((UINT8 *) Buffer + Index)); + Index += 2; + break; + case 3: + IDS_HDT_CONSOLE (GNB_TRACE, "%08x ", *(UINT32 *) ((UINT8 *) Buffer + Index)); + Index += 4; + break; + case 4: + IDS_HDT_CONSOLE (GNB_TRACE, "%08x%08", *(UINT32 *) ((UINT8 *) Buffer + Index), *(UINT32 *) ((UINT8 *) Buffer + Index + 4)); + Index += 8; + break; + default: + IDS_HDT_CONSOLE (GNB_TRACE, "ERROR! Incorrect Data Width\n"); + return; + } + if (++DataItemCount >= LineWidth) { + IDS_HDT_CONSOLE (GNB_TRACE, "\n"); + DataItemCount = 0; + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Dump buffer to HDTOUT + * + * + * @param[in] ServiceId Service ID + * @param[in] SocketId Socket ID + * @param[in] ServiceProtocol Service protocol + * @param[in] StdHeader Standard Configuration Header + */ +AGESA_STATUS +GnbLibLocateService ( + IN GNB_SERVICE_ID ServiceId, + IN UINT8 SocketId, + IN VOID **ServiceProtocol, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GNB_SERVICE *SeviceEntry; + CPU_LOGICAL_ID LogicalId; + SeviceEntry = ServiceTable; + GetLogicalIdOfSocket (SocketId, &LogicalId, StdHeader); + while (SeviceEntry != NULL) { + if (SeviceEntry->ServiceId == ServiceId && (LogicalId.Family & SeviceEntry->Family) != 0) { + *ServiceProtocol = SeviceEntry->ServiceProtocol; + return AGESA_SUCCESS; + } + SeviceEntry = SeviceEntry->NextService; + } + return AGESA_UNSUPPORTED; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.h new file mode 100644 index 0000000..ffbeba6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.h @@ -0,0 +1,193 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB register access services. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBLIB_H_ +#define _GNBLIB_H_ + +#define IOC_WRITE_ENABLE 0x80 + +VOID +GnbLibPciIndirectReadField ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + OUT UINT32 *Value, + IN VOID *Config + ); + +VOID +GnbLibPciIndirectWrite ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN VOID *Config + ); + +VOID +GnbLibPciIndirectRead ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN ACCESS_WIDTH Width, + OUT VOID *Value, + IN VOID *Config + ); + +VOID +GnbLibPciIndirectRMW ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN ACCESS_WIDTH Width, + IN UINT32 Mask, + IN UINT32 Value, + IN VOID *Config + ); + +VOID +GnbLibPciIndirectWriteField ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + IN UINT32 Value, + IN BOOLEAN S3Save, + IN VOID *Config + ); + + +VOID +GnbLibPciRMW ( + IN UINT32 Address, + IN ACCESS_WIDTH Width, + IN UINT32 Mask, + IN UINT32 Value, + IN VOID *Config + ); + +VOID +GnbLibIoRMW ( + IN UINT16 Address, + IN ACCESS_WIDTH Width, + IN UINT32 Mask, + IN UINT32 Value, + IN VOID *Config + ); + + +UINT32 +GnbLibPowerOf ( + IN UINT32 Value, + IN UINT32 Power + ); + +VOID* +GnbLibFind ( + IN UINT8 *Buf1, + IN UINTN Buf1Length, + IN UINT8 *Buf2, + IN UINTN Buf2Length + ); + +VOID +GnbLibIndirectIoBlockRead ( + IN UINT16 IndexPort, + IN UINT16 DataPort, + IN ACCESS_WIDTH Width, + IN UINT32 IndexAddress, + IN UINT32 Count, + IN VOID *Buffer, + IN VOID *Config + ); + +UINT8 +GnbLiGetIoapicId ( + IN UINT64 IoApicBaseAddress, + IN VOID *Config + ); + +VOID +GnbLibDebugDumpBuffer ( + IN VOID *Buffer, + IN UINT32 Count, + IN UINT8 DataWidth, + IN UINT8 LineWidth + ); + +AGESA_STATUS +GnbLibLocateService ( + IN GNB_SERVICE_ID ServiceId, + IN UINT8 SocketId, + IN VOID **ServiceProtocol, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c new file mode 100644 index 0000000..39259f7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c @@ -0,0 +1,157 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access various CPU registers. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "Porting.h" +#include "AMD.h" +#include "GnbLibCpuAcc.h" +#include "GnbLibPciAcc.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Read CPU (DCT) indirect registers + * + * + * + * @param[in] Address PCI address of DCT register + * @param[in] IndirectAddress Offset of DCT register + * @param[out] Value Pointer to value + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibCpuPciIndirectRead ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + OUT UINT32 *Value, + IN VOID *Config + ) +{ + UINT32 OffsetRegisterValue; + GnbLibPciWrite (Address, AccessWidth32, &IndirectAddress, Config); + do { + GnbLibPciRead (Address , AccessWidth32, &OffsetRegisterValue, Config); + } while ((OffsetRegisterValue & BIT31) == 0); + GnbLibPciRead (Address + 4, AccessWidth32, Value, Config); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Write CPU (DCT) indirect registers + * + * + * + * @param[in] Address PCI address of DCT register + * @param[in] IndirectAddress Offset of DCT register + * @param[in] Value Pointer to value + * @param[in] Config Pointer to standard header + */ +VOID +GnbLibCpuPciIndirectWrite ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN UINT32 *Value, + IN VOID *Config + ) +{ + UINT32 OffsetRegisterValue; + OffsetRegisterValue = IndirectAddress | BIT30; + GnbLibPciWrite (Address + 4, AccessWidth32, Value, Config); + GnbLibPciWrite (Address, AccessWidth32, &IndirectAddress, Config); + do { + GnbLibPciRead (Address , AccessWidth32, &OffsetRegisterValue, Config); + } while ((OffsetRegisterValue & BIT31) == 0); +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h new file mode 100644 index 0000000..4eea7b8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h @@ -0,0 +1,92 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access various CPU registers. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _CPUACCLIB_H_ +#define _CPUACCLIB_H_ + +VOID +GnbLibCpuPciIndirectWrite ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN UINT32 *Value, + IN VOID *Config + ); + +VOID +GnbLibCpuPciIndirectRead ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + OUT UINT32 *Value, + IN VOID *Config + ); + + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c new file mode 100644 index 0000000..aa243de --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c @@ -0,0 +1,186 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access heap. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "Porting.h" +#include "AMD.h" +#include "amdlib.h" +#include "heapManager.h" +#include "GnbLibPciAcc.h" +#include "GnbLibHeap.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------*/ +/** + * Allocates space for a new buffer in the heap + * + * + * @param[in] Handle Buffer handle + * @param[in] Length Buffer length + * @param[in] StdHeader Standard configuration header + * + * @retval NULL Buffer allocation fail + * + */ + +VOID * +GnbAllocateHeapBuffer ( + IN UINT32 Handle, + IN UINTN Length, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + AllocHeapParams.RequestedBufferSize = (UINT32) Length; + AllocHeapParams.BufferHandle = Handle; + AllocHeapParams.Persist = HEAP_SYSTEM_MEM; + Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader); + if (Status != AGESA_SUCCESS) { + return NULL; + } + return AllocHeapParams.BufferPtr; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Allocates space for a new buffer in the heap and clear it + * + * + * @param[in] Handle Buffer handle + * @param[in] Length Buffer length + * @param[in] StdHeader Standard configuration header + * + * @retval NULL Buffer allocation fail + * + */ + +VOID * +GnbAllocateHeapBufferAndClear ( + IN UINT32 Handle, + IN UINTN Length, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + VOID *Buffer; + Buffer = GnbAllocateHeapBuffer (Handle, Length, StdHeader); + if (Buffer != NULL) { + LibAmdMemFill (Buffer, 0x00, Length, StdHeader); + } + return Buffer; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Locates a previously allocated buffer on the heap. + * + * + * @param[in] Handle Buffer handle + * @param[in] StdHeader Standard configuration header + * + * @retval NULL Buffer handle not found + * + */ + +VOID * +GnbLocateHeapBuffer ( + IN UINT32 Handle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + LOCATE_HEAP_PTR LocHeapParams; + LocHeapParams.BufferHandle = Handle; + Status = HeapLocateBuffer (&LocHeapParams, StdHeader); + if (Status != AGESA_SUCCESS) { + return NULL; + } + return LocHeapParams.BufferPtr; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h new file mode 100644 index 0000000..61a618a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h @@ -0,0 +1,96 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access heap. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _GNBHEAPLIB_H_ +#define _GNBHEAPLIB_H_ + +VOID * +GnbAllocateHeapBuffer ( + IN UINT32 Handle, + IN UINTN Length, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID * +GnbLocateHeapBuffer ( + IN UINT32 Handle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID * +GnbAllocateHeapBufferAndClear ( + IN UINT32 Handle, + IN UINTN Length, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c new file mode 100644 index 0000000..b5341f8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c @@ -0,0 +1,149 @@ +/* $NoKeywords:$ */ +/** + * @file + * +* Service procedure to access I/O registers. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "Porting.h" +#include "AMD.h" +#include "amdlib.h" +#include "GnbLibIoAcc.h" +#include "S3SaveState.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBIOACC_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +/*----------------------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------------------*/ +/** + * Write I/O Port + * + * + * + * @param[in] Address Physical Address + * @param[in] Width Access width + * @param[in] Value Pointer to value + * @param[in] StdHeader Standard configuration header + */ + +VOID +GnbLibIoWrite ( + IN UINT16 Address, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN VOID *StdHeader + ) +{ + if (Width >= AccessS3SaveWidth8) { + S3_SAVE_IO_WRITE (StdHeader, Address, Width, Value); + } + LibAmdIoWrite (Width, Address, Value, StdHeader); +} +/** + * Read IO port + * + * + * + * @param[in] Address Physical Address + * @param[in] Width Access width + * @param[out] Value Pointer to value + * @param[in] StdHeader Standard configuration header + */ + +VOID +GnbLibIoRead ( + IN UINT16 Address, + IN ACCESS_WIDTH Width, + OUT VOID *Value, + IN VOID *StdHeader + ) +{ + LibAmdIoRead (Width, Address, Value, StdHeader); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h new file mode 100644 index 0000000..0066fad --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h @@ -0,0 +1,93 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access I/O registers. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _IOACCLIB_H_ +#define _IOACCLIB_H_ + + +VOID +GnbLibIoWrite ( + IN UINT16 Address, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN VOID *StdHeader + ); + +VOID +GnbLibIoRead ( + IN UINT16 Address, + IN ACCESS_WIDTH Width, + OUT VOID *Value, + IN VOID *StdHeader + ); + + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c new file mode 100644 index 0000000..affdb10 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c @@ -0,0 +1,152 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access MMIO registers. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "Porting.h" +#include "AMD.h" +#include "amdlib.h" +#include "GnbLibMemAcc.h" +#include "S3SaveState.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBMEMACC_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Write Memory/MMIO registers + * + * + * + * @param[in] Address Physical Address + * @param[in] Width Access width + * @param[in] Value Pointer to value + * @param[in] StdHeader Standard configuration header + */ + +VOID +GnbLibMemWrite ( + IN UINT64 Address, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN VOID *StdHeader + ) +{ + if (Width >= AccessS3SaveWidth8) { + S3_SAVE_MEM_WRITE (StdHeader, Address, Width, Value); + } + LibAmdMemWrite (Width, Address, Value, StdHeader); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Read Memory/MMIO registers + * + * + * + * @param[in] Address Physical Address + * @param[in] Width Access width + * @param[out] Value Pointer to value + * @param[in] StdHeader Standard configuration header + */ + +VOID +GnbLibMemRead ( + IN UINT64 Address, + IN ACCESS_WIDTH Width, + OUT VOID *Value, + IN VOID *StdHeader + ) +{ + LibAmdMemRead (Width, Address, Value, StdHeader); +} + + + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h new file mode 100644 index 0000000..e0179d2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h @@ -0,0 +1,100 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access MMIO registers. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _MEMACCLIB_H_ +#define _MEMACCLIB_H_ + +VOID +GnbLibMemWrite ( + IN UINT64 Address, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN VOID *StdHeader + ); + +VOID +GnbLibMemRead ( + IN UINT64 Address, + IN ACCESS_WIDTH Width, + OUT VOID *Value, + IN VOID *StdHeader + ); + +VOID +GnbLibMemRMW ( + IN UINT64 Address, + IN ACCESS_WIDTH Width, + IN UINT32 Mask, + IN UINT32 Value, + IN VOID *Config + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c new file mode 100644 index 0000000..1353342 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c @@ -0,0 +1,430 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Various PCI service routines. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + +#include "AGESA.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbLibPciAcc.h" +#include "GnbLibPci.h" +#include "GnbLib.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE + +/*----------------------------------------------------------------------------------------*/ +/* + * Check if device present + * + * + * + * @param[in] Address PCI address (as described in PCI_ADDR) + * @param[in] StdHeader Standard configuration header + * @retval TRUE Device is present + * @retval FALSE Device is not present + */ + +BOOLEAN +GnbLibPciIsDevicePresent ( + IN UINT32 Address, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 DeviceId; + GnbLibPciRead (Address, AccessWidth32, &DeviceId, StdHeader); + if (DeviceId == 0xffffffff) { + return FALSE; + } else { + return TRUE; + } +} + + +/*----------------------------------------------------------------------------------------*/ +/* + * Check if device is bridge + * + * + * + * @param[in] Address PCI address (as described in PCI_ADDR) + * @param[in] StdHeader Standard configuration header + * @retval TRUE Device is a bridge + * @retval FALSE Device is not a bridge + */ + +BOOLEAN +GnbLibPciIsBridgeDevice ( + IN UINT32 Address, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 Header; + GnbLibPciRead (Address | 0xe, AccessWidth8, &Header, StdHeader); + if ((Header & 0x7f) == 1) { + return TRUE; + } else { + return FALSE; + } +} + +/*----------------------------------------------------------------------------------------*/ +/* + * Check if device is multifunction + * + * + * + * @param[in] Address PCI address (as described in PCI_ADDR) + * @param[in] StdHeader Standard configuration header + * @retval TRUE Device is a multifunction device. + * @retval FALSE Device is a single function device. + * + */ +BOOLEAN +GnbLibPciIsMultiFunctionDevice ( + IN UINT32 Address, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 Header; + GnbLibPciRead (Address | 0xe, AccessWidth8, &Header, StdHeader); + if ((Header & 0x80) != 0) { + return TRUE; + } else { + return FALSE; + } +} + +/*----------------------------------------------------------------------------------------*/ +/* + * Check if device is PCIe device + * + * + * + * @param[in] Address PCI address (as described in PCI_ADDR) + * @param[in] StdHeader Standard configuration header + * @retval TRUE Device is a PCIe device + * @retval FALSE Device is not a PCIe device + * + */ + +BOOLEAN +GnbLibPciIsPcieDevice ( + IN UINT32 Address, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + if (GnbLibFindPciCapability (Address, PCIE_CAP_ID, StdHeader) != 0 ) { + return TRUE; + } else { + return FALSE; + } +} + + +/*----------------------------------------------------------------------------------------*/ +/* + * Find PCI capability pointer + * + * + * + * @param[in] Address PCI address (as described in PCI_ADDR) + * @param[in] CapabilityId PCI capability ID + * @param[in] StdHeader Standard configuration header + * @retval Register address of capability pointer + * + */ + +UINT8 +GnbLibFindPciCapability ( + IN UINT32 Address, + IN UINT8 CapabilityId, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 CapabilityPtr; + UINT8 CurrentCapabilityId; + CapabilityPtr = 0x34; + if (!GnbLibPciIsDevicePresent (Address, StdHeader)) { + return 0; + } + while (CapabilityPtr != 0) { + GnbLibPciRead (Address | CapabilityPtr, AccessWidth8 , &CapabilityPtr, StdHeader); + if (CapabilityPtr != 0) { + GnbLibPciRead (Address | CapabilityPtr , AccessWidth8 , &CurrentCapabilityId, StdHeader); + if (CurrentCapabilityId == CapabilityId) { + break; + } + CapabilityPtr++; + } + } + return CapabilityPtr; +} +/*----------------------------------------------------------------------------------------*/ +/* + * Find PCIe extended capability pointer + * + * + * + * @param[in] Address PCI address (as described in PCI_ADDR) + * @param[in] ExtendedCapabilityId Extended PCIe capability ID + * @param[in] StdHeader Standard configuration header + * @retval Register address of extended capability pointer + * + */ + +#if 0 /* Not used */ +UINT16 +GnbLibFindPcieExtendedCapability ( + IN UINT32 Address, + IN UINT16 ExtendedCapabilityId, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT16 CapabilityPtr; + UINT32 ExtendedCapabilityIdBlock; + if (GnbLibPciIsPcieDevice (Address, StdHeader)) { + GnbLibPciRead (Address | 0x100 , AccessWidth32 , &ExtendedCapabilityIdBlock, StdHeader); + if ((ExtendedCapabilityIdBlock != 0) && ((UINT16)ExtendedCapabilityIdBlock != 0xffff)) { + do { + CapabilityPtr = (UINT16) ((ExtendedCapabilityIdBlock >> 20) & 0xfff); + if ((UINT16)ExtendedCapabilityIdBlock == ExtendedCapabilityId) { + return CapabilityPtr; + } + GnbLibPciRead (Address | CapabilityPtr , AccessWidth32 , &ExtendedCapabilityIdBlock, StdHeader); + } while (((ExtendedCapabilityIdBlock >> 20) & 0xfff) != 0); + } + } + return 0; +} +#endif +/*----------------------------------------------------------------------------------------*/ +/* + * Scan range of device on PCI bus. + * + * + * + * @param[in] Start Start address to start scan from + * @param[in] End End address of scan + * @param[in] ScanData Supporting data + * + */ +/*----------------------------------------------------------------------------------------*/ +VOID +GnbLibPciScan ( + IN PCI_ADDR Start, + IN PCI_ADDR End, + IN GNB_PCI_SCAN_DATA *ScanData + ) +{ + UINTN Bus; + UINTN Device; + UINTN LastDevice; + UINTN Function; + UINTN LastFunction; + PCI_ADDR PciDevice; + SCAN_STATUS Status; + + for (Bus = Start.Address.Bus; Bus <= End.Address.Bus; Bus++) { + Device = (Bus == Start.Address.Bus) ? Start.Address.Device : 0x00; + LastDevice = (Bus == End.Address.Bus) ? End.Address.Device : 0x1F; + for ( ; Device <= LastDevice; Device++) { + if ((Bus == Start.Address.Bus) && (Device == Start.Address.Device)) { + Function = Start.Address.Function; + } else { + Function = 0x0; + } + PciDevice.AddressValue = MAKE_SBDFO (0, Bus, Device, Function, 0); + if (!GnbLibPciIsDevicePresent (PciDevice.AddressValue, ScanData->StdHeader)) { + continue; + } + if (GnbLibPciIsMultiFunctionDevice (PciDevice.AddressValue, ScanData->StdHeader)) { + if ((Bus == End.Address.Bus) && (Device == End.Address.Device)) { + LastFunction = Start.Address.Function; + } else { + LastFunction = 0x7; + } + } else { + LastFunction = 0x0; + } + for ( ; Function <= LastFunction; Function++) { + PciDevice.AddressValue = MAKE_SBDFO (0, Bus, Device, Function, 0); + if (GnbLibPciIsDevicePresent (PciDevice.AddressValue, ScanData->StdHeader)) { + Status = ScanData->GnbScanCallback (PciDevice, ScanData); + if ((Status & SCAN_SKIP_FUNCTIONS) != 0) { + Function = LastFunction + 1; + } + if ((Status & SCAN_SKIP_DEVICES) != 0) { + Device = LastDevice + 1; + } + if ((Status & SCAN_SKIP_BUSES) != 0) { + Bus = End.Address.Bus + 1; + } + } + } + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Scan all subordinate buses + * + * + * @param[in] Bridge PCI bridge address + * @param[in,out] ScanData Scan configuration data + * + */ +VOID +GnbLibPciScanSecondaryBus ( + IN PCI_ADDR Bridge, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ) +{ + PCI_ADDR StartRange; + PCI_ADDR EndRange; + UINT8 SecondaryBus; + GnbLibPciRead (Bridge.AddressValue | 0x19, AccessWidth8, &SecondaryBus, ScanData->StdHeader); + if (SecondaryBus != 0) { + StartRange.AddressValue = MAKE_SBDFO (0, SecondaryBus, 0, 0, 0); + EndRange.AddressValue = MAKE_SBDFO (0, SecondaryBus, 0x1f, 0x7, 0); + GnbLibPciScan (StartRange, EndRange, ScanData); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get PCIe device type + * + * + * + * @param[in] Device PCI address of device. + * @param[in] StdHeader Northbridge configuration structure pointer. + * + * @retval PCIE_DEVICE_TYPE + */ + /*----------------------------------------------------------------------------------------*/ + +PCIE_DEVICE_TYPE +GnbLibGetPcieDeviceType ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 PcieCapPtr; + UINT8 Value; + + PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader); + if (PcieCapPtr != 0) { + GnbLibPciRead (Device.AddressValue | (PcieCapPtr + 0x2) , AccessWidth8, &Value, StdHeader); + return Value >> 4; + } + return PcieNotPcieDevice; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Save config space area + * + * + * + * @param[in] Address PCI address of device. + * @param[in] StartRegisterAddress Start register address. + * @param[in] EndRegisterAddress End register address. + * @param[in] Width Acess width. + * @param[in] StdHeader Standard header. + * + */ + /*----------------------------------------------------------------------------------------*/ + +VOID +GnbLibS3SaveConfigSpace ( + IN UINT32 Address, + IN UINT16 StartRegisterAddress, + IN UINT16 EndRegisterAddress, + IN ACCESS_WIDTH Width, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT16 Index; + UINT16 Delta; + UINT16 Length; + Length = (StartRegisterAddress < EndRegisterAddress) ? (EndRegisterAddress - StartRegisterAddress) : (StartRegisterAddress - EndRegisterAddress); + Delta = LibAmdAccessWidth (Width); + for (Index = 0; Index <= Length; Index = Index + Delta) { + GnbLibPciRMW ( + Address | ((StartRegisterAddress < EndRegisterAddress) ? (StartRegisterAddress + Index) : (StartRegisterAddress - Index)), + Width, + 0xffffffff, + 0x0, + StdHeader + ); + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h new file mode 100644 index 0000000..a0825cf --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h @@ -0,0 +1,186 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Various PCI service routines. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _GNBLIBPCI_H_ +#define _GNBLIBPCI_H_ + +#define PCIE_CAP_ID 0x10 +#define IOMMU_CAP_ID 0x0F + +/// PCIe device type +typedef enum { + PcieDeviceEndPoint, ///< Endpoint + PcieDeviceLegacyEndPoint, ///< Legacy endpoint + PcieDeviceRootComplex = 4, ///< Root complex + PcieDeviceUpstreamPort, ///< Upstream port + PcieDeviceDownstreamPort, ///< Downstream Port + PcieDevicePcieToPcix, ///< PCIe to PCI/PCIx bridge + PcieDevicePcixToPcie, ///< PCI/PCIx to PCIe bridge + PcieNotPcieDevice = 0xff ///< unknown device +} PCIE_DEVICE_TYPE; + +typedef UINT32 SCAN_STATUS; + +#define SCAN_SKIP_FUNCTIONS 0x1 +#define SCAN_SKIP_DEVICES 0x2 +#define SCAN_SKIP_BUSES 0x4 +#define SCAN_SUCCESS 0x0 + +// Forward declaration needed for multi-structure mutual references +AGESA_FORWARD_DECLARATION (GNB_PCI_SCAN_DATA); + +typedef SCAN_STATUS (*GNB_SCAN_CALLBACK) ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ); + +///Scan supporting data +struct _GNB_PCI_SCAN_DATA { + GNB_SCAN_CALLBACK GnbScanCallback; ///< Callback for each found device + AMD_CONFIG_PARAMS *StdHeader; ///< Standard configuration header +}; + +#define PCIE_CAP_ID 0x10 +#define PCIE_LINK_CAP_REGISTER 0x0C +#define PCIE_LINK_CTRL_REGISTER 0x10 +#define PCIE_DEVICE_CAP_REGISTER 0x04 +#define PCIE_DEVICE_CTRL_REGISTER 0x08 +#define PCIE_ASPM_L1_SUPPORT_CAP BIT11 + +#define MAX_PAYLOAD_128 0x0 ///< Max allowed payload size 128 bytes +#define MAX_PAYLOAD_256 0x1 ///< Max allowed payload size 256 bytes +#define MAX_PAYLOAD_512 0x2 ///< Max allowed payload size 512 bytes +#define MAX_PAYLOAD_1024 0x3 ///< Max allowed payload size 1024 bytes +#define MAX_PAYLOAD_2048 0x4 ///< Max allowed payload size 2048 bytes +#define MAX_PAYLOAD_4096 0x5 ///< Max allowed payload size 4096 bytes +#define MAX_PAYLOAD 0x5 ///< Max allowed payload size according to spec is 101b (4096 bytes) + +BOOLEAN +GnbLibPciIsDevicePresent ( + IN UINT32 Address, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GnbLibPciIsBridgeDevice ( + IN UINT32 Address, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GnbLibPciIsMultiFunctionDevice ( + IN UINT32 Address, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GnbLibPciIsPcieDevice ( + IN UINT32 Address, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +GnbLibFindPciCapability ( + IN UINT32 Address, + IN UINT8 CapabilityId, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbLibPciScan ( + IN PCI_ADDR Start, + IN PCI_ADDR End, + IN GNB_PCI_SCAN_DATA *ScanData + ); + +VOID +GnbLibPciScanSecondaryBus ( + IN PCI_ADDR Bridge, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ); + +PCIE_DEVICE_TYPE +GnbLibGetPcieDeviceType ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbLibS3SaveConfigSpace ( + IN UINT32 Address, + IN UINT16 StartRegisterAddress, + IN UINT16 EndRegisterAddress, + IN ACCESS_WIDTH Width, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c new file mode 100644 index 0000000..ccb2078 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c @@ -0,0 +1,183 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access PCI config space registers + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "Porting.h" +#include "AMD.h" +#include "amdlib.h" +#include "GnbLibPciAcc.h" +#include "S3SaveState.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCIACC_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Write PCI registers + * + * + * + * @param[in] Address PCI address (as presented in PCI_ADDR.AddressValue) + * @param[in] Width Access width + * @param[in] Value Pointer to value + * @param[in] StdHeader Pointer to standard header + */ +VOID +GnbLibPciWrite ( + IN UINT32 Address, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + PciAddress.AddressValue = Address; + if (Width >= AccessS3SaveWidth8) { + S3_SAVE_PCI_WRITE (StdHeader, PciAddress, Width, Value); + } + LibAmdPciWrite (Width, PciAddress, Value, StdHeader); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Read PCI registers + * + * + * + * @param[in] Address PCI address (as presented in PCI_ADDR.AddressValue) + * @param[in] Width Access width + * @param[out] Value Pointer to value + * @param[in] StdHeader Pointer to standard header + */ + +VOID +GnbLibPciRead ( + IN UINT32 Address, + IN ACCESS_WIDTH Width, + OUT VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + PciAddress.AddressValue = Address; + LibAmdPciRead (Width, PciAddress, Value, StdHeader); +} + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Poll PCI reg + * + * + * + * @param[in] Address PCI address (as presented in PCI_ADDR.AddressValue) + * @param[in] Width Access width + * @param[in] Data Data to compare + * @param[in] DataMask AND mask + * @param[in] StdHeader Standard configuration header + */ + +VOID +GnbLibPciPoll ( + IN UINT32 Address, + IN ACCESS_WIDTH Width, + IN VOID *Data, + IN VOID *DataMask, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + PciAddress.AddressValue = Address; + if (Width >= AccessS3SaveWidth8) { + S3_SAVE_PCI_POLL (StdHeader, PciAddress, Width, Data, DataMask, 0xffffffff); + } + LibAmdPciPoll (Width, PciAddress, Data, DataMask, 0xffffffff, StdHeader); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h new file mode 100644 index 0000000..a921bf1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h @@ -0,0 +1,100 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to access PCI config space registers + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBLIBPCIACC_H_ +#define _GNBLIBPCIACC_H_ + +VOID +GnbLibPciWrite ( + IN UINT32 Address, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbLibPciRead ( + IN UINT32 Address, + IN ACCESS_WIDTH Width, + OUT VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbLibPciPoll ( + IN UINT32 Address, + IN ACCESS_WIDTH Width, + IN VOID *Data, + IN VOID *DataMask, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c new file mode 100644 index 0000000..d6936d4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c @@ -0,0 +1,542 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific function translation + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBPCIETRANSLATION_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +/*----------------------------------------------------------------------------------------*/ +/** + * Configure engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] EngineType Engine Type + * @param[in] ConfigurationId Configuration ID + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_UNSUPPORTED No more configuration available for given engine type + * @retval AGESA_ERROR Requested configuration not supported + */ +AGESA_STATUS +PcieFmConfigureEnginesLaneAllocation ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIE_ENGINE_TYPE EngineType, + IN UINT8 ConfigurationId + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_CONFIG_SERVICES *PcieConfigService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Wrapper->Header); + Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieConfigService->PcieFmConfigureEnginesLaneAllocation (Wrapper, EngineType, ConfigurationId); + } + return AGESA_ERROR; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get core configuration value + * + * + * + * @param[in] Wrapper Pointer to internal configuration data area + * @param[in] CoreId Core ID + * @param[in] ConfigurationSignature Configuration signature + * @param[out] ConfigurationValue Configuration value (for core configuration) + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_ERROR Core configuration value can not be determined + */ +AGESA_STATUS +PcieFmGetCoreConfigurationValue ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 CoreId, + IN UINT64 ConfigurationSignature, + IN UINT8 *ConfigurationValue + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_INIT_SERVICES *PcieInitService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Wrapper->Header); + Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieInitService->PcieFmGetCoreConfigurationValue (Wrapper, CoreId, ConfigurationSignature, ConfigurationValue); + } + return AGESA_ERROR; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if engine can be remapped to Device/function number requested by user + * defined engine descriptor + * + * Function only called if requested device/function does not much native device/function + * + * @param[in] PortDescriptor Pointer to user defined engine descriptor + * @param[in] Engine Pointer engine configuration + * @retval TRUE Descriptor can be mapped to engine + * @retval FALSE Descriptor can NOT be mapped to engine + */ + +BOOLEAN +PcieFmCheckPortPciDeviceMapping ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_CONFIG_SERVICES *PcieConfigService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); + Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieConfigService->PcieFmCheckPortPciDeviceMapping (PortDescriptor, Engine); + } + return FALSE; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get core configuration string + * + * Debug function for logging configuration + * + * @param[in] Wrapper Pointer to internal configuration data area + * @param[in] ConfigurationValue Configuration value + * @retval Configuration string + */ + +CONST CHAR8* +PcieFmDebugGetCoreConfigurationString ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationValue + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_DEBUG_SERVICES *PcieDebugService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); + Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (VOID **)&PcieDebugService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieDebugService->PcieFmDebugGetCoreConfigurationString (Wrapper, ConfigurationValue); + } + return " !!! Something Wrong !!!"; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get wrapper name + * + * Debug function for logging wrapper name + * + * @param[in] Wrapper Pointer to internal configuration data area + * @retval Wrapper Name string + */ + +CONST CHAR8* +PcieFmDebugGetWrapperNameString ( + IN PCIe_WRAPPER_CONFIG *Wrapper + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_DEBUG_SERVICES *PcieDebugService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); + Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (VOID **)&PcieDebugService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieDebugService->PcieFmDebugGetWrapperNameString (Wrapper); + } + return " !!! Something Wrong !!!"; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get register address name + * + * Debug function for logging register trace + * + * @param[in] Silicon Silicon config descriptor + * @param[in] AddressFrame Address Frame + * @retval Register address name + */ +CONST CHAR8* +PcieFmDebugGetHostRegAddressSpaceString ( + IN PCIe_SILICON_CONFIG *Silicon, + IN UINT16 AddressFrame + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_DEBUG_SERVICES *PcieDebugService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Silicon->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); + Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (VOID **)&PcieDebugService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieDebugService->PcieFmDebugGetHostRegAddressSpaceString (Silicon, AddressFrame); + } + return " !!! Something Wrong !!!"; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if the lane can be muxed by link width requested by user + * defined engine descriptor + * + * Check Engine StartCoreLane could be aligned by user requested link width(x1, x2, x4, x8, x16). + * Check Engine StartCoreLane could be aligned by user requested link width x2. + * + * @param[in] PortDescriptor Pointer to user defined engine descriptor + * @param[in] Engine Pointer engine configuration + * @retval TRUE Lane can be muxed + * @retval FALSE Lane can NOT be muxed + */ + +BOOLEAN +PcieFmCheckPortPcieLaneCanBeMuxed ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_CONFIG_SERVICES *PcieConfigService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); + Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieConfigService->PcieFmCheckPortPcieLaneCanBeMuxed (PortDescriptor, Engine); + } + return FALSE; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Map engine to specific PCI device address + * + * + * + * @param[in] Engine Pointer to engine configuration + * @retval AGESA_ERROR Fail to map PCI device address + * @retval AGESA_SUCCESS Successfully allocate PCI address + */ + +AGESA_STATUS +PcieFmMapPortPciAddress ( + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_CONFIG_SERVICES *PcieConfigService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); + Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieConfigService->PcieFmMapPortPciAddress (Engine); + } + return AGESA_ERROR; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get total number of silicons/wrappers/engines for this complex + * + * + * + * @param[in] SocketId Socket ID. + * @param[out] Length Length of configuration info block + * @param[out] StdHeader Standard Configuration Header + * @retval AGESA_SUCCESS Configuration data length is correct + */ +AGESA_STATUS +PcieFmGetComplexDataLength ( + IN UINT8 SocketId, + OUT UINTN *Length, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + PCIe_FAM_CONFIG_SERVICES *PcieConfigService; + Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (VOID **)&PcieConfigService, StdHeader); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieConfigService->PcieFmGetComplexDataLength (SocketId, Length, StdHeader); + } + return Status; +} + + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Build configuration + * + * + * @param[in] SocketId Socket ID. + * @param[out] Buffer Pointer to buffer to build internal complex data structure + * @param[out] StdHeader Standard configuration header. + * @retval AGESA_SUCCESS Configuration data build successfully + */ +AGESA_STATUS +PcieFmBuildComplexConfiguration ( + IN UINT8 SocketId, + OUT VOID *Buffer, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + PCIe_FAM_CONFIG_SERVICES *PcieConfigService; + Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (VOID **)&PcieConfigService, StdHeader); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieConfigService->PcieFmBuildComplexConfiguration (SocketId, Buffer, StdHeader); + } + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get max link speed capability supported by this port + * + * + * + * @param[in] Flags See Flags PCIE_PORT_GEN_CAP_BOOT / PCIE_PORT_GEN_CAP_MAX + * @param[in] Engine Pointer to engine config descriptor + * @retval PcieGen1/PcieGen2 Max supported link gen capability + */ +PCIE_LINK_SPEED_CAP +PcieFmGetLinkSpeedCap ( + IN UINT32 Flags, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_INIT_SERVICES *PcieInitService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); + Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieInitService->PcieFmGetLinkSpeedCap (Flags, Engine); + } + return PcieGen1; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get native PHY lane bitmap + * + * + * @param[in] PhyLaneBitmap Package PHY lane bitmap + * @param[in] Engine Standard configuration header. + * @retval Native PHY lane bitmap + */ +UINT32 +PcieFmGetNativePhyLaneBitmap ( + IN UINT32 PhyLaneBitmap, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_FAM_INIT_SERVICES *PcieInitService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); + Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieInitService->PcieFmGetNativePhyLaneBitmap (PhyLaneBitmap, Engine); + } + return 0x0; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set current link speed + * + * + * @param[in] LinkSpeedCapability Link Speed Capability + * @param[in] Engine Pointer to engine configuration descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +PcieFmSetLinkSpeedCap ( + IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_FAM_INIT_SERVICES *PcieInitService; + + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); + Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + PcieInitService->PcieFmSetLinkSpeedCap (LinkSpeedCapability, Engine, Pcie); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get SB port info + * + * + * @param[out] SocketId Socket ID + * @param[out] SbPort Pointer to SB configuration descriptor + * @param[in] StdHeader Standard configuration header. + * @retval AGESA_SUCCESS SB configuration determined successfully + */ +AGESA_STATUS +PcieFmGetSbConfigInfo ( + IN UINT8 SocketId, + OUT PCIe_PORT_DESCRIPTOR *SbPort, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + PCIe_FAM_CONFIG_SERVICES *PcieConfigService; + Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (VOID **)&PcieConfigService, StdHeader); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return PcieConfigService->PcieFmGetSbConfigInfo (SocketId, SbPort, StdHeader); + } + return Status; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c new file mode 100644 index 0000000..2ac05a2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c @@ -0,0 +1,157 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific function translation + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbFamServices.h" +#include "GnbCommonLib.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBTRANSLATION_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if IOMMU unit present and enabled + * + * + * + * + * @param[in] GnbHandle Gnb handle + * @param[in] StdHeader Standard configuration header + * + */ +BOOLEAN +GnbFmCheckIommuPresent ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + GNB_FAM_IOMMU_SERVICES *GnbIommuConfigService; + Status = GnbLibLocateService (GnbIommuService, GnbGetSocketId (GnbHandle), (VOID **)&GnbIommuConfigService, StdHeader); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return GnbIommuConfigService->GnbFmCheckIommuPresent (GnbHandle, StdHeader); + } + return FALSE; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Create IVRS entry + * + * + * @param[in] GnbHandle Gnb handle + * @param[in] Type Entry type + * @param[in] Ivrs IVRS table pointer + * @param[in] StdHeader Standard configuration header + * + */ + +AGESA_STATUS +GnbFmCreateIvrsEntry ( + IN GNB_HANDLE *GnbHandle, + IN IVRS_BLOCK_TYPE Type, + IN VOID *Ivrs, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + GNB_FAM_IOMMU_SERVICES *GnbIommuConfigService; + Status = GnbLibLocateService (GnbIommuService, GnbGetSocketId (GnbHandle), (VOID **)&GnbIommuConfigService, StdHeader); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + return GnbIommuConfigService->GnbFmCreateIvrsEntry (GnbHandle, Type, Ivrs, StdHeader); + } + return Status; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c new file mode 100644 index 0000000..e142ac7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c @@ -0,0 +1,160 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize GFX configuration data structure. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbCommonLib.h" +#include "GnbGfxConfig.h" +#include "GfxConfigLib.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGENV_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GfxConfigEnvInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Update GFX config info at ENV + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS Always succeeds + */ + +AGESA_STATUS +GfxConfigEnvInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + AMD_ENV_PARAMS *EnvParamsPtr; + GFX_PLATFORM_CONFIG *Gfx; + AGESA_STATUS Status; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigEnvInterface Enter\n"); + Status = GfxLocateConfigData (StdHeader, &Gfx); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + EnvParamsPtr = (AMD_ENV_PARAMS *) StdHeader; + Gfx->Gnb3dStereoPinIndex = EnvParamsPtr->GnbEnvConfiguration.Gnb3dStereoPinIndex; + Gfx->LvdsSpreadSpectrum = EnvParamsPtr->GnbEnvConfiguration.LvdsSpreadSpectrum; + Gfx->LvdsSpreadSpectrumRate = EnvParamsPtr->GnbEnvConfiguration.LvdsSpreadSpectrumRate; + Gfx->LvdsPowerOnSeqDigonToDe = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqDigonToDe; + Gfx->LvdsPowerOnSeqDeToVaryBl = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqDeToVaryBl; + Gfx->LvdsPowerOnSeqDeToDigon = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqDeToDigon; + Gfx->LvdsPowerOnSeqVaryBlToDe = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqVaryBlToDe; + Gfx->LvdsPowerOnSeqOnToOffDelay = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqOnToOffDelay; + Gfx->LvdsPowerOnSeqVaryBlToBlon = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqVaryBlToBlon; + Gfx->LvdsPowerOnSeqBlonToVaryBl = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqBlonToVaryBl; + Gfx->LvdsMaxPixelClockFreq = EnvParamsPtr->GnbEnvConfiguration.LvdsMaxPixelClockFreq; + Gfx->LcdBitDepthControlValue = EnvParamsPtr->GnbEnvConfiguration.LcdBitDepthControlValue; + Gfx->Lvds24bbpPanelMode = EnvParamsPtr->GnbEnvConfiguration.Lvds24bbpPanelMode; + Gfx->LvdsMiscControl.Value = EnvParamsPtr->GnbEnvConfiguration.LvdsMiscControl.Value; + Gfx->PcieRefClkSpreadSpectrum = EnvParamsPtr->GnbEnvConfiguration.PcieRefClkSpreadSpectrum; + Gfx->GnbRemoteDisplaySupport = EnvParamsPtr->GnbEnvConfiguration.GnbRemoteDisplaySupport; + Gfx->gfxplmcfg0 = EnvParamsPtr->GnbEnvConfiguration.LvdsMiscVoltAdjustment; + Gfx->DisplayMiscControl.Value = EnvParamsPtr->GnbEnvConfiguration.DisplayMiscControl.Value; + GfxGetUmaInfo (&Gfx->UmaInfo, StdHeader); + } + GNB_DEBUG_CODE ( + GfxConfigDebugDump (Gfx); + ); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigEnvInterface Exit [0x%x]\n", Status); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c new file mode 100644 index 0000000..cdf4771 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c @@ -0,0 +1,259 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize GFX configuration data structure. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GfxConfigLib.h" +#include "GnbCommonLib.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGLIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Enable GMM Access + * + * + * + * @param[in,out] Gfx Pointer to GFX configuration + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GfxEnableGmmAccess ( + IN OUT GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT32 Value; + + if (!GnbLibPciIsDevicePresent (Gfx->GfxPciAddress.AddressValue, GnbLibGetHeader (Gfx))) { + IDS_ERROR_TRAP; + return AGESA_ERROR; + } + + // Check if base address for GMM allocated + GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x18, AccessWidth32, &Gfx->GmmBase, GnbLibGetHeader (Gfx)); + if (Gfx->GmmBase == 0) { + IDS_ERROR_TRAP; + return AGESA_ERROR; + } + // Check if base address for FB allocated + GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x10, AccessWidth32, &Value, GnbLibGetHeader (Gfx)); + if ((Value & 0xfffffff0) == 0) { + IDS_ERROR_TRAP; + return AGESA_ERROR; + } + //Push CPU MMIO pci config to S3 script + GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 0x18, 1, 0), 0xBC, 0x80, AccessS3SaveWidth32, GnbLibGetHeader (Gfx)); + // Turn on memory decoding on APC to enable access to GMM register space + if (Gfx->GfxControllerMode == GfxControllerLegacyBridgeMode) { + GnbLibPciRMW (MAKE_SBDFO (0, 0, 1, 0, 0x4), AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx)); + //Push APC pci config to S3 script + GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 1, 0, 0), 0x2C, 0x18, AccessS3SaveWidth32, GnbLibGetHeader (Gfx)); + GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 1, 0, 0), 0x4, 0x4, AccessS3SaveWidth16, GnbLibGetHeader (Gfx)); + } + // Turn on memory decoding on GFX to enable access to GMM register space + GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx)); + //Push iGPU pci config to S3 script + GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x24, 0x10, AccessS3SaveWidth32, GnbLibGetHeader (Gfx)); + GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x04, 0x04, AccessS3SaveWidth16, GnbLibGetHeader (Gfx)); + return AGESA_SUCCESS; +} + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get UMA info + * + * UMA info stored on heap by memory module + * + * @param[out] UmaInfo Pointer to UMA info structure + * @param[in] StdHeader Standard configuration header + */ + +VOID +GfxGetUmaInfo ( + OUT UMA_INFO *UmaInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UMA_INFO *MemUmaInfo; + + MemUmaInfo = GnbLocateHeapBuffer (AMD_UMA_INFO_HANDLE, StdHeader); + if (MemUmaInfo == NULL) { + LibAmdMemFill (UmaInfo, 0x00, sizeof (UMA_INFO), StdHeader); + UmaInfo->UmaMode = UMA_NONE; + } else { + LibAmdMemCopy (UmaInfo, MemUmaInfo, sizeof (UMA_INFO), StdHeader); + if ((UmaInfo->UmaBase == 0) || (UmaInfo->UmaSize == 0)) { + UmaInfo->UmaMode = UMA_NONE; + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Locate UMA configuration data + * + * + * + * @param[in] StdHeader Standard configuration header + * @param[in,out] Gfx Pointer to GFX configuration + * @retval AGESA_STATUS Data located + * @retval AGESA_FATA Data not found + */ + +AGESA_STATUS +GfxLocateConfigData ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT GFX_PLATFORM_CONFIG **Gfx + ) +{ + *Gfx = GnbLocateHeapBuffer (AMD_GFX_PLATFORM_CONFIG_HANDLE, StdHeader); + if (*Gfx == NULL) { + IDS_ERROR_TRAP; + return AGESA_FATAL; + } + (*Gfx)->StdHeader = /* (PVOID) */(UINT32) StdHeader; + return AGESA_SUCCESS; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Debug dump + * + * + * + * @param[in] Gfx Pointer to GFX configuration + */ + +VOID +GfxConfigDebugDump ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + IDS_HDT_CONSOLE (GFX_MISC, "<-------------- GFX Config Start ------------->\n"); + IDS_HDT_CONSOLE (GFX_MISC, " HD Audio - %s\n", (Gfx->GnbHdAudio == 0) ? "Disabled" : "Enabled"); + IDS_HDT_CONSOLE (GFX_MISC, " DynamicRefreshRate - 0x%x\n", Gfx->DynamicRefreshRate); + IDS_HDT_CONSOLE (GFX_MISC, " LcdBackLightControl - 0x%x\n", Gfx->LcdBackLightControl); + IDS_HDT_CONSOLE (GFX_MISC, " AbmSupport - %s\n", (Gfx->AbmSupport == 0) ? "Disabled" : "Enabled"); + IDS_HDT_CONSOLE (GFX_MISC, " GmcClockGating - %s\n", (Gfx->GmcClockGating == 0) ? "Disabled" : "Enabled"); + IDS_HDT_CONSOLE (GFX_MISC, " GmcPowerGating - %s\n", + (Gfx->GmcPowerGating == GmcPowerGatingDisabled) ? "Disabled" : ( + (Gfx->GmcPowerGating == GmcPowerGatingStutterOnly) ? "GmcPowerGatingStutterOnly" : ( + (Gfx->GmcPowerGating == GmcPowerGatingWidthStutter) ? "GmcPowerGatingWidthStutter" : "Unknown")) + ); + IDS_HDT_CONSOLE (GFX_MISC, " UmaSteering - %s\n", + (Gfx->UmaSteering == excel993 ) ? "excel993" : ( + (Gfx->UmaSteering == excel992 ) ? "excel992" : "Unknown") + ); + IDS_HDT_CONSOLE (GFX_MISC, " iGpuVgaMode - %s\n", + (Gfx->iGpuVgaMode == iGpuVgaAdapter) ? "VGA" : ( + (Gfx->iGpuVgaMode == iGpuVgaNonAdapter) ? "Non VGA" : "Unknown") + ); + IDS_HDT_CONSOLE (GFX_MISC, " UmaMode - %s\n", (Gfx->UmaInfo.UmaMode == UMA_NONE) ? "No UMA" : "UMA"); + if (Gfx->UmaInfo.UmaMode != UMA_NONE) { + IDS_HDT_CONSOLE (GFX_MISC, " UmaBase - 0x%x\n", Gfx->UmaInfo.UmaBase); + IDS_HDT_CONSOLE (GFX_MISC, " UmaSize - 0x%x\n", Gfx->UmaInfo.UmaSize); + IDS_HDT_CONSOLE (GFX_MISC, " UmaAttributes - 0x%x\n", Gfx->UmaInfo.UmaAttributes); + } + IDS_HDT_CONSOLE (GFX_MISC, "<-------------- GFX Config End --------------->\n"); + +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.h new file mode 100644 index 0000000..0c0aef7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.h @@ -0,0 +1,98 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize GFX configuration data structure. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _GFXCONFIGLIB_H_ +#define _GFXCONFIGLIB_H_ + +VOID +GfxConfigDebugDump ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGetUmaInfo ( + OUT UMA_INFO *UmaInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GfxLocateConfigData ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT GFX_PLATFORM_CONFIG **Gfx + ); + +AGESA_STATUS +GfxEnableGmmAccess ( + IN OUT GFX_PLATFORM_CONFIG *Gfx + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c new file mode 100644 index 0000000..f2323aa --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c @@ -0,0 +1,140 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize GFX configuration data structure. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbCommonLib.h" +#include "GnbGfxConfig.h" +#include "GfxConfigLib.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGMID_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GfxConfigMidInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Update GFX config info at ENV + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS Always succeeds + */ + +AGESA_STATUS +GfxConfigMidInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + AMD_MID_PARAMS *MidParamsPtr; + GFX_PLATFORM_CONFIG *Gfx; + AGESA_STATUS Status; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigMidInterface Enter\n"); + Status = GfxLocateConfigData (StdHeader, &Gfx); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + MidParamsPtr = (AMD_MID_PARAMS *) StdHeader; + Gfx->iGpuVgaMode = MidParamsPtr->GnbMidConfiguration.iGpuVgaMode; + } + GNB_DEBUG_CODE ( + GfxConfigDebugDump (Gfx); + ); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigMidInterface Exit [0x%x]\n", Status); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c new file mode 100644 index 0000000..04efa71 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c @@ -0,0 +1,163 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize GFX configuration data structure. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbCommonLib.h" +#include "GfxConfigLib.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGPOST_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GfxConfigPostInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Allocate UMA configuration data + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS Always succeeds + */ + +AGESA_STATUS +GfxConfigPostInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GFX_PLATFORM_CONFIG *Gfx; + AMD_POST_PARAMS *PostParamsPtr; + AGESA_STATUS Status; + PostParamsPtr = (AMD_POST_PARAMS *)StdHeader; + Status = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigPostInterface Enter\n"); + Gfx = GnbAllocateHeapBuffer (AMD_GFX_PLATFORM_CONFIG_HANDLE, sizeof (GFX_PLATFORM_CONFIG), StdHeader); + ASSERT (Gfx != NULL); + if (Gfx != NULL) { + LibAmdMemFill (Gfx, 0x00, sizeof (GFX_PLATFORM_CONFIG), StdHeader); + if (GnbBuildOptions.IgfxModeAsPcieEp) { + Gfx->GfxControllerMode = GfxControllerPcieEndpointMode; + Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 0, 1, 0, 0); + } else { + Gfx->GfxControllerMode = GfxControllerLegacyBridgeMode; + Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 1, 5, 0, 0); + } + Gfx->StdHeader = /* (PVOID) */(UINT32) StdHeader; + Gfx->GnbHdAudio = PostParamsPtr->PlatformConfig.GnbHdAudio; + Gfx->AbmSupport = PostParamsPtr->PlatformConfig.AbmSupport; + Gfx->DynamicRefreshRate = PostParamsPtr->PlatformConfig.DynamicRefreshRate; + Gfx->LcdBackLightControl = PostParamsPtr->PlatformConfig.LcdBackLightControl; + Gfx->AmdPlatformType = UserOptions.CfgAmdPlatformType; + Gfx->GmcClockGating = GnbBuildOptions.CfgGmcClockGating; + Gfx->GmcPowerGating = GnbBuildOptions.GmcPowerGating; + Gfx->UmaSteering = excel992 ; + GNB_DEBUG_CODE ( + GfxConfigDebugDump (Gfx); + ); + } else { + Status = AGESA_ERROR; + } + IDS_OPTION_HOOK (IDS_GNB_PLATFORMCFG_OVERRIDE, Gfx, StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigPostInterface Exit [0x%x]\n", Status); + return Status; +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h new file mode 100644 index 0000000..b94ae4a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h @@ -0,0 +1,78 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize GFX configuration data structure. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _GNBGFXCONFIG_H_ +#define _GNBGFXCONFIG_H_ + +#include "GfxConfigLib.h" + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c new file mode 100644 index 0000000..cc16c33 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c @@ -0,0 +1,211 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Supporting services to collect discrete GFX card info + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbCommonLib.h" +#include "GfxCardInfo.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXCARDINFO_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +typedef struct { + GNB_PCI_SCAN_DATA ScanData; + GFX_CARD_CARD_INFO *GfxCardInfo; + PCI_ADDR BaseBridge; + UINT8 BusNumber; +} GFX_SCAN_DATA; + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +SCAN_STATUS +GfxScanPcieDevice ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ); + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get information about all discrete GFX card in system + * + * + * + * @param[out] GfxCardInfo Pointer to GFX card info structure + * @param[in] StdHeader Standard configuration header + */ + +VOID +GfxGetDiscreteCardInfo ( + OUT GFX_CARD_CARD_INFO *GfxCardInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GFX_SCAN_DATA GfxScanData; + PCI_ADDR Start; + PCI_ADDR End; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxGetDiscreteCardInfo Enter\n"); + Start.AddressValue = MAKE_SBDFO (0, 0, 2, 0, 0); + End.AddressValue = MAKE_SBDFO (0, 0, 0x1f, 7, 0); + GfxScanData.BusNumber = 5; + GfxScanData.ScanData.GnbScanCallback = GfxScanPcieDevice; + GfxScanData.ScanData.StdHeader = StdHeader; + GfxScanData.GfxCardInfo = GfxCardInfo; + GnbLibPciScan (Start, End, &GfxScanData.ScanData); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxGetDiscreteCardInfo Exit\n"); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Evaluate device + * + * + * + * @param[in] Device PCI Address + * @param[in,out] ScanData Scan configuration data + * @retval Scan Status of 0 + */ + +SCAN_STATUS +GfxScanPcieDevice ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ) +{ + UINT8 ClassCode; + UINT32 VendorId; + + IDS_HDT_CONSOLE (GFX_MISC, " Evaluate device [%d:%d:%d]\n", + Device.Address.Bus, Device.Address.Device, Device.Address.Function + ); + + if (GnbLibPciIsBridgeDevice (Device.AddressValue, ScanData->StdHeader)) { + UINT32 SaveBusConfiguration; + UINT32 Value; + + if (Device.Address.Bus == 0) { + ((GFX_SCAN_DATA *) ScanData)->BaseBridge = Device; + } + GnbLibPciRead (Device.AddressValue | 0x18, AccessWidth32, &SaveBusConfiguration, ScanData->StdHeader); + Value = (((0xFF << 8) | ((GFX_SCAN_DATA *) ScanData)->BusNumber) << 8) | Device.Address.Bus; + GnbLibPciWrite (Device.AddressValue | 0x18, AccessWidth32, &Value, ScanData->StdHeader); + ((GFX_SCAN_DATA *) ScanData)->BusNumber++; + + GnbLibPciScanSecondaryBus (Device, ScanData); + + ((GFX_SCAN_DATA *) ScanData)->BusNumber--; + GnbLibPciWrite (Device.AddressValue | 0x18, AccessWidth32, &SaveBusConfiguration, ScanData->StdHeader); + return 0; + } + GnbLibPciRead (Device.AddressValue | 0x0b, AccessWidth8, &ClassCode, ScanData->StdHeader); + if (ClassCode == 3) { + IDS_HDT_CONSOLE (GFX_MISC, " Found GFX Card\n" + ); + + GnbLibPciRead (Device.AddressValue | 0x00, AccessWidth32, &VendorId, ScanData->StdHeader); + if (!GnbLibPciIsPcieDevice (Device.AddressValue, ScanData->StdHeader)) { + IDS_HDT_CONSOLE (GFX_MISC, " GFX Card is PCI device\n" + ); + ((GFX_SCAN_DATA *) ScanData)->GfxCardInfo->PciGfxCardBitmap |= (1 << ((GFX_SCAN_DATA *) ScanData)->BaseBridge.Address.Device); + return 0; + } + if ((UINT16) VendorId == 0x1002) { + IDS_HDT_CONSOLE (GFX_MISC, " GFX Card is AMD PCIe device\n" + ); + ((GFX_SCAN_DATA *) ScanData)->GfxCardInfo->AmdPcieGfxCardBitmap |= (1 << ((GFX_SCAN_DATA *) ScanData)->BaseBridge.Address.Device); + } + ((GFX_SCAN_DATA *) ScanData)->GfxCardInfo->PcieGfxCardBitmap |= (1 << ((GFX_SCAN_DATA *) ScanData)->BaseBridge.Address.Device); + } + return 0; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h new file mode 100644 index 0000000..e90ea23 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h @@ -0,0 +1,83 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Supporting services to collect discrete GFX card info + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + +#ifndef _GFXCARDINFO_H_ +#define _GFXCARDINFO_H_ + +VOID +GfxGetDiscreteCardInfo ( + OUT GFX_CARD_CARD_INFO *GfxCardInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c new file mode 100644 index 0000000..1e89d03 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c @@ -0,0 +1,636 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to initialize Integrated Info Table + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbGfx.h" +#include "GnbCommonLib.h" +#include "GnbPcieInitLibV1.h" +#include "GnbPcieConfig.h" +#include "GnbGfxFamServices.h" +#include "GnbRegistersLN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +typedef struct { + PCIE_CONNECTOR_TYPE ConnectorType; + UINT8 DisplayDeviceEnum; + UINT16 ConnectorEnum; + UINT16 EncoderEnum; + UINT8 ConnectorIndex; +} EXT_CONNECTOR_INFO; + +typedef struct { + UINT8 DisplayDeviceEnum; + UINT8 DeviceIndex; + UINT16 DeviceTag; + UINT16 DeviceAcpiEnum; +} EXT_DISPLAY_DEVICE_INFO; + +typedef struct { + AGESA_STATUS Status; + UINT8 DisplayDeviceEnum; + UINT8 RequestedPriorityIndex; + UINT8 CurrentPriorityIndex; + PCIe_ENGINE_CONFIG *Engine; +} CONNECTOR_ENUM_INFO; + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +GfxIntegratedEnumConnectorsForDevice ( + IN UINT8 DisplayDeviceEnum, + OUT EXT_DISPLAY_PATH *DisplayPathList, + IN OUT PCIe_PLATFORM_CONFIG *Pcie, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxIntegratedDebugDumpDisplayPath ( + IN EXT_DISPLAY_PATH *DisplayPath, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +AGESA_STATUS +GfxIntegratedEnumerateAllConnectors ( + OUT EXT_DISPLAY_PATH *DisplayPathList, + IN OUT PCIe_PLATFORM_CONFIG *Pcie, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxIntegratedCopyDisplayInfo ( + IN PCIe_ENGINE_CONFIG *Engine, + OUT EXT_DISPLAY_PATH *DisplayPath, + OUT EXT_DISPLAY_PATH *SecondaryDisplayPath, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +EXT_CONNECTOR_INFO ConnectorInfoTable[] = { + { + ConnectorTypeDP, + DEVICE_DFP, + CONNECTOR_DISPLAYPORT_ENUM, + ENCODER_NOT_PRESENT, + 0, + }, + { + ConnectorTypeEDP, + DEVICE_LCD, + CONNECTOR_eDP_ENUM, + ENCODER_NOT_PRESENT, + 1 + }, + { + ConnectorTypeSingleLinkDVI, + DEVICE_DFP, + CONNECTOR_SINGLE_LINK_DVI_D_ENUM, + ENCODER_NOT_PRESENT, + 2 + }, + { + ConnectorTypeDualLinkDVI, + DEVICE_DFP, + CONNECTOR_DUAL_LINK_DVI_D_ENUM, + ENCODER_NOT_PRESENT, + 3 + }, + { + ConnectorTypeHDMI, + DEVICE_DFP, + CONNECTOR_HDMI_TYPE_A_ENUM, + ENCODER_NOT_PRESENT, + 4 + }, + { + ConnectorTypeTravisDpToVga, + DEVICE_CRT, + CONNECTOR_VGA_ENUM, + ENCODER_TRAVIS_ENUM_ID1, + 5 + }, + { + ConnectorTypeTravisDpToLvds, + DEVICE_LCD, + CONNECTOR_LVDS_ENUM, + ENCODER_TRAVIS_ENUM_ID2, + 6 + }, + { + ConnectorTypeNutmegDpToVga, + DEVICE_CRT, + CONNECTOR_VGA_ENUM, + ENCODER_ALMOND_ENUM_ID1, + 5 + }, + { + ConnectorTypeSingleLinkDviI, + DEVICE_DFP, + CONNECTOR_SINGLE_LINK_DVI_I_ENUM, + ENCODER_NOT_PRESENT, + 5 + }, + { + ConnectorTypeCrt, + DEVICE_CRT, + CONNECTOR_VGA_ENUM, + ENCODER_NOT_PRESENT, + 5 + }, + { + ConnectorTypeLvds, + DEVICE_LCD, + CONNECTOR_LVDS_ENUM, + ENCODER_NOT_PRESENT, + 6 + }, + { + ConnectorTypeEDPToLvds, + DEVICE_LCD, + CONNECTOR_eDP_ENUM, + ENCODER_NOT_PRESENT, + 1 + }, + { + ConnectorTypeEDPToRealtecLvds, + DEVICE_LCD, + CONNECTOR_eDP_ENUM, + ENCODER_NOT_PRESENT, + 1 + }, + { + ConnectorTypeAutoDetect, + DEVICE_LCD, + CONNECTOR_LVDS_eDP_ENUM, + ENCODER_TRAVIS_ENUM_ID2, + 7 + }, +}; + +UINT8 ConnectorNumerArray[] = { +// DP eDP SDVI-D DDVI-D HDMI VGA LVDS Auto (eDP, LVDS, Travis LVDS) + 6, 1, 6, 6, 6, 1, 1, 2 +}; +/*----------------------------------------------------------------------------------------*/ +/** + * Enumerate all display connectors for specific display device type. + * + * + * + * @param[in] ConnectorType Connector type (see PCIe_DDI_DATA::ConnectorType). + * @retval Pointer to EXT_CONNECTOR_INFO + * @retval NULL if connector type unknown. + */ +STATIC EXT_CONNECTOR_INFO* +GfxIntegratedExtConnectorInfo ( + IN UINT8 ConnectorType + ) +{ + UINTN Index; + for (Index = 0; Index < (sizeof (ConnectorInfoTable) / sizeof (EXT_CONNECTOR_INFO)); Index++) { + if (ConnectorInfoTable[Index].ConnectorType == ConnectorType) { + return &ConnectorInfoTable[Index]; + } + } + return NULL; +} + +EXT_DISPLAY_DEVICE_INFO DisplayDeviceInfoTable[] = { + { + DEVICE_CRT, + 1, + ATOM_DEVICE_CRT1_SUPPORT, + 0x100, + }, + { + DEVICE_LCD, + 1, + ATOM_DEVICE_LCD1_SUPPORT, + 0x110, + }, + { + DEVICE_DFP, + 1, + ATOM_DEVICE_DFP1_SUPPORT, + 0x210, + }, + { + DEVICE_DFP, + 2, + ATOM_DEVICE_DFP2_SUPPORT, + 0x220, + }, + { + DEVICE_DFP, + 3, + ATOM_DEVICE_DFP3_SUPPORT, + 0x230, + }, + { + DEVICE_DFP, + 4, + ATOM_DEVICE_DFP4_SUPPORT, + 0x240, + }, + { + DEVICE_DFP, + 5, + ATOM_DEVICE_DFP5_SUPPORT, + 0x250, + }, + { + DEVICE_DFP, + 6, + ATOM_DEVICE_DFP6_SUPPORT, + 0x260, + } +}; +/*----------------------------------------------------------------------------------------*/ +/** + * Enumerate all display connectors for specific display device type. + * + * + * + * @param[in] DisplayDeviceEnum Display device enum + * @param[in] DisplayDeviceIndex Display device index + * @retval Pointer to EXT_DISPLAY_DEVICE_INFO + * @retval NULL if can not get display device info + */ +STATIC EXT_DISPLAY_DEVICE_INFO* +GfxIntegratedExtDisplayDeviceInfo ( + IN UINT8 DisplayDeviceEnum, + IN UINT8 DisplayDeviceIndex + ) +{ + UINT8 Index; + UINT8 LastIndex; + LastIndex = 0xff; + for (Index = 0; Index < (sizeof (DisplayDeviceInfoTable) / sizeof (EXT_DISPLAY_DEVICE_INFO)); Index++) { + if (DisplayDeviceInfoTable[Index].DisplayDeviceEnum == DisplayDeviceEnum) { + LastIndex = Index; + if (DisplayDeviceInfoTable[Index].DeviceIndex == DisplayDeviceIndex) { + return &DisplayDeviceInfoTable[Index]; + } + } + } + if (DisplayDeviceEnum == DEVICE_LCD && LastIndex != 0xff) { + return &DisplayDeviceInfoTable[LastIndex]; + } + return NULL; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Enumerate all display connectors + * + * + * + * @param[out] DisplayPathList Display path list + * @param[in,out] Pcie PCIe platform configuration info + * @param[in] Gfx Gfx configuration info + */ +AGESA_STATUS +GfxIntegratedEnumerateAllConnectors ( + OUT EXT_DISPLAY_PATH *DisplayPathList, + IN OUT PCIe_PLATFORM_CONFIG *Pcie, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + AgesaStatus = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAllConnectors Enter\n"); + Status = GfxIntegratedEnumConnectorsForDevice ( + DEVICE_DFP, + DisplayPathList, + Pcie, + Gfx + ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + Status = GfxIntegratedEnumConnectorsForDevice ( + DEVICE_CRT, + DisplayPathList, + Pcie, + Gfx + ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + Status = GfxIntegratedEnumConnectorsForDevice ( + DEVICE_LCD, + DisplayPathList, + Pcie, + Gfx + ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAllConnectors Exit [0x%x]\n", Status); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Enumerate all display connectors for specific display device type. + * + * + * + * @param[in] Engine Engine configuration info + * @param[in,out] Buffer Buffer pointer + * @param[in] Pcie PCIe configuration info + */ +VOID +STATIC +GfxIntegratedDdiInterfaceCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + CONNECTOR_ENUM_INFO *ConnectorEnumInfo; + EXT_CONNECTOR_INFO *ExtConnectorInfo; + ConnectorEnumInfo = (CONNECTOR_ENUM_INFO*) Buffer; + ExtConnectorInfo = GfxIntegratedExtConnectorInfo (Engine->Type.Ddi.DdiData.ConnectorType); + if (ExtConnectorInfo == NULL) { + AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo->Status); + PcieConfigDisableEngine (Engine); + return; + } + if (ExtConnectorInfo->DisplayDeviceEnum != ConnectorEnumInfo->DisplayDeviceEnum) { + //Not device type we are looking for + return; + } + if (Engine->Type.Ddi.DisplayPriorityIndex >= ConnectorEnumInfo->RequestedPriorityIndex && + Engine->Type.Ddi.DisplayPriorityIndex < ConnectorEnumInfo->CurrentPriorityIndex) { + ConnectorEnumInfo->CurrentPriorityIndex = Engine->Type.Ddi.DisplayPriorityIndex; + ConnectorEnumInfo->Engine = Engine; + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Enumerate all display connectors for specific display device type. + * + * + * + * @param[in] DisplayDeviceEnum Display device list + * @param[out] DisplayPathList Display path list + * @param[in,out] Pcie PCIe configuration info + * @param[in] Gfx Gfx configuration info + */ +AGESA_STATUS +GfxIntegratedEnumConnectorsForDevice ( + IN UINT8 DisplayDeviceEnum, + OUT EXT_DISPLAY_PATH *DisplayPathList, + IN OUT PCIe_PLATFORM_CONFIG *Pcie, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT8 DisplayDeviceIndex; + CONNECTOR_ENUM_INFO ConnectorEnumInfo; + EXT_CONNECTOR_INFO *ExtConnectorInfo; + EXT_DISPLAY_DEVICE_INFO *ExtDisplayDeviceInfo; + AGESA_STATUS Status; + UINT8 ConnectorIdArray[sizeof (ConnectorNumerArray)]; + ConnectorEnumInfo.Status = AGESA_SUCCESS; + DisplayDeviceIndex = 1; + ConnectorEnumInfo.RequestedPriorityIndex = 0; + ConnectorEnumInfo.DisplayDeviceEnum = DisplayDeviceEnum; + LibAmdMemFill (ConnectorIdArray, 0x00, sizeof (ConnectorIdArray), GnbLibGetHeader (Gfx)); + do { + ConnectorEnumInfo.Engine = NULL; + ConnectorEnumInfo.CurrentPriorityIndex = 0xff; + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_VIRTUAL | DESCRIPTOR_DDI_ENGINE, + GfxIntegratedDdiInterfaceCallback, + &ConnectorEnumInfo, + Pcie + ); + if (ConnectorEnumInfo.Engine == NULL) { + break; // No more connector support this + } + ConnectorEnumInfo.RequestedPriorityIndex = ConnectorEnumInfo.CurrentPriorityIndex + 1; + ExtConnectorInfo = GfxIntegratedExtConnectorInfo (ConnectorEnumInfo.Engine->Type.Ddi.DdiData.ConnectorType); + ASSERT (ExtConnectorInfo != NULL); + ASSERT (ExtConnectorInfo->ConnectorIndex < sizeof (ConnectorIdArray)); + if (ConnectorIdArray[ExtConnectorInfo->ConnectorIndex] >= ConnectorNumerArray[ExtConnectorInfo->ConnectorIndex]) { + //Run out of supported connectors + AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); + PcieConfigDisableEngine (ConnectorEnumInfo.Engine); + continue; + } + ConnectorEnumInfo.Engine->Type.Ddi.ConnectorId = ConnectorIdArray[ExtConnectorInfo->ConnectorIndex] + 1; + ExtDisplayDeviceInfo = GfxIntegratedExtDisplayDeviceInfo (DisplayDeviceEnum, DisplayDeviceIndex); + if (ExtDisplayDeviceInfo == NULL) { + //Run out of supported display device types + AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); + Status = AGESA_ERROR; + PcieConfigDisableEngine (ConnectorEnumInfo.Engine); + } + + if ((Gfx->Gnb3dStereoPinIndex != 0) && (ConnectorEnumInfo.Engine->Type.Ddi.DdiData.HdpIndex == (Gfx->Gnb3dStereoPinIndex - 1))) { + AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status); + Status = AGESA_ERROR; + PcieConfigDisableEngine (ConnectorEnumInfo.Engine); + } + + ConnectorEnumInfo.Engine->Type.Ddi.DisplayDeviceId = DisplayDeviceIndex; + + Status = GfxFmMapEngineToDisplayPath (ConnectorEnumInfo.Engine, DisplayPathList, Gfx); + AGESA_STATUS_UPDATE (Status, ConnectorEnumInfo.Status); + if (Status != AGESA_SUCCESS) { + continue; + } + ConnectorIdArray[ExtConnectorInfo->ConnectorIndex]++; + DisplayDeviceIndex++; + } while (ConnectorEnumInfo.Engine != NULL); + return ConnectorEnumInfo.Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize display path for given engine + * + * + * + * @param[in] Engine Engine configuration info + * @param[out] DisplayPath Display path list + * @param[out] SecondaryDisplayPath Secondary display path list + * @param[in] Gfx Gfx configuration info + */ + +VOID +GfxIntegratedCopyDisplayInfo ( + IN PCIe_ENGINE_CONFIG *Engine, + OUT EXT_DISPLAY_PATH *DisplayPath, + OUT EXT_DISPLAY_PATH *SecondaryDisplayPath, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + EXT_CONNECTOR_INFO *ExtConnectorInfo; + EXT_DISPLAY_DEVICE_INFO *ExtDisplayDeviceInfo; + ExtConnectorInfo = GfxIntegratedExtConnectorInfo (Engine->Type.Ddi.DdiData.ConnectorType); + ExtDisplayDeviceInfo = GfxIntegratedExtDisplayDeviceInfo (ExtConnectorInfo->DisplayDeviceEnum, Engine->Type.Ddi.DisplayDeviceId); + DisplayPath->usDeviceConnector = ExtConnectorInfo->ConnectorEnum | (Engine->Type.Ddi.ConnectorId << 8); + DisplayPath->usDeviceTag = ExtDisplayDeviceInfo->DeviceTag; + DisplayPath->usDeviceACPIEnum = ExtDisplayDeviceInfo->DeviceAcpiEnum; + DisplayPath->ucExtAUXDDCLutIndex = Engine->Type.Ddi.DdiData.AuxIndex; + DisplayPath->ucExtHPDPINLutIndex = Engine->Type.Ddi.DdiData.HdpIndex; + DisplayPath->ucChPNInvert = Engine->Type.Ddi.DdiData.LanePnInversionMask; + DisplayPath->usCaps = Engine->Type.Ddi.DdiData.Flags; + DisplayPath->usExtEncoderObjId = ExtConnectorInfo->EncoderEnum; + if (Engine->Type.Ddi.DdiData.Mapping[0].ChannelMappingValue == 0) { + DisplayPath->ChannelMapping.ucChannelMapping = (Engine->EngineData.StartLane < Engine->EngineData.EndLane) ? 0xE4 : 0x1B; + } else { + DisplayPath->ChannelMapping.ucChannelMapping = Engine->Type.Ddi.DdiData.Mapping[0].ChannelMappingValue; + } + GNB_DEBUG_CODE ( + GfxIntegratedDebugDumpDisplayPath (DisplayPath, Gfx); + ); + if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDualLinkDVI) { + if (SecondaryDisplayPath != NULL) { + SecondaryDisplayPath->usDeviceConnector = DisplayPath->usDeviceConnector; + } + GNB_DEBUG_CODE ( + GfxIntegratedDebugDumpDisplayPath (DisplayPath, Gfx); + ); + + if (Engine->Type.Ddi.DdiData.Mapping[1].ChannelMappingValue == 0) { + DisplayPath->ChannelMapping.ucChannelMapping = (Engine->EngineData.StartLane < Engine->EngineData.EndLane) ? 0xE4 : 0x1B; + } else { + DisplayPath->ChannelMapping.ucChannelMapping = Engine->Type.Ddi.DdiData.Mapping[1].ChannelMappingValue; + } + } +} + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Dump display path settings + * + * + * + * @param[in] DisplayPath Display path + * @param[in] Gfx Gfx configuration + */ + +VOID +GfxIntegratedDebugDumpDisplayPath ( + IN EXT_DISPLAY_PATH *DisplayPath, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + IDS_HDT_CONSOLE (GFX_MISC, " usDeviceConnector = 0x%x\n", + DisplayPath->usDeviceConnector + ); + IDS_HDT_CONSOLE (GFX_MISC, " usDeviceTag = 0x%x\n", + DisplayPath->usDeviceTag + ); + IDS_HDT_CONSOLE (GFX_MISC, " usDeviceACPIEnum = 0x%x\n", + DisplayPath->usDeviceACPIEnum + ); + IDS_HDT_CONSOLE (GFX_MISC, " usExtEncoderObjId = 0x%x\n", + DisplayPath->usExtEncoderObjId + ); + IDS_HDT_CONSOLE (GFX_MISC, " ucChannelMapping = 0x%x\n", + DisplayPath->ChannelMapping.ucChannelMapping + ); + IDS_HDT_CONSOLE (GFX_MISC, " ucChPNInvert = 0x%x\n", + DisplayPath->ucChPNInvert + ); + IDS_HDT_CONSOLE (GFX_MISC, " usCaps = 0x%x\n", + DisplayPath->usCaps + ); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.h new file mode 100644 index 0000000..0527f33 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.h @@ -0,0 +1,91 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to initialize Integrated Info Table + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GFXENUMCONNECTORS_H_ +#define _GFXENUMCONNECTORS_H_ + + +VOID +GfxIntegratedCopyDisplayInfo ( + IN PCIe_ENGINE_CONFIG *Engine, + OUT EXT_DISPLAY_PATH *DisplayPath, + OUT EXT_DISPLAY_PATH *SecondaryDisplayPath, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +AGESA_STATUS +GfxIntegratedEnumerateAllConnectors ( + OUT EXT_DISPLAY_PATH *DisplayPathList, + IN OUT PCIe_PLATFORM_CONFIG *Pcie, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c new file mode 100644 index 0000000..462fa72 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c @@ -0,0 +1,1013 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to initialize Integrated Info Table + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbFuseTable.h" +#include "GnbPcie.h" +#include "GnbGfx.h" +#include "GnbFuseTable.h" +#include "GnbGfxFamServices.h" +#include "GnbCommonLib.h" +#include "GfxPowerPlayTable.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXPOWERPLAYTABLE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +/// Software state +typedef struct { + BOOLEAN Valid; ///< State valid + UINT16 Classification; ///< State classification + UINT32 CapsAndSettings; ///< State capability and settings + UINT16 Classification2; ///< State classification2 + UINT32 Vclk; ///< UVD VCLK + UINT32 Dclk; ///< UVD DCLK + UINT8 NumberOfDpmStates; ///< Number of DPM states + UINT8 DpmSatesArray[MAX_NUM_OF_DPM_STATES]; ///< DPM state index array +} SW_STATE; + +/// DPM state +typedef struct { + BOOLEAN Valid; ///< State valid + UINT32 Sclk; ///< Sclk in kHz + UINT8 Vid; ///< VID index + UINT16 Tdp; ///< Tdp limit +} DPM_STATE; + +typedef struct { + GFX_PLATFORM_CONFIG *Gfx; + ATOM_PPLIB_POWERPLAYTABLE3 *PpTable; + PP_FUSE_ARRAY *PpFuses; + SW_STATE SwStateArray [MAX_NUM_OF_SW_STATES]; ///< SW state array + DPM_STATE DpmStateArray[MAX_NUM_OF_DPM_STATES]; ///< Sclk DPM state array + UINT8 NumOfClockVoltageLimitEnties; /// + ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD VceClockVoltageLimitArray[MAX_NUM_OF_VCE_CLK_STATES]; + UINT8 NumOfVceClockEnties; + VCECLOCKINFO VceClockInfoArray[MAX_NUM_OF_VCE_CLK_STATES]; + UINT8 NumOfVceStateEntries; + ATOM_PPLIB_VCE_STATE_RECORD VceStateArray[MAX_NUM_OF_VCE_STATES]; ///< VCE state array +} PP_WORKSPACE; +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +GfxIntegratedDebugDumpPpTable ( + IN ATOM_PPLIB_POWERPLAYTABLE3 *PpTable, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Locate existing tdp + * + * + * @param[in ] PpFuses Pointer to PP_FUSE_ARRAY + * @param[in] Sclk Sclk in 10kHz + * @param[in] StdHeader Standard configuration header + * @retval Tdp limit in DPM state array + */ + +STATIC UINT16 +GfxPowerPlayLocateTdp ( + IN PP_FUSE_ARRAY *PpFuses, + IN UINT32 Sclk, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 Index; + UINT32 DpmIndex; + UINT32 DpmSclk; + UINT32 DeltaSclk; + UINT32 MinDeltaSclk; + + DpmIndex = 0; + MinDeltaSclk = 0xFFFFFFFF; + for (Index = 0; Index < MAX_NUM_OF_FUSED_DPM_STATES; Index++) { + if (PpFuses->SclkDpmDid[Index] != 0) { + DpmSclk = GfxFmCalculateClock (PpFuses->SclkDpmDid[Index], StdHeader); + DeltaSclk = (DpmSclk > Sclk) ? (DpmSclk - Sclk) : (Sclk - DpmSclk); + if (DeltaSclk < MinDeltaSclk) { + MinDeltaSclk = MinDeltaSclk; + DpmIndex = Index; + } + } + } + return PpFuses->SclkDpmTdpLimit[DpmIndex]; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Create new software state + * + * + * @param[in, out] PpWorkspace PP workspace + * @retval Pointer to state entry in SW state array + */ + +STATIC SW_STATE* +GfxPowerPlayCreateSwState ( + IN OUT PP_WORKSPACE *PpWorkspace + ) +{ + UINTN Index; + for (Index = 0; Index < MAX_NUM_OF_SW_STATES; Index++) { + if (PpWorkspace->SwStateArray[Index].Valid == FALSE) { + PpWorkspace->SwStateArray[Index].Valid = TRUE; + return &(PpWorkspace->SwStateArray[Index]); + } + } + return NULL; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Create new DPM state + * + * + * @param[in, out] PpWorkspace PP workspace + * @param[in] Sclk SCLK in kHz + * @param[in] Vid Vid index + * @param[in] Tdp Tdp limit + * @retval Index of state entry in DPM state array + */ + +STATIC UINT8 +GfxPowerPlayCreateDpmState ( + IN OUT PP_WORKSPACE *PpWorkspace, + IN UINT32 Sclk, + IN UINT8 Vid, + IN UINT16 Tdp + ) +{ + UINT8 Index; + for (Index = 0; Index < MAX_NUM_OF_DPM_STATES; Index++) { + if (PpWorkspace->DpmStateArray[Index].Valid == FALSE) { + PpWorkspace->DpmStateArray[Index].Sclk = Sclk; + PpWorkspace->DpmStateArray[Index].Vid = Vid; + PpWorkspace->DpmStateArray[Index].Valid = TRUE; + PpWorkspace->DpmStateArray[Index].Tdp = Tdp; + return Index; + } + } + return 0; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Locate existing or Create new DPM state + * + * + * @param[in, out] PpWorkspace PP workspace + * @param[in] Sclk SCLK in kHz + * @param[in] Vid Vid index + * @param[in] Tdp Tdp limit + * @retval Index of state entry in DPM state array + */ + +STATIC UINT8 +GfxPowerPlayAddDpmState ( + IN OUT PP_WORKSPACE *PpWorkspace, + IN UINT32 Sclk, + IN UINT8 Vid, + IN UINT16 Tdp + ) +{ + UINT8 Index; + for (Index = 0; Index < MAX_NUM_OF_DPM_STATES; Index++) { + if (PpWorkspace->DpmStateArray[Index].Valid && Sclk == PpWorkspace->DpmStateArray[Index].Sclk && Vid == PpWorkspace->DpmStateArray[Index].Vid) { + return Index; + } + } + return GfxPowerPlayCreateDpmState (PpWorkspace, Sclk, Vid, Tdp); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Add reference to DPM state for SW state + * + * + * @param[in, out] SwStateArray Pointer to SW state array + * @param[in] DpmStateIndex DPM state index + */ + +STATIC VOID +GfxPowerPlayAddDpmStateToSwState ( + IN OUT SW_STATE *SwStateArray, + IN UINT8 DpmStateIndex + ) +{ + SwStateArray->DpmSatesArray[SwStateArray->NumberOfDpmStates++] = DpmStateIndex; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Copy SW state info to PPTable + * + * + * @param[in, out] PpWorkspace PP workspace + */ +STATIC VOID * +GfxPowerPlayAttachStateInfoBlock ( + IN OUT PP_WORKSPACE *PpWorkspace + ) +{ + UINT8 Index; + UINT8 SwStateIndex; + STATE_ARRAY *StateArray; + ATOM_PPLIB_STATE_V2 *States; + StateArray = (STATE_ARRAY *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize); + States = &StateArray->States[0]; + SwStateIndex = 0; + for (Index = 0; Index < MAX_NUM_OF_SW_STATES; Index++) { + if (PpWorkspace->SwStateArray[Index].Valid && PpWorkspace->SwStateArray[Index].NumberOfDpmStates != 0) { + States->nonClockInfoIndex = SwStateIndex; + States->ucNumDPMLevels = PpWorkspace->SwStateArray[Index].NumberOfDpmStates; + LibAmdMemCopy ( + &States->ClockInfoIndex[0], + PpWorkspace->SwStateArray[Index].DpmSatesArray, + PpWorkspace->SwStateArray[Index].NumberOfDpmStates, + GnbLibGetHeader (PpWorkspace->Gfx) + ); + States = (ATOM_PPLIB_STATE_V2*) ((UINT8*) States + sizeof (ATOM_PPLIB_STATE_V2) + sizeof (UINT8) * (States->ucNumDPMLevels - 1)); + SwStateIndex++; + } + } + StateArray->ucNumEntries = SwStateIndex; + PpWorkspace->PpTable->sHeader.usStructureSize = PpWorkspace->PpTable->sHeader.usStructureSize + (USHORT) ((UINT8 *) States - (UINT8 *) StateArray); + return StateArray; +} +/*----------------------------------------------------------------------------------------*/ +/** + * Copy clock info to PPTable + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID * +GfxPowerPlayAttachClockInfoBlock ( + IN OUT PP_WORKSPACE *PpWorkspace + ) +{ + CLOCK_INFO_ARRAY *ClockInfoArray; + UINT8 Index; + UINT8 ClkStateIndex; + ClkStateIndex = 0; + ClockInfoArray = (CLOCK_INFO_ARRAY *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize); + for (Index = 0; Index < MAX_NUM_OF_DPM_STATES; Index++) { + if (PpWorkspace->DpmStateArray[Index].Valid == TRUE) { + ClockInfoArray->ClockInfo[ClkStateIndex].ucEngineClockHigh = (UINT8) (PpWorkspace->DpmStateArray[Index].Sclk >> 16); + ClockInfoArray->ClockInfo[ClkStateIndex].usEngineClockLow = (UINT16) (PpWorkspace->DpmStateArray[Index].Sclk); + ClockInfoArray->ClockInfo[ClkStateIndex].vddcIndex = PpWorkspace->DpmStateArray[Index].Vid; + ClockInfoArray->ClockInfo[ClkStateIndex].tdpLimit = PpWorkspace->DpmStateArray[Index].Tdp; + ClkStateIndex++; + } + } + ClockInfoArray->ucNumEntries = ClkStateIndex; + ClockInfoArray->ucEntrySize = sizeof (ATOM_PPLIB_SUMO_CLOCK_INFO); + PpWorkspace->PpTable->sHeader.usStructureSize += sizeof (CLOCK_INFO_ARRAY) + sizeof (ATOM_PPLIB_SUMO_CLOCK_INFO) * ClkStateIndex - sizeof (ATOM_PPLIB_SUMO_CLOCK_INFO); + return ClockInfoArray; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Copy non clock info to PPTable + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID * +GfxPowerPlayAttachNonClockInfoBlock ( + IN OUT PP_WORKSPACE *PpWorkspace + ) +{ + NON_CLOCK_INFO_ARRAY *NonClockInfoArray; + UINT8 Index; + UINT8 NonClkStateIndex; + + NonClockInfoArray = (NON_CLOCK_INFO_ARRAY *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize); + NonClkStateIndex = 0; + for (Index = 0; Index < MAX_NUM_OF_SW_STATES; Index++) { + if (PpWorkspace->SwStateArray[Index].Valid && PpWorkspace->SwStateArray[Index].NumberOfDpmStates != 0) { + NonClockInfoArray->NonClockInfo[NonClkStateIndex].usClassification = PpWorkspace->SwStateArray[Index].Classification; + NonClockInfoArray->NonClockInfo[NonClkStateIndex].ulCapsAndSettings = PpWorkspace->SwStateArray[Index].CapsAndSettings; + NonClockInfoArray->NonClockInfo[NonClkStateIndex].usClassification2 = PpWorkspace->SwStateArray[Index].Classification2; + NonClockInfoArray->NonClockInfo[NonClkStateIndex].ulDCLK = PpWorkspace->SwStateArray[Index].Dclk; + NonClockInfoArray->NonClockInfo[NonClkStateIndex].ulVCLK = PpWorkspace->SwStateArray[Index].Vclk; + NonClkStateIndex++; + } + } + NonClockInfoArray->ucNumEntries = NonClkStateIndex; + NonClockInfoArray->ucEntrySize = sizeof (ATOM_PPLIB_NONCLOCK_INFO); + PpWorkspace->PpTable->sHeader.usStructureSize += sizeof (NON_CLOCK_INFO_ARRAY) + sizeof (ATOM_PPLIB_NONCLOCK_INFO) * NonClkStateIndex - sizeof (ATOM_PPLIB_NONCLOCK_INFO); + return NonClockInfoArray; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if fused state valid + * + * + * @param[out] Index State index + * @param[in] PpFuses Pointer to fuse table + * @param[in] Gfx Gfx configuration info + * @retval TRUE State is valid + */ +STATIC BOOLEAN +GfxPowerPlayIsFusedStateValid ( + IN UINT8 Index, + IN PP_FUSE_ARRAY *PpFuses, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + BOOLEAN Result; + Result = FALSE; + if (PpFuses->SclkDpmValid[Index] != 0) { + Result = TRUE; + if (PpFuses->PolicyLabel[Index] == POLICY_LABEL_BATTERY && (Gfx->AmdPlatformType & AMD_PLATFORM_MOBILE) == 0) { + Result = FALSE; + } + } + return Result; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get SW state calssification from fuses + * + * + * @param[out] Index State index + * @param[in] PpFuses Pointer to fuse table + * @param[in] Gfx Gfx configuration info + * @retval State classification + */ + +STATIC UINT16 +GfxPowerPlayGetClassificationFromFuses ( + IN UINT8 Index, + IN PP_FUSE_ARRAY *PpFuses, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT16 Classification; + Classification = 0; + switch (PpFuses->PolicyFlags[Index]) { + case 0x1: + Classification |= ATOM_PPLIB_CLASSIFICATION_NONUVDSTATE; + break; + case 0x2: + Classification |= ATOM_PPLIB_CLASSIFICATION_UVDSTATE; + break; + case 0x4: + //Possible SD + HD state + break; + case 0x8: + Classification |= ATOM_PPLIB_CLASSIFICATION_HDSTATE; + break; + case 0x10: + Classification |= ATOM_PPLIB_CLASSIFICATION_SDSTATE; + break; + default: + break; + } + switch (PpFuses->PolicyLabel[Index]) { + case POLICY_LABEL_BATTERY: + Classification |= ATOM_PPLIB_CLASSIFICATION_UI_BATTERY; + break; + case POLICY_LABEL_PERFORMANCE: + Classification |= ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE; + break; + default: + break; + } + return Classification; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get SW state calssification2 from fuses + * + * + * @param[out] Index State index + * @param[in] PpFuses Pointer to fuse table + * @param[in] Gfx Gfx configuration info + * @retval State classification2 + */ + +STATIC UINT16 +GfxPowerPlayGetClassification2FromFuses ( + IN UINT8 Index, + IN PP_FUSE_ARRAY *PpFuses, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT16 Classification2; + Classification2 = 0; + + switch (PpFuses->PolicyFlags[Index]) { + + case 0x4: + Classification2 |= ATOM_PPLIB_CLASSIFICATION2_MVC; + break; + + default: + break; + } + + return Classification2; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Build SCLK state info + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID +GfxPowerPlayBuildSclkStateTable ( + IN OUT PP_WORKSPACE *PpWorkspace + ) +{ + UINT8 ClkStateIndex; + UINT8 DpmFuseIndex; + UINT8 Index; + UINT32 Sclk; + SW_STATE *State; + PP_FUSE_ARRAY *PpFuses; + + PpFuses = PpWorkspace->PpFuses; + // Create States from Fuses + for (Index = 0; Index < MAX_NUM_OF_FUSED_SW_STATES; Index++) { + if (GfxPowerPlayIsFusedStateValid (Index, PpFuses, PpWorkspace->Gfx)) { + //Create new SW State; + State = GfxPowerPlayCreateSwState (PpWorkspace); + State->Classification = GfxPowerPlayGetClassificationFromFuses (Index, PpFuses, PpWorkspace->Gfx); + State->Classification2 = GfxPowerPlayGetClassification2FromFuses (Index, PpFuses, PpWorkspace->Gfx); + if ((State->Classification & (ATOM_PPLIB_CLASSIFICATION_HDSTATE | ATOM_PPLIB_CLASSIFICATION_UVDSTATE | ATOM_PPLIB_CLASSIFICATION_SDSTATE)) != 0 || + (State->Classification2 & ATOM_PPLIB_CLASSIFICATION2_MVC) != 0) { + State->Vclk = (PpFuses->VclkDid[PpFuses->VclkDclkSel[Index]] != 0) ? GfxFmCalculateClock (PpFuses->VclkDid[PpFuses->VclkDclkSel[Index]], GnbLibGetHeader (PpWorkspace->Gfx)) : 0; + State->Dclk = (PpFuses->DclkDid[PpFuses->VclkDclkSel[Index]] != 0) ? GfxFmCalculateClock (PpFuses->DclkDid[PpFuses->VclkDclkSel[Index]], GnbLibGetHeader (PpWorkspace->Gfx)) : 0; + } + if (((State->Classification & 0x7) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) || + ((State->Classification & (ATOM_PPLIB_CLASSIFICATION_HDSTATE | ATOM_PPLIB_CLASSIFICATION_SDSTATE)) != 0)) { + if (PpWorkspace->Gfx->AbmSupport != 0) { + State->CapsAndSettings |= ATOM_PPLIB_ENABLE_VARIBRIGHT; + } + if (PpWorkspace->Gfx->DynamicRefreshRate != 0) { + State->CapsAndSettings |= ATOM_PPLIB_ENABLE_DRR; + } + } + for (DpmFuseIndex = 0; DpmFuseIndex < MAX_NUM_OF_FUSED_DPM_STATES; DpmFuseIndex++) { + if ((PpFuses->SclkDpmValid[Index] & (1 << DpmFuseIndex)) != 0 ) { + Sclk = (PpFuses->SclkDpmDid[DpmFuseIndex] != 0) ? GfxFmCalculateClock (PpFuses->SclkDpmDid[DpmFuseIndex], GnbLibGetHeader (PpWorkspace->Gfx)) : 0; + if (Sclk != 0) { + ClkStateIndex = GfxPowerPlayAddDpmState (PpWorkspace, Sclk, PpFuses->SclkDpmVid[DpmFuseIndex], PpFuses->SclkDpmTdpLimit[DpmFuseIndex]); + GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex); + } + } + } + } + } + // Create Boot State + State = GfxPowerPlayCreateSwState (PpWorkspace); + State->Classification = ATOM_PPLIB_CLASSIFICATION_BOOT; + Sclk = 200 * 100; + ClkStateIndex = GfxPowerPlayAddDpmState (PpWorkspace, Sclk, 0, GfxPowerPlayLocateTdp (PpFuses, Sclk, GnbLibGetHeader (PpWorkspace->Gfx))); + GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex); + + // Create Thermal State + State = GfxPowerPlayCreateSwState (PpWorkspace); + State->Classification = ATOM_PPLIB_CLASSIFICATION_THERMAL; + Sclk = GfxFmCalculateClock (PpFuses->SclkThermDid, GnbLibGetHeader (PpWorkspace->Gfx)); + ClkStateIndex = GfxPowerPlayAddDpmState (PpWorkspace, Sclk, 0, GfxPowerPlayLocateTdp (PpFuses, Sclk, GnbLibGetHeader (PpWorkspace->Gfx))); + GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Add ECLK state + * + * + * @param[in, out] PpWorkspace PP workspace + * @param[in] Eclk SCLK in kHz + * @retval Index of state entry in ECLK clock array + */ + +STATIC UINT8 +GfxPowerPlayAddEclkState ( + IN OUT PP_WORKSPACE *PpWorkspace, + IN UINT32 Eclk + ) +{ + UINT8 Index; + USHORT EclkLow; + UCHAR EclkHigh; + EclkLow = (USHORT) (Eclk & 0xffff); + EclkHigh = (UCHAR) (Eclk >> 16); + for (Index = 0; Index < PpWorkspace->NumOfVceClockEnties; Index++) { + if (PpWorkspace->VceClockInfoArray[Index].ucECClkHigh == EclkHigh && PpWorkspace->VceClockInfoArray[Index].usECClkLow == EclkLow) { + return Index; + } + } + PpWorkspace->VceClockInfoArray[PpWorkspace->NumOfVceClockEnties].ucECClkHigh = EclkHigh; + PpWorkspace->VceClockInfoArray[PpWorkspace->NumOfVceClockEnties].usECClkLow = EclkLow; + PpWorkspace->VceClockInfoArray[PpWorkspace->NumOfVceClockEnties].ucEVClkHigh = EclkHigh; + PpWorkspace->VceClockInfoArray[PpWorkspace->NumOfVceClockEnties].usEVClkLow = EclkLow; + return PpWorkspace->NumOfVceClockEnties++; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Add ECLK state + * + * + * @param[in, out] PpWorkspace PP workspace + * @param[in] EclkIndex ECLK index + * @param[in] Vid Vid index + * @retval Index of state entry in Eclk Voltage record array + */ + +STATIC UINT8 +GfxPowerPlayAddEclkVoltageRecord ( + IN OUT PP_WORKSPACE *PpWorkspace, + IN UINT8 EclkIndex, + IN UINT8 Vid + ) +{ + UINT8 Index; + for (Index = 0; Index < PpWorkspace->NumOfClockVoltageLimitEnties; Index++) { + if (PpWorkspace->VceClockVoltageLimitArray[Index].ucVCEClockInfoIndex == EclkIndex) { + return Index; + } + } + PpWorkspace->VceClockVoltageLimitArray[PpWorkspace->NumOfClockVoltageLimitEnties].ucVCEClockInfoIndex = EclkIndex; + PpWorkspace->VceClockVoltageLimitArray[PpWorkspace->NumOfClockVoltageLimitEnties].usVoltage = Vid; + return PpWorkspace->NumOfClockVoltageLimitEnties++; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Attach extended header + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID * +GfxPowerPlayAttachVceTableRevBlock ( + IN OUT PP_WORKSPACE *PpWorkspace + ) +{ + ATOM_PPLIB_VCE_TABLE *VceTable; + VceTable = (ATOM_PPLIB_VCE_TABLE *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize); + VceTable->revid = 0; + PpWorkspace->PpTable->sHeader.usStructureSize += sizeof (ATOM_PPLIB_VCE_TABLE); + return VceTable; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Attach extended header + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID * +GfxPowerPlayAttachExtendedHeaderBlock ( + IN OUT PP_WORKSPACE *PpWorkspace + ) +{ + ATOM_PPLIB_EXTENDEDHEADER *ExtendedHeader; + ExtendedHeader = (ATOM_PPLIB_EXTENDEDHEADER *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize); + ExtendedHeader->usSize = sizeof (ATOM_PPLIB_EXTENDEDHEADER); + PpWorkspace->PpTable->sHeader.usStructureSize += sizeof (ATOM_PPLIB_EXTENDEDHEADER); + return ExtendedHeader; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Attach VCE clock info block + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID * +GfxPowerPlayAttachVceClockInfoBlock ( + IN OUT PP_WORKSPACE *PpWorkspace + ) +{ + VCECLOCKINFOARRAY *VceClockInfoArray; + VceClockInfoArray = (VCECLOCKINFOARRAY *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize); + VceClockInfoArray->ucNumEntries = PpWorkspace->NumOfVceClockEnties; + LibAmdMemCopy ( + &VceClockInfoArray->entries[0], + &PpWorkspace->VceClockInfoArray[0], + VceClockInfoArray->ucNumEntries * sizeof (VCECLOCKINFO), + GnbLibGetHeader (PpWorkspace->Gfx) + ); + PpWorkspace->PpTable->sHeader.usStructureSize = PpWorkspace->PpTable->sHeader.usStructureSize + + sizeof (VCECLOCKINFOARRAY) + + VceClockInfoArray->ucNumEntries * sizeof (VCECLOCKINFO) - + sizeof (VCECLOCKINFO); + return VceClockInfoArray; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Attach VCE voltage limit block + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID * +GfxPowerPlayAttachVceVoltageLimitBlock ( + IN OUT PP_WORKSPACE *PpWorkspace + ) +{ + ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE *VceClockVoltageLimitTable; + VceClockVoltageLimitTable = (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize); + VceClockVoltageLimitTable->numEntries = PpWorkspace->NumOfClockVoltageLimitEnties; + LibAmdMemCopy ( + &VceClockVoltageLimitTable->entries[0], + &PpWorkspace->VceClockVoltageLimitArray[0], + VceClockVoltageLimitTable->numEntries * sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD), + GnbLibGetHeader (PpWorkspace->Gfx) + ); + PpWorkspace->PpTable->sHeader.usStructureSize = PpWorkspace->PpTable->sHeader.usStructureSize + + sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE) + + VceClockVoltageLimitTable->numEntries * sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD) - + sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD); + return VceClockVoltageLimitTable; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Attach VCE state block + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID * +GfxPowerPlayAttachVceStateTaleBlock ( + IN OUT PP_WORKSPACE *PpWorkspace + ) +{ + ATOM_PPLIB_VCE_STATE_TABLE *VceStateTable; + VceStateTable = (ATOM_PPLIB_VCE_STATE_TABLE *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize); + VceStateTable->numEntries = PpWorkspace->NumOfVceStateEntries; + LibAmdMemCopy ( + &VceStateTable->entries[0], + &PpWorkspace->VceStateArray[0], + VceStateTable->numEntries * sizeof (ATOM_PPLIB_VCE_STATE_RECORD), + GnbLibGetHeader (PpWorkspace->Gfx) + ); + PpWorkspace->PpTable->sHeader.usStructureSize = PpWorkspace->PpTable->sHeader.usStructureSize + + sizeof (ATOM_PPLIB_VCE_STATE_TABLE) + + VceStateTable->numEntries * sizeof (ATOM_PPLIB_VCE_STATE_RECORD) - + sizeof (ATOM_PPLIB_VCE_STATE_RECORD); + return VceStateTable; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Build VCE state info + * + * + * @param[in, out] PpWorkspace PP workspace + */ + +STATIC VOID +GfxPowerPlayBuildVceStateTable ( + IN OUT PP_WORKSPACE *PpWorkspace + ) +{ + UINT8 Index; + UINT8 VceStateIndex; + UINT8 Vid; + UINT32 Eclk; + UINT32 Sclk; + UINT8 UsedStateBitmap; + UsedStateBitmap = 0; + // build used state + for (Index = 0; Index < (sizeof (PpWorkspace->PpFuses->VceFlags) / sizeof (PpWorkspace->PpFuses->VceFlags[0])) ; Index++) { + UsedStateBitmap |= PpWorkspace->PpFuses->VceFlags[Index]; + for (VceStateIndex = 0; VceStateIndex < (sizeof (PpWorkspace->VceStateArray) / sizeof (PpWorkspace->VceStateArray[0])); VceStateIndex++) { + if ((PpWorkspace->PpFuses->VceFlags[Index] & (1 << VceStateIndex)) != 0) { + Sclk = GfxFmCalculateClock (PpWorkspace->PpFuses->SclkDpmDid[PpWorkspace->PpFuses->VceReqSclkSel[Index]], GnbLibGetHeader (PpWorkspace->Gfx)); + Vid = PpWorkspace->PpFuses->SclkDpmVid[PpWorkspace->PpFuses->VceReqSclkSel[Index]]; + PpWorkspace->VceStateArray[VceStateIndex].ucClockInfoIndex = GfxPowerPlayAddDpmState (PpWorkspace, Sclk, Vid, GfxPowerPlayLocateTdp (PpWorkspace->PpFuses, Sclk, GnbLibGetHeader (PpWorkspace->Gfx))); + if (PpWorkspace->PpFuses->VceMclk[Index] == 1) { + PpWorkspace->VceStateArray[VceStateIndex].ucClockInfoIndex |= (PpWorkspace->PpFuses->VceMclk[Index] << 6); + } + Eclk = GfxFmCalculateClock (PpWorkspace->PpFuses->EclkDid[Index], GnbLibGetHeader (PpWorkspace->Gfx)); + PpWorkspace->VceStateArray[VceStateIndex].ucVCEClockInfoIndex = GfxPowerPlayAddEclkState (PpWorkspace, Eclk); + GfxPowerPlayAddEclkVoltageRecord (PpWorkspace, PpWorkspace->VceStateArray[VceStateIndex].ucVCEClockInfoIndex, Vid); + PpWorkspace->NumOfVceStateEntries++; + } + } + } + //build unused states + for (VceStateIndex = 0; VceStateIndex < (sizeof (PpWorkspace->VceStateArray) / sizeof (PpWorkspace->VceStateArray[0])); VceStateIndex++) { + if ((UsedStateBitmap & (1 << VceStateIndex)) == 0) { + PpWorkspace->VceStateArray[VceStateIndex].ucClockInfoIndex = 0; + PpWorkspace->VceStateArray[VceStateIndex].ucVCEClockInfoIndex = GfxPowerPlayAddEclkState (PpWorkspace, 0); + PpWorkspace->NumOfVceStateEntries++; + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Build PP table + * + * + * @param[out] Buffer Buffer to create PP table + * @param[in] Gfx Gfx configuration info + * @retval AGESA_SUCCESS + * @retval AGESA_ERROR + */ + +AGESA_STATUS +GfxPowerPlayBuildTable ( + OUT VOID *Buffer, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + PP_WORKSPACE PpWorkspace; + VOID *BlockPtr; + + LibAmdMemFill (&PpWorkspace, 0x00, sizeof (PP_WORKSPACE), GnbLibGetHeader (Gfx)); + PpWorkspace.PpFuses = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx)); + ASSERT (PpWorkspace.PpFuses != NULL); + if (PpWorkspace.PpFuses == NULL) { + return AGESA_ERROR; + } + PpWorkspace.PpTable = (ATOM_PPLIB_POWERPLAYTABLE3 *) Buffer; + PpWorkspace.Gfx = Gfx; + //Fill static info + PpWorkspace.PpTable->sHeader.ucTableFormatRevision = 6; + PpWorkspace.PpTable->sHeader.ucTableContentRevision = 1; + PpWorkspace.PpTable->ucDataRevision = PpWorkspace.PpFuses->PPlayTableRev; + PpWorkspace.PpTable->sThermalController.ucType = ATOM_PP_THERMALCONTROLLER_SUMO; + PpWorkspace.PpTable->sThermalController.ucFanParameters = ATOM_PP_FANPARAMETERS_NOFAN; + PpWorkspace.PpTable->sHeader.usStructureSize = sizeof (ATOM_PPLIB_POWERPLAYTABLE3); + PpWorkspace.PpTable->usTableSize = sizeof (ATOM_PPLIB_POWERPLAYTABLE3); + PpWorkspace.PpTable->usFormatID = 7; + if ((Gfx->AmdPlatformType & AMD_PLATFORM_MOBILE) != 0) { + PpWorkspace.PpTable->ulPlatformCaps |= ATOM_PP_PLATFORM_CAP_POWERPLAY; + } + + // Fill Slck SW/DPM state info + GfxPowerPlayBuildSclkStateTable (&PpWorkspace); + // Fill Eclk state info + if (PpWorkspace.PpFuses->VceSateTableSupport) { + GfxPowerPlayBuildVceStateTable (&PpWorkspace); + } + + //Copy state info to actual PP table + BlockPtr = GfxPowerPlayAttachStateInfoBlock (&PpWorkspace); + PpWorkspace.PpTable->usStateArrayOffset = (USHORT) ((UINT8 *) BlockPtr - (UINT8 *) (PpWorkspace.PpTable)); + BlockPtr = GfxPowerPlayAttachClockInfoBlock (&PpWorkspace); + PpWorkspace.PpTable->usClockInfoArrayOffset = (USHORT) ((UINT8 *) BlockPtr - (UINT8 *) (PpWorkspace.PpTable)); + BlockPtr = GfxPowerPlayAttachNonClockInfoBlock (&PpWorkspace); + PpWorkspace.PpTable->usNonClockInfoArrayOffset = (USHORT) ((UINT8 *) BlockPtr - (UINT8 *) (PpWorkspace.PpTable)); + if (PpWorkspace.PpFuses->VceSateTableSupport) { + ATOM_PPLIB_EXTENDEDHEADER *ExtendedHeader; + ExtendedHeader = (ATOM_PPLIB_EXTENDEDHEADER *) GfxPowerPlayAttachExtendedHeaderBlock (&PpWorkspace); + PpWorkspace.PpTable->usExtendendedHeaderOffset = (USHORT) ((UINT8 *) ExtendedHeader - (UINT8 *) (PpWorkspace.PpTable)); + BlockPtr = GfxPowerPlayAttachVceTableRevBlock (&PpWorkspace); + ExtendedHeader->usVCETableOffset = (USHORT) ((UINT8 *) BlockPtr - (UINT8 *) (PpWorkspace.PpTable)); + GfxPowerPlayAttachVceClockInfoBlock (&PpWorkspace); + GfxPowerPlayAttachVceVoltageLimitBlock (&PpWorkspace); + GfxPowerPlayAttachVceStateTaleBlock (&PpWorkspace); + + } + GNB_DEBUG_CODE ( + GfxIntegratedDebugDumpPpTable (PpWorkspace.PpTable, Gfx); + ); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Dump PP table + * + * + * + * @param[in] PpTable Power Play table + * @param[in] Gfx Gfx configuration info + */ + +VOID +GfxIntegratedDebugDumpPpTable ( + IN ATOM_PPLIB_POWERPLAYTABLE3 *PpTable, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINTN Index; + UINTN DpmIndex; + STATE_ARRAY *StateArray; + ATOM_PPLIB_STATE_V2 *StatesPtr; + NON_CLOCK_INFO_ARRAY *NonClockInfoArrayPtr; + CLOCK_INFO_ARRAY *ClockInfoArrayPtr; + ATOM_PPLIB_EXTENDEDHEADER *ExtendedHeader; + ATOM_PPLIB_VCE_STATE_TABLE *VceStateTable; + ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE *VceClockVoltageLimitTable; + VCECLOCKINFOARRAY *VceClockInfoArray; + UINT8 SclkIndex; + UINT8 EclkIndex; + + IDS_HDT_CONSOLE (GFX_MISC, " < --- Power Play Table ------ > \n"); + IDS_HDT_CONSOLE (GFX_MISC, " Table Revision = %d\n", PpTable->ucDataRevision); + StateArray = (STATE_ARRAY *) ((UINT8 *) PpTable + PpTable->usStateArrayOffset); + StatesPtr = StateArray->States; + NonClockInfoArrayPtr = (NON_CLOCK_INFO_ARRAY *) ((UINT8 *) PpTable + PpTable->usNonClockInfoArrayOffset); + ClockInfoArrayPtr = (CLOCK_INFO_ARRAY *) ((UINT8 *) PpTable + PpTable->usClockInfoArrayOffset); + IDS_HDT_CONSOLE (GFX_MISC, " < --- SW State Table ---------> \n"); + for (Index = 0; Index < StateArray->ucNumEntries; Index++) { + IDS_HDT_CONSOLE (GFX_MISC, " State #%d\n", Index + 1 + ); + IDS_HDT_CONSOLE (GFX_MISC, " Classification 0x%x\n", + NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].usClassification + ); + IDS_HDT_CONSOLE (GFX_MISC, " Classification2 0x%x\n", + NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].usClassification2 + ); + IDS_HDT_CONSOLE (GFX_MISC, " VCLK = %dkHz\n", + NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].ulVCLK + ); + IDS_HDT_CONSOLE (GFX_MISC, " DCLK = %dkHz\n", + NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].ulDCLK + ); + IDS_HDT_CONSOLE (GFX_MISC, " DPM State Index: "); + for (DpmIndex = 0; DpmIndex < StatesPtr->ucNumDPMLevels; DpmIndex++) { + IDS_HDT_CONSOLE (GFX_MISC, "%d ", + StatesPtr->ClockInfoIndex [DpmIndex] + ); + } + IDS_HDT_CONSOLE (GFX_MISC, "\n"); + StatesPtr = (ATOM_PPLIB_STATE_V2 *) ((UINT8 *) StatesPtr + sizeof (ATOM_PPLIB_STATE_V2) + StatesPtr->ucNumDPMLevels - 1); + } + IDS_HDT_CONSOLE (GFX_MISC, " < --- SCLK DPM State Table ---> \n"); + for (Index = 0; Index < ClockInfoArrayPtr->ucNumEntries; Index++) { + UINT32 Sclk; + Sclk = ClockInfoArrayPtr->ClockInfo[Index].usEngineClockLow | (ClockInfoArrayPtr->ClockInfo[Index].ucEngineClockHigh << 16); + IDS_HDT_CONSOLE (GFX_MISC, " DPM State #%d\n", + Index + ); + IDS_HDT_CONSOLE (GFX_MISC, " SCLK = %d\n", + ClockInfoArrayPtr->ClockInfo[Index].usEngineClockLow | (ClockInfoArrayPtr->ClockInfo[Index].ucEngineClockHigh << 16) + ); + IDS_HDT_CONSOLE (GFX_MISC, " VID index = %d\n", + ClockInfoArrayPtr->ClockInfo[Index].vddcIndex + ); + IDS_HDT_CONSOLE (GFX_MISC, " tdpLimit = %d\n", + ClockInfoArrayPtr->ClockInfo[Index].tdpLimit + ); + } + if (PpTable->usExtendendedHeaderOffset != 0) { + ExtendedHeader = (ATOM_PPLIB_EXTENDEDHEADER *) ((UINT8 *) PpTable + PpTable->usExtendendedHeaderOffset); + VceClockInfoArray = (VCECLOCKINFOARRAY *) ((UINT8 *) ExtendedHeader + sizeof (ATOM_PPLIB_EXTENDEDHEADER) + sizeof (ATOM_PPLIB_VCE_TABLE)); + VceClockVoltageLimitTable = (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE *) ((UINT8 *) VceClockInfoArray + + sizeof (VCECLOCKINFOARRAY) + + VceClockInfoArray->ucNumEntries * sizeof (VCECLOCKINFO) - + sizeof (VCECLOCKINFO)); + VceStateTable = (ATOM_PPLIB_VCE_STATE_TABLE *) ((UINT8 *) VceClockVoltageLimitTable + + sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE) + + VceClockVoltageLimitTable->numEntries * sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD) - + sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD)); + + IDS_HDT_CONSOLE (GFX_MISC, " < --- VCE State Table [%d]--> \n", VceStateTable->numEntries); + for (Index = 0; Index < VceStateTable->numEntries; Index++) { + SclkIndex = VceStateTable->entries[Index].ucClockInfoIndex & 0x3F; + EclkIndex = VceStateTable->entries[Index].ucVCEClockInfoIndex; + IDS_HDT_CONSOLE (GFX_MISC, " VCE State #%d\n", Index + ); + if ((VceClockInfoArray->entries[EclkIndex].usECClkLow | (VceClockInfoArray->entries[EclkIndex].ucECClkHigh << 16)) == 0) { + IDS_HDT_CONSOLE (GFX_MISC, " Disable\n"); + } else { + IDS_HDT_CONSOLE (GFX_MISC, " SCLK = %d\n", + ClockInfoArrayPtr->ClockInfo[SclkIndex].usEngineClockLow | (ClockInfoArrayPtr->ClockInfo[SclkIndex].ucEngineClockHigh << 16) + ); + IDS_HDT_CONSOLE (GFX_MISC, " ECCLK = %d\n", + VceClockInfoArray->entries[EclkIndex].usECClkLow | (VceClockInfoArray->entries[EclkIndex].ucECClkHigh << 16) + ); + IDS_HDT_CONSOLE (GFX_MISC, " EVCLK = %d\n", + VceClockInfoArray->entries[EclkIndex].usEVClkLow | (VceClockInfoArray->entries[EclkIndex].ucEVClkHigh << 16) + ); + IDS_HDT_CONSOLE (GFX_MISC, " MCLK = %d\n", + (VceStateTable->entries[Index].ucClockInfoIndex >> 6 ) & 0x3 + ); + } + } + IDS_HDT_CONSOLE (GFX_MISC, " < --- VCE Voltage Record Table ---> \n"); + for (Index = 0; Index < VceClockVoltageLimitTable->numEntries; Index++) { + EclkIndex = VceClockVoltageLimitTable->entries[Index].ucVCEClockInfoIndex; + IDS_HDT_CONSOLE (GFX_MISC, " VCE Voltage Record #%d\n", Index + ); + IDS_HDT_CONSOLE (GFX_MISC, " ECLK = %d\n", + VceClockInfoArray->entries[EclkIndex].usECClkLow | (VceClockInfoArray->entries[EclkIndex].ucECClkHigh << 16) + ); + IDS_HDT_CONSOLE (GFX_MISC, " VID index = %d\n", + VceClockVoltageLimitTable->entries[Index].usVoltage + ); + } + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h new file mode 100644 index 0000000..fd19f60 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h @@ -0,0 +1,278 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to initialize Power Play Table + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GFXPOWERPLAYTABLE_H_ +#define _GFXPOWERPLAYTABLE_H_ + +#pragma pack (push, 1) + +#define POLICY_LABEL_BATTERY 0x1 +#define POLICY_LABEL_PERFORMANCE 0x2 + +#define MAX_NUM_OF_SW_STATES 10 +#define MAX_NUM_OF_DPM_STATES 10 +#define MAX_NUM_OF_VCE_CLK_STATES 5 +#define MAX_NUM_OF_VCE_STATES 6 +#define MAX_NUM_OF_FUSED_DPM_STATES 5 +#define MAX_NUM_OF_FUSED_SW_STATES 6 +/// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps +#define ATOM_PP_PLATFORM_CAP_BACKBIAS 1 +#define ATOM_PP_PLATFORM_CAP_POWERPLAY 2 +#define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4 +#define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8 +#define ATOM_PP_PLATFORM_CAP_ASPM_L1 16 +#define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32 +#define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64 +#define ATOM_PP_PLATFORM_CAP_STEPVDDC 128 +#define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256 +#define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512 +#define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024 +#define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048 +#define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096 +#define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, e.g. on an AC->DC transition. +#define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). +#define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 // Does +#define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000ul // Enable the 'regulator hot' feature. +#define ATOM_PP_PLATFORM_CAP_BACO 0x00020000ul // Does the driver supports BACO state. + + +#define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1 +#define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3 +#define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5 + +#define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008 +#define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010 +#define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020 +#define ATOM_PPLIB_CLASSIFICATION_REST 0x0040 +#define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080 +#define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100 +#define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200 +#define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400 +#define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800 +#define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000 +#define ATOM_PPLIB_CLASSIFICATION_HD2STATE 0x2000 +#define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000 +#define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000 +#define ATOM_PPLIB_CLASSIFICATION_NONUVDSTATE 0x0000 + +#define ATOM_PPLIB_CLASSIFICATION2_MVC 0x0004 //Multi-View + +#define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000ul +#define ATOM_PPLIB_ENABLE_DRR 0x00080000ul + +#define ATOM_PP_FANPARAMETERS_NOFAN 0x80 +#define ATOM_PP_THERMALCONTROLLER_SUMO 0x0E + +/// DPM state info +typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO { + USHORT usEngineClockLow; ///< Sclk [15:0] (Sclk in 10khz) + UCHAR ucEngineClockHigh; ///< Sclk [23:16](Sclk in 10khz) + UCHAR vddcIndex; ///< 2-bit VDDC index; + USHORT tdpLimit; ///< TDP Limit + USHORT rsv1; ///< Reserved + ULONG rsv2[2]; ///< Reserved +} ATOM_PPLIB_SUMO_CLOCK_INFO; + +/// Non clock info +typedef struct _ATOM_PPLIB_NONCLOCK_INFO { + USHORT usClassification; ///< State classification see ATOM_PPLIB_CLASSIFICATION_* + UCHAR ucMinTemperature; ///< Reserved + UCHAR ucMaxTemperature; ///< Reserved + ULONG ulCapsAndSettings; ///< Capability Setting (ATOM_PPLIB_ENABLE_DRR or ATOM_PPLIB_ENABLE_VARIBRIGHT or 0) + UCHAR ucRequiredPower; ///< Reserved + USHORT usClassification2; ///< Reserved + ULONG ulVCLK; ///< UVD clocks VCLK unit is in 10KHz + ULONG ulDCLK; ///< UVD clocks DCLK unit is in 10KHz + UCHAR ucUnused[5]; ///< Reserved +} ATOM_PPLIB_NONCLOCK_INFO; + +/// Thermal controller info stub +typedef struct _ATOM_PPLIB_THERMALCONTROLLER { + UCHAR ucType; ///< Reserved. Should be set 0xE + UCHAR ucI2cLine; ///< Reserved. Should be set 0 + UCHAR ucI2cAddress; ///< Reserved. Should be set 0 + UCHAR ucFanParameters; ///< Reserved. Should be set 0x80 + UCHAR ucFanMinRPM; ///< Reserved. Should be set 0 + UCHAR ucFanMaxRPM; ///< Reserved. Should be set 0 + UCHAR ucReserved; ///< Reserved. Should be set 0 + UCHAR ucFlags; ///< Reserved. Should be set 0 +} ATOM_PPLIB_THERMALCONTROLLER; + +/// SW state info +typedef struct _ATOM_PPLIB_STATE_V2 { + UCHAR ucNumDPMLevels; ///< Number of valid DPM levels in this state + UCHAR nonClockInfoIndex; ///< Index to the array of NonClockInfos + UCHAR ClockInfoIndex[1]; ///< Array of DPM states. Actual number calculated during state enumeration +} ATOM_PPLIB_STATE_V2; + +/// SW state Array +typedef struct { + UCHAR ucNumEntries; ///< Number of SW states + ATOM_PPLIB_STATE_V2 States[1]; ///< SW state info. Actual number calculated during state enumeration +} STATE_ARRAY; + +/// Clock info Array +typedef struct { + UCHAR ucNumEntries; ///< Number of ClockInfo entries + UCHAR ucEntrySize; ///< size of ATOM_PPLIB_SUMO_CLOCK_INFO + ATOM_PPLIB_SUMO_CLOCK_INFO ClockInfo[1]; ///< Clock info array. Size will be determined dynamically base on fuses +} CLOCK_INFO_ARRAY; + +/// Non clock info Array +typedef struct { + + UCHAR ucNumEntries; ///< Number of Entries; + UCHAR ucEntrySize; ///< Size of NonClockInfo + ATOM_PPLIB_NONCLOCK_INFO NonClockInfo[1]; ///< Non clock info array +} NON_CLOCK_INFO_ARRAY; + +/// VCE clock info +typedef struct { + USHORT usEVClkLow; ///< EVCLK low + UCHAR ucEVClkHigh; ///< EVCLK high + USHORT usECClkLow; ///< ECCLK low + UCHAR ucECClkHigh; ///< ECCLK high +} VCECLOCKINFO; + +/// VCE clock info array +typedef struct { + UCHAR ucNumEntries; ///< Number of entries + VCECLOCKINFO entries[1]; ///< VCE clock arrau +} VCECLOCKINFOARRAY; + +/// VCE voltage limit record +typedef struct { + USHORT usVoltage; ///< Voltage index + UCHAR ucVCEClockInfoIndex; ///< Index of VCE clock state +} ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD; + +/// VCE voltage limit table +typedef struct { + UCHAR numEntries; ///< Number of entries + ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD entries[1]; ///< Coltage limit state array +} ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE; + +/// VCE state record +typedef struct { + UCHAR ucVCEClockInfoIndex; ///< Index of VCE clock state + UCHAR ucClockInfoIndex; ///< Index of SCLK clock state +} ATOM_PPLIB_VCE_STATE_RECORD; + +/// VCE state table +typedef struct { + UCHAR numEntries; ///< Number of state entries + ATOM_PPLIB_VCE_STATE_RECORD entries[1]; ///< State entries +} ATOM_PPLIB_VCE_STATE_TABLE; + +/// Extended header +typedef struct { + USHORT usSize; ///< size of header + ULONG rsv15; ///< reserved + ULONG rsv16; ///< reserved + USHORT usVCETableOffset; ///< offset of ATOM_PPLIB_VCE_TABLE +} ATOM_PPLIB_EXTENDEDHEADER; + +/// VCE table +typedef struct { + UCHAR revid; ///< revision ID +} ATOM_PPLIB_VCE_TABLE; + +/// Power Play table +typedef struct _ATOM_PPLIB_POWERPLAYTABLE3 { + ATOM_COMMON_TABLE_HEADER sHeader; ///< Common header + UCHAR ucDataRevision; ///< Revision of PP table + UCHAR Reserved1[4]; ///< Reserved + USHORT usStateArrayOffset; ///< Offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures + USHORT usClockInfoArrayOffset; ///< Offset from start of the table to ClockInfoArray + USHORT usNonClockInfoArrayOffset; ///< Offset from Start of the table to NonClockInfoArray + USHORT Reserved2[2]; ///< Reserved + USHORT usTableSize; ///< the size of this structure, or the extended structure + ULONG ulPlatformCaps; ///< See ATOM_PPLIB_CAPS_* + ATOM_PPLIB_THERMALCONTROLLER sThermalController; ///< Thermal controller stub. + USHORT Reserved4[2]; ///< Reserved + UCHAR Reserved5; ///< Reserved + USHORT Reserved6; ///< Reserved + USHORT usFormatID; ///< Format ID + USHORT Reserved7[1]; ///< Reserved + USHORT usExtendendedHeaderOffset; ///< Extended header offset +} ATOM_PPLIB_POWERPLAYTABLE3; + +#pragma pack (pop) + + +AGESA_STATUS +GfxPowerPlayBuildTable ( + OUT VOID *Buffer, + IN GFX_PLATFORM_CONFIG *Gfx + ); + + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c new file mode 100644 index 0000000..a01e6e7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c @@ -0,0 +1,225 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Supporting services to collect discrete GFX card info + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbCommonLib.h" +#include "GnbGfxInitLibV1.h" +#include "GfxCardInfo.h" +#include "GnbRegistersLN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GNBGFXINITLIBV1_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if GFX controller fused off + * + * + * @param[in] StdHeader Standard configuration header + * @retval TRUE Gfx controller present and available + */ +BOOLEAN +GfxLibIsControllerPresent ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return GnbLibPciIsDevicePresent (MAKE_SBDFO (0, 0, 1, 0, 0), StdHeader); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Init Gfx SSID Registers + * + * + * + * @param[in] Gfx Pointer to global GFX configuration + * @retval AGESA_STATUS Always succeeds + */ + +AGESA_STATUS +GfxInitSsid ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + AGESA_STATUS Status; + UINT32 TempData; + PCI_ADDR IgpuAddress; + PCI_ADDR HdaudioAddress; + + Status = AGESA_SUCCESS; + TempData = 0; + + IgpuAddress = Gfx->GfxPciAddress; + HdaudioAddress = Gfx->GfxPciAddress; + HdaudioAddress.Address.Function = 1; + + // Set SSID for internal GPU + if (UserOptions.CfgGnbIGPUSSID != 0) { + GnbLibPciRMW ((IgpuAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, UserOptions.CfgGnbIGPUSSID, GnbLibGetHeader (Gfx)); + } else { + GnbLibPciRead (IgpuAddress.AddressValue, AccessS3SaveWidth32, &TempData, GnbLibGetHeader (Gfx)); + GnbLibPciRMW ((IgpuAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, TempData, GnbLibGetHeader (Gfx)); + } + + // Set SSID for internal HD Audio + if (UserOptions.CfgGnbHDAudioSSID != 0) { + GnbLibPciRMW ((HdaudioAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, UserOptions.CfgGnbHDAudioSSID, GnbLibGetHeader (Gfx)); + } else { + GnbLibPciRead (HdaudioAddress.AddressValue, AccessS3SaveWidth32, &TempData, GnbLibGetHeader (Gfx)); + GnbLibPciRMW ((HdaudioAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, TempData, GnbLibGetHeader (Gfx)); + } + + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Copy memory content to FB + * + * + * @param[in] Source Pointer to source + * @param[in] FbOffset FB offset + * @param[in] Length The length to copy + * @param[in] Gfx Pointer to global GFX configuration + * + */ +VOID +GfxLibCopyMemToFb ( + IN VOID *Source, + IN UINT32 FbOffset, + IN UINT32 Length, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + GMMx00_STRUCT GMMx00; + GMMx04_STRUCT GMMx04; + UINT32 Index; + for (Index = 0; Index < Length; Index = Index + 4 ) { + GMMx00.Value = 0x80000000 | (FbOffset + Index); + GMMx04.Value = *(UINT32*) ((UINT8*)Source + Index); + GnbLibMemWrite (Gfx->GmmBase + GMMx00_ADDRESS, AccessWidth32, &GMMx00.Value, GnbLibGetHeader (Gfx)); + GnbLibMemWrite (Gfx->GmmBase + GMMx04_ADDRESS, AccessWidth32, &GMMx04.Value, GnbLibGetHeader (Gfx)); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Set iGpu VGA mode + * + * + * @param[in] Gfx Pointer to global GFX configuration + * + */ +VOID +GfxLibSetiGpuVgaMode ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + GnbLibPciIndirectRMW ( + GNB_SBDFO | D0F0x60_ADDRESS, + D0F0x64_x1D_ADDRESS | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + (UINT32) ~D0F0x64_x1D_VgaEn_MASK, + ((Gfx->iGpuVgaMode == iGpuVgaAdapter) ? 1 : 0) << D0F0x64_x1D_VgaEn_OFFSET, + GnbLibGetHeader (Gfx) + ); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h new file mode 100644 index 0000000..eb68a44 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h @@ -0,0 +1,107 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Gfx Library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + +#ifndef _GNBGFXINITLIBV1_H_ +#define _GNBGFXINITLIBV1_H_ + +#include "GnbPcie.h" +#include "GnbGfx.h" +#include "GfxEnumConnectors.h" +#include "GfxPowerPlayTable.h" +#include "GfxCardInfo.h" + +BOOLEAN +GfxLibIsControllerPresent ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GfxInitSsid ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + + +VOID +GfxLibCopyMemToFb ( + IN VOID *Source, + IN UINT32 FbOffset, + IN UINT32 Length, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxLibSetiGpuVgaMode ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c new file mode 100644 index 0000000..037eadd --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c @@ -0,0 +1,493 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbTable.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "GnbGfxInitLibV1.h" +#include "GnbGfxConfig.h" +#include "GnbGfxFamServices.h" +#include "GfxLibTN.h" +#include "GnbRegistersTN.h" +#include "GnbInitTN.h" +#include "GnbRegisterAccTN.h" +#include "GnbHandleLib.h" +#include "GnbTimerLib.h" +#include "cpuFamilyTranslation.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXENVINITTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_TABLE ROMDATA GfxEnvInitTableTN[]; +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GfxEnvInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Shut Down Disabled SIMDs + * + * @param[in] Property GNB property + * @param[in] Gfx Pointer to global GFX configuration + * @retval AGESA_STATUS + */ + +STATIC AGESA_STATUS +GfxShutDownDisabledSimdsTN ( + IN UINT32 Property, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + ex1006_STRUCT ex1006 ; + ex1009_STRUCT ex1009; + D0F0xBC_xE03002F8_STRUCT D0F0xBC_xE03002F8; + D0F0xBC_xE03002FC_STRUCT D0F0xBC_xE03002FC; + D0F0xBC_xE0300054_STRUCT GfxChainPgfsmConfig; + UINT8 n; + UINT32 Mask; + CPU_LOGICAL_ID LogicalId; + GNB_HANDLE *GnbHandle; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxShutDownDisabledSimdsTN Enter\n"); + + GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx)); + ASSERT (GnbHandle != NULL); + GetLogicalIdOfSocket (GnbGetSocketId (GnbHandle), &LogicalId, GnbLibGetHeader (Gfx)); + + GfxChainPgfsmConfig.Value = 0; + GfxChainPgfsmConfig.Field.PowerDown = 1; + GfxChainPgfsmConfig.Field.P2Select = 1; + GfxChainPgfsmConfig.Field.FsmAddr = 0xFF; + + //Step 1: Read fuse to see which SIMD(s) have been disabled + GnbRegisterReadTN (TYPE_D0F0xBC , 0xe000101c , &ex1006.Value, 0, GnbLibGetHeader (Gfx)); + + //Step 2: Check which SIMD has been disabled + for (n = 0; n < 6; n++) { + if (((Property & TABLE_PROPERTY_IGFX_DISABLED) != 0) || ((ex1006.Field.ex1006_0 >> n) & 0x1)) { + IDS_HDT_CONSOLE (GNB_TRACE, "Disable SIMD %d\n", n); + //Step 3: Make sure PGFSM has been programmed in GFX Power Island. + //Step 4: Make sure SCLK frequency is below 400Mhz + //Step 5: Enable PGFSM clock + GnbRegisterReadTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, 0, GnbLibGetHeader (Gfx)); + ex1009.Value |= (0x1 << (0 + n)); + GnbRegisterWriteTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + //Step 6 + GnbRegisterWriteTN (TYPE_D0F0xBC, (D0F0xBC_xE0300054_ADDRESS + (n * 0x1C)), &GfxChainPgfsmConfig.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + //Step 7 + Mask = (UINT32) (0x1F << (n * 5)); + do { + GnbRegisterReadTN (D0F0xBC_xE03002F8_TYPE, D0F0xBC_xE03002F8_ADDRESS, &D0F0xBC_xE03002F8.Value, 0, GnbLibGetHeader (Gfx)); + } while ((D0F0xBC_xE03002F8.Value & Mask )!= 0); + //Step 8: Restore previous SCLK divider + if ((LogicalId.Revision & 0x0000000000000100ull ) != 0x0000000000000100ull ) { + do { + GnbRegisterReadTN (D0F0xBC_xE03002FC_TYPE, D0F0xBC_xE03002FC_ADDRESS, &D0F0xBC_xE03002FC.Value, 0, GnbLibGetHeader (Gfx)); + } while ((D0F0xBC_xE03002FC.Value & Mask )!= Mask); + } else { + } + //Step 10: Turn off PGFSM clock + GnbRegisterReadTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, 0, GnbLibGetHeader (Gfx)); + ex1009.Value &= (~ (UINT64) (0x1 << (0 + n))); + GnbRegisterWriteTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + } + } + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxShutDownDisabledSimdsTN Exit\n"); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Shut Down Disabled SIMDs + * + * + * @param[in] Gfx Pointer to global GFX configuration + * @retval AGESA_STATUS + */ + +STATIC AGESA_STATUS +GfxShutDownDisabledRbsTN ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + ex1006_STRUCT ex1006 ; + D0F0xBC_xE0003024_STRUCT D0F0xBC_xE0003024; + D0F0xBC_xE03000FC_STRUCT D0F0xBC_xE03000FC; + D0F0xBC_xE0300100_STRUCT D0F0xBC_xE0300100; + ex1009_STRUCT ex1009 ; + D0F0xBC_xE03002F4_STRUCT D0F0xBC_xE03002F4; + D0F0xBC_xE03002E4_STRUCT D0F0xBC_xE03002E4; + UINT8 i; + UINT8 RbNumber; + UINT32 Mask1; + UINT32 Mask2; + + D0F0xBC_xE03000FC.Value = 0; + D0F0xBC_xE03000FC.Field.WriteOp = 1; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxShutDownDisabledRbsTN Enter\n"); + + //Step 1: Read fuse to see which SIMD(s) have been disabled + GnbRegisterReadTN (TYPE_D0F0xBC , 0xe000101c , &ex1006.Value, 0, GnbLibGetHeader (Gfx)); + + //Step 2: Power down disabled RB + if (ex1006.Field.ex1006_1 == 0x1) { + RbNumber = 0; + Mask1 = 0x3FFFA; + Mask2 = 0x5; + } else if (ex1006.Field.ex1006_1 == 0x2) { + RbNumber = 1; + Mask1 = 0x3FFF5; + Mask2 = 0xA; + } else { + return AGESA_SUCCESS; + } + //Step 3: Enable PGFSM commands during reset + GnbRegisterReadTN (D0F0xBC_xE0003024_TYPE, D0F0xBC_xE0003024_ADDRESS, &D0F0xBC_xE0003024.Value, 0, GnbLibGetHeader (Gfx)); + D0F0xBC_xE0003024.Value |= 0x1; + GnbRegisterWriteTN (D0F0xBC_xE0003024_TYPE, D0F0xBC_xE0003024_ADDRESS, &D0F0xBC_xE0003024.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + + //Step 4: Make sure PGFSM has been programmed before sending power down command. + //CB0 = 0, DB0 = 2, CB1 = 1, DB1 = 3 + for (i = RbNumber; i < 4; i += 2) { + D0F0xBC_xE0300100.Value = (5 << 16 ) | (4 << 8 ) | (10 << 0 ); //reg0 + GnbRegisterWriteTN (D0F0xBC_xE0300100_TYPE, D0F0xBC_xE0300100_ADDRESS, &D0F0xBC_xE0300100.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + D0F0xBC_xE03000FC.Field.FsmAddr = i; + D0F0xBC_xE03000FC.Field.RegAddr = 2 ; + GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbLibStallS3Save (1, GnbLibGetHeader (Gfx)); + + D0F0xBC_xE0300100.Value = (50 << 0 ) | (50 << 12 ); //reg1 + GnbRegisterWriteTN (D0F0xBC_xE0300100_TYPE, D0F0xBC_xE0300100_ADDRESS, &D0F0xBC_xE0300100.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + D0F0xBC_xE03000FC.Field.RegAddr = 3 ; + GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbLibStallS3Save (1, GnbLibGetHeader (Gfx)); + + D0F0xBC_xE0300100.Value = 0; //control + GnbRegisterWriteTN (D0F0xBC_xE0300100_TYPE, D0F0xBC_xE0300100_ADDRESS, &D0F0xBC_xE0300100.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + D0F0xBC_xE03000FC.Field.RegAddr = 1 ; + GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbLibStallS3Save (1, GnbLibGetHeader (Gfx)); + } + //Step 5: Make sure SCLK frequency is below 400Mhz + //Step 6: Enable PGFSM clock + GnbRegisterReadTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, 0, GnbLibGetHeader (Gfx)); + ex1009.Field.ex1009_1 = 1; + GnbRegisterWriteTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + + //Step 7 + D0F0xBC_xE03000FC.Value = 0; + D0F0xBC_xE03000FC.Field.PowerDown = 1; + D0F0xBC_xE03000FC.Field.P1Select = 1; + D0F0xBC_xE03000FC.Field.P2Select = 1; + D0F0xBC_xE03000FC.Field.FsmAddr = RbNumber; + GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbLibStallS3Save (1, GnbLibGetHeader (Gfx)); + + //Step 8 + D0F0xBC_xE03000FC.Field.FsmAddr = RbNumber + 1; + GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbLibStallS3Save (1, GnbLibGetHeader (Gfx)); + + //Step 9: Wait for isolation to be asserted for RB0/RB1 + do { + GnbRegisterReadTN (D0F0xBC_xE03002F4_TYPE, D0F0xBC_xE03002F4_ADDRESS, &D0F0xBC_xE03002F4.Value, 0, GnbLibGetHeader (Gfx)); + } while ((D0F0xBC_xE03002F4.Value & Mask1 )!= 0); + //Step 10: Restore previous SCLK divider + //Step 11: Wait for PSO daughter to be asserted for RB0/RB1 + do { + GnbRegisterReadTN (D0F0xBC_xE03002E4_TYPE, D0F0xBC_xE03002E4_ADDRESS, &D0F0xBC_xE03002E4.Value, 0, GnbLibGetHeader (Gfx)); + } while ((D0F0xBC_xE03002E4.Value & Mask2 )!= Mask2); + + //Step 12: Set PGFSM power up override bits so SMU will not power up disabled RB + D0F0xBC_xE0300100.Value = 0x3 << 11; + D0F0xBC_xE03000FC.Value = 0; + D0F0xBC_xE03000FC.Field.RegAddr = 1 ; + GnbRegisterWriteTN (D0F0xBC_xE0300100_TYPE, D0F0xBC_xE0300100_ADDRESS, &D0F0xBC_xE0300100.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + D0F0xBC_xE03000FC.Field.FsmAddr = RbNumber; + GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbLibStallS3Save (1, GnbLibGetHeader (Gfx)); + D0F0xBC_xE03000FC.Field.FsmAddr = RbNumber + 1; + GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbLibStallS3Save (1, GnbLibGetHeader (Gfx)); + + //Step 13: Turn off PGFSM clock + GnbRegisterReadTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, 0, GnbLibGetHeader (Gfx)); + ex1009.Field.ex1009_1 = 1; + GnbRegisterWriteTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + + //Step 14: Disable PGFSM commands during reset + GnbRegisterReadTN (D0F0xBC_xE0003024_TYPE, D0F0xBC_xE0003024_ADDRESS, &D0F0xBC_xE0003024.Value, 0, GnbLibGetHeader (Gfx)); + D0F0xBC_xE0003024.Value &= 0xFFFFFFFE; + GnbRegisterWriteTN (D0F0xBC_xE0003024_TYPE, D0F0xBC_xE0003024_ADDRESS, &D0F0xBC_xE0003024.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxShutDownDisabledRbsTN Exit\n"); + + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize GFX straps. + * + * + * @param[in] Gfx Pointer to global GFX configuration + * @retval AGESA_STATUS + */ + +STATIC AGESA_STATUS +GfxEnvInitTN ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + D0F0x64_x1C_STRUCT D0F0x64_x1C; + D0F0x64_x1D_STRUCT D0F0x64_x1D; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxEnvInitTN Enter\n"); + + GnbLibPciIndirectRead ( + GNB_SBDFO | D0F0x60_ADDRESS, + D0F0x64_x1C_ADDRESS | IOC_WRITE_ENABLE, + AccessWidth32, + &D0F0x64_x1C.Value, + GnbLibGetHeader (Gfx) + ); + + GnbLibPciIndirectRead ( + GNB_SBDFO | D0F0x60_ADDRESS, + D0F0x64_x1D_ADDRESS | IOC_WRITE_ENABLE, + AccessWidth32, + &D0F0x64_x1D.Value, + GnbLibGetHeader (Gfx) + ); + + D0F0x64_x1C.Field.AudioNonlegacyDeviceTypeEn = 0x0; + D0F0x64_x1C.Field.F0NonlegacyDeviceTypeEn = 0x0; + + D0F0x64_x1D.Field.IntGfxAsPcieEn = 0x1; + D0F0x64_x1C.Field.RcieEn = 0x1; + + D0F0x64_x1D.Field.VgaEn = 0x1; + + D0F0x64_x1C.Field.AudioEn = Gfx->GnbHdAudio; + D0F0x64_x1C.Field.F0En = 0x1; + D0F0x64_x1C.Field.RegApSize = 0x1; + + if (Gfx->UmaInfo.UmaSize > 128 * 0x100000) { + D0F0x64_x1C.Field.MemApSize = 0x1; + } else if (Gfx->UmaInfo.UmaSize > 64 * 0x100000) { + D0F0x64_x1C.Field.MemApSize = 0x0; + } else if (Gfx->UmaInfo.UmaSize > 32 * 0x100000) { + D0F0x64_x1C.Field.MemApSize = 0x2; + } else { + D0F0x64_x1C.Field.MemApSize = 0x3; + } + GnbLibPciIndirectWrite ( + GNB_SBDFO | D0F0x60_ADDRESS, + D0F0x64_x1D_ADDRESS | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + &D0F0x64_x1D.Value, + GnbLibGetHeader (Gfx) + ); + + GnbLibPciIndirectWrite ( + GNB_SBDFO | D0F0x60_ADDRESS, + D0F0x64_x1C_ADDRESS | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + &D0F0x64_x1C.Value, + GnbLibGetHeader (Gfx) + ); + + D0F0x64_x1C.Field.WriteDis = 0x1; + + GnbLibPciIndirectWrite ( + GNB_SBDFO | D0F0x60_ADDRESS, + D0F0x64_x1C_ADDRESS | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + &D0F0x64_x1C.Value, + GnbLibGetHeader (Gfx) + ); + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxEnvInitTN Exit\n"); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GFX at Env Post. + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + + +AGESA_STATUS +GfxEnvInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + GFX_PLATFORM_CONFIG *Gfx; + GNB_HANDLE *GnbHandle; + UINT32 Property; + BOOLEAN ShutDownDisabledSimd; + BOOLEAN ShutDownDisabledRb; + UINT8 SclkDid; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxEnvInterfaceTN Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Property = TABLE_PROPERTY_DEAFULT; + ShutDownDisabledSimd = GnbBuildOptions.CfgUnusedSimdPowerGatingEnable; + ShutDownDisabledRb = GnbBuildOptions.CfgUnusedRbPowerGatingEnable; + + Status = GfxLocateConfigData (StdHeader, &Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + if (Gfx->UmaInfo.UmaMode != UMA_NONE) { + Status = GfxEnvInitTN (Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + } else { + GfxFmDisableController (StdHeader); + Property |= TABLE_PROPERTY_IGFX_DISABLED; + } + } else { + GfxFmDisableController (StdHeader); + Property |= TABLE_PROPERTY_IGFX_DISABLED; + } + // + // Set sclk to 100Mhz + // + SclkDid = GfxRequestSclkTNS3Save ( + GfxLibCalculateDidTN (98 * 100, StdHeader), + StdHeader + ); + + GnbHandle = GnbGetHandle (StdHeader); + ASSERT (GnbHandle != NULL); + Status = GnbProcessTable ( + GnbHandle, + GfxEnvInitTableTN, + Property, + GNB_TABLE_FLAGS_FORCE_S3_SAVE, + StdHeader + ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + if (ShutDownDisabledSimd == TRUE) { + GfxShutDownDisabledSimdsTN (Property, Gfx); + } + + if ((Property & TABLE_PROPERTY_IGFX_DISABLED) != 0) { + if (ShutDownDisabledRb == TRUE) { + GfxShutDownDisabledRbsTN (Gfx); + } + } + // + // Restore Sclk + // + GfxRequestSclkTNS3Save ( + SclkDid, + StdHeader + ); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxEnvInterfaceTN Exit [0x%x]\n", AgesaStatus); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c new file mode 100644 index 0000000..1cd96d3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c @@ -0,0 +1,595 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 64152 $ @e $Date: 2012-01-16 21:38:07 -0600 (Mon, 16 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbCommonLib.h" +#include "GnbTable.h" +#include "GnbPcieConfig.h" +#include "GnbRegisterAccTN.h" +#include "cpuFamilyTranslation.h" +#include "GnbRegistersTN.h" +#include "GfxLibTN.h" +#include "GfxGmcInitTN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXGMCINITTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_TABLE ROMDATA GfxGmcColockGatingDisableTN []; +extern GNB_TABLE ROMDATA GfxGmcInitTableTN []; +extern GNB_TABLE ROMDATA GfxGmcColockGatingEnableTN []; + + +#define GNB_GFX_DRAM_CH_0_PRESENT 1 +#define GNB_GFX_DRAM_CH_1_PRESENT 2 + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +DCT_REGISTER_ENTRY DctRegisterTable [] = { + { + TYPE_D18F2_dct0, + D18F2x94_dct0_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x94_dct0) + }, + { + TYPE_D18F2_dct1, + D18F2x94_dct1_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x94_dct1) + }, + { + TYPE_D18F2_dct0, + D18F2x2E0_dct0_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x2E0_dct0) + }, + { + TYPE_D18F2_dct1, + D18F2x2E0_dct1_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x2E0_dct1) + }, + { + TYPE_D18F2_dct0_mp0, + D18F2x200_dct0_mp0_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x200_dct0_mp0) + }, + { + TYPE_D18F2_dct0_mp1, + D18F2x200_dct0_mp1_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x200_dct0_mp1) + }, + { + TYPE_D18F2_dct1_mp0, + D18F2x200_dct1_mp0_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x200_dct1_mp0) + }, + { + TYPE_D18F2_dct1_mp1, + D18F2x200_dct1_mp1_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x200_dct1_mp1) + }, + { + TYPE_D18F2_dct0_mp0, + D18F2x204_dct0_mp0_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x204_dct0_mp0) + }, + { + TYPE_D18F2_dct0_mp1, + D18F2x204_dct0_mp1_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x204_dct0_mp1) + }, + { + TYPE_D18F2_dct1_mp0, + D18F2x204_dct1_mp0_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x204_dct1_mp0) + }, + { + TYPE_D18F2_dct1_mp1, + D18F2x204_dct1_mp1_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x204_dct1_mp1) + }, + { + TYPE_D18F2_dct0_mp0, + D18F2x22C_dct0_mp0_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x22C_dct0_mp0) + }, + { + TYPE_D18F2_dct0_mp1, + D18F2x22C_dct0_mp1_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x22C_dct0_mp1) + }, + { + TYPE_D18F2_dct1_mp0, + D18F2x22C_dct1_mp0_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x22C_dct1_mp0) + }, + { + TYPE_D18F2_dct1_mp1, + D18F2x22C_dct1_mp1_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x22C_dct1_mp1) + }, + { + TYPE_D18F2_dct0_mp0, + D18F2x21C_dct0_mp0_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x21C_dct0_mp0) + }, + { + TYPE_D18F2_dct0_mp1, + D18F2x21C_dct0_mp1_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x21C_dct0_mp1) + }, + { + TYPE_D18F2_dct1_mp0, + D18F2x21C_dct1_mp0_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x21C_dct1_mp0) + }, + { + TYPE_D18F2_dct1_mp1, + D18F2x21C_dct1_mp1_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x21C_dct1_mp1) + }, + { + TYPE_D18F2_dct0_mp0, + D18F2x20C_dct0_mp0_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x20C_dct0_mp0) + }, + { + TYPE_D18F2_dct0_mp1, + D18F2x20C_dct0_mp1_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x20C_dct0_mp1) + }, + { + TYPE_D18F2_dct1_mp0, + D18F2x20C_dct1_mp0_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x20C_dct1_mp0) + }, + { + TYPE_D18F2_dct1_mp1, + D18F2x20C_dct1_mp1_ADDRESS, + (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x20C_dct1_mp1) + } +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize Fb location + * + * + * + * @param[in] Gfx Pointer to global GFX configuration + * + */ +STATIC VOID +GfxGmcInitializeFbLocationTN ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + GMMx2024_STRUCT GMMx2024; + GMMx2068_STRUCT GMMx2068; + GMMx2C04_STRUCT GMMx2C04; + GMMx5428_STRUCT GMMx5428; + UINT64 FBBase; + UINT64 FBTop; + FBBase = 0x0F00000000; + FBTop = FBBase + Gfx->UmaInfo.UmaSize - 1; + GMMx2024.Value = 0; + GMMx2C04.Value = 0; + GMMx2024.Field.FB_BASE = (UINT16) (FBBase >> 24); + GMMx2024.Field.FB_TOP = (UINT16) (FBTop >> 24); + GMMx2068.Field.FB_OFFSET = (UINT32) (Gfx->UmaInfo.UmaBase >> 22); + GMMx2C04.Field.NONSURF_BASE = (UINT32) (FBBase >> 8); + GMMx5428.Field.CONFIG_MEMSIZE = Gfx->UmaInfo.UmaSize >> 20; + GnbRegisterWriteTN (GMMx2024_TYPE, GMMx2024_ADDRESS, &GMMx2024.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteTN (GMMx2068_TYPE, GMMx2068_ADDRESS, &GMMx2068.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteTN (GMMx2C04_TYPE, GMMx2C04_ADDRESS, &GMMx2C04.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteTN (GMMx5428_TYPE, GMMx5428_ADDRESS, &GMMx5428.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get Sequencer model info + * + * + * @param[out] DctChannelInfo Various DCT/GMM info + * @param[in] Gfx Pointer to global GFX configuration + */ + +STATIC VOID +GfxGmcDctMemoryChannelInfoTN ( + OUT DCT_CHANNEL_INFO *DctChannelInfo, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + + UINT32 Index; + UINT32 Value; + + for (Index = 0; Index < (sizeof (DctRegisterTable) / sizeof (DCT_REGISTER_ENTRY)); Index++) { + GnbRegisterReadTN ( + DctRegisterTable[Index].RegisterSpaceType, + DctRegisterTable[Index].Address, + &Value, + 0, + GnbLibGetHeader (Gfx) + ); + *(UINT32 *)((UINT8 *) DctChannelInfo + DctRegisterTable[Index].DctChannelInfoTableOffset) = Value; + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize sequencer model + * + * + * + * @param[in] Gfx Pointer to global GFX configuration + * + */ +STATIC VOID +GfxGmcInitializeSequencerTN ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + + UINT32 memps0_freq; + UINT32 memps1_freq; + UINT32 scale_mp0; + UINT32 scale_mp1; + UINT8 DramChannelPresent; + ex1047_STRUCT ex1047 ; + ex1048_STRUCT ex1048 ; + ex1060_STRUCT ex1060 ; + ex1061_STRUCT ex1061 ; + ex1062_STRUCT ex1062 ; + DCT_CHANNEL_INFO DctChannel; + D18F5x170_STRUCT D18F5x170; + ex1012_STRUCT ex1012 ; + ex1034_STRUCT ex1034 ; + + GfxGmcDctMemoryChannelInfoTN (&DctChannel, Gfx); + + DramChannelPresent = 0; + if (!DctChannel.D18F2x94_dct1.Field.DisDramInterface) { + DramChannelPresent |= GNB_GFX_DRAM_CH_1_PRESENT; + } + + if (!DctChannel.D18F2x94_dct0.Field.DisDramInterface) { + //if (channel 0 present) + //memps0_freq = extract frequency from DRAM Configuration High <D18F2x094_dct[0]>[4:0] encoding + //memps1_freq = extract frequency from Memory P-state Control Status <D18F2x2E0_dct[0]>[28:24] encoding + DramChannelPresent |= GNB_GFX_DRAM_CH_0_PRESENT; + memps0_freq = GfxLibExtractDramFrequency ((UINT8) DctChannel.D18F2x94_dct0.Field.MemClkFreq, GnbLibGetHeader (Gfx)); + memps1_freq = GfxLibExtractDramFrequency ((UINT8) DctChannel.D18F2x2E0_dct0.Field.M1MemClkFreq, GnbLibGetHeader (Gfx)); + } else { + //memps0_freq = extract frequency from DRAM Configuration High <D18F2x094_dct[1]>[4:0] encoding + //memps1_freq = extract frequency from Memory P-state Control Status <D18F2x2E0_dct[1]>[28:24] encoding + memps0_freq = GfxLibExtractDramFrequency ((UINT8) DctChannel.D18F2x94_dct1.Field.MemClkFreq, GnbLibGetHeader (Gfx)); + memps1_freq = GfxLibExtractDramFrequency ((UINT8) DctChannel.D18F2x2E0_dct1.Field.M1MemClkFreq, GnbLibGetHeader (Gfx)); + } + + GnbRegisterReadTN (D18F5x170_TYPE, D18F5x170_ADDRESS, &D18F5x170.Value, 0, GnbLibGetHeader (Gfx)); + if (D18F5x170.Field.MemPstateDis == 1) { + memps1_freq = memps0_freq; + } + + //scale_mp0 = sclk_max_freq / memps0_freq + //scale_mp1 = sclk_max_freq / memps1_freq + //Multiply it by 100 to avoid dealing with floating point values + scale_mp0 = (GfxLibGetMaxSclk (GnbLibGetHeader (Gfx)) * 100) / memps0_freq; + scale_mp1 = (GfxLibGetMaxSclk (GnbLibGetHeader (Gfx)) * 100) / memps1_freq; + + GnbRegisterReadTN (TYPE_GMM , 0x2774 , &ex1047.Value, 0, GnbLibGetHeader (Gfx)); + GnbRegisterReadTN (TYPE_GMM , 0x2778 , &ex1048.Value, 0, GnbLibGetHeader (Gfx)); + GnbRegisterReadTN (TYPE_GMM , 0x27f0 , &ex1060.Value, 0, GnbLibGetHeader (Gfx)); + GnbRegisterReadTN (TYPE_GMM , 0x27fc , &ex1061.Value, 0, GnbLibGetHeader (Gfx)); + + if (((DramChannelPresent & GNB_GFX_DRAM_CH_0_PRESENT) != 0) && ((DramChannelPresent & GNB_GFX_DRAM_CH_1_PRESENT) != 0)) { + ex1047.Field.ex1047_0 = (MIN (DctChannel.D18F2x200_dct0_mp0.Field.Trcd, DctChannel.D18F2x200_dct1_mp0.Field.Trcd) * scale_mp0) / 100; + ex1047.Field.ex1047_1 = ex1047.Field.ex1047_0; + ex1047.Field.ex1047_2 = (MIN ((DctChannel.D18F2x204_dct0_mp0.Field.Trc - DctChannel.D18F2x200_dct0_mp0.Field.Trcd), + (DctChannel.D18F2x204_dct1_mp0.Field.Trc - DctChannel.D18F2x200_dct1_mp0.Field.Trcd)) * scale_mp0) / 100; + ex1047.Field.ex1047_3 = ex1047.Field.ex1047_2; + + ex1048.Field.ex1048_0 = (MIN (DctChannel.D18F2x204_dct0_mp0.Field.Trc, DctChannel.D18F2x204_dct1_mp0.Field.Trc) * scale_mp0) / 100; + ex1048.Field.ex1048_1 = (MIN (DctChannel.D18F2x200_dct0_mp0.Field.Trp, DctChannel.D18F2x200_dct1_mp0.Field.Trp) * scale_mp0) / 100; + ex1048.Field.ex1048_2 = (MIN ((DctChannel.D18F2x22C_dct0_mp0.Field.Twr + DctChannel.D18F2x200_dct0_mp0.Field.Trp), + (DctChannel.D18F2x22C_dct1_mp0.Field.Twr + DctChannel.D18F2x200_dct1_mp0.Field.Trp)) * scale_mp0) / 100; + ex1048.Field.ex1048_3 = ((MIN ((DctChannel.D18F2x20C_dct0_mp0.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct0_mp0.Field.Twtr + DctChannel.D18F2x21C_dct0_mp0.Field.TrwtTO), + (DctChannel.D18F2x20C_dct1_mp0.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct1_mp0.Field.Twtr + DctChannel.D18F2x21C_dct1_mp0.Field.TrwtTO)) / 2) * scale_mp0) / 100; + + ex1060.Field.ex1060_0 = (MIN (DctChannel.D18F2x200_dct0_mp1.Field.Trcd, DctChannel.D18F2x200_dct1_mp1.Field.Trcd) * scale_mp1) / 100; + ex1060.Field.ex1060_1 = ex1060.Field.ex1060_0; + ex1060.Field.ex1060_2 = (MIN ((DctChannel.D18F2x204_dct0_mp1.Field.Trc - DctChannel.D18F2x200_dct0_mp1.Field.Trcd), + (DctChannel.D18F2x204_dct1_mp1.Field.Trc - DctChannel.D18F2x200_dct1_mp1.Field.Trcd)) * scale_mp1) / 100; + ex1060.Field.ex1060_3 = ex1060.Field.ex1060_2; + + ex1061.Field.ex1061_0 = (MIN (DctChannel.D18F2x204_dct0_mp1.Field.Trc, DctChannel.D18F2x204_dct1_mp1.Field.Trc) * scale_mp1) / 100; + ex1061.Field.ex1061_1 = (MIN (DctChannel.D18F2x200_dct0_mp1.Field.Trp, DctChannel.D18F2x200_dct1_mp1.Field.Trp) * scale_mp1) / 100; + ex1061.Field.ex1061_2 = (MIN ((DctChannel.D18F2x22C_dct0_mp1.Field.Twr + DctChannel.D18F2x200_dct0_mp1.Field.Trp), + (DctChannel.D18F2x22C_dct1_mp1.Field.Twr + DctChannel.D18F2x200_dct1_mp1.Field.Trp)) * scale_mp1) / 100; + ex1061.Field.ex1061_3 = ((MIN ((DctChannel.D18F2x20C_dct0_mp1.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct0_mp1.Field.Twtr + DctChannel.D18F2x21C_dct0_mp1.Field.TrwtTO), + (DctChannel.D18F2x20C_dct1_mp1.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct1_mp1.Field.Twtr + DctChannel.D18F2x21C_dct1_mp1.Field.TrwtTO)) / 2) * scale_mp1) / 100; + + } else if ((DramChannelPresent & GNB_GFX_DRAM_CH_0_PRESENT) != 0) { + ex1047.Field.ex1047_0 = (DctChannel.D18F2x200_dct0_mp0.Field.Trcd * scale_mp0) / 100; + ex1047.Field.ex1047_1 = ex1047.Field.ex1047_0; + ex1047.Field.ex1047_2 = ((DctChannel.D18F2x204_dct0_mp0.Field.Trc - DctChannel.D18F2x200_dct0_mp0.Field.Trcd) * scale_mp0) / 100; + ex1047.Field.ex1047_3 = ex1047.Field.ex1047_2; + + ex1048.Field.ex1048_0 = (DctChannel.D18F2x204_dct0_mp0.Field.Trc * scale_mp0) / 100; + ex1048.Field.ex1048_1 = (DctChannel.D18F2x200_dct0_mp0.Field.Trp * scale_mp0) / 100; + ex1048.Field.ex1048_2 = ((DctChannel.D18F2x22C_dct0_mp0.Field.Twr + DctChannel.D18F2x200_dct0_mp0.Field.Trp) * scale_mp0) / 100; + ex1048.Field.ex1048_3 = (((DctChannel.D18F2x20C_dct0_mp0.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct0_mp0.Field.Twtr + DctChannel.D18F2x21C_dct0_mp0.Field.TrwtTO) / 2) * scale_mp0) / 100; + + ex1060.Field.ex1060_0 = (DctChannel.D18F2x200_dct0_mp1.Field.Trcd * scale_mp1) / 100; + ex1060.Field.ex1060_1 = ex1060.Field.ex1060_0; + ex1060.Field.ex1060_2 = ((DctChannel.D18F2x204_dct0_mp1.Field.Trc - DctChannel.D18F2x200_dct0_mp1.Field.Trcd) * scale_mp1) / 100; + ex1060.Field.ex1060_3 = ex1060.Field.ex1060_2; + + ex1061.Field.ex1061_0 = (DctChannel.D18F2x204_dct0_mp1.Field.Trc * scale_mp1) / 100; + ex1061.Field.ex1061_1 = (DctChannel.D18F2x200_dct0_mp1.Field.Trp * scale_mp1) / 100; + ex1061.Field.ex1061_2 = ((DctChannel.D18F2x22C_dct0_mp1.Field.Twr + DctChannel.D18F2x200_dct0_mp1.Field.Trp) * scale_mp1) / 100; + ex1061.Field.ex1061_3 = (((DctChannel.D18F2x20C_dct0_mp1.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct0_mp1.Field.Twtr + DctChannel.D18F2x21C_dct0_mp1.Field.TrwtTO) / 2) * scale_mp1) / 100; + + } else { + ex1047.Field.ex1047_0 = (DctChannel.D18F2x200_dct1_mp0.Field.Trcd * scale_mp0) / 100; + ex1047.Field.ex1047_1 = ex1047.Field.ex1047_0; + ex1047.Field.ex1047_2 = ((DctChannel.D18F2x204_dct1_mp0.Field.Trc - DctChannel.D18F2x200_dct1_mp0.Field.Trcd) * scale_mp0) / 100; + ex1047.Field.ex1047_3 = ex1047.Field.ex1047_2; + + ex1048.Field.ex1048_0 = (DctChannel.D18F2x204_dct1_mp0.Field.Trc * scale_mp0) / 100; + ex1048.Field.ex1048_1 = (DctChannel.D18F2x200_dct1_mp0.Field.Trp * scale_mp0) / 100; + ex1048.Field.ex1048_2 = ((DctChannel.D18F2x22C_dct1_mp0.Field.Twr + DctChannel.D18F2x200_dct1_mp0.Field.Trp) * scale_mp0) / 100; + ex1048.Field.ex1048_3 = (((DctChannel.D18F2x20C_dct1_mp0.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct1_mp0.Field.Twtr + DctChannel.D18F2x21C_dct1_mp0.Field.TrwtTO) / 2) * scale_mp0) / 100; + + ex1060.Field.ex1060_0 = (DctChannel.D18F2x200_dct1_mp1.Field.Trcd * scale_mp1) / 100; + ex1060.Field.ex1060_1 = ex1060.Field.ex1060_0; + ex1060.Field.ex1060_2 = ((DctChannel.D18F2x204_dct1_mp1.Field.Trc - DctChannel.D18F2x200_dct1_mp1.Field.Trcd) * scale_mp1) / 100; + ex1060.Field.ex1060_3 = ex1060.Field.ex1060_2; + + ex1061.Field.ex1061_0 = (DctChannel.D18F2x204_dct1_mp1.Field.Trc * scale_mp1) / 100; + ex1061.Field.ex1061_1 = (DctChannel.D18F2x200_dct1_mp1.Field.Trp * scale_mp1) / 100; + ex1061.Field.ex1061_2 = ((DctChannel.D18F2x22C_dct1_mp1.Field.Twr + DctChannel.D18F2x200_dct1_mp1.Field.Trp) * scale_mp1) / 100; + ex1061.Field.ex1061_3 = (((DctChannel.D18F2x20C_dct1_mp1.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct1_mp1.Field.Twtr + DctChannel.D18F2x21C_dct1_mp1.Field.TrwtTO) / 2) * scale_mp1) / 100; + } + + GnbRegisterWriteTN (TYPE_GMM , 0x2774 , &ex1047.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteTN (TYPE_GMM , 0x2778 , &ex1048.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteTN (TYPE_GMM , 0x27f0 , &ex1060.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteTN (TYPE_GMM , 0x27fc , &ex1061.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + ex1062.Field.ex1062_0 = GfxLibGetNumberOfSclkPerDramBurst (scale_mp0, GnbLibGetHeader (Gfx)); + ex1062.Field.ex1062_1 = GfxLibGetNumberOfSclkPerDramBurst (scale_mp1, GnbLibGetHeader (Gfx)); + GnbRegisterWriteTN (TYPE_GMM , 0x2808 , &ex1062.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + + + //MC Performance settings base on memory channel configuration + //If 1 channel + ex1012.Value = 0x210; + ex1034.Value = 0x3; + if (((DramChannelPresent & GNB_GFX_DRAM_CH_0_PRESENT) != 0) && ((DramChannelPresent & GNB_GFX_DRAM_CH_1_PRESENT) != 0)) { + //If 2 channels + ex1012.Value = 0x1210; + ex1034.Value = 0xC3; + } + GnbRegisterWriteTN (TYPE_GMM , 0x2004 , &ex1012.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteTN (TYPE_GMM , 0x2214 , &ex1034.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * + * + * + * @param[in] Gfx Pointer to global GFX configuration + */ + +STATIC VOID +GfxGmcSecureGarlicAccessTN ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + ex1064_STRUCT ex1064 ; + ex1065_STRUCT ex1065 ; + GMMx287C_STRUCT GMMx287C; + + ex1064.Value = (UINT32) (Gfx->UmaInfo.UmaBase >> 20); + GnbRegisterWriteTN (TYPE_GMM , 0x2868 , &ex1064.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + ex1065.Value = (UINT32) (((Gfx->UmaInfo.UmaBase + Gfx->UmaInfo.UmaSize) >> 20) - 1); + GnbRegisterWriteTN (TYPE_GMM , 0x286c , &ex1065.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + // Areag FB - 32K reserved by VBIOS for SBIOS to use + GMMx287C.Value = (UINT32) ((Gfx->UmaInfo.UmaBase + Gfx->UmaInfo.UmaSize - 32 * 1024) >> 12); + GnbRegisterWriteTN (GMMx287C_TYPE, GMMx287C_ADDRESS, &GMMx287C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize C6 aperture location + * + * + * + * @param[in] Gfx Pointer to global GFX configuration + * + */ +STATIC VOID +GfxGmcInitializeC6LocationTN ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + D18F2x118_STRUCT D18F2x118; + D18F1x44_STRUCT D18F1x44; + GMMx2870_STRUCT GMMx2870; + GMMx2874_STRUCT GMMx2874; + + // From D18F1x[144:140,44:40] DRAM Base/Limit, + // {DramBase[47:24], 00_0000h} <= address[47:0] <= {DramLimit[47:24], FF_FFFFh}. + GnbRegisterReadTN (D18F1x44_TYPE, D18F1x44_ADDRESS, &D18F1x44.Value, 0, GnbLibGetHeader (Gfx)); + // + // base 39:20, base = Dram Limit + 1 + // ex: system 256 MB on Node 0, D18F1x44.Field.DramLimit_39_24_ = 0xE (240MB -1) + // Node DRAM D18F1x[144:140,44:40] CC6DRAMRange D18F4x128 D18F1x120 D18F1x124 + // 0 256MB 0MB ~ 240 MB - 1 240 MB ~ 256 MB - 1 0 0 MB, 256 MB - 1 + // + + // base 39:20 + GMMx2870.Value = ((D18F1x44.Field.DramLimit_39_24_ + 1) << 4); + // top 39:20 + GMMx2874.Value = (((D18F1x44.Field.DramLimit_39_24_ + 1) << 24) + (16 * 0x100000) - 1) >> 20; + + // Check C6 enable, D18F2x118[CC6SaveEn] + GnbRegisterReadTN (TYPE_D18F2 , 0x118 , &D18F2x118.Value, 0, GnbLibGetHeader (Gfx)); + + if (D18F2x118.Field.CC6SaveEn) { + + GnbRegisterWriteTN (GMMx2874_TYPE, GMMx2874_ADDRESS, &GMMx2874.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteTN (GMMx2870_TYPE, GMMx2870_ADDRESS, &GMMx2870.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize GMC + * + * + * + * @param[in] Gfx Pointer to global GFX configuration + * + */ + +AGESA_STATUS +GfxGmcInitTN ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + GMMx28D8_STRUCT GMMx28D8; + ex1017_STRUCT ex1017 ; + GNB_HANDLE *GnbHandle; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInitTN Enter\n"); + GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx)); + ASSERT (GnbHandle != NULL); + GnbProcessTable ( + GnbHandle, + GfxGmcColockGatingDisableTN, + 0, + GNB_TABLE_FLAGS_FORCE_S3_SAVE, + GnbLibGetHeader (Gfx) + ); + GfxGmcInitializeSequencerTN (Gfx); + GfxGmcInitializeFbLocationTN (Gfx); + GfxGmcSecureGarlicAccessTN (Gfx); + GfxGmcInitializeC6LocationTN (Gfx); + GnbProcessTable ( + GnbHandle, + GfxGmcInitTableTN, + 0, + GNB_TABLE_FLAGS_FORCE_S3_SAVE, + GnbLibGetHeader (Gfx) + ); + if (Gfx->GmcClockGating) { + GnbProcessTable ( + GnbHandle, + GfxGmcColockGatingEnableTN, + 0, + GNB_TABLE_FLAGS_FORCE_S3_SAVE, + GnbLibGetHeader (Gfx) + ); + } + if (Gfx->UmaSteering == excel993 ) { + ex1017.Value = 0x2; + GnbRegisterWriteTN (TYPE_GMM , 0x206c , &ex1017.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + } + IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE, Gfx, GnbLibGetHeader (Gfx)); + if (Gfx->GmcLockRegisters) { + GnbRegisterReadTN (GMMx28D8_TYPE, GMMx28D8_ADDRESS, &GMMx28D8.Value, 0, GnbLibGetHeader (Gfx)); + GMMx28D8.Field.CRITICAL_REGS_LOCK = 1; + GnbRegisterWriteTN (GMMx28D8_TYPE, GMMx28D8_ADDRESS, &GMMx28D8.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + } + if (Gfx->GmcPowerGating != GmcPowerGatingDisabled) { + } + IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInitTN Exit\n"); + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.h new file mode 100644 index 0000000..91de2f7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.h @@ -0,0 +1,121 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * various service procedures + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GFXGMCINITTN_H_ +#define _GFXGMCINITTN_H_ + +#include "GnbRegistersTN.h" + +AGESA_STATUS +GfxGmcInitTN ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +#pragma pack (push, 1) + +/// DCT channel information +typedef struct { + D18F2x94_dct0_STRUCT D18F2x94_dct0; ///< Register 0x94 + D18F2x94_dct1_STRUCT D18F2x94_dct1; ///< Register 0x94 + D18F2x2E0_dct0_STRUCT D18F2x2E0_dct0; ///< Register 0x2E0 + D18F2x2E0_dct1_STRUCT D18F2x2E0_dct1; ///< Register 0x2E0 + D18F2x200_dct0_mp0_STRUCT D18F2x200_dct0_mp0; ///< Register 0x200 + D18F2x200_dct0_mp1_STRUCT D18F2x200_dct0_mp1; ///< Register 0x200 + D18F2x200_dct1_mp0_STRUCT D18F2x200_dct1_mp0; ///< Register 0x200 + D18F2x200_dct1_mp1_STRUCT D18F2x200_dct1_mp1; ///< Register 0x200 + D18F2x204_dct0_mp0_STRUCT D18F2x204_dct0_mp0; ///< Register 0x204 + D18F2x204_dct0_mp1_STRUCT D18F2x204_dct0_mp1; ///< Register 0x204 + D18F2x204_dct1_mp0_STRUCT D18F2x204_dct1_mp0; ///< Register 0x204 + D18F2x204_dct1_mp1_STRUCT D18F2x204_dct1_mp1; ///< Register 0x204 + D18F2x22C_dct0_mp0_STRUCT D18F2x22C_dct0_mp0; ///< Register 0x22C + D18F2x22C_dct0_mp1_STRUCT D18F2x22C_dct0_mp1; ///< Register 0x22C + D18F2x22C_dct1_mp0_STRUCT D18F2x22C_dct1_mp0; ///< Register 0x22C + D18F2x22C_dct1_mp1_STRUCT D18F2x22C_dct1_mp1; ///< Register 0x22C + D18F2x21C_dct0_mp0_STRUCT D18F2x21C_dct0_mp0; ///< Register 0x21C + D18F2x21C_dct0_mp1_STRUCT D18F2x21C_dct0_mp1; ///< Register 0x21C + D18F2x21C_dct1_mp0_STRUCT D18F2x21C_dct1_mp0; ///< Register 0x21C + D18F2x21C_dct1_mp1_STRUCT D18F2x21C_dct1_mp1; ///< Register 0x21C + D18F2x20C_dct0_mp0_STRUCT D18F2x20C_dct0_mp0; ///< Register 0x20C + D18F2x20C_dct0_mp1_STRUCT D18F2x20C_dct0_mp1; ///< Register 0x20C + D18F2x20C_dct1_mp0_STRUCT D18F2x20C_dct1_mp0; ///< Register 0x20C + D18F2x20C_dct1_mp1_STRUCT D18F2x20C_dct1_mp1; ///< Register 0x20C +} DCT_CHANNEL_INFO; + +/// DCT_CHANNEL_INFO field entry +typedef struct { + UINT8 RegisterSpaceType; ///< Register type + UINT32 Address; ///< Register address + UINT16 DctChannelInfoTableOffset; ///< destination offset in DCT_CHANNEL_INFO table +} DCT_REGISTER_ENTRY; + +#pragma pack (pop) + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c new file mode 100644 index 0000000..15c0109 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c @@ -0,0 +1,922 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 64730 $ @e $Date: 2012-01-30 02:05:39 -0600 (Mon, 30 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "GeneralServices.h" +#include "Gnb.h" +#include "GnbFuseTable.h" +#include "GnbPcie.h" +#include "GnbGfx.h" +#include "GnbSbLib.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbGfxConfig.h" +#include "GnbGfxInitLibV1.h" +#include "GnbGfxFamServices.h" +#include "GnbRegistersTN.h" +#include "GnbRegisterAccTN.h" +#include "GnbNbInitLibV1.h" +#include "GfxConfigLib.h" +#include "GfxLibTN.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXINTEGRATEDINFOTABLETN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +#define GFX_REFCLK 100 // (in MHz) Reference clock is 100 MHz +#define GFX_NCLK_MIN 700 // (in MHz) Minimum value for NCLK is 700 MHz +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GfxIntInfoTableInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +CONST UINT8 DdiLaneConfigArrayTN [][4] = { + {31, 24, 1, 0}, + {24, 31, 0, 1}, + {24, 27, 0, 0}, + {27, 24, 0, 0}, + {28, 31, 1, 1}, + {31, 28, 1, 1}, + {32, 38, 2, 2}, + {32, 35, 2, 2}, + {35, 32, 2, 2}, + {8 , 15, 3, 3}, + {15, 8 , 3, 3}, + {12, 15, 3, 3}, + {15, 12, 3, 3}, + {16, 19, 4, 4}, + {19, 16, 4, 4}, + {16, 23, 4, 5}, + {23, 16, 5, 4}, + {20, 23, 5, 5}, + {23, 20, 5, 5}, +}; + + +/*----------------------------------------------------------------------------------------*/ +/** + * Init TN Support for eDP to Lvds translators + * + * + * @param[in] Engine Engine configuration info + * @param[in,out] Buffer Buffer pointer + * @param[in] Pcie PCIe configuration info + */ +VOID +STATIC +GfxIntegrateducEDPToLVDSRxIdCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 *uceDPToLVDSRxId; + uceDPToLVDSRxId = (UINT8*) Buffer; + // APU output DP signal to a 3rd party DP translator chip (Analogix, Parade etc), + // the chip is handled by the 3rd party DP Rx firmware and it does not require the AMD SW to have a special + // initialize/enable/disable sequence to control this chip, the AMD SW just follows the eDP spec + // to enable the LVDS panel through this chip. + + if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDPToLvds) { + *uceDPToLVDSRxId = eDP_TO_LVDS_COMMON_ID; + IDS_HDT_CONSOLE (GNB_TRACE, "Found 3rd party common EDPToLvds Connector\n"); + } + // APU output DP signal to a 3rd party DP translator chip which requires a AMD SW one time initialization + // to the chip based on the LVDS panel parameters ( such as power sequence time and panel SS parameter etc ). + // After that, the AMD SW does not need any specific enable/disable sequences to control this chip and just + // follows the eDP spec. to control the panel. + if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDPToRealtecLvds) { + *uceDPToLVDSRxId = eDP_TO_LVDS_REALTEK_ID; + IDS_HDT_CONSOLE (GNB_TRACE, "Found Realtec EDPToLvds Connector\n"); + } + +} + +/*----------------------------------------------------------------------------------------*/ +/** + *Init TN Nb p-State MemclkFreq + * + * + * @param[in] IntegratedInfoTable Integrated info table pointer + * @param[in] Gfx Gfx configuration info + */ + +STATIC VOID +GfxFillNbPstateMemclkFreqTN ( + IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + D18F2x94_dct0_STRUCT D18F2x94; + D18F2x2E0_dct0_STRUCT D18F2x2E0; + D18F5x160_STRUCT NbPstate; + UINT8 i; + UINT8 Channel; + ULONG memps0_freq; + ULONG memps1_freq; + + if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT0) != 0) { + Channel = 0; + } else { + Channel = 1; + } + + GnbRegisterReadTN ( + ((Channel == 0) ? D18F2x94_dct0_TYPE : D18F2x94_dct1_TYPE), + ((Channel == 0) ? D18F2x94_dct0_ADDRESS : D18F2x94_dct1_ADDRESS), + &D18F2x94.Value, + 0, + GnbLibGetHeader (Gfx) + ); + + GnbRegisterReadTN ( + ((Channel == 0) ? D18F2x2E0_dct0_TYPE : D18F2x2E0_dct1_TYPE), + ((Channel == 0) ? D18F2x2E0_dct0_ADDRESS : D18F2x2E0_dct1_ADDRESS), + &D18F2x2E0.Value, + 0, + GnbLibGetHeader (Gfx) + ); + + memps0_freq = 100 * GfxLibExtractDramFrequency ((UINT8) D18F2x94.Field.MemClkFreq, GnbLibGetHeader (Gfx)); + memps1_freq = 100 * GfxLibExtractDramFrequency ((UINT8) D18F2x2E0.Field.M1MemClkFreq, GnbLibGetHeader (Gfx)); + + for (i = 0; i < 4; i++) { + NbPstate.Value = 0; + GnbRegisterReadTN ( + TYPE_D18F5, + (D18F5x160_ADDRESS + (i * 4)), + &NbPstate.Value, + 0, + GnbLibGetHeader (Gfx) + ); + if (NbPstate.Field.NbPstateEn == 1) { + IntegratedInfoTable->ulNbpStateMemclkFreq[i] = (NbPstate.Field.MemPstate == 0) ? memps0_freq : memps1_freq; + } + } + +} + +/*----------------------------------------------------------------------------------------*/ +/** + *Init TN HTC Data + * + * + * @param[in] IntegratedInfoTable Integrated info table pointer + * @param[in] Gfx Gfx configuration info + */ + +STATIC VOID +GfxFillHtcDataTN ( + IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + D18F3x64_STRUCT D18F3x64; + + GnbRegisterReadTN ( + D18F3x64_TYPE, + D18F3x64_ADDRESS, + &D18F3x64.Value, + 0, + GnbLibGetHeader (Gfx) + ); + + if (D18F3x64.Field.HtcEn == 1) { + IntegratedInfoTable->ucHtcTmpLmt = (UCHAR) (D18F3x64.Field.HtcTmpLmt / 2 + 52); + IntegratedInfoTable->ucHtcHystLmt = (UCHAR) (D18F3x64.Field.HtcHystLmt / 2); + } else { + IntegratedInfoTable->ucHtcTmpLmt = 0; + IntegratedInfoTable->ucHtcHystLmt = 0; + } +} +/*----------------------------------------------------------------------------------------*/ +/** + * Get TN CSR phy self refresh power down mode. + * + * + * @param[in] Channel DCT controller index + * @param[in] StdHeader Standard configuration header + * @retval CsrPhySrPllPdMode + */ +STATIC UINT32 +GfxLibGetMemPhyPllPdModeTN ( + IN UINT8 Channel, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D18F2xA8_dct0_STRUCT D18F2xA8; + + GnbRegisterReadTN ( + ((Channel == 0) ? D18F2xA8_dct0_TYPE : D18F2xA8_dct1_TYPE), + ((Channel == 0) ? D18F2xA8_dct0_ADDRESS : D18F2xA8_dct1_ADDRESS), + &D18F2xA8.Value, + 0, + StdHeader + ); + + IDS_HDT_CONSOLE (GNB_TRACE, "MemPhyPllPdMode : %x\n", D18F2xA8.Field.MemPhyPllPdMode); + return D18F2xA8.Field.MemPhyPllPdMode; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get TN disable DLL shutdown in self-refresh mode. + * + * + * @param[in] Channel DCT controller index + * @param[in] StdHeader Standard configuration header + * @retval DisDllShutdownSR + */ +STATIC UINT32 +GfxLibGetDisDllShutdownSRTN ( + IN UINT8 Channel, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D18F2x90_dct0_STRUCT D18F2x90; + + GnbRegisterReadTN ( + ((Channel == 0) ? D18F2x90_dct0_TYPE : D18F2x90_dct1_TYPE), + ((Channel == 0) ? D18F2x90_dct0_ADDRESS : D18F2x90_dct1_ADDRESS), + &D18F2x90.Value, + 0, + StdHeader + ); + + IDS_HDT_CONSOLE (GNB_TRACE, "DisDllShutdownSR : %x\n", D18F2x90.Field.DisDllShutdownSR); + return D18F2x90.Field.DisDllShutdownSR; +} + +/*----------------------------------------------------------------------------------------*/ +/** + *Init TN NbPstateVid + * + * + * @param[in] IntegratedInfoTable Integrated info table pointer + * @param[in] Gfx Gfx configuration info + */ + +STATIC VOID +GfxFillNbPStateVidTN ( + IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + //TN Register Mapping for D18F5x1[6C:60] + D18F5x160_STRUCT NbPstate[4]; + D0F0xBC_x1F428_STRUCT D0F0xBC_x1F428; + UINT8 MinNclkIndex; + UINT8 i; + + MinNclkIndex = 0; + IntegratedInfoTable->ucNBDPMEnable = 0; + + + GnbRegisterReadTN ( + D0F0xBC_x1F428_TYPE, + D0F0xBC_x1F428_ADDRESS, + &D0F0xBC_x1F428.Value, + 0, + GnbLibGetHeader (Gfx) + ); + // Check if NbPstate enbale + if (D0F0xBC_x1F428.Field.EnableNbDpm == 1) { + //1: enable 0: not enable + IntegratedInfoTable->ucNBDPMEnable = 1; + } + + for (i = 0; i < 4; i++) { + GnbRegisterReadTN ( + TYPE_D18F5, + (D18F5x160_ADDRESS + (i * 4)), + &NbPstate[i].Value, + 0, + GnbLibGetHeader (Gfx) + ); + if (NbPstate[i].Field.NbPstateEn == 1) { + MinNclkIndex = i; + } + IntegratedInfoTable->ulNbpStateNClkFreq[i] = GfxLibGetNclkTN ((UINT8) NbPstate[i].Field.NbFid, (UINT8) NbPstate[i].Field.NbDid); + } + IntegratedInfoTable->usNBP0Voltage = (USHORT) ((NbPstate[0].Field.NbVid_7_ << 7) | NbPstate[0].Field.NbVid_6_0_); + IntegratedInfoTable->usNBP1Voltage = (USHORT) ((NbPstate[1].Field.NbVid_7_ << 7) | NbPstate[1].Field.NbVid_6_0_); + IntegratedInfoTable->usNBP2Voltage = (USHORT) ((NbPstate[2].Field.NbVid_7_ << 7) | NbPstate[2].Field.NbVid_6_0_); + IntegratedInfoTable->usNBP3Voltage = (USHORT) ((NbPstate[3].Field.NbVid_7_ << 7) | NbPstate[3].Field.NbVid_6_0_); + + IntegratedInfoTable->ulMinimumNClk = GfxLibGetNclkTN ((UINT8) NbPstate[MinNclkIndex].Field.NbFid, (UINT8) NbPstate[MinNclkIndex].Field.NbDid); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize display path for given engine + * + * + * + * @param[in] Engine Engine configuration info + * @param[out] DisplayPathList Display path list + * @param[in] Gfx Pointer to global GFX configuration + */ + +AGESA_STATUS +GfxFmMapEngineToDisplayPath ( + IN PCIe_ENGINE_CONFIG *Engine, + OUT EXT_DISPLAY_PATH *DisplayPathList, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + AGESA_STATUS Status; + UINT8 PrimaryDisplayPathId; + UINT8 SecondaryDisplayPathId; + UINTN DisplayPathIndex; + PrimaryDisplayPathId = 0xff; + SecondaryDisplayPathId = 0xff; + for (DisplayPathIndex = 0; DisplayPathIndex < (sizeof (DdiLaneConfigArrayTN) / 4); DisplayPathIndex++) { + if (DdiLaneConfigArrayTN[DisplayPathIndex][0] == Engine->EngineData.StartLane && + DdiLaneConfigArrayTN[DisplayPathIndex][1] == Engine->EngineData.EndLane) { + PrimaryDisplayPathId = DdiLaneConfigArrayTN[DisplayPathIndex][2]; + SecondaryDisplayPathId = DdiLaneConfigArrayTN[DisplayPathIndex][3]; + break; + } + } + if (PrimaryDisplayPathId != 0xff) { + IDS_HDT_CONSOLE (GFX_MISC, " Allocate Display Connector at Primary sPath[%d]\n", PrimaryDisplayPathId); + Engine->InitStatus |= INIT_STATUS_DDI_ACTIVE; + GfxIntegratedCopyDisplayInfo ( + Engine, + &DisplayPathList[PrimaryDisplayPathId], + (PrimaryDisplayPathId != SecondaryDisplayPathId) ? &DisplayPathList[SecondaryDisplayPathId] : NULL, + Gfx + ); + Status = AGESA_SUCCESS; + } else { + IDS_HDT_CONSOLE (GFX_MISC, " Error!!! Map DDI lanes %d - %d to display path failed\n", + Engine->EngineData.StartLane, + Engine->EngineData.EndLane + ); + PutEventLog ( + AGESA_ERROR, + GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION, + Engine->EngineData.StartLane, + Engine->EngineData.EndLane, + 0, + 0, + GnbLibGetHeader (Gfx) + ); + Status = AGESA_ERROR; + } + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Copy memory content to FB + * + * + * @param[in] SystemInfoTableV2Ptr Pointer to integrated info table + * @param[in] Gfx Pointer to global GFX configuration + * + */ +STATIC VOID +GfxIntInfoTabablePostToFb ( + IN ATOM_FUSION_SYSTEM_INFO_V2 *SystemInfoTableV2Ptr, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT32 Index; + UINT32 TableOffset; + UINT32 FbAddress; + + TableOffset = (UINT32) (Gfx->UmaInfo.UmaSize - sizeof (ATOM_FUSION_SYSTEM_INFO_V2)) | 0x80000000; + for (Index = 0; Index < sizeof (ATOM_FUSION_SYSTEM_INFO_V2); Index = Index + 4 ) { + FbAddress = TableOffset + Index; + GnbLibMemWrite (Gfx->GmmBase + GMMx00_ADDRESS, AccessWidth32, &FbAddress, GnbLibGetHeader (Gfx)); + GnbLibMemWrite (Gfx->GmmBase + GMMx04_ADDRESS, AccessWidth32, (UINT8*) SystemInfoTableV2Ptr + Index, GnbLibGetHeader (Gfx)); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + *Init Dispclk <-> VID table + * + * + * @param[in] PpFuseArray Fuse array pointer + * @param[in] IntegratedInfoTable Integrated info table pointer + * @param[in] Gfx Gfx configuration info + */ + +STATIC VOID +GfxIntInfoTableInitDispclkTable ( + IN PP_FUSE_ARRAY *PpFuseArray, + IN ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINTN Index; + for (Index = 0; Index < 4; Index++) { + if (PpFuseArray->DisplclkDid[Index] != 0) { + IntegratedInfoTable->sDISPCLK_Voltage[Index].ulMaximumSupportedCLK = GfxFmCalculateClock ( + PpFuseArray->DisplclkDid[Index], + GnbLibGetHeader (Gfx) + ); + IntegratedInfoTable->sDISPCLK_Voltage[Index].ulVoltageIndex = (ULONG) Index; + } + } + IntegratedInfoTable->ucDPMState0VclkFid = PpFuseArray->VclkDid[0]; + IntegratedInfoTable->ucDPMState1VclkFid = PpFuseArray->VclkDid[1]; + IntegratedInfoTable->ucDPMState2VclkFid = PpFuseArray->VclkDid[2]; + IntegratedInfoTable->ucDPMState3VclkFid = PpFuseArray->VclkDid[3]; + IntegratedInfoTable->ucDPMState0DclkFid = PpFuseArray->DclkDid[0]; + IntegratedInfoTable->ucDPMState1DclkFid = PpFuseArray->DclkDid[1]; + IntegratedInfoTable->ucDPMState2DclkFid = PpFuseArray->DclkDid[2]; + IntegratedInfoTable->ucDPMState3DclkFid = PpFuseArray->DclkDid[3]; +} + +/*----------------------------------------------------------------------------------------*/ +/** + *Init Sclk <-> VID table + * + * + * @param[in] PpFuseArray Fuse array pointer + * @param[in] IntegratedInfoTable Integrated info table pointer + * @param[in] Gfx Gfx configuration info + */ + +STATIC VOID +GfxIntInfoTableInitSclkTable ( + IN PP_FUSE_ARRAY *PpFuseArray, + IN ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINTN Index; + UINTN AvailSclkIndex; + ATOM_AVAILABLE_SCLK_LIST *AvailSclkList; + BOOLEAN Sorting; + AvailSclkList = &IntegratedInfoTable->sAvail_SCLK[0]; + + AvailSclkIndex = 0; + for (Index = 0; Index < MAX_NUM_OF_FUSED_DPM_STATES; Index++) { + if (PpFuseArray->SclkDpmDid[Index] != 0) { + AvailSclkList[AvailSclkIndex].ulSupportedSCLK = GfxFmCalculateClock (PpFuseArray->SclkDpmDid[Index], GnbLibGetHeader (Gfx)); + AvailSclkList[AvailSclkIndex].usVoltageIndex = PpFuseArray->SclkDpmVid[Index]; + AvailSclkList[AvailSclkIndex].usVoltageID = PpFuseArray->SclkVid[PpFuseArray->SclkDpmVid[Index]]; + AvailSclkIndex++; + } + } + //Sort by VoltageIndex & ulSupportedSCLK + if (AvailSclkIndex > 1) { + do { + Sorting = FALSE; + for (Index = 0; Index < (AvailSclkIndex - 1); Index++) { + ATOM_AVAILABLE_SCLK_LIST Temp; + BOOLEAN Exchange; + Exchange = FALSE; + if (AvailSclkList[Index].usVoltageIndex > AvailSclkList[Index + 1].usVoltageIndex) { + Exchange = TRUE; + } + if ((AvailSclkList[Index].usVoltageIndex == AvailSclkList[Index + 1].usVoltageIndex) && + (AvailSclkList[Index].ulSupportedSCLK > AvailSclkList[Index + 1].ulSupportedSCLK)) { + Exchange = TRUE; + } + if (Exchange) { + Sorting = TRUE; + LibAmdMemCopy (&Temp, &AvailSclkList[Index], sizeof (ATOM_AVAILABLE_SCLK_LIST), GnbLibGetHeader (Gfx)); + LibAmdMemCopy (&AvailSclkList[Index], &AvailSclkList[Index + 1], sizeof (ATOM_AVAILABLE_SCLK_LIST), GnbLibGetHeader (Gfx)); + LibAmdMemCopy (&AvailSclkList[Index + 1], &Temp, sizeof (ATOM_AVAILABLE_SCLK_LIST), GnbLibGetHeader (Gfx)); + } + } + } while (Sorting); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + *Read GFX PGFSM register + * + * + * @param[in] RegisterAddress Index of PGFSM register + * @param[out] Value Pointer to value + * @param[in] StdHeader Standard configuration header + */ + +STATIC VOID +GfxPgfsmRegisterReadTN ( + IN UINT32 RegisterAddress, + OUT UINT32 *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 RegisterWriteValue; + UINT32 RegisterReadValue; + RegisterWriteValue = (RegisterAddress << D0F0xBC_xE0300000_RegAddr_OFFSET) + + (1 << D0F0xBC_xE0300000_ReadOp_OFFSET) + + (0 << D0F0xBC_xE0300000_FsmAddr_OFFSET); + IDS_HDT_CONSOLE (GNB_TRACE, "Read PGFSM Register %d\n", RegisterAddress); + GnbRegisterWriteTN ( + D0F0xBC_xE0300000_TYPE, + D0F0xBC_xE0300000_ADDRESS, + &RegisterWriteValue, + 0, + StdHeader); + do { + GnbRegisterReadTN ( + D0F0xBC_xE0300008_TYPE, + D0F0xBC_xE0300008_ADDRESS, + &RegisterReadValue, + 0, + StdHeader); + } while ((RegisterReadValue & D0F0xBC_xE0300008_ReadValid_MASK) == 0); + *Value = RegisterReadValue & D0F0xBC_xE0300008_ReadValue_MASK; +} + +/*----------------------------------------------------------------------------------------*/ +/** + *Calculate ulGMCRestoreResetTime + * + * + * @param[in] IntegratedInfoTable Integrated info table pointer + * @param[in] Gfx Gfx configuration info + * @param[in] PpFuseArray Fuse array pointer + * @retval AGESA_STATUS + */ + +STATIC AGESA_STATUS +GfxCalculateRestoreResetTimeTN ( + IN ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable, + IN GFX_PLATFORM_CONFIG *Gfx, + IN PP_FUSE_ARRAY *PpFuseArray + ) +{ + UINT8 MaxDid; + ULONG FreqSclk; + UINTN Index; + UINT32 TSclk; + UINT32 TRefClk; + UINT32 TNclkHalf; + UINT32 PgfsmDelayReg0; + UINT32 PgfsmDelayReg1; + UINT32 ResetTime; + UINT32 IsoTime; + UINT32 MemSd; + UINT32 MotherPso; + UINT32 DaughterPso; + UINT32 THandshake; + UINT32 TGmcSync; + UINT32 TPuCmd; + UINT32 TPgfsmCmdSerialization; + UINT32 TReset; + UINT32 TMoPso; + UINT32 TDaPso; + UINT32 TMemSd; + UINT32 TIso; + UINT32 TRegRestore; + UINT32 TPgfsmCleanUp; + UINT32 TGmcPu; + UINT32 TGmcPd; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxCalculateRestoreResetTimeTN Enter\n"); + // Find FreqSclk = MIN of frequencies SclkDpmDid (0 to 4) and SclkThermDid + // First find the highest Did + MaxDid = PpFuseArray->SclkThermDid; + for (Index = 0; Index < 4; Index++) { + // Compare with SclkDpmDid[x] - These are stored in: + // IntegratedInfoTable-> sDISPCLK_Voltage[Index].ulMaximumSupportedCLK + MaxDid = MAX (MaxDid, PpFuseArray->SclkDpmDid[Index]); + } + IDS_HDT_CONSOLE (GNB_TRACE, "MaxDid = %d\n", MaxDid); + FreqSclk = GfxFmCalculateClock (MaxDid, GnbLibGetHeader (Gfx)); + // FreqSclk is in 10KHz units - need calculations in nS + // For accuracy, do calculations in .01nS, then convert at the end + TSclk = (100 * (1000000000 / 10000)) / FreqSclk; + // FreqRefClk frequency of reference clock + // Caclculate period in .01 nS + TRefClk = (100 * 1000) / GFX_REFCLK; + // FreqNclkHalf = half of Minimum NCLK value + // Calculate period in .01 nS + TNclkHalf = (100 * 1000) / (GFX_NCLK_MIN / 2); + + // Read delay time values from PGFSM registers + GfxPgfsmRegisterReadTN (2 , &PgfsmDelayReg0, GnbLibGetHeader (Gfx)); + GfxPgfsmRegisterReadTN (3 , &PgfsmDelayReg1, GnbLibGetHeader (Gfx)); + ResetTime = (PgfsmDelayReg0 & 0x000000FF ) >> 0 ; + IsoTime = (PgfsmDelayReg0 & 0x0000FF00 ) >> 8 ; + MemSd = (PgfsmDelayReg0 & 0x00FF0000 ) >> 16 ; + MotherPso = (PgfsmDelayReg1 & 0x00000FFF ) >> 0 ; + DaughterPso = (PgfsmDelayReg1 & 0x00FFF000 ) >> 12 ; + IDS_HDT_CONSOLE (GNB_TRACE, "ResetTime = %d\n", ResetTime); + IDS_HDT_CONSOLE (GNB_TRACE, "IsoTime = %d\n", IsoTime); + IDS_HDT_CONSOLE (GNB_TRACE, "MemSd = %d\n", MemSd); + IDS_HDT_CONSOLE (GNB_TRACE, "MotherPso = %d\n", MotherPso); + IDS_HDT_CONSOLE (GNB_TRACE, "DaughterPso = %d\n", DaughterPso); + + // Calculate various timing values required for the final calculation + // THandshake = 10*1/FreqNclkHalf + THandshake = 10 * TNclkHalf; + // TGmcSync = 2.5*(1/FreqRefclk+1/FreqSclk) + TGmcSync = (25 * (TRefClk + TSclk)) / 10; + // TPuCmd =9*1/FreqSclk + TPuCmd = 9 * TSclk; + // TPgfsmCmdSerialization = 82*1/FreqSclk + TPgfsmCmdSerialization = 82 * TSclk; + // TReset = (RESET_TIME+3)*1/FreqRefclk+3*1/FreqSclk+TGmcSync + TReset = ((ResetTime + 3) * TRefClk) + (3 * TSclk) + TGmcSync; + // TMoPso = (MOTHER_PSO+3)*1/FreqRefclk+3*1/FreqSclk+TgmcSync + TMoPso = ((MotherPso + 3) * TRefClk) + (3 * TSclk) + TGmcSync; + // TDaPso = (DAUGHTER_PSO+3)*1/FreqRefclk+3*1/FreqSclk+TgmcSync + TDaPso = ((DaughterPso + 3) * TRefClk) + (3 * TSclk) + TGmcSync; + // TMemSD = (MEM_SD+3)*1/FreqRefclk+3*1/FreqSclk+TgmcSync + TMemSd = ((MemSd + 3) * TRefClk) + (3 * TSclk) + TGmcSync; + // TIso = (ISO_TIME+3)*1/FreqRefclk+3*1/FreqSclk+TgmcSync + TIso = ((IsoTime + 3) * TRefClk) + (3 * TSclk) + TGmcSync; + // TRegRestore = 508*1/FreqSclk + TRegRestore = 508 * TSclk; + // TPgfsmCleanUp = 3*1/FreqSclk + TPgfsmCleanUp = 3 * TSclk; + // TGmcPu = TPUCmd + TPgfsmCmdSerialization + TReset + TMoPso + TDaPso + TMemSD + TIso + TRegRestore + TGmcPu = TPuCmd + TPgfsmCmdSerialization + TReset + TMoPso + TDaPso + TMemSd + TIso + TRegRestore; + // TGmcPd = THandshake + TPgfsmCmdSerialization + Tiso + TmemSD + TMoPso + TDaPso + TpgfsmCleanUp + 3*TReset + TGmcPd = THandshake + TPgfsmCmdSerialization + TIso + TMemSd + TMoPso + TDaPso + TPgfsmCleanUp + (3 * TReset); + // ulGMCRestoreResetTime = TGmcPu + TGmcPd + // All calculated times are in .01nS for accuracy. We can now correct that. + // By adding 99 and dividing by 100, value is rounded up to next 1 nS + IntegratedInfoTable->ulGMCRestoreResetTime = (TGmcPd + TGmcPu + 99) / 100; + IDS_HDT_CONSOLE (GNB_TRACE, "ulGMCRestoreResetTime = %d\n", IntegratedInfoTable->ulGMCRestoreResetTime); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxCalculateRestoreResetTimeTN Exit\n"); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Build integrated info table + * + * + * + * @param[in] Gfx Gfx configuration info + * @retval AGESA_STATUS + */ +AGESA_STATUS +STATIC +GfxIntInfoTableInitTN ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + ATOM_FUSION_SYSTEM_INFO_V2 SystemInfoTableV2; + PP_FUSE_ARRAY *PpFuseArray; + PCIe_PLATFORM_CONFIG *Pcie; + ATOM_PPLIB_POWERPLAYTABLE3 *PpTable; + UINT8 Channel; + + AgesaStatus = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInitTN Enter\n"); + LibAmdMemFill (&SystemInfoTableV2, 0x00, sizeof (ATOM_FUSION_SYSTEM_INFO_V2), GnbLibGetHeader (Gfx)); + SystemInfoTableV2.sIntegratedSysInfo.sHeader.usStructureSize = sizeof (ATOM_INTEGRATED_SYSTEM_INFO_V1_7); + ASSERT (SystemInfoTableV2.sIntegratedSysInfo.sHeader.usStructureSize == 512); + SystemInfoTableV2.sIntegratedSysInfo.sHeader.ucTableFormatRevision = 1; + SystemInfoTableV2.sIntegratedSysInfo.sHeader.ucTableContentRevision = 7; + SystemInfoTableV2.sIntegratedSysInfo.ulDentistVCOFreq = GfxLibGetSytemPllCofTN (GnbLibGetHeader (Gfx)) * 100; + SystemInfoTableV2.sIntegratedSysInfo.ulBootUpUMAClock = Gfx->UmaInfo.MemClock * 100; + SystemInfoTableV2.sIntegratedSysInfo.usRequestedPWMFreqInHz = Gfx->LcdBackLightControl; + SystemInfoTableV2.sIntegratedSysInfo.ucUMAChannelNumber = ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_INTERLEAVE) == 0) ? 1 : 2; + SystemInfoTableV2.sIntegratedSysInfo.ucMemoryType = 3; //DDR3 + SystemInfoTableV2.sIntegratedSysInfo.ulBootUpEngineClock = 200 * 100; //Set default engine clock to 200MhZ + SystemInfoTableV2.sIntegratedSysInfo.usBootUpNBVoltage = GnbLocateHighestVidIndex (GnbLibGetHeader (Gfx)); + SystemInfoTableV2.sIntegratedSysInfo.ulMinEngineClock = 200 * 100; + SystemInfoTableV2.sIntegratedSysInfo.usPanelRefreshRateRange = Gfx->DynamicRefreshRate; + SystemInfoTableV2.sIntegratedSysInfo.usLvdsSSPercentage = Gfx->LvdsSpreadSpectrum; + //Locate PCIe configuration data to get definitions of display connectors + SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.usStructureSize = sizeof (ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO); + SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableFormatRevision = 1; + SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableContentRevision = 1; + SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uc3DStereoPinId = Gfx->Gnb3dStereoPinIndex; + SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.ucRemoteDisplayConfig = Gfx->GnbRemoteDisplaySupport; + SystemInfoTableV2.sIntegratedSysInfo.usExtDispConnInfoOffset = offsetof (ATOM_INTEGRATED_SYSTEM_INFO_V1_7, sExtDispConnInfo); + SystemInfoTableV2.sIntegratedSysInfo.ulSB_MMIO_Base_Addr = SbGetSbMmioBaseAddress (GnbLibGetHeader (Gfx)); + + SystemInfoTableV2.sIntegratedSysInfo.usPCIEClkSSPercentage = Gfx->PcieRefClkSpreadSpectrum; + + SystemInfoTableV2.sIntegratedSysInfo.ucLvdsMisc = Gfx->LvdsMiscControl.Value; + IDS_HDT_CONSOLE (GNB_TRACE, "Lvds Misc control : %x\n", Gfx->LvdsMiscControl.Value); + if (Gfx->LvdsMiscControl.Field.TravisLvdsVoltOverwriteEn) { + SystemInfoTableV2.sIntegratedSysInfo.gnbgfxline429 = Gfx->gfxplmcfg0 ; + IDS_HDT_CONSOLE (GNB_TRACE, "TravisLVDSVoltAdjust : %x\n", Gfx->gfxplmcfg0 ); + } + + SystemInfoTableV2.sIntegratedSysInfo.ulOtherDisplayMisc = Gfx->DisplayMiscControl.Value; + IDS_HDT_CONSOLE (GNB_TRACE, "Display Misc control : %x\n", Gfx->DisplayMiscControl.Value); + + // LVDS + SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqDIGONtoDE_in4Ms = Gfx->LvdsPowerOnSeqDigonToDe; + SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms = Gfx->LvdsPowerOnSeqDeToVaryBl; + SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms = Gfx->LvdsPowerOnSeqVaryBlToDe; + SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqDEtoDIGON_in4Ms = Gfx->LvdsPowerOnSeqDeToDigon; + SystemInfoTableV2.sIntegratedSysInfo.ucLVDSOffToOnDelay_in4Ms = Gfx->LvdsPowerOnSeqOnToOffDelay; + SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms = Gfx->LvdsPowerOnSeqVaryBlToBlon; + SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms = Gfx->LvdsPowerOnSeqBlonToVaryBl; + SystemInfoTableV2.sIntegratedSysInfo.ulLCDBitDepthControlVal = Gfx->LcdBitDepthControlValue; + SystemInfoTableV2.sIntegratedSysInfo.usMaxLVDSPclkFreqInSingleLink = Gfx->LvdsMaxPixelClockFreq; + Status = PcieLocateConfigurationData (GnbLibGetHeader (Gfx), &Pcie); + ASSERT (Status == AGESA_SUCCESS); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + Status = GfxIntegratedEnumerateAllConnectors ( + &SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sPath[0], + Pcie, + Gfx + ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } + + SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uceDPToLVDSRxId = eDP_TO_LVDS_RX_DISABLE; + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_VIRTUAL | DESCRIPTOR_DDI_ENGINE, + GfxIntegrateducEDPToLVDSRxIdCallback, + &SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uceDPToLVDSRxId, + Pcie + ); + + // Build PP table + PpTable = (ATOM_PPLIB_POWERPLAYTABLE3*) &SystemInfoTableV2.ulPowerplayTable; + // Build PP table + Status = GfxPowerPlayBuildTable (PpTable, Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + // Assign usFormatID to 0x000B to represent Trinity + PpTable->usFormatID = 0xB; + // Build info from fuses + PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx)); + ASSERT (PpFuseArray != NULL); + if (PpFuseArray != NULL) { + // Build Display clock info + GfxIntInfoTableInitDispclkTable (PpFuseArray, &SystemInfoTableV2.sIntegratedSysInfo, Gfx); + // Build Sclk info table + GfxIntInfoTableInitSclkTable (PpFuseArray, &SystemInfoTableV2.sIntegratedSysInfo, Gfx); + } else { + Status = AGESA_ERROR; + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } + //@todo review if thouse parameters needed + // Fill in Nb P-state MemclkFreq Data + GfxFillNbPstateMemclkFreqTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx); + // Fill in HTC Data + GfxFillHtcDataTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx); + // Fill in NB P states VID + GfxFillNbPStateVidTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx); + // Fill in NCLK info + //GfxFillNclkInfo (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); + // Fill in the M3 arbitration control tables + //GfxFillM3ArbritrationControl (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); + // Family specific data update + + // Determine ulGMCRestoreResetTime + Status = GfxCalculateRestoreResetTimeTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx, PpFuseArray); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + //GfxFmIntegratedInfoTableInit (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); + SystemInfoTableV2.sIntegratedSysInfo.ulDDR_DLL_PowerUpTime = 4940; + SystemInfoTableV2.sIntegratedSysInfo.ulDDR_PLL_PowerUpTime = 2000; + + if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT0) != 0) { + Channel = 0; + } else { + Channel = 1; + } + if (GfxLibGetMemPhyPllPdModeTN (Channel, GnbLibGetHeader (Gfx)) != 0) { + SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT2; + } + if (GfxLibGetDisDllShutdownSRTN (Channel, GnbLibGetHeader (Gfx)) == 0) { + SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT1; + } + if (GnbBuildOptions.CfgPciePowerGatingFlags != (PCIE_POWERGATING_SKIP_CORE | PCIE_POWERGATING_SKIP_PHY)) { + SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT0; + } + SystemInfoTableV2.sIntegratedSysInfo.ulGPUCapInfo = GPUCAPINFO_TMDS_HDMI_USE_CASCADE_PLL_MODE | GPUCAPINFO_DP_USE_SINGLE_PLL_MODE; + + IDS_HDT_CONSOLE (GNB_TRACE, "ulSystemConfig : %x\n", SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig); + IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG, &SystemInfoTableV2.sIntegratedSysInfo, GnbLibGetHeader (Gfx)); + //Copy integrated info table to Frame Buffer. (Do not use LibAmdMemCopy, routine not guaranteed access to above 4G memory in 32 bit mode.) + GfxIntInfoTabablePostToFb (&SystemInfoTableV2, Gfx); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInit Exit [0x%x]\n", Status); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Build integrated info table + * GMC FB access requred + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +GfxIntInfoTableInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + GFX_PLATFORM_CONFIG *Gfx; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInterfaceTN Enter\n"); + AgesaStatus = AGESA_SUCCESS; + if (GfxLibIsControllerPresent (StdHeader)) { + Status = GfxLocateConfigData (StdHeader, &Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status != AGESA_FATAL) { + Status = GfxIntInfoTableInitTN (Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInterfaceTN Exit[0x%x]\n", AgesaStatus); + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c new file mode 100644 index 0000000..8aace22 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c @@ -0,0 +1,478 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize PP/DPM fuse table. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "S3SaveState.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GfxLibTN.h" +#include "GnbCommonLib.h" +#include "GnbRegisterAccTN.h" +#include "GnbRegistersTN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXLIBTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +CONST UINT16 GfxMemClockFrequencyDefinitionTable [][8] = { +{0 , 0 , 0 , 0 , 333, 0, 400, 0 }, +{0 , 0 , 533, 0 , 0 , 0 , 667, 0 }, +{0 , 0 , 800, 0 , 0 , 0 , 0 , 0 }, +{0 , 1050, 1066, 0 , 0, 0 , 0, 1200} +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +GfxFmDisableController ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +GfxFmCalculateClock ( + IN UINT8 Did, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GfxFmIsVbiosPosted ( + IN GFX_PLATFORM_CONFIG *Gfx + ); +/*----------------------------------------------------------------------------------------*/ +/** + * Disable GFX controller + * + * + * + * @param[in] StdHeader Standard configuration header + */ + +VOID +GfxFmDisableController ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GnbLibPciRMW ( + MAKE_SBDFO (0, 0, 0, 0,D0F0x7C_ADDRESS), + AccessS3SaveWidth32, + 0xffffffff, + 1 << D0F0x7C_ForceIntGFXDisable_OFFSET, + StdHeader + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get system PLL COF + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval System PLL COF + */ +UINT32 +GfxLibGetSytemPllCofTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D0F0xBC_xFF000000_STRUCT D0F0xBC_xFF000000; + GnbRegisterReadTN (D0F0xBC_xFF000000_TYPE, D0F0xBC_xFF000000_ADDRESS, &D0F0xBC_xFF000000.Value, 0, StdHeader); + return 100 * (D0F0xBC_xFF000000.Field.MainPllOpFreqIdStartup + 0x10); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Calculate COF for DFS out of Main PLL + * + * + * + * @param[in] Did Did + * @param[in] StdHeader Standard Configuration Header + * @retval COF in 10khz + */ + +UINT32 +GfxFmCalculateClock ( + IN UINT8 Did, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Divider; + UINT32 SystemPllCof; + SystemPllCof = GfxLibGetSytemPllCofTN (StdHeader) * 100; + if (Did >= 8 && Did <= 0x3F) { + Divider = Did * 25; + } else if (Did > 0x3F && Did <= 0x5F) { + Divider = (Did - 64) * 50 + 1600; + } else if (Did > 0x5F && Did <= 0x7E) { + Divider = (Did - 96) * 100 + 3200; + } else if (Did == 0x7f) { + Divider = 128 * 100; + } else { + ASSERT (FALSE); + return 200 * 100; + } + ASSERT (Divider != 0); + return (((SystemPllCof * 100) + (Divider - 1)) / Divider); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set idle voltage mode for GFX + * + * + * @param[in] Gfx Pointer to global GFX configuration + */ + +BOOLEAN +GfxFmIsVbiosPosted ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT32 Value; + + GnbRegisterReadTN (GMMx670_TYPE, GMMx670_ADDRESS, &Value, 0, GnbLibGetHeader (Gfx)); + return ((Value & BIT16) == 0) ? TRUE : FALSE; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Extract DRAM frequency + * + * + * + * @param[in] Encoding Memory Clock Frequency Value Definition + * @param[in] StdHeader Standard configuration header + * @retval Dram fraquency Mhz + */ +UINT32 +GfxLibExtractDramFrequency ( + IN UINT8 Encoding, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + if (Encoding >= (sizeof (GfxMemClockFrequencyDefinitionTable) / sizeof (UINT16))) { + ASSERT (FALSE); + return 0; + } + return GfxMemClockFrequencyDefinitionTable[Encoding / 8][Encoding % 8]; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get max SCLK + * + * + * @param[in] StdHeader Standard configuration header + * @retval Max SCLK in Mhz + */ +UINT32 +GfxLibGetMaxSclk ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 MaxSclkClk; + D0F0xBC_xFF000000_STRUCT D0F0xBC_xFF000000; + D0F0xBC_xE0003048_STRUCT D0F0xBC_xE0003048; + + GnbRegisterReadTN (TYPE_D0F0xBC, D0F0xBC_xFF000000_ADDRESS, &D0F0xBC_xFF000000.Value, 0, StdHeader); + GnbRegisterReadTN (TYPE_D0F0xBC, D0F0xBC_xE0003048_ADDRESS, &D0F0xBC_xE0003048.Value, 0, StdHeader); + //sclk_max_freq = 100 * (GCLK_PLL_FUSES.MainPllOptFreqIdStartup + 16) / + // (((SCLK_MIN_DIV.INT<<12 + SCLK_MIN_DIV.FRAC)>>12) + MaxSclkClk = 100 * (D0F0xBC_xFF000000.Field.MainPllOpFreqIdStartup + 16); + MaxSclkClk /= ((D0F0xBC_xE0003048.Field.Intv << 12) + D0F0xBC_xE0003048.Field.Fracv) >> 12; + return MaxSclkClk; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get number of SCLK Dram burst + * + * + * @param[in] ScaleMp Scaled number of sclk_max_freq / memps_freq + * @param[in] StdHeader Standard configuration header + * @retval number of sclks (*2) per dram burst, except (0,1,2,3)=(1,1.25,1.5,1.75) + */ +UINT32 +GfxLibGetNumberOfSclkPerDramBurst ( + IN UINT32 ScaleMp, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + if ((2 * ScaleMp) < 125) { + return 0; //STATE0 = 0 + } else if ((2 * ScaleMp) < 150) { + return 1; //STATE0 = 1 + } else if ((2 * ScaleMp) < 175) { + return 2; //STATE0 = 2 + } else if ((2 * ScaleMp) < 200) { + return 3; //STATE0 = 3 + } else { + //STATE0 = floor(4*scale_mp[0] ) + return ((4 * ScaleMp) / 100); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Calculate TN NCLK clock + * + * + * + * @param[in] NbFid NbFid + * @param[in] NbDid NbDid + * @retval Clock in 10KHz + */ + +UINT32 +GfxLibGetNclkTN ( + IN UINT8 NbFid, + IN UINT8 NbDid + ) +{ + UINT32 Divider; + //i.e. NBCOF[0] = (100 * (D18F5x160[NbFid] + 4h) / (2^D18F5x160[NbDid])) Mhz + if (NbDid == 1) { + Divider = 2; + } else if (NbDid == 0) { + Divider = 1; + } else { + Divider = 1; + } + ASSERT (NbDid == 0 || NbDid == 1); + return ((10000 * (NbFid + 4)) / Divider); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set VID through CG client + * + * + * @param[in] Vid VID code + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GfxRequestVoltageTN ( + IN UINT8 Vid, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GMMx770_STRUCT GMMx770; + GMMx774_STRUCT GMMx774; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxRequestVoltageTN Enter\n"); + + GnbRegisterReadTN (GMMx770_TYPE, GMMx770_ADDRESS, &GMMx770, 0, StdHeader); + GMMx770.Field.VoltageChangeEn = 1; + GnbRegisterWriteTN (GMMx770_TYPE, GMMx770_ADDRESS, &GMMx770, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + GMMx770.Field.VoltageLevel = Vid; + GMMx770.Field.VoltageChangeReq = ~GMMx770.Field.VoltageChangeReq; + GnbRegisterWriteTN (GMMx770_TYPE, GMMx770_ADDRESS, &GMMx770, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + do { + GnbRegisterReadTN (GMMx774_TYPE, GMMx774_ADDRESS, &GMMx774, 0, StdHeader); + } while (GMMx774.Field.VoltageChangeAck != GMMx770.Field.VoltageChangeReq); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxRequestVoltageTN Exit\n"); + return AGESA_SUCCESS; +} + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Set SCLK + * + * + * @param[in] Did Devider + * @param[in] StdHeader Standard configuration header + * @retval previous DID + */ + +UINT8 +GfxRequestSclkTNS3Save ( + IN UINT8 Did, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + S3_SAVE_DISPATCH (StdHeader, GfxRequestSclkTNS3Script_ID, sizeof (Did), &Did); + return GfxRequestSclkTN (Did, StdHeader); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Set SCLK + * + * + * @param[in] Did Devider + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +UINT8 +GfxRequestSclkTN ( + IN UINT8 Did, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GMMx600_STRUCT GMMx600; + GMMx604_STRUCT GMMx604; + UINT8 OriginalDid; + do { + GnbRegisterReadTN (GMMx604_TYPE, GMMx604_ADDRESS, &GMMx604, 0, StdHeader); + } while (GMMx604.Field.SclkStatus == 0); + GnbRegisterReadTN (GMMx600_TYPE, GMMx600_ADDRESS, &GMMx600, 0, StdHeader); + OriginalDid = (UINT8) GMMx600.Field.IndClkDiv; + GMMx600.Field.IndClkDiv = Did; + GnbRegisterWriteTN (GMMx600_TYPE, GMMx600_ADDRESS, &GMMx600, 0, StdHeader); + do { + GnbRegisterReadTN (GMMx604_TYPE, GMMx604_ADDRESS, &GMMx604, 0, StdHeader); + } while (GMMx604.Field.SclkStatus == 0); + return OriginalDid; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Set Sclk in S3 script + * + * + * + * @param[in] StdHeader Standard configuration header + * @param[in] ContextLength Context Length (not used) + * @param[in] Context pointer to UINT32 number of us + */ +VOID +GfxRequestSclkTNS3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID* Context + ) +{ + GfxRequestSclkTN (* ((UINT8*) Context), StdHeader); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Calculate did from main VCO + * + * + * + * @param[in] Vco Vco in 10Khz + * @param[in] StdHeader Standard configuration header + * @retval DID + */ + +UINT8 +GfxLibCalculateDidTN ( + IN UINT32 Vco, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Divider; + UINT32 SystemPllCof; + UINT8 Did; + ASSERT (Vco != 0); + SystemPllCof = GfxLibGetSytemPllCofTN (StdHeader) * 100; + Divider = ((SystemPllCof * 100) + (Vco - 1)) / Vco; + Did = 0; + if (Divider < 200) { + } else if (Divider <= 1575) { + Did = (UINT8) (Divider / 25); + } else if (Divider <= 3150) { + Did = (UINT8) ((Divider - 1600) / 50) + 64; + } else if (Divider <= 6200) { + Did = (UINT8) ((Divider - 3200) / 100) + 96; + } else { + Did = 0x7f; + } + return Did; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.h new file mode 100644 index 0000000..69dd647 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.h @@ -0,0 +1,134 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * various service procedures + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GFXLIBTN_H_ +#define _GFXLIBTN_H_ + +UINT32 +GfxLibGetSytemPllCofTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +GfxLibExtractDramFrequency ( + IN UINT8 Encoding, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +GfxLibGetMaxSclk ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +GfxLibGetNumberOfSclkPerDramBurst ( + IN UINT32 ScaleMp, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +GfxLibGetNclkTN ( + IN UINT8 NbFid, + IN UINT8 NbDid + ); + +AGESA_STATUS +GfxRequestVoltageTN ( + IN UINT8 Vid, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +GfxRequestSclkTN ( + IN UINT8 Did, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +GfxRequestSclkTNS3Save ( + IN UINT8 Did, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GfxRequestSclkTNS3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID* Context + ); + +UINT8 +GfxLibCalculateDidTN ( + IN UINT32 Vco, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c new file mode 100644 index 0000000..4e3efa5 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c @@ -0,0 +1,304 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 65199 $ @e $Date: 2012-02-09 21:36:06 -0600 (Thu, 09 Feb 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbGfxConfig.h" +#include "GnbGfxInitLibV1.h" +#include "GnbNbInitLibV1.h" +#include "GnbGfxFamServices.h" +#include "GfxLibTN.h" +#include "GfxGmcInitTN.h" +#include "GnbRegisterAccTN.h" +#include "GnbRegistersTN.h" +#include "PcieConfigData.h" +#include "PcieConfigLib.h" +#include "cpuFamilyTranslation.h" +#include "GnbHandleLib.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXMIDINITTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GfxIntegratedEnumerateAudioConnectors ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +AGESA_STATUS +GfxMidInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +exec803 /* GfxAzWorkaroundTN */ ( + IN GFX_PLATFORM_CONFIG *Gfx + ); +/*----------------------------------------------------------------------------------------*/ +/** + * Set boot up voltage + * + * + * @param[in] Gfx Pointer to global GFX configuration + * @retval AGESA_STATUS + */ + +STATIC AGESA_STATUS +GfxSetBootUpVoltageTN ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + IDS_HDT_CONSOLE (GNB_TRACE, "GfxSetBootUpVoltageTN Enter\n"); + GfxRequestVoltageTN (GnbLocateHighestVidCode (GnbLibGetHeader (Gfx)), GnbLibGetHeader (Gfx)); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set boot up voltage + * + * + * @param[in] Gfx Pointer to global GFX configuration + */ + +VOID +exec803 /* GfxAzWorkaroundTN */ ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT32 i; + UINT32 Address; + UINT32 Data; + + + Data = 0x156; + for (i = 0; i < 6; i++) { + Address = 0x5E00 + (i * 0x18); + GnbLibMemWrite (Gfx->GmmBase + Address, AccessS3SaveWidth32, &Data, GnbLibGetHeader (Gfx)); + GnbLibMemRMW (Gfx->GmmBase + Address + 4, AccessS3SaveWidth32, 0xFFFFFF00, 0xF0, GnbLibGetHeader (Gfx)); + } + + return; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GFX at Mid Post. + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GfxMidInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + GFX_PLATFORM_CONFIG *Gfx; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxMidInterfaceTN Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = GfxLocateConfigData (StdHeader, &Gfx); + ASSERT (Status == AGESA_SUCCESS); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_FATAL) { + GfxFmDisableController (StdHeader); + } else { + if (Gfx->UmaInfo.UmaMode != UMA_NONE) { + Status = GfxEnableGmmAccess (Gfx); + ASSERT (Status == AGESA_SUCCESS); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status != AGESA_SUCCESS) { + // Can not initialize GMM registers going to disable GFX controller + IDS_HDT_CONSOLE (GNB_TRACE, " Fail to establish GMM access\n"); + Gfx->UmaInfo.UmaMode = UMA_NONE; + GfxFmDisableController (StdHeader); + } else { + Status = GfxGmcInitTN (Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + Status = GfxSetBootUpVoltageTN (Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + Status = GfxInitSsid (Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + Status = GfxIntegratedEnumerateAudioConnectors (Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + exec803 /* GfxAzWorkaroundTN */ (Gfx); + } + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "GfxMidInterfaceTN Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Determine number of audio ports for each connector + * + * + * + * @param[in] Engine Engine configuration info + * @param[in,out] Buffer Buffer pointer + * @param[in] Pcie PCIe configuration info + */ +VOID +STATIC +GfxIntegratedAudioEnumCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 *AudioCount; + AudioCount = (UINT8*) Buffer; + if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeHDMI) { + IDS_HDT_CONSOLE (GNB_TRACE, "Found HDMI Connector\n"); + (*AudioCount)++; + } else if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDP) { + if ((Engine->Type.Ddi.DdiData.Flags & DDI_DATA_FLAGS_DP1_1_ONLY) == 0) { + IDS_HDT_CONSOLE (GNB_TRACE, "Found DP1.2 Connector\n"); + *AudioCount += 4; + } else { + IDS_HDT_CONSOLE (GNB_TRACE, "Found DP1.1 Connector\n"); + (*AudioCount)++; + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "New AudioCount = %d\n", *AudioCount); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Enumerate all display connectors with audio capability and configure number of ports + * + * + * + * @param[in] Gfx Gfx configuration info + */ +AGESA_STATUS +GfxIntegratedEnumerateAudioConnectors ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT8 AudioCount; + AGESA_STATUS Status; + GMMx5F50_STRUCT GMMx5F50; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAudioConnectors Enter\n"); + + Status = PcieLocateConfigurationData (GnbLibGetHeader (Gfx), &Pcie); + if ((Status == AGESA_SUCCESS) && (Gfx->GnbHdAudio != 0)) { + AudioCount = 0; + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_VIRTUAL | DESCRIPTOR_DDI_ENGINE, + GfxIntegratedAudioEnumCallback, + &AudioCount, + Pcie + ); + if (AudioCount > 4) { + AudioCount = 4; + } + GMMx5F50.Value = 0x00; + GMMx5F50.Field.PortConnectivity = (7 - AudioCount); + GMMx5F50.Field.PortConnectivityOverrideEnable = 1; + GnbRegisterWriteTN (GMMx5F50_TYPE, GMMx5F50_ADDRESS, &GMMx5F50.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + } + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAudioConnectors Exit\n"); + return Status; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c new file mode 100644 index 0000000..36e013e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c @@ -0,0 +1,155 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbGfx.h" +#include "GnbGfxConfig.h" +#include "GnbFuseTable.h" +#include "GnbGfxInitLibV1.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXPOSTINITTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GfxPostInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GFX at Post. + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + + +AGESA_STATUS +GfxPostInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AMD_POST_PARAMS *PostParamsPtr; + GFX_CARD_CARD_INFO GfxDiscreteCardInfo; + AGESA_STATUS Status; + GFX_PLATFORM_CONFIG *Gfx; + PostParamsPtr = (AMD_POST_PARAMS *)StdHeader; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxPostInterfaceTN Enter\n"); + Status = GfxLocateConfigData (StdHeader, &Gfx); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + if (GfxLibIsControllerPresent (StdHeader)) { + if (PostParamsPtr->MemConfig.UmaMode != UMA_NONE) { + LibAmdMemFill (&GfxDiscreteCardInfo, 0x0, sizeof (GfxDiscreteCardInfo), StdHeader); + GfxGetDiscreteCardInfo (&GfxDiscreteCardInfo, StdHeader); + if (((GfxDiscreteCardInfo.PciGfxCardBitmap != 0) || + (GfxDiscreteCardInfo.AmdPcieGfxCardBitmap != GfxDiscreteCardInfo.PcieGfxCardBitmap)) || + ((PostParamsPtr->GnbPostConfig.IgpuEnableDisablePolicy == IGPU_DISABLE_ANY_PCIE) && + ((GfxDiscreteCardInfo.PciGfxCardBitmap != 0) || (GfxDiscreteCardInfo.PcieGfxCardBitmap != 0)))) { + PostParamsPtr->MemConfig.UmaMode = UMA_NONE; + IDS_HDT_CONSOLE (GFX_MISC, " GfxDisabled due dGPU policy\n"); + } + } + } else { + PostParamsPtr->MemConfig.UmaMode = UMA_NONE; + Gfx->GfxFusedOff = TRUE; + } + } else { + PostParamsPtr->MemConfig.UmaMode = UMA_NONE; + } + IDS_HDT_CONSOLE (GNB_TRACE, "GfxPostInterfaceTN Exit [0x%x]\n", Status); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxTablesTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxTablesTN.c new file mode 100644 index 0000000..876614e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxTablesTN.c @@ -0,0 +1,1096 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GFx tables + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 64726 $ @e $Date: 2012-01-30 01:00:01 -0600 (Mon, 30 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbTable.h" +#include "GnbRegistersTN.h" +#include "cpuFamilyTranslation.h" +#include "GnbInitTN.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T A B L E S + *---------------------------------------------------------------------------------------- + */ + +GNB_TABLE ROMDATA GfxGmcColockGatingDisableTN [] = { + //2.1 Disable clock-gating + GNB_ENTRY_WR (TYPE_GMM , 0x20c0 , 0x00000C80), + GNB_ENTRY_WR (TYPE_GMM , 0x2478 , 0x00000400), + GNB_ENTRY_WR (TYPE_GMM , 0x20b8 , 0x00000400), + GNB_ENTRY_WR (TYPE_GMM , 0x20bc , 0x00000400), + GNB_ENTRY_WR (TYPE_GMM , 0x2648 , 0x00000400), + GNB_ENTRY_WR (TYPE_GMM , 0x264c , 0x00000400), + GNB_ENTRY_WR (TYPE_GMM , 0x2650 , 0x00000400), + GNB_ENTRY_WR (TYPE_GMM , 0x15c0 , 0x00001401), + GNB_ENTRY_TERMINATE +}; + + +GNB_TABLE ROMDATA GfxGmcInitTableTN [] = { + GNB_ENTRY_RMW (D18F5x178_TYPE, D18F5x178_ADDRESS, D18F5x178_SwGfxDis_MASK, 0 << D18F5x178_SwGfxDis_OFFSET), + //2.2 System memory address translation + GNB_ENTRY_COPY (GMMx2814_TYPE, GMMx2814_ADDRESS, 0, 32, D18F2x40_dct0_TYPE, D18F2x40_dct0_ADDRESS, 0, 32), + GNB_ENTRY_COPY (GMMx2818_TYPE, GMMx2818_ADDRESS, 0, 32, D18F2x40_dct1_TYPE, D18F2x40_dct1_ADDRESS, 0, 32), + GNB_ENTRY_COPY (GMMx281C_TYPE, GMMx281C_ADDRESS, 0, 32, D18F2x44_dct0_TYPE, D18F2x44_dct0_ADDRESS, 0, 32), + GNB_ENTRY_COPY (GMMx2820_TYPE, GMMx2820_ADDRESS, 0, 32, D18F2x44_dct1_TYPE, D18F2x44_dct1_ADDRESS, 0, 32), + GNB_ENTRY_COPY (GMMx2824_TYPE, GMMx2824_ADDRESS, 0, 32, D18F2x48_dct0_TYPE, D18F2x48_dct0_ADDRESS, 0, 32), + GNB_ENTRY_COPY (GMMx2828_TYPE, GMMx2828_ADDRESS, 0, 32, D18F2x48_dct1_TYPE, D18F2x48_dct1_ADDRESS, 0, 32), + GNB_ENTRY_COPY (GMMx282C_TYPE, GMMx282C_ADDRESS, 0, 32, D18F2x4C_dct0_TYPE, D18F2x4C_dct0_ADDRESS, 0, 32), + GNB_ENTRY_COPY (GMMx2830_TYPE, GMMx2830_ADDRESS, 0, 32, D18F2x4C_dct1_TYPE, D18F2x4C_dct1_ADDRESS, 0, 32), + GNB_ENTRY_COPY (GMMx2834_TYPE, GMMx2834_ADDRESS, 0, 32, D18F2x60_dct0_TYPE, D18F2x60_dct0_ADDRESS, 0, 32), + GNB_ENTRY_COPY (GMMx2838_TYPE, GMMx2838_ADDRESS, 0, 32, D18F2x64_dct0_TYPE, D18F2x64_dct0_ADDRESS, 0, 32), + GNB_ENTRY_COPY (GMMx283C_TYPE, GMMx283C_ADDRESS, 0, 32, D18F2x60_dct1_TYPE, D18F2x60_dct1_ADDRESS, 0, 32), + GNB_ENTRY_COPY (GMMx2840_TYPE, GMMx2840_ADDRESS, 0, 32, D18F2x64_dct1_TYPE, D18F2x64_dct1_ADDRESS, 0, 32), + GNB_ENTRY_COPY (GMMx2844_TYPE, GMMx2844_ADDRESS, 0, 8, D18F2x80_dct0_TYPE, D18F2x80_dct0_ADDRESS, 0, 8), + GNB_ENTRY_COPY (GMMx2844_TYPE, GMMx2844_ADDRESS, 16, 1, D18F2x94_dct0_TYPE, D18F2x94_dct0_ADDRESS, 22, 1), + GNB_ENTRY_COPY (GMMx2844_TYPE, GMMx2844_ADDRESS, 19, 1, D18F2xA8_dct0_TYPE, D18F2xA8_dct0_ADDRESS, 20, 1), + GNB_ENTRY_COPY (GMMx2848_TYPE, GMMx2848_ADDRESS, 0, 8, D18F2x80_dct1_TYPE, D18F2x80_dct1_ADDRESS, 0, 8), + GNB_ENTRY_COPY (GMMx2848_TYPE, GMMx2848_ADDRESS, 16, 1, D18F2x94_dct1_TYPE, D18F2x94_dct1_ADDRESS, 22, 1), + GNB_ENTRY_COPY (GMMx2848_TYPE, GMMx2848_ADDRESS, 19, 1, D18F2xA8_dct1_TYPE, D18F2xA8_dct1_ADDRESS, 20, 1), + GNB_ENTRY_COPY (GMMx284C_TYPE, GMMx284C_ADDRESS, 0, 32, TYPE_D18F2 , 0x110 , 0, 32), + GNB_ENTRY_COPY (GMMx2850_TYPE, GMMx2850_ADDRESS, 0, 32, D18F2x114_TYPE, D18F2x114_ADDRESS, 0, 32), + GNB_ENTRY_COPY (GMMx2854_TYPE, GMMx2854_ADDRESS, 0, 32, D18F1xF0_TYPE, D18F1xF0_ADDRESS, 0, 32), + //GNB_ENTRY_COPY (GMMx2858_TYPE, GMMx2858_ADDRESS, 0, 32, ????, ????, 0, 32), + GNB_ENTRY_COPY (GMMx285C_TYPE, GMMx285C_ADDRESS, 0, 32, TYPE_D18F2 , 0x10c , 0, 32), + // 2.4 RENG init + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000000), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x001b0a05), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000001D), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00080500), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000027), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0001050c), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000002a), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x1000051e), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000000ff), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000000ff), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000002e), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00010536), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000031), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0001053e), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000034), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00010546), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000037), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x001a054e), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000053), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0001056f), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000056), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00010572), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000059), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00020575), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000005d), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00000800), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000005f), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x001a0801), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000007b), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0001082a), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000007e), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0014082d), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000094), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00040843), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000009a), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00170851), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000b3), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x001d086a), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000d2), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00000891), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000d4), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00000893), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000d6), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00020895), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000da), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00020899), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000de), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0002089d), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000e2), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000208a1), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000e6), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x006808cd), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000150), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0016094d), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000168), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000d096d), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000177), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0009097f), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000182), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000a098a), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000018e), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000d0998), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000019d), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000409a7), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000001a3), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x003709cd), + GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000001dc), + GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000f0a21), + GNB_ENTRY_WR (GMMx28D4_TYPE, GMMx28D4_ADDRESS, 0x7b1ec000), + GNB_ENTRY_WR (GMMx28D8_TYPE, GMMx28D8_ADDRESS, 0x200cf01d), + // 2.5 + GNB_ENTRY_RMW (GMMx5490_TYPE, GMMx5490_ADDRESS, GMMx5490_FB_WRITE_EN_MASK | GMMx5490_FB_READ_EN_MASK, (1 << GMMx5490_FB_READ_EN_OFFSET) | (1 << GMMx5490_FB_WRITE_EN_OFFSET)), + // 2.6 Perfromance tuning + GNB_ENTRY_WR (TYPE_GMM , 0x27d0 , 0x10734847), + GNB_ENTRY_WR (TYPE_GMM , 0x27c0 , 0x00032005), + GNB_ENTRY_WR (TYPE_GMM , 0x27c4 , 0x00C12008), + GNB_ENTRY_WR (TYPE_GMM , 0x27d4 , 0x00003d3c), + GNB_ENTRY_WR (TYPE_GMM , 0x277c , 0x00000007), + GNB_ENTRY_WR (TYPE_GMM , 0x2198 , 0x000221b1), + GNB_ENTRY_WR (TYPE_GMM , 0x2750 , 0x00080A20), + GNB_ENTRY_WR (TYPE_GMM , 0x201c , 0x66660006), + GNB_ENTRY_WR (TYPE_GMM , 0x2020 , 0x70770007), + GNB_ENTRY_WR (TYPE_GMM , 0x2018 , 0x66070050), + GNB_ENTRY_WR (TYPE_GMM , 0x2014 , 0x77550000), + GNB_ENTRY_WR (TYPE_GMM , 0x2794 , 0xfcfcfdfc), + GNB_ENTRY_WR (TYPE_GMM , 0x2798 , 0xfcfcfdfc), + GNB_ENTRY_WR (TYPE_GMM , 0x27a4 , 0x00ffffff), + GNB_ENTRY_WR (TYPE_GMM , 0x27a8 , 0x00ffffff), + GNB_ENTRY_WR (TYPE_GMM , 0x278c , 0x00000004), + GNB_ENTRY_WR (TYPE_GMM , 0x2790 , 0x00000004), + GNB_ENTRY_WR (TYPE_GMM , 0x2628 , 0x44111222), + GNB_ENTRY_WR (TYPE_GMM , 0x25e0 , 0x00000004), + GNB_ENTRY_WR (TYPE_GMM , 0x262c , 0x11222111), + GNB_ENTRY_WR (TYPE_GMM , 0x25e4 , 0x00000002), + //2.7 Miscellaneous programming + GNB_ENTRY_WR (TYPE_GMM , 0x20b4 , 0x00000000), + //2.8 Enabling garlic interface + GNB_ENTRY_RMW (TYPE_GMM , 0x2878 , 0x1 , 1 << 0 ), + // Limit number of garlic credits to 12 + GNB_ENTRY_WR (TYPE_GMM , 0x276c , 0x000000ff), + GNB_ENTRY_WR (TYPE_GMM , 0x2898 , 0x01800360), + GNB_ENTRY_RMW (TYPE_GMM , 0x289c , 0x8000 , 1 << 15 ), + GNB_ENTRY_REV_RMW (0x0000000000000100ull , TYPE_GMM , 0x289c , 0x8000 , 0 << 15 ), + GNB_ENTRY_RMW (GMMxC64_TYPE, GMMxC64_ADDRESS, GMMxC64_MCIFMEM_CACHE_MODE_DIS_MASK, 0 << GMMxC64_MCIFMEM_CACHE_MODE_DIS_OFFSET), + GNB_ENTRY_REV_RMW (0x0000000000000100ull , GMMxC64_TYPE, GMMxC64_ADDRESS, GMMxC64_MCIFMEM_CACHE_MODE_DIS_MASK, 1 << GMMxC64_MCIFMEM_CACHE_MODE_DIS_OFFSET), + //2.10 UVD and VCE latency + //These settings are to improve UVD and VCE latency. + //They need these settings to get good memory performance. + GNB_ENTRY_WR (TYPE_GMM , 0x2750 , 0x00080200), + GNB_ENTRY_WR (TYPE_GMM , 0x2190 , 0x001EA1A1), + GNB_ENTRY_WR (TYPE_GMM , 0x2180 , 0x0000A1E1), + GNB_ENTRY_WR (TYPE_GMM , 0x218c , 0x000FA1E1), + GNB_ENTRY_WR (GMMx2188_TYPE, GMMx2188_ADDRESS, 0x0000A1E1), + GNB_ENTRY_WR (TYPE_GMM , 0x21f0 , 0x0000A1F1), + GNB_ENTRY_WR (TYPE_GMM , 0x21ec , 0x0000A1F1), + GNB_ENTRY_WR (TYPE_GMM , 0x21f8 , 0x0000A1E1), + GNB_ENTRY_WR (TYPE_GMM , 0x21f4 , 0x0000A1E1), + GNB_ENTRY_RMW (TYPE_GMM , 0x690 , 0x20000000 , 1 << 29 ), + GNB_ENTRY_RMW (TYPE_GMM , 0x21a8 , 0x4 , 0), +//MC Performance settings base on memory channel configuration, so, move settings to GfxGmcInitializeSequencerTN() +// GNB_ENTRY_WR (TYPE_GMM , 0x2214 , 0x00000003), + GNB_ENTRY_WR (TYPE_GMM , 0x2218 , 0x0000000C), + GNB_ENTRY_WR (GMMx2888_TYPE, GMMx2888_ADDRESS, 0x000007DE), + GNB_ENTRY_WR (GMMx25C8_TYPE, GMMx25C8_ADDRESS, 0x00403932), + GNB_ENTRY_WR (GMMx2114_TYPE, GMMx2114_ADDRESS, 0x00000015), + //2.11 Remove blackout + GNB_ENTRY_WR (GMMx25C0_TYPE, GMMx25C0_ADDRESS, 0x00000000), + GNB_ENTRY_WR (TYPE_GMM , 0x20ec , 0x000001DC), + GNB_ENTRY_WR (TYPE_GMM , 0x20d4 , 0x00000016), + GNB_ENTRY_WR (TYPE_GMM , 0x20ac , 0x00000000), + GNB_ENTRY_RMW (TYPE_GMM , 0x2760 , 0x3 , 1 << 0 ), + GNB_ENTRY_TERMINATE +}; + +GNB_TABLE ROMDATA GfxGmcColockGatingEnableTN [] = { + GNB_ENTRY_WR (TYPE_GMM , 0x20c0 , 0x00040c80), + GNB_ENTRY_WR (TYPE_GMM , 0x2478 , 0x00040400), + GNB_ENTRY_WR (TYPE_GMM , 0x20b8 , 0x00040400), + GNB_ENTRY_WR (TYPE_GMM , 0x20bc , 0x00040400), + GNB_ENTRY_WR (TYPE_GMM , 0x2648 , 0x00040400), + GNB_ENTRY_WR (TYPE_GMM , 0x264c , 0x00040400), + GNB_ENTRY_WR (TYPE_GMM , 0x2650 , 0x00040400), + GNB_ENTRY_WR (TYPE_GMM , 0x15c0 , 0x00041401), + //In addition to above registers it is necessary to reset override bits for VMC, MCB, and MCD blocks + //Implement in GnbCgttOverrideTN + GNB_ENTRY_TERMINATE +}; + +GNB_TABLE ROMDATA GfxEnvInitTableTN [] = { + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + TYPE_GMM , + 0xe60 , + 0x0, + (0x1 << 1 ) | (0x1 << 0 ) | + (0x1 << 5 ) | (0x1 << 2 ) | + (0x1 << 7 ) | (0x1 << 6 ) | + (0x1 << 9 ) | (0x1 << 8 ) | + (0x1 << 11 ) | (0x1 << 10 ) | + (0x1 << 14 ) | (0x1 << 13 ) | + (0x1 << 17 ) | (0x1 << 15 ) | + (0x1 << 19 ) | (0x1 << 18 ) | + (0x1 << 24 ) | (0x1 << 20 ) + ), +//--------------------------------------------------------------------------- +// Configure GMC Power Island + GNB_ENTRY_WR ( + D0F0xBC_xE0300004_TYPE, + D0F0xBC_xE0300004_ADDRESS, + (10 << 0 ) | (4 << 8 ) | + (5 << 16 ) + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300000_TYPE, + D0F0xBC_xE0300000_ADDRESS, + (0xff << D0F0xBC_xE0300000_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300000_WriteOp_OFFSET) | + (2 << D0F0xBC_xE0300000_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300004_TYPE, + D0F0xBC_xE0300004_ADDRESS, + (90 << 0 ) | (50 << 12 ) + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300000_TYPE, + D0F0xBC_xE0300000_ADDRESS, + (0xff << D0F0xBC_xE0300000_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300000_WriteOp_OFFSET) | + (3 << D0F0xBC_xE0300000_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300004_TYPE, + D0F0xBC_xE0300004_ADDRESS, + 0x0 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300000_TYPE, + D0F0xBC_xE0300000_ADDRESS, + (0xff << D0F0xBC_xE0300000_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300000_WriteOp_OFFSET) | (1 << D0F0xBC_xE0300000_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), +// Shutdown GMC if integrated GFX disabled + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0003024_TYPE, + D0F0xBC_xE0003024_ADDRESS, + 0x1, + 0x1 + ), + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0300000_TYPE, + D0F0xBC_xE0300000_ADDRESS, + (0xff << D0F0xBC_xE0300000_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300000_PowerDown_OFFSET) | + (1 << D0F0xBC_xE0300000_P1Select_OFFSET) | (1 << D0F0xBC_xE0300000_P2Select_OFFSET) + ), + GNB_ENTRY_PROPERTY_POLL ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0300200_TYPE, + D0F0xBC_xE0300200_ADDRESS, + D0F0xBC_xE0300200_P1IsoN_MASK, + 0 + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0003024_TYPE, + D0F0xBC_xE0003024_ADDRESS, + 0x1, + 0x0 + ), +//--------------------------------------------------------------------------- +// Configure UVD Power Island + GNB_ENTRY_WR ( + D0F0xBC_xE0300040_TYPE, + D0F0xBC_xE0300040_ADDRESS, + (10 << 0 ) | (50 << 8 ) | + (5 << 16 ) + ), + GNB_ENTRY_WR ( + D0F0xBC_xE030003C_TYPE, + D0F0xBC_xE030003C_ADDRESS, + (0xff << D0F0xBC_xE030003C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030003C_WriteOp_OFFSET) | + (2 << D0F0xBC_xE030003C_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300040_TYPE, + D0F0xBC_xE0300040_ADDRESS, + (50 << 0 ) | (50 << 12 ) + ), + GNB_ENTRY_WR ( + D0F0xBC_xE030003C_TYPE, + D0F0xBC_xE030003C_ADDRESS, + (0xff << D0F0xBC_xE030003C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030003C_WriteOp_OFFSET) | + (3 << D0F0xBC_xE030003C_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300040_TYPE, + D0F0xBC_xE0300040_ADDRESS, + 0x0 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE030003C_TYPE, + D0F0xBC_xE030003C_ADDRESS, + (0xff << D0F0xBC_xE030003C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030003C_WriteOp_OFFSET) | (1 << D0F0xBC_xE030003C_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), +// Shutdown UVD if integrated GFX disabled + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0003024_TYPE, + D0F0xBC_xE0003024_ADDRESS, + 0x1, + 0x1 + ), + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE030003C_TYPE, + D0F0xBC_xE030003C_ADDRESS, + (0xff << D0F0xBC_xE030003C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030003C_PowerDown_OFFSET) | + (1 << D0F0xBC_xE030003C_P1Select_OFFSET) | (1 << D0F0xBC_xE030003C_P2Select_OFFSET) + ), + GNB_ENTRY_PROPERTY_POLL ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0300218_TYPE, + D0F0xBC_xE0300218_ADDRESS, + D0F0xBC_xE0300218_P1IsoN_MASK, + 0x0 + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0300324_TYPE, + D0F0xBC_xE0300324_ADDRESS, + D0F0xBC_xE0300324_UvdPgfsmClockEn_MASK, + 0x0 + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0003024_TYPE, + D0F0xBC_xE0003024_ADDRESS, + 0x1, + 0x0 + ), +//--------------------------------------------------------------------------- +// Configure VCE Power Island + GNB_ENTRY_WR ( + D0F0xBC_xE0300028_TYPE, + D0F0xBC_xE0300028_ADDRESS, + (10 << 0 ) | (50 << 8 ) | + (5 << 16 ) + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300024_TYPE, + D0F0xBC_xE0300024_ADDRESS, + (0xff << D0F0xBC_xE0300024_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300024_WriteOp_OFFSET) | + (2 << D0F0xBC_xE0300024_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300028_TYPE, + D0F0xBC_xE0300028_ADDRESS, + (50 << 0 ) | (50 << 12 ) + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300024_TYPE, + D0F0xBC_xE0300024_ADDRESS, + (0xff << D0F0xBC_xE0300024_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300024_WriteOp_OFFSET) | + (3 << D0F0xBC_xE0300024_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300028_TYPE, + D0F0xBC_xE0300028_ADDRESS, + 0x0 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300024_TYPE, + D0F0xBC_xE0300024_ADDRESS, + (0xff << D0F0xBC_xE0300024_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300024_WriteOp_OFFSET) | (1 << D0F0xBC_xE0300024_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), +// Shutdown VCE if integrated GFX disabled + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0003024_TYPE, + D0F0xBC_xE0003024_ADDRESS, + 0x1, + 0x1 + ), + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0300024_TYPE, + D0F0xBC_xE0300024_ADDRESS, + (0xff << D0F0xBC_xE0300024_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300024_PowerDown_OFFSET) | + (1 << D0F0xBC_xE0300024_P1Select_OFFSET) | (1 << D0F0xBC_xE0300024_P2Select_OFFSET) + ), + GNB_ENTRY_PROPERTY_POLL ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE030020C_TYPE, + D0F0xBC_xE030020C_ADDRESS, + D0F0xBC_xE030020C_P1IsoN_MASK, + 0x0 + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0300324_TYPE, + D0F0xBC_xE0300324_ADDRESS, + D0F0xBC_xE0300324_VcePgfsmClockEn_MASK, + 0x0 + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0003024_TYPE, + D0F0xBC_xE0003024_ADDRESS, + 0x1, + 0x0 + ), + +//--------------------------------------------------------------------------- +// Configure DCE Power Island + // Step 1: Take control over DC2 PGFSM. By default display sends power up/down commands. + GNB_ENTRY_WR ( + D0F0xBC_xE03002DC_TYPE, + D0F0xBC_xE03002DC_ADDRESS, + (1 << D0F0xBC_xE03002DC_DC2_PGFSM_CONTROL_OFFSET) + ), + //Step 2: Read CC_RCU_FUSES register + //If Internal GPU is fused off go to Step 3, ELSE Go to Step 4. + + //Step 3: Enable PGFSM commands during reset + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0003024_TYPE, + D0F0xBC_xE0003024_ADDRESS, + 0x1, + 0x1 + ), + //Step 4: + GNB_ENTRY_WR ( + D0F0xBC_xE0300034_TYPE, + D0F0xBC_xE0300034_ADDRESS, + (10 << 0 ) | (50 << 8 ) | + (5 << 16 ) + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300030_TYPE, + D0F0xBC_xE0300030_ADDRESS, + (0xff << D0F0xBC_xE0300030_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300030_WriteOp_OFFSET) | + (2 << D0F0xBC_xE0300030_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300034_TYPE, + D0F0xBC_xE0300034_ADDRESS, + (50 << 0 ) | (50 << 12 ) + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300030_TYPE, + D0F0xBC_xE0300030_ADDRESS, + (0xff << D0F0xBC_xE0300030_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300030_WriteOp_OFFSET) | + (3 << D0F0xBC_xE0300030_WriteOp_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300034_TYPE, + D0F0xBC_xE0300034_ADDRESS, + 0x0 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300030_TYPE, + D0F0xBC_xE0300030_ADDRESS, + (0xff << D0F0xBC_xE0300030_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300030_WriteOp_OFFSET) | (1 << D0F0xBC_xE0300030_WriteOp_OFFSET) + ), + GNB_ENTRY_STALL (1), + //Step 5: IF (cc_rcu_fuses.f.gpu_dis == 0x1) Skip Step6 ELSE Go to Step 6 + //Step 6: Disable PGFSM commands during reset. Move to after shutdown DCE. + //Step 7: Release control over DC2 PGFSM. Move to after shutdown DCE. + +// Shutdown DCE if integrated GFX disabled + //Step 1: Take control over DC2 PGFSM. By default display sends power up down commands. + //Step 2: Read CC_RCU_FUSES register + //Step 3: Enable PGFSM commands during reset + //Step 4: Make sure SCLK frequency is below 400Mhz + //Step 5: Enable PGFSM clock + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0300324_TYPE, + D0F0xBC_xE0300324_ADDRESS, + D0F0xBC_xE0300324_Dc2PgfsmClockEn_MASK, + (1 << D0F0xBC_xE0300324_Dc2PgfsmClockEn_OFFSET) + ), + //Step 6 + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0300030_TYPE, + D0F0xBC_xE0300030_ADDRESS, + (0xff << D0F0xBC_xE0300030_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300030_PowerDown_OFFSET) | + (1 << D0F0xBC_xE0300030_P1Select_OFFSET) | (1 << D0F0xBC_xE0300030_P2Select_OFFSET) + ), + //Step 7 + GNB_ENTRY_PROPERTY_POLL ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0300210_TYPE, + D0F0xBC_xE0300210_ADDRESS, + D0F0xBC_xE0300210_P1IsoN_MASK, + (0 << D0F0xBC_xE0300210_P1IsoN_OFFSET) + ), + //Step 8: Restore previous SCLK divider + //Step 9: Wait PSO daughter to be asserted + GNB_ENTRY_PROPERTY_POLL ( + TABLE_PROPERTY_IGFX_DISABLED, + TYPE_D0F0xBC , + 0xe0300210 , + 0x2000 , + (1 << 13 ) + ), + //Step 10: Turn off PGFSM clock + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0300324_TYPE, + D0F0xBC_xE0300324_ADDRESS, + D0F0xBC_xE0300324_Dc2PgfsmClockEn_MASK, + (0 << D0F0xBC_xE0300324_Dc2PgfsmClockEn_OFFSET) + ), + //Step 11: Disable PGFSM commands during reset. Same final 2 step as DCE power island + GNB_ENTRY_RMW ( + D0F0xBC_xE0003024_TYPE, + D0F0xBC_xE0003024_ADDRESS, + 0x1, + 0x0 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE03002DC_TYPE, + D0F0xBC_xE03002DC_ADDRESS, + (0 << D0F0xBC_xE03002DC_DC2_PGFSM_CONTROL_OFFSET) + ), + +//--------------------------------------------------------------------------- +// Configure GFX Power Island + + //Step 3 + GNB_ENTRY_WR ( + D0F0xBC_xE0300058_TYPE, + D0F0xBC_xE0300058_ADDRESS, + (5 << 16 ) | (4 << 8 ) | + (10 << 0 ) //reg0 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300054_TYPE, + D0F0xBC_xE0300054_ADDRESS, + (0xff << D0F0xBC_xE0300054_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300054_WriteOp_OFFSET) | + (2 << D0F0xBC_xE0300054_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300058_TYPE, + D0F0xBC_xE0300058_ADDRESS, + (50 << 0 ) | (50 << 12 ) //reg1 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300054_TYPE, + D0F0xBC_xE0300054_ADDRESS, + (0xff << D0F0xBC_xE0300054_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300054_WriteOp_OFFSET) | + (3 << D0F0xBC_xE0300054_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300058_TYPE, + D0F0xBC_xE0300058_ADDRESS, + 0 // control + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300054_TYPE, + D0F0xBC_xE0300054_ADDRESS, + (0xff << D0F0xBC_xE0300054_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300054_WriteOp_OFFSET) | + (1 << D0F0xBC_xE0300054_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + // Step 4 + GNB_ENTRY_WR ( + D0F0xBC_xE0300074_TYPE, + D0F0xBC_xE0300074_ADDRESS, + (5 << 16 ) | (4 << 8 ) | + (10 << 0 ) //reg0 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300070_TYPE, + D0F0xBC_xE0300070_ADDRESS, + (0xff << D0F0xBC_xE0300070_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300070_WriteOp_OFFSET) | + (2 << D0F0xBC_xE0300070_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300074_TYPE, + D0F0xBC_xE0300074_ADDRESS, + (50 << 0 ) | (50 << 12 ) //reg1 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300070_TYPE, + D0F0xBC_xE0300070_ADDRESS, + (0xff << D0F0xBC_xE0300070_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300070_WriteOp_OFFSET) | + (3 << D0F0xBC_xE0300070_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300074_TYPE, + D0F0xBC_xE0300074_ADDRESS, + 0 // control + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300070_TYPE, + D0F0xBC_xE0300070_ADDRESS, + (0xff << D0F0xBC_xE0300070_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300070_WriteOp_OFFSET) | + (1 << D0F0xBC_xE0300070_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + // Step 5 + GNB_ENTRY_WR ( + D0F0xBC_xE0300090_TYPE, + D0F0xBC_xE0300090_ADDRESS, + (5 << 16 ) | (4 << 8 ) | + (10 << 0 ) //reg0 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE030008C_TYPE, + D0F0xBC_xE030008C_ADDRESS, + (0xff << D0F0xBC_xE030008C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030008C_WriteOp_OFFSET) | + (2 << D0F0xBC_xE030008C_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300090_TYPE, + D0F0xBC_xE0300090_ADDRESS, + (50 << 0 ) | (50 << 12 ) //reg1 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE030008C_TYPE, + D0F0xBC_xE030008C_ADDRESS, + (0xff << D0F0xBC_xE030008C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030008C_WriteOp_OFFSET) | + (3 << D0F0xBC_xE030008C_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300090_TYPE, + D0F0xBC_xE0300090_ADDRESS, + 0 // control + ), + GNB_ENTRY_WR ( + D0F0xBC_xE030008C_TYPE, + D0F0xBC_xE030008C_ADDRESS, + (0xff << D0F0xBC_xE030008C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030008C_WriteOp_OFFSET) | + (1 << D0F0xBC_xE030008C_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + // Step 6 + GNB_ENTRY_WR ( + D0F0xBC_xE03000AC_TYPE, + D0F0xBC_xE03000AC_ADDRESS, + (5 << 16 ) | (4 << 8 ) | + (10 << 0 ) //reg0 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE03000A8_TYPE, + D0F0xBC_xE03000A8_ADDRESS, + (0xff << D0F0xBC_xE03000A8_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000A8_WriteOp_OFFSET) | + (2 << D0F0xBC_xE03000A8_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE03000AC_TYPE, + D0F0xBC_xE03000AC_ADDRESS, + (50 << 0 ) | (50 << 12 ) //reg1 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE03000A8_TYPE, + D0F0xBC_xE03000A8_ADDRESS, + (0xff << D0F0xBC_xE03000A8_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000A8_WriteOp_OFFSET) | + (3 << D0F0xBC_xE03000A8_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE03000AC_TYPE, + D0F0xBC_xE03000AC_ADDRESS, + 0 // control + ), + GNB_ENTRY_WR ( + D0F0xBC_xE03000A8_TYPE, + D0F0xBC_xE03000A8_ADDRESS, + (0xff << D0F0xBC_xE03000A8_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000A8_WriteOp_OFFSET) | + (1 << D0F0xBC_xE03000A8_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + // Step 7 + GNB_ENTRY_WR ( + D0F0xBC_xE03000C8_TYPE, + D0F0xBC_xE03000C8_ADDRESS, + (5 << 16 ) | (4 << 8 ) | + (10 << 0 ) //reg0 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE03000C4_TYPE, + D0F0xBC_xE03000C4_ADDRESS, + (0xff << D0F0xBC_xE03000C4_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000C4_WriteOp_OFFSET) | + (2 << D0F0xBC_xE03000C4_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE03000C8_TYPE, + D0F0xBC_xE03000C8_ADDRESS, + (50 << 0 ) | (50 << 12 ) //reg1 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE03000C4_TYPE, + D0F0xBC_xE03000C4_ADDRESS, + (0xff << D0F0xBC_xE03000C4_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000C4_WriteOp_OFFSET) | + (3 << D0F0xBC_xE03000C4_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE03000C8_TYPE, + D0F0xBC_xE03000C8_ADDRESS, + 0 // control + ), + GNB_ENTRY_WR ( + D0F0xBC_xE03000C4_TYPE, + D0F0xBC_xE03000C4_ADDRESS, + (0xff << D0F0xBC_xE03000C4_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000C4_WriteOp_OFFSET) | + (1 << D0F0xBC_xE03000C4_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + // Step 8 + GNB_ENTRY_WR ( + D0F0xBC_xE03000E4_TYPE, + D0F0xBC_xE03000E4_ADDRESS, + (5 << 16 ) | (4 << 8 ) | + (10 << 0 ) //reg0 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE03000E0_TYPE, + D0F0xBC_xE03000E0_ADDRESS, + (0xff << D0F0xBC_xE03000E0_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000E0_WriteOp_OFFSET) | + (2 << D0F0xBC_xE03000E0_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE03000E4_TYPE, + D0F0xBC_xE03000E4_ADDRESS, + (50 << 0 ) | (50 << 12 ) //reg1 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE03000E0_TYPE, + D0F0xBC_xE03000E0_ADDRESS, + (0xff << D0F0xBC_xE03000E0_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000E0_WriteOp_OFFSET) | + (3 << D0F0xBC_xE03000E0_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE03000E4_TYPE, + D0F0xBC_xE03000E4_ADDRESS, + 0 // control + ), + GNB_ENTRY_WR ( + D0F0xBC_xE03000E0_TYPE, + D0F0xBC_xE03000E0_ADDRESS, + (0xff << D0F0xBC_xE03000E0_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000E0_WriteOp_OFFSET) | + (1 << D0F0xBC_xE03000E0_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + // Step 9 + GNB_ENTRY_WR ( + D0F0xBC_xE0300100_TYPE, + D0F0xBC_xE0300100_ADDRESS, + (5 << 16 ) | (4 << 8 ) | + (10 << 0 ) //reg0 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE03000FC_TYPE, + D0F0xBC_xE03000FC_ADDRESS, + (0xff << D0F0xBC_xE03000FC_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000FC_WriteOp_OFFSET) | + (2 << D0F0xBC_xE03000FC_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300100_TYPE, + D0F0xBC_xE0300100_ADDRESS, + (50 << 0 ) | (50 << 12 ) //reg1 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE03000FC_TYPE, + D0F0xBC_xE03000FC_ADDRESS, + (0xff << D0F0xBC_xE03000FC_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000FC_WriteOp_OFFSET) | + (3 << D0F0xBC_xE03000FC_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300100_TYPE, + D0F0xBC_xE0300100_ADDRESS, + 0 // control + ), + GNB_ENTRY_WR ( + D0F0xBC_xE03000FC_TYPE, + D0F0xBC_xE03000FC_ADDRESS, + (0xff << D0F0xBC_xE03000FC_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000FC_WriteOp_OFFSET) | + (1 << D0F0xBC_xE03000FC_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + // Step 10 + GNB_ENTRY_RMW ( + TYPE_D0F0xBC , + 0xe0300328 , + 0x1 | 0x2 | + 0x4 | 0x8 | + 0x10 | 0x20 | + 0x40 , + 0x0 + ), + // Step 12 + GNB_ENTRY_RMW ( + D0F0xBC_xE0003024_TYPE, + D0F0xBC_xE0003024_ADDRESS, + 0x1, + 0x0 + ), +// Shutdown Gfx if integrated GFX disabled + // Step 2 + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0003024_TYPE, + D0F0xBC_xE0003024_ADDRESS, + 0x1, + 0x1 + ), + // Step 3: Save current SCLK. Make sure SCLK frequency is below 400Mhz + // Step 5 + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + TYPE_D0F0xBC , + 0xe0300328 , + 0x1 | 0x2 | + 0x4 | 0x8 | + 0x10 | 0x20 | + 0x40 , + (1 << 0 ) | (1 << 1 ) | + (1 << 2 ) | (1 << 3 ) | + (1 << 4 ) | (1 << 5 ) | + (1 << 6 ) + ), + // Step 6 + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0300054_TYPE, + D0F0xBC_xE0300054_ADDRESS, + (0xff << D0F0xBC_xE0300054_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300054_PowerDown_OFFSET) | + (1 << D0F0xBC_xE0300054_P1Select_OFFSET) | (1 << D0F0xBC_xE0300054_P2Select_OFFSET) + ), + // Step 7 + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0300070_TYPE, + D0F0xBC_xE0300070_ADDRESS, + (0xff << D0F0xBC_xE0300070_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300070_PowerDown_OFFSET) | + (1 << D0F0xBC_xE0300070_P1Select_OFFSET) | (1 << D0F0xBC_xE0300070_P2Select_OFFSET) + ), + // Step 8 + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE030008C_TYPE, + D0F0xBC_xE030008C_ADDRESS, + (0xff << D0F0xBC_xE030008C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030008C_PowerDown_OFFSET) | + (1 << D0F0xBC_xE030008C_P1Select_OFFSET) | (1 << D0F0xBC_xE030008C_P2Select_OFFSET) + ), + // Step 9 + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE03000A8_TYPE, + D0F0xBC_xE03000A8_ADDRESS, + (0xff << D0F0xBC_xE03000A8_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000A8_PowerDown_OFFSET) | + (1 << D0F0xBC_xE03000A8_P1Select_OFFSET) | (1 << D0F0xBC_xE03000A8_P2Select_OFFSET) + ), + // Step 10 + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE03000C4_TYPE, + D0F0xBC_xE03000C4_ADDRESS, + (0xff << D0F0xBC_xE03000C4_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000C4_PowerDown_OFFSET) | + (1 << D0F0xBC_xE03000C4_P1Select_OFFSET) | (1 << D0F0xBC_xE03000C4_P2Select_OFFSET) + ), + // Step 11 + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE03000E0_TYPE, + D0F0xBC_xE03000E0_ADDRESS, + (0xff << D0F0xBC_xE03000E0_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000E0_PowerDown_OFFSET) | + (1 << D0F0xBC_xE03000E0_P1Select_OFFSET) | (1 << D0F0xBC_xE03000E0_P2Select_OFFSET) + ), + // Step 12 + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE03000FC_TYPE, + D0F0xBC_xE03000FC_ADDRESS, + (0xff << D0F0xBC_xE03000FC_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000FC_PowerDown_OFFSET) | + (1 << D0F0xBC_xE03000FC_P1Select_OFFSET) | (1 << D0F0xBC_xE03000FC_P2Select_OFFSET) + ), + // Step 13 + GNB_ENTRY_PROPERTY_POLL ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE03002F4_TYPE, + D0F0xBC_xE03002F4_ADDRESS, + 0xFFFFFFFF, + 0 + ), + // Step 14 + GNB_ENTRY_PROPERTY_POLL ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE03002F0_TYPE, + D0F0xBC_xE03002F0_ADDRESS, + 0xFFFFFFFF, + 0 + ), + // Step 15: Restore SCLK that is saved in step 4 + // Step 16 + GNB_ENTRY_FULL_POLL ( + TABLE_PROPERTY_IGFX_DISABLED, + (AMD_F15_TN_ALL & 0x0000000000000100ull) /* AMD_F15_TN_GT_A0 */, + D0F0xBC_xE03002FC_TYPE, + D0F0xBC_xE03002FC_ADDRESS, + 0xFFFFFFFF, + 0x3FFFFFFF + ), + // Step 17 + GNB_ENTRY_FULL_POLL ( + TABLE_PROPERTY_IGFX_DISABLED, + (AMD_F15_TN_ALL & 0x0000000000000100ull) /* AMD_F15_TN_GT_A0 */, + D0F0xBC_xE03002E4_TYPE, + D0F0xBC_xE03002E4_ADDRESS, + 0xFFFFFFFF, + 0x3FFFF + ), + // Step 18 + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + TYPE_D0F0xBC , + 0xe0300328 , + 0x1 | 0x2 | + 0x4 | 0x8 | + 0x10 | 0x20 | + 0x40 , + 0 + ), + // Step 19 + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0003024_TYPE, + D0F0xBC_xE0003024_ADDRESS, + 0x1, + 0x0 + ), +//--------------------------------------------------------------------------- +// Isolate DC, SYS and CP tile when Internal Graphics is disabled + // Step 2: Reduce SCLK frequency to 100Mhz. Save current SCLK divider. + // Step 3 + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F0xBC_xE0003034_TYPE, + D0F0xBC_xE0003034_ADDRESS, + D0F0xBC_xE0003034_SysIso_MASK | D0F0xBC_xE0003034_CpIso_MASK | + D0F0xBC_xE0003034_Dc0Iso_MASK | D0F0xBC_xE0003034_Dc1Iso_MASK | + D0F0xBC_xE0003034_DciIso_MASK | D0F0xBC_xE0003034_DcipgIso_MASK, + (1 << D0F0xBC_xE0003034_SysIso_OFFSET) | (1 << D0F0xBC_xE0003034_CpIso_OFFSET) | + (1 << D0F0xBC_xE0003034_Dc0Iso_OFFSET) | (1 << D0F0xBC_xE0003034_Dc1Iso_OFFSET) | + (1 << D0F0xBC_xE0003034_DciIso_OFFSET) | (1 << D0F0xBC_xE0003034_DcipgIso_OFFSET) + ), + //Step 4: Restore pervious SCLK frequency + +//--------------------------------------------------------------------------- +// For IOMMU add logic of GfxDis + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + D0F2xF4_x57_TYPE, + D0F2xF4_x57_ADDRESS, + D0F2xF4_x57_L1ImuIntGfxDis_MASK, + (0x1 << D0F2xF4_x57_L1ImuIntGfxDis_OFFSET) + ), + + GNB_ENTRY_TERMINATE +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c new file mode 100644 index 0000000..b8dc935 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c @@ -0,0 +1,353 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe early post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbBapmCoeffCalcTN.h" +#include "GnbRegisterAccTN.h" +#include "GnbRegistersTN.h" +#include "GnbInitTN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBBAPMCOEFFCALC_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +#define GnbFpLibGetExp(V) ((INT32) ((*((UINT64*) &Value) >> 52) & 0x7FF) - (1023 + 52)) +#define GnbFpLibGetMnts(V) (INT64) ((*((UINT64*) &Value) & ((1ull << 52) - 1)) | (1ull << 52)) + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +INT32 _fltused = 0; + +/*----------------------------------------------------------------------------------------*/ +/** + * Calculate power of + * + * + * @param[in] Value value + * @param[in] Pow power + * @retval Value^Pow + */ + +STATIC DOUBLE +GnbBapmPowerOf ( + IN DOUBLE Value, + IN UINTN Pow + ) +{ + DOUBLE Result; + Result = Value; + while ( --Pow > 0) { + Result *= Value; + } + return Result; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Decode R from fuse + * + * + * @param[in] FuseR R fused value + * @retval R + */ +STATIC DOUBLE +GnbBapmDecodeR ( + IN UINT32 FuseR + ) +{ + DOUBLE Value; + Value = ((DOUBLE) (FuseR & 0x1ff)) / (2 << (8 - 1)); + Value = GnbBapmPowerOf (Value, 4); + return ((FuseR & 0x200) != 0) ? (-1) * Value : Value; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Decode Tau from fuse + * + * + * @param[in] FuseTau Tau fused value + * @retval Tau + */ +STATIC DOUBLE +GnbBapmDecodeTau ( + IN UINT32 FuseTau + ) +{ + DOUBLE Value; + Value = FuseTau; + Value = GnbBapmPowerOf (Value / (2 << (9 - 1)), 16); + return Value; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Calaculate X + * + * + * @param[in] Ts Samplig rate + * @param[in] Tau Tau value + * @param[in] R R value + * @retval X + */ +STATIC DOUBLE +GnbBapmCalculateX ( + IN DOUBLE Ts, + IN DOUBLE Tau, + IN DOUBLE R + ) +{ + //X=(R*Ts)/(2*Tau+Ts); + DOUBLE Result; + Result = (R * Ts) / (2 * Tau + Ts); + return (Result * GnbBapmPowerOf (2, 36)) + 0.5; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Calaculate Y + * + * + * @param[in] Ts Samplig rate + * @param[in] Tau Tau value + * @retval Y + */ +STATIC DOUBLE +GnbBapmCalculateY ( + IN DOUBLE Ts, + IN DOUBLE Tau + ) +{ + //Y=(2*Tau-Ts)/(2*Tau+Ts); + DOUBLE Result; + Result = (2 * Tau - Ts) / (2 * Tau + Ts); + return (Result * GnbBapmPowerOf (2, 32)) + 0.5; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set X & Y value + * + * + * @param[in] X X value + * @param[in] Y Y value + * @param[in] AddrOffset Offset of address + * @param[in] StdHeader Standard configuration header + */ +STATIC VOID +GnbBapmSetYAndX ( + IN INT32 X, + IN INT32 Y, + IN UINT32 AddrOffset, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GnbRegisterWriteTN ( + D0F0xBC_x1F480_TYPE, + D0F0xBC_x1F480_ADDRESS + AddrOffset, + &X, + 0, + StdHeader + ); + IDS_HDT_CONSOLE (GNB_TRACE, "X: 0x%08x\n", X); + GnbRegisterWriteTN ( + D0F0xBC_x1F480_TYPE, + D0F0xBC_x1F480_ADDRESS + AddrOffset + 4, + &Y, + 0, + StdHeader + ); + IDS_HDT_CONSOLE (GNB_TRACE, "Y: 0x%08x\n", Y); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Extract INt32 from DOUBLE + * + * + * + * @param[in] Value Double value + * @retval int32 + */ +INT32 +GnbFpLibDoubleToInt32 ( + IN DOUBLE Value + ) +{ + INT64 Mantissa; + INT32 Exponent; + Mantissa = GnbFpLibGetMnts (Value); + Exponent = GnbFpLibGetExp (Value); + if (Exponent < -64) { + Mantissa = 0; + } else if (Exponent < 0) { + Mantissa >>= - Exponent; + } else { + Mantissa <<= Exponent; + } + return (INT32) ((Value < 0) ? - Mantissa : Mantissa); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Calcuate BAPM coefficient + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +VOID +GnbBapmCalculateCoeffsTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 RFuse1; + UINT32 TauFuse1; + UINT32 Index; + DOUBLE R; + DOUBLE Tau; + DOUBLE Ts; + INT32 X; + INT32 Y; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmCalculateCoeffsTN Enter\n"); + + LibAmdFinit (); + + Ts = ((DOUBLE) (D0F0xBC_x1F468_TimerPeriod_Value * D0F0xBC_x1F46C_BapmPeriod_Value) / 100) / 1000000; + + for (Index = 0; Index < 15; Index++) { + GnbRegisterReadTN ( + TYPE_D0F0xBC , + 0xe01040c4 + Index * 4, + &RFuse1, + 0, + StdHeader + ); + GnbRegisterReadTN ( + TYPE_D0F0xBC , + 0xe01040c4 + (Index + 15) * 4, + &TauFuse1, + 0, + StdHeader + ); + + R = GnbBapmDecodeR (RFuse1 & 0x3FF); + Tau = GnbBapmDecodeTau (TauFuse1 & 0x3FF); + + X = GnbFpLibDoubleToInt32 (GnbBapmCalculateX (Ts, Tau, R)); + Y = GnbFpLibDoubleToInt32 (GnbBapmCalculateY (Ts, Tau)); + GnbBapmSetYAndX (X, Y, Index * 2 * 4, StdHeader); + + R = GnbBapmDecodeR ((RFuse1 >> 10) & 0x3FF); + Tau = GnbBapmDecodeTau ((TauFuse1 >> 10) & 0x3FF); + + X = GnbFpLibDoubleToInt32 (GnbBapmCalculateX (Ts, Tau, R)); + Y = GnbFpLibDoubleToInt32 (GnbBapmCalculateY (Ts, Tau)); + + GnbBapmSetYAndX (X, Y, (Index * 2 + 30) * 4 , StdHeader); + + R = GnbBapmDecodeR ((RFuse1 >> 20) & 0x3FF); + Tau = GnbBapmDecodeTau ((TauFuse1 >> 20) & 0x3FF); + + X = GnbFpLibDoubleToInt32 (GnbBapmCalculateX (Ts, Tau, R)); + Y = GnbFpLibDoubleToInt32 (GnbBapmCalculateY (Ts, Tau)); + + GnbBapmSetYAndX (X, Y, (Index * 2 + 60) * 4 , StdHeader); + } + IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmCalculateCoeffsTN Exit\n"); +} + + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.h new file mode 100644 index 0000000..3ed7b48 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.h @@ -0,0 +1,87 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB CAC weights table + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBBAPMCOEFFCALCTN_H_ +#define _GNBBAPMCOEFFCALCTN_H_ + +typedef double DOUBLE; + +VOID +GnbBapmCalculateCoeffsTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +INT32 +GnbFpLibDoubleToInt32 ( + IN DOUBLE Value + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h new file mode 100644 index 0000000..bf17ad1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h @@ -0,0 +1,175 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB CAC weights table + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBCACWEIGHTSTABLETN_H_ +#define _GNBCACWEIGHTSTABLETN_H_ + +UINT32 CacWeightsTN[] = { + 0xD65, + 0x289A, + 0x289A, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x16F, + 0x0, + 0x0, + 0x0, + 0x0, + 0x16A5, + 0x592, + 0x0, + 0x0, + 0xE60, + 0x0, + 0xE60, + 0x0, + 0xE60, + 0x0, + 0xE60, + 0x0, + 0xE60, + 0x0, + 0xE60, + 0xEC9, + 0xEC9, + 0x41A, + 0x41A, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0xF15, + 0xF15, + 0xF15, + 0xF15, + 0xF15, + 0xF15, + 0x79, + 0x79, + 0x79, + 0x0, + 0x0, + 0x0, + 0x0, + 0x3F2, + 0x3F2, + 0x0, + 0x0, + 0x123, + 0x0, + 0x0, + 0x0, + 0x123, + 0x0, + 0x0, + 0x0, + 0x0, + 0x195B, + 0x629, + 0x0, + 0x0, + 0x195B, + 0x629, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x755, + 0x0, + 0x755, + 0x0, + 0x755, + 0x0, + 0x755, + 0x0, + 0x755, + 0x0, + 0x755, + 0x0, + 0x88B, + 0x1206, + 0x0, + 0x88B, + 0x1206, + 0x0, + 0x0 +}; + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c new file mode 100644 index 0000000..b3b3101 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c @@ -0,0 +1,888 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe early post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 64732 $ @e $Date: 2012-01-30 02:16:26 -0600 (Mon, 30 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "OptionGnb.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbTable.h" +#include "GnbNbInitLibV4.h" +#include "GnbSmuFirmwareTN.h" +#include "GnbRegisterAccTN.h" +#include "GnbRegistersTN.h" +#include "GfxLibTN.h" +#include "GnbCacWeightsTN.h" +#include "cpuFamilyTranslation.h" +#include "GnbHandleLib.h" +#include "GnbBapmCoeffCalcTN.h" +#include "GnbInitTN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBEARLYINITTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_TABLE ROMDATA GnbEarlyInitTableTN []; +extern GNB_TABLE ROMDATA GnbEarlierInitTableBeforeSmuTN []; +extern GNB_TABLE ROMDATA GnbEarlierInitTableAfterSmuTN []; +extern GNB_BUILD_OPTIONS GnbBuildOptions; +extern BUILD_OPT_CFG UserOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GnbEarlyInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbEarlierInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader +); +/*----------------------------------------------------------------------------------------*/ +/** + * Gnb TN Decrease all of the SMU VIDs by 4 (+25mV) + + * + * + * + * @param[in] StdHeader Standard configuration header + */ +STATIC VOID +GnbAdjustSmuVidBeforeSmuTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D0F0xBC_xE0001008_STRUCT D0F0xBC_xE0001008; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbAdjustSmuVidBeforeSmuTN Enter\n"); + + GnbRegisterReadTN (D0F0xBC_xE0001008_TYPE, D0F0xBC_xE0001008_ADDRESS, &D0F0xBC_xE0001008, 0, StdHeader); + D0F0xBC_xE0001008.Field.SClkVid3 -= 4; + D0F0xBC_xE0001008.Field.SClkVid2 -= 4; + D0F0xBC_xE0001008.Field.SClkVid1 -= 4; + D0F0xBC_xE0001008.Field.SClkVid0 -= 4; + GnbRegisterWriteTN (D0F0xBC_xE0001008_TYPE, D0F0xBC_xE0001008_ADDRESS, &D0F0xBC_xE0001008, 0, StdHeader); + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbAdjustSmuVidBeforeSmuTN Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Gnb TN Decrease all of the SMU VIDs by 4 (+25mV) + + * + * + * + * @param[in] StdHeader Standard configuration header + */ +STATIC VOID +GnbAdjustSmuVidAfterSmuTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D0F0xBC_x1F88C_STRUCT D0F0xBC_x1F88C; + D0F0xBC_x1F8DC_STRUCT D0F0xBC_x1F8DC; + D0F0xBC_x1F8E0_STRUCT D0F0xBC_x1F8E0; + D0F0xBC_x1F8E4_STRUCT D0F0xBC_x1F8E4; + D0F0xBC_x1F8E8_STRUCT D0F0xBC_x1F8E8; + D0F0xBC_x1F400_STRUCT D0F0xBC_x1F400; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbAdjustSmuVidAfterSmuTN Enter\n"); + + //Adjust SMU VIDs + GnbRegisterReadTN (D0F0xBC_x1F88C_TYPE, D0F0xBC_x1F88C_ADDRESS, &D0F0xBC_x1F88C, 0, StdHeader); + GnbRegisterReadTN (D0F0xBC_x1F8DC_TYPE, D0F0xBC_x1F8DC_ADDRESS, &D0F0xBC_x1F8DC, 0, StdHeader); + GnbRegisterReadTN (D0F0xBC_x1F8E0_TYPE, D0F0xBC_x1F8E0_ADDRESS, &D0F0xBC_x1F8E0, 0, StdHeader); + GnbRegisterReadTN (D0F0xBC_x1F8E4_TYPE, D0F0xBC_x1F8E4_ADDRESS, &D0F0xBC_x1F8E4, 0, StdHeader); + GnbRegisterReadTN (D0F0xBC_x1F8E8_TYPE, D0F0xBC_x1F8E8_ADDRESS, &D0F0xBC_x1F8E8, 0, StdHeader); + + D0F0xBC_x1F88C.Field.NbVid_3 -= 4; + D0F0xBC_x1F88C.Field.NbVid_2 -= 4; + D0F0xBC_x1F88C.Field.NbVid_1 -= 4; + D0F0xBC_x1F88C.Field.NbVid_0 -= 4; + + D0F0xBC_x1F8DC.Field.SClkVid3 -= 4; + D0F0xBC_x1F8DC.Field.SClkVid2 -= 4; + D0F0xBC_x1F8DC.Field.SClkVid1 -= 4; + D0F0xBC_x1F8DC.Field.SClkVid0 -= 4; + D0F0xBC_x1F8E0.Field.BapmSclkVid_2 -= 4; + D0F0xBC_x1F8E0.Field.BapmSclkVid_1 -= 4; + D0F0xBC_x1F8E0.Field.BapmSclkVid_0 -= 4; + D0F0xBC_x1F8E4.Field.BapmNbVid_1 -= 4; + D0F0xBC_x1F8E4.Field.BapmNbVid_0 -= 4; + D0F0xBC_x1F8E4.Field.BapmSclkVid_3 -= 4; + D0F0xBC_x1F8E8.Field.BapmNbVid_3 -= 4; + D0F0xBC_x1F8E8.Field.BapmNbVid_2 -= 4; + + GnbRegisterWriteTN (D0F0xBC_x1F88C_TYPE, D0F0xBC_x1F88C_ADDRESS, &D0F0xBC_x1F88C, 0, StdHeader); + GnbRegisterWriteTN (D0F0xBC_x1F8DC_TYPE, D0F0xBC_x1F8DC_ADDRESS, &D0F0xBC_x1F8DC, 0, StdHeader); + GnbRegisterWriteTN (D0F0xBC_x1F8E0_TYPE, D0F0xBC_x1F8E0_ADDRESS, &D0F0xBC_x1F8E0, 0, StdHeader); + GnbRegisterWriteTN (D0F0xBC_x1F8E4_TYPE, D0F0xBC_x1F8E4_ADDRESS, &D0F0xBC_x1F8E4, 0, StdHeader); + GnbRegisterWriteTN (D0F0xBC_x1F8E8_TYPE, D0F0xBC_x1F8E8_ADDRESS, &D0F0xBC_x1F8E8, 0, StdHeader); + + //D0F0xBC_x1F400[SviLoadLineOffsetVddNB]=01b (-25mV) + GnbRegisterReadTN (D0F0xBC_x1F400_TYPE, D0F0xBC_x1F400_ADDRESS, &D0F0xBC_x1F400, 0, StdHeader); + D0F0xBC_x1F400.Field.SviLoadLineOffsetVddNB = 1; + GnbRegisterWriteTN (D0F0xBC_x1F400_TYPE, D0F0xBC_x1F400_ADDRESS, &D0F0xBC_x1F400, 0, StdHeader); + + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbAdjustSmuVidAfterSmuTN Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Gnb SMU LHTC support + * + * Part of BAPM enablement. + * When BAPM is disabled in battery mode firmware will enable LHTC. + * + * @param[in] StdHeader Standard configuration header + */ +STATIC VOID +GnbBapmLhtcInitTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D0F0xBC_x1F638_STRUCT D0F0xBC_x1F638; + D0F0xBC_x1F428_STRUCT D0F0xBC_x1F428; + D0F0xBC_x1F86C_STRUCT D0F0xBC_x1F86C; + D0F0xBC_x1F628_STRUCT D0F0xBC_x1F628; + D0F0xBC_xE0104188_STRUCT D0F0xBC_xE0104188; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmLhtcInitTN Enter\n"); + + GnbRegisterReadTN (D0F0xBC_x1F638_TYPE, D0F0xBC_x1F638_ADDRESS, &D0F0xBC_x1F638, 0, StdHeader); + GnbRegisterReadTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader); + GnbRegisterReadTN (D0F0xBC_xE0104188_TYPE, D0F0xBC_xE0104188_ADDRESS, &D0F0xBC_xE0104188, 0, StdHeader); + + //1. Set HTC period to 10 in PM_TIMERS_2 register + //Still need to keep PM_CONFIG.Enable_HTC_Limit to 0 + D0F0xBC_x1F428.Field.field_4 = 0; + GnbRegisterWriteTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader); + D0F0xBC_x1F638.Field.HtcPeriod = 10; + GnbRegisterWriteTN (D0F0xBC_x1F638_TYPE, D0F0xBC_x1F638_ADDRESS, &D0F0xBC_x1F638, 0, StdHeader); + + //2. Read BapmLhtcCap fuse + GnbRegisterReadTN (D0F0xBC_x1F86C_TYPE, D0F0xBC_x1F86C_ADDRESS, &D0F0xBC_x1F86C, 0, StdHeader); + GnbRegisterReadTN (D0F0xBC_x1F628_TYPE, D0F0xBC_x1F628_ADDRESS, &D0F0xBC_x1F628, 0, StdHeader); + if (D0F0xBC_x1F86C.Field.BapmLhtcCap == 0) { + D0F0xBC_x1F628.Field.HtcActivePstateLimit = 0; + } else { + D0F0xBC_x1F628.Field.HtcActivePstateLimit = D0F0xBC_xE0104188.Field.LhtcPstateLimit; + } + GnbRegisterWriteTN (D0F0xBC_x1F628_TYPE, D0F0xBC_x1F628_ADDRESS, &D0F0xBC_x1F628, 0, StdHeader); + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmLhtcInitTN Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Measured temperature with BAPM + * + * + * + * + * @param[in] StdHeader Standard configuration header + */ +STATIC VOID +GnbBapmMeasuredTempTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D0F0xBC_x1F428_STRUCT D0F0xBC_x1F428; + D0F0xBC_xE0104188_STRUCT D0F0xBC_xE0104188; + D0F0xBC_x1F844_STRUCT D0F0xBC_x1F844; + D0F0xBC_x1F848_STRUCT D0F0xBC_x1F848; + D0F0xBC_x1F84C_STRUCT D0F0xBC_x1F84C; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmMeasuredTempTN Enter\n"); + + GnbRegisterReadTN (D0F0xBC_xE0104188_TYPE, D0F0xBC_xE0104188_ADDRESS, &D0F0xBC_xE0104188, 0, StdHeader); + + //Measured temperature with BAPM + GnbRegisterReadTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader); + D0F0xBC_x1F428.Field.line180 = 0; + if (D0F0xBC_xE0104188.Field.BapmMeasuredTemp == 1) { + D0F0xBC_x1F844.Value = 0x38B; + GnbRegisterWriteTN (D0F0xBC_x1F844_TYPE, D0F0xBC_x1F844_ADDRESS, &D0F0xBC_x1F844, 0, StdHeader); + D0F0xBC_x1F848.Value = 0x38D; + GnbRegisterWriteTN (D0F0xBC_x1F848_TYPE, D0F0xBC_x1F848_ADDRESS, &D0F0xBC_x1F848, 0, StdHeader); + D0F0xBC_x1F84C.Value = 0x389; + GnbRegisterWriteTN (D0F0xBC_x1F84C_TYPE, D0F0xBC_x1F84C_ADDRESS, &D0F0xBC_x1F84C, 0, StdHeader); + + D0F0xBC_x1F428.Field.line180 = 1; + } + GnbRegisterWriteTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader); + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmMeasuredTempTN Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Gnb SMU LHTC Enable + * + * Part of BAPM enablement. + * When BAPM is disabled in battery mode firmware will enable LHTC. + * + * @param[in] StdHeader Standard configuration header + */ +STATIC VOID +GnbLhtcEnableTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D0F0xBC_x1F428_STRUCT D0F0xBC_x1F428; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbLhtcEnableTN Enter\n"); + + GnbRegisterReadTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader); + D0F0xBC_x1F428.Field.field_4 = 1; + GnbRegisterWriteTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader); + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbLhtcEnableTN Exit\n"); +} +/*----------------------------------------------------------------------------------------*/ +/** + * Gnb TN Update BAPMTI_TjOffset + * + * + * + * @param[in] StdHeader Standard configuration header + */ +STATIC VOID +GnbTjOffsetUpdateTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D0F0xBC_x1F870_STRUCT D0F0xBC_x1F870; + + CPU_LOGICAL_ID LogicalId; + GNB_HANDLE *GnbHandle; + D0F0xBC_xE0104040_STRUCT D0F0xBC_xE0104040; + D0F0xBC_x1F85C_STRUCT D0F0xBC_x1F85C; + ex1075_STRUCT ex1075 ; + UINT32 TimerPeriod; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbTjOffsetUpdateTN Enter\n"); + + + TimerPeriod = D0F0xBC_x1F468_TimerPeriod_Value; + GnbRegisterReadTN (D0F0xBC_x1F85C_TYPE, D0F0xBC_x1F85C_ADDRESS, &D0F0xBC_x1F85C, 0, StdHeader); + GnbRegisterReadTN (TYPE_D0F0xBC , 0xe010413c , &ex1075, 0, StdHeader); + // Determine desired AgingRate: + // PM_FUSES4.TdpAgeRate * Fuse[BAPMTI_Ts] (encoded in us) + // Re-encode TdpAgeRate with 1ms BAPM interval + D0F0xBC_x1F85C.Field.TdpAgeRate = (D0F0xBC_x1F85C.Field.TdpAgeRate * ex1075.Field.ex1075_0 ) / (TimerPeriod / 100); + GnbRegisterWriteTN (D0F0xBC_x1F85C_TYPE, D0F0xBC_x1F85C_ADDRESS, &D0F0xBC_x1F85C, 0, StdHeader); + + GnbHandle = GnbGetHandle (StdHeader); + ASSERT (GnbHandle != NULL); + GetLogicalIdOfSocket (GnbGetSocketId (GnbHandle), &LogicalId, StdHeader); + if ((LogicalId.Revision & 0x0000000000000100ull ) != 0x0000000000000100ull ) { + IDS_HDT_CONSOLE (GNB_TRACE, "CPU Rev = %x, Skip GnbTjOffsetUpdateTN\n", LogicalId.Revision); + return; + } + GnbRegisterReadTN (D0F0xBC_xE0104040_TYPE, D0F0xBC_xE0104040_ADDRESS, &D0F0xBC_xE0104040, 0, StdHeader); + GnbRegisterReadTN (D0F0xBC_x1F870_TYPE, D0F0xBC_x1F870_ADDRESS, &D0F0xBC_x1F870, 0, StdHeader); + //9900h=FS1r2/FP2 Devastator + //9903h=FS1r2/FP2 Devastator Lite + //9990h=FS1r2/FP2 Scrapper + //9901h=FM2 Devastator + //9904h=FM2 Devastator Lite + //9991h=FM2 Scrapper + if ((D0F0xBC_xE0104040.Field.DeviceID == 0x9900) || (D0F0xBC_xE0104040.Field.DeviceID == 0x9903)) { + D0F0xBC_x1F870.Field.BAPMTI_TjOffset_0 = 0x26; + D0F0xBC_x1F870.Field.BAPMTI_TjOffset_1 = 0x26; + D0F0xBC_x1F870.Field.BAPMTI_TjOffset_2 = 0x26; + } else if (D0F0xBC_xE0104040.Field.DeviceID == 0x9990) { + D0F0xBC_x1F870.Field.BAPMTI_TjOffset_0 = 0x2E; + D0F0xBC_x1F870.Field.BAPMTI_TjOffset_1 = 0x2E; + D0F0xBC_x1F870.Field.BAPMTI_TjOffset_2 = 0x2E; + } else { + IDS_HDT_CONSOLE (GNB_TRACE, "GnbTjOffsetUpdateTN Skip DID- %x\n", D0F0xBC_xE0104040.Field.DeviceID); + } + GnbRegisterWriteTN (D0F0xBC_x1F870_TYPE, D0F0xBC_x1F870_ADDRESS, &D0F0xBC_x1F870, 0, StdHeader); + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbTjOffsetUpdateTN Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * GPU CAC enablement and weights programming + * + * + * + * @param[in] StdHeader Standard configuration header + */ + +STATIC VOID +GnbCacEnablement ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D0F0xBC_x1F464_STRUCT D0F0xBC_x1F464; + ex1071_STRUCT ex1071 ; + ex1072_STRUCT ex1072 ; + PCI_ADDR PciAddress; + UINT8 Index; + ex1073_STRUCT ex1073 ; + D18F5x160_STRUCT D18F5x160; + DOUBLE UnbCac; + GMMx898_STRUCT GMMx898; + + GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f920 , &ex1072, 0, StdHeader); + ex1072.Field.ex1072_2 = 0x29; + GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1f920 , &ex1072, 0, StdHeader); + + //UNB_CAC_VALUE.UNB_CAC = 2.3734E-04 * FNBPS0 (in MHz) * 2^GPU_CAC_AVRG_CNTL.WEIGHT_PREC + GnbRegisterReadTN (D18F5x160_TYPE, D18F5x160_ADDRESS, &D18F5x160.Value, 0, StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, "NBP0 10khz %x (%d)\n", GfxLibGetNclkTN ((UINT8) D18F5x160.Field.NbFid, (UINT8) D18F5x160.Field.NbDid), GfxLibGetNclkTN ((UINT8) D18F5x160.Field.NbFid, (UINT8) D18F5x160.Field.NbDid)); + UnbCac = 0.00000204831536 * (1 << ex1072.Field.ex1072_0 ) * GfxLibGetNclkTN ((UINT8) D18F5x160.Field.NbFid, (UINT8) D18F5x160.Field.NbDid); + ex1073.Field.ex1073_0 = (UINT32) GnbFpLibDoubleToInt32 (UnbCac); + IDS_HDT_CONSOLE (GNB_TRACE, "UnbCac %x (%d)\n", ex1073.Field.ex1073_0 , ex1073.Field.ex1073_0 ); + GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1f91c , &ex1073.Value, 0, StdHeader); + + GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f160 , &ex1071, 0, StdHeader); + ex1071.Field.ex1071_0 = 0x1; + ex1071.Field.ex1071_3 = 0x4; + ex1071.Field.ex1071_4 = 0x25; + GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1f160 , &ex1071, 0, StdHeader); + + GnbRegisterReadTN (GMMx898_TYPE, GMMx898_ADDRESS, &GMMx898, 0, StdHeader); + GMMx898.Field.Threshold = 0x31; + GnbRegisterWriteTN (GMMx898_TYPE, GMMx898_ADDRESS, &GMMx898, 0, StdHeader); + + // Set CAC/TDP interval + GnbRegisterReadTN (D0F0xBC_x1F464_TYPE, D0F0xBC_x1F464_ADDRESS, &D0F0xBC_x1F464, 0, StdHeader); + D0F0xBC_x1F464.Field.TdpCntl = 1; + GnbRegisterWriteTN (D0F0xBC_x1F464_TYPE, D0F0xBC_x1F464_ADDRESS, &D0F0xBC_x1F464, 0, StdHeader); + + // Program GPU CAC weights + + for (Index = 0; Index < (sizeof (CacWeightsTN) / sizeof (CacWeightsTN[0])); Index++) { + GnbRegisterWriteTN (TYPE_D0F0xBC , (0x1f9a0 + (Index * 4)), &CacWeightsTN[Index], 0, StdHeader); + } + + // Call BIOS service SMC_MSG_CONFIG_TDP_CNTL + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0); + GnbSmuServiceRequestV4 ( + PciAddress, + SMC_MSG_CONFIG_TDP_CNTL, + 0, + StdHeader + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Decode power of CPU out of Watt + * + * + * + * @param[in] Encode PwrCpu encode + * @param[in] StdHeader Standard Configuration Header + * @retval mWatt + */ +STATIC INT32 +CpuPowerDecode ( + IN UINT8 Encode, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + INT32 Power; + ex1002_STRUCT ex1002 ; + + GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f850 , &ex1002, 0, StdHeader); + + //TdpWatt = TdpWattEncode / 1024 + //PwrCpu / TdpWatt = Encode + //PwrCpu = Encode * TdpWattEncode / 1024 + + Power = (INT32) ((Encode * ex1002.Field.ex1002_0 *1000) / 1024); + + return Power; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Encode the offset of power of CPU + * + * + * + * @param[in] NewPower New power of mWatt + * @param[in] OrgPower Original power of mWatt + * @param[in] StdHeader Standard Configuration Header + * @retval Encode + */ +STATIC UINT8 +CpuPowerOffsetEncode ( + IN INT32 NewPower, + IN INT32 OrgPower, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + INT8 PowerOffsetEncode; + INT32 PowerOffset; + ex1002_STRUCT ex1002 ; + BOOLEAN Postive; + + GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f850 , &ex1002, 0, StdHeader); + if (NewPower > OrgPower) { + PowerOffset = NewPower - OrgPower; + Postive = TRUE; + } else { + PowerOffset = OrgPower - NewPower; + Postive = FALSE; + } + IDS_HDT_CONSOLE (GNB_TRACE, "Cpu New Pwr %x (%d)\n", NewPower, NewPower); + IDS_HDT_CONSOLE (GNB_TRACE, "Cpu org Pwr %x (%d)\n", OrgPower, OrgPower); + IDS_HDT_CONSOLE (GNB_TRACE, "Tdp2Watt %x, (%d)\n", ex1002.Field.ex1002_0 , ex1002.Field.ex1002_0 ); + //Ceil of (mWatt *1024 / TdpWattEncode) / 1000 = Encode in watt + PowerOffset = (((PowerOffset * 1024) / ex1002.Field.ex1002_0 ) + 500) / 1000; + + if (Postive) { + PowerOffsetEncode = (INT8) PowerOffset; + } else { + PowerOffsetEncode = 0 - (INT8) PowerOffset; + } + IDS_HDT_CONSOLE (GNB_TRACE, "PowerOffsetEncode %x\n", PowerOffsetEncode); + return (UINT8) PowerOffsetEncode; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Decode power of GPU out of Watt + * + * + * + * @param[in] Encode PwrGpu encode + * @param[in] StdHeader Standard Configuration Header + * @retval mWatt + */ +STATIC INT16 +GpuPowerDecode ( + IN UINT16 Encode, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + INT16 Power; + + Power = (INT16) Encode; + + + return Power; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Decode Max Tj + * + * + * + * @param[in] Encode Tj encode + * @retval 100 x Tj + */ +STATIC INT16 +TjMaxDecode ( + IN UINT8 Encode + ) +{ + INT16 TjMax; + + TjMax = (INT16) Encode; + + return (TjMax * 100); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * for BAPMTI_TjOffset decoding + * + * + * + * @param[in] Encode Tj encode + * @retval 100 x Tjoffset + */ +STATIC INT16 +TjOffsetDecode ( + IN UINT8 Encode + ) +{ + UINT16 Number; + UINT8 Floating; + BOOLEAN Postive; + UINT8 TjOffsetEncode; + + TjOffsetEncode = Encode; + Postive = TRUE; + + if (Encode == 0) { + return 0; + } + + if ((TjOffsetEncode & 0x80) != 0) { + Postive = FALSE; + TjOffsetEncode = (UINT8) (~(Encode - 1)); + } + + Number = ((TjOffsetEncode >> 2) & 0x1F) * 100; + + Floating = (TjOffsetEncode & 0x3); + if (Floating == 1) { + Number += 25; + } else if (Floating == 2) { + Number += 50; + } else if (Floating == 3) { + Number += 75; + } else { + } + + if (Postive) { + return (INT16) Number; + } else { + return (INT16) (0 - Number); + } + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Trinity SMU supports a software-writeable TjOffset (called swTjOffset) that can be programmed to + * account for underspec thermal solutions. + * There is a mechanism for customers to adjust TjOffset (via BAPM_PARAMETERS3.TjOffset) + * for under-performing thermal solutions. + * BIOS will adjust NomPow/MidPow/MaxPow based on this software-programmable TjOffset (called swTjOffset). + * SMU firmware will add this value to Fuse[TjOffset] for all TE's during BAPM calculations. + * + * Tj stands for junction temperature of the processor. However, here is a general description of + * our software-programmable TjOffset for BAPM (Birdirectional Application Power Management): + * "swTjOffset is an adjustable offset for BAPM thermal calculations to account for changes in + * junction temperature, TjOffset. For further details, see Thermal Guide." + * + * @param[in] StdHeader Standard configuration header + */ +STATIC VOID +GnbSoftwareTjOffsetTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D0F0xBC_x1F860_STRUCT D0F0xBC_x1F860; + D0F0xBC_x1F864_STRUCT D0F0xBC_x1F864; + ex999_STRUCT ex999 ; + D0F0xBC_x1F870_STRUCT D0F0xBC_x1F870; + ex1000_STRUCT ex1000 ; + ex1001_STRUCT ex1001 ; + + ex996_STRUCT ex996; + ex997_STRUCT ex997 ; + D0F0xBC_x1F6B4_STRUCT D0F0xBC_x1F6B4; + ex998_STRUCT ex998 ; + INT8 SwTjOffset; + INT16 Delta_T_org; + INT16 Delta_T_new; + INT32 Cpu_New_Pwr; + INT32 Gpu_New_Pwr; + + SwTjOffset = (INT8) UserOptions.CfgGnbSwTjOffset; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbSoftwareTjOffsetTN Enter\n"); + + IDS_OPTION_HOOK (IDS_GNB_PMM_SWTJOFFSET, &SwTjOffset, StdHeader); + if (SwTjOffset == 0) { + return; + } + + IDS_HDT_CONSOLE (GNB_TRACE, "User Input Tj Offset %x\n", SwTjOffset); + GnbRegisterReadTN (D0F0xBC_x1F860_TYPE, D0F0xBC_x1F860_ADDRESS, &D0F0xBC_x1F860, 0, StdHeader); + GnbRegisterReadTN (D0F0xBC_x1F864_TYPE, D0F0xBC_x1F864_ADDRESS, &D0F0xBC_x1F864, 0, StdHeader); + GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f868 , &ex999, 0, StdHeader); + GnbRegisterReadTN (D0F0xBC_x1F870_TYPE, D0F0xBC_x1F870_ADDRESS, &D0F0xBC_x1F870, 0, StdHeader); + GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f898 , &ex1000, 0, StdHeader); + GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f8c0 , &ex1001, 0, StdHeader); + + //Tjoffset_new = Tjoffset_org + SwTjOffset + //Delta_T_org = T_die - Tjoffset_org - 45 + + //Delta_T_new = T_die - Tjoffset_new - 45 + // = T_die - (Tjoffset_org + SwTjOffset) - 45 + // = T_die - Tjoffset_org - SwTjOffset - 45 + + //Pwr_new = Pwr_org * (Delta_T_new/Delta_T_org) + // = Pwr_org * (T_org - TjOffset) / T_org + + //Cpu0 + Delta_T_org = TjMaxDecode ((UINT8) D0F0xBC_x1F860.Field.BAPMTI_TjMax_0) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_0) - 4500; + Delta_T_new = TjMaxDecode ((UINT8) D0F0xBC_x1F860.Field.BAPMTI_TjMax_0) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_0) - (SwTjOffset * 100) - 4500; + IDS_HDT_CONSOLE (GNB_TRACE, "Cpu0 Delta T org %x (%d)\n", Delta_T_org, Delta_T_org); + IDS_HDT_CONSOLE (GNB_TRACE, "Cpu0 Delta T New %x (%d)\n", Delta_T_new, Delta_T_new); + Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex999.Field.ex999_3 , StdHeader) * Delta_T_new) / Delta_T_org; + ex996.Field.ex996_2 = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex999.Field.ex999_3 , StdHeader), StdHeader); + Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex999.Field.ex999_2 , StdHeader) * Delta_T_new) / Delta_T_org; + ex996.Field.ex996_3 = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex999.Field.ex999_2 , StdHeader), StdHeader); + Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex1001.Field.ex1001_2 , StdHeader) * Delta_T_new) / Delta_T_org; + ex998.Field.ex998_2 = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex1001.Field.ex1001_2 , StdHeader), StdHeader); + + //Cpu1 + Delta_T_org = TjMaxDecode ((UINT8) D0F0xBC_x1F860.Field.BAPMTI_TjMax_1) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_1) - 4500; + Delta_T_new = TjMaxDecode ((UINT8) D0F0xBC_x1F860.Field.BAPMTI_TjMax_1) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_1) - (SwTjOffset * 100) - 4500; + IDS_HDT_CONSOLE (GNB_TRACE, "Cpu1 Delta T org %x (%d)\n", Delta_T_org, Delta_T_org); + IDS_HDT_CONSOLE (GNB_TRACE, "Cpu1 Delta T New %x (%d)\n", Delta_T_new, Delta_T_new); + Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex999.Field.ex999_1 , StdHeader) * Delta_T_new) / Delta_T_org; + ex996.Field.ex996_0 = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex999.Field.ex999_1, StdHeader), StdHeader); + Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex999.Field.ex999_0 , StdHeader) * Delta_T_new) / Delta_T_org; + ex996.Field.ex996_1 = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex999.Field.ex999_0 , StdHeader), StdHeader); + Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex1001.Field.ex1001_1 , StdHeader) * Delta_T_new) / Delta_T_org; + ex998.Field.ex998_1 = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex1001.Field.ex1001_1 , StdHeader), StdHeader); + + //GPU + Delta_T_org = TjMaxDecode ((UINT8) D0F0xBC_x1F864.Field.BAPMTI_GpuTjMax) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_2) - 4500; + Delta_T_new = TjMaxDecode ((UINT8) D0F0xBC_x1F864.Field.BAPMTI_GpuTjMax) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_2) - (SwTjOffset * 100) - 4500; + IDS_HDT_CONSOLE (GNB_TRACE, "Gpu Delta T org %x (%d)\n", Delta_T_org, Delta_T_org); + IDS_HDT_CONSOLE (GNB_TRACE, "Gpu Delta T New %x (%d)\n", Delta_T_new, Delta_T_new); + Gpu_New_Pwr = (GpuPowerDecode ((UINT16) ex1000.Field.ex1000_1 , StdHeader) * Delta_T_new) / Delta_T_org; + ex997.Field.ex997_0 = (UINT16) (Gpu_New_Pwr - GpuPowerDecode ((UINT16) ex1000.Field.ex1000_1 , StdHeader)); + Gpu_New_Pwr = (GpuPowerDecode ((UINT16) ex1000.Field.ex1000_0 , StdHeader) * Delta_T_new) / Delta_T_org; + ex997.Field.ex997_1 = (UINT16) (Gpu_New_Pwr - GpuPowerDecode ((UINT16) ex1000.Field.ex1000_0 , StdHeader)); + Gpu_New_Pwr = (GpuPowerDecode ((UINT16) ex1001.Field.ex1001_0 , StdHeader) * Delta_T_new) / Delta_T_org; + ex998.Field.ex998_0 = (UINT16) (Gpu_New_Pwr - GpuPowerDecode ((UINT16) ex1001.Field.ex1001_0 , StdHeader)); + + //SwTjOffset + D0F0xBC_x1F6B4.Field.TjOffset = SwTjOffset; + + GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1f6ac , &ex996, 0, StdHeader); + GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1f6b0 , &ex997, 0, StdHeader); + GnbRegisterWriteTN (D0F0xBC_x1F6B4_TYPE, D0F0xBC_x1F6B4_ADDRESS, &D0F0xBC_x1F6B4, 0, StdHeader); + GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1F6B8 , &ex998, 0, StdHeader); + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbSoftwareTjOffsetTN Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init TDC + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +STATIC VOID +GnbInitTdc ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AMD_EARLY_PARAMS *EarlyParams; + D0F0xBC_x1F62C_STRUCT D0F0xBC_x1F62C; + D0F0xBC_x1F840_STRUCT D0F0xBC_x1F840; + + EarlyParams = (AMD_EARLY_PARAMS *) StdHeader; + D0F0xBC_x1F62C.Field.Idd = EarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit / 10; + D0F0xBC_x1F62C.Field.Iddnb = EarlyParams->PlatformConfig.VrmProperties[NbVrm].CurrentLimit / 10; + GnbRegisterWriteTN (D0F0xBC_x1F62C_TYPE, D0F0xBC_x1F62C_ADDRESS, &D0F0xBC_x1F62C, 0, StdHeader); + + D0F0xBC_x1F840.Field.IddspikeOCP = EarlyParams->PlatformConfig.VrmProperties[CoreVrm].SviOcpLevel / 10; + D0F0xBC_x1F840.Field.IddNbspikeOCP = EarlyParams->PlatformConfig.VrmProperties[NbVrm].SviOcpLevel / 10; + GnbRegisterWriteTN (D0F0xBC_x1F840_TYPE, D0F0xBC_x1F840_ADDRESS, &D0F0xBC_x1F840, 0, StdHeader); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Early Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GnbEarlyInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + GNB_HANDLE *GnbHandle; + UINT32 Property; + D0F0xBC_xE0104188_STRUCT D0F0xBC_xE0104188; + + Status = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlyInterfaceTN Enter\n"); + Property = TABLE_PROPERTY_DEAFULT; + + //Check fuse to support BAPM disabled. + GnbRegisterReadTN (D0F0xBC_xE0104188_TYPE, D0F0xBC_xE0104188_ADDRESS, &D0F0xBC_xE0104188, 0, StdHeader); + if (D0F0xBC_xE0104188.Field.BapmDisable == 0) { + Property |= GnbBuildOptions.CfgBapmSupport ? TABLE_PROPERTY_BAPM : 0; + } + + IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader); + + // SMU LHTC support init + GnbBapmLhtcInitTN (StdHeader); + + if ((Property & TABLE_PROPERTY_BAPM) == TABLE_PROPERTY_BAPM) { + GnbTjOffsetUpdateTN (StdHeader); + GnbSoftwareTjOffsetTN (StdHeader); + GnbBapmCalculateCoeffsTN (StdHeader); + GnbCacEnablement (StdHeader); + GnbBapmMeasuredTempTN (StdHeader); + } else { + // If BAPM is disabled (either through fusing or CBS option), AGESA should enable LHTC algorithm. + // Right now, LHTC is only enabled in the "DisableBAPM()" firmware routine, so unless Driver specifically calls this message, + // LHTC will never be enabled if BAPM is disabled from the start. + GnbLhtcEnableTN (StdHeader); + } + + GnbInitTdc (StdHeader); + GnbHandle = GnbGetHandle (StdHeader); + ASSERT (GnbHandle != NULL); + Status = GnbProcessTable ( + GnbHandle, + GnbEarlyInitTableTN, + Property, + 0, + StdHeader + ); + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlyInterfaceTN Exit [0x%x]\n", Status); + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Early Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GnbEarlierInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + GNB_HANDLE *GnbHandle; + D0F0xBC_xE0107060_STRUCT D0F0xBC_xE0107060; + D0F0xBC_xE0001008_STRUCT D0F0xBC_xE0001008; + Status = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlierInterfaceTN Enter\n"); + + GnbAdjustSmuVidBeforeSmuTN (StdHeader); + + GnbHandle = GnbGetHandle (StdHeader); + ASSERT (GnbHandle != NULL); + GnbRegisterReadTN (D0F0xBC_xE0107060_TYPE, D0F0xBC_xE0107060_ADDRESS, &D0F0xBC_xE0107060, 0, StdHeader); + GnbRegisterReadTN (D0F0xBC_xE0001008_TYPE, D0F0xBC_xE0001008_ADDRESS, &D0F0xBC_xE0001008, 0, StdHeader); + GfxRequestVoltageTN ((UINT8) D0F0xBC_xE0001008.Field.SClkVid1, StdHeader); + GfxRequestSclkTN ((UINT8) D0F0xBC_xE0107060.Field.SClkDpmDid1, StdHeader); + Status = GnbProcessTable ( + GnbHandle, + GnbEarlierInitTableBeforeSmuTN, + 0, + 0, + StdHeader + ); + GnbSmuFirmwareLoadV4 (GnbHandle->Address, (FIRMWARE_HEADER_V4*) &FirmwareTN[0], StdHeader); + Status = GnbProcessTable ( + GnbHandle, + GnbEarlierInitTableAfterSmuTN, + 0, + 0, + StdHeader + ); + + GnbAdjustSmuVidAfterSmuTN (StdHeader); + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlierInterfaceTN Exit [0x%x]\n", Status); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c new file mode 100644 index 0000000..f98884d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c @@ -0,0 +1,197 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbCommonLib.h" +#include "GnbTable.h" +#include "GnbPcieConfig.h" +#include "GnbNbInitLibV1.h" +#include "GnbNbInitLibV4.h" +#include "GnbFuseTableTN.h" +#include "GnbRegisterAccTN.h" +#include "GnbRegistersTN.h" +#include "heapManager.h" +#include "GnbFuseTable.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBENVINITTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern GNB_BUILD_OPTIONS GnbBuildOptions; +extern GNB_TABLE ROMDATA GnbEnvInitTableTN []; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GnbEnvInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Early Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GnbEnvInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AMD_ENV_PARAMS *EnvParamsPtr; + UINT32 Property; + GNB_HANDLE *GnbHandle; + D18F5x170_STRUCT D18F5x170; + D0F0xBC_x1F8DC_STRUCT D0F0xBC_x1F8DC; + PP_FUSE_ARRAY *PpFuseArray; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnvInterfaceTN Enter\n"); + Property = TABLE_PROPERTY_DEAFULT; + EnvParamsPtr = (AMD_ENV_PARAMS *) StdHeader; + GnbHandle = GnbGetHandle (StdHeader); + ASSERT (GnbHandle != NULL); + GnbLoadFuseTableTN (StdHeader); + Status = GnbSetTom (GnbGetHostPciAddress (GnbHandle), StdHeader); + GnbOrbDynamicWake (GnbGetHostPciAddress (GnbHandle), StdHeader); + GnbClumpUnitIdV4 (GnbHandle, StdHeader); + GnbLpcDmaDeadlockPreventionV4 (GnbHandle, StdHeader); + Property |= GnbBuildOptions.CfgLoadlineEnable ? TABLE_PROPERTY_LOADLINE_ENABLE : 0; + Property |= GnbBuildOptions.CfgIommuL1ClockGatingEnable ? TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING : 0; + Property |= GnbBuildOptions.CfgIommuL2ClockGatingEnable ? TABLE_PROPERTY_IOMMU_L2_CLOCK_GATING : 0; + if (!EnvParamsPtr->GnbEnvConfiguration.IommuSupport) { + Property |= TABLE_PROPERTY_IOMMU_DISABLED; + } + + if (GnbBuildOptions.CfgNbdpmEnable) { + GnbRegisterReadTN ( + TYPE_D18F5, + D18F5x170_ADDRESS, + &D18F5x170.Value, + 0, + StdHeader + ); + // Check if NbPstate enbale + if ((D18F5x170.Field.SwNbPstateLoDis != 1) && (D18F5x170.Field.NbPstateMaxVal != 0)) { + Property |= TABLE_PROPERTY_NBDPM; + PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); + if (PpFuseArray != NULL) { + // NBDPM is requesting SclkVid0 from the register. + // Write them back if SclkVid has been changed in PpFuseArray. + GnbRegisterReadTN (D0F0xBC_x1F8DC_TYPE, D0F0xBC_x1F8DC_ADDRESS, &D0F0xBC_x1F8DC.Value, 0, StdHeader); + if ((D0F0xBC_x1F8DC.Field.SClkVid0 != PpFuseArray->SclkVid[0]) || + (D0F0xBC_x1F8DC.Field.SClkVid1 != PpFuseArray->SclkVid[1]) || + (D0F0xBC_x1F8DC.Field.SClkVid2 != PpFuseArray->SclkVid[2]) || + (D0F0xBC_x1F8DC.Field.SClkVid3 != PpFuseArray->SclkVid[3])) { + D0F0xBC_x1F8DC.Field.SClkVid0 = PpFuseArray->SclkVid[0]; + D0F0xBC_x1F8DC.Field.SClkVid1 = PpFuseArray->SclkVid[1]; + D0F0xBC_x1F8DC.Field.SClkVid2 = PpFuseArray->SclkVid[2]; + D0F0xBC_x1F8DC.Field.SClkVid3 = PpFuseArray->SclkVid[3]; + GnbRegisterWriteTN (D0F0xBC_x1F8DC_TYPE, D0F0xBC_x1F8DC_ADDRESS, &D0F0xBC_x1F8DC.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + } + } + } + } + + IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader); + + Status = GnbProcessTable ( + GnbHandle, + GnbEnvInitTableTN, + Property, + GNB_TABLE_FLAGS_FORCE_S3_SAVE, + StdHeader + ); + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnvInterfaceTN Exit [0x%x]\n", Status); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c new file mode 100644 index 0000000..c2bb882 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c @@ -0,0 +1,1000 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Gnb fuse table + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbGfxFamServices.h" +#include "GnbCommonLib.h" +#include "GnbFuseTable.h" +#include "GnbFuseTableTN.h" +#include "GnbRegistersTN.h" +#include "GnbRegisterAccTN.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBFUSETABLETN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +GnbFuseTableDebugDumpTN ( + IN PP_FUSE_ARRAY *PpFuseArray, + IN AMD_CONFIG_PARAMS *StdHeader + ); + + + +PP_FUSE_ARRAY ex907 = { + 0, // PP table revision + {1, 0, 0, 0, 0, 0}, // Valid DPM states + {0x40, 0, 0, 0, 0, 0}, // Sclk DPM DID + {0, 0, 0, 0, 0, 0}, // Sclk DPM VID + {0, 0, 0, 0, 0}, // Sclk DPM Cac + {1, 0, 0, 0, 0, 0}, // State policy flags + {2, 0, 0, 0, 0, 0}, // State policy label + {0x40, 0, 0, 0}, // VCLK DID + {0x40, 0, 0, 0}, // DCLK DID + 8, // Thermal SCLK + {0, 0, 0, 0, 0, 0}, // Vclk/Dclk selector + {0, 0, 0, 0}, // Valid Lclk DPM states + {0x40, 0x40, 0x40, 0}, // Lclk DPM DID + {0x40, 0x40, 0x40, 0}, // Lclk DPM VID + {0, 0, 0, 0}, // Displclk DID + 3, // Pcie Gen 2 VID + 0x10, // Main PLL id for 3200 VCO + 0, // WRCK SMU clock Divisor + {0x24, 0x24, 0x24, 0x24}, // SCLK VID + 0, // GPU boost cap + {0, 0, 0, 0, 0, 0}, // Sclk DPM TDP limit + 0, // TDP limit PG + 0, // Boost margin + 0, // Throttle margin + TRUE, // Support VCE in PP table + {0x3, 0xC, 0x30, 0xC0}, // VCE Flags + {0, 1, 0, 1}, // MCLK for VCE + {0, 0, 0, 0}, // SCLK selector for VCE + {0x40, 0x40, 0x40, 0x40} // Eclk DID +}; + + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0104158_TABLE [] = { + { + D0F0xBC_xE0104158_EClkDid0_OFFSET, + D0F0xBC_xE0104158_EClkDid0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, EclkDid[0]) + }, + { + D0F0xBC_xE0104158_EClkDid1_OFFSET, + D0F0xBC_xE0104158_EClkDid1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, EclkDid[1]) + }, + { + D0F0xBC_xE0104158_EClkDid2_OFFSET, + D0F0xBC_xE0104158_EClkDid2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, EclkDid[2]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010415B_TABLE [] = { + { + D0F0xBC_xE010415B_EClkDid3_OFFSET, + D0F0xBC_xE010415B_EClkDid3_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, EclkDid[3]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0104184_TABLE [] = { + { + D0F0xBC_xE0104184_VCEFlag0_OFFSET, + D0F0xBC_xE0104184_VCEFlag0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VceFlags[0]) + }, + { + D0F0xBC_xE0104184_VCEFlag1_OFFSET, + D0F0xBC_xE0104184_VCEFlag1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VceFlags[1]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0104187_TABLE [] = { + { + D0F0xBC_xE0104187_VCEFlag2_OFFSET, + D0F0xBC_xE0104187_VCEFlag2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VceFlags[2]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0104188_TABLE [] = { + { + D0F0xBC_xE0104188_VCEFlag3_OFFSET, + D0F0xBC_xE0104188_VCEFlag3_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VceFlags[3]) + }, + { + D0F0xBC_xE0104188_ReqSclkSel0_OFFSET, + D0F0xBC_xE0104188_ReqSclkSel0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VceReqSclkSel[0]) + }, + { + D0F0xBC_xE0104188_ReqSclkSel1_OFFSET, + D0F0xBC_xE0104188_ReqSclkSel1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VceReqSclkSel[1]) + }, + { + D0F0xBC_xE0104188_ReqSclkSel2_OFFSET, + D0F0xBC_xE0104188_ReqSclkSel2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VceReqSclkSel[2]) + }, + { + D0F0xBC_xE0104188_ReqSclkSel3_OFFSET, + D0F0xBC_xE0104188_ReqSclkSel3_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VceReqSclkSel[3]) + }, + { + D0F0xBC_xE0104188_VCEMclk_OFFSET + 0, + 1, + (UINT16) offsetof (PP_FUSE_ARRAY, VceMclk[0]) + }, + { + D0F0xBC_xE0104188_VCEMclk_OFFSET + 1, + 1, + (UINT16) offsetof (PP_FUSE_ARRAY, VceMclk[1]) + }, + { + D0F0xBC_xE0104188_VCEMclk_OFFSET + 2, + 1, + (UINT16) offsetof (PP_FUSE_ARRAY, VceMclk[2]) + }, + { + D0F0xBC_xE0104188_VCEMclk_OFFSET + 3, + 1, + (UINT16) offsetof (PP_FUSE_ARRAY, VceMclk[3]) + }, +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0106020_TABLE [] = { + { + D0F0xBC_xE0106020_PowerplayDClkVClkSel0_OFFSET, + D0F0xBC_xE0106020_PowerplayDClkVClkSel0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[0]) + }, + { + D0F0xBC_xE0106020_PowerplayDClkVClkSel1_OFFSET, + D0F0xBC_xE0106020_PowerplayDClkVClkSel1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[1]) + }, + { + D0F0xBC_xE0106020_PowerplayDClkVClkSel2_OFFSET, + D0F0xBC_xE0106020_PowerplayDClkVClkSel2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[2]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0106023_TABLE [] = { + { + D0F0xBC_xE0106023_PowerplayDClkVClkSel3_OFFSET, + D0F0xBC_xE0106023_PowerplayDClkVClkSel3_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[3]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0106024_TABLE [] = { + { + D0F0xBC_xE0106024_PowerplayDClkVClkSel4_OFFSET, + D0F0xBC_xE0106024_PowerplayDClkVClkSel4_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[4]) + }, + { + D0F0xBC_xE0106024_PowerplayDClkVClkSel5_OFFSET, + D0F0xBC_xE0106024_PowerplayDClkVClkSel5_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[5]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010705C_TABLE [] = { + { + D0F0xBC_xE010705C_PowerplayTableRev_OFFSET, + D0F0xBC_xE010705C_PowerplayTableRev_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, PPlayTableRev) + }, + { + D0F0xBC_xE010705C_SClkThermDid_OFFSET, + D0F0xBC_xE010705C_SClkThermDid_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkThermDid) + }, + { + D0F0xBC_xE010705C_PcieGen2Vid_OFFSET, + D0F0xBC_xE010705C_PcieGen2Vid_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, PcieGen2Vid) + } +}; +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010705F_TABLE [] = { + { + D0F0xBC_xE010705F_SClkDpmVid0_OFFSET, + D0F0xBC_xE010705F_SClkDpmVid0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[0]) + }, + { + D0F0xBC_xE010705F_SClkDpmVid0_OFFSET, + D0F0xBC_xE010705F_SClkDpmVid0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmVid[0]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107060_TABLE [] = { + { + D0F0xBC_xE0107060_SClkDpmVid1_OFFSET, + D0F0xBC_xE0107060_SClkDpmVid1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[1]) + }, + { + D0F0xBC_xE0107060_SClkDpmVid1_OFFSET, + D0F0xBC_xE0107060_SClkDpmVid1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmVid[1]) + }, + { + D0F0xBC_xE0107060_SClkDpmVid2_OFFSET, + D0F0xBC_xE0107060_SClkDpmVid2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[2]) + }, + { + D0F0xBC_xE0107060_SClkDpmVid2_OFFSET, + D0F0xBC_xE0107060_SClkDpmVid2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmVid[2]) + }, + { + D0F0xBC_xE0107060_SClkDpmVid3_OFFSET, + D0F0xBC_xE0107060_SClkDpmVid3_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[3]) + }, + { + D0F0xBC_xE0107060_SClkDpmVid4_OFFSET, + D0F0xBC_xE0107060_SClkDpmVid4_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[4]) + }, + { + D0F0xBC_xE0107060_SClkDpmDid0_OFFSET, + D0F0xBC_xE0107060_SClkDpmDid0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[0]) + }, + { + D0F0xBC_xE0107060_SClkDpmDid1_OFFSET, + D0F0xBC_xE0107060_SClkDpmDid1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[1]) + }, + { + D0F0xBC_xE0107060_SClkDpmDid2_OFFSET, + D0F0xBC_xE0107060_SClkDpmDid2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[2]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107063_TABLE [] = { + { + D0F0xBC_xE0107063_SClkDpmDid3_OFFSET, + D0F0xBC_xE0107063_SClkDpmDid3_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[3]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107064_TABLE [] = { + { + D0F0xBC_xE0107064_SClkDpmDid4_OFFSET, + D0F0xBC_xE0107064_SClkDpmDid4_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[4]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107067_TABLE [] = { + { + D0F0xBC_xE0107067_DispClkDid0_OFFSET, + D0F0xBC_xE0107067_DispClkDid0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, DisplclkDid[0]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107068_TABLE [] = { + { + D0F0xBC_xE0107068_DispClkDid1_OFFSET, + D0F0xBC_xE0107068_DispClkDid1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, DisplclkDid[1]) + }, + { + D0F0xBC_xE0107068_DispClkDid2_OFFSET, + D0F0xBC_xE0107068_DispClkDid2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, DisplclkDid[2]) + }, + { + D0F0xBC_xE0107068_DispClkDid3_OFFSET, + D0F0xBC_xE0107068_DispClkDid3_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, DisplclkDid[3]) + }, + { + D0F0xBC_xE0107068_LClkDpmDid0_OFFSET, + D0F0xBC_xE0107068_LClkDpmDid0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmDid[0]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010706B_TABLE [] = { + { + D0F0xBC_xE010706B_LClkDpmDid1_OFFSET, + D0F0xBC_xE010706B_LClkDpmDid1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmDid[1]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010706C_TABLE [] = { + { + D0F0xBC_xE010706C_LClkDpmDid2_OFFSET, + D0F0xBC_xE010706C_LClkDpmDid2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmDid[2]) + }, + { + D0F0xBC_xE010706C_LClkDpmDid3_OFFSET, + D0F0xBC_xE010706C_LClkDpmDid3_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmDid[3]) + }, + { + D0F0xBC_xE010706C_LClkDpmValid_OFFSET + 0, + 1, + (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmValid[0]) + }, + { + D0F0xBC_xE010706C_LClkDpmValid_OFFSET + 1, + 1, + (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmValid[1]) + }, + { + D0F0xBC_xE010706C_LClkDpmValid_OFFSET + 2, + 1, + (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmValid[2]) + }, + { + D0F0xBC_xE010706C_LClkDpmValid_OFFSET + 3, + 1, + (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmValid[3]) + }, + { + D0F0xBC_xE010706C_DClkDid0_OFFSET, + D0F0xBC_xE010706C_DClkDid0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, DclkDid[0]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010706F_TABLE [] = { + { + D0F0xBC_xE010706F_DClkDid1_OFFSET, + D0F0xBC_xE010706F_DClkDid1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, DclkDid[1]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107070_TABLE [] = { + { + D0F0xBC_xE0107070_DClkDid2_OFFSET, + D0F0xBC_xE0107070_DClkDid2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, DclkDid[2]) + }, + { + D0F0xBC_xE0107070_DClkDid3_OFFSET, + D0F0xBC_xE0107070_DClkDid3_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, DclkDid[3]) + }, + { + D0F0xBC_xE0107070_VClkDid0_OFFSET, + D0F0xBC_xE0107070_VClkDid0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VclkDid[0]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107073_TABLE [] = { + { + D0F0xBC_xE0107073_VClkDid1_OFFSET, + D0F0xBC_xE0107073_VClkDid1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VclkDid[1]) + }, +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107074_TABLE [] = { + { + D0F0xBC_xE0107074_VClkDid2_OFFSET, + D0F0xBC_xE0107074_VClkDid2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VclkDid[2]) + }, + { + D0F0xBC_xE0107074_VClkDid3_OFFSET, + D0F0xBC_xE0107074_VClkDid3_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, VclkDid[3]) + }, + { + D0F0xBC_xE0107074_PowerplaySclkDpmValid0_OFFSET, + D0F0xBC_xE0107074_PowerplaySclkDpmValid0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[0]) + }, + { + D0F0xBC_xE0107074_PowerplaySclkDpmValid1_OFFSET, + D0F0xBC_xE0107074_PowerplaySclkDpmValid1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[1]) + }, + { + D0F0xBC_xE0107074_PowerplaySclkDpmValid2_OFFSET, + D0F0xBC_xE0107074_PowerplaySclkDpmValid2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[2]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107077_TABLE [] = { + { + D0F0xBC_xE0107077_PowerplaySclkDpmValid3_OFFSET, + D0F0xBC_xE0107077_PowerplaySclkDpmValid3_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[3]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107078_TABLE [] = { + { + D0F0xBC_xE0107078_PowerplaySclkDpmValid4_OFFSET, + D0F0xBC_xE0107078_PowerplaySclkDpmValid4_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[4]) + }, + { + D0F0xBC_xE0107078_PowerplaySclkDpmValid5_OFFSET, + D0F0xBC_xE0107078_PowerplaySclkDpmValid5_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[5]) + }, + { + D0F0xBC_xE0107078_PowerplayPolicyLabel0_OFFSET, + D0F0xBC_xE0107078_PowerplayPolicyLabel0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[0]) + }, + { + D0F0xBC_xE0107078_PowerplayPolicyLabel1_OFFSET, + D0F0xBC_xE0107078_PowerplayPolicyLabel1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[1]) + }, + { + D0F0xBC_xE0107078_PowerplayPolicyLabel2_OFFSET, + D0F0xBC_xE0107078_PowerplayPolicyLabel2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[2]) + }, + { + D0F0xBC_xE0107078_PowerplayPolicyLabel3_OFFSET, + D0F0xBC_xE0107078_PowerplayPolicyLabel3_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[3]) + }, + { + D0F0xBC_xE0107078_PowerplayPolicyLabel4_OFFSET, + D0F0xBC_xE0107078_PowerplayPolicyLabel4_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[4]) + }, + { + D0F0xBC_xE0107078_PowerplayPolicyLabel5_OFFSET, + D0F0xBC_xE0107078_PowerplayPolicyLabel5_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[5]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010707B_TABLE [] = { + { + D0F0xBC_xE010707B_PowerplayStateFlag0_OFFSET, + D0F0xBC_xE010707B_PowerplayStateFlag0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[0]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010707C_TABLE [] = { + { + D0F0xBC_xE010707C_PowerplayStateFlag1_OFFSET, + D0F0xBC_xE010707C_PowerplayStateFlag1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[1]) + }, + { + D0F0xBC_xE010707C_PowerplayStateFlag2_OFFSET, + D0F0xBC_xE010707C_PowerplayStateFlag2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[2]) + }, + { + D0F0xBC_xE010707C_PowerplayStateFlag3_OFFSET, + D0F0xBC_xE010707C_PowerplayStateFlag3_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[3]) + }, + { + D0F0xBC_xE010707C_PowerplayStateFlag4_OFFSET, + D0F0xBC_xE010707C_PowerplayStateFlag4_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[4]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010707F_TABLE [] = { + { + D0F0xBC_xE010707F_PowerplayStateFlag5_OFFSET, + D0F0xBC_xE010707F_PowerplayStateFlag5_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[5]) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xFF000000_TABLE [] = { + { + D0F0xBC_xFF000000_MainPllOpFreqIdStartup_OFFSET, + D0F0xBC_xFF000000_MainPllOpFreqIdStartup_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, MainPllId) + } +}; + +FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0001008_TABLE [] = { + { + D0F0xBC_xE0001008_SClkVid0_OFFSET, + D0F0xBC_xE0001008_SClkVid0_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkVid[0]) + }, + { + D0F0xBC_xE0001008_SClkVid1_OFFSET, + D0F0xBC_xE0001008_SClkVid1_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkVid[1]) + }, + { + D0F0xBC_xE0001008_SClkVid2_OFFSET, + D0F0xBC_xE0001008_SClkVid2_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkVid[2]) + }, + { + D0F0xBC_xE0001008_SClkVid3_OFFSET, + D0F0xBC_xE0001008_SClkVid3_WIDTH, + (UINT16) offsetof (PP_FUSE_ARRAY, SclkVid[3]) + } +}; + + +FUSE_TABLE_ENTRY_TN FuseRegisterTableTN [] = { + { + D0F0xBC_xE0104158_TYPE, + D0F0xBC_xE0104158_ADDRESS, + sizeof (D0F0xBC_xE0104158_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0104158_TABLE + }, + { + D0F0xBC_xE010415B_TYPE, + D0F0xBC_xE010415B_ADDRESS, + sizeof (D0F0xBC_xE010415B_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE010415B_TABLE + }, + { + D0F0xBC_xE0104184_TYPE, + D0F0xBC_xE0104184_ADDRESS, + sizeof (D0F0xBC_xE0104184_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0104184_TABLE + }, + { + D0F0xBC_xE0104187_TYPE, + D0F0xBC_xE0104187_ADDRESS, + sizeof (D0F0xBC_xE0104187_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0104187_TABLE + }, + { + D0F0xBC_xE0104188_TYPE, + D0F0xBC_xE0104188_ADDRESS, + sizeof (D0F0xBC_xE0104188_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0104188_TABLE + }, + { + D0F0xBC_xE0106020_TYPE, + D0F0xBC_xE0106020_ADDRESS, + sizeof (D0F0xBC_xE0106020_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0106020_TABLE + }, + { + D0F0xBC_xE0106023_TYPE, + D0F0xBC_xE0106023_ADDRESS, + sizeof (D0F0xBC_xE0106023_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0106023_TABLE + }, + { + D0F0xBC_xE0106024_TYPE, + D0F0xBC_xE0106024_ADDRESS, + sizeof (D0F0xBC_xE0106024_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0106024_TABLE + }, + { + D0F0xBC_xE010705C_TYPE, + D0F0xBC_xE010705C_ADDRESS, + sizeof (D0F0xBC_xE010705C_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE010705C_TABLE + }, + { + D0F0xBC_xE010705F_TYPE, + D0F0xBC_xE010705F_ADDRESS, + sizeof (D0F0xBC_xE010705F_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE010705F_TABLE + }, + { + D0F0xBC_xE0107060_TYPE, + D0F0xBC_xE0107060_ADDRESS, + sizeof (D0F0xBC_xE0107060_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0107060_TABLE + }, + { + D0F0xBC_xE0107063_TYPE, + D0F0xBC_xE0107063_ADDRESS, + sizeof (D0F0xBC_xE0107063_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0107063_TABLE + }, + { + D0F0xBC_xE0107064_TYPE, + D0F0xBC_xE0107064_ADDRESS, + sizeof (D0F0xBC_xE0107064_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0107064_TABLE + }, + { + D0F0xBC_xE0107067_TYPE, + D0F0xBC_xE0107067_ADDRESS, + sizeof (D0F0xBC_xE0107067_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0107067_TABLE + }, + { + D0F0xBC_xE0107068_TYPE, + D0F0xBC_xE0107068_ADDRESS, + sizeof (D0F0xBC_xE0107068_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0107068_TABLE + }, + { + D0F0xBC_xE010706B_TYPE, + D0F0xBC_xE010706B_ADDRESS, + sizeof (D0F0xBC_xE010706B_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE010706B_TABLE + }, + { + D0F0xBC_xE010706C_TYPE, + D0F0xBC_xE010706C_ADDRESS, + sizeof (D0F0xBC_xE010706C_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE010706C_TABLE + }, + { + D0F0xBC_xE010706F_TYPE, + D0F0xBC_xE010706F_ADDRESS, + sizeof (D0F0xBC_xE010706F_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE010706F_TABLE + }, + { + D0F0xBC_xE0107070_TYPE, + D0F0xBC_xE0107070_ADDRESS, + sizeof (D0F0xBC_xE0107070_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0107070_TABLE + }, + { + D0F0xBC_xE0107073_TYPE, + D0F0xBC_xE0107073_ADDRESS, + sizeof (D0F0xBC_xE0107073_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0107073_TABLE + }, + { + D0F0xBC_xE0107074_TYPE, + D0F0xBC_xE0107074_ADDRESS, + sizeof (D0F0xBC_xE0107074_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0107074_TABLE + }, + { + D0F0xBC_xE0107077_TYPE, + D0F0xBC_xE0107077_ADDRESS, + sizeof (D0F0xBC_xE0107077_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0107077_TABLE + }, + { + D0F0xBC_xE0107078_TYPE, + D0F0xBC_xE0107078_ADDRESS, + sizeof (D0F0xBC_xE0107078_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0107078_TABLE + }, + { + D0F0xBC_xE010707B_TYPE, + D0F0xBC_xE010707B_ADDRESS, + sizeof (D0F0xBC_xE010707B_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE010707B_TABLE + }, + { + D0F0xBC_xE010707C_TYPE, + D0F0xBC_xE010707C_ADDRESS, + sizeof (D0F0xBC_xE010707C_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE010707C_TABLE + }, + { + D0F0xBC_xE010707F_TYPE, + D0F0xBC_xE010707F_ADDRESS, + sizeof (D0F0xBC_xE010707F_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE010707F_TABLE + }, + { + D0F0xBC_xFF000000_TYPE, + D0F0xBC_xFF000000_ADDRESS, + sizeof (D0F0xBC_xFF000000_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xFF000000_TABLE + }, + { + D0F0xBC_xE0001008_TYPE, + D0F0xBC_xE0001008_ADDRESS, + sizeof (D0F0xBC_xE0001008_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN), + D0F0xBC_xE0001008_TABLE + } +}; + +FUSE_TABLE_TN FuseTableTN = { + sizeof (FuseRegisterTableTN) / sizeof (FUSE_TABLE_ENTRY_TN), + FuseRegisterTableTN +}; + +/*----------------------------------------------------------------------------------------*/ +/** + * Load Fuse Table TN + * + * + * @param[out] PpFuseArray Pointer to save fuse table + * @param[in] StdHeader Pointer to Standard configuration + * @retval AGESA_STATUS + */ + +STATIC VOID +NbFuseLoadFuseTableTN ( + OUT PP_FUSE_ARRAY *PpFuseArray, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + FUSE_TABLE_TN *FuseTable; + UINTN RegisterIndex; + FuseTable = &FuseTableTN; + for (RegisterIndex = 0; RegisterIndex < FuseTable->FuseTableLength; RegisterIndex++ ) { + UINTN FieldIndex; + UINTN FuseRegisterTableLength; + UINT32 FuseValue; + FuseRegisterTableLength = FuseTable->FuseTable[RegisterIndex].FuseRegisterTableLength; + + GnbRegisterReadTN ( + FuseTable->FuseTable[RegisterIndex].RegisterSpaceType, + FuseTable->FuseTable[RegisterIndex].Register, + &FuseValue, + 0, + StdHeader + ); + for (FieldIndex = 0; FieldIndex < FuseRegisterTableLength; FieldIndex++) { + FUSE_REGISTER_ENTRY_TN RegisterEntry; + RegisterEntry = FuseTable->FuseTable[RegisterIndex].FuseRegisterTable[FieldIndex]; + *((UINT8 *) PpFuseArray + RegisterEntry.FuseOffset) = (UINT8) ((FuseValue >> RegisterEntry.FieldOffset) & + ((1 << RegisterEntry.FieldWidth) - 1)); + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Gnb load fuse table + * + * + * + * @param[in] StdHeader Pointer to Standard configuration + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GnbLoadFuseTableTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PP_FUSE_ARRAY *PpFuseArray; + AGESA_STATUS Status; + D18F3xA0_STRUCT D18F3xA0; + + Status = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbLoadFuseTableTN Enter\n"); + + PpFuseArray = (PP_FUSE_ARRAY *) GnbAllocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, sizeof (PP_FUSE_ARRAY), StdHeader); + ASSERT (PpFuseArray != NULL); + if (PpFuseArray != NULL) { + //Support for real fuste table + GnbRegisterReadTN (D18F3xA0_TYPE, D18F3xA0_ADDRESS, &D18F3xA0.Value, 0, StdHeader); + if ((D18F3xA0.Field.CofVidProg) && (GnbBuildOptions.GnbLoadRealFuseTable)) { + NbFuseLoadFuseTableTN (PpFuseArray, StdHeader); + PpFuseArray->VceSateTableSupport = TRUE; + IDS_HDT_CONSOLE (NB_MISC, " Processor Fused\n"); + } else { + LibAmdMemCopy (PpFuseArray, &ex907 , sizeof (PP_FUSE_ARRAY), StdHeader); + IDS_HDT_CONSOLE (NB_MISC, " Processor Unfuse\n"); + } + } else { + Status = AGESA_ERROR; + } + IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PPFUSE_OVERRIDE, PpFuseArray, StdHeader); + GnbFuseTableDebugDumpTN (PpFuseArray, StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, "GnbLoadFuseTableTN Exit [0x%x]\n", Status); + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Debug dump fuse table + * + * + * @param[out] PpFuseArray Pointer to save fuse table + * @param[in] StdHeader Pointer to Standard configuration + */ + +VOID +GnbFuseTableDebugDumpTN ( + IN PP_FUSE_ARRAY *PpFuseArray, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINTN Index; + + IDS_HDT_CONSOLE (NB_MISC, "<------------ GNB FUSE TABLE------------>\n"); + for (Index = 0; Index < 4; Index++) { + if (PpFuseArray->LclkDpmValid[Index] != 0) { + IDS_HDT_CONSOLE ( + NB_MISC, + " LCLK DID[%d] - 0x%02x (%dMHz)\n", + Index, + PpFuseArray->LclkDpmDid[Index], + (PpFuseArray->LclkDpmDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->LclkDpmDid[Index], StdHeader) / 100) : 0 + ); + IDS_HDT_CONSOLE (NB_MISC, " LCLK VID[%d] - 0x02%x\n", Index, PpFuseArray->LclkDpmVid[Index]); + } + } + for (Index = 0; Index < 4; Index++) { + IDS_HDT_CONSOLE ( + NB_MISC, + " VCLK DID[%d] - 0x%02x (%dMHz)\n", + Index, + PpFuseArray->VclkDid[Index], + (PpFuseArray->VclkDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->VclkDid[Index], StdHeader) / 100) : 0 + ); + IDS_HDT_CONSOLE ( + NB_MISC, + " DCLK DID[%d] - 0x%02x (%dMHz)\n", + Index, + PpFuseArray->DclkDid[Index], + (PpFuseArray->DclkDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->DclkDid[Index], StdHeader) / 100) : 0 + ); + } + for (Index = 0; Index < 4; Index++) { + IDS_HDT_CONSOLE ( + NB_MISC, + " DISPCLK DID[%d] - 0x%02x (%dMHz)\n", + Index, + PpFuseArray->DisplclkDid[Index], + (PpFuseArray->DisplclkDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->DisplclkDid[Index], StdHeader) / 100) : 0 + ); + } + for (Index = 0; Index < 4; Index++) { + IDS_HDT_CONSOLE ( + NB_MISC, + " ECLK DID[%d] - 0x%02x (%dMHz)\n", + Index, + PpFuseArray->EclkDid[Index], + (PpFuseArray->EclkDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->EclkDid[Index], StdHeader) / 100) : 0 + ); + IDS_HDT_CONSOLE ( + NB_MISC, + " VCE SCLK DID[%d] - 0x%02x (%dMHz)\n", + Index, + PpFuseArray->SclkDpmDid[PpFuseArray->VceReqSclkSel[Index]], + (PpFuseArray->SclkDpmDid[PpFuseArray->VceReqSclkSel[Index]] != 0) ? (GfxFmCalculateClock (PpFuseArray->SclkDpmDid[PpFuseArray->VceReqSclkSel[Index]], StdHeader) / 100) : 0 + ); + IDS_HDT_CONSOLE ( + NB_MISC, + " VCE Flags[ % d] - 0x % 02x\n", + Index, + PpFuseArray->VceFlags[Index] + ); + } + for (Index = 0; Index < 6; Index++) { + IDS_HDT_CONSOLE ( + NB_MISC, + " SCLK DID[%d] - 0x%02x (%dMHz)\n", + Index, + PpFuseArray->SclkDpmDid[Index], + (PpFuseArray->SclkDpmDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->SclkDpmDid[Index], StdHeader) / 100) : 0 + ); + IDS_HDT_CONSOLE ( + NB_MISC, + " SCLK TDP[%d] - 0x%x \n", + Index, + PpFuseArray->SclkDpmTdpLimit[Index] + ); + IDS_HDT_CONSOLE (NB_MISC, " SCLK VID[%d] - 0x%02x\n", Index, PpFuseArray->SclkDpmVid[Index]); + } + for (Index = 0; Index < 6; Index++) { + IDS_HDT_CONSOLE (NB_MISC, " State #%d\n", Index); + } + IDS_HDT_CONSOLE (NB_MISC, "<------------ GNB FUSE END-------------->\n"); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.h new file mode 100644 index 0000000..5d6177f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.h @@ -0,0 +1,105 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Fuse table initialization + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBFUSETABLETN_H_ +#define _GNBFUSETABLETN_H_ + +#pragma pack (push, 1) + +/// Fuse field entry +typedef struct { + UINT8 FieldOffset; ///< Field offset in fuse register + UINT8 FieldWidth; ///< Width of field + UINT16 FuseOffset; ///< destination offset in translation table +} FUSE_REGISTER_ENTRY_TN; + +/// Fuse register entry +typedef struct { + UINT8 RegisterSpaceType; ///< Register type + UINT32 Register; ///< FCR register address + UINT8 FuseRegisterTableLength; ///< Length of field table for this register + FUSE_REGISTER_ENTRY_TN *FuseRegisterTable; ///< Pointer to field table +} FUSE_TABLE_ENTRY_TN; + +/// Fuse translation table +typedef struct { + UINT8 FuseTableLength; ///< Length of translation table + FUSE_TABLE_ENTRY_TN *FuseTable; ///< Pointer to register table +} FUSE_TABLE_TN; + +#pragma pack (pop) + +AGESA_STATUS +GnbLoadFuseTableTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTN.h new file mode 100644 index 0000000..76196f1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTN.h @@ -0,0 +1,78 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Various TN definitions + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBINITTN_H_ +#define _GNBINITTN_H_ + +#define D0F0xBC_x1F468_TimerPeriod_Value 100000 +#define D0F0xBC_x1F46C_BapmPeriod_Value 1 + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h new file mode 100644 index 0000000..e6ac431 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h @@ -0,0 +1,200 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Tn service installation file + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _GNB_INIT_TN_INSTALL_H_ +#define _GNB_INIT_TN_INSTALL_H_ + +//----------------------------------------------------------------------- +// Specify definition used by module services +//----------------------------------------------------------------------- + +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbFamServices.h" + +//----------------------------------------------------------------------- +// Export services +//----------------------------------------------------------------------- + +#if (AGESA_ENTRY_INIT_EARLY == TRUE) + extern F_PCIEFMGETCOMPLEXDATALENGTH PcieGetComplexDataLengthTN; + extern F_PCIEFMBUILDCOMPLEXCONFIGURATION PcieBuildComplexConfigurationTN; + extern F_PCIEFMCONFIGUREENGINESLANEALLOCATION PcieConfigureEnginesLaneAllocationTN; + extern F_PCIEFMCHECKPORTPCIDEVICEMAPPING PcieCheckPortPciDeviceMappingTN; + extern F_PCIEFMMAPPORTPCIADDRESS PcieMapPortPciAddressTN; + extern F_PCIEFMCHECKPORTPCIELANECANBEMUXED PcieCheckPortPcieLaneCanBeMuxedTN; + extern F_PCIEFMGETSBCONFIGINFO PcieGetSbConfigInfoTN; + PCIe_FAM_CONFIG_SERVICES GnbPcieConfigProtocolTN = { + PcieGetComplexDataLengthTN, + PcieBuildComplexConfigurationTN, + PcieConfigureEnginesLaneAllocationTN, + PcieCheckPortPciDeviceMappingTN, + PcieMapPortPciAddressTN, + PcieCheckPortPcieLaneCanBeMuxedTN, + PcieGetSbConfigInfoTN + }; + + GNB_SERVICE GnbPcieCongigServicesTN = { + GnbPcieFamConfigService, + AMD_FAMILY_TN, + &GnbPcieConfigProtocolTN, + SERVICES_POINTER + }; + #undef SERVICES_POINTER + #define SERVICES_POINTER &GnbPcieCongigServicesTN +#endif + +#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) + extern F_PCIEFMGETCORECONFIGURATIONVALUE PcieGetCoreConfigurationValueTN; + extern F_PCIEFMGETLINKSPEEDCAP PcieGetLinkSpeedCapTN; + extern F_PCIEFMGETNATIVEPHYLANEBITMAP PcieGetNativePhyLaneBitmapTN; + extern F_PCIEFMSETLINKSPEEDCAP PcieSetLinkSpeedCapV4; + + PCIe_FAM_INIT_SERVICES GnbPcieInitProtocolTN = { + PcieGetCoreConfigurationValueTN, + PcieGetLinkSpeedCapTN, + PcieGetNativePhyLaneBitmapTN, + PcieSetLinkSpeedCapV4 + }; + + GNB_SERVICE GnbPcieInitServicesTN = { + GnbPcieFamInitService, + AMD_FAMILY_TN, + &GnbPcieInitProtocolTN, + SERVICES_POINTER + }; + #undef SERVICES_POINTER + #define SERVICES_POINTER &GnbPcieInitServicesTN +#endif + +#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) + #if IDSOPT_IDS_ENABLED == TRUE + #if IDSOPT_TRACING_ENABLED == TRUE + extern F_PCIEFMDEBUGGETHOSTREGADDRESSSPACESTRING PcieDebugGetHostRegAddressSpaceStringTN; + extern F_PCIEFMDEBUGGETWRAPPERNAMESTRING PcieDebugGetWrapperNameStringTN; + extern F_PCIEFMDEBUGGETCORECONFIGURATIONSTRING PcieDebugGetCoreConfigurationStringTN; + + PCIe_FAM_DEBUG_SERVICES GnbPcieDebugProtocolTN = { + PcieDebugGetHostRegAddressSpaceStringTN, + PcieDebugGetWrapperNameStringTN, + PcieDebugGetCoreConfigurationStringTN + }; + + GNB_SERVICE GnbPcieDebugServicesTN = { + GnbPcieFamDebugService, + AMD_FAMILY_TN, + &GnbPcieDebugProtocolTN, + SERVICES_POINTER + }; + #undef SERVICES_POINTER + #define SERVICES_POINTER &GnbPcieDebugServicesTN + #endif + #endif +#endif + +#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) + extern F_GNB_REGISTER_ACCESS GnbRegisterReadServiceTN; + extern F_GNB_REGISTER_ACCESS GnbRegisterWriteServiceTN; + + GNB_REGISTER_SERVICE GnbRegiterAccessProtocol = { + GnbRegisterReadServiceTN, + GnbRegisterWriteServiceTN + }; + + GNB_SERVICE GnbRegisterAccessServicesTN = { + GnbRegisterAccessService, + AMD_FAMILY_TN, + &GnbRegiterAccessProtocol, + SERVICES_POINTER + }; + #undef SERVICES_POINTER + #define SERVICES_POINTER &GnbRegisterAccessServicesTN + + extern F_GNBFMCREATEIVRSENTRY GnbCreateIvrsEntryTN; + extern F_GNBFMCHECKIOMMUPRESENT GnbCheckIommuPresentTN; + + GNB_FAM_IOMMU_SERVICES GnbIommuConfigProtocolTN = { + GnbCheckIommuPresentTN, + GnbCreateIvrsEntryTN + }; + + GNB_SERVICE GnbIommuConfigServicesTN = { + GnbIommuService, + AMD_FAMILY_TN, + &GnbIommuConfigProtocolTN, + SERVICES_POINTER + }; + #undef SERVICES_POINTER + #define SERVICES_POINTER &GnbIommuConfigServicesTN + +#endif +#endif // _GNB_INIT_TN_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c new file mode 100644 index 0000000..8f176d7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c @@ -0,0 +1,289 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 64352 $ @e $Date: 2012-01-19 03:54:04 -0600 (Thu, 19 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "cpuLateInit.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbIommu.h" +#include "GnbIvrsLib.h" +#include "GnbSbIommuLib.h" +#include "GnbCommonLib.h" +#include "GnbNbInitLibV4.h" +#include "GnbIommuIvrs.h" +#include "GnbRegisterAccTN.h" +#include "GnbRegistersTN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBIOMMUIVRSTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +GnbCreateIvhdHeaderTN ( + IN IVRS_BLOCK_TYPE Type, + OUT IVRS_IVHD_ENTRY *Ivhd, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbCreateIvhdTN ( + OUT IVRS_IVHD_ENTRY *Ivhd, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbCreateIvhdrTN ( + OUT IVRS_IVHD_ENTRY *Ivhd, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbCreateIvrsEntryTN ( + IN GNB_HANDLE *GnbHandle, + IN IVRS_BLOCK_TYPE Type, + IN VOID *Ivrs, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GnbCheckIommuPresentTN ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if IOMMU unit present and enabled + * + * + * + * + * @param[in] GnbHandle Gnb handle + * @param[in] StdHeader Standard configuration header + * + */ +BOOLEAN +GnbCheckIommuPresentTN ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + if (GnbLibPciIsDevicePresent (MAKE_SBDFO (0, 0, 0, 2, 0), StdHeader)) { + return TRUE; + } + return FALSE; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Create IVRS entry + * + * + * @param[in] GnbHandle Gnb handle + * @param[in] Type Entry type + * @param[in] Ivrs IVRS table pointer + * @param[in] StdHeader Standard configuration header + * + */ + +AGESA_STATUS +GnbCreateIvrsEntryTN ( + IN GNB_HANDLE *GnbHandle, + IN IVRS_BLOCK_TYPE Type, + IN VOID *Ivrs, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + IVRS_IVHD_ENTRY *Ivhd; + UINT8 IommuCapabilityOffset; + UINT32 Value; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbFmCreateIvrsEntry Entry\n"); + if (Type == IvrsIvhdBlock || Type == IvrsIvhdrBlock) { + // Update IVINFO + IommuCapabilityOffset = GnbLibFindPciCapability (MAKE_SBDFO (0, 0, 0, 2, 0), IOMMU_CAP_ID, StdHeader); + GnbLibPciRead (MAKE_SBDFO (0, 0, 0, 2, IommuCapabilityOffset + 0x10), AccessWidth32, &Value, StdHeader); + ((IOMMU_IVRS_HEADER *) Ivrs)->IvInfo = Value & (IVINFO_HTATSRESV_MASK | IVINFO_VASIZE_MASK | IVINFO_GASIZE_MASK | IVINFO_PASIZE_MASK); + + // Address of IVHD entry + Ivhd = (IVRS_IVHD_ENTRY*) ((UINT8 *)Ivrs + ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength); + GnbCreateIvhdHeaderTN (Type, Ivhd, StdHeader); + if (Type == IvrsIvhdBlock) { + GnbCreateIvhdTN (Ivhd, StdHeader); + } else { + GnbCreateIvhdrTN (Ivhd, StdHeader); + } + ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength = ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength + Ivhd->Length; + } + IDS_HDT_CONSOLE (GNB_TRACE, "GnbFmCreateIvrsEntry Exit\n"); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Create IVRS entry + * + * + * @param[in] Type Block type + * @param[in] Ivhd IVHD header pointer + * @param[in] StdHeader Standard configuration header + * + */ +VOID +GnbCreateIvhdHeaderTN ( + IN IVRS_BLOCK_TYPE Type, + OUT IVRS_IVHD_ENTRY *Ivhd, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Value; + Ivhd->Type = (UINT8) Type; + Ivhd->Flags = IVHD_FLAG_COHERENT | IVHD_FLAG_IOTLBSUP | IVHD_FLAG_ISOC | IVHD_FLAG_RESPASSPW | IVHD_FLAG_PASSPW | IVHD_FLAG_PPRSUB | IVHD_FLAG_PREFSUP; + Ivhd->Length = sizeof (IVRS_IVHD_ENTRY); + Ivhd->DeviceId = 0x2; + Ivhd->CapabilityOffset = GnbLibFindPciCapability (MAKE_SBDFO (0, 0, 0, 2, 0), IOMMU_CAP_ID, StdHeader); + Ivhd->PciSegment = 0; + GnbLibPciRead (MAKE_SBDFO (0, 0, 0, 2, Ivhd->CapabilityOffset + 0x4), AccessWidth32, &Ivhd->BaseAddress, StdHeader); + GnbLibPciRead (MAKE_SBDFO (0, 0, 0, 2, Ivhd->CapabilityOffset + 0x8), AccessWidth32, (UINT8 *) &Ivhd->BaseAddress + 4, StdHeader); + Ivhd->BaseAddress = Ivhd->BaseAddress & 0xfffffffffffffffe; + ASSERT (Ivhd->BaseAddress != 0x0); + GnbLibPciRead (MAKE_SBDFO (0, 0, 0, 2, Ivhd->CapabilityOffset + 0x10), AccessWidth32, &Value, StdHeader); + Ivhd->IommuInfo = (UINT16) (Value & 0x1f) | (0x13 << IVHD_INFO_UNITID_OFFSET); + Ivhd->IommuEfr = (0 << IVHD_EFR_XTSUP_OFFSET) | (0 << IVHD_EFR_NXSUP_OFFSET) | (1 << IVHD_EFR_GTSUP_OFFSET) | + (0 << IVHD_EFR_GLXSUP_OFFSET) | (1 << IVHD_EFR_IASUP_OFFSET) | (0 << IVHD_EFR_GASUP_OFFSET) | + (0 << IVHD_EFR_HESUP_OFFSET) | (0x8 << IVHD_EFR_PASMAX_OFFSET) | (0 << IVHD_EFR_MSINUMPPR_OFFSET) | + (4 << IVHD_EFR_PNCOUNTERS_OFFSET) | (2 << IVHD_EFR_PNBANKS_OFFSET); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Create IVHD entry + * + * + * @param[in] Ivhd IVHD header pointer + * @param[in] StdHeader Standard configuration header + * + */ +VOID +GnbCreateIvhdTN ( + OUT IVRS_IVHD_ENTRY *Ivhd, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR Start; + PCI_ADDR End; + Start.AddressValue = MAKE_SBDFO (0, 0, 1, 0, 0); + End.AddressValue = MAKE_SBDFO (0, 0xFF, 0x1F, 6, 0); + GnbIvhdAddDeviceRangeEntry (Start, End, 0, Ivhd, StdHeader); + SbCreateIvhdEntries (Ivhd, StdHeader); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Create IVHDR entry + * + * + * @param[in] Ivhd IVHD header pointer + * @param[in] StdHeader Standard configuration header + * + */ +VOID +GnbCreateIvhdrTN ( + OUT IVRS_IVHD_ENTRY *Ivhd, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c new file mode 100644 index 0000000..626f33d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c @@ -0,0 +1,574 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 64352 $ @e $Date: 2012-01-19 03:54:04 -0600 (Thu, 19 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbFuseTable.h" +#include "heapManager.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbNbInitLibV1.h" +#include "GnbNbInitLibV4.h" +#include "GnbGfxInitLibV1.h" +#include "GnbGfxConfig.h" +#include "GnbTable.h" +#include "GnbRegisterAccTN.h" +#include "GnbRegistersTN.h" +#include "OptionGnb.h" +#include "GfxLibTN.h" +#include "GnbFamServices.h" +#include "GnbGfxFamServices.h" +#include "GnbBapmCoeffCalcTN.h" +#include "PcieComplexDataTN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBMIDINITTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_BUILD_OPTIONS GnbBuildOptions; +extern GNB_TABLE ROMDATA GnbMidInitTableTN[]; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +#define NUM_DPM_STATES 8 + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GnbMidInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Registers needs to be set if no GFX PCIe ports beeing us + * + * + * + * @param[in] Pcie Pointer to PCIe_PLATFORM_CONFIG + */ + +VOID +STATIC +GnbIommuMidInitCheckGfxPciePorts ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_WRAPPER_CONFIG *WrapperList; + BOOLEAN GfxPciePortUsed; + D0F2xF4_x57_STRUCT D0F2xF4_x57; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInitCheckGfxPciePorts Enter\n"); + GfxPciePortUsed = FALSE; + + WrapperList = PcieConfigGetChildWrapper (Pcie); + ASSERT (WrapperList != NULL); + if (WrapperList->WrapId == GFX_WRAP_ID) { + PCIe_ENGINE_CONFIG *EngineList; + EngineList = PcieConfigGetChildEngine (WrapperList); + while (EngineList != NULL) { + if (PcieConfigIsPcieEngine (EngineList)) { + IDS_HDT_CONSOLE (GNB_TRACE, "Checking Gfx ports device number %x\n", EngineList->Type.Port.NativeDevNumber); + if (PcieConfigCheckPortStatus (EngineList, INIT_STATUS_PCIE_TRAINING_SUCCESS) || + ((EngineList->Type.Port.PortData.LinkHotplug != HotplugDisabled) && (EngineList->Type.Port.PortData.LinkHotplug != HotplugInboard))) { + // GFX PCIe ports beeing used + GfxPciePortUsed = TRUE; + IDS_HDT_CONSOLE (GNB_TRACE, "GFX PCIe ports beeing used\n"); + break; + } + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + } + + if (!GfxPciePortUsed) { + //D0F2xF4_x57.Field.L1ImuPcieGfxDis needs to be set + GnbRegisterReadTN (D0F2xF4_x57_TYPE, D0F2xF4_x57_ADDRESS, &D0F2xF4_x57.Value, 0, GnbLibGetHeader (Pcie)); + D0F2xF4_x57.Field.L1ImuPcieGfxDis = 1; + GnbRegisterWriteTN (D0F2xF4_x57_TYPE, D0F2xF4_x57_ADDRESS, &D0F2xF4_x57.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie)); + } + IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInitCheckGfxPciePorts Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to for each PCIe port + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +GnbIommuMidInitOnPortCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + GNB_TOPOLOGY_INFO TopologyInfo; + D0F2xFC_x07_L1_STRUCT D0F2xFC_x07_L1; + D0F2xFC_x0D_L1_STRUCT D0F2xFC_x0D_L1; + UINT8 L1cfgSel; + TopologyInfo.PhantomFunction = FALSE; + TopologyInfo.PcieToPciexBridge = FALSE; + if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { + TopologyInfo.PhantomFunction = TRUE; + TopologyInfo.PcieToPciexBridge = TRUE; + } else { + if (PcieConfigIsSbPcieEngine (Engine)) { + PCI_ADDR StartSbPcieDev; + PCI_ADDR EndSbPcieDev; + StartSbPcieDev.AddressValue = MAKE_SBDFO (0, 0, 0x15, 0, 0); + EndSbPcieDev.AddressValue = MAKE_SBDFO (0, 0, 0x15, 7, 0); + GnbGetTopologyInfoV4 (StartSbPcieDev, EndSbPcieDev, &TopologyInfo, GnbLibGetHeader (Pcie)); + } else { + GnbGetTopologyInfoV4 (Engine->Type.Port.Address, Engine->Type.Port.Address, &TopologyInfo, GnbLibGetHeader (Pcie)); + } + } + L1cfgSel = (Engine->Type.Port.CoreId == 1) ? 1 : 0; + if (TopologyInfo.PhantomFunction) { + GnbRegisterReadTN ( + D0F2xFC_x07_L1_TYPE, + D0F2xFC_x07_L1_ADDRESS (L1cfgSel), + &D0F2xFC_x07_L1.Value, + 0, + GnbLibGetHeader (Pcie) + ); + D0F2xFC_x07_L1.Value |= BIT0; + GnbRegisterWriteTN ( + D0F2xFC_x07_L1_TYPE, + D0F2xFC_x07_L1_ADDRESS (L1cfgSel), + &D0F2xFC_x07_L1.Value, + GNB_REG_ACC_FLAG_S3SAVE, + GnbLibGetHeader (Pcie) + ); + } + if (TopologyInfo.PcieToPciexBridge) { + GnbRegisterReadTN ( + D0F2xFC_x0D_L1_TYPE, + D0F2xFC_x0D_L1_ADDRESS (L1cfgSel), + &D0F2xFC_x0D_L1.Value, + 0, + GnbLibGetHeader (Pcie) + ); + D0F2xFC_x0D_L1.Field.VOQPortBits = 0x7; + GnbRegisterWriteTN ( + D0F2xFC_x0D_L1_TYPE, + D0F2xFC_x0D_L1_ADDRESS (L1cfgSel), + &D0F2xFC_x0D_L1.Value, + GNB_REG_ACC_FLAG_S3SAVE, + GnbLibGetHeader (Pcie) + ); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Orb/Ioc Cgtt Override setting + * + * + * @param[in] Property Property + * @param[in] StdHeader Standard configuration header + */ + +VOID +STATIC +GnbCgttOverrideTN ( + IN UINT32 Property, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 CGINDx0_Value; + UINT32 CGINDx1_Value; + GFX_PLATFORM_CONFIG *Gfx; + AGESA_STATUS Status; + D0F0x64_x23_STRUCT D0F0x64_x23; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbCgttOverrideTN Enter\n"); + + CGINDx0_Value = 0xFFFFFFFF; + //When orb clock gating is enabled in the BIOS clear CG_ORB_cgtt_lclk_override - bit 13 + CGINDx1_Value = 0xFFFFFFFF; + if ((Property & TABLE_PROPERTY_ORB_CLK_GATING) == TABLE_PROPERTY_ORB_CLK_GATING) { + CGINDx1_Value &= 0xFFFFDFFF; + } + //When ioc clock gating is enabled in the BIOS clear CG_IOC_cgtt_lclk_override - bit 15 + if ((Property & TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING) == TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING) { + CGINDx1_Value &= 0xFFFF7FFF; + if ((Property & TABLE_PROPERTY_IOMMU_DISABLED) != TABLE_PROPERTY_IOMMU_DISABLED) { + //only IOMMU enabled and IOC clock gating enable + GnbRegisterReadTN (D0F0x64_x23_TYPE, D0F0x64_x23_ADDRESS, &D0F0x64_x23.Value, 0, StdHeader); + D0F0x64_x23.Field.SoftOverrideClk0 = 1; + D0F0x64_x23.Field.SoftOverrideClk1 = 1; + D0F0x64_x23.Field.SoftOverrideClk3 = 1; + D0F0x64_x23.Field.SoftOverrideClk4 = 1; + GnbRegisterWriteTN (D0F0x64_x23_TYPE, D0F0x64_x23_ADDRESS, &D0F0x64_x23.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + } + } + //When smu sclk clock gating is enabled in the BIOS clear CG_IOC_cgtt_lclk_override - bit 18 + if ((Property & TABLE_PROPERTY_SMU_SCLK_CLOCK_GATING) == TABLE_PROPERTY_SMU_SCLK_CLOCK_GATING) { + CGINDx1_Value &= 0xFFFBFFFF; + } + + Status = GfxLocateConfigData (StdHeader, &Gfx); + if (Status != AGESA_FATAL) { + if (Gfx->GmcClockGating) { + //In addition to above registers it is necessary to reset override bits for VMC, MCB, and MCD blocks + // CGINDx0, clear bit 27, bit 28 + CGINDx0_Value &= 0xE7FFFFFF; + GnbRegisterWriteTN (TYPE_CGIND, 0x0, &CGINDx0_Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + // CGINDx1, clear bit 11 + CGINDx1_Value &= 0xFFFFF7FF; + } + + } + + if (CGINDx1_Value != 0xFFFFFFFF) { + GnbRegisterWriteTN (TYPE_CGIND, 0x1, &CGINDx1_Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + } + IDS_HDT_CONSOLE (GNB_TRACE, "GnbCgttOverrideTN Exit\n"); + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * IOMMU Mid Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +STATIC AGESA_STATUS +GnbIommuMidInit ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInit Enter\n"); + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + if (Status == AGESA_SUCCESS) { + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + GnbIommuMidInitOnPortCallback, + NULL, + Pcie + ); + } + + GnbIommuMidInitCheckGfxPciePorts (Pcie); + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInit Exit [0x%x]\n", Status); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * IOMMU Mid Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +STATIC AGESA_STATUS +GnbLclkDpmInitTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + PP_FUSE_ARRAY *PpFuseArray; + PCI_ADDR GnbPciAddress; + UINT32 Index; + UINT8 LclkDpmMode; + D0F0xBC_x1F200_STRUCT D0F0xBC_x1F200[NUM_DPM_STATES]; + D0F0xBC_x1F208_STRUCT D0F0xBC_x1F208[NUM_DPM_STATES]; + D0F0xBC_x1F210_STRUCT D0F0xBC_x1F210[NUM_DPM_STATES]; + D0F0xBC_x1F300_STRUCT D0F0xBC_x1F300; + ex1003_STRUCT ex1003 [NUM_DPM_STATES]; + DOUBLE PcieCacLut; + ex1072_STRUCT ex1072 ; + D0F0xBC_x1FE00_STRUCT D0F0xBC_x1FE00; + D0F0xBC_x1F30C_STRUCT D0F0xBC_x1F30C; + D18F3x64_STRUCT D18F3x64; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbLclkDpmInitTN Enter\n"); + Status = AGESA_SUCCESS; + LclkDpmMode = GnbBuildOptions.LclkDpmEn ? LclkDpmRcActivity : LclkDpmDisabled; + IDS_OPTION_HOOK (IDS_GNB_LCLK_DPM_EN, &LclkDpmMode, StdHeader); + if (LclkDpmMode == LclkDpmRcActivity) { + PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); + if (PpFuseArray != NULL) { + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + if (Status == AGESA_SUCCESS) { + GnbPciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0); + //Clear DPM_EN bit in LCLK_DPM_CNTL register + //Call BIOS service SMC_MSG_CONFIG_LCLK_DPM to disable LCLK DPM + GnbRegisterReadTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, 0, StdHeader); + D0F0xBC_x1F300.Field.LclkDpmEn = 0x0; + GnbRegisterWriteTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + GnbSmuServiceRequestV4 ( + GnbPciAddress, + SMC_MSG_CONFIG_LCLK_DPM, + GNB_REG_ACC_FLAG_S3SAVE, + StdHeader + ); + + //Initialize LCLK states + LibAmdMemFill (D0F0xBC_x1F200, 0x00, sizeof (D0F0xBC_x1F200), StdHeader); + LibAmdMemFill (D0F0xBC_x1F208, 0x00, sizeof (D0F0xBC_x1F208), StdHeader); + LibAmdMemFill (ex1003, 0x00, sizeof (D0F0xBC_x1F208), StdHeader); + + D0F0xBC_x1F200[0].Field.LclkDivider = PpFuseArray->LclkDpmDid[0]; + D0F0xBC_x1F200[0].Field.VID = PpFuseArray->SclkVid[PpFuseArray->LclkDpmVid[0]]; + D0F0xBC_x1F200[0].Field.LowVoltageReqThreshold = 0xa; + D0F0xBC_x1F210[0].Field.ActivityThreshold = 0xf; + + D0F0xBC_x1F200[5].Field.LclkDivider = PpFuseArray->LclkDpmDid[1]; + D0F0xBC_x1F200[5].Field.VID = PpFuseArray->SclkVid[PpFuseArray->LclkDpmVid[1]]; + D0F0xBC_x1F200[5].Field.LowVoltageReqThreshold = 0xa; + D0F0xBC_x1F210[5].Field.ActivityThreshold = 0x32; + D0F0xBC_x1F200[5].Field.StateValid = 0x1; + + D0F0xBC_x1F200[6].Field.LclkDivider = PpFuseArray->LclkDpmDid[2]; + D0F0xBC_x1F200[6].Field.VID = PpFuseArray->SclkVid[PpFuseArray->LclkDpmVid[2]]; + D0F0xBC_x1F200[6].Field.LowVoltageReqThreshold = 0xa; + D0F0xBC_x1F210[6].Field.ActivityThreshold = 0x32; + D0F0xBC_x1F200[6].Field.StateValid = 0x1; + + GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f920 , &ex1072.Value, 0, StdHeader); + PcieCacLut = 0.0000057028 * (1 << ex1072.Field.ex1072_0 ); + IDS_HDT_CONSOLE (GNB_TRACE, "LCLK DPM1 10khz %x (%d)\n", GfxFmCalculateClock (PpFuseArray->LclkDpmDid[1], StdHeader), GfxFmCalculateClock (PpFuseArray->LclkDpmDid[1], StdHeader)); + D0F0xBC_x1FE00.Field.Data = (UINT32) GnbFpLibDoubleToInt32 (PcieCacLut * GfxFmCalculateClock (PpFuseArray->LclkDpmDid[1], StdHeader)); + GnbRegisterWriteTN (D0F0xBC_x1FE00_TYPE, D0F0xBC_x1FE00_ADDRESS, &D0F0xBC_x1FE00.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + PcieCacLut = 0.00000540239329 * (1 << ex1072.Field.ex1072_0 ); + ex1003[6].Field.ex1003_0 = (UINT32) GnbFpLibDoubleToInt32 (PcieCacLut * GfxFmCalculateClock (PpFuseArray->LclkDpmDid[2], StdHeader)); + IDS_HDT_CONSOLE (GNB_TRACE, "LCLK DPM2 10khz %x (%d)\n", GfxFmCalculateClock (PpFuseArray->LclkDpmDid[2], StdHeader), GfxFmCalculateClock (PpFuseArray->LclkDpmDid[2], StdHeader)); + + for (Index = 0; Index < NUM_DPM_STATES; ++Index) { + GnbRegisterWriteTN ( + D0F0xBC_x1F200_TYPE, + D0F0xBC_x1F200_ADDRESS + Index * 0x20, + &D0F0xBC_x1F200[Index].Value, + GNB_REG_ACC_FLAG_S3SAVE, + StdHeader + ); + GnbRegisterWriteTN ( + D0F0xBC_x1F208_TYPE, + D0F0xBC_x1F208_ADDRESS + Index * 0x20, + &D0F0xBC_x1F208[Index].Value, + GNB_REG_ACC_FLAG_S3SAVE, + StdHeader + ); + GnbRegisterWriteTN ( + D0F0xBC_x1F210_TYPE, + D0F0xBC_x1F210_ADDRESS + Index * 0x20, + &D0F0xBC_x1F210[Index].Value, + GNB_REG_ACC_FLAG_S3SAVE, + StdHeader + ); + GnbRegisterWriteTN ( + TYPE_D0F0xBC , + 0x1f940 + Index * 4, + &ex1003[Index].Value, + GNB_REG_ACC_FLAG_S3SAVE, + StdHeader + ); + } + //Enable LCLK DPM Voltage Scaling + GnbRegisterReadTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, 0, StdHeader); + D0F0xBC_x1F300.Field.VoltageChgEn = 0x1; + D0F0xBC_x1F300.Field.LclkDpmEn = 0x1; + D0F0xBC_x1F300.Field.LclkDpmBootState = 0x5; + GnbRegisterWriteTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + + //Programming Lclk Thermal Throttling Threshold + GnbRegisterReadTN (D18F3x64_TYPE, D18F3x64_ADDRESS, &D18F3x64.Value, 0, StdHeader); + GnbRegisterReadTN (D0F0xBC_x1F30C_TYPE, D0F0xBC_x1F30C_ADDRESS, &D0F0xBC_x1F30C.Value, 0, StdHeader); + D0F0xBC_x1F30C.Field.LowThreshold = (UINT16) (((D18F3x64.Field.HtcTmpLmt / 2 + 52) - 1 + 49) * 8); + D0F0xBC_x1F30C.Field.HighThreshold = (UINT16) (((D18F3x64.Field.HtcTmpLmt / 2 + 52) + 49) * 8); + GnbRegisterWriteTN (D0F0xBC_x1F30C_TYPE, D0F0xBC_x1F30C_ADDRESS, &D0F0xBC_x1F30C.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + + GnbSmuServiceRequestV4 ( + GnbPciAddress, + SMC_MSG_CONFIG_LCLK_DPM, + GNB_REG_ACC_FLAG_S3SAVE, + StdHeader + ); + } + } else { + Status = AGESA_ERROR; + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "GnbLclkDpmInitTN Exit [0x%x]\n", Status); + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Mid Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GnbMidInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + UINT32 Property; + AGESA_STATUS AgesaStatus; + GNB_HANDLE *GnbHandle; + UINT8 SclkDid; + + AgesaStatus = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbMidInterfaceTN Enter\n"); + + GnbHandle = GnbGetHandle (StdHeader); + ASSERT (GnbHandle != NULL); + + Property = TABLE_PROPERTY_DEAFULT; + Property |= GfxLibIsControllerPresent (StdHeader) ? 0 : TABLE_PROPERTY_IGFX_DISABLED; + Property |= GnbBuildOptions.LclkDeepSleepEn ? TABLE_PROPERTY_LCLK_DEEP_SLEEP : 0; + Property |= GnbBuildOptions.CfgOrbClockGatingEnable ? TABLE_PROPERTY_ORB_CLK_GATING : 0; + Property |= GnbBuildOptions.CfgIocLclkClockGatingEnable ? TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING : 0; + Property |= GnbBuildOptions.CfgIocSclkClockGatingEnable ? TABLE_PROPERTY_IOC_SCLK_CLOCK_GATING : 0; + Property |= GnbFmCheckIommuPresent (GnbHandle, StdHeader) ? 0: TABLE_PROPERTY_IOMMU_DISABLED; + Property |= GnbBuildOptions.SmuSclkClockGatingEnable ? TABLE_PROPERTY_SMU_SCLK_CLOCK_GATING : 0; + + IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader); + + if ((Property & TABLE_PROPERTY_IOMMU_DISABLED) == 0) { + Status = GnbEnableIommuMmioV4 (GnbHandle, StdHeader); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + Status = GnbIommuMidInit (StdHeader); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } + // + // Set sclk to 100Mhz + // + SclkDid = GfxRequestSclkTNS3Save ( + GfxLibCalculateDidTN (98 * 100, StdHeader), + StdHeader + ); + + Status = GnbProcessTable ( + GnbHandle, + GnbMidInitTableTN, + Property, + GNB_TABLE_FLAGS_FORCE_S3_SAVE, + StdHeader + ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + // + // Restore Sclk + // + GfxRequestSclkTNS3Save ( + SclkDid, + StdHeader + ); + + GnbCgttOverrideTN (Property, StdHeader); + + Status = GnbLclkDpmInitTN (StdHeader); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbMidInterfaceTN Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c new file mode 100644 index 0000000..efa2af1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c @@ -0,0 +1,128 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbNbInitLibV1.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBPOSTINITTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GnbPostInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Early Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GnbPostInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + PCI_ADDR GnbAddress; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbPostInterfaceTN Enter\n"); + GnbAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0); + Status = GnbSetTom (GnbAddress, StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, "GnbPostInterfaceTN Exit [0x%x]\n", Status); + return Status; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c new file mode 100644 index 0000000..8d36a1f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c @@ -0,0 +1,1334 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize PP/DPM fuse table. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 64211 $ @e $Date: 2012-01-17 23:00:25 -0600 (Tue, 17 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbNbInitLibV4.h" +#include "GnbRegisterAccTN.h" +#include "GnbRegistersTN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBREGISTERACCTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define GNB_IGNORED_PARAM 0xFF +#define ORB_WRITE_ENABLE 0x100 +#define IOMMU_L1_WRITE_ENABLE 0x80000000ul +#define IOMMU_L2_WRITE_ENABLE 0x100 + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +GnbRegisterWriteTNDump ( + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + IN VOID *Value + ); +AGESA_STATUS +GnbRegisterReadServiceTN ( + IN GNB_HANDLE *GnbHandle, + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + OUT VOID *Value, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbRegisterWriteServiceTN ( + IN GNB_HANDLE *GnbHandle, + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + IN VOID *Value, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ); +/*----------------------------------------------------------------------------------------*/ +/* + * Config Dct and Mp. + * + * + * + * @param[in] DctCfgSel Dct0/Dct1 + * @param[in] MemPsSel Mp0/Mp1 + * @param[in] StdHeader Standard configuration header + * + * @return true - Memory Pstate context has been changed + * @return false - Memory Pstate context has not been changed + */ +STATIC BOOLEAN +GnbDctMpConfigTN ( + IN UINT8 DctCfgSel, + IN UINT8 MemPsSel, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + // Select DCT and memory P-state, D18F1x10C[DctCfgSel], D18F1x10C[MemPsSel] + D18F1x10C_STRUCT D18F1x10C; + BOOLEAN MemPsChangd; + ACCESS_WIDTH Width; + + MemPsChangd = FALSE; + Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32; + + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 1, D18F1x10C_ADDRESS), + Width, + &D18F1x10C.Value, + StdHeader + ); + + if ((DctCfgSel != 0xFF) && (DctCfgSel < 2)) { + D18F1x10C.Field.DctCfgSel = DctCfgSel; + } + + if ((MemPsSel != 0xFF) && (MemPsSel < 2) && (D18F1x10C.Field.MemPsSel != MemPsSel)) { + //Switches Mem Pstate + D18F1x10C.Field.MemPsSel = MemPsSel; + MemPsChangd = TRUE; + } + + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 1, D18F1x10C_ADDRESS), + Width, + &D18F1x10C.Value, + StdHeader + ); + + return MemPsChangd; + +} + +/*----------------------------------------------------------------------------------------*/ +/* + * Routine to Read Dct Additional Data. + * + * + * + * @param[in] Address D18F2x9c Register offset + * @param[in] DctCfgSel Dct0/Dct1 + * @param[in] MemPsSel Mp0/Mp1 + * @param[out] Value Read value + * @param[in] StdHeader Standard configuration header + */ +STATIC VOID +GnbDctAdditionalDataReadTN ( + IN UINT32 Address, + IN UINT8 DctCfgSel, + IN UINT8 MemPsSel, + IN UINT32 Flags, + OUT VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D18F2x98_dct0_STRUCT D18F2x98; + BOOLEAN PstateChanged; + ACCESS_WIDTH Width; + + Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32; + + PstateChanged = GnbDctMpConfigTN ( + DctCfgSel, + MemPsSel, + Flags, + StdHeader + ); + + // Clear DctAccessWrite + D18F2x98.Field.DctOffset = Address & 0x3FFFFFFF; + D18F2x98.Field.DctAccessWrite = 0; + + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 2, ((DctCfgSel == 0) ? D18F2x98_dct0_ADDRESS : D18F2x98_dct1_ADDRESS)), + Width, + &D18F2x98.Value, + StdHeader + ); + + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 2, ((DctCfgSel == 0) ? D18F2x9C_dct0_ADDRESS : D18F2x9C_dct1_ADDRESS)), + Width, + Value, + StdHeader + ); + + if (PstateChanged) { + GnbDctMpConfigTN ( + DctCfgSel, + ((MemPsSel == 0) ? 1 : 0), + Flags, + StdHeader + ); + } +} + +/*----------------------------------------------------------------------------------------*/ +/* + * Routine to Write Dct Additional Data. + * + * + * + * @param[in] Address D18F2x9c Register offset + * @param[in] DctCfgSel Dct0/Dct1 + * @param[in] MemPsSel Mp0/Mp1 + * @param[in] Value Write value + * @param[in] StdHeader Standard configuration header + */ +STATIC VOID +GnbDctAdditionalDataWriteTN ( + IN UINT32 Address, + IN UINT8 DctCfgSel, + IN UINT8 MemPsSel, + IN UINT32 Flags, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D18F2x98_dct0_STRUCT D18F2x98; + BOOLEAN PstateChanged; + ACCESS_WIDTH Width; + + Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32; + + PstateChanged = GnbDctMpConfigTN ( + DctCfgSel, + MemPsSel, + Flags, + StdHeader + ); + + // Put write data on + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 2, ((DctCfgSel == 0) ? D18F2x9C_dct0_ADDRESS : D18F2x9C_dct1_ADDRESS)), + Width, + Value, + StdHeader + ); + + // Set DctAccessWrite + D18F2x98.Field.DctOffset = Address & 0x3FFFFFFF; + D18F2x98.Field.DctAccessWrite = 1; + + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 2, ((DctCfgSel == 0) ? D18F2x98_dct0_ADDRESS : D18F2x98_dct1_ADDRESS)), + Width, + &D18F2x98.Value, + StdHeader + ); + + if (PstateChanged) { + GnbDctMpConfigTN ( + DctCfgSel, + ((MemPsSel == 0) ? 1 : 0), + Flags, + StdHeader + ); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/* + * Routine to read all register spaces. + * + * + * + * @param[in] GnbHandle GNB handle + * @param[in] RegisterSpaceType Register space type + * @param[in] Address Register offset, but PortDevice + * @param[out] Value Return value + * @param[in] Flags Flags - BIT0 indicates S3 save/restore + * @param[in] StdHeader Standard configuration header + */ +AGESA_STATUS +GnbRegisterReadServiceTN ( + IN GNB_HANDLE *GnbHandle, + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + OUT VOID *Value, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return GnbRegisterReadTN (RegisterSpaceType, Address, Value, Flags, StdHeader); +} +/*----------------------------------------------------------------------------------------*/ +/* + * Routine to read all register spaces. + * + * + * + * @param[in] RegisterSpaceType Register space type + * @param[in] Address Register offset, but PortDevice + * @param[out] Value Return value + * @param[in] Flags Flags - BIT0 indicates S3 save/restore + * @param[in] StdHeader Standard configuration header + */ +AGESA_STATUS +GnbRegisterReadTN ( + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + OUT VOID *Value, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + ACCESS_WIDTH Width; + UINT32 TempValue; + UINT32 TempAddress; + BOOLEAN PstateChanged; + + Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32; + TempAddress = 0; + TempValue = 0; + + + switch (RegisterSpaceType) { + case TYPE_D0F0: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0, 0, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D0F2: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0, 2, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D1F0: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 1, 0, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D1F1: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 1, 1, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_DxF0: + // Treat it as complete address for ports + GnbLibPciRead ( + Address, + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F1: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 1, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F2: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F3: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 3, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F4: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 4, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F5: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 5, Address), + Width, + Value, + StdHeader + ); + break; + + case TYPE_D0F0x64: + // Miscellaneous Index Data, access the registers D0F0x64_x[FF:00] + // Write enable bit7 + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), + Address, + Width, + Value, + StdHeader + ); + break; + + case TYPE_D0F0x98: + // Northbridge ORB Configuration Offset, access D0F0x98_x[FF:00] + // Write enable bit8 + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 0, D0F0x94_ADDRESS), + Address, + Width, + Value, + StdHeader + ); + break; + + case TYPE_D0F0xBC: + { + //SMU, access D0F0xBC_x[FFFFFFFF:00000000] + // No write enable + UINT64 TempData; + //ASSERT ((Address < 0xE0100000 || Address > 0xE0108FFFF) && (Address & 0x3) == 0); + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 0, D0F0xB8_ADDRESS), + (Address & (~0x3ull)), + Width, + &TempData, + StdHeader + ); + if ((Address & 0x3) != 0) { + //Non aligned access allowed to fuse block + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 0, D0F0xB8_ADDRESS), + (Address & (~0x3ull)) + 4, + Width, + ((UINT32 *) &TempData) + 1, + StdHeader + ); + } + * ((UINT32*) Value) = (UINT32) (TempData >> ((Address & 0x3) * 8)); + break; + } + case TYPE_D0F0xE4: + // D0F0xE0 Link Index Address, access D0F0xE4_x[FFFF_FFFF:0000_0000] + // No write enable + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 0, D0F0xE0_ADDRESS), + Address, + Width, + Value, + StdHeader + ); + break; + + case TYPE_D0F2xF4: + // IOMMU L2 Config Index, to access the registers D0F2xF4_x[FF:00]. + // Write enable bit8 + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 2, 0xF0),//D0F2xF0_ADDRESS + Address, + Width, + Value, + StdHeader + ); + break; + + case TYPE_D0F2xFC: + // IOMMU L1 Config Index, access the registers D0F2xFC_x[FFFF:0000]_L1[3:0] + // Write enable bit31 + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 2, 0xF8),//D0F2xF8_ADDRESS + Address, + Width, + Value, + StdHeader + ); + break; + + case TYPE_DxF0xE4: + // D[8:2]F0xE0 Root Port Index, access the registers D[8:2]F0xE4_x[FF:00] + // No write enable + TempValue = ((Address >> 16) & 0xFF); + TempAddress = Address & 0xFF; + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, (TempValue), 0, 0xE0),//DxF0xE0_ADDRESS + TempAddress, + Width, + Value, + StdHeader + ); + break; + + case TYPE_MSR: + LibAmdMsrRead (Address, Value, StdHeader); + break; + + case TYPE_GMM: + ASSERT (Address < 0x40000); + + if ((Address >= 0x600) && (Address <= 0x8FF)) { + // CG + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 0, 0xB8), + (0xE0002000 | (Address - 0x600)), + Width, + Value, + StdHeader + ); + } else { + // SRBM + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 0, 0xB8), + (0x80080000 | (Address & 0x3FFFF)), + Width, + Value, + StdHeader + ); + } + break; + + case TYPE_D18F2x9C_dct0: + GnbDctAdditionalDataReadTN ( + Address, + 0, + GNB_IGNORED_PARAM, + Flags, + Value, + StdHeader + ); + break; + + case TYPE_D18F2x9C_dct0_mp0: + GnbDctAdditionalDataReadTN ( + Address, + 0, + 0, + Flags, + Value, + StdHeader + ); + break; + + case TYPE_D18F2x9C_dct0_mp1: + GnbDctAdditionalDataReadTN ( + Address, + 0, + 1, + Flags, + Value, + StdHeader + ); + break; + + case TYPE_D18F2x9C_dct1: + GnbDctAdditionalDataReadTN ( + Address, + 1, + GNB_IGNORED_PARAM, + Flags, + Value, + StdHeader + ); + break; + + case TYPE_D18F2x9C_dct1_mp0: + GnbDctAdditionalDataReadTN ( + Address, + 1, + 0, + Flags, + Value, + StdHeader + ); + break; + + case TYPE_D18F2x9C_dct1_mp1: + GnbDctAdditionalDataReadTN ( + Address, + 1, + 1, + Flags, + Value, + StdHeader + ); + break; + + case TYPE_D18F2_dct0: + GnbDctMpConfigTN ( + 0, + GNB_IGNORED_PARAM, + Flags, + StdHeader + ); + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + break; + + case TYPE_D18F2_dct0_mp0: + PstateChanged = GnbDctMpConfigTN ( + 0, + 0, + Flags, + StdHeader + ); + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + if (PstateChanged) { + GnbDctMpConfigTN ( + 0, + 1, + Flags, + StdHeader + ); + } + break; + + case TYPE_D18F2_dct0_mp1: + PstateChanged = GnbDctMpConfigTN ( + 0, + 1, + Flags, + StdHeader + ); + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + if (PstateChanged) { + GnbDctMpConfigTN ( + 0, + 0, + Flags, + StdHeader + ); + } + break; + + case TYPE_D18F2_dct1: + GnbDctMpConfigTN ( + 1, + GNB_IGNORED_PARAM, + Flags, + StdHeader + ); + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + break; + + case TYPE_D18F2_dct1_mp0: + PstateChanged = GnbDctMpConfigTN ( + 1, + 0, + Flags, + StdHeader + ); + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + if (PstateChanged) { + GnbDctMpConfigTN ( + 1, + 1, + Flags, + StdHeader + ); + } + break; + + case TYPE_D18F2_dct1_mp1: + PstateChanged = GnbDctMpConfigTN ( + 1, + 1, + Flags, + StdHeader + ); + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + if (PstateChanged) { + GnbDctMpConfigTN ( + 1, + 0, + Flags, + StdHeader + ); + } + break; + + case TYPE_CGIND: + // CG index + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 0, 0xB8), + (0xE0002000 | (0x8F8 - 0x600)), + Width, + &Address, + StdHeader + ); + // CG data + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 0, 0xB8), + (0xE0002000 | (0x8FC - 0x600)), + Width, + Value, + StdHeader + ); + break; + + default: + ASSERT (FALSE); + break; + } + + + + + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/* + * Routine to write all register spaces. + * + * + * + * @param[in] GnbHandle GnbHandle + * @param[in] RegisterSpaceType Register space type + * @param[in] Address Register offset, but PortDevice + * @param[out] Value The value to write + * @param[in] Flags Flags - BIT0 indicates S3 save/restore + * @param[in] StdHeader Standard configuration header + */ +AGESA_STATUS +GnbRegisterWriteServiceTN ( + IN GNB_HANDLE *GnbHandle, + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + IN VOID *Value, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return GnbRegisterWriteTN (RegisterSpaceType, Address, Value, Flags, StdHeader); +} + +/*----------------------------------------------------------------------------------------*/ +/* + * Routine to write all register spaces. + * + * + * + * @param[in] RegisterSpaceType Register space type + * @param[in] Address Register offset, but PortDevice + * @param[out] Value The value to write + * @param[in] Flags Flags - BIT0 indicates S3 save/restore + * @param[in] StdHeader Standard configuration header + */ +AGESA_STATUS +GnbRegisterWriteTN ( + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + IN VOID *Value, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + ACCESS_WIDTH Width; + UINT32 TempValue; + UINT32 TempAddress; + PCI_ADDR PciAddress; + BOOLEAN PstateChanged; + + Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32; + TempAddress = 0; + TempValue = 0; + + GNB_DEBUG_CODE ( + GnbRegisterWriteTNDump (RegisterSpaceType, Address, Value); + ); + + switch (RegisterSpaceType) { + case TYPE_D0F0: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0, 0, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D0F2: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0, 2, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D1F0: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 1, 0, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D1F1: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 1, 1, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_DxF0: + // Treat it as complete address for ports + GnbLibPciWrite ( + Address, + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F1: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 1, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F2: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F3: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 3, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F4: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 4, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F5: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 5, Address), + Width, + Value, + StdHeader + ); + break; + + case TYPE_D0F0x64: + // Miscellaneous Index Data, access the registers D0F0x64_x[FF:00] + // Write enable bit7 + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), + Address | IOC_WRITE_ENABLE, + Width, + Value, + StdHeader + ); + break; + + case TYPE_D0F0x98: + // Northbridge ORB Configuration Offset, access D0F0x98_x[FF:00] + // Write enable bit8 + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 0, D0F0x94_ADDRESS), + Address | ORB_WRITE_ENABLE, + Width, + Value, + StdHeader + ); + break; + + case TYPE_D0F0xBC: + //SMU, access D0F0xBC_x[FFFFFFFF:00000000] + // No write enable + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 0, 0xB8), + Address, + Width, + Value, + StdHeader + ); + break; + + case TYPE_D0F0xE4: + // D0F0xE0 Link Index Address, access D0F0xE4_x[FFFF_FFFF:0000_0000] + // No write enable + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 0, D0F0xE0_ADDRESS), + Address, + Width, + Value, + StdHeader + ); + break; + + case TYPE_D0F2xF4: + // IOMMU L2 Config Index, to access the registers D0F2xF4_x[FF:00]. + // Write enable bit8 + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 2, 0xF0),//D0F2xF0_ADDRESS + Address | IOMMU_L2_WRITE_ENABLE, + Width, + Value, + StdHeader + ); + break; + + case TYPE_D0F2xFC: + // IOMMU L1 Config Index, access the registers D0F2xFC_x[FFFF:0000]_L1[3:0] + // Write enable bit31 + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 2, 0xF8),//D0F2xF8_ADDRESS + Address | IOMMU_L1_WRITE_ENABLE, + Width, + Value, + StdHeader + ); + break; + + case TYPE_DxF0xE4: + // D[8:2]F0xE0 Root Port Index, access the registers D[8:2]F0xE4_x[FF:00] + // No write enable + TempValue = ((Address >> 16) & 0xFF); + TempAddress = Address & 0xFF; + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, (TempValue), 0, 0xE0),//DxF0xE0_ADDRESS + TempAddress, + Width, + Value, + StdHeader + ); + break; + + case TYPE_MSR: + LibAmdMsrWrite (Address, Value, StdHeader); + break; + + case TYPE_GMM: + ASSERT (Address < 0x40000); + + if ((Address >= 0x600) && (Address <= 0x8FF)) { + // CG + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 0, 0xB8), + (0xE0002000 | (Address - 0x600)), + Width, + Value, + StdHeader + ); + } else { + // SRBM + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 0, 0xB8), + (0x80080000 | (Address & 0x3FFFF)), + Width, + Value, + StdHeader + ); + } + break; + + case TYPE_D18F2x9C_dct0: + GnbDctAdditionalDataWriteTN ( + Address, + 0, + GNB_IGNORED_PARAM, + Flags, + Value, + StdHeader + ); + break; + + case TYPE_D18F2x9C_dct0_mp0: + GnbDctAdditionalDataWriteTN ( + Address, + 0, + 0, + Flags, + Value, + StdHeader + ); + break; + + case TYPE_D18F2x9C_dct0_mp1: + GnbDctAdditionalDataWriteTN ( + Address, + 0, + 1, + Flags, + Value, + StdHeader + ); + break; + + case TYPE_D18F2x9C_dct1: + GnbDctAdditionalDataWriteTN ( + Address, + 1, + GNB_IGNORED_PARAM, + Flags, + Value, + StdHeader + ); + break; + + case TYPE_D18F2x9C_dct1_mp0: + GnbDctAdditionalDataWriteTN ( + Address, + 1, + 0, + Flags, + Value, + StdHeader + ); + break; + + case TYPE_D18F2x9C_dct1_mp1: + GnbDctAdditionalDataWriteTN ( + Address, + 1, + 1, + Flags, + Value, + StdHeader + ); + break; + + case TYPE_D18F2_dct0: + GnbDctMpConfigTN ( + 0, + GNB_IGNORED_PARAM, + Flags, + StdHeader + ); + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + break; + + case TYPE_D18F2_dct0_mp0: + PstateChanged = GnbDctMpConfigTN ( + 0, + 0, + Flags, + StdHeader + ); + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + if (PstateChanged) { + GnbDctMpConfigTN ( + 0, + 1, + Flags, + StdHeader + ); + } + break; + + case TYPE_D18F2_dct0_mp1: + PstateChanged = GnbDctMpConfigTN ( + 0, + 1, + Flags, + StdHeader + ); + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + if (PstateChanged) { + GnbDctMpConfigTN ( + 0, + 0, + Flags, + StdHeader + ); + } + break; + + case TYPE_D18F2_dct1: + GnbDctMpConfigTN ( + 1, + GNB_IGNORED_PARAM, + Flags, + StdHeader + ); + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + break; + + case TYPE_D18F2_dct1_mp0: + PstateChanged = GnbDctMpConfigTN ( + 1, + 0, + Flags, + StdHeader + ); + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + if (PstateChanged) { + GnbDctMpConfigTN ( + 1, + 1, + Flags, + StdHeader + ); + } + break; + + case TYPE_D18F2_dct1_mp1: + PstateChanged = GnbDctMpConfigTN ( + 1, + 1, + Flags, + StdHeader + ); + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + if (PstateChanged) { + GnbDctMpConfigTN ( + 1, + 0, + Flags, + StdHeader + ); + } + break; + + case TYPE_CGIND: + // CG index + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 0, 0xB8), + (0xE0002000 | (0x8F8 - 0x600)), + Width, + &Address, + StdHeader + ); + // CG data + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 0, 0xB8), + (0xE0002000 | (0x8FC - 0x600)), + Width, + Value, + StdHeader + ); + break; + case TYPE_SMU_MSG: + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0); + GnbSmuServiceRequestV4 (PciAddress, (UINT8) Address, Flags, StdHeader); + break; + default: + ASSERT (FALSE); + break; + } + + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/* + * Routine to dump all write register spaces. + * + * + * + * @param[in] RegisterSpaceType Register space type + * @param[in] Address Register offset + * @param[in] Value The value to write + */ +VOID +GnbRegisterWriteTNDump ( + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + IN VOID *Value + ) +{ + IDS_HDT_CONSOLE (NB_MISC, " R WRITE Space %s Address 0x%04x, Value 0x%04x\n", + (RegisterSpaceType == TYPE_D0F0) ? "TYPE_D0F0" : ( + (RegisterSpaceType == TYPE_D0F0x64) ? "TYPE_D0F0x64" : ( + (RegisterSpaceType == TYPE_D0F0x98) ? "TYPE_D0F0x98" : ( + (RegisterSpaceType == TYPE_D0F0xBC) ? "TYPE_D0F0xBC" : ( + (RegisterSpaceType == TYPE_D0F0xE4) ? "TYPE_D0F0xE4" : ( + (RegisterSpaceType == TYPE_DxF0) ? "TYPE_DxF0" : ( + (RegisterSpaceType == TYPE_DxF0xE4) ? "TYPE_DxF0xE4" : ( + (RegisterSpaceType == TYPE_D0F2) ? "TYPE_D0F2" : ( + (RegisterSpaceType == TYPE_D0F2xF4) ? "TYPE_D0F2xF4" : ( + (RegisterSpaceType == TYPE_D0F2xFC) ? "TYPE_D0F2xFC" : ( + (RegisterSpaceType == TYPE_D18F1) ? "TYPE_D18F1" : ( + (RegisterSpaceType == TYPE_D18F2) ? "TYPE_D18F2" : ( + (RegisterSpaceType == TYPE_D18F3) ? "TYPE_D18F3" : ( + (RegisterSpaceType == TYPE_D18F4) ? "TYPE_D18F4" : ( + (RegisterSpaceType == TYPE_D18F5) ? "TYPE_D18F5" : ( + (RegisterSpaceType == TYPE_MSR) ? "TYPE_MSR" : ( + (RegisterSpaceType == TYPE_D1F0) ? "TYPE_D1F0" : ( + (RegisterSpaceType == TYPE_D1F1) ? "TYPE_D1F1" : ( + (RegisterSpaceType == TYPE_GMM) ? "TYPE_GMM" : ( + (RegisterSpaceType == TYPE_D18F2x9C_dct0) ? "TYPE_D18F2x9C_dct0" : ( + (RegisterSpaceType == TYPE_D18F2x9C_dct0_mp0) ? "TYPE_D18F2x9C_dct0_mp0" : ( + (RegisterSpaceType == TYPE_D18F2x9C_dct0_mp1) ? "TYPE_D18F2x9C_dct0_mp1" : ( + (RegisterSpaceType == TYPE_D18F2x9C_dct1) ? "TYPE_D18F2x9C_dct1" : ( + (RegisterSpaceType == TYPE_D18F2x9C_dct1_mp0) ? "TYPE_D18F2x9C_dct1_mp0" : ( + (RegisterSpaceType == TYPE_D18F2x9C_dct1_mp1) ? "TYPE_D18F2x9C_dct1_mp1" : ( + (RegisterSpaceType == TYPE_D18F2_dct0) ? "TYPE_D18F2_dct0" : ( + (RegisterSpaceType == TYPE_D18F2_dct0_mp0) ? "TYPE_D18F2_dct0_mp0" : ( + (RegisterSpaceType == TYPE_D18F2_dct0_mp1) ? "TYPE_D18F2_dct0_mp1" : ( + (RegisterSpaceType == TYPE_D18F2_dct1) ? "TYPE_D18F2_dct1" : ( + (RegisterSpaceType == TYPE_D18F2_dct1_mp0) ? "TYPE_D18F2_dct1_mp0" : ( + (RegisterSpaceType == TYPE_SMU_MSG) ? "TYPE_SMU_MSG" : ( + (RegisterSpaceType == TYPE_D18F2_dct1_mp1) ? "TYPE_D18F2_dct1_mp1" : "Invalid"))))))))))))))))))))))))))))))), + Address, + *((UINT32*)Value) + ); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.h new file mode 100644 index 0000000..6de5c46 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.h @@ -0,0 +1,101 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * various service procedures + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBREGISTERACCTN_H_ +#define _GNBREGISTERACCTN_H_ + +AGESA_STATUS +GnbRegisterWriteTN ( + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + IN VOID *Value, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbRegisterReadTN ( + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + OUT VOID *Value, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +// Marco +// DxF0 Port space +#define PORT_SPACE(Dev, Offset) MAKE_SBDFO (0, 0, Dev, 0, Offset) + +// DxF0xE4 Port indirect space +#define PORTINDT_SPACE(Dev , Func, Offset) ((((UINT32) (Dev)) << 16) | (((UINT32) (Func)) << 8) | \ + ((UINT32)(Offset))) + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h new file mode 100644 index 0000000..8c44a71 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h @@ -0,0 +1,14126 @@ +/** + * @file + * + * SMU firmware + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 65874 $ @e $Date: 2012-02-26 21:24:59 -0600 (Sun, 26 Feb 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _GNBSMUFIRMWARETN_H_ +#define _GNBSMUFIRMWARETN_H_ + +UINT32 FirmwareTN[] = { + 0x000a0004, + 0x00000040, + 0x000036a1, + 0x00010100, + 0xeee2b111, + 0x724cbe84, + 0xf7cde4cd, + 0xbf04e85e, + 0x9bdebdfc, + 0x0001d7f4, + 0x0001d904, + 0x00000000, + 0x0001d925, + 0x0001d934, + 0x0001d848, + 0x0001da6c, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xaa55aa55, + 0x98000000, + 0x98000000, + 0xd0000000, + 0x78010001, + 0x38210100, + 0xd0e10000, + 0xd1210000, + 0xf8000039, + 0x5b9d0000, + 0xf8000062, + 0xf80033ff, + 0xe0000098, + 0x34000000, + 0x34000000, + 0x34000000, + 0x34000000, + 0x5b9d0000, + 0x37de0004, + 0xf8000044, + 0xf8003456, + 0xe000007d, + 0x34000000, + 0x34000000, + 0x34000000, + 0x5b9d0000, + 0xf8000052, + 0xf800344e, + 0xe0000088, + 0x34000000, + 0x34000000, + 0x34000000, + 0x34000000, + 0x5b9d0000, + 0x37de0004, + 0xf8000034, + 0xf8003458, + 0xe000006d, + 0x34000000, + 0x34000000, + 0x34000000, + 0x5b9d0000, + 0x37de0004, + 0xf800002c, + 0xf8003462, + 0xe0000065, + 0x34000000, + 0x34000000, + 0x34000000, + 0x5b9d0000, + 0xf8000025, + 0x34010002, + 0xf8003476, + 0xe000005d, + 0x34000000, + 0x34000000, + 0x34000000, + 0x5b9d0000, + 0x37de0004, + 0xf800001c, + 0xf8003464, + 0xe0000055, + 0x34000000, + 0x34000000, + 0x34000000, + 0x98000000, + 0x781c0001, + 0x3b9cebfc, + 0x781a0002, + 0x3b5a5b80, + 0x78010001, + 0x3821db84, + 0x78030001, + 0x3863e038, + 0x44230004, + 0x58200000, + 0x34210004, + 0xe3fffffd, + 0x34010000, + 0x34020000, + 0x78030001, + 0x3863fe80, + 0x58610000, + 0x58610018, + 0x34030000, + 0xf80002b5, + 0xf800013d, + 0x379cff80, + 0x5b810004, + 0x5b820008, + 0x5b83000c, + 0x5b840010, + 0x5b850014, + 0x5b860018, + 0x5b87001c, + 0x5b880020, + 0x5b890024, + 0x5b8a0028, + 0x5b9e0078, + 0x5b9f007c, + 0x2b810080, + 0x5b810074, + 0xbb800800, + 0x34210080, + 0x5b810070, + 0x98210800, + 0xd0010000, + 0xc3a00000, + 0x379cff80, + 0x5b810004, + 0x5b820008, + 0x5b83000c, + 0x5b840010, + 0x5b850014, + 0x5b860018, + 0x5b87001c, + 0x5b880020, + 0x5b890024, + 0x5b8a0028, + 0x5b8b002c, + 0x5b8c0030, + 0x5b8d0034, + 0x5b8e0038, + 0x5b8f003c, + 0x5b900040, + 0x5b910044, + 0x5b920048, + 0x5b93004c, + 0x5b940050, + 0x5b950054, + 0x5b960058, + 0x5b97005c, + 0x5b980060, + 0x5b990064, + 0x5b9a0068, + 0x5b9b006c, + 0x5b9e0078, + 0x5b9f007c, + 0x2b810080, + 0x5b810074, + 0xbb800800, + 0x34210080, + 0x5b810070, + 0x98210800, + 0xd0010000, + 0xc3a00000, + 0x34010002, + 0xd0010000, + 0x2b810004, + 0x2b820008, + 0x2b83000c, + 0x2b840010, + 0x2b850014, + 0x2b860018, + 0x2b87001c, + 0x2b880020, + 0x2b890024, + 0x2b8a0028, + 0x2b9d0074, + 0x2b9e0078, + 0x2b9f007c, + 0x2b9c0070, + 0x34000000, + 0xc3c00000, + 0x34010002, + 0xd0010000, + 0x2b810004, + 0x2b820008, + 0x2b83000c, + 0x2b840010, + 0x2b850014, + 0x2b860018, + 0x2b87001c, + 0x2b880020, + 0x2b890024, + 0x2b8a0028, + 0x2b8b002c, + 0x2b8c0030, + 0x2b8d0034, + 0x2b8e0038, + 0x2b8f003c, + 0x2b900040, + 0x2b910044, + 0x2b920048, + 0x2b93004c, + 0x2b940050, + 0x2b950054, + 0x2b960058, + 0x2b97005c, + 0x2b980060, + 0x2b990064, + 0x2b9a0068, + 0x2b9b006c, + 0x2b9d0074, + 0x2b9e0078, + 0x2b9f007c, + 0x2b9c0070, + 0x34000000, + 0xc3e00000, + 0x379cfffc, + 0x5b9d0004, + 0xf80000cc, + 0x2b9d0004, + 0x379c0004, + 0xc3a00000, + 0x379cfffc, + 0x5b9d0004, + 0xf80000cd, + 0x2b9d0004, + 0x379c0004, + 0xc3a00000, + 0x379cfff4, + 0x5b8b000c, + 0x5b8c0008, + 0x5b9d0004, + 0x780c0001, + 0xb9801000, + 0x3842db84, + 0x34010001, + 0x58410000, + 0x90201000, + 0x90401800, + 0x340b0001, + 0xa0621800, + 0x34050000, + 0x44650018, + 0x78020001, + 0x3842db8c, + 0xb8402000, + 0xa1630800, + 0x44200009, + 0x28430000, + 0x5c60000c, + 0x90201000, + 0xa5600800, + 0xa0411000, + 0xd0220000, + 0xd04b0000, + 0xe3ffffee, + 0x3d6b0001, + 0x34a50001, + 0x34840008, + 0x34420008, + 0xe3fffff2, + 0x28820004, + 0xb8a00800, + 0xd8600000, + 0xd04b0000, + 0xe3ffffe4, + 0x398cdb84, + 0x34010000, + 0x59810000, + 0x2b8b000c, + 0x2b8c0008, + 0x2b9d0004, + 0x379c000c, + 0xc3a00000, + 0x78020001, + 0x3842db88, + 0x28440000, + 0x5c80000f, + 0x34010001, + 0x58410000, + 0x78030001, + 0xb8801000, + 0x3863db8c, + 0x3401001f, + 0x58620000, + 0x58620004, + 0x3421ffff, + 0x34630008, + 0x4c20fffc, + 0x90000800, + 0x38210001, + 0xd0010000, + 0xc3a00000, + 0x379cfff0, + 0x5b8b0010, + 0x5b8c000c, + 0x5b8d0008, + 0x5b9d0004, + 0xb8205800, + 0xb8406800, + 0xb8606000, + 0xfbffffe5, + 0x34010001, + 0xbc2b2000, + 0x3402fffe, + 0x3401001f, + 0x502b0002, + 0xe0000019, + 0x90001800, + 0x3401fffe, + 0xa0611800, + 0xd0030000, + 0x78010001, + 0x3d620003, + 0x3821db8c, + 0xb4411000, + 0x584d0004, + 0x584c0000, + 0x90200800, + 0xa4801000, + 0x5d800003, + 0xa0220800, + 0xe0000002, + 0xb8240800, + 0xd0210000, + 0x78010001, + 0x3821db84, + 0x28210000, + 0x38630001, + 0x5c200002, + 0xd0030000, + 0x34020000, + 0xb8400800, + 0x2b8b0010, + 0x2b8c000c, + 0x2b8d0008, + 0x2b9d0004, + 0x379c0010, + 0xc3a00000, + 0x34020001, + 0xbc411000, + 0x3403fffe, + 0xa4402000, + 0x3402001f, + 0x50410002, + 0xe000000f, + 0x90001000, + 0x3401fffe, + 0xa0411000, + 0xd0020000, + 0x90200800, + 0xa0240800, + 0xd0210000, + 0x78010001, + 0x3821db84, + 0x28210000, + 0x38420001, + 0x5c200002, + 0xd0020000, + 0x34030000, + 0xb8600800, + 0xc3a00000, + 0x379cfff8, + 0x5b8b0008, + 0x5b9d0004, + 0xb8205800, + 0xfbffffa4, + 0x34010001, + 0xbc2b1800, + 0x3402fffe, + 0x3401001f, + 0x502b0002, + 0xe000000f, + 0x90001000, + 0x3401fffe, + 0xa0411000, + 0xd0020000, + 0x90200800, + 0xb8230800, + 0xd0210000, + 0x78010001, + 0x3821db84, + 0x28210000, + 0x38420001, + 0x5c200002, + 0xd0020000, + 0x34020000, + 0xb8400800, + 0x2b8b0008, + 0x2b9d0004, + 0x379c0008, + 0xc3a00000, + 0x379cfff8, + 0x5b8b0008, + 0x5b9d0004, + 0xb8205800, + 0xfbffff86, + 0x90001000, + 0x3401fffe, + 0xa0411000, + 0xd0020000, + 0xd02b0000, + 0x78010001, + 0x3821db84, + 0x28210000, + 0x38420001, + 0x5c200002, + 0xd0020000, + 0x2b8b0008, + 0x2b9d0004, + 0x379c0008, + 0xc3a00000, + 0x90000800, + 0x3402fffe, + 0xa0220800, + 0xd0010000, + 0x90200800, + 0x34020000, + 0xd0220000, + 0xc3a00000, + 0x34080001, + 0xac000007, + 0x34010001, + 0xd0810000, + 0x34000000, + 0x34000000, + 0x34000000, + 0x34000000, + 0xc3a00000, + 0x34010001, + 0xd0610000, + 0x34000000, + 0x34000000, + 0x34000000, + 0x34000000, + 0xc3a00000, + 0xc3a00000, + 0x78038000, + 0x78018000, + 0x38630000, + 0x38210040, + 0x58610180, + 0x34010000, + 0x58610100, + 0x78014000, + 0x34020001, + 0x58620104, + 0x38210003, + 0x5861010c, + 0x34010003, + 0x5861010c, + 0x34010002, + 0x58610110, + 0x34010004, + 0x5861000c, + 0x28610004, + 0x38210002, + 0x58610004, + 0xc3a00000, + 0x379cffe8, + 0x5b8b0018, + 0x5b8c0014, + 0x5b8d0010, + 0x5b8e000c, + 0x5b8f0008, + 0x5b9d0004, + 0x7805e000, + 0xb8a00800, + 0x38211000, + 0x28210004, + 0x780d0001, + 0x780c0001, + 0x202101fc, + 0x00220002, + 0x780b0001, + 0x780e0001, + 0x780f0001, + 0x78040001, + 0x74410007, + 0x39add848, + 0x398cd7f4, + 0x396bd925, + 0x39ced904, + 0x39eff160, + 0x3884e02c, + 0x5c200003, + 0x34022000, + 0xe0000014, + 0x7441003f, + 0x5c200003, + 0x3c42000a, + 0xe0000010, + 0x7441005f, + 0x5c200006, + 0x3c42000b, + 0x7801ffff, + 0x38210000, + 0xb4411000, + 0xe0000009, + 0x3c41000c, + 0x7443007e, + 0x7802fffc, + 0x38420000, + 0xb4221000, + 0x44600003, + 0x78020008, + 0x38420000, + 0x7801e000, + 0x38213048, + 0x58220000, + 0x7801e000, + 0x58820000, + 0x38212000, + 0x28210000, + 0x2021007f, + 0xb8201000, + 0x5c200007, + 0x38a51000, + 0x28a20004, + 0x78010003, + 0x3821f800, + 0xa0411000, + 0x0042000b, + 0xb8400800, + 0xf80029f4, + 0x7801e000, + 0x38211000, + 0x283d001c, + 0x7802e000, + 0x38422208, + 0x28410000, + 0x78090001, + 0x78030001, + 0x38210001, + 0x58410000, + 0x3929f000, + 0x3863ffff, + 0x340a0000, + 0x592a0000, + 0x35290004, + 0x55230002, + 0xe3fffffd, + 0x78020001, + 0x78018000, + 0x3842f15c, + 0x38210000, + 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0xb5470800, + 0x28210000, + 0xd8200000, + 0x78018001, + 0x38210000, + 0x28210058, + 0xe3ffff99, + 0xb9a01800, + 0x3863e028, + 0x40610000, + 0x34040001, + 0x3422ffff, + 0x202100ff, + 0x50810008, + 0x30620000, + 0x2b8b0010, + 0x2b8c000c, + 0x2b8d0008, + 0x2b9d0004, + 0x379c0010, + 0xc3a00000, + 0x30620000, + 0x204100ff, + 0x5c20ff7f, + 0x78018000, + 0x38210000, + 0x58240008, + 0x34000000, + 0x34000000, + 0x34000000, + 0x34000000, + 0x34000000, + 0xe3ffff76, + 0x78060001, + 0x38c6f1a0, + 0x78050001, + 0x38a5d7f4, + 0x30c1000b, + 0x28a70028, + 0xb8202000, + 0x34080000, + 0x34030003, + 0x48e30009, + 0x28a10038, + 0x34220060, + 0x40410003, + 0x3442ffe0, + 0x5c200010, + 0x3463ffff, + 0x48e30002, + 0xe3fffffb, + 0x28a10010, + 0x4501000f, + 0x7c810010, + 0x5c20000b, + 0x40c10002, + 0x34020000, + 0x30c10008, + 0x40c10000, + 0x30c10009, + 0x78010001, + 0x3821db7c, + 0xe000000c, + 0xb8604000, + 0xe3fffff3, + 0x7c810020, + 0x5c20001a, + 0x40c10003, + 0x34020001, + 0x30c10008, + 0x40c10001, + 0x30c10009, + 0x78010001, + 0x3821db7c, + 0x7804e000, + 0x30220000, + 0x38842018, + 0x28820000, + 0x40c10008, + 0x3405ff80, + 0xa0451000, + 0x2021007f, + 0xb8411000, + 0x7803e000, + 0x58820000, + 0x38632010, + 0x40c20009, + 0x28610000, + 0x2042007f, + 0xa0250800, + 0xb8220800, + 0x58610000, + 0xc3a00000, + 0x379cfffc, + 0x5b9d0004, + 0x78010001, + 0x3821f150, + 0x40210002, + 0x78028000, + 0x78038008, + 0x78040001, + 0x38420010, + 0x38630000, + 0x3884f1a0, + 0x4420000a, + 0x28420000, + 0x34010000, + 0x58610220, + 0x4083000a, + 0x20420030, + 0xb8400800, + 0x3082000b, + 0x44430002, + 0xfbffffb0, + 0x2b9d0004, + 0x379c0004, + 0xc3a00000, + 0x379cfff4, + 0x5b8b000c, + 0x5b8c0008, + 0x5b9d0004, + 0xfbffd231, + 0xb8206000, + 0x780b0001, + 0xfbffd232, + 0x396bf1a0, + 0x41620007, + 0x78030001, + 0x3863db7c, + 0x3022000f, + 0x78010001, + 0x3182000f, + 0x3821f150, + 0x40210002, + 0x34020010, + 0x44200007, + 0x40610000, + 0x7c210001, + 0x5c200002, + 0x34020020, + 0xb8400800, + 0xfbffff94, + 0x2b8b000c, + 0x2b8c0008, + 0x2b9d0004, + 0x379c000c, + 0xc3a00000, + 0xc3a00000, + 0xc3a00000, + 0xc3a00000, + 0x01300000, + 0x01310000, + 0x01310000, + 0x01320000, + 0x01330000, + 0x01100000, + 0x01110000, + 0x02110000, + 0x01120000, + 0x01130000, + 0x01200000, + 0x01210000, + 0x02210000, + 0x01220000, + 0x01230000, + 0x00000100, + 0x00000000, + 0x000a0003, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000007, + 0x0001f000, + 0x0001f000, + 0x0001f000, + 0x000113dc, + 0x00011318, + 0x01010101, + 0x01010101, + 0x7fff0000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x000a0003, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000007, + 0x0001f200, + 0x0001f200, + 0x0001f200, + 0x00011bf8, + 0x00011b58, + 0x0001f8f0, + 0x00015000, + 0x0001420c, + 0x00010e64, + 0x00011928, + 0x0001b748, + 0x0001b8dc, + 0x00000000, + 0x00017510, + 0x000156bc, + 0x00015d18, + 0x00016528, + 0x000169d0, + 0x00016e2c, + 0x000174d0, + 0x00012f3c, + 0x0001d6d4, + 0x0000ea60, + 0x00004e20, + 0x64000000, + 0x000186a0, + 0x0001f480, + 0x80402010, + 0x08040200, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x01010000, + 0x01000100, + 0x00000000, + 0x00000000, + 0x01010101, + 0x00000000, + 0x00000000, + 0x00000000, + 0x0001f120, + 0x00000000, + 0x04000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00003178, + 0x00000000, + 0x00003171, + 0x00000000, + 0x00003172, + 0x00000000, + 0x00007103, + 0x00000000, + 0x00007116, + 0x00000000, + 0x0000317d, + 0x00000000, + 0x00007103, + 0x00000000, + 0x0000712e, + 0x00000000, + 0x0000710f, + 0x00000000, + 0x00007110, + 0x00000000, + 0x00007111, + 0x00000000, + 0x00007112, + 0x00000000, + 0x00007113, + 0x00000000, + 0x0000715c, + 0x00000000, + 0x0000715d, + 0x00000000, + 0x00007162, + 0x00000000, + 0x00007117, + 0x00000000, + 0x00007157, + 0x00000000, + 0x00007106, + 0x00000000, + 0x0001ab20, + 0x00010788, + 0x0001a8d8, + 0x00019fec, + 0x0001a4a0, + 0x00019a00, + 0x0001a450, + 0x000199b4, + 0x0001a420, + 0x00011d94, + 0x00010418, + 0x00010430, + 0x00013138, + 0x00013d5c, + 0x00012398, + 0x00015970, + 0x0001244c, + 0x0001bb5c, + 0x0001b864, + 0x00012c48, + 0x00012300, + 0x00012354, + 0x00016834, + 0x00012530, + 0x00016e2c, + 0x0001a984, + 0x0001396c, + 0x0001aa60, + 0x00011e80, + 0x0001d380, + 0x00011bf8, + 0x00011b58, + 0x00014c0c, + 0x00014e28, + 0x0001a704, + 0x00019d34, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x0001c1a8, + 0x0001c1e0, + 0x00012f3c, + 0x0001724c, + 0x0001aab8, + 0x00010788, + 0x00010788, + 0x00010788, + 0x0001af7c, + 0x00010788, + 0x00010788, + 0x00010788, + 0x0001adb4, + 0x00012f34, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x0001d7ac, + 0x0001d7b0, + 0x00010788, + 0x000121b8, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00013340, + 0x0001420c, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00010788, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c new file mode 100644 index 0000000..75f8c9c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c @@ -0,0 +1,1121 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbTable.h" +#include "GnbRegistersTN.h" +#include "GnbInitTN.h" +#include "cpuFamRegisters.h" +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T A B L E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +GNB_TABLE ROMDATA GnbEarlierInitTableBeforeSmuTN [] = { + GNB_ENTRY_RMW ( + D0F0x98_x07_TYPE, + D0F0x98_x07_ADDRESS, + D0F0x98_x07_SMUCsrIsocEn_MASK, + (1 << D0F0x98_x07_SMUCsrIsocEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0x98_x1E_TYPE, + D0F0x98_x1E_ADDRESS, + D0F0x98_x1E_HiPriEn_MASK, + (1 << D0F0x98_x1E_HiPriEn_OFFSET) + ), + + GNB_ENTRY_TERMINATE +}; + +GNB_TABLE ROMDATA GnbEarlierInitTableAfterSmuTN [] = { + // Config GFX to legacy mode initially + GNB_ENTRY_RMW ( + D0F0x64_x1D_TYPE, + D0F0x64_x1D_ADDRESS, + D0F0x64_x1D_IntGfxAsPcieEn_MASK, + 0 + ), + GNB_ENTRY_REV_RMW ( + 0x0000000000000100ull , + D0F0xBC_x1F87C_TYPE, + D0F0xBC_x1F87C_ADDRESS, + D0F0xBC_x1F87C_LL_PCIE_LoadStep_MASK | D0F0xBC_x1F87C_LL_VddNbLoadStepBase_MASK, + 0 + ), + GNB_ENTRY_REV_RMW ( + 0x0000000000000100ull , + D0F0xBC_x1F880_TYPE, + D0F0xBC_x1F880_ADDRESS, + D0F0xBC_x1F880_LL_VCE_LoadStep_MASK | D0F0xBC_x1F880_LL_UVD_LoadStep_MASK, + 0 + ), + GNB_ENTRY_REV_RMW ( + 0x0000000000000100ull , + D0F0xBC_x1F884_TYPE, + D0F0xBC_x1F884_ADDRESS, + D0F0xBC_x1F884_LL_DCE2_LoadStep_MASK | D0F0xBC_x1F884_LL_DCE_LoadStep_MASK, + 0 + ), + GNB_ENTRY_REV_RMW ( + 0x0000000000000100ull , + D0F0xBC_x1F888_TYPE, + D0F0xBC_x1F888_ADDRESS, + D0F0xBC_x1F888_LL_GPU_LoadStep_MASK, + 0 + ), + // Configure load line VID + GNB_ENTRY_WR ( + D0F0xBC_x1F3D8_TYPE, + D0F0xBC_x1F3D8_ADDRESS, + (0x00 << D0F0xBC_x1F3D8_LoadLineTrim3_OFFSET) | + (0xFE << D0F0xBC_x1F3D8_LoadLineTrim2_OFFSET) | + (0xFC << D0F0xBC_x1F3D8_LoadLineTrim1_OFFSET) | + (0xF6 << D0F0xBC_x1F3D8_LoadLineTrim0_OFFSET) + ), + GNB_ENTRY_WR ( + D0F0xBC_x1F3DC_TYPE, + D0F0xBC_x1F3DC_ADDRESS, + (0x08 << D0F0xBC_x1F3DC_LoadLineTrim7_OFFSET) | + (0x06 << D0F0xBC_x1F3DC_LoadLineTrim6_OFFSET) | + (0x04 << D0F0xBC_x1F3DC_LoadLineTrim5_OFFSET) | + (0x02 << D0F0xBC_x1F3DC_LoadLineTrim4_OFFSET) + ), + GNB_ENTRY_WR ( + D0F0xBC_x1F404_TYPE, + D0F0xBC_x1F404_ADDRESS, + (0x19 << D0F0xBC_x1F404_LoadLineOffset3_OFFSET) | + (0x00 << D0F0xBC_x1F404_LoadLineOffset2_OFFSET) | + (0xE7 << D0F0xBC_x1F404_LoadLineOffset1_OFFSET) | + (0x00 << D0F0xBC_x1F404_LoadLineOffset0_OFFSET) + ), + GNB_ENTRY_COPY ( + D0F0xBC_x1F3F8_TYPE, + D0F0xBC_x1F3F8_ADDRESS, + D0F0xBC_x1F3F8_SviInitLoadLineVdd_OFFSET, D0F0xBC_x1F3F8_SviInitLoadLineVdd_WIDTH, + D0F0xBC_xE01040A8_TYPE, + D0F0xBC_xE01040A8_ADDRESS, + D0F0xBC_xE01040A8_SviLoadLineVdd_OFFSET, D0F0xBC_xE01040A8_SviLoadLineVdd_WIDTH + ), + GNB_ENTRY_COPY ( + D0F0xBC_x1F3F8_TYPE, + D0F0xBC_x1F3F8_ADDRESS, + D0F0xBC_x1F3F8_SviInitLoadLineVddNB_OFFSET, D0F0xBC_x1F3F8_SviInitLoadLineVddNB_WIDTH, + D0F0xBC_xE01040A8_TYPE, + D0F0xBC_xE01040A8_ADDRESS, + D0F0xBC_xE01040A8_SviLoadLineVddNb_OFFSET, D0F0xBC_xE01040A8_SviLoadLineVddNb_WIDTH + ), + GNB_ENTRY_COPY ( + D0F0xBC_x1F3F8_TYPE, + D0F0xBC_x1F3F8_ADDRESS, + D0F0xBC_x1F3F8_SviTrimValueVdd_OFFSET, D0F0xBC_x1F3F8_SviTrimValueVdd_WIDTH, + D0F0xBC_xE0104184_TYPE, + D0F0xBC_xE0104184_ADDRESS, + D0F0xBC_xE0104184_SviLoadLineTrimVdd_OFFSET, D0F0xBC_xE0104184_SviLoadLineTrimVdd_WIDTH + ), + GNB_ENTRY_COPY ( + D18F5x12C_TYPE, + D18F5x12C_ADDRESS, + D18F5x12C_CoreLoadLineTrim_OFFSET, D18F5x12C_CoreLoadLineTrim_WIDTH, + D0F0xBC_xE0104184_TYPE, + D0F0xBC_xE0104184_ADDRESS, + D0F0xBC_xE0104184_SviLoadLineTrimVdd_OFFSET, D0F0xBC_xE0104184_SviLoadLineTrimVdd_WIDTH + ), + GNB_ENTRY_COPY ( + D0F0xBC_x1F3F8_TYPE, + D0F0xBC_x1F3F8_ADDRESS, + D0F0xBC_x1F3F8_SviTrimValueVddNB_OFFSET, D0F0xBC_x1F3F8_SviTrimValueVddNB_WIDTH, + D0F0xBC_xE0104184_TYPE, + D0F0xBC_xE0104184_ADDRESS, + D0F0xBC_xE0104184_SviLoadLineTrimVddNb_OFFSET, D0F0xBC_xE0104184_SviLoadLineTrimVddNb_WIDTH + ), + GNB_ENTRY_COPY ( + D18F5x188_TYPE, + D18F5x188_ADDRESS, + D18F5x188_NbLoadLineTrim_OFFSET, D18F5x188_NbLoadLineTrim_WIDTH, + D0F0xBC_xE0104184_TYPE, + D0F0xBC_xE0104184_ADDRESS, + D0F0xBC_xE0104184_SviLoadLineTrimVddNb_OFFSET, D0F0xBC_xE0104184_SviLoadLineTrimVddNb_WIDTH + ), + GNB_ENTRY_RMW ( + D0F0xBC_x1F3FC_TYPE, + D0F0xBC_x1F3FC_ADDRESS, + D0F0xBC_x1F3FC_SviVidStepBase_MASK | D0F0xBC_x1F3FC_SviVidStep_MASK, + (0x1838 << D0F0xBC_x1F3FC_SviVidStepBase_OFFSET) | (0x19 << D0F0xBC_x1F3FC_SviVidStep_OFFSET) + ), + GNB_ENTRY_COPY ( + D0F0xBC_x1F400_TYPE, + D0F0xBC_x1F400_ADDRESS, + D0F0xBC_x1F400_SviLoadLineOffsetVdd_OFFSET, D0F0xBC_x1F400_SviLoadLineOffsetVdd_WIDTH, + D0F0xBC_xE0104184_TYPE, + D0F0xBC_xE0104184_ADDRESS, + D0F0xBC_xE0104184_SviLoadLineOffsetVdd_OFFSET, D0F0xBC_xE0104184_SviLoadLineOffsetVdd_WIDTH + ), + GNB_ENTRY_COPY ( + D18F5x12C_TYPE, + D18F5x12C_ADDRESS, + D18F5x12C_CoreOffsetTrim_OFFSET, D18F5x12C_CoreOffsetTrim_WIDTH, + D0F0xBC_xE0104184_TYPE, + D0F0xBC_xE0104184_ADDRESS, + D0F0xBC_xE0104184_SviLoadLineOffsetVdd_OFFSET, D0F0xBC_xE0104184_SviLoadLineOffsetVdd_WIDTH + ), + GNB_ENTRY_COPY ( + D0F0xBC_x1F400_TYPE, + D0F0xBC_x1F400_ADDRESS, + D0F0xBC_x1F400_SviLoadLineOffsetVddNB_OFFSET, D0F0xBC_x1F400_SviLoadLineOffsetVddNB_WIDTH, + D0F0xBC_xE0104184_TYPE, + D0F0xBC_xE0104184_ADDRESS, + D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_OFFSET, D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_WIDTH + ), + GNB_ENTRY_REV_RMW ( + 0x0000000000000100ull , + D0F0xBC_x1F400_TYPE, + D0F0xBC_x1F400_ADDRESS, + D0F0xBC_x1F400_SviLoadLineOffsetVddNB_MASK | D0F0xBC_x1F400_SviLoadLineOffsetVdd_MASK, + (2 << D0F0xBC_x1F400_SviLoadLineOffsetVddNB_OFFSET) | (2 << D0F0xBC_x1F400_SviLoadLineOffsetVdd_OFFSET) + ), +// GNB_ENTRY_COPY ( +// D18F5x188_TYPE, +// D18F5x188_ADDRESS, +// D18F5x188_NbOffsetTrim_OFFSET, D18F5x188_NbOffsetTrim_WIDTH, +// D0F0xBC_xE0104184_TYPE, +// D0F0xBC_xE0104184_ADDRESS, +// D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_OFFSET, D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_WIDTH +// ), + GNB_ENTRY_REV_RMW ( + 0x0000000000000100ull , + D18F5x188_TYPE, + D18F5x188_ADDRESS, + D18F5x188_NbLoadLineTrim_MASK,// | D18F5x188_NbOffsetTrim_MASK, + (3 << D18F5x188_NbLoadLineTrim_OFFSET)// | (2 << D18F5x188_NbOffsetTrim_OFFSET) + ), + GNB_ENTRY_REV_RMW ( + 0x0000000000000100ull , + D18F5x12C_TYPE, + D18F5x12C_ADDRESS, + D18F5x12C_CoreLoadLineTrim_MASK | D18F5x12C_CoreOffsetTrim_MASK, + (3 << D18F5x12C_CoreLoadLineTrim_OFFSET) | (2 << D18F5x12C_CoreOffsetTrim_OFFSET) + ), + GNB_ENTRY_REV_RMW ( + 0x0000000000000100ull , + D0F0xBC_x1F3F8_TYPE, + D0F0xBC_x1F3F8_ADDRESS, + D0F0xBC_x1F3F8_SviTrimValueVdd_MASK | D0F0xBC_x1F3F8_SviTrimValueVddNB_MASK, + (3 << D0F0xBC_x1F3F8_SviTrimValueVdd_OFFSET) | (3 << D0F0xBC_x1F3F8_SviTrimValueVddNB_OFFSET) + ), + // Enable SVI2 + GNB_ENTRY_RMW ( + D0F0xBC_x1F428_TYPE, + D0F0xBC_x1F428_ADDRESS, + D0F0xBC_x1F428_SviMode_MASK, + (1 << D0F0xBC_x1F428_SviMode_OFFSET) + ), + GNB_ENTRY_TERMINATE +}; + +GNB_TABLE ROMDATA GnbEarlyInitTableTN [] = { + GNB_ENTRY_WR ( + D0F0x04_TYPE, + D0F0x04_ADDRESS, + (0x1 << D0F0x04_MemAccessEn_OFFSET) | (0x1 << D0F0x04_BusMasterEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0x4C_TYPE, + D0F0x4C_ADDRESS, + D0F0x4C_CfgRdTime_MASK, + 0x2 << D0F0x4C_CfgRdTime_OFFSET + ), + GNB_ENTRY_RMW ( + D0F0x84_TYPE, + D0F0x84_ADDRESS, + D0F0x84_Ev6Mode_MASK, + 0x1 << D0F0x84_Ev6Mode_OFFSET + ), + GNB_ENTRY_RMW ( + D0F0x64_x46_TYPE, + D0F0x64_x46_ADDRESS, + 0x6 , + 1 << D0F0x64_x46_Msi64bitEn_OFFSET + ), + GNB_ENTRY_RMW ( + D0F0x98_x0C_TYPE, + D0F0x98_x0C_ADDRESS, + D0F0x98_x0C_StrictSelWinnerEn_MASK, + 1 << D0F0x98_x0C_StrictSelWinnerEn_OFFSET + ), + // Configure PM timer + GNB_ENTRY_RMW ( + D0F0xBC_x1F468_TYPE, + D0F0xBC_x1F468_ADDRESS, + D0F0xBC_x1F468_TimerPeriod_MASK, + D0F0xBC_x1F468_TimerPeriod_Value << D0F0xBC_x1F468_TimerPeriod_OFFSET + ), + GNB_ENTRY_WR ( + SMU_MSG_TYPE, + SMC_MSG_EN_PM_CNTL, + 0 + ), + //Enable voltage controller + GNB_ENTRY_RMW ( + D0F0xBC_x1F460_TYPE, + D0F0xBC_x1F460_ADDRESS, + D0F0xBC_x1F460_VoltageCntl_MASK, + 1 << D0F0xBC_x1F460_VoltageCntl_OFFSET + ), + GNB_ENTRY_COPY ( + D0F0xBC_x1F384_TYPE, + D0F0xBC_x1F384_ADDRESS, + D0F0xBC_x1F384_FirmwareVid_OFFSET, + D0F0xBC_x1F384_FirmwareVid_WIDTH, + D0F0xBC_xE0001008_TYPE , + D0F0xBC_xE0001008_ADDRESS, + D0F0xBC_xE0001008_SClkVid0_OFFSET, + D0F0xBC_xE0001008_SClkVid0_WIDTH + ), + GNB_ENTRY_WR ( + SMU_MSG_TYPE, + SMC_MSG_CONFIG_VOLTAGE_CNTL, + 0 + ), + GNB_ENTRY_POLL ( + GMMx7B0_TYPE, + GMMx7B0_ADDRESS, + GMMx7B0_SMU_VOLTAGE_EN_MASK, + 0x1 << GMMx7B0_SMU_VOLTAGE_EN_OFFSET + ), + // Enable thermal controller + GNB_ENTRY_RMW ( + D0F0xBC_x1F460_TYPE, + D0F0xBC_x1F460_ADDRESS, + D0F0xBC_x1F460_ThermalCntl_MASK, + 30 << D0F0xBC_x1F460_ThermalCntl_OFFSET + ), + GNB_ENTRY_RMW ( + D0F0xBC_x1F388_TYPE, + D0F0xBC_x1F388_ADDRESS, + D0F0xBC_x1F388_CsrAddr_MASK | D0F0xBC_x1F388_TcenId_MASK, + (0x9 << D0F0xBC_x1F388_CsrAddr_OFFSET) | (0xE << D0F0xBC_x1F388_TcenId_OFFSET) + ), + GNB_ENTRY_WR ( + SMU_MSG_TYPE, + SMC_MSG_CONFIG_THERMAL_CNTL, + 0 + ), + GNB_ENTRY_COPY ( + D0F0xBC_x1F400_TYPE, + D0F0xBC_x1F400_ADDRESS, + D0F0xBC_x1F400_PstateMax_OFFSET, + D0F0xBC_x1F400_PstateMax_WIDTH, + TYPE_D18F3 , + 0xdc , + 8 , + 3 + ), + // Configure VPC + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_BAPM, + D0F0xBC_x1F428_TYPE, + D0F0xBC_x1F428_ADDRESS, + D0F0xBC_x1F428_EnableVpcAccumulators_MASK, + (1 << D0F0xBC_x1F428_EnableVpcAccumulators_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0xBC_x1F428_TYPE, + D0F0xBC_x1F428_ADDRESS, + D0F0xBC_x1F428_PstateAllCpusIdle_MASK | D0F0xBC_x1F428_NbPstateAllCpusIdle_MASK, + (1 << D0F0xBC_x1F428_NbPstateAllCpusIdle_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0xBC_x1F46C_TYPE, + D0F0xBC_x1F46C_ADDRESS, + D0F0xBC_x1F46C_VpcPeriod_MASK, + (0x1B58 << D0F0xBC_x1F46C_VpcPeriod_OFFSET) + ), + + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_BAPM, + SMU_MSG_TYPE, + SMC_MSG_CONFIG_VPC_ACCUMULATOR, + 0 + ), + // Enable TDC + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_BAPM, + D0F0xBC_x1F428_TYPE, + D0F0xBC_x1F428_ADDRESS, + D0F0xBC_x1F428_EnableTdcLimit_MASK, + (1 << D0F0xBC_x1F428_EnableTdcLimit_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0xBC_x1F638_TYPE, + D0F0xBC_x1F638_ADDRESS, + D0F0xBC_x1F638_TdcPeriod_MASK, + (0x1 << D0F0xBC_x1F638_TdcPeriod_OFFSET) + ), + + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_BAPM, + SMU_MSG_TYPE, + SMC_MSG_CONFIG_TDC_LIMIT, + 0 + ), + + // Enable LPMx + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_BAPM, + D0F0xBC_x1F428_TYPE, + D0F0xBC_x1F428_ADDRESS, + D0F0xBC_x1F428_EnableLpmx_MASK, + (1 << D0F0xBC_x1F428_EnableLpmx_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0xBC_x1F46C_TYPE, + D0F0xBC_x1F46C_ADDRESS, + D0F0xBC_x1F46C_LpmxPeriod_MASK, + (1 << D0F0xBC_x1F46C_LpmxPeriod_OFFSET) + ), + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_BAPM, + SMU_MSG_TYPE, + SMC_MSG_CONFIG_LPMx, + 0 + ), + // Enable BAPM + GNB_ENTRY_RMW ( + D0F0xBC_x1F428_TYPE, + D0F0xBC_x1F428_ADDRESS, + D0F0xBC_x1F428_BapmCoeffOverride_MASK, + (0x1 << D0F0xBC_x1F428_BapmCoeffOverride_OFFSET) + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_BAPM, + D0F0xBC_x1F428_TYPE, + D0F0xBC_x1F428_ADDRESS, + D0F0xBC_x1F428_EnableBapm_MASK, + (1 << D0F0xBC_x1F428_EnableBapm_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0xBC_x1F46C_TYPE, + D0F0xBC_x1F46C_ADDRESS, + D0F0xBC_x1F46C_BapmPeriod_MASK, + (D0F0xBC_x1F46C_BapmPeriod_Value << D0F0xBC_x1F46C_BapmPeriod_OFFSET) + ), + // Config BAPM + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_BAPM, + SMU_MSG_TYPE, + SMC_MSG_CONFIG_BAPM, + 0 + ), + GNB_ENTRY_TERMINATE +}; + +GNB_TABLE ROMDATA GnbEnvInitTableTN [] = { +//--------------------------------------------------------------------------- +// ORB Init +//D0F0x98_x07[IocBwOptEn] +//D0F0x98_x07[DropZeroMaskWrEn] +//D0F0x98_x28[ForceCoherentIntr] = 1 +//D0F0x98_x07[UnadjustThrottlingStpclk ] = 1 +//D0F0x98_x07[MSIHTIntConversionEn] = 0 +//D0F0x98_x07[IommuBwOptEn] = 1 +//D0F0x98_x07[IommuIsocPassPWMode] = 1 +//D0F0x98_x08[NpWrrLenC] = 1 +//D0F0x98_x28[ForceCoherentIntr] = 1 +//D0F0x98_x2C[NBOutbWakeMask] = 1 +//D0F0x98_x2C[OrbRxIdlesMask] = 1 + + GNB_ENTRY_RMW ( + D0F0x98_x07_TYPE, + D0F0x98_x07_ADDRESS, + D0F0x98_x07_UnadjustThrottlingStpclk_MASK | D0F0x98_x07_MSIHTIntConversionEn_MASK | + D0F0x98_x07_IommuBwOptEn_MASK | D0F0x98_x07_IommuIsocPassPWMode_MASK | + D0F0x98_x07_IocBwOptEn_MASK | D0F0x98_x07_DropZeroMaskWrEn_MASK, + (0x1 << D0F0x98_x07_UnadjustThrottlingStpclk_OFFSET) | (0x0 << D0F0x98_x07_MSIHTIntConversionEn_OFFSET) | + (0x1 << D0F0x98_x07_IommuBwOptEn_OFFSET) | (0x1 << D0F0x98_x07_IommuIsocPassPWMode_OFFSET) | + (0x1 << D0F0x98_x07_IocBwOptEn_OFFSET) | (0x1 << D0F0x98_x07_DropZeroMaskWrEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0x98_x08_TYPE, + D0F0x98_x08_ADDRESS, + D0F0x98_x08_NpWrrLenC_MASK, + 0x1 << D0F0x98_x08_NpWrrLenC_OFFSET + ), + GNB_ENTRY_RMW ( + D0F0x98_x28_TYPE, + D0F0x98_x28_ADDRESS, + D0F0x98_x28_ForceCoherentIntr_MASK, + 0x1 << D0F0x98_x28_ForceCoherentIntr_OFFSET + ), + GNB_ENTRY_RMW ( + D0F0x98_x2C_TYPE, + D0F0x98_x2C_ADDRESS, + D0F0x98_x2C_NBOutbWakeMask_MASK | D0F0x98_x2C_OrbRxIdlesMask_MASK, + (0x1 << D0F0x98_x2C_NBOutbWakeMask_OFFSET) | (0x1 << D0F0x98_x2C_OrbRxIdlesMask_OFFSET) + ), +//--------------------------------------------------------------------------- +//IOMMU L2 Initialization + GNB_ENTRY_RMW ( + D0F2xF4_x10_TYPE, + D0F2xF4_x10_ADDRESS, + D0F2xF4_x10_DTCInvalidationSel_MASK, + 0x2 << D0F2xF4_x10_DTCInvalidationSel_OFFSET + ), + GNB_ENTRY_RMW ( + D0F2xF4_x11_TYPE, + D0F2xF4_x11_ADDRESS, + D0F2xF4_x11_DtcAddressMask_MASK | D0F2xF4_x11_DtcAltHashEn_MASK, + (0x0 << D0F2xF4_x11_DtcAddressMask_OFFSET) | (0x1 << D0F2xF4_x11_DtcAltHashEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xF4_x14_TYPE, + D0F2xF4_x14_ADDRESS, + D0F2xF4_x14_ITCInvalidationSel_MASK, + 0x2 << D0F2xF4_x14_ITCInvalidationSel_OFFSET + ), + GNB_ENTRY_RMW ( + D0F2xF4_x15_TYPE, + D0F2xF4_x15_ADDRESS, + D0F2xF4_x15_ITCAddressMask_MASK | D0F2xF4_x15_ItcAltHashEn_MASK, + (0x0 << D0F2xF4_x15_ITCAddressMask_OFFSET) | (1 << D0F2xF4_x15_ItcAltHashEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xF4_x18_TYPE, + D0F2xF4_x18_ADDRESS, + D0F2xF4_x18_PTCAInvalidationSel_MASK, + 0x2 << D0F2xF4_x18_PTCAInvalidationSel_OFFSET + ), + GNB_ENTRY_RMW ( + D0F2xF4_x19_TYPE, + D0F2xF4_x19_ADDRESS, + D0F2xF4_x19_PTCAAddressMask_MASK | D0F2xF4_x19_PtcAltHashEn_MASK, + (0x0 << D0F2xF4_x19_PTCAAddressMask_OFFSET) | (1 << D0F2xF4_x19_PtcAltHashEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xF4_x30_TYPE, + D0F2xF4_x30_ADDRESS, + D0F2xF4_x30_ERRRuleLock1_MASK, + 0x1 << D0F2xF4_x30_ERRRuleLock1_OFFSET + ), + GNB_ENTRY_RMW ( + D0F2xF4_x34_TYPE, + D0F2xF4_x34_ADDRESS, + D0F2xF4_x34_L2aregHostPgsize_MASK | D0F2xF4_x34_L2aregGstPgsize_MASK, + (0x2 << D0F2xF4_x34_L2aregHostPgsize_OFFSET) | (0x2 << D0F2xF4_x34_L2aregGstPgsize_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xF4_x47_TYPE, + D0F2xF4_x47_ADDRESS, + D0F2xF4_x47_TwAtomicFilterEn_MASK | D0F2xF4_x47_TwNwEn_MASK, + (0x1 << D0F2xF4_x47_TwAtomicFilterEn_OFFSET) | (1 << D0F2xF4_x47_TwNwEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xF4_x4C_TYPE, + D0F2xF4_x4C_ADDRESS, + D0F2xF4_x4C_GstPartialPtcCntrl_MASK, + 0x3 << D0F2xF4_x4C_GstPartialPtcCntrl_OFFSET + ), + GNB_ENTRY_RMW ( + D0F2xF4_x50_TYPE, + D0F2xF4_x50_ADDRESS, + D0F2xF4_x50_PDCInvalidationSel_MASK, + 0x2 << D0F2xF4_x50_PDCInvalidationSel_OFFSET + ), + GNB_ENTRY_RMW ( + D0F2xF4_x51_TYPE, + D0F2xF4_x51_ADDRESS, + D0F2xF4_x51_PDCAddressMask_MASK | D0F2xF4_x51_PdcAltHashEn_MASK, + (0x0 << D0F2xF4_x51_PDCAddressMask_OFFSET) | (1 << D0F2xF4_x51_PdcAltHashEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xF4_x56_TYPE, + D0F2xF4_x56_ADDRESS, + D0F2xF4_x56_CPFlushOnInv_MASK | D0F2xF4_x56_CPFlushOnWait_MASK, + (0x0 << D0F2xF4_x56_CPFlushOnInv_OFFSET) | (1 << D0F2xF4_x56_CPFlushOnWait_OFFSET) + ), + + GNB_ENTRY_RMW ( + D0F2xF4_x80_TYPE, + D0F2xF4_x80_ADDRESS, + D0F2xF4_x80_ERRRuleLock0_MASK, + 0x1 << D0F2xF4_x80_ERRRuleLock0_OFFSET + ), + GNB_ENTRY_RMW ( + D0F2xF4_x90_TYPE, + D0F2xF4_x90_ADDRESS, + D0F2xF4_x90_CKGateL2BMiscDisable_MASK | D0F2xF4_x90_CKGateL2BDynamicDisable_MASK | D0F2xF4_x90_CKGateL2BRegsDisable_MASK | D0F2xF4_x90_CKGateL2BCacheDisable_MASK, + (0x1 << D0F2xF4_x90_CKGateL2BMiscDisable_OFFSET) | (0x1 << D0F2xF4_x90_CKGateL2BDynamicDisable_OFFSET) | (0x1 << D0F2xF4_x90_CKGateL2BRegsDisable_OFFSET) | (0x1 << D0F2xF4_x90_CKGateL2BCacheDisable_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xF4_x92_TYPE, + D0F2xF4_x92_ADDRESS, + D0F2xF4_x92_PprIntcoallesceEn_MASK | D0F2xF4_x92_PprIntreqdelay_MASK | D0F2xF4_x92_PprInttimedelay_MASK, + (0x0 << D0F2xF4_x92_PprIntcoallesceEn_OFFSET) | (0x20 << D0F2xF4_x92_PprIntreqdelay_OFFSET) | (0x15 << D0F2xF4_x92_PprInttimedelay_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xF4_x94_TYPE, + D0F2xF4_x94_ADDRESS, + D0F2xF4_x94_L2bregHostPgsize_MASK | D0F2xF4_x94_L2bregGstPgsize_MASK, + (0x2 << D0F2xF4_x94_L2bregHostPgsize_OFFSET) | (0x2ull << D0F2xF4_x94_L2bregGstPgsize_OFFSET) + ), +//IOMMU L1 Initialization + GNB_ENTRY_RMW ( + D0F2xFC_x0C_L1_TYPE, + D0F2xFC_x0C_L1_ADDRESS (L1_SEL_GFX), + D0F2xFC_x0C_L1_L1VirtOrderQueues_MASK, + 0x4 << D0F2xFC_x0C_L1_L1VirtOrderQueues_OFFSET + ), + GNB_ENTRY_RMW ( + D0F2xFC_x32_L1_TYPE, + D0F2xFC_x32_L1_ADDRESS (L1_SEL_GFX), + D0F2xFC_x32_L1_AtsMultipleL1toL2En_MASK | D0F2xFC_x32_L1_AtsMultipleRespEn_MASK | D0F2xFC_x32_L1_TimeoutPulseExtEn_MASK, + (0x1 << D0F2xFC_x32_L1_AtsMultipleL1toL2En_OFFSET) | (0x1 << D0F2xFC_x32_L1_AtsMultipleRespEn_OFFSET) | (0x1 << D0F2xFC_x32_L1_TimeoutPulseExtEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xFC_x07_L1_TYPE, + D0F2xFC_x07_L1_ADDRESS (L1_SEL_GFX), + D0F2xFC_x07_L1_L1NwEn_MASK | D0F2xFC_x07_L1_AtsPhysPageOverlapDis_MASK | + D0F2xFC_x07_L1_AtsSeqNumEn_MASK | D0F2xFC_x07_L1_SpecReqFilterEn_MASK, + (0x1 << D0F2xFC_x07_L1_L1NwEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_AtsPhysPageOverlapDis_OFFSET) | + (0x1 << D0F2xFC_x07_L1_AtsSeqNumEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_SpecReqFilterEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xFC_x0C_L1_TYPE, + D0F2xFC_x0C_L1_ADDRESS (L1_SEL_GPPSB), + D0F2xFC_x0C_L1_L1VirtOrderQueues_MASK, + 0x4 << D0F2xFC_x0C_L1_L1VirtOrderQueues_OFFSET + ), + GNB_ENTRY_RMW ( + D0F2xFC_x32_L1_TYPE, + D0F2xFC_x32_L1_ADDRESS (L1_SEL_GPPSB), + D0F2xFC_x32_L1_AtsMultipleL1toL2En_MASK | D0F2xFC_x32_L1_AtsMultipleRespEn_MASK | D0F2xFC_x32_L1_TimeoutPulseExtEn_MASK, + (0x1 << D0F2xFC_x32_L1_AtsMultipleL1toL2En_OFFSET) | (0x1 << D0F2xFC_x32_L1_AtsMultipleRespEn_OFFSET) | (0x1 << D0F2xFC_x32_L1_TimeoutPulseExtEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xFC_x07_L1_TYPE, + D0F2xFC_x07_L1_ADDRESS (L1_SEL_GPPSB), + D0F2xFC_x07_L1_L1NwEn_MASK | D0F2xFC_x07_L1_AtsPhysPageOverlapDis_MASK | + D0F2xFC_x07_L1_AtsSeqNumEn_MASK | D0F2xFC_x07_L1_SpecReqFilterEn_MASK, + (0x1 << D0F2xFC_x07_L1_L1NwEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_AtsPhysPageOverlapDis_OFFSET) | + (0x1 << D0F2xFC_x07_L1_AtsSeqNumEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_SpecReqFilterEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xFC_x0C_L1_TYPE, + D0F2xFC_x0C_L1_ADDRESS (L1_SEL_GBIF), + D0F2xFC_x0C_L1_L1VirtOrderQueues_MASK, + 0x4 << D0F2xFC_x0C_L1_L1VirtOrderQueues_OFFSET + ), + GNB_ENTRY_RMW ( + D0F2xFC_x32_L1_TYPE, + D0F2xFC_x32_L1_ADDRESS (L1_SEL_GBIF), + D0F2xFC_x32_L1_AtsMultipleL1toL2En_MASK | D0F2xFC_x32_L1_AtsMultipleRespEn_MASK | D0F2xFC_x32_L1_TimeoutPulseExtEn_MASK, + (0x1 << D0F2xFC_x32_L1_AtsMultipleL1toL2En_OFFSET) | (0x1 << D0F2xFC_x32_L1_AtsMultipleRespEn_OFFSET) | (0x1 << D0F2xFC_x32_L1_TimeoutPulseExtEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xFC_x07_L1_TYPE, + D0F2xFC_x07_L1_ADDRESS (L1_SEL_GBIF), + D0F2xFC_x07_L1_L1NwEn_MASK | D0F2xFC_x07_L1_AtsPhysPageOverlapDis_MASK | + D0F2xFC_x07_L1_AtsSeqNumEn_MASK | D0F2xFC_x07_L1_SpecReqFilterEn_MASK, + (0x1 << D0F2xFC_x07_L1_L1NwEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_AtsPhysPageOverlapDis_OFFSET) | + (0x1 << D0F2xFC_x07_L1_AtsSeqNumEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_SpecReqFilterEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xFC_x0C_L1_TYPE, + D0F2xFC_x0C_L1_ADDRESS (L1_SEL_INTGEN), + D0F2xFC_x0C_L1_L1VirtOrderQueues_MASK, + 0x4 << D0F2xFC_x0C_L1_L1VirtOrderQueues_OFFSET + ), + GNB_ENTRY_RMW ( + D0F2xFC_x32_L1_TYPE, + D0F2xFC_x32_L1_ADDRESS (L1_SEL_INTGEN), + D0F2xFC_x32_L1_AtsMultipleL1toL2En_MASK | D0F2xFC_x32_L1_AtsMultipleRespEn_MASK | D0F2xFC_x32_L1_TimeoutPulseExtEn_MASK, + (0x1 << D0F2xFC_x32_L1_AtsMultipleL1toL2En_OFFSET) | (0x1 << D0F2xFC_x32_L1_AtsMultipleRespEn_OFFSET) | (0x1 << D0F2xFC_x32_L1_TimeoutPulseExtEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F2xFC_x07_L1_TYPE, + D0F2xFC_x07_L1_ADDRESS (L1_SEL_INTGEN), + D0F2xFC_x07_L1_L1NwEn_MASK | D0F2xFC_x07_L1_AtsPhysPageOverlapDis_MASK | + D0F2xFC_x07_L1_AtsSeqNumEn_MASK | D0F2xFC_x07_L1_SpecReqFilterEn_MASK, + (0x1 << D0F2xFC_x07_L1_L1NwEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_AtsPhysPageOverlapDis_OFFSET) | + (0x1 << D0F2xFC_x07_L1_AtsSeqNumEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_SpecReqFilterEn_OFFSET) + ), +//--------------------------------------------------------------------------- +// IOMMU Initialization + GNB_ENTRY_RMW ( + D0F2x70_TYPE, + D0F2x70_ADDRESS, + D0F2x70_PcSupW_MASK, + (0x0 << D0F2x70_PcSupW_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0x64_x0D_TYPE, + D0F0x64_x0D_ADDRESS, + D0F0x64_x0D_PciDev0Fn2RegEn_MASK, + (0x1 << D0F0x64_x0D_PciDev0Fn2RegEn_OFFSET) + ), +// IOMMU L2 clock gating + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IOMMU_L2_CLOCK_GATING, + D0F2xF4_x33_TYPE, + D0F2xF4_x33_ADDRESS, + D0F2xF4_x33_CKGateL2ARegsDisable_MASK | D0F2xF4_x33_CKGateL2ADynamicDisable_MASK | D0F2xF4_x33_CKGateL2ACacheDisable_MASK, + 0x0 + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IOMMU_L2_CLOCK_GATING, + D0F2xF4_x90_TYPE, + D0F2xF4_x90_ADDRESS, + D0F2xF4_x90_CKGateL2BRegsDisable_MASK | D0F2xF4_x90_CKGateL2BDynamicDisable_MASK | D0F2xF4_x90_CKGateL2BMiscDisable_MASK | D0F2xF4_x90_CKGateL2BCacheDisable_MASK, + 0x0 + ), +// IOMMU L1 clock gating + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING, + D0F2xFC_x33_L1_TYPE, + D0F2xFC_x33_L1_ADDRESS (L1_SEL_GFX), + D0F2xFC_x33_L1_L1DmaClkgateEn_MASK | D0F2xFC_x33_L1_L1CacheClkgateEn_MASK | + D0F2xFC_x33_L1_L1CpslvClkgateEn_MASK | D0F2xFC_x33_L1_L1DmaInputClkgateEn_MASK | + D0F2xFC_x33_L1_L1PerfClkgateEn_MASK | D0F2xFC_x33_L1_L1MemoryClkgateEn_MASK | + D0F2xFC_x33_L1_L1RegClkgateEn_MASK | D0F2xFC_x33_L1_L1L2ClkgateEn_MASK, + (0x1 << D0F2xFC_x33_L1_L1DmaClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1CacheClkgateEn_OFFSET) | + (0x1 << D0F2xFC_x33_L1_L1CpslvClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1DmaInputClkgateEn_OFFSET) | + (0x1 << D0F2xFC_x33_L1_L1PerfClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1MemoryClkgateEn_OFFSET) | + (0x1 << D0F2xFC_x33_L1_L1RegClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1L2ClkgateEn_OFFSET) + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING, + D0F2xFC_x33_L1_TYPE, + D0F2xFC_x33_L1_ADDRESS (L1_SEL_GPPSB), + D0F2xFC_x33_L1_L1DmaClkgateEn_MASK | D0F2xFC_x33_L1_L1CacheClkgateEn_MASK | + D0F2xFC_x33_L1_L1CpslvClkgateEn_MASK | D0F2xFC_x33_L1_L1DmaInputClkgateEn_MASK | + D0F2xFC_x33_L1_L1PerfClkgateEn_MASK | D0F2xFC_x33_L1_L1MemoryClkgateEn_MASK | + D0F2xFC_x33_L1_L1RegClkgateEn_MASK | D0F2xFC_x33_L1_L1L2ClkgateEn_MASK, + (0x1 << D0F2xFC_x33_L1_L1DmaClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1CacheClkgateEn_OFFSET) | + (0x1 << D0F2xFC_x33_L1_L1CpslvClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1DmaInputClkgateEn_OFFSET) | + (0x1 << D0F2xFC_x33_L1_L1PerfClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1MemoryClkgateEn_OFFSET) | + (0x1 << D0F2xFC_x33_L1_L1RegClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1L2ClkgateEn_OFFSET) + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING, + D0F2xFC_x33_L1_TYPE, + D0F2xFC_x33_L1_ADDRESS (L1_SEL_GBIF), + D0F2xFC_x33_L1_L1DmaClkgateEn_MASK | D0F2xFC_x33_L1_L1CacheClkgateEn_MASK | + D0F2xFC_x33_L1_L1CpslvClkgateEn_MASK | D0F2xFC_x33_L1_L1DmaInputClkgateEn_MASK | + D0F2xFC_x33_L1_L1PerfClkgateEn_MASK | D0F2xFC_x33_L1_L1MemoryClkgateEn_MASK | + D0F2xFC_x33_L1_L1RegClkgateEn_MASK | D0F2xFC_x33_L1_L1L2ClkgateEn_MASK, + (0x1 << D0F2xFC_x33_L1_L1DmaClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1CacheClkgateEn_OFFSET) | + (0x1 << D0F2xFC_x33_L1_L1CpslvClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1DmaInputClkgateEn_OFFSET) | + (0x1 << D0F2xFC_x33_L1_L1PerfClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1MemoryClkgateEn_OFFSET) | + (0x1 << D0F2xFC_x33_L1_L1RegClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1L2ClkgateEn_OFFSET) + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING, + D0F2xFC_x33_L1_TYPE, + D0F2xFC_x33_L1_ADDRESS (L1_SEL_INTGEN), + D0F2xFC_x33_L1_L1DmaClkgateEn_MASK | D0F2xFC_x33_L1_L1CacheClkgateEn_MASK | + D0F2xFC_x33_L1_L1CpslvClkgateEn_MASK | D0F2xFC_x33_L1_L1DmaInputClkgateEn_MASK | + D0F2xFC_x33_L1_L1PerfClkgateEn_MASK | D0F2xFC_x33_L1_L1MemoryClkgateEn_MASK | + D0F2xFC_x33_L1_L1RegClkgateEn_MASK | D0F2xFC_x33_L1_L1L2ClkgateEn_MASK, + (0x1 << D0F2xFC_x33_L1_L1DmaClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1CacheClkgateEn_OFFSET) | + (0x1 << D0F2xFC_x33_L1_L1CpslvClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1DmaInputClkgateEn_OFFSET) | + (0x1 << D0F2xFC_x33_L1_L1PerfClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1MemoryClkgateEn_OFFSET) | + (0x1 << D0F2xFC_x33_L1_L1RegClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1L2ClkgateEn_OFFSET) + ), +//--------------------------------------------------------------------------- +// Configure IOMMU Power Island + GNB_ENTRY_WR ( + D0F0xBC_xE030001C_TYPE, + D0F0xBC_xE030001C_ADDRESS, + (10 << 0 ) | (50 << 8 ) | + (5 << 16 ) + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300018_TYPE, + D0F0xBC_xE0300018_ADDRESS, + (0xff << D0F0xBC_xE0300018_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300018_WriteOp_OFFSET) | + (2 << D0F0xBC_xE0300018_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE030001C_TYPE, + D0F0xBC_xE030001C_ADDRESS, + (50 << 0 ) | (50 << 12 ) + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300018_TYPE, + D0F0xBC_xE0300018_ADDRESS, + (0xff << D0F0xBC_xE0300018_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300018_WriteOp_OFFSET) | + (3 << D0F0xBC_xE0300018_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE030001C_TYPE, + D0F0xBC_xE030001C_ADDRESS, + 0x0 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE0300018_TYPE, + D0F0xBC_xE0300018_ADDRESS, + (0xff << D0F0xBC_xE0300018_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300018_WriteOp_OFFSET) | + (1 << D0F0xBC_xE0300018_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_RMW ( + D0F0xBC_xE0300320_TYPE, + D0F0xBC_xE0300320_ADDRESS, + D0F0xBC_xE0300320_IommuPgfsmClockEn_MASK, + 0x0 + ), +// Hide IOMMU function if disabled + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IOMMU_DISABLED, + D0F0x64_x0D_TYPE, + D0F0x64_x0D_ADDRESS, + D0F0x64_x0D_PciDev0Fn2RegEn_MASK, + 0x0 + ), + //NB P-state Configuration for Runtime + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_NBDPM, + D0F0xBC_x1F428_TYPE, + D0F0xBC_x1F428_ADDRESS, + D0F0xBC_x1F428_EnableNbDpm_MASK, + (1 << D0F0xBC_x1F428_EnableNbDpm_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0xBC_x1F638_TYPE, + D0F0xBC_x1F638_ADDRESS, + D0F0xBC_x1F638_NbdpmPeriod_MASK | D0F0xBC_x1F638_PginterlockPeriod_MASK, + (1 << D0F0xBC_x1F638_NbdpmPeriod_OFFSET) | (1 << D0F0xBC_x1F638_PginterlockPeriod_OFFSET) + ), + + GNB_ENTRY_COPY ( + D0F0xBC_x1F5F8_TYPE, + D0F0xBC_x1F5F8_ADDRESS, + D0F0xBC_x1F5F8_Dpm0PgNbPsLo_OFFSET, D0F0xBC_x1F5F8_Dpm0PgNbPsLo_WIDTH, + D0F0xBC_xE010703C_TYPE, + D0F0xBC_xE010703C_ADDRESS, + D0F0xBC_xE010703C_NbPstateLo_OFFSET, D0F0xBC_xE010703C_NbPstateLo_WIDTH + ), + GNB_ENTRY_COPY ( + D0F0xBC_x1F5F8_TYPE, + D0F0xBC_x1F5F8_ADDRESS, + D0F0xBC_x1F5F8_Dpm0PgNbPsHi_OFFSET, D0F0xBC_x1F5F8_Dpm0PgNbPsHi_WIDTH, + D0F0xBC_xE010703C_TYPE, + D0F0xBC_xE010703C_ADDRESS, + D0F0xBC_xE010703C_NbPstateHi_OFFSET, D0F0xBC_xE010703C_NbPstateHi_WIDTH + ), + GNB_ENTRY_COPY ( + D0F0xBC_x1F5F8_TYPE, + D0F0xBC_x1F5F8_ADDRESS, + D0F0xBC_x1F5F8_DpmXNbPsLo_OFFSET, D0F0xBC_x1F5F8_DpmXNbPsLo_WIDTH, + D0F0xBC_xE010703C_TYPE, + D0F0xBC_xE010703C_ADDRESS, + D0F0xBC_xE010703C_NbPstateLo_OFFSET, D0F0xBC_xE010703C_NbPstateLo_WIDTH + ), + GNB_ENTRY_COPY ( + D0F0xBC_x1F5F8_TYPE, + D0F0xBC_x1F5F8_ADDRESS, + D0F0xBC_x1F5F8_DpmXNbPsHi_OFFSET, D0F0xBC_x1F5F8_DpmXNbPsHi_WIDTH, + D0F0xBC_xE010703C_TYPE, + D0F0xBC_xE010703C_ADDRESS, + D0F0xBC_xE010703C_NbPstateHi_OFFSET, D0F0xBC_xE010703C_NbPstateHi_WIDTH + ), + GNB_ENTRY_RMW ( + D0F0xBC_x1F5F8_TYPE, + D0F0xBC_x1F5F8_ADDRESS, + D0F0xBC_x1F5F8_Hysteresis_MASK | D0F0xBC_x1F5F8_SkipDPM0_MASK | + D0F0xBC_x1F5F8_SkipPG_MASK | D0F0xBC_x1F5F8_EnableNbPsi1_MASK | D0F0xBC_x1F5F8_EnableDpmPstatePoll_MASK, + (10 << D0F0xBC_x1F5F8_Hysteresis_OFFSET) | (1 << D0F0xBC_x1F5F8_SkipDPM0_OFFSET) | + (1 << D0F0xBC_x1F5F8_EnableNbPsi1_OFFSET) | (1 << D0F0xBC_x1F5F8_EnableDpmPstatePoll_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0xBC_x1F6E4_TYPE, + D0F0xBC_x1F6E4_ADDRESS, + D0F0xBC_x1F6E4_DdrVoltFloor_MASK | D0F0xBC_x1F6E4_BapmDdrVoltFloor_MASK, + (0xFF << D0F0xBC_x1F6E4_DdrVoltFloor_OFFSET) | (0xFF << D0F0xBC_x1F6E4_BapmDdrVoltFloor_OFFSET) + ), + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_NBDPM, + SMU_MSG_TYPE, + SMC_MSG_CONFIG_NBDPM, + 0 + ), + +//--------------------------------------------------------------------------- +// Configure PCIe Power Island + GNB_ENTRY_WR ( + D0F0xBC_xE0300010_TYPE, + D0F0xBC_xE0300010_ADDRESS, + (10 << 0 ) | (50 << 8 ) | + (5 << 16 ) + ), + GNB_ENTRY_WR ( + D0F0xBC_xE030000C_TYPE, + D0F0xBC_xE030000C_ADDRESS, + (0xff << D0F0xBC_xE030000C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030000C_WriteOp_OFFSET) | + (2 << D0F0xBC_xE030000C_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300010_TYPE, + D0F0xBC_xE0300010_ADDRESS, + (50 << 0 ) | (50 << 12 ) + ), + GNB_ENTRY_WR ( + D0F0xBC_xE030000C_TYPE, + D0F0xBC_xE030000C_ADDRESS, + (0xff << D0F0xBC_xE030000C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030000C_WriteOp_OFFSET) | + (3 << D0F0xBC_xE030000C_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_WR ( + D0F0xBC_xE0300010_TYPE, + D0F0xBC_xE0300010_ADDRESS, + 0x0 + ), + GNB_ENTRY_WR ( + D0F0xBC_xE030000C_TYPE, + D0F0xBC_xE030000C_ADDRESS, + (0xff << D0F0xBC_xE030000C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030000C_WriteOp_OFFSET) | (1 << D0F0xBC_xE030000C_RegAddr_OFFSET) + ), + GNB_ENTRY_STALL (1), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_LOADLINE_ENABLE, + TYPE_D0F0xBC , + 0x1f428 , + 0x40 , + (1 << 6 ) + ), + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_LOADLINE_ENABLE, + SMU_MSG_TYPE, + SMC_MSG_CONFIG_LOADLINE, + 0 + ), + GNB_ENTRY_TERMINATE +}; + +GNB_TABLE ROMDATA GnbMidInitTableTN [] = { +//--------------------------------------------------------------------------- +// Enable LCLK Deep Sleep + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_LCLK_DEEP_SLEEP, + TYPE_GMM, + GMMx7A0_ADDRESS, + GMMx7A0_DivId_MASK | GMMx7A0_RampDis_MASK | GMMx7A0_Hysteresis_MASK | GMMx7A0_SclkRunningMask_MASK | GMMx7A0_SmuBusyMask_MASK | GMMx7A0_PcieLclkIdle1Mask_MASK | GMMx7A0_PcieLclkIdle2Mask_MASK | GMMx7A0_L1imugfxIdleMask_MASK | GMMx7A0_L1imugppsbIdleMask_MASK | GMMx7A0_L1imubifIdleMask_MASK | GMMx7A0_L1imuintgenIdleMask_MASK | GMMx7A0_L2imuIdleMask_MASK | GMMx7A0_OrbIdleMask_MASK | GMMx7A0_OnInbWakeMask_MASK | GMMx7A0_OnInbWakeAckMask_MASK | GMMx7A0_OnOutbWakeMask_MASK | GMMx7A0_OnOutbWakeAckMask_MASK | GMMx7A0_DmaactiveMask_MASK, + (0x5 << GMMx7A0_DivId_OFFSET) | (0x0 << GMMx7A0_RampDis_OFFSET) | (0xF << GMMx7A0_Hysteresis_OFFSET) | (0x1 << GMMx7A0_SclkRunningMask_OFFSET) | (0x1 << GMMx7A0_SmuBusyMask_OFFSET) | (0x1 << GMMx7A0_PcieLclkIdle1Mask_OFFSET) | (0x1 << GMMx7A0_PcieLclkIdle2Mask_OFFSET) | (0x1 << GMMx7A0_L1imugfxIdleMask_OFFSET) | (0x1 << GMMx7A0_L1imugppsbIdleMask_OFFSET) | (0x1 << GMMx7A0_L1imubifIdleMask_OFFSET) | (0x1 << GMMx7A0_L1imuintgenIdleMask_OFFSET) | (0x1 << GMMx7A0_L2imuIdleMask_OFFSET) | (0x1 << GMMx7A0_OrbIdleMask_OFFSET) | (0x1 << GMMx7A0_OnInbWakeMask_OFFSET) | (0x1 << GMMx7A0_OnInbWakeAckMask_OFFSET) | (0x1 << GMMx7A0_OnOutbWakeMask_OFFSET) | (0x1 << GMMx7A0_OnOutbWakeAckMask_OFFSET) | (0x1 << GMMx7A0_DmaactiveMask_OFFSET) + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + TYPE_GMM, + GMMx7A0_ADDRESS, + GMMx7A0_SclkRunningMask_MASK, + 0x0 + ), +// Reset : 0, Enable : 1 + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_LCLK_DEEP_SLEEP, + TYPE_GMM, + GMMx7A0_ADDRESS, + GMMx7A0_EnableDs_MASK, + (0x1 << GMMx7A0_EnableDs_OFFSET) + ), +//--------------------------------------------------------------------------- +// LCLK DPM init + GNB_ENTRY_RMW ( + D0F0xBC_xE0000120_TYPE, + D0F0xBC_xE0000120_ADDRESS, + D0F0xBC_xE0000120_BusyCntSel_MASK | D0F0xBC_xE0000120_ActivityCntRst_MASK | + D0F0xBC_xE0000120_PeriodCntRst_MASK | D0F0xBC_xE0000120_EnOrbUsCnt_MASK | + D0F0xBC_xE0000120_EnOrbDsCnt_MASK, + (0x3 << D0F0xBC_xE0000120_BusyCntSel_OFFSET) | (0 << D0F0xBC_xE0000120_ActivityCntRst_OFFSET) | + (0x0 << D0F0xBC_xE0000120_PeriodCntRst_OFFSET) | (0x1 << D0F0xBC_xE0000120_EnOrbUsCnt_OFFSET) | + (0x1 << D0F0xBC_xE0000120_EnOrbDsCnt_OFFSET) + ), + //Programming Lclk Thermal Throttling Threshold in GnbLclkDpmInitTN() + GNB_ENTRY_RMW ( + D0F0xBC_x1F308_TYPE, + D0F0xBC_x1F308_ADDRESS, + D0F0xBC_x1F308_LclkThermalThrottlingEn_MASK, + (0x1 << D0F0xBC_x1F308_LclkThermalThrottlingEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0xBC_x1F460_TYPE, + D0F0xBC_x1F460_ADDRESS, + D0F0xBC_x1F460_LclkDpm_MASK, + (0x1 << D0F0xBC_x1F460_LclkDpm_OFFSET) + ), +//--------------------------------------------------------------------------- +// ORB clock gating + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_ORB_CLK_GATING, + D0F0x98_x49_TYPE, + D0F0x98_x49_ADDRESS, + D0F0x98_x49_SoftOverrideClk6_MASK | D0F0x98_x49_SoftOverrideClk5_MASK | D0F0x98_x49_SoftOverrideClk4_MASK | D0F0x98_x49_SoftOverrideClk3_MASK | D0F0x98_x49_SoftOverrideClk2_MASK | D0F0x98_x49_SoftOverrideClk1_MASK | D0F0x98_x49_SoftOverrideClk0_MASK, + 0x0 + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_ORB_CLK_GATING, + D0F0x98_x4A_TYPE, + D0F0x98_x4A_ADDRESS, + D0F0x98_x4A_SoftOverrideClk6_MASK | D0F0x98_x4A_SoftOverrideClk5_MASK | D0F0x98_x4A_SoftOverrideClk4_MASK | D0F0x98_x4A_SoftOverrideClk3_MASK | D0F0x98_x4A_SoftOverrideClk2_MASK | D0F0x98_x4A_SoftOverrideClk1_MASK | D0F0x98_x4A_SoftOverrideClk0_MASK, + (1 << D0F0x98_x4A_SoftOverrideClk0_OFFSET) + ), + +//--------------------------------------------------------------------------- +// IOC clock gating + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING, + D0F0x64_x22_TYPE, + D0F0x64_x22_ADDRESS, + D0F0x64_x22_SoftOverrideClk4_MASK | D0F0x64_x22_SoftOverrideClk3_MASK | D0F0x64_x22_SoftOverrideClk2_MASK | D0F0x64_x22_SoftOverrideClk1_MASK | D0F0x64_x22_SoftOverrideClk0_MASK, + 0x0 + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING, + D0F0x64_x23_TYPE, + D0F0x64_x23_ADDRESS, + D0F0x64_x23_SoftOverrideClk4_MASK | D0F0x64_x23_SoftOverrideClk3_MASK | D0F0x64_x23_SoftOverrideClk2_MASK | D0F0x64_x23_SoftOverrideClk1_MASK | D0F0x64_x23_SoftOverrideClk0_MASK, + 0x0 + ), + +//--------------------------------------------------------------------------- +// Shutdown IOMMU if disabled + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IOMMU_DISABLED, + D0F0xBC_xE0300320_TYPE, + D0F0xBC_xE0300320_ADDRESS, + D0F0xBC_xE0300320_IommuPgfsmClockEn_MASK, + 1 << D0F0xBC_xE0300320_IommuPgfsmClockEn_OFFSET + ), + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_IOMMU_DISABLED, + D0F0xBC_xE0300018_TYPE, + D0F0xBC_xE0300018_ADDRESS, + (0xff << D0F0xBC_xE0300018_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300018_PowerDown_OFFSET) | + (1 << D0F0xBC_xE0300018_P1Select_OFFSET) | (1 << D0F0xBC_xE0300018_P2Select_OFFSET) + ), + GNB_ENTRY_PROPERTY_POLL ( + TABLE_PROPERTY_IOMMU_DISABLED, + D0F0xBC_xE0300208_TYPE, + 0xe0300208 , + D0F0xBC_xE0300208_P1IsoN_MASK, + 0 << D0F0xBC_xE0300208_P1IsoN_OFFSET + ), + GNB_ENTRY_PROPERTY_POLL ( + TABLE_PROPERTY_IOMMU_DISABLED, + TYPE_D0F0xBC , + 0xe0300208 , + 0x2000 , + 1 << 13 + ), + GNB_ENTRY_STALL (10), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IOMMU_DISABLED, + D0F0xBC_xE0300320_TYPE, + D0F0xBC_xE0300320_ADDRESS, + D0F0xBC_xE0300320_IommuPgfsmClockEn_MASK, + 0x0 + ), +//--------------------------------------------------------------------------- + GNB_ENTRY_TERMINATE +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h new file mode 100644 index 0000000..f3bf14a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h @@ -0,0 +1,242 @@ +/** + * @file + * + * ALIB SSDT table + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63659 $ @e $Date: 2012-01-03 00:42:47 -0600 (Tue, 03 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _PCIEALIBSSDTTNFM2_H_ +#define _PCIEALIBSSDTTNFM2_H_ + +UINT8 AlibSsdtTNFM2[] = { + 0x53, 0x53, 0x44, 0x54, 0x1F, 0x05, 0x00, 0x00, + 0x02, 0xE2, 0x41, 0x4D, 0x44, 0x00, 0x00, 0x00, + 0x41, 0x4C, 0x49, 0x42, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x4D, 0x53, 0x46, 0x54, + 0x00, 0x00, 0x00, 0x04, 0x10, 0x4A, 0x4F, 0x5C, + 0x5F, 0x53, 0x42, 0x5F, 0x08, 0x41, 0x30, 0x30, + 0x31, 0x0A, 0x06, 0x08, 0x41, 0x44, 0x30, 0x31, + 0x0C, 0x00, 0x00, 0x00, 0xE0, 0x06, 0x41, 0x44, + 0x30, 0x31, 0x41, 0x30, 0x31, 0x33, 0x14, 0x31, + 0x41, 0x30, 0x30, 0x36, 0x0A, 0x72, 0x41, 0x30, + 0x31, 0x33, 0x79, 0x68, 0x0A, 0x0C, 0x00, 0x60, + 0x72, 0x69, 0x60, 0x60, 0x5B, 0x80, 0x41, 0x30, + 0x31, 0x34, 0x00, 0x60, 0x0A, 0x04, 0x5B, 0x81, + 0x0B, 0x41, 0x30, 0x31, 0x34, 0x03, 0x41, 0x30, + 0x31, 0x35, 0x20, 0xA4, 0x41, 0x30, 0x31, 0x35, + 0x14, 0x32, 0x41, 0x30, 0x30, 0x37, 0x0B, 0x72, + 0x41, 0x30, 0x31, 0x33, 0x79, 0x68, 0x0A, 0x0C, + 0x00, 0x60, 0x72, 0x69, 0x60, 0x60, 0x5B, 0x80, + 0x41, 0x30, 0x31, 0x34, 0x00, 0x60, 0x0A, 0x04, + 0x5B, 0x81, 0x0B, 0x41, 0x30, 0x31, 0x34, 0x03, + 0x41, 0x30, 0x31, 0x35, 0x20, 0x70, 0x6A, 0x41, + 0x30, 0x31, 0x35, 0x14, 0x1C, 0x41, 0x30, 0x31, + 0x36, 0x0C, 0x70, 0x41, 0x30, 0x30, 0x36, 0x68, + 0x69, 0x60, 0x7D, 0x7B, 0x60, 0x6A, 0x00, 0x6B, + 0x60, 0x41, 0x30, 0x30, 0x37, 0x68, 0x69, 0x60, + 0x5B, 0x01, 0x41, 0x30, 0x31, 0x37, 0x00, 0x14, + 0x32, 0x41, 0x30, 0x31, 0x38, 0x02, 0x5B, 0x23, + 0x41, 0x30, 0x31, 0x37, 0xFF, 0xFF, 0x70, 0x79, + 0x72, 0x68, 0x0A, 0x02, 0x00, 0x0A, 0x03, 0x00, + 0x60, 0x41, 0x30, 0x30, 0x37, 0x60, 0x0A, 0xE0, + 0x69, 0x70, 0x41, 0x30, 0x30, 0x36, 0x60, 0x0A, + 0xE4, 0x60, 0x5B, 0x27, 0x41, 0x30, 0x31, 0x37, + 0xA4, 0x60, 0x14, 0x2F, 0x41, 0x30, 0x31, 0x39, + 0x03, 0x5B, 0x23, 0x41, 0x30, 0x31, 0x37, 0xFF, + 0xFF, 0x70, 0x79, 0x72, 0x68, 0x0A, 0x02, 0x00, + 0x0A, 0x03, 0x00, 0x60, 0x41, 0x30, 0x30, 0x37, + 0x60, 0x0A, 0xE0, 0x69, 0x41, 0x30, 0x30, 0x37, + 0x60, 0x0A, 0xE4, 0x6A, 0x5B, 0x27, 0x41, 0x30, + 0x31, 0x37, 0x14, 0x1C, 0x41, 0x30, 0x32, 0x30, + 0x04, 0x70, 0x41, 0x30, 0x31, 0x38, 0x68, 0x69, + 0x60, 0x7D, 0x7B, 0x60, 0x6A, 0x00, 0x6B, 0x60, + 0x41, 0x30, 0x31, 0x39, 0x68, 0x69, 0x60, 0x5B, + 0x01, 0x41, 0x30, 0x32, 0x31, 0x00, 0x14, 0x29, + 0x41, 0x30, 0x30, 0x38, 0x03, 0x5B, 0x23, 0x41, + 0x30, 0x32, 0x31, 0xFF, 0xFF, 0x41, 0x30, 0x30, + 0x37, 0x68, 0x69, 0x6A, 0x70, 0x41, 0x30, 0x30, + 0x36, 0x68, 0x72, 0x69, 0x0A, 0x04, 0x00, 0x60, + 0x5B, 0x27, 0x41, 0x30, 0x32, 0x31, 0xA4, 0x60, + 0x14, 0x26, 0x41, 0x30, 0x31, 0x32, 0x04, 0x5B, + 0x23, 0x41, 0x30, 0x32, 0x31, 0xFF, 0xFF, 0x41, + 0x30, 0x30, 0x37, 0x68, 0x69, 0x6A, 0x41, 0x30, + 0x30, 0x37, 0x68, 0x72, 0x69, 0x0A, 0x04, 0x00, + 0x6B, 0x5B, 0x27, 0x41, 0x30, 0x32, 0x31, 0x14, + 0x1E, 0x41, 0x30, 0x32, 0x32, 0x05, 0x70, 0x41, + 0x30, 0x30, 0x38, 0x68, 0x69, 0x6A, 0x60, 0x7D, + 0x7B, 0x60, 0x6B, 0x00, 0x6C, 0x60, 0x41, 0x30, + 0x31, 0x32, 0x68, 0x69, 0x6A, 0x60, 0x14, 0x42, + 0x05, 0x41, 0x30, 0x32, 0x33, 0x02, 0x70, 0x0A, + 0x34, 0x61, 0xA0, 0x11, 0x93, 0x41, 0x30, 0x30, + 0x36, 0x68, 0x0A, 0x00, 0x0C, 0xFF, 0xFF, 0xFF, + 0xFF, 0xA4, 0x0A, 0x00, 0x70, 0x0A, 0x01, 0x60, + 0xA2, 0x2E, 0x93, 0x60, 0x0A, 0x01, 0x70, 0x7B, + 0x41, 0x30, 0x30, 0x36, 0x68, 0x61, 0x0A, 0xFF, + 0x00, 0x61, 0xA0, 0x06, 0x93, 0x61, 0x0A, 0x00, + 0xA5, 0xA0, 0x11, 0x93, 0x7B, 0x41, 0x30, 0x30, + 0x36, 0x68, 0x61, 0x0A, 0xFF, 0x00, 0x69, 0x70, + 0x0A, 0x00, 0x60, 0xA1, 0x03, 0x75, 0x61, 0xA4, + 0x61, 0x14, 0x47, 0x09, 0x41, 0x30, 0x32, 0x34, + 0x0A, 0x5B, 0x80, 0x50, 0x4D, 0x49, 0x4F, 0x01, + 0x0B, 0xD6, 0x0C, 0x0A, 0x02, 0x5B, 0x81, 0x10, + 0x50, 0x4D, 0x49, 0x4F, 0x01, 0x50, 0x4D, 0x52, + 0x49, 0x08, 0x50, 0x4D, 0x52, 0x44, 0x08, 0x5B, + 0x86, 0x12, 0x50, 0x4D, 0x52, 0x49, 0x50, 0x4D, + 0x52, 0x44, 0x01, 0x00, 0x40, 0x70, 0x41, 0x42, + 0x41, 0x52, 0x20, 0x5B, 0x80, 0x41, 0x43, 0x46, + 0x47, 0x01, 0x41, 0x42, 0x41, 0x52, 0x0A, 0x08, + 0x5B, 0x81, 0x10, 0x41, 0x43, 0x46, 0x47, 0x03, + 0x41, 0x42, 0x49, 0x58, 0x20, 0x41, 0x42, 0x44, + 0x41, 0x20, 0x70, 0x0A, 0x00, 0x60, 0xA0, 0x17, + 0x93, 0x69, 0x0A, 0x00, 0x70, 0x0C, 0x68, 0x00, + 0x00, 0x80, 0x41, 0x42, 0x49, 0x58, 0x70, 0x41, + 0x42, 0x44, 0x41, 0x60, 0xA4, 0x60, 0xA1, 0x22, + 0x70, 0x0C, 0x68, 0x00, 0x00, 0x80, 0x41, 0x42, + 0x49, 0x58, 0x70, 0x41, 0x42, 0x44, 0x41, 0x60, + 0x7D, 0x7B, 0x60, 0x0C, 0xFC, 0xFF, 0xFF, 0xFF, + 0x00, 0x68, 0x60, 0x70, 0x60, 0x41, 0x42, 0x44, + 0x41, 0x08, 0x41, 0x30, 0x32, 0x35, 0x11, 0x04, + 0x0B, 0x00, 0x01, 0x14, 0x46, 0x08, 0x41, 0x30, + 0x30, 0x39, 0x01, 0xA2, 0x16, 0x92, 0x93, 0x7B, + 0x41, 0x30, 0x30, 0x38, 0x0A, 0x00, 0x0A, 0xB8, + 0x0C, 0x04, 0x30, 0x00, 0xE0, 0x0A, 0x02, 0x00, + 0x0A, 0x02, 0x70, 0x41, 0x30, 0x30, 0x38, 0x0A, + 0x00, 0x0A, 0xB8, 0x0C, 0x00, 0x30, 0x00, 0xE0, + 0x60, 0x7D, 0x7B, 0x60, 0x0C, 0x00, 0x00, 0xFE, + 0xFF, 0x00, 0x7B, 0x80, 0x7B, 0x60, 0x0A, 0x01, + 0x00, 0x00, 0x0A, 0x01, 0x00, 0x60, 0x7D, 0x60, + 0x79, 0x68, 0x0A, 0x01, 0x00, 0x60, 0x41, 0x30, + 0x31, 0x32, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x00, + 0x30, 0x00, 0xE0, 0x60, 0xA2, 0x16, 0x92, 0x93, + 0x7B, 0x41, 0x30, 0x30, 0x38, 0x0A, 0x00, 0x0A, + 0xB8, 0x0C, 0x04, 0x30, 0x00, 0xE0, 0x0A, 0x01, + 0x00, 0x0A, 0x01, 0xA2, 0x16, 0x92, 0x93, 0x7B, + 0x41, 0x30, 0x30, 0x38, 0x0A, 0x00, 0x0A, 0xB8, + 0x0C, 0x04, 0x30, 0x00, 0xE0, 0x0A, 0x02, 0x00, + 0x0A, 0x02, 0x08, 0x41, 0x30, 0x30, 0x32, 0x0A, + 0x00, 0x08, 0x41, 0x30, 0x30, 0x33, 0x0A, 0x00, + 0x08, 0x41, 0x30, 0x30, 0x34, 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b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h new file mode 100644 index 0000000..e9776d0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h @@ -0,0 +1,1065 @@ +/** + * @file + * + * ALIB SSDT table + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 65976 $ @e $Date: 2012-02-27 22:24:12 -0600 (Mon, 27 Feb 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _PCIEALIBSSDTTNFS1_H_ +#define _PCIEALIBSSDTTNFS1_H_ + +UINT8 AlibSsdtTNFS1[] = { + 0x53, 0x53, 0x44, 0x54, 0xD4, 0x1E, 0x00, 0x00, + 0x02, 0x5C, 0x41, 0x4D, 0x44, 0x00, 0x00, 0x00, + 0x41, 0x4C, 0x49, 0x42, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x4D, 0x53, 0x46, 0x54, + 0x00, 0x00, 0x00, 0x04, 0x10, 0x8F, 0xEA, 0x01, + 0x5C, 0x5F, 0x53, 0x42, 0x5F, 0x08, 0x41, 0x30, + 0x30, 0x31, 0x0A, 0x06, 0x08, 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+#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c new file mode 100644 index 0000000..8629095 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c @@ -0,0 +1,119 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe ALIB + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. 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BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "Ids.h" +#include "PcieAlibSsdtTNFM2.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEALIBTNFM2_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID * +PcieAlibGetBaseTableTNFM2 ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Get base SSDT table + * + * + * + * @param[in] StdHeader Standard Configuration Header + * @retval pointer to SSTD table + */ +VOID * +PcieAlibGetBaseTableTNFM2 ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return &AlibSsdtTNFM2[0]; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.esl new file mode 100644 index 0000000..49bae5f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.esl @@ -0,0 +1,196 @@ +/** + * @file + * + * ALIB ASL library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63659 $ @e $Date: 2012-01-03 00:42:47 -0600 (Tue, 03 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +DefinitionBlock ( + "PcieAlibSsdtTN.aml", + "SSDT", + 2, + "AMD", + "ALIB", + 0x1 + ) +{ + Scope(_SB) { + + Name (varMaxPortIndexNumber, 6) + + include ("PcieAlibMmioData.asl") + include ("PcieAlibPciLib.asl") + include ("PcieAlibDebugLib.asl") + include ("PcieSmuServiceV4.asl") + + + Name (varBapmControl, 0) + Name (varCstateIntControlState, 0) + Name (varIsStateInitialized, 0) + /*----------------------------------------------------------------------------------------*/ + /** + * APM/PDM stub + * + * Arg0 - AC/DC state + * + */ + Method (procApmPdmActivate, 1, NotSerialized) { + Store (Or(ShiftLeft (0x18, 3), 4), Local2) + if (LEqual (varIsStateInitialized, 0)) { + Store (procPciDwordRead (Local2, 0x124), varCstateIntControlState) + Store (1, varIsStateInitialized) + } + + Store (procPciDwordRead (Local2, 0x124), Local3) + if (LEqual (Arg0,DEF_PSPP_STATE_AC)) { + // Disable PC6 on AC + Or (Local3, And (varCstateIntControlState, 0x00400000), Local3) + } else { + // Enable PC6 on DC + And (Local3, 0xFFBFFFFF, Local3) + } + procPciDwordWrite (Local2, 0x124, Local3) + + if (LEqual (varBapmControl, 0)) { + // If GFX present driver manage BAPM if not ALIB manage BAPM + if (LEqual (procPciDwordRead (0x08, 0x00), 0xffffffff)) { + And (procIndirectRegisterRead (0x0, 0xB8, 0x1F428), 0x2, Local1); + // check if BAPM was enable during BIOS post + if (LEqual (Local1, 0x2)) { + Store (1, varBapmControl) + } + } + } + if (LEqual (varBapmControl,1)) { + if (LEqual (Arg0,DEF_PSPP_STATE_AC)) { + // Enable BAPM on AC + Store (32, Local0) + } else { + // Disable BAPM on DC + Store (33, Local0) + } + procNbSmuServiceRequest (Local0); + } + } + + Name (varRestoreNbps, 0) + Name (varRestoreNbDpmState, 0) + /*----------------------------------------------------------------------------------------*/ + /** + * _WAK + * + * + * + */ + Method (AWAK, 1) { + if (LEqual (Arg0, 3)) { + // Clear D18F5x170 [SwNbPstateLoDis] only if it was 0 in APTS + if (LEqual (varRestoreNbps, 1)) { + Store (procPciDwordRead (0xC5, 0x170), Local0) + procPciDwordWrite (0xC5, 0x170, And (Local0, Not (ShiftLeft (1, 14)))) + Store (0, varRestoreNbps); + } + if (LEqual (varRestoreNbDpmState, 1)) { + Store (procIndirectRegisterRead (0x0, 0xB8, 0x1F428), Local0) + procIndirectRegisterWrite (0x0, 0xB8, 0x1F428, Or (Local0, ShiftLeft (1, 5))) + procNbSmuServiceRequest (22); + Store (0, varRestoreNbDpmState) + } + } + } + /*----------------------------------------------------------------------------------------*/ + /** + * _PTS + * + * + * + */ + Method (APTS, 1) { + if (LEqual (Arg0, 3)) { + procApmPdmActivate (DEF_PSPP_STATE_DC); + // Disable NBDPM + Store (procIndirectRegisterRead (0x0, 0xB8, 0x1F428), Local0) + if (LNotEqual (And (Local0, ShiftLeft (1, 5)), 0)) { + // NBDPM enabled lets disable it + procIndirectRegisterWrite (0x0, 0xB8, 0x1F428, And (Local0, Not (ShiftLeft (1, 5)))) + procNbSmuServiceRequest (22); + // Indicate needs to restore NBDPM + Store (1, varRestoreNbDpmState); + } + // Save state of D18F5x170 [SwNbPstateLoDis] + Store (procPciDwordRead (0xC5, 0x170), Local0) + if (LEqual (And (Local0, ShiftLeft (1, 14)), 0)) { + // Set D18F5x170 [SwNbPstateLoDis] = 1 + procPciDwordWrite (0xC5, 0x170, Or (Local0, ShiftLeft (1, 14))) + Store (1, varRestoreNbps); + } + } + } + } //End of Scope(_SB) +} //End of DefinitionBlock + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c new file mode 100644 index 0000000..baa0f85 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c @@ -0,0 +1,119 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe ALIB + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "Ids.h" +#include "PcieAlibSsdtTNFS1.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEALIBTNFS1_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID * +PcieAlibGetBaseTableTNFS1 ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Get base SSDT table + * + * + * + * @param[in] StdHeader Standard Configuration Header + * @retval pointer to SSTD table + */ +VOID * +PcieAlibGetBaseTableTNFS1 ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return &AlibSsdtTNFS1[0]; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c new file mode 100644 index 0000000..9c55714 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c @@ -0,0 +1,491 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific PCIe configuration data definition + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "PcieComplexDataTN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIECOMPLEXDATATN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +TN_COMPLEX_CONFIG ComplexDataTN = { + //Silicon + { + { + DESCRIPTOR_SILICON | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY, + 0, + 0, + offsetof (TN_COMPLEX_CONFIG, GfxWrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon) + }, + 0, + 0 + }, + //Gfx Wrapper + { + { + DESCRIPTOR_PCIE_WRAPPER | DESCRIPTOR_DDI_WRAPPER, + offsetof (TN_COMPLEX_CONFIG, GfxWrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon), + offsetof (TN_COMPLEX_CONFIG, GppWrapper) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper), + offsetof (TN_COMPLEX_CONFIG, Port2) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper) + }, + + GFX_WRAP_ID, + GFX_NUMBER_OF_PIFs, + GFX_START_PHY_LANE, + GFX_END_PHY_LANE, + GFX_CORE_ID, + GFX_CORE_ID, + 16, + { + 1, //PowerOffUnusedLanesEnabled, + 1, //PowerOffUnusedPllsEnabled + 1, //ClkGating + 1, //LclkGating + 1, //TxclkGatingPllPowerDown + 1, //PllOffInL1 + 0 //AccessEncoding + }, + }, + //Gpp Wrapper + { + { + DESCRIPTOR_PCIE_WRAPPER, + offsetof (TN_COMPLEX_CONFIG, GppWrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon), + offsetof (TN_COMPLEX_CONFIG, DdiWrapper) - offsetof (TN_COMPLEX_CONFIG, GppWrapper), + offsetof (TN_COMPLEX_CONFIG, Port4) - offsetof (TN_COMPLEX_CONFIG, GppWrapper) + }, + GPP_WRAP_ID, + GPP_NUMBER_OF_PIFs, + GPP_START_PHY_LANE, + GPP_END_PHY_LANE, + GPP_CORE_ID, + GPP_CORE_ID, + 8, + { + 1, //PowerOffUnusedLanesEnabled, + 1, //PowerOffUnusedPllsEnabled + 1, //ClkGating + 1, //LclkGating + 1, //TxclkGatingPllPowerDown + 1, //PllOffInL1 + 0 //AccessEncoding + }, + }, + //DDI Wrapper + { + { + DESCRIPTOR_DDI_WRAPPER, + offsetof (TN_COMPLEX_CONFIG, DdiWrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon), + offsetof (TN_COMPLEX_CONFIG, Ddi2Wrapper) - offsetof (TN_COMPLEX_CONFIG, DdiWrapper), + offsetof (TN_COMPLEX_CONFIG, DpE) - offsetof (TN_COMPLEX_CONFIG, DdiWrapper) + }, + DDI_WRAP_ID, + DDI_NUMBER_OF_PIFs, + DDI_START_PHY_LANE, + DDI_END_PHY_LANE, + 0xf, + 0x0, + 8, + { + 1, //PowerOffUnusedLanesEnabled, + 1, //PowerOffUnusedPllsEnabled + 1, //ClkGating + 1, //LclkGating + 1, //TxclkGatingPllPowerDown + 0, //PllOffInL1 + 0 //AccessEncoding + }, + }, + //DDI2 Wrapper + { + { + DESCRIPTOR_DDI_WRAPPER | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY, + offsetof (TN_COMPLEX_CONFIG, Ddi2Wrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon), + 0, + offsetof (TN_COMPLEX_CONFIG, DpA) - offsetof (TN_COMPLEX_CONFIG, Ddi2Wrapper) + }, + DDI2_WRAP_ID, + DDI2_NUMBER_OF_PIFs, + DDI2_START_PHY_LANE, + DDI2_END_PHY_LANE, + 0xf, + 0x0, + 8, + { + 1, //PowerOffUnusedLanesEnabled, + 1, //PowerOffUnusedPllsEnabled + 1, //ClkGating + 1, //LclkGating + 1, //TxclkGatingPllPowerDown + 0, //PllOffInL1 + 0 //AccessEncoding + }, + }, + //Port 2 + { + { + DESCRIPTOR_PCIE_ENGINE, + offsetof (TN_COMPLEX_CONFIG, Port2) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper), + offsetof (TN_COMPLEX_CONFIG, Port3) - offsetof (TN_COMPLEX_CONFIG, Port2), + 0 + }, + { PciePortEngine, 8, 23}, + 0, //Initialization Status + 0xFF, //Scratch + { + { + {0}, + 0, + 15, + 2, + 0, + GFX_CORE_ID, + 0, + {0}, + LinkStateResetExit, + 0, + 2, + 1 + }, + }, + }, + //Port 3 + { + { + DESCRIPTOR_PCIE_ENGINE, + offsetof (TN_COMPLEX_CONFIG, Port3) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper), + offsetof (TN_COMPLEX_CONFIG, DpB) - offsetof (TN_COMPLEX_CONFIG, Port3), + 0 + }, + { PciePortEngine, UNUSED_LANE_ID, UNUSED_LANE_ID }, + 0, //Initialization Status + 0xFF, //Scratch + { + { + {0}, + UNUSED_LANE_ID, + UNUSED_LANE_ID, + 3, + 0, + GFX_CORE_ID, + 1, + {0}, + LinkStateResetExit, + 1, + 3, + 1 + }, + }, + }, + //DdiB + { + { + DESCRIPTOR_DDI_ENGINE, + offsetof (TN_COMPLEX_CONFIG, DpB) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper), + offsetof (TN_COMPLEX_CONFIG, DpC) - offsetof (TN_COMPLEX_CONFIG, DpB), + 0 + }, + {PcieDdiEngine}, + 0, //Initialization Status + 0xFF //Scratch + }, + //DdiC + { + { + DESCRIPTOR_DDI_ENGINE, + offsetof (TN_COMPLEX_CONFIG, DpC) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper), + offsetof (TN_COMPLEX_CONFIG, DpD) - offsetof (TN_COMPLEX_CONFIG, DpC), + 0 + }, + {PcieDdiEngine}, + 0, //Initialization Status + 0xFF //Scratch + }, + //DdiD + { + { + DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_TERMINATE_LIST, + offsetof (TN_COMPLEX_CONFIG, DpD) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper), + offsetof (TN_COMPLEX_CONFIG, Port4) - offsetof (TN_COMPLEX_CONFIG, DpD), + 0 + }, + {PcieDdiEngine}, + 0, //Initialization Status + 0xFF //Scratch + }, + + //Port 4 + { + { + DESCRIPTOR_PCIE_ENGINE, + offsetof (TN_COMPLEX_CONFIG, Port4) - offsetof (TN_COMPLEX_CONFIG, GppWrapper), + offsetof (TN_COMPLEX_CONFIG, Port5) - offsetof (TN_COMPLEX_CONFIG, Port4), + 0 + }, + { PciePortEngine, 4, 4}, + 0, //Initialization Status + 0xFF, //Scratch + { + { + {0}, + 4, + 4, + 4, + 0, + GPP_CORE_ID, + 1, + {0}, + LinkStateResetExit, + 2, + 0, + 0 + }, + }, + }, + //Port 5 + { + { + DESCRIPTOR_PCIE_ENGINE, + offsetof (TN_COMPLEX_CONFIG, Port5) - offsetof (TN_COMPLEX_CONFIG, GppWrapper), + offsetof (TN_COMPLEX_CONFIG, Port6) - offsetof (TN_COMPLEX_CONFIG, Port5), + 0 + }, + { PciePortEngine, 5, 5}, + 0, //Initialization Status + 0xFF, //Scratch + { + { + {0}, + 5, + 5, + 5, + 0, + GPP_CORE_ID, + 2, + {0}, + LinkStateResetExit, + 3, + 0, + 0 + }, + }, + }, + //Port 6 + { + { + DESCRIPTOR_PCIE_ENGINE, + offsetof (TN_COMPLEX_CONFIG, Port6) - offsetof (TN_COMPLEX_CONFIG, GppWrapper), + offsetof (TN_COMPLEX_CONFIG, Port7) - offsetof (TN_COMPLEX_CONFIG, Port6), + 0 + }, + { PciePortEngine, 6, 6 }, + 0, //Initialization Status + 0xFF, //Scratch + { + { + {0}, + 6, + 6, + 6, + 0, + GPP_CORE_ID, + 3, + {0}, + LinkStateResetExit, + 4, + 0, + 0 + }, + }, + }, + //Port 7 + { + { + DESCRIPTOR_PCIE_ENGINE, + offsetof (TN_COMPLEX_CONFIG, Port7) - offsetof (TN_COMPLEX_CONFIG, GppWrapper), + offsetof (TN_COMPLEX_CONFIG, Port8) - offsetof (TN_COMPLEX_CONFIG, Port7), + 0 + }, + { PciePortEngine, 7, 7 }, + 0, //Initialization Status + 0xFF, //Scratch + { + { + {0}, + 7, + 7, + 7, + 0, + GPP_CORE_ID, + 4, + {0}, + LinkStateResetExit, + 5, + 0, + 0 + }, + }, + }, + //Port 8 + { + { + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_TERMINATE_LIST, + offsetof (TN_COMPLEX_CONFIG, Port8) - offsetof (TN_COMPLEX_CONFIG, GppWrapper), + offsetof (TN_COMPLEX_CONFIG, DpE) - offsetof (TN_COMPLEX_CONFIG, Port8), + 0 + }, + { PciePortEngine, 0, 3 }, + INIT_STATUS_PCIE_TRAINING_SUCCESS, //Initialization Status + 0xFF, //Scratch + { + { + {PortEnabled, 0, 8, 0, PcieGenMaxSupported, AspmL0sL1, HotplugDisabled, 0x0, {0}}, + 0, + 3, + 8, + 0, + GPP_CORE_ID, + 0, + {MAKE_SBDFO (0, 0, 8, 0, 0)}, + LinkStateTrainingSuccess, + 6, + 0, + 0 + }, + }, + }, + //DpE + { + { + DESCRIPTOR_DDI_ENGINE, + offsetof (TN_COMPLEX_CONFIG, DpE) - offsetof (TN_COMPLEX_CONFIG, DdiWrapper), + offsetof (TN_COMPLEX_CONFIG, DpF) - offsetof (TN_COMPLEX_CONFIG, DpE), + 0 + }, + {PcieDdiEngine}, + 0, //Initialization Status + 0xFF //Scratch + }, + //DpF + { + { + DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_TERMINATE_LIST, + offsetof (TN_COMPLEX_CONFIG, DpF) - offsetof (TN_COMPLEX_CONFIG, DdiWrapper), + offsetof (TN_COMPLEX_CONFIG, DpA) - offsetof (TN_COMPLEX_CONFIG, DpF), + 0 + }, + {PcieDdiEngine}, + 0, //Initialization Status + 0xFF //Scratch + }, + //DpA + { + { + DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY, + offsetof (TN_COMPLEX_CONFIG, DpA) - offsetof (TN_COMPLEX_CONFIG, Ddi2Wrapper), + 0, + 0 + }, + {PcieDdiEngine}, + 0, //Initialization Status + 0xFF //Scratch + }, + //F12 specific Silicon + { + OscFuses, + {0, 0, 0, 0, 0, 0} + } +}; + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.h new file mode 100644 index 0000000..623636c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.h @@ -0,0 +1,160 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific PCIe definitions + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _PCIECOMPLEXDATATN_H_ +#define _PCIECOMPLEXDATATN_H_ + +#define SOCKET_ID 0 + +#define MAX_NUM_PHYs 2 +#define MAX_NUM_LANE_PER_PHY 8 + +#define NUMBER_OF_PORTS 8 +#define NUMBER_OF_GPP_PORTS 5 +#define NUMBER_OF_GFX_PORTS 2 +#define NUMBER_OF_GFX_DDIS 3 +#define NUMBER_OF_DDIS 2 +#define NUMBER_OF_DDIS2 1 +#define NUMBER_OF_WRAPPERS 3 +#define NUMBER_OF_SILICONS 1 + +#define GFX_WRAP_ID 1 +#define GFX_NUMBER_OF_PIFs 2 +#define GFX_START_PHY_LANE 8 +#define GFX_END_PHY_LANE 23 +#define GFX_CORE_ID 2 + +#define GFX_CORE_x16 ((16 << 8) | 0) +#define GFX_CORE_x8x8 ((8 << 8) | 8) + +#define GPP_WRAP_ID 0 +#define GPP_NUMBER_OF_PIFs 1 +#define GPP_START_PHY_LANE 0 +#define GPP_END_PHY_LANE 7 +#define GPP_CORE_ID 1 + +#define GPP_CORE_x4x1x1x1x1 ((1ull << 32) | (1ull << 24) | (1ull << 16) | (1ull << 8) | (4ull << 0)) +#define GPP_CORE_x4x2x1x1 ((2ull << 32) | (1ull << 24) | (1ull << 16) | (0ull << 8) | (4ull << 0)) +#define GPP_CORE_x4x2x1x1_ST ((2ull << 32) | (0ull << 24) | (1ull << 16) | (1ull << 8) | (4ull << 0)) +#define GPP_CORE_x4x2x2 ((2ull << 32) | (2ull << 24) | (0ull << 16) | (0ull << 8) | (4ull << 0)) +#define GPP_CORE_x4x2x2_ST ((2ull << 32) | (0ull << 24) | (2ull << 16) | (0ull << 8) | (4ull << 0)) +#define GPP_CORE_x4x4 ((4ull << 32) | (0ull << 24) | (0ull << 16) | (0ull << 8) | (4ull << 0)) + +#define DDI_WRAP_ID 2 +#define DDI_NUMBER_OF_PIFs 1 +#define DDI_START_PHY_LANE 24 +#define DDI_END_PHY_LANE 31 + +#define DDI2_WRAP_ID 3 +#define DDI2_NUMBER_OF_PIFs 1 +#define DDI2_START_PHY_LANE 32 +#define DDI2_END_PHY_LANE 38 + +///Gen2 capability +typedef enum { + OscFuses, ///< Not capable + OscRO, ///< Gen2 with RO + OscLC, ///< Gen2 with LC + OscDefault, ///< Skip initialization of OSC +} OSC_MODE; + +///Family specific silicon configuration +typedef struct { + OSC_MODE OscMode; ///<OSC mode + UINT8 PortDevMap[6]; ///< Device number that has beed allocated already +} TN_PCIe_SILICON_CONFIG; + + +/// Complex Configuration +typedef struct { + PCIe_SILICON_CONFIG Silicon; ///< Silicon + PCIe_WRAPPER_CONFIG GfxWrapper; ///< Graphics Wrapper + PCIe_WRAPPER_CONFIG GppWrapper; ///< General Purpose Port + PCIe_WRAPPER_CONFIG DdiWrapper; ///< DDI + PCIe_WRAPPER_CONFIG Ddi2Wrapper; ///< DDI + PCIe_ENGINE_CONFIG Port2; ///< Port 2 + PCIe_ENGINE_CONFIG Port3; ///< Port 3 + PCIe_ENGINE_CONFIG DpB; ///< DPB + PCIe_ENGINE_CONFIG DpC; ///< DPC + PCIe_ENGINE_CONFIG DpD; ///< DPD + PCIe_ENGINE_CONFIG Port4; ///< Port 4 + PCIe_ENGINE_CONFIG Port5; ///< Port 5 + PCIe_ENGINE_CONFIG Port6; ///< Port 6 + PCIe_ENGINE_CONFIG Port7; ///< Port 7 + PCIe_ENGINE_CONFIG Port8; ///< Port 8 + PCIe_ENGINE_CONFIG DpE; ///< DPE + PCIe_ENGINE_CONFIG DpF; ///< DPF + PCIe_ENGINE_CONFIG DpA; ///< DPA + TN_PCIe_SILICON_CONFIG FmSilicon; ///< Fm Silicon +} TN_COMPLEX_CONFIG; + + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c new file mode 100644 index 0000000..8d687d9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c @@ -0,0 +1,1002 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific PCIe wrapper configuration services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbRegistersTN.h" +#include "GnbRegisterAccTN.h" +#include "PcieComplexDataTN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIECONFIGTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern TN_COMPLEX_CONFIG ComplexDataTN; +extern PCIe_PORT_DESCRIPTOR DefaultSbPort; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +PcieConfigureEnginesLaneAllocationTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIE_ENGINE_TYPE EngineType, + IN UINT8 ConfigurationId + ); + +AGESA_STATUS +STATIC +PcieConfigureGfxEnginesLaneAllocationTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIE_ENGINE_TYPE EngineType, + IN UINT8 ConfigurationId + ); + +AGESA_STATUS +STATIC +PcieConfigureGppEnginesLaneAllocationTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationId + ); + +AGESA_STATUS +STATIC +PcieConfigureDdiEnginesLaneAllocationTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationId + ); + +AGESA_STATUS +STATIC +PcieConfigureDdi2EnginesLaneAllocationTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationId + ); + +AGESA_STATUS +PcieGetCoreConfigurationValueTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 CoreId, + IN UINT64 ConfigurationSignature, + IN UINT8 *ConfigurationValue + ); + +BOOLEAN +PcieCheckPortPciDeviceMappingTN ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ); + +CONST CHAR8* +PcieDebugGetCoreConfigurationStringTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationValue + ); + +CONST CHAR8* +PcieDebugGetWrapperNameStringTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper + ); + +CONST CHAR8* +PcieDebugGetHostRegAddressSpaceStringTN ( + IN PCIe_SILICON_CONFIG *Silicon, + IN UINT16 AddressFrame + ); + +BOOLEAN +PcieCheckPortPcieLaneCanBeMuxedTN ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ); + +AGESA_STATUS +PcieMapPortPciAddressTN ( + IN PCIe_ENGINE_CONFIG *Engine + ); + +AGESA_STATUS +PcieGetComplexDataLengthTN ( + IN UINT8 SocketId, + OUT UINTN *Length, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PcieBuildComplexConfigurationTN ( + IN UINT8 SocketId, + OUT VOID *Buffer, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +PcieGetNativePhyLaneBitmapTN ( + IN UINT32 PhyLaneBitmap, + IN PCIe_ENGINE_CONFIG *Engine + ); + +AGESA_STATUS +PcieGetSbConfigInfoTN ( + IN UINT8 SocketId, + OUT PCIe_PORT_DESCRIPTOR *SbPort, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Configure engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] EngineType Engine Type + * @param[in] ConfigurationId Configuration ID + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_UNSUPPORTED No more configuration available for given engine type + * @retval AGESA_ERROR Requested configuration not supported + */ +AGESA_STATUS +PcieConfigureEnginesLaneAllocationTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIE_ENGINE_TYPE EngineType, + IN UINT8 ConfigurationId + ) +{ + AGESA_STATUS Status; + Status = AGESA_ERROR; + switch (Wrapper->WrapId) { + case GFX_WRAP_ID: + Status = PcieConfigureGfxEnginesLaneAllocationTN (Wrapper, EngineType, ConfigurationId); + break; + case GPP_WRAP_ID: + if (EngineType != PciePortEngine) { + return AGESA_UNSUPPORTED; + } + Status = PcieConfigureGppEnginesLaneAllocationTN (Wrapper, ConfigurationId); + break; + case DDI_WRAP_ID: + if (EngineType != PcieDdiEngine) { + return AGESA_UNSUPPORTED; + } + Status = PcieConfigureDdiEnginesLaneAllocationTN (Wrapper, ConfigurationId); + break; + case DDI2_WRAP_ID: + if (EngineType != PcieDdiEngine) { + return AGESA_UNSUPPORTED; + } + Status = PcieConfigureDdi2EnginesLaneAllocationTN (Wrapper, ConfigurationId); + break; + default: + ASSERT (FALSE); + } + return Status; +} + +CONST UINT8 GfxPortLaneConfigurationTable [][NUMBER_OF_GFX_PORTS * 2] = { +{0, 15, UNUSED_LANE_ID, UNUSED_LANE_ID}, +{0, 7, 8, 15} +}; + +/*----------------------------------------------------------------------------------------*/ +/** + * Configure GFX engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] ConfigurationId Configuration ID + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_ERROR Requested configuration not supported + */ + +AGESA_STATUS +STATIC +PcieConfigureGfxPortEnginesLaneAllocationTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationId + ) +{ + UINTN CoreLaneIndex; + PCIe_ENGINE_CONFIG *EnginesList; + if (ConfigurationId > ((sizeof (GfxPortLaneConfigurationTable) / (NUMBER_OF_GFX_PORTS * 2)) - 1)) { + return AGESA_ERROR; + } + EnginesList = PcieConfigGetChildEngine (Wrapper); + CoreLaneIndex = 0; + while (EnginesList != NULL) { + if (PcieLibIsPcieEngine (EnginesList)) { + PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED); + EnginesList->Type.Port.StartCoreLane = GfxPortLaneConfigurationTable [ConfigurationId][CoreLaneIndex++]; + EnginesList->Type.Port.EndCoreLane = GfxPortLaneConfigurationTable [ConfigurationId][CoreLaneIndex++]; + } + EnginesList = PcieLibGetNextDescriptor (EnginesList); + } + return AGESA_SUCCESS; +} + +CONST UINT8 GfxDdiLaneConfigurationTable [][NUMBER_OF_GFX_DDIS * 2] = { + {0, 7, 8, 15, UNUSED_LANE_ID, UNUSED_LANE_ID}, + {4, 7, 8, 15, UNUSED_LANE_ID, UNUSED_LANE_ID}, + {0, 7, 8, 11, 12, 15}, + {4, 7, 8, 11, 12, 15} +}; +/*----------------------------------------------------------------------------------------*/ +/** + * Configure GFX engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] ConfigurationId Configuration ID + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_ERROR Requested configuration not supported + */ + +AGESA_STATUS +STATIC +PcieConfigureGfxDdiEnginesLaneAllocationTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationId + ) +{ + UINTN LaneIndex; + PCIe_ENGINE_CONFIG *EnginesList; + if (ConfigurationId > ((sizeof (GfxDdiLaneConfigurationTable) / (NUMBER_OF_GFX_DDIS * 2)) - 1)) { + return AGESA_ERROR; + } + LaneIndex = 0; + EnginesList = PcieConfigGetChildEngine (Wrapper); + while (EnginesList != NULL) { + if (PcieLibIsDdiEngine (EnginesList)) { + PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED); + EnginesList->EngineData.StartLane = GfxDdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane; + EnginesList->EngineData.EndLane = GfxDdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane; + } + EnginesList = PcieLibGetNextDescriptor (EnginesList); + } + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Configure GFX engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] EngineType Engine Type + * @param[in] ConfigurationId Configuration ID + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_UNSUPPORTED Configuration not applicable + * @retval AGESA_ERROR Requested configuration not supported + */ + +AGESA_STATUS +STATIC +PcieConfigureGfxEnginesLaneAllocationTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIE_ENGINE_TYPE EngineType, + IN UINT8 ConfigurationId + ) +{ + AGESA_STATUS Status; + + switch (EngineType) { + case PciePortEngine: + Status = PcieConfigureGfxPortEnginesLaneAllocationTN (Wrapper, ConfigurationId); + break; + case PcieDdiEngine: + Status = PcieConfigureGfxDdiEnginesLaneAllocationTN (Wrapper, ConfigurationId); + break; + default: + Status = AGESA_UNSUPPORTED; + } + return Status; +} + + + +CONST UINT8 GppLaneConfigurationTable [][NUMBER_OF_GPP_PORTS * 2] = { +//4 5 6 7 8 (SB) + {4, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, + {4, 5, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, + {4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, + {4, 5, 6, 6, 7, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, + {4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 6, 7, 7, 0, 3}, + {4, 4, 5, 5, 6, 6, 7, 7, 0, 3} +}; + + +/*----------------------------------------------------------------------------------------*/ +/** + * Configure GFX engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] ConfigurationId Configuration ID + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_ERROR Requested configuration not supported + */ + + +AGESA_STATUS +STATIC +PcieConfigureGppEnginesLaneAllocationTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationId + ) +{ + PCIe_ENGINE_CONFIG *EnginesList; + UINTN CoreLaneIndex; + UINTN PortIdIndex; + if (ConfigurationId > ((sizeof (GppLaneConfigurationTable) / (NUMBER_OF_GPP_PORTS * 2)) - 1)) { + return AGESA_ERROR; + } + EnginesList = PcieConfigGetChildEngine (Wrapper); + CoreLaneIndex = 0; + PortIdIndex = 0; + while (EnginesList != NULL) { + PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED); + EnginesList->Type.Port.StartCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++]; + EnginesList->Type.Port.EndCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++]; + EnginesList = PcieLibGetNextDescriptor (EnginesList); + } + return AGESA_SUCCESS; +} + + +CONST UINT8 DdiLaneConfigurationTable [][NUMBER_OF_DDIS * 2] = { + {0, 3, 4, 7}, + {0, 7, UNUSED_LANE_ID, UNUSED_LANE_ID} +}; + +/*----------------------------------------------------------------------------------------*/ +/** + * Configure DDI engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] ConfigurationId Configuration ID + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_ERROR Requested configuration not supported + */ + + +AGESA_STATUS +STATIC +PcieConfigureDdiEnginesLaneAllocationTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationId + ) +{ + PCIe_ENGINE_CONFIG *EnginesList; + UINTN LaneIndex; + EnginesList = PcieConfigGetChildEngine (Wrapper); + if (ConfigurationId > ((sizeof (DdiLaneConfigurationTable) / (NUMBER_OF_DDIS * 2)) - 1)) { + return AGESA_ERROR; + } + LaneIndex = 0; + while (EnginesList != NULL) { + PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED); + EnginesList->EngineData.StartLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane; + EnginesList->EngineData.EndLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane; + EnginesList = PcieLibGetNextDescriptor (EnginesList); + } + return AGESA_SUCCESS; +} + + +CONST UINT8 Ddi2LaneConfigurationTable [][NUMBER_OF_DDIS2 * 2] = { + {0, 6}, + {0, 3} +}; + +/*----------------------------------------------------------------------------------------*/ +/** + * Configure DDI engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] ConfigurationId Configuration ID + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_ERROR Requested configuration not supported + */ + + +AGESA_STATUS +STATIC +PcieConfigureDdi2EnginesLaneAllocationTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationId + ) +{ + PCIe_ENGINE_CONFIG *EnginesList; + UINTN LaneIndex; + EnginesList = PcieConfigGetChildEngine (Wrapper); + if (ConfigurationId > ((sizeof (Ddi2LaneConfigurationTable) / (NUMBER_OF_DDIS2 * 2)) - 1)) { + return AGESA_ERROR; + } + LaneIndex = 0; + while (EnginesList != NULL) { + PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED); + EnginesList->EngineData.StartLane = Ddi2LaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane; + EnginesList->EngineData.EndLane = Ddi2LaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane; + EnginesList = PcieLibGetNextDescriptor (EnginesList); + } + return AGESA_SUCCESS; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get configuration Value for GFX wrapper + * + * + * + * @param[in] ConfigurationSignature Configuration signature + * @param[out] ConfigurationValue Configuration value + * @retval AGESA_SUCCESS Correct core configuration value returned by in *ConfigurationValue + * @retval AGESA_ERROR ConfigurationSignature is incorrect. + */ +STATIC AGESA_STATUS +PcieGetGfxConfigurationValueTN ( + IN UINT64 ConfigurationSignature, + OUT UINT8 *ConfigurationValue + ) +{ + switch (ConfigurationSignature) { + case GFX_CORE_x16: + *ConfigurationValue = 0; + break; + case GFX_CORE_x8x8: + *ConfigurationValue = 0x5; + break; + default: + ASSERT (FALSE); + return AGESA_ERROR; + } + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get configuration Value for GPP wrapper + * + * + * + * @param[in] ConfigurationSignature Configuration signature + * @param[out] ConfigurationValue Configuration value + * @retval AGESA_SUCCESS Correct core configuration value returned by in *ConfigurationValue + * @retval AGESA_ERROR ConfigurationSignature is incorrect + */ +STATIC AGESA_STATUS +PcieGetGppConfigurationValueTN ( + IN UINT64 ConfigurationSignature, + OUT UINT8 *ConfigurationValue + ) +{ + switch (ConfigurationSignature) { + case GPP_CORE_x4x1x1x1x1: + *ConfigurationValue = 0x4; + break; + case GPP_CORE_x4x2x1x1: + *ConfigurationValue = 0x3; + break; + case GPP_CORE_x4x2x2: + *ConfigurationValue = 0x2; + break; + case GPP_CORE_x4x4: + *ConfigurationValue = 0x1; + break; + default: + ASSERT (FALSE); + return AGESA_ERROR; + } + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get core configuration value + * + * + * + * @param[in] Wrapper Pointer to internal configuration data area + * @param[in] CoreId Core ID + * @param[in] ConfigurationSignature Configuration signature + * @param[out] ConfigurationValue Configuration value (for core configuration) + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_ERROR Core configuration value can not be determined + */ +AGESA_STATUS +PcieGetCoreConfigurationValueTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 CoreId, + IN UINT64 ConfigurationSignature, + IN UINT8 *ConfigurationValue + ) +{ + AGESA_STATUS Status; + + if (Wrapper->WrapId == GFX_WRAP_ID) { + Status = PcieGetGfxConfigurationValueTN (ConfigurationSignature, ConfigurationValue); + } else if (Wrapper->WrapId == GPP_WRAP_ID) { + Status = PcieGetGppConfigurationValueTN (ConfigurationSignature, ConfigurationValue); + } else { + Status = AGESA_ERROR; + } + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if engine can be remapped to Device/function number requested by user + * defined engine descriptor + * + * Function only called if requested device/function does not much native device/function + * + * @param[in] PortDescriptor Pointer to user defined engine descriptor + * @param[in] Engine Pointer engine configuration + * @retval TRUE Descriptor can be mapped to engine + * @retval FALSE Descriptor can NOT be mapped to engine + */ + +BOOLEAN +PcieCheckPortPciDeviceMappingTN ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + BOOLEAN Result; + if (PortDescriptor->Port.DeviceNumber >= 2 && PortDescriptor->Port.DeviceNumber <= 7 && PortDescriptor->Port.FunctionNumber == 0 && !PcieConfigIsSbPcieEngine (Engine)) { + Result = TRUE; + } else { + Result = FALSE; + } + return Result; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get core configuration string + * + * Debug function for logging configuration + * + * @param[in] Wrapper Pointer to internal configuration data area + * @param[in] ConfigurationValue Configuration value + * @retval Configuration string + */ + +CONST CHAR8* +PcieDebugGetCoreConfigurationStringTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationValue + ) +{ + switch (ConfigurationValue) { + case 0: + return "1x16"; + case 5: + return "2x8"; + case 4: + return "1x4, 4x1"; + case 3: + return "1x4, 1x2, 2x1"; + case 2: + return "1x4, 2x2"; + case 1: + return "1x4, 1x4"; + default: + break; + } + return " !!! Something Wrong !!!"; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get wrapper name + * + * Debug function for logging wrapper name + * + * @param[in] Wrapper Pointer to internal configuration data area + * @retval Wrapper Name string + */ + +CONST CHAR8* +PcieDebugGetWrapperNameStringTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper + ) +{ + switch (Wrapper->WrapId) { + case GPP_WRAP_ID: + return "GPPSB"; + case GFX_WRAP_ID: + return "GFX"; + case DDI_WRAP_ID: + return "DDI"; + case DDI2_WRAP_ID: + return "DDI2"; + default: + break; + } + return " !!! Something Wrong !!!"; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get register address name + * + * Debug function for logging register trace + * + * @param[in] Silicon Silicon config descriptor + * @param[in] AddressFrame Address Frame + * @retval Register address name + */ +CONST CHAR8* +PcieDebugGetHostRegAddressSpaceStringTN ( + IN PCIe_SILICON_CONFIG *Silicon, + IN UINT16 AddressFrame + ) +{ + switch (AddressFrame) { + case 0x130: + return "GPP WRAP"; + case 0x131: + return "GFX WRAP"; + case 0x132: + return "DDI WRAP"; + case 0x133: + return "DDI2 WRAP"; + case 0x110: + return "GPP PIF0"; + case 0x111: + return "GFX PIF0"; + case 0x211: + return "GFX PIF1"; + case 0x112: + return "DDI PIF0"; + case 0x113: + return "DDI2 PIF0"; + case 0x120: + return "GPP PHY0"; + case 0x121: + return "GFX PHY0"; + case 0x221: + return "GFX PHY1"; + case 0x122: + return "DDI PHY0"; + case 0x123: + return "DDI2 PHY0"; + case 0x101: + return "GPP CORE"; + case 0x201: + return "GFX CORE"; + default: + break; + } + return " !!! Something Wrong !!!"; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if the lane can be muxed by link width requested by user + * defined engine descriptor + * + * Check Engine StartCoreLane could be aligned by user requested link width(x1, x2, x4, x8, x16). + * Check Engine StartCoreLane could be aligned by user requested link width x2. + * + * @param[in] PortDescriptor Pointer to user defined engine descriptor + * @param[in] Engine Pointer engine configuration + * @retval TRUE Lane can be muxed + * @retval FALSE Lane can NOT be muxed + */ + +BOOLEAN +PcieCheckPortPcieLaneCanBeMuxedTN ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + UINT16 DescriptorHiLane; + UINT16 DescriptorLoLane; + UINT16 DescriptorNumberOfLanes; + PCIe_WRAPPER_CONFIG *Wrapper; + UINT16 NormalizedLoPhyLane; + BOOLEAN Result; + + Result = FALSE; + Wrapper = PcieConfigGetParentWrapper (Engine); + DescriptorLoLane = MIN (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane); + DescriptorHiLane = MAX (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane); + DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1; + + NormalizedLoPhyLane = DescriptorLoLane - Wrapper->StartPhyLane; + + if (NormalizedLoPhyLane == Engine->Type.Port.StartCoreLane) { + Result = TRUE; + } else { + if (((PortDescriptor->Port.MiscControls.SbLink == 0x0) && ((Engine->Type.Port.StartCoreLane % 2) == 0)) || (Engine->Type.Port.StartCoreLane == 0)) { + if (NormalizedLoPhyLane == 0) { + Result = TRUE; + } else { + if (((NormalizedLoPhyLane % 2) == 0) && ((NormalizedLoPhyLane % DescriptorNumberOfLanes) == 0)) { + Result = TRUE; + } + } + } + } + return Result; +} + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Map engine to specific PCI device address + * + * + * + * @param[in] Engine Pointer to engine configuration + * @retval AGESA_ERROR Fail to map PCI device address + * @retval AGESA_SUCCESS Successfully allocate PCI address + */ + +AGESA_STATUS +PcieMapPortPciAddressTN ( + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + AGESA_STATUS Status; + TN_COMPLEX_CONFIG *ComplexConfig; + PCIe_PLATFORM_CONFIG *Pcie; + UINT8 PortDevMap[6]; + UINT8 FreeDevMap[6]; + UINT8 PortIndex; + UINT8 EnginePortIndex; + UINT8 FreeIndex; + D0F0x64_x20_STRUCT D0F0x64_x20; + D0F0x64_x21_STRUCT D0F0x64_x21; + Status = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapPortPciAddressTN Enter\n"); + if (Engine->Type.Port.PortData.DeviceNumber == 0 && Engine->Type.Port.PortData.FunctionNumber == 0) { + Engine->Type.Port.PortData.DeviceNumber = Engine->Type.Port.NativeDevNumber; + Engine->Type.Port.PortData.FunctionNumber = Engine->Type.Port.NativeFunNumber; + } + if (!PcieConfigIsSbPcieEngine (Engine)) { + ComplexConfig = (TN_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_SILICON, &Engine->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header); + LibAmdMemFill (&FreeDevMap[0], 0x0, sizeof (FreeDevMap), GnbLibGetHeader (Pcie)); + LibAmdMemCopy (&PortDevMap[0], &ComplexConfig->FmSilicon.PortDevMap, sizeof (PortDevMap), GnbLibGetHeader (Pcie)); + for (PortIndex = 0; PortIndex < sizeof (PortDevMap); PortIndex++) { + if (PortDevMap[PortIndex] != 0) { + FreeDevMap[PortDevMap[PortIndex] - 2] = 1; + } + } + EnginePortIndex = Engine->Type.Port.PortData.DeviceNumber - 2; + if (FreeDevMap[EnginePortIndex] == 0) { + // Dev number not yet allocated + ComplexConfig->FmSilicon.PortDevMap[Engine->Type.Port.NativeDevNumber - 2] = Engine->Type.Port.PortData.DeviceNumber; + FreeDevMap[EnginePortIndex] = 1; + PortDevMap[Engine->Type.Port.NativeDevNumber - 2] = Engine->Type.Port.PortData.DeviceNumber; + for (PortIndex = 0; PortIndex < sizeof (PortDevMap); PortIndex++) { + if (PortDevMap[PortIndex] == 0) { + for (FreeIndex = 0; FreeIndex < sizeof (FreeDevMap); FreeIndex++) { + if (FreeDevMap[FreeIndex] == 0) { + FreeDevMap[FreeIndex] = 1; + break; + } + } + PortDevMap[PortIndex] = FreeIndex + 2; + } + } + + GnbRegisterReadTN (D0F0x64_x20_TYPE, D0F0x64_x20_ADDRESS, &D0F0x64_x20, 0, GnbLibGetHeader (Pcie)); + D0F0x64_x20.Field.ProgDevMapEn = 0; + GnbRegisterWriteTN (D0F0x64_x20_TYPE, D0F0x64_x20_ADDRESS, &D0F0x64_x20, 0, GnbLibGetHeader (Pcie)); + GnbRegisterReadTN (D0F0x64_x21_TYPE, D0F0x64_x21_ADDRESS, &D0F0x64_x21, 0, GnbLibGetHeader (Pcie)); + D0F0x64_x21.Field.GfxPortADevmap = PortDevMap[2 - 2]; + D0F0x64_x21.Field.GfxPortBDevmap = PortDevMap[3 - 2]; + D0F0x64_x20.Field.GppPortBDevmap = PortDevMap[4 - 2]; + D0F0x64_x20.Field.GppPortCDevmap = PortDevMap[5 - 2]; + D0F0x64_x20.Field.GppPortDDevmap = PortDevMap[6 - 2]; + D0F0x64_x20.Field.GppPortEDevmap = PortDevMap[7 - 2]; + D0F0x64_x20.Field.ProgDevMapEn = 0x1; + GnbRegisterWriteTN (D0F0x64_x20_TYPE, D0F0x64_x20_ADDRESS, &D0F0x64_x20, 0, GnbLibGetHeader (Pcie)); + GnbRegisterWriteTN (D0F0x64_x21_TYPE, D0F0x64_x21_ADDRESS, &D0F0x64_x21, 0, GnbLibGetHeader (Pcie)); + D0F0x64_x20.Field.ProgDevMapEn = 1; + GnbRegisterWriteTN (D0F0x64_x20_TYPE, D0F0x64_x20_ADDRESS, &D0F0x64_x20, 0, GnbLibGetHeader (Pcie)); + } else { + IDS_HDT_CONSOLE (GNB_TRACE, " Fail device %d to port %d\n", Engine->Type.Port.PortData.DeviceNumber, Engine->Type.Port.NativeDevNumber); + Status = AGESA_ERROR; + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapPortPciAddressTN Exit [0x%x]\n", Status); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get total number of silicons/wrappers/engines for this complex + * + * + * + * @param[in] SocketId Socket ID. + * @param[out] Length Length of configuration info block + * @param[out] StdHeader Standard configuration header + * @retval AGESA_SUCCESS Configuration data length is correct + */ +AGESA_STATUS +PcieGetComplexDataLengthTN ( + IN UINT8 SocketId, + OUT UINTN *Length, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *Length = sizeof (TN_COMPLEX_CONFIG); + return AGESA_SUCCESS; +} + + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Build configuration + * + * + * + * @param[in] SocketId Socket ID. + * @param[out] Buffer Pointer to buffer to build internal complex data structure + * @param[out] StdHeader Standard configuration header. + * @retval AGESA_SUCCESS Configuration data build successfully + */ +AGESA_STATUS +PcieBuildComplexConfigurationTN ( + IN UINT8 SocketId, + OUT VOID *Buffer, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + LibAmdMemCopy (Buffer, &ComplexDataTN, sizeof (TN_COMPLEX_CONFIG), StdHeader); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * get native PHY lane bitmap + * + * + * @param[in] PhyLaneBitmap Package PHY lane bitmap + * @param[in] Engine Standard configuration header. + * @retval Native PHY lane bitmap + */ +UINT32 +PcieGetNativePhyLaneBitmapTN ( + IN UINT32 PhyLaneBitmap, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + return PhyLaneBitmap; +} + +STATIC PCIe_PORT_DESCRIPTOR DefaultSbPortTN = { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeLowLoss, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmL0sL1, 0) +}; + +/*----------------------------------------------------------------------------------------*/ +/** + * Build default SB configuration descriptor + * + * + * @param[in] SocketId Socket Id + * @param[out] SbPort Pointer to SB configuration descriptor + * @param[in] StdHeader Standard configuration header. + * @retval AGESA_SUCCESS Configuration data build successfully + */ +AGESA_STATUS +PcieGetSbConfigInfoTN ( + IN UINT8 SocketId, + OUT PCIe_PORT_DESCRIPTOR *SbPort, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + LibAmdMemCopy (SbPort, &DefaultSbPortTN, sizeof (DefaultSbPortTN), StdHeader); + return AGESA_SUCCESS; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c new file mode 100644 index 0000000..642f41f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c @@ -0,0 +1,810 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 64781 $ @e $Date: 2012-01-30 21:19:50 -0600 (Mon, 30 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieTrainingV1.h" +#include "GnbPcieInitLibV1.h" +#include "GnbPcieInitLibV4.h" +#include "GnbNbInitLibV4.h" +#include "PcieLibTN.h" +#include "PcieComplexDataTN.h" +#include "GnbRegistersTN.h" +#include "GnbRegisterAccTN.h" +#include "cpuFamilyTranslation.h" +#include "cpuFamRegisters.h" +#include "F15TnPackageType.h" +#include "GeneralServices.h" +#include "Filecode.h" + +#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEEARLYINITTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; +extern CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA CoreInitTableTN; +extern CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA PcieInitEarlyTableTN; +extern CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitEarlyTableTN; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +PcieEarlyInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * PHY lane parameter Init + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Buffer Pointer to buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ +STATIC AGESA_STATUS +PciePhyLaneInitInitCallbackTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Phy; + UINT8 PhyLaneIndex; + UINT8 Lane; + UINT32 LaneBitmap; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLaneInitInitCallbackTN Enter\n"); + LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE, 0, Wrapper); + for (Lane = 0; Lane < Wrapper->NumberOfLanes; ++Lane) { + if ((LaneBitmap & (1 << Lane)) != 0) { + Phy = Lane / MAX_NUM_LANE_PER_PHY; + PhyLaneIndex = Lane - Phy * MAX_NUM_LANE_PER_PHY; + PcieRegisterRMW ( + Wrapper, + PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_400A_ADDRESS + PhyLaneIndex * 0x80), + D0F0xE4_PHY_400A_BiasDisInLs2_MASK | D0F0xE4_PHY_400A_Ls2ExitTime_MASK, + (1 << D0F0xE4_PHY_400A_BiasDisInLs2_OFFSET) | (1 << D0F0xE4_PHY_400A_Ls2ExitTime_OFFSET), + FALSE, + Pcie + ); + PcieRegisterRMW ( + Wrapper, + PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_4002_ADDRESS + PhyLaneIndex * 0x80), + D0F0xE4_PHY_4002_LfcMax_MASK, + (8 << D0F0xE4_PHY_4002_LfcMax_OFFSET), + FALSE, + Pcie + ); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLaneInitInitCallbackTN Exit\n"); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Satic init for various registers. + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +STATIC +PcieEarlyStaticInitTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINTN Index; + + for (Index = 0; Index < PcieInitEarlyTableTN.Length; Index++) { + GnbLibPciIndirectRMW ( + MAKE_SBDFO (0,0,0,0, D0F0xE0_ADDRESS), + PcieInitEarlyTableTN.Table[Index].Reg, + AccessWidth32, + (UINT32)~PcieInitEarlyTableTN.Table[Index].Mask, + PcieInitEarlyTableTN.Table[Index].Data, + GnbLibGetHeader (Pcie) + ); + } + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init core registers. + * + * + * @param[in] Wrapper Pointer to wrapper configuration descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +STATIC +PcieEarlyCoreInitTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 CoreId; + UINTN Index; + if (PcieLibIsPcieWrapper (Wrapper)) { + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyCoreInitTN Enter\n"); + for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { + for (Index = 0; Index < CoreInitTableTN.Length; Index++) { + UINT32 Value; + Value = PcieRegisterRead ( + Wrapper, + CORE_SPACE (CoreId, CoreInitTableTN.Table[Index].Reg), + Pcie + ); + Value &= (~CoreInitTableTN.Table[Index].Mask); + Value |= CoreInitTableTN.Table[Index].Data; + PcieRegisterWrite ( + Wrapper, + CORE_SPACE (CoreId, CoreInitTableTN.Table[Index].Reg), + Value, + FALSE, + Pcie + ); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyCoreInitTN Exit\n"); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set Dll Cap based on fuses + * + * + * + * @param[in] Wrapper Pointer to Wrapper configuration data area + * @param[in] Pcie Pointer to PCIe configuration data area + */ +STATIC VOID +PcieSetDllCapTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D18F3x1FC_STRUCT D18F3x1FC; + D0F0xE4_PHY_500F_STRUCT D0F0xE4_PHY_500F; + D0F0xE4_PHY_4010_STRUCT D0F0xE4_PHY_4010; + D0F0xE4_PHY_4011_STRUCT D0F0xE4_PHY_4011; + UINT32 Gen1Index; + UINT32 Gen2Index; + CPU_LOGICAL_ID LogicalId; + GNB_HANDLE *GnbHandle; + + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDllCapTN Enter\n"); + + D0F0xE4_PHY_500F.Value = 0; + GnbHandle = GnbGetHandle (GnbLibGetHeader (Pcie)); + ASSERT (GnbHandle != NULL); + GetLogicalIdOfSocket (GnbGetSocketId (GnbHandle), &LogicalId, GnbLibGetHeader (Pcie)); + + //Read SWDllCapTableEn + GnbRegisterReadTN (D18F3x1FC_TYPE, D18F3x1FC_ADDRESS, &D18F3x1FC, 0, GnbLibGetHeader (Pcie)); + IDS_HDT_CONSOLE (GNB_TRACE, "Read D18F3x1FC value %x\n", D18F3x1FC.Value); + + if ((D18F3x1FC.Field.SWDllCapTableEn != 0) || ((LogicalId.Revision & 0x0000000000000100ull ) != 0x0000000000000100ull )) { + IDS_HDT_CONSOLE (GNB_TRACE, "Executing DLL configuration\n"); + // Read D0F0xE4_x0[2:1]2[1:0]_[5:4][7:6,3:0][9,1]0 Phy Receiver Functional Fuse Control (FuseFuncDllProcessCompCtl[1:0]) + + IDS_HDT_CONSOLE (GNB_TRACE, "Reading 0x4010 from PHY_SPACE %x\n", PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4010_ADDRESS)); + D0F0xE4_PHY_4010.Value = PcieRegisterRead (Wrapper, PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4010_ADDRESS), Pcie); + IDS_HDT_CONSOLE (GNB_TRACE, "Read 4010 value = %x\n", D0F0xE4_PHY_4010.Value); + // Read D0F0xE4_x0[2:1]2[1:0]_[5:4][7:6,3:0][9,1]1 Phy Receiver Process Fuse Control (FuseProcDllProcessComp[2:0]) + IDS_HDT_CONSOLE (GNB_TRACE, "Reading 0x4011 from PHY_SPACE %x\n", PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4011_ADDRESS)); + D0F0xE4_PHY_4011.Value = PcieRegisterRead (Wrapper, PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4011_ADDRESS), Pcie); + IDS_HDT_CONSOLE (GNB_TRACE, "Read 4011 value = %x\n", D0F0xE4_PHY_4011.Value); + + // If FuseProcDllProcessCompCtl[1:0] == 2'b11 Then Gen1Index[3:0] = FuseProcDllProcessComp[2:0], 0 + // Else... + // If FuseProcDllProcessComp[2:0] == 3'b000 Then Gen1Index[3:0] =4'b1101 //Typical + // If FuseProcDllProcessComp[2:0] == 3'b001 Then Gen1Index[3:0] =4'b1111 //Fast + // If FuseProcDllProcessComp[2:0] == 3'b010 Then Gen1Index[3:0] =4'b1010 //Slow + IDS_HDT_CONSOLE (GNB_TRACE, "FuseFuncDllProcessCompCtl %x\n", D0F0xE4_PHY_4010.Field.FuseFuncDllProcessCompCtl); + if (D0F0xE4_PHY_4010.Field.FuseFuncDllProcessCompCtl == 3) { + IDS_HDT_CONSOLE (GNB_TRACE, "Setting Gen1Index from FuseFuncDllProcessComp %x\n", D0F0xE4_PHY_4011.Field.FuseProcDllProcessComp); + Gen1Index = D0F0xE4_PHY_4011.Field.FuseProcDllProcessComp << 1; + } else { + IDS_HDT_CONSOLE (GNB_TRACE, "Setting Gen1Index from switch case..."); + switch (D0F0xE4_PHY_4011.Field.FuseProcDllProcessComp) { + case 0: + IDS_HDT_CONSOLE (GNB_TRACE, "case 0 - using 0xd\n"); + Gen1Index = 0xd; + break; + case 1: + IDS_HDT_CONSOLE (GNB_TRACE, "case 1 - using 0xf\n"); + Gen1Index = 0xf; + break; + case 2: + IDS_HDT_CONSOLE (GNB_TRACE, "case 2 - using 0xa\n"); + Gen1Index = 0xa; + break; + default: + IDS_HDT_CONSOLE (GNB_TRACE, "default - using 0xd\n"); + Gen1Index = 0xd; //Use typical for default case + break; + } + } + D0F0xE4_PHY_500F.Field.DllProcessFreqCtlIndex1 = Gen1Index; + IDS_HDT_CONSOLE (GNB_TRACE, "Set Gen1Index to %x\n", Gen1Index); + // Bits 3:0 = Gen1Index[3:0] + // Bits 10:7 = DllProcessFreqCtlIndex2Rate50[3:0] + if (D18F3x1FC.Field.SWDllCapTableEn != 0) { + IDS_HDT_CONSOLE (GNB_TRACE, "Gen2Index - using DllProcFreqCtlIndex2Rate50 = %x\n", D18F3x1FC.Field.DllProcFreqCtlIndex2Rate50); + Gen2Index = D18F3x1FC.Field.DllProcFreqCtlIndex2Rate50; + } else { + Gen2Index = 0x03; // Hard coded default + } + D0F0xE4_PHY_500F.Field.DllProcessFreqCtlIndex2 = Gen2Index; + IDS_HDT_CONSOLE (GNB_TRACE, "Set Gen2Index to %x\n", Gen2Index); + PcieRegisterWrite ( + Wrapper, + PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_500F_ADDRESS), + D0F0xE4_PHY_500F.Value, + FALSE, + Pcie + ); + // Set DllProcessFreqCtlOverride on second write + D0F0xE4_PHY_500F.Field.DllProcessFreqCtlOverride = 1; + PcieRegisterWrite ( + Wrapper, + PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_500F_ADDRESS), + D0F0xE4_PHY_500F.Value, + FALSE, + Pcie + ); + if (Wrapper->WrapId == 1) { + // For Wrapper 1, configure PHY0 and PHY1 + D0F0xE4_PHY_500F.Field.DllProcessFreqCtlOverride = 0; + PcieRegisterWrite ( + Wrapper, + PHY_SPACE (Wrapper->WrapId, 1, D0F0xE4_PHY_500F_ADDRESS), + D0F0xE4_PHY_500F.Value, + FALSE, + Pcie + ); + // Set DllProcessFreqCtlOverride on second write + D0F0xE4_PHY_500F.Field.DllProcessFreqCtlOverride = 1; + PcieRegisterWrite ( + Wrapper, + PHY_SPACE (Wrapper->WrapId, 1, D0F0xE4_PHY_500F_ADDRESS), + D0F0xE4_PHY_500F.Value, + FALSE, + Pcie + ); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDllCapTN Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * TN FP2 PCIE allocation x8 check + * + * + * + * @param[in] Wrapper Pointer to wrapper configuration descriptor + * @param[in] Buffer Pointer buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ + + +STATIC AGESA_STATUS +PcieFP2x8CheckCallbackTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 LaneBitmap; + AGESA_STATUS Status; + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieFP2x8CheckCallbackTN Enter\n"); + + Status = AGESA_SUCCESS; + if (Wrapper->WrapId == GFX_WRAP_ID) { + + LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE | LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper); + IDS_HDT_CONSOLE (GNB_TRACE, "FP2 GFX Wrpper phy LaneBitmap = %x\n", LaneBitmap); + + if (((LaneBitmap & 0xFF) != 0) && ((LaneBitmap & 0xFF00) != 0)) { + IDS_HDT_CONSOLE (GNB_TRACE, "Error!! FP2 GFX Wrpper cannot use both phy#\n"); + Status = AGESA_ERROR; + PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper); + PutEventLog ( + AGESA_ERROR, + GNB_EVENT_INVALID_LANES_CONFIGURATION, + (LibAmdBitScanForward (LaneBitmap) + Wrapper->StartPhyLane), + (LibAmdBitScanReverse (LaneBitmap) + Wrapper->StartPhyLane), + 0, + 0, + GnbLibGetHeader (Pcie) + ); + + ASSERT (FALSE); + } + } + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieFP2x8CheckCallbackTN Exit\n"); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * TN FP2 PCIE critera check + * + * + * + * @param[in] Pcie Pointer to PICe configuration data area + */ + + +STATIC AGESA_STATUS +PcieFP2CriteriaTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieFP2CriteriaTN Enter\n"); + + // PACKAGE_TYPE_FP2 1 + // PACKAGE_TYPE_FS1r2 2 + // PACKAGE_TYPE_FM2 4 + if (LibAmdGetPackageType (GnbLibGetHeader (Pcie)) != PACKAGE_TYPE_FP2) { + return AGESA_SUCCESS; + } + // FP2 force gen1 + Pcie->PsppPolicy = PsppPowerSaving; + // FP2 only use x8 on the same PHY + Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieFP2x8CheckCallbackTN, NULL, Pcie); + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieFP2CriteriaTN Exit\n"); + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * RX offset cancellation enablement + * + * + * + * @param[in] Wrapper Pointer to Wrapper configuration data area + * @param[in] Pcie Pointer to PCIe configuration data area + */ +STATIC VOID +PcieOffsetCancelCalibration ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 LaneBitmap; + D0F0xBC_x1F39C_STRUCT D0F0xBC_x1F39C; + + LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper); + if ((Wrapper->WrapId != GFX_WRAP_ID) && (Wrapper->WrapId != GPP_WRAP_ID)) { + return; + } + + if (LaneBitmap != 0) { + D0F0xBC_x1F39C.Value = 0; + D0F0xBC_x1F39C.Field.Tx = 1; + D0F0xBC_x1F39C.Field.Rx = 1; + D0F0xBC_x1F39C.Field.UpperLaneID = LibAmdBitScanReverse (LaneBitmap) + Wrapper->StartPhyLane; + D0F0xBC_x1F39C.Field.LowerLaneID = LibAmdBitScanForward (LaneBitmap) + Wrapper->StartPhyLane; + GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE, D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie)); + GnbSmuServiceRequestV4 ( + PcieConfigGetParentSilicon (Wrapper)->Address, + SMC_MSG_PHY_LN_OFF, + GNB_REG_ACC_FLAG_S3SAVE, + GnbLibGetHeader (Pcie) + ); + GnbSmuServiceRequestV4 ( + PcieConfigGetParentSilicon (Wrapper)->Address, + SMC_MSG_PHY_LN_ON, + GNB_REG_ACC_FLAG_S3SAVE, + GnbLibGetHeader (Pcie) + ); + } + PcieTopologyLaneControl ( + EnableLanes, + PcieUtilGetWrapperLaneBitMap (LANE_TYPE_ALL, 0, Wrapper), + Wrapper, + Pcie + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Per wrapper Pcie Init SRBM reset prior Aaccess to wrapper registers. + * + * + * @param[in] Wrapper Pointer to wrapper configuration descriptor + * @param[in] Buffer Pointer buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ +STATIC AGESA_STATUS +PcieInitSrbmCallbackTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie); + PcieOffsetCancelCalibration (Wrapper, Pcie); + PciePifApplyGanging (Wrapper, Pcie); + PciePhyApplyGanging (Wrapper, Pcie); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PHY Pll Personality Init Callback + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Buffer Pointer to buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ +STATIC AGESA_STATUS +PciePhyLetPllPersonalityInitCallbackTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLetPllPersonalityInitCallbackTN Enter\n"); + PciePifPllPowerControl (PowerDownPifs, Wrapper, Pcie); + PciePifSetPllRampTime (NormalRampup, Wrapper, Pcie); + PciePollPifForCompeletion (Wrapper, Pcie); + PcieTopologyLaneControl ( + DisableLanes, + PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper), + Wrapper, + Pcie + ); + PciePollPifForCompeletion (Wrapper, Pcie); + PcieSetPhyPersonalityTN (Wrapper, Pcie); + PcieWrapSetTxS1CtrlForLaneMux (Wrapper, Pcie); + PciePollPifForCompeletion (Wrapper, Pcie); + PcieTopologyLaneControl ( + EnableLanes, + PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, 0, Wrapper), + Wrapper, + Pcie + ); + PcieWrapSetTxOffCtrlForLaneMux (Wrapper, Pcie); + PciePollPifForCompeletion (Wrapper, Pcie); + PciePifPllPowerControl (PowerUpPifs, Wrapper, Pcie); + IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLetPllPersonalityInitCallbackTN Exit\n"); + return AGESA_SUCCESS; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Per wrapper Pcie Init prior training. + * + * + * @param[in] Wrapper Pointer to wrapper configuration descriptor + * @param[in] Buffer Pointer buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ +AGESA_STATUS +STATIC +PcieEarlyInitCallbackTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + BOOLEAN CoreConfigChanged; + BOOLEAN PllConfigChanged; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCallbackTN Enter\n"); + CoreConfigChanged = FALSE; + PllConfigChanged = FALSE; + PcieTopologyPrepareForReconfig (Wrapper, Pcie); + Status = PcieTopologySetCoreConfig (Wrapper, &CoreConfigChanged, Pcie); + ASSERT (Status == AGESA_SUCCESS); + PcieTopologyApplyLaneMux (Wrapper, Pcie); + PciePifSetRxDetectPowerMode (Wrapper, Pcie); + PciePifSetLs2ExitTime (Wrapper, Pcie); + PcieTopologySelectMasterPll (Wrapper, &PllConfigChanged, Pcie); + if (CoreConfigChanged || PllConfigChanged) { + PcieTopologyExecuteReconfigV4 (Wrapper, Pcie); + } + PcieTopologyCleanUpReconfig (Wrapper, Pcie); + PcieTopologySetLinkReversalV4 (Wrapper, Pcie); + + if (Wrapper->Features.PowerOffUnusedPlls != 0) { + PciePifPllPowerDown ( + PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC | LANE_TYPE_DDI_PHY_NATIVE, Wrapper), + Wrapper, + Pcie + ); + PciePifPllInitForDdi (Wrapper, Pcie); + PciePwrPowerDownDdiPllsV4 (Wrapper, Pcie); + } + PcieTopologyLaneControl ( + DisableLanes, + PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC, Wrapper), + Wrapper, + Pcie + ); + PcieSetDdiOwnPhyV4 (Wrapper, Pcie); + PciePollPifForCompeletion (Wrapper, Pcie); + PciePhyAvertClockPickers (Wrapper, Pcie); + PcieEarlyCoreInitTN (Wrapper, Pcie); + PcieSetSsidV4 (UserOptions.CfgGnbPcieSSID, Wrapper, Pcie); + if (PcieConfigIsPcieWrapper (Wrapper)) { + PcieSetDllCapTN (Wrapper, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCallbackTN Exit [%x]\n", Status); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Pcie Init + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Topology successfully mapped + * @retval AGESA_ERROR Topology can not be mapped + */ + +AGESA_STATUS +STATIC +PcieEarlyInitTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitTN Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = PcieFP2CriteriaTN (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieInitSrbmCallbackTN, NULL, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + PcieEarlyStaticInitTN (Pcie); + Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PciePhyLetPllPersonalityInitCallbackTN, NULL, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + PcieOscInitTN (Pcie); + Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PciePhyLaneInitInitCallbackTN, NULL, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieEarlyInitCallbackTN, NULL, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + PcieSetVoltageTN (PcieGen1, Pcie); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitTN Exit [%x]\n", AgesaStatus); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all active ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieEarlyPortInitCallbackTN ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackTN Enter\n"); + ASSERT (Engine->EngineData.EngineType == PciePortEngine); + PciePortProgramRegisterTable (PortInitEarlyTableTN.Table, PortInitEarlyTableTN.Length, Engine, FALSE, Pcie); + PcieSetLinkSpeedCapV4 (PcieGen1, Engine, Pcie); + PcieSetLinkWidthCap (Engine, Pcie); + PcieCompletionTimeout (Engine, Pcie); + PcieLinkSetSlotCap (Engine, Pcie); + PcieLinkInitHotplug (Engine, Pcie); + //PciePhyChannelCharacteristic (Engine, Pcie); + if (Engine->Type.Port.PortData.PortPresent == PortDisabled || + (Engine->Type.Port.PortData.EndpointStatus == EndpointNotPresent && + Engine->Type.Port.PortData.LinkHotplug != HotplugEnhanced && + Engine->Type.Port.PortData.LinkHotplug != HotplugServer)) { + ASSERT (!PcieConfigIsSbPcieEngine (Engine)); + // + // Pass endpoint tstaus in scratch + // + PciePortRegisterRMW ( + Engine, + DxF0xE4_x01_ADDRESS, + 0x1, + 0x1, + FALSE, + Pcie + ); + PcieTrainingSetPortState (Engine, LinkStateDeviceNotPresent, FALSE, Pcie); + } + if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { + PcieTrainingSetPortState (Engine, LinkStateTrainingCompleted, FALSE, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackTN Exit\n"); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Master procedure to init various features on all active ports + * + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ + +AGESA_STATUS +STATIC +PcieEarlyPortInitTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + // Leave all device in Presence Detect Presence state for distributed training will be completed at PciePortPostEarlyInit + if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) { + Pcie->TrainingExitState = LinkStateResetExit; + } + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieEarlyPortInitCallbackTN, + NULL, + Pcie + ); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Early Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +PcieEarlyInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + PCIe_PLATFORM_CONFIG *Pcie; + AgesaStatus = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInterfaceTN Enter\n"); + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + PciePortsVisibilityControlTN (UnhidePorts, Pcie); + + Status = PcieEarlyInitTN (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieEarlyPortInitTN (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieTraining (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_PHY_CONFIG, Pcie, StdHeader); + PciePortsVisibilityControlTN (HidePorts, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInterfaceTN Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c new file mode 100644 index 0000000..f0cf287 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c @@ -0,0 +1,122 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "S3SaveState.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEENVINITTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +PcieEnvInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Env Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +PcieEnvInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + S3_SAVE_DISPATCH (StdHeader, PcieLateRestoreTNS3Script_ID, 0, NULL); + return AGESA_SUCCESS; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c new file mode 100644 index 0000000..3d00bdb --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c @@ -0,0 +1,639 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * TN specific PCIe configuration data services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbFuseTable.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "GnbSbLib.h" +#include "GnbPcieInitLibV1.h" +#include "GnbPcieConfig.h" +#include "GnbPcieTrainingV1.h" +#include "GnbNbInitLibV4.h" +#include "GnbNbInitLibV1.h" +#include "PcieComplexDataTN.h" +#include "PcieLibTN.h" +#include "GnbRegistersTN.h" +#include "GnbRegisterAccTN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIELIBTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +PCIE_LINK_SPEED_CAP +PcieGetLinkSpeedCapTN ( + IN UINT32 Flags, + IN PCIe_ENGINE_CONFIG *Engine + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Control port visibility in PCI config space + * + * + * @param[in] Control Make port Hide/Unhide ports + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PciePortsVisibilityControlTN ( + IN PCIE_PORT_VISIBILITY Control, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_SILICON_CONFIG *Silicon; + Silicon = (PCIe_SILICON_CONFIG *) PcieConfigGetChild (DESCRIPTOR_SILICON, &Pcie->Header); + ASSERT (Silicon != NULL); + switch (Control) { + case UnhidePorts: + PcieSiliconUnHidePorts (Silicon, Pcie); + break; + case HidePorts: + PcieSiliconHidePorts (Silicon, Pcie); + break; + default: + ASSERT (FALSE); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Power down inactive lanes + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PciePowerDownPllInL1TN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + + UINT32 LaneBitmapForPllOffInL1; + UINT32 ActiveLaneBitmap; + UINT8 PllPowerUpLatency; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerDownPllInL1TN Enter\n"); + ActiveLaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, Wrapper); + if (ActiveLaneBitmap != 0) { + PllPowerUpLatency = PciePifGetPllPowerUpLatencyTN (Wrapper, Pcie); + LaneBitmapForPllOffInL1 = PcieLanesToPowerDownPllInL1 (PllPowerUpLatency, Wrapper, Pcie); + if ((LaneBitmapForPllOffInL1 != 0) && ((ActiveLaneBitmap & LaneBitmapForPllOffInL1) == ActiveLaneBitmap)) { + LaneBitmapForPllOffInL1 &= PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, 0, Wrapper); + LaneBitmapForPllOffInL1 |= PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL, 0, Wrapper); + PciePifSetPllModeForL1 (LaneBitmapForPllOffInL1, Wrapper, Pcie); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerDownPllInL1TN Exit\n"); +} + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Request boot up voltage + * + * + * + * @param[in] LinkCap Global GEN capability + * @param[in] Pcie Pointer to PCIe configuration data area + */ +VOID +PcieSetVoltageTN ( + IN PCIE_LINK_SPEED_CAP LinkCap, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 TargetVid; + D0F0xBC_xE010705C_STRUCT D0F0xBC_xE010705C; + GMMx63C_STRUCT GMMx63C; + GMMx640_STRUCT GMMx640; + UINT8 MinVidIndex; + D0F0xBC_xE0001008_STRUCT D0F0xBC_xE0001008; + UINT8 SclkVid[4]; + UINT8 Index; + PP_FUSE_ARRAY *PpFuseArray; + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetVoltageTN Enter\n"); + PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Pcie)); + if (PpFuseArray == NULL) { + GnbRegisterReadTN (D0F0xBC_xE0001008_TYPE, D0F0xBC_xE0001008_ADDRESS, &D0F0xBC_xE0001008, 0, GnbLibGetHeader (Pcie)); + SclkVid[0] = (UINT8) D0F0xBC_xE0001008.Field.SClkVid0; + SclkVid[1] = (UINT8) D0F0xBC_xE0001008.Field.SClkVid1; + SclkVid[2] = (UINT8) D0F0xBC_xE0001008.Field.SClkVid2; + SclkVid[3] = (UINT8) D0F0xBC_xE0001008.Field.SClkVid3; + GnbRegisterReadTN (TYPE_D0F0xBC, D0F0xBC_xE010705C_ADDRESS, &D0F0xBC_xE010705C, 0, GnbLibGetHeader (Pcie)); + Index = (UINT8) D0F0xBC_xE010705C.Field.PcieGen2Vid; + } else { + SclkVid[0] = PpFuseArray->SclkVid[0]; + SclkVid[1] = PpFuseArray->SclkVid[1]; + SclkVid[2] = PpFuseArray->SclkVid[2]; + SclkVid[3] = PpFuseArray->SclkVid[3]; + Index = PpFuseArray->PcieGen2Vid; + } + if (LinkCap > PcieGen1) { + ASSERT (SclkVid[Index] != 0); + TargetVid = SclkVid[Index]; + } else { + + MinVidIndex = 0; + for (Index = 0; Index < 4; Index++) { + if (SclkVid[Index] > SclkVid[MinVidIndex]) { + MinVidIndex = (UINT8) Index; + } + } + ASSERT (SclkVid[MinVidIndex] != 0); + TargetVid = SclkVid[MinVidIndex]; + } + IDS_HDT_CONSOLE (PCIE_MISC, " Set Voltage for Gen %d, Vid code %d\n", LinkCap, TargetVid); + + GnbRegisterReadTN (GMMx63C_TYPE, GMMx63C_ADDRESS, &GMMx63C, 0, GnbLibGetHeader (Pcie)); + //Wait for voltage change to complete before it can issue next voltage change request + do { + GnbRegisterReadTN (GMMx640_TYPE, GMMx640_ADDRESS, &GMMx640, 0, GnbLibGetHeader (Pcie)); + } while (GMMx640.Field.VoltageChangeAck != GMMx63C.Field.VoltageChangeReq); + //Enable voltage client + if (LinkCap == PcieGen1) { + GMMx63C.Field.VoltageChangeEn = 0; + } else { + GMMx63C.Field.VoltageChangeEn = 1; + } + GnbRegisterWriteTN (GMMx63C_TYPE, GMMx63C_ADDRESS, &GMMx63C, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie)); + //Program level and toggle request + GMMx63C.Field.VoltageLevel = TargetVid; + GMMx63C.Field.VoltageChangeReq = !GMMx63C.Field.VoltageChangeReq; + GnbRegisterWriteTN (GMMx63C_TYPE, GMMx63C_ADDRESS, &GMMx63C, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie)); + //Wait for voltage change to complete before it can issue next voltage change request + do { + GnbRegisterReadTN (GMMx640_TYPE, GMMx640_ADDRESS, &GMMx640, 0, GnbLibGetHeader (Pcie)); + } while (GMMx640.Field.VoltageChangeAck != GMMx63C.Field.VoltageChangeReq); + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetVoltageTN Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PLL power up latency + * + * + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Pcie Pointer to PICe configuration data area + * @retval Pll wake up latency in us + */ +UINT8 +PciePifGetPllPowerUpLatencyTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + return 35; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get max link speed capability supported by this port + * + * + * + * @param[in] Flags See Flags PCIE_PORT_GEN_CAP_BOOT / PCIE_PORT_GEN_CAP_MAX + * @param[in] Engine Pointer to engine config descriptor + * @retval PcieGen1/PcieGen2 Max supported link gen capability + */ +PCIE_LINK_SPEED_CAP +PcieGetLinkSpeedCapTN ( + IN UINT32 Flags, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + PCIE_LINK_SPEED_CAP LinkSpeedCapability; + TN_COMPLEX_CONFIG *ComplexData; + PCIe_PLATFORM_CONFIG *Pcie; + + ASSERT (Engine->Type.Port.PortData.LinkSpeedCapability < MaxPcieGen); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header); + LinkSpeedCapability = PcieGen2; + ComplexData = (TN_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_SILICON, &Engine->Header); + if (ComplexData->FmSilicon.OscMode == OscRO || ComplexData->FmSilicon.OscMode == OscLC || ComplexData->FmSilicon.OscMode == OscDefault) { + LinkSpeedCapability = PcieGen2; + } else { + LinkSpeedCapability = PcieGen1; + } + if (Engine->Type.Port.PortData.LinkSpeedCapability == PcieGenMaxSupported) { + Engine->Type.Port.PortData.LinkSpeedCapability = (UINT8) LinkSpeedCapability; + } + if (Pcie->PsppPolicy == PsppPowerSaving) { + LinkSpeedCapability = PcieGen1; + } + if (Engine->Type.Port.PortData.LinkSpeedCapability < LinkSpeedCapability) { + LinkSpeedCapability = Engine->Type.Port.PortData.LinkSpeedCapability; + } + if ((Flags & PCIE_PORT_GEN_CAP_BOOT) != 0) { + if ((Pcie->PsppPolicy == PsppBalanceLow || Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) && !PcieConfigIsSbPcieEngine (Engine)) { + LinkSpeedCapability = PcieGen1; + } + } + return LinkSpeedCapability; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Set PLL personality + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieSetPhyPersonalityTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Phy; + UINT8 Mode; + if (Wrapper->WrapId == GFX_WRAP_ID || Wrapper->WrapId == DDI_WRAP_ID || Wrapper->WrapId == DDI2_WRAP_ID) { + for (Phy = 0; Phy < Wrapper->NumberOfPIFs; Phy++) { + if (Wrapper->WrapId == GFX_WRAP_ID) { + Mode = (Phy == 0)? 0x1 : 0; + } else { + Mode = 0x2; + } + PcieRegisterWriteField ( + Wrapper, + PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_2005_ADDRESS), + D0F0xE4_PHY_2005_PllMode_OFFSET, + D0F0xE4_PHY_2005_PllMode_WIDTH, + Mode, + FALSE, + Pcie + ); + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * DCC recalibration + * + * + * + * @param[in] Wrapper Pointer to internal configuration data area + * @param[in,out] Buffer Pointer to buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ + +STATIC AGESA_STATUS +PcieForceDccRecalibrationCallbackTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PciePhyForceDccRecalibration (Wrapper, Pcie); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Prepare for Osc switch + * + * + * + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Buffer Pointer to buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ + +STATIC AGESA_STATUS +PcieOscPifInitPrePowerdownCallback ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PciePifFullPowerStateControl (PowerDownPifs, Wrapper, Pcie); + PcieTopologyLaneControl ( + DisableLanes, + PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper), + Wrapper, + Pcie + ); + PciePifSetPllRampTime (LongRampup, Wrapper, Pcie); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Do Osc switch + * + * + * + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Buffer Pointer to buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ + +STATIC AGESA_STATUS +PcieOscInitPllModeCallback ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + TN_COMPLEX_CONFIG *ComplexData; + TN_PCIe_SILICON_CONFIG *FmSilicon; + UINT8 Phy; + ComplexData = (TN_COMPLEX_CONFIG *) PcieConfigGetParentSilicon (Wrapper); + ASSERT (ComplexData != NULL); + FmSilicon = &ComplexData->FmSilicon; + if (Wrapper->WrapId == GFX_WRAP_ID) { + Phy = 1; + } else if (Wrapper->WrapId == GPP_WRAP_ID) { + Phy = 0; + } else { + ASSERT (FALSE); + return AGESA_ERROR; + } + switch (FmSilicon->OscMode) { + case OscLC: + PcieRegisterWriteField ( + Wrapper, + PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_2002_ADDRESS), + D0F0xE4_PHY_2002_IsLc_OFFSET, + D0F0xE4_PHY_2002_IsLc_WIDTH, + 0x1, + FALSE, + Pcie + ); + break; + case OscRO: + PcieRegisterWriteField ( + Wrapper, + PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_2002_ADDRESS), + D0F0xE4_PHY_2002_RoCalEn_OFFSET, + D0F0xE4_PHY_2002_RoCalEn_WIDTH, + 0x0, + FALSE, + Pcie + ); + PcieRegisterWriteField ( + Wrapper, + PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_2002_ADDRESS), + D0F0xE4_PHY_2002_RoCalEn_OFFSET, + D0F0xE4_PHY_2002_RoCalEn_WIDTH, + 0x1, + FALSE, + Pcie + ); + break; + default: + ASSERT (FALSE); + } + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Post Osc init + * + * + * + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Buffer Pointer to buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ + +STATIC AGESA_STATUS +PcieOscPifInitPostPowerdownCallback ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PcieWrapSetTxS1CtrlForLaneMux (Wrapper, Pcie); + PciePollPifForCompeletion (Wrapper, Pcie); + PcieTopologyLaneControl ( + EnableLanes, + PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, 0, Wrapper), + Wrapper, + Pcie + ); + PcieWrapSetTxOffCtrlForLaneMux (Wrapper, Pcie); + PciePollPifForCompeletion (Wrapper, Pcie); + PciePifSetPllRampTime (NormalRampup, Wrapper, Pcie); + PciePifFullPowerStateControl (PowerUpPifs, Wrapper, Pcie); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Prepare PHY for Gen2 + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PcieOscInitTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + TN_COMPLEX_CONFIG *ComplexData; + TN_PCIe_SILICON_CONFIG *FmSilicon; + D0F0xE4_WRAP_FFF1_STRUCT D0F0xE4_WRAP_FFF1; + AGESA_STATUS Status; + UINT8 SaveSbLinkAspm; + UINT32 Value; + + Value = 0; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieOscInitTN Enter\n"); + ComplexData = (TN_COMPLEX_CONFIG *) PcieConfigGetChild (DESCRIPTOR_SILICON, &Pcie->Header); + ASSERT (ComplexData != NULL); + FmSilicon = &ComplexData->FmSilicon; + + IDS_HDT_CONSOLE (GNB_TRACE, " OSC Mode - %s\n", + (FmSilicon->OscMode == OscFuses) ? "Fuses" : ( + (FmSilicon->OscMode == OscRO) ? "RO" : ( + (FmSilicon->OscMode == OscLC) ? "LC" : ( + (FmSilicon->OscMode == OscDefault) ? "Skip" : "Unknown"))) + ); + + if (FmSilicon->OscMode == OscFuses) { + D0F0xE4_WRAP_FFF1.Value = PcieRegisterRead ( + &ComplexData->GppWrapper, + WRAP_SPACE (ComplexData->GppWrapper.WrapId, D0F0xE4_WRAP_FFF1_ADDRESS), + Pcie + ); + + if (D0F0xE4_WRAP_FFF1.Field.ROSupportGen2) { + FmSilicon->OscMode = OscRO; + } else if (D0F0xE4_WRAP_FFF1.Field.LcSupportGen2) { + FmSilicon->OscMode = OscLC; + } else { + FmSilicon->OscMode = OscDefault; + } + + IDS_HDT_CONSOLE (GNB_TRACE, " OSC Mode From Fuses - %s\n", + (FmSilicon->OscMode == OscFuses) ? "Fuses" : ( + (FmSilicon->OscMode == OscRO) ? "RO" : ( + (FmSilicon->OscMode == OscLC) ? "LC" : ( + (FmSilicon->OscMode == OscDefault) ? "Skip" : "Unknown"))) + ); + } + if (FmSilicon->OscMode != OscDefault) { + + PcieConfigRunProcForAllWrappers ( + DESCRIPTOR_PCIE_WRAPPER, + PcieOscPifInitPrePowerdownCallback, + NULL, + Pcie + ); + PcieConfigRunProcForAllWrappers ( + DESCRIPTOR_PCIE_WRAPPER, + PcieOscInitPllModeCallback, + NULL, + Pcie + ); + PcieConfigRunProcForAllWrappers ( + DESCRIPTOR_PCIE_WRAPPER, + PcieForceDccRecalibrationCallbackTN, + NULL, + Pcie + ); + + SaveSbLinkAspm = ComplexData->Port8.Type.Port.PortData.LinkAspm; + ComplexData->Port8.Type.Port.PortData.LinkAspm = AspmL1; + + Status = SbPcieLinkAspmControl (&ComplexData->Port8, Pcie); + ASSERT (Status == AGESA_SUCCESS); +#ifdef USE_L1_POLLING + //Use L1 Entry pooling + PciePollLinkForL1Entry (&ComplexData->Port8, Pcie); +#else + { + D0F0xBC_x1F630_STRUCT D0F0xBC_x1F630; + + GnbRegisterReadTN (D0F0xBC_x1F630_TYPE, D0F0xBC_x1F630_ADDRESS, &D0F0xBC_x1F630.Value, 0, GnbLibGetHeader (Pcie)); + D0F0xBC_x1F630.Field.RECONF_WAIT = 60; + GnbRegisterWriteTN (D0F0xBC_x1F630_TYPE, D0F0xBC_x1F630_ADDRESS, &D0F0xBC_x1F630.Value, 0, GnbLibGetHeader (Pcie)); + + GnbSmuServiceRequestV4 ( + ComplexData->Silicon.Address, + SMC_MSG_PCIE_PLLSWITCH, + 0, + GnbLibGetHeader (Pcie) + ); + } +#endif + ComplexData->Port8.Type.Port.PortData.LinkAspm = AspmDisabled; + + SbPcieLinkAspmControl (&ComplexData->Port8, Pcie); + PciePollLinkForL0Exit (&ComplexData->Port8, Pcie); + + ComplexData->Port8.Type.Port.PortData.LinkAspm = SaveSbLinkAspm; + + PcieConfigRunProcForAllWrappers ( + DESCRIPTOR_PCIE_WRAPPER, + PcieOscPifInitPostPowerdownCallback, + NULL, + Pcie + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieOscInitTN Exit\n"); +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.h new file mode 100644 index 0000000..1f65ce2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.h @@ -0,0 +1,110 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * TN specific PCIe configuration data services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _PCIELIBTN_H_ +#define _PCIELIBTN_H_ + +VOID +PciePortsVisibilityControlTN ( + IN PCIE_PORT_VISIBILITY Control, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePowerDownPllInL1TN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieSetVoltageTN ( + IN PCIE_LINK_SPEED_CAP LinkCap, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +UINT8 +PciePifGetPllPowerUpLatencyTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieSetPhyPersonalityTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieOscInitTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c new file mode 100644 index 0000000..2a751be --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c @@ -0,0 +1,283 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbPcieInitLibV4.h" +#include "GnbFamServices.h" +#include "PcieLibTN.h" +#include "PciePowerGateTN.h" +#include "PciePortServicesV4.h" +#include "PcieMaxPayloadV4.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEMIDINITTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_BUILD_OPTIONS GnbBuildOptions; +extern CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitMidTableTN; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +PcieMidInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all active ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieMidPortInitCallbackTN ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PciePortProgramRegisterTable (PortInitMidTableTN.Table, PortInitMidTableTN.Length, Engine, TRUE, Pcie); + if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { + PcieEnableSlotPowerLimit (Engine, Pcie); + if (GnbFmCheckIommuPresent ((GNB_HANDLE*) PcieConfigGetParentSilicon (Engine), GnbLibGetHeader (Pcie))) { + PcieInitPortForIommuV4 (Engine, Pcie); + } + } + PcieEnableAspm (Engine, Pcie); + if (GnbBuildOptions.CfgMaxPayloadEnable) { + PcieSetMaxPayload (Engine->Type.Port.Address, GnbLibGetHeader (Pcie)); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Master procedure to init various features on all active ports + * + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ + +AGESA_STATUS +STATIC +PcieMidPortInitTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + PCIE_LINK_SPEED_CAP GlobalSpeedCap; + + Status = AGESA_SUCCESS; + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieMidPortInitCallbackTN, + NULL, + Pcie + ); + + GlobalSpeedCap = PcieUtilGlobalGenCapability ( + PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS | PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS, + Pcie + ); + + + PcieSetVoltageTN (GlobalSpeedCap, Pcie); + + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Per wrapper Pcie Late Init. + * + * + * @param[in] Wrapper Pointer to wrapper configuration descriptor + * @param[in] Buffer Pointer buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ +AGESA_STATUS +STATIC +PcieMidInitCallbackTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PciePwrPowerDownUnusedLanes (Wrapper, Pcie); + PciePowerDownPllInL1TN (Wrapper, Pcie); + PciePwrClockGatingV4 (Wrapper, Pcie); + PcieLockRegisters (Wrapper, Pcie); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Pcie Late Init + * + * Late PCIe initialization + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Topology successfully mapped + * @retval AGESA_ERROR Topology can not be mapped + */ + +AGESA_STATUS +STATIC +PcieMidInitTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInitTN Enter\n"); + AgesaStatus = AGESA_SUCCESS; + + Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieMidInitCallbackTN, NULL, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + Status = PciePowerGateTN (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInitTN Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Mid Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +PcieMidInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInterfaceTN Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + PciePortsVisibilityControlTN (UnhidePorts, Pcie); + + Status = PcieMidPortInitTN (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieMidInitTN (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + PciePortsVisibilityControlTN (HidePorts, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInterfaceTN Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c new file mode 100644 index 0000000..b30e92b --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c @@ -0,0 +1,498 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63818 $ @e $Date: 2012-01-09 03:02:03 -0600 (Mon, 09 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbPcieConfig.h" +#include "GnbPcieTrainingV1.h" +#include "GnbPcieInitLibV1.h" +#include "GnbPcieInitLibV4.h" +#include "PcieLibTN.h" +#include "GnbRegistersTN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEPOSTINITTN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +PciePostEarlyInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PciePostInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PciePostS3InterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +PcieLateRestoreInitTNS3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID* Context + ); +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PciePostPortInitCallbackTN ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIE_LINK_SPEED_CAP LinkSpeedCapability; + ASSERT (Engine->EngineData.EngineType == PciePortEngine); + if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { + PcieLinkSafeMode (Engine, Pcie); + } + LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine); + PcieSetLinkSpeedCapV4 (LinkSpeedCapability, Engine, Pcie); + if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) && (LinkSpeedCapability > PcieGen1) && !PcieConfigIsSbPcieEngine (Engine)) { + PcieTrainingSetPortState (Engine, LinkStateRetrain, FALSE, Pcie); + PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS); + } + if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { + PcieForceCompliance (Engine, Pcie); + PcieTrainingSetPortState (Engine, LinkStateResetExit, FALSE, Pcie); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PciePostS3PortInitCallbackTN ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIE_LINK_SPEED_CAP LinkSpeedCapability; + PCIE_LINK_TRAINING_STATE State; + + ASSERT (Engine->EngineData.EngineType == PciePortEngine); + + LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine); + PcieSetLinkSpeedCapV4 (LinkSpeedCapability, Engine, Pcie); + + if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { + PcieLinkSafeMode (Engine, Pcie); + } + + if (!PcieConfigIsSbPcieEngine (Engine)) { + // + // General Port + // + State = LinkStateDeviceNotPresent; + if (Engine->Type.Port.PortData.LinkHotplug == HotplugDisabled || Engine->Type.Port.PortData.LinkHotplug == HotplugInboard) { + // + // Non hotplug device: we only check status from previous boot + // + if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { + State = LinkStateResetExit; + } + } else { + UINT32 PcieScratch; + // + // Get endpoint staus from scratch + // + PcieScratch = PciePortRegisterRead (Engine, DxF0xE4_x01_ADDRESS, Pcie); + // + // Hotplug device: we check ep status if reported + // + if ((PcieScratch & 0x1) == 0) { + State = LinkStateResetExit; + } + } + // + // For compialnce we always leave link in enabled state + // + if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode) { + State = LinkStateResetExit; + } + PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS); + } else { + // + // SB port + // + State = LinkStateTrainingSuccess; + } + PcieTrainingSetPortState (Engine, State, FALSE, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Master procedure to init various features on all active ports + * + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ + +AGESA_STATUS +STATIC +PciePostEarlyPortInitTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + // Distributed Training started at PciePortInit complete it now to get access to PCIe devices + if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) { + Pcie->TrainingExitState = LinkStateTrainingCompleted; + } + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Master procedure to init various features on all active ports + * + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ + +AGESA_STATUS +STATIC +PciePostPortInitTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PciePostPortInitCallbackTN, + NULL, + Pcie + ); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Master procedure to init various features on all active ports + * + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ + +AGESA_STATUS +STATIC +PciePostS3PortInitTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PciePostS3PortInitCallbackTN, + NULL, + Pcie + ); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Pcie Init + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Topology successfully mapped + * @retval AGESA_ERROR Topology can not be mapped + */ + +AGESA_STATUS +STATIC +PciePostInitTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIE_LINK_SPEED_CAP GlobalSpeedCap; + + GlobalSpeedCap = PcieUtilGlobalGenCapability ( + PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS | PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS, + Pcie + ); + + + PcieSetVoltageTN (GlobalSpeedCap, Pcie); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +PciePostEarlyInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePostEarlyInterfaceTN Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + PciePortsVisibilityControlTN (UnhidePorts, Pcie); + + Status = PciePostEarlyPortInitTN (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieTraining (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + PciePortsVisibilityControlTN (HidePorts, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePostEarlyInterfaceTN Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +PciePostInterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInterfaceTN Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + PciePortsVisibilityControlTN (UnhidePorts, Pcie); + + Status = PciePostInitTN (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PciePostPortInitTN (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieTraining (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + PciePortsVisibilityControlTN (HidePorts, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInterfaceTN Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +PciePostS3InterfaceTN ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePostS3InterfaceTN Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + PciePortsVisibilityControlTN (UnhidePorts, Pcie); + + Status = PciePostInitTN (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) { + Status = PciePostS3PortInitTN (Pcie); + } else { + Status = PciePostPortInitTN (Pcie); + } + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieTraining (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + PciePortsVisibilityControlTN (HidePorts, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePostS3InterfaceTN Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe S3 restore + * + * + * + * @param[in] StdHeader Standard configuration header + * @param[in] ContextLength Context Length (not used) + * @param[in] Context Context pointer (not used) + */ +VOID +PcieLateRestoreInitTNS3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID* Context + ) +{ + PciePostS3InterfaceTN (StdHeader); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c new file mode 100644 index 0000000..4197fd8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c @@ -0,0 +1,383 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe power gate initialization + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "OptionGnb.h" +#include "GnbPcieConfig.h" +#include "GnbPcieFamServices.h" +#include "GnbPcieInitLibV1.h" +#include "GnbNbInitLibV4.h" +#include "GnbRegistersTN.h" +#include "GnbRegisterAccTN.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEPOWERGATETN_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +PciePowerGateTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Report used lanes + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PciePowerGateReportActiveLanesCallbackTN ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D0F0xBC_x1F39C_STRUCT D0F0xBC_x1F39C; + UINT32 LaneBitmap; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateReportActiveLanesCallbackTN Enter\n"); + LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_DDI_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, Engine); + if (LaneBitmap != 0) { + D0F0xBC_x1F39C.Value = 0; + D0F0xBC_x1F39C.Field.Tx = 0; + D0F0xBC_x1F39C.Field.Rx = 0; + D0F0xBC_x1F39C.Field.Core = 0; + D0F0xBC_x1F39C.Field.SkipPhy = 1; + D0F0xBC_x1F39C.Field.SkipCore = 1; + D0F0xBC_x1F39C.Field.UpperLaneID = LibAmdBitScanReverse (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane; + D0F0xBC_x1F39C.Field.LowerLaneID = LibAmdBitScanForward (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane; + IDS_HDT_CONSOLE ( + PCIE_MISC, + " LowerLaneID - %02d UpperLaneID - %02d Tx - %d Rx - %d Core - %d Exit\n", + D0F0xBC_x1F39C.Field.LowerLaneID, + D0F0xBC_x1F39C.Field.UpperLaneID, + D0F0xBC_x1F39C.Field.Tx, + D0F0xBC_x1F39C.Field.Rx, + D0F0xBC_x1F39C.Field.Core + ); + if (PcieConfigIsPcieEngine (Engine) && PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine) == PcieGen2) { + D0F0xBC_x1F610_STRUCT D0F0xBC_x1F610; + UINT32 Gen2LaneBitmap; + Gen2LaneBitmap = ((1 << (D0F0xBC_x1F39C.Field.UpperLaneID - D0F0xBC_x1F39C.Field.LowerLaneID + 1)) - 1) << D0F0xBC_x1F39C.Field.LowerLaneID; + GnbRegisterReadTN (D0F0xBC_x1F610_TYPE, D0F0xBC_x1F610_ADDRESS, &D0F0xBC_x1F610.Value, 0, GnbLibGetHeader (Pcie)); + D0F0xBC_x1F610.Field.GFXH |= (Gen2LaneBitmap >> 16) & 0xFF; + D0F0xBC_x1F610.Field.GFXL |= (Gen2LaneBitmap >> 8) & 0xFF; + D0F0xBC_x1F610.Field.GPPSB |= (Gen2LaneBitmap & 0xFF ); + GnbRegisterWriteTN (D0F0xBC_x1F610_TYPE, D0F0xBC_x1F610_ADDRESS, &D0F0xBC_x1F610.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie)); + } + GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE, D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie)); + GnbSmuServiceRequestV4 ( + PcieConfigGetParentSilicon (Engine)->Address, + SMC_MSG_PHY_LN_ON, + GNB_REG_ACC_FLAG_S3SAVE, + GnbLibGetHeader (Pcie) + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateReportActiveLanesCallbackTN Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Power down unused lanes + * + * + * + * + * @param[in] Wrapper Pointer to wrapper configuration + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS + * + */ + +AGESA_STATUS +STATIC +PciePowerGatePowerDownUnusedLanesCallbackTN ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 Index; + UINTN State; + UINT32 LaneBitmap; + UINT16 StartLane; + UINT16 EndLane; + D0F0xBC_x1F39C_STRUCT D0F0xBC_x1F39C; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePowerDownUnusedLanesCallbackTN Enter\n"); + + LaneBitmap = PcieUtilGetWrapperLaneBitMap ( + LANE_TYPE_PHY_NATIVE_ALL, + LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_DDI_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, + Wrapper + ); + IDS_HDT_CONSOLE (GNB_TRACE, " Lane Bitmap 0x%x\n", LaneBitmap); + if (LaneBitmap != 0) { + State = 0; + StartLane = 0; + EndLane = 0; + for (Index = 0; Index <= (LibAmdBitScanReverse (LaneBitmap) + 1); Index++) { + if ((State == 0) && ((LaneBitmap & (1 << Index)) != 0)) { + StartLane = Index; + State = 1; + } else if ((State == 1) && ((LaneBitmap & (1 << Index)) == 0)) { + EndLane = Index - 1; + State = 0; + GnbRegisterReadTN (D0F0xBC_x1F39C_TYPE, D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, 0, GnbLibGetHeader (Pcie)); + D0F0xBC_x1F39C.Field.Tx = 1; + D0F0xBC_x1F39C.Field.Rx = 1; + D0F0xBC_x1F39C.Field.Core = 1; + D0F0xBC_x1F39C.Field.LowerLaneID = StartLane + Wrapper->StartPhyLane; + D0F0xBC_x1F39C.Field.UpperLaneID = EndLane + Wrapper->StartPhyLane; + IDS_HDT_CONSOLE ( + PCIE_MISC, + " LowerLaneID - %02d UpperLaneID - %02d Tx - %d Rx - %d Core - %d Exit\n", + D0F0xBC_x1F39C.Field.LowerLaneID, + D0F0xBC_x1F39C.Field.UpperLaneID, + D0F0xBC_x1F39C.Field.Tx, + D0F0xBC_x1F39C.Field.Rx, + D0F0xBC_x1F39C.Field.Core + ); + GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE, D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie)); + GnbSmuServiceRequestV4 ( + PcieConfigGetParentSilicon (Wrapper)->Address, + SMC_MSG_PHY_LN_OFF, + GNB_REG_ACC_FLAG_S3SAVE, + GnbLibGetHeader (Pcie) + ); + } + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePowerDownUnusedLanesCallbackTN Exit\n"); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Power down unused lanes + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PciePowerGatePowerDownLanesCallbackTN ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D0F0xBC_x1F39C_STRUCT D0F0xBC_x1F39C; + UINT32 LaneBitmap; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePowerDownLanesCallbackTN Enter\n"); + LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE, Engine); + if (LaneBitmap != 0) { + GnbRegisterReadTN (D0F0xBC_x1F39C_TYPE, D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, 0, GnbLibGetHeader (Pcie)); + D0F0xBC_x1F39C.Field.Tx = 1; + D0F0xBC_x1F39C.Field.Rx = 1; + D0F0xBC_x1F39C.Field.Core = 0; + D0F0xBC_x1F39C.Field.UpperLaneID = LibAmdBitScanReverse (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane; + D0F0xBC_x1F39C.Field.LowerLaneID = LibAmdBitScanForward (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane; + IDS_HDT_CONSOLE ( + PCIE_MISC, + " PCIe Lanes LowerLaneID - %02d UpperLaneID - %02d Tx - %d Rx - %d Core - %d Exit\n", + D0F0xBC_x1F39C.Field.LowerLaneID, + D0F0xBC_x1F39C.Field.UpperLaneID, + D0F0xBC_x1F39C.Field.Tx, + D0F0xBC_x1F39C.Field.Rx, + D0F0xBC_x1F39C.Field.Core + ); + GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE, D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie)); + GnbSmuServiceRequestV4 ( + PcieConfigGetParentSilicon (Engine)->Address, + SMC_MSG_PHY_LN_OFF, + GNB_REG_ACC_FLAG_S3SAVE, + GnbLibGetHeader (Pcie) + ); + } + LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE_ACTIVE, 0, Engine); + if (LaneBitmap != 0) { + GnbRegisterReadTN (D0F0xBC_x1F39C_TYPE, D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, 0, GnbLibGetHeader (Pcie)); + D0F0xBC_x1F39C.Field.Tx = 1; + D0F0xBC_x1F39C.Field.Rx = 1; + D0F0xBC_x1F39C.Field.Core = 1; + D0F0xBC_x1F39C.Field.UpperLaneID = LibAmdBitScanReverse (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane; + D0F0xBC_x1F39C.Field.LowerLaneID = LibAmdBitScanForward (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane; + IDS_HDT_CONSOLE ( + PCIE_MISC, + " DDI Lanes LowerLaneID - %02d UpperLaneID - %02d Tx - %d Rx - %d Core - %d Exit\n", + D0F0xBC_x1F39C.Field.LowerLaneID, + D0F0xBC_x1F39C.Field.UpperLaneID, + D0F0xBC_x1F39C.Field.Tx, + D0F0xBC_x1F39C.Field.Rx, + D0F0xBC_x1F39C.Field.Core + ); + GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE, D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie)); + GnbSmuServiceRequestV4 ( + PcieConfigGetParentSilicon (Engine)->Address, + SMC_MSG_PHY_LN_OFF, + GNB_REG_ACC_FLAG_S3SAVE, + GnbLibGetHeader (Pcie) + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePowerDownLanesCallbackTN Exit\n"); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Pcie Power gate init + * + * Late PCIe initialization + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Topology successfully mapped + */ + +AGESA_STATUS +PciePowerGateTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 PowerGatingFlags; + D0F0xBC_x1F39C_STRUCT D0F0xBC_x1F39C; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateTN Enter\n"); + PowerGatingFlags = GnbBuildOptions.CfgPciePowerGatingFlags; + // Report used lanes + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_DDI_ENGINE, + PciePowerGateReportActiveLanesCallbackTN, + NULL, + Pcie + ); + + IDS_OPTION_HOOK (IDS_GNB_PCIE_POWER_GATING, &PowerGatingFlags, GnbLibGetHeader (Pcie)); + + // Update flags + GnbRegisterReadTN (D0F0xBC_x1F39C_TYPE, D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, 0, GnbLibGetHeader (Pcie)); + if ((PowerGatingFlags & PCIE_POWERGATING_SKIP_CORE) == 0) { + D0F0xBC_x1F39C.Field.SkipCore = 0; + } + if ((PowerGatingFlags & PCIE_POWERGATING_SKIP_PHY) == 0) { + D0F0xBC_x1F39C.Field.SkipPhy = 0; + } + GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE, D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie)); + // Power down unused lanes + PcieConfigRunProcForAllWrappers ( + DESCRIPTOR_PCIE_WRAPPER | DESCRIPTOR_DDI_WRAPPER, + PciePowerGatePowerDownUnusedLanesCallbackTN, + NULL, + Pcie + ); + //Power down hotplug lanes + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_DDI_ENGINE, + PciePowerGatePowerDownLanesCallbackTN, + NULL, + Pcie + ); + IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateTN Exit\n"); + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.h new file mode 100644 index 0000000..b8d2116 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.h @@ -0,0 +1,81 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe power gate initialization + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _PCIEPOWERGATETN_H_ +#define _PCIEPOWERGATETN_H_ + +AGESA_STATUS +PciePowerGateTN ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c new file mode 100644 index 0000000..faa2fa8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c @@ -0,0 +1,258 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 65061 $ @e $Date: 2012-02-06 23:48:39 -0600 (Mon, 06 Feb 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "PcieComplexDataTN.h" +#include "GnbRegistersTN.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T A B L E S + *---------------------------------------------------------------------------------------- + */ + +STATIC PCIE_HOST_REGISTER_ENTRY PcieInitEarlyTable ROMDATA[] = { + { + WRAP_SPACE (GPP_WRAP_ID, D0F0xE4_WRAP_8016_ADDRESS), + D0F0xE4_WRAP_8016_CalibAckLatency_MASK, + 0 + }, + { + PHY_SPACE (GPP_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS), + D0F0xE4_PHY_2008_VdDetectEn_MASK, + 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET + }, + { + PHY_SPACE (GFX_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS), + D0F0xE4_PHY_2008_VdDetectEn_MASK, + 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET + }, + { + PHY_SPACE (GFX_WRAP_ID, 1, D0F0xE4_PHY_2008_ADDRESS), + D0F0xE4_PHY_2008_VdDetectEn_MASK, + 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET + }, + { + PHY_SPACE (DDI_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS), + D0F0xE4_PHY_2008_VdDetectEn_MASK, + 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET + }, + { + PHY_SPACE (DDI2_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS), + D0F0xE4_PHY_2008_VdDetectEn_MASK, + 0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET + } + }; + +CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA PcieInitEarlyTableTN = { + &PcieInitEarlyTable[0], + sizeof (PcieInitEarlyTable) / sizeof (PCIE_HOST_REGISTER_ENTRY) +}; + +STATIC PCIE_HOST_REGISTER_ENTRY ROMDATA CoreInitTable [] = { + { + D0F0xE4_CORE_0020_ADDRESS, + D0F0xE4_CORE_0020_CiRcOrderingDis_MASK | + D0F0xE4_CORE_0020_CiSlvOrderingDis_MASK, + (0x1 << D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET) + }, + { + D0F0xE4_CORE_0010_ADDRESS, + D0F0xE4_CORE_0010_RxSbAdjPayloadSize_MASK, + (0x4 << D0F0xE4_CORE_0010_RxSbAdjPayloadSize_OFFSET) + }, + { + D0F0xE4_CORE_001C_ADDRESS, + D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK | + D0F0xE4_CORE_001C_TxArbSlvLimit_MASK | + D0F0xE4_CORE_001C_TxArbMstLimit_MASK, + (0x1 << D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET) | + (0x4 << D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET) | + (0x4 << D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET) + }, + { + D0F0xE4_CORE_0040_ADDRESS, + D0F0xE4_CORE_0040_PElecIdleMode_MASK, + (0x2 << D0F0xE4_CORE_0040_PElecIdleMode_OFFSET) + }, + { + D0F0xE4_CORE_0002_ADDRESS, + D0F0xE4_CORE_0002_HwDebug_0__MASK, + (0x1 << D0F0xE4_CORE_0002_HwDebug_0__OFFSET) + }, + { + D0F0xE4_CORE_00C1_ADDRESS, + D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK | + D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK, + (0x1 << D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET) | + (0x1 << D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET) + }, + { + D0F0xE4_CORE_00B0_ADDRESS, + D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK, + (0x1 << D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET) + } +}; + +CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA CoreInitTableTN = { + &CoreInitTable[0], + sizeof (CoreInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY) +}; + + +STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitEarlyTable [] = { + { + DxF0xE4_x02_ADDRESS, + DxF0xE4_x02_RegsLcAllowTxL1Control_MASK, + (0x1 << DxF0xE4_x02_RegsLcAllowTxL1Control_OFFSET) + }, + { + DxF0xE4_x70_ADDRESS, + DxF0xE4_x70_RxRcbCplTimeoutMode_MASK, + (0x1 << DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET) + }, + { + DxF0xE4_xA0_ADDRESS, + DxF0xE4_xA0_Lc16xClearTxPipe_MASK | DxF0xE4_xA0_LcL1ImmediateAck_MASK | DxF0xE4_xA0_LcL0sInactivity_MASK, + (0x3 << DxF0xE4_xA0_Lc16xClearTxPipe_OFFSET) | + (0x1 << DxF0xE4_xA0_LcL1ImmediateAck_OFFSET) | + (0x6 << DxF0xE4_xA0_LcL0sInactivity_OFFSET) + }, + { + DxF0xE4_xA1_ADDRESS, + DxF0xE4_xA1_LcDontGotoL0sifL1Armed_MASK, + (0x1 << DxF0xE4_xA1_LcDontGotoL0sifL1Armed_OFFSET) + }, + { + DxF0xE4_xA2_ADDRESS, + DxF0xE4_xA2_LcRenegotiateEn_MASK | DxF0xE4_xA2_LcUpconfigureSupport_MASK, + (0x1 << DxF0xE4_xA2_LcRenegotiateEn_OFFSET) | + (0x1 << DxF0xE4_xA2_LcUpconfigureSupport_OFFSET) + }, + { + DxF0xE4_xA3_ADDRESS, + DxF0xE4_xA3_LcXmitFtsBeforeRecovery_MASK, + (0x1 << DxF0xE4_xA3_LcXmitFtsBeforeRecovery_OFFSET) + }, + { + DxF0xE4_xB1_ADDRESS, + DxF0xE4_xB1_LcDeassertRxEnInL0s_MASK | DxF0xE4_xB1_LcBlockElIdleinL0_MASK, + (0x1 << DxF0xE4_xB1_LcDeassertRxEnInL0s_OFFSET) | + (0x1 << DxF0xE4_xB1_LcBlockElIdleinL0_OFFSET) + } +}; + +CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitEarlyTableTN = { + &PortInitEarlyTable[0], + sizeof (PortInitEarlyTable) / sizeof (PCIE_PORT_REGISTER_ENTRY) +}; + + +STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitMidTable [] = { + { + DxF0xE4_xA2_ADDRESS, + DxF0xE4_xA2_LcDynLanesPwrState_MASK, + (0x3 << DxF0xE4_xA2_LcDynLanesPwrState_OFFSET) + }, + { + DxF0xE4_xC0_ADDRESS, + DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK, + (0x1 << DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET) + } +}; + +CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitMidTableTN = { + &PortInitMidTable[0], + sizeof (PortInitMidTable) / sizeof (PCIE_PORT_REGISTER_ENTRY) +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c new file mode 100644 index 0000000..fb44d83 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c @@ -0,0 +1,361 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe ALIB + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "cpuLateInit.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbFamServices.h" +#include "GnbCommonLib.h" +#include "GnbIvrsLib.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBIOMMUIVRS_GNBIOMMUIVRS_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions; +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +#define IVRS_TABLE_LENGTH 8 * 1024 + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +GnbBuildIvmdList ( + IN IVRS_BLOCK_TYPE Type, + IN VOID *Ivrs, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbIommuIvrsTableDump ( + IN VOID *Ivrs, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbIommuIvrsTable ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +IOMMU_IVRS_HEADER IvrsHeader = { + {'I', 'V', 'R', 'S'}, + sizeof (IOMMU_IVRS_HEADER), + 2, + 0, + {'A', 'M', 'D', ' ', ' ', 0}, + {'A', 'M', 'D', 'I', 'O', 'M', 'M', 'U'}, + 1, + {'A','M','D',' '}, + 0, + 0, + 0 +}; + + +/*----------------------------------------------------------------------------------------*/ +/** + * Build IVRS table + * + * + * + * @param[in] StdHeader Standard Configuration Header + * @retval AGESA_SUCCESS + * @retval AGESA_ERROR + */ + +AGESA_STATUS +GnbIommuIvrsTable ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AMD_LATE_PARAMS *LateParamsPtr; + VOID *Ivrs; + BOOLEAN IvrsSupport; + GNB_HANDLE *GnbHandle; + + Status = AGESA_SUCCESS; + LateParamsPtr = (AMD_LATE_PARAMS*) StdHeader; + IvrsSupport = FALSE; + Ivrs = LateParamsPtr->AcpiIvrs; + if (Ivrs == NULL) { + Ivrs = GnbAllocateHeapBuffer ( + AMD_ACPI_IVRS_BUFFER_HANDLE, + IVRS_TABLE_LENGTH, + StdHeader + ); + ASSERT (Ivrs != NULL); + if (Ivrs == NULL) { + return AGESA_ERROR; + } + LateParamsPtr->AcpiIvrs = Ivrs; + } + LibAmdMemFill (Ivrs, 0x0, IVRS_TABLE_LENGTH, StdHeader); + LibAmdMemCopy (Ivrs, &IvrsHeader, sizeof (IvrsHeader), StdHeader); + + GnbHandle = GnbGetHandle (StdHeader); + while (GnbHandle != NULL) { + if (GnbFmCheckIommuPresent (GnbHandle, StdHeader)) { + IDS_HDT_CONSOLE (GNB_TRACE, "Build IVRS for Socket %d Silicon %d\n", GnbGetSocketId (GnbHandle) , GnbGetSiliconId (GnbHandle)); + IvrsSupport = TRUE; + GnbFmCreateIvrsEntry (GnbHandle, IvrsIvhdBlock, Ivrs, StdHeader); + GnbBuildIvmdList (IvrsIvmdBlock, Ivrs, StdHeader); + if (GnbBuildOptions.IvrsRelativeAddrNamesSupport) { + GnbFmCreateIvrsEntry (GnbHandle, IvrsIvhdrBlock, Ivrs, StdHeader); + GnbBuildIvmdList (IvrsIvmdrBlock, Ivrs, StdHeader); + } + } + GnbHandle = GnbGetNextHandle (GnbHandle); + } + if (IvrsSupport == TRUE) { + ChecksumAcpiTable ((ACPI_TABLE_HEADER*) Ivrs, StdHeader); + GNB_DEBUG_CODE (GnbIommuIvrsTableDump (Ivrs, StdHeader)); + } else { + IDS_HDT_CONSOLE (GNB_TRACE, " IVRS table not generated\n"); + LateParamsPtr->AcpiIvrs = NULL; + } + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Build IVMD list + * + * + * @param[in] Type Entry type + * @param[in] Ivrs IVRS table pointer + * @param[in] StdHeader Standard configuration header + * + */ + +AGESA_STATUS +GnbBuildIvmdList ( + IN IVRS_BLOCK_TYPE Type, + IN VOID *Ivrs, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + IOMMU_EXCLUSION_RANGE_DESCRIPTOR *IvrsExclusionRangeList; + IVRS_IVMD_ENTRY *Ivmd; + UINT16 StartId; + UINT16 EndId; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbBuildIvmdList Entry\n"); + IvrsExclusionRangeList = ((AMD_LATE_PARAMS*)StdHeader)->IvrsExclusionRangeList; + if (IvrsExclusionRangeList != NULL) { + // Process the entire IvrsExclusionRangeList here and create an IVMD for eache entry + IDS_HDT_CONSOLE (GNB_TRACE, "Process Exclusion Range List\n"); + while ((IvrsExclusionRangeList->Flags & DESCRIPTOR_TERMINATE_LIST) == 0) { + if ((IvrsExclusionRangeList->Flags & DESCRIPTOR_IGNORE) == 0) { + // Address of IVMD entry + Ivmd = (IVRS_IVMD_ENTRY*) ((UINT8 *)Ivrs + ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength); + StartId = + (IvrsExclusionRangeList->RequestorIdStart.Bus << 8) + + (IvrsExclusionRangeList->RequestorIdStart.Device << 3) + + (IvrsExclusionRangeList->RequestorIdStart.Function); + EndId = + (IvrsExclusionRangeList->RequestorIdEnd.Bus << 8) + + (IvrsExclusionRangeList->RequestorIdEnd.Device << 3) + + (IvrsExclusionRangeList->RequestorIdEnd.Function); + GnbIvmdAddEntry ( + Type, + StartId, + EndId, + IvrsExclusionRangeList->RangeBaseAddress, + IvrsExclusionRangeList->RangeLength, + Ivmd, + StdHeader); + // Add entry size to existing table length + ((IOMMU_IVRS_HEADER *)Ivrs)->TableLength += sizeof (IVRS_IVMD_ENTRY); + } + // Point to next entry in IvrsExclusionRangeList + IvrsExclusionRangeList++; + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "GnbBuildIvmdList Exit\n"); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Dump IVRS table + * + * + * @param[in] Ivrs Pointer to IVRS table + * @param[in] StdHeader Standard Configuration Header + */ + +VOID +GnbIommuIvrsTableDump ( + IN VOID *Ivrs, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 *Block; + UINT8 *Entry; + Block = (UINT8 *) Ivrs + sizeof (IOMMU_IVRS_HEADER); + IDS_HDT_CONSOLE (GNB_TRACE, "<---------- IVRS Table Start -----------> \n"); + IDS_HDT_CONSOLE (GNB_TRACE, " IVInfo = 0x%08x\n", ((IOMMU_IVRS_HEADER *) Ivrs)-> IvInfo); + while (Block < ((UINT8 *) Ivrs + ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength)) { + if (*Block == IvrsIvhdBlock) { + IDS_HDT_CONSOLE (GNB_TRACE, " <-------------IVHD Block Start -------->\n"); + IDS_HDT_CONSOLE (GNB_TRACE, " Flags = 0x%02x\n", ((IVRS_IVHD_ENTRY *) Block)->Flags); + IDS_HDT_CONSOLE (GNB_TRACE, " DeviceId = 0x%04x\n", ((IVRS_IVHD_ENTRY *) Block)->DeviceId); + IDS_HDT_CONSOLE (GNB_TRACE, " CapabilityOffset = 0x%02x\n", ((IVRS_IVHD_ENTRY *) Block)->CapabilityOffset); + IDS_HDT_CONSOLE (GNB_TRACE, " BaseAddress = 0x%08x%08x\n", (UINT32) (((IVRS_IVHD_ENTRY *) Block)->BaseAddress >> 32), (UINT32) ((IVRS_IVHD_ENTRY *) Block)->BaseAddress); + IDS_HDT_CONSOLE (GNB_TRACE, " PCI Segment = 0x%04x\n", ((IVRS_IVHD_ENTRY *) Block)->PciSegment); + IDS_HDT_CONSOLE (GNB_TRACE, " IommuInfo = 0x%04x\n", ((IVRS_IVHD_ENTRY *) Block)->IommuInfo); + IDS_HDT_CONSOLE (GNB_TRACE, " IommuEfr = 0x%08x\n", ((IVRS_IVHD_ENTRY *) Block)->IommuEfr); + Entry = Block + sizeof (IVRS_IVHD_ENTRY); + IDS_HDT_CONSOLE (GNB_TRACE, " <-------------IVHD Block Device Entries Start -------->\n"); + while (Entry < (Block + ((IVRS_IVHD_ENTRY *) Block)->Length)) { + IDS_HDT_CONSOLE (GNB_TRACE, " "); + switch (*Entry) { + case IvhdEntrySelect: + case IvhdEntryEndRange: + GnbLibDebugDumpBuffer (Entry, 4, 1, 4); + Entry = Entry + 4; + break; + case IvhdEntryStartRange: + GnbLibDebugDumpBuffer (Entry, 8, 1, 8); + Entry = Entry + 8; + break; + case IvhdEntryAliasStartRange: + GnbLibDebugDumpBuffer (Entry, 12, 1, 12); + Entry = Entry + 12; + break; + case IvhdEntryAliasSelect: + case IvhdEntryExtendedSelect: + case IvhdEntrySpecialDevice: + GnbLibDebugDumpBuffer (Entry, 8, 1, 8); + Entry = Entry + 8; + break; + case IvhdEntryPadding: + Entry = Entry + 4; + break; + default: + IDS_HDT_CONSOLE (GNB_TRACE, " Unsupported entry type [%d]\n"); + ASSERT (FALSE); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, " <-------------IVHD Block Device Entries End -------->\n"); + IDS_HDT_CONSOLE (GNB_TRACE, " <-------------IVHD Block End ---------->\n"); + Block = Block + ((IVRS_IVHD_ENTRY *) Block)->Length; + } else if ( + (*Block == IvrsIvmdBlock) || + (*Block == IvrsIvmdBlockRange) || + (*Block == IvrsIvmdBlockSingle) || + (*Block == IvrsIvmdrBlock) || + (*Block == IvrsIvmdrBlockSingle)) { + IDS_HDT_CONSOLE (GNB_TRACE, " <-------------IVMD Block Start -------->\n"); + IDS_HDT_CONSOLE (GNB_TRACE, " Flags = 0x%02x\n", ((IVRS_IVMD_ENTRY *) Block)->Flags); + IDS_HDT_CONSOLE (GNB_TRACE, " DeviceId = 0x%04x\n", ((IVRS_IVMD_ENTRY *) Block)->DeviceId); + switch (*Block) { + case IvrsIvmdBlock: + case IvrsIvmdrBlock: + IDS_HDT_CONSOLE (GNB_TRACE, " Applies to all devices\n"); + break; + case IvrsIvmdBlockSingle: + case IvrsIvmdrBlockSingle: + IDS_HDT_CONSOLE (GNB_TRACE, " Applies to a single device\n"); + break; + default: + IDS_HDT_CONSOLE (GNB_TRACE, " DeviceId End = 0x%04x\n", ((IVRS_IVMD_ENTRY *) Block)->AuxiliaryData); + } + IDS_HDT_CONSOLE (GNB_TRACE, " StartAddress = 0x%08x%08x\n", (UINT32) (((IVRS_IVMD_ENTRY *) Block)->BlockStart >> 32), (UINT32) ((IVRS_IVMD_ENTRY *) Block)->BlockStart); + IDS_HDT_CONSOLE (GNB_TRACE, " BockLength = 0x%08x%08x\n", (UINT32) (((IVRS_IVMD_ENTRY *) Block)->BlockLength >> 32), (UINT32) ((IVRS_IVMD_ENTRY *) Block)->BlockLength); + IDS_HDT_CONSOLE (GNB_TRACE, " <-------------IVMD Block End ---------->\n"); + Block = Block + ((IVRS_IVMD_ENTRY *) Block)->Length; + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "<---------- IVRS Table Raw Data --------> \n"); + GnbLibDebugDumpBuffer (Ivrs, ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength, 1, 16); + IDS_HDT_CONSOLE (GNB_TRACE, "\n"); + IDS_HDT_CONSOLE (GNB_TRACE, "<---------- IVRS Table End -------------> \n"); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.h new file mode 100644 index 0000000..c48224f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.h @@ -0,0 +1,81 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe ALIB + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _GNBIOMMUIVRS_H_ +#define _GNBIOMMUIVRS_H_ + +AGESA_STATUS +GnbIommuIvrsTable ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c new file mode 100644 index 0000000..b5eb7ed --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c @@ -0,0 +1,168 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "S3SaveState.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "GnbFamServices.h" +#include "GnbRegistersTN.h" +#include "heapManager.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBIOMMUSCRATCH_GNBIOMMUSCRATCH_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Set Iommu Scratch Memory Range + * 1) code needs to be executed at Late Init + * 2) Allocate heap using heap type HEAP_RUNTIME_SYSTEM_MEM + * 3) Allocate enough memory to be able to get address aligned required by register + * 4) Assign same address to all Gnb in system + * + * + * @param[in] StdHeader Standard configuration header + */ + +AGESA_STATUS +GnbIommuScratchMemoryRangeInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + UINT32 AddressLow; + UINT32 AddressHigh; + GNB_HANDLE *GnbHandle; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuScratchMemoryRangeInterface Enter\n"); + + AllocHeapParams.RequestedBufferSize = 128; + AllocHeapParams.BufferHandle = AMD_GNB_IOMMU_SCRATCH_MEM_HANDLE; + AllocHeapParams.Persist = HEAP_RUNTIME_SYSTEM_MEM; + Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader); + if (Status != AGESA_SUCCESS) { + IDS_HDT_CONSOLE (GNB_TRACE, " Iommu Scratch Memory not allocated.\n"); + ASSERT (FALSE); + return AGESA_FATAL; + } + + AddressLow = (((UINT32) ((UINT64) AllocHeapParams.BufferPtr)) + 0x3F) & D0F0x98_x27_IOMMUUrAddr_31_6__MASK; + AddressHigh = ((UINT32) (((UINT64) AllocHeapParams.BufferPtr) >> 32)) & D0F0x98_x26_IOMMUUrAddr_39_32__MASK; + + GnbHandle = GnbGetHandle (StdHeader); + while (GnbHandle != NULL) { + if (GnbFmCheckIommuPresent (GnbHandle, StdHeader)) { + IDS_HDT_CONSOLE (GNB_TRACE, "Set Iommu Scratch Memory for Socket %d Silicon %d\n", GnbGetSocketId (GnbHandle) , GnbGetSiliconId (GnbHandle)); + GnbLibPciIndirectWrite ( + GnbHandle->Address.AddressValue | D0F0x94_ADDRESS, + D0F0x98_x27_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), + AccessS3SaveWidth32, + &AddressLow, + StdHeader); + + GnbLibPciIndirectWrite ( + GnbHandle->Address.AddressValue | D0F0x94_ADDRESS, + D0F0x98_x26_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), + AccessS3SaveWidth32, + &AddressHigh, + StdHeader); + } + GnbHandle = GnbGetNextHandle (GnbHandle); + } + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuScratchMemoryRangeInterface Exit\n"); + + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c new file mode 100644 index 0000000..d18493e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c @@ -0,0 +1,267 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe ALIB + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 64895 $ @e $Date: 2012-02-02 01:01:48 -0600 (Thu, 02 Feb 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + + +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "cpuLateInit.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbIommu.h" +#include "GnbFamServices.h" +#include "GnbCommonLib.h" +#include "GnbIommuIvrs.h" +#include "GnbIvrsLib.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBIVRSLIB_GNBIVRSLIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Create IVHDR entry for device range + * + * + * @param[in] StartRange Address of start range + * @param[in] EndRange Address of end range + * @param[in] DataSetting Data setting + * @param[in] Ivhd Pointer to IVHD entry + * @param[in] StdHeader Standard configuration header + * + */ +VOID +GnbIvhdAddDeviceRangeEntry ( + IN PCI_ADDR StartRange, + IN PCI_ADDR EndRange, + IN UINT8 DataSetting, + IN IVRS_IVHD_ENTRY *Ivhd, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + IVHD_GENERIC_ENTRY *Entry; + Entry = (IVHD_GENERIC_ENTRY *) ((UINT8 *) Ivhd + Ivhd->Length); + Entry->Type = IvhdEntryStartRange; + Entry->DeviceId = DEVICE_ID (StartRange); + Entry->DataSetting = DataSetting; + Ivhd->Length += sizeof (IVHD_GENERIC_ENTRY); + Entry = (IVHD_GENERIC_ENTRY *) ((UINT8 *) Ivhd + Ivhd->Length); + Entry->Type = IvhdEntryEndRange; + Entry->DeviceId = DEVICE_ID (EndRange); + Ivhd->Length += sizeof (IVHD_GENERIC_ENTRY); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Create IVHDR entry for aliased range + * + * + * @param[in] StartRange Address of start range + * @param[in] EndRange Address of end range + * @param[in] Alias Address of alias requestor ID for range + * @param[in] DataSetting Data setting + * @param[in] Ivhd Pointer to IVHD entry + * @param[in] StdHeader Standard configuration header + * + */ +VOID +GnbIvhdAddDeviceAliasRangeEntry ( + IN PCI_ADDR StartRange, + IN PCI_ADDR EndRange, + IN PCI_ADDR Alias, + IN UINT8 DataSetting, + IN IVRS_IVHD_ENTRY *Ivhd, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + IVHD_ALIAS_ENTRY *RangeEntry; + IVHD_GENERIC_ENTRY *Entry; + UINT16 Offset; + Offset = (Ivhd->Length + 0x7) & (~ 0x7); + RangeEntry = (IVHD_ALIAS_ENTRY *) ((UINT8 *) Ivhd + Offset); + RangeEntry->Type = IvhdEntryAliasStartRange; + RangeEntry->DeviceId = DEVICE_ID (StartRange); + RangeEntry->AliasDeviceId = DEVICE_ID (Alias); + RangeEntry->DataSetting = DataSetting; + Ivhd->Length = sizeof (IVHD_ALIAS_ENTRY) + Offset; + Entry = (IVHD_GENERIC_ENTRY *) ((UINT8 *) Ivhd + Ivhd->Length); + Entry->Type = IvhdEntryEndRange; + Entry->DeviceId = DEVICE_ID (EndRange); + Ivhd->Length += sizeof (IVHD_GENERIC_ENTRY); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Create IVHDR entry for special device + * + * + * @param[in] SpecialDevice Special device Type + * @param[in] Device Address of requestor ID for special device + * @param[in] Id Apic ID/ Hpet ID + * @param[in] DataSetting Data setting + * @param[in] Ivhd Pointer to IVHD entry + * @param[in] StdHeader Standard configuration header + * + */ +VOID +GnbIvhdAddSpecialDeviceEntry ( + IN IVHD_SPECIAL_DEVICE SpecialDevice, + IN PCI_ADDR Device, + IN UINT8 Id, + IN UINT8 DataSetting, + IN IVRS_IVHD_ENTRY *Ivhd, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + IVHD_SPECIAL_ENTRY *SpecialEntry; + UINT16 Offset; + Offset = (Ivhd->Length + 0x7) & (~ 0x7); + SpecialEntry = (IVHD_SPECIAL_ENTRY *) ((UINT8 *) Ivhd + Offset); + SpecialEntry->Type = IvhdEntrySpecialDevice; + SpecialEntry->AliasDeviceId = DEVICE_ID (Device); + SpecialEntry->Variety = (UINT8) SpecialDevice; + SpecialEntry->Handle = Id; + SpecialEntry->DataSetting = DataSetting; + Ivhd->Length = sizeof (IVHD_SPECIAL_ENTRY) + Offset; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Create IVMD entry + * + * + * @param[in] Type Root type for IVMD (IvrsIvmdBlock or IvrsIvmdrBlock) + * @param[in] StartDevice Device ID of start device range + * Use 0x0000 for ALL + * @param[in] EndDevice Device ID of end device range + * Use 0xFFFF for ALL + * Use == StartDevice for specific device + * @param[in] BlockAddress Address of memory block to be excluded + * @param[in] BlockLength Length of memory block go be excluded + * @param[in] Ivmd Pointer to IVMD entry + * @param[in] StdHeader Standard configuration header + * + */ +VOID +GnbIvmdAddEntry ( + IN IVRS_BLOCK_TYPE Type, + IN UINT16 StartDevice, + IN UINT16 EndDevice, + IN UINT64 BlockAddress, + IN UINT64 BlockLength, + IN IVRS_IVMD_ENTRY *Ivmd, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + Ivmd->Flags = IVMD_FLAG_EXCLUSION_RANGE; + Ivmd->Length = sizeof (IVRS_IVMD_ENTRY); + Ivmd->DeviceId = StartDevice; + Ivmd->AuxiliaryData = 0x0; + Ivmd->Reserved = 0x0000000000000000; + Ivmd->BlockStart = BlockAddress; + Ivmd->BlockLength = BlockLength; + if (Type == IvrsIvmdBlock) { + if (StartDevice == EndDevice) { + Ivmd->Type = IvrsIvmdBlockSingle; + } else if ((StartDevice == 0x0000) && (EndDevice == 0xFFFF)) { + Ivmd->Type = IvrsIvmdBlock; + } else { + Ivmd->Type = IvrsIvmdBlockRange; + Ivmd->AuxiliaryData = EndDevice; + } + } else { + if (StartDevice == EndDevice) { + Ivmd->Type = IvrsIvmdrBlockSingle; + } else { + Ivmd->Type = IvrsIvmdrBlock; + } + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.h new file mode 100644 index 0000000..5291d34 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.h @@ -0,0 +1,117 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe ALIB + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _GNBIVRSLIB_H_ +#define _GNBIVRSLIB_H_ + + +VOID +GnbIvhdAddDeviceRangeEntry ( + IN PCI_ADDR StartRange, + IN PCI_ADDR EndRange, + IN UINT8 DataSetting, + IN IVRS_IVHD_ENTRY *Ivhd, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbIvhdAddDeviceAliasRangeEntry ( + IN PCI_ADDR StartRange, + IN PCI_ADDR EndRange, + IN PCI_ADDR Alias, + IN UINT8 DataSetting, + IN IVRS_IVHD_ENTRY *Ivhd, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbIvhdAddSpecialDeviceEntry ( + IN IVHD_SPECIAL_DEVICE SpecialDevice, + IN PCI_ADDR Device, + IN UINT8 Id, + IN UINT8 DataSetting, + IN IVRS_IVHD_ENTRY *Ivhd, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbIvmdAddEntry ( + IN IVRS_BLOCK_TYPE Type, + IN UINT16 StartDevice, + IN UINT16 EndDevice, + IN UINT64 BlockAddress, + IN UINT64 BlockLength, + IN IVRS_IVMD_ENTRY *Ivmd, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c new file mode 100644 index 0000000..f160e8b --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c @@ -0,0 +1,203 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB UNB library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "cpuServices.h" +#include "Gnb.h" +#include "GnbCommonLib.h" +#include "GnbFamServices.h" +#include "GnbPcieConfig.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBMSOCKETLIB_GNBMSOCKETLIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get Host bridge PCI Address + * + * + * + * @param[in] GnbHandle Socket ID + * @param[in] StdHeader Standard configuration header + * @retval PCI address of GNB for a given socket/silicon. + */ + +PCI_ADDR +GnbFmGetPciAddress ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR GnbPciAddress; + UINT8 NodeId; + UINT8 Register; + UINT32 Value; + GnbPciAddress.AddressValue = ILLEGAL_SBDFO; + NodeId = GnbGetNodeId (GnbHandle); + for (Register = 0xE0; Register <= 0xEC; Register = Register + 4) { + GnbLibPciRead (MAKE_SBDFO (0, 0, 24 + NodeId, 1, Register), AccessWidth32, &Value, StdHeader); + if (((Value >> 4) & 0x7) == NodeId) { + GnbPciAddress.AddressValue = MAKE_SBDFO (0, (Value >> 16) & 0xff, 0, 0, 0); + break; + } + } + ASSERT (GnbPciAddress.AddressValue != ILLEGAL_SBDFO); + return GnbPciAddress; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get bus range decoded by GNB + * + * Final bus allocation can not be assumed until AmdInitMid + * + * @param[in] GnbHandle GNB handle + * @param[out] StartBusNumber Beggining of the Bus Range + * @param[out] EndBusNumber End of the Bus Range + * @param[in] StdHeader Standard configuration header + * @retval Satus + */ +AGESA_STATUS +GnbFmGetBusDecodeRange ( + IN GNB_HANDLE *GnbHandle, + OUT UINT8 *StartBusNumber, + OUT UINT8 *EndBusNumber, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 NodeId; + UINT8 Register; + UINT32 Value; + AGESA_STATUS Status; + Status = AGESA_ERROR; + NodeId = GnbGetNodeId (GnbHandle); + for (Register = 0xE0; Register <= 0xEC; Register = Register + 4) { + GnbLibPciRead (MAKE_SBDFO (0, 0, 24 + NodeId, 1, Register), AccessWidth32, &Value, StdHeader); + if (((Value >> 4) & 0x7) == NodeId) { + *StartBusNumber = (UINT8) ((Value >> 16) & 0xff); + *EndBusNumber = (UINT8) ((Value >> 24) & 0xff); + Status = AGESA_SUCCESS; + break; + } + } + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get link to which GNB connected to + * + * + * @param[in] GnbHandle GNB handle + * @param[out] LinkId Link to which GNB connected to + * @param[in] StdHeader Standard configuration header + * @retval Satus + */ + +AGESA_STATUS +GnbFmGetLinkId ( + IN GNB_HANDLE *GnbHandle, + OUT UINT8 *LinkId, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Value; + ASSERT (GnbHandle->NodeId != 0xFF); + GnbLibPciRead (MAKE_SBDFO (0, 0, 0x18 + GnbHandle->NodeId, 0, 0x1A0), AccessWidth32, &Value, StdHeader); + *LinkId = LibAmdBitScanForward (Value & 0xAAAA) / 2; + ASSERT (*LinkId < 8); + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c new file mode 100644 index 0000000..942d34d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c @@ -0,0 +1,432 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbFuseTable.h" +#include "GnbCommonLib.h" +#include "GnbNbInitLibV1.h" +#include "GnbRegistersLN.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBNBINITLIBV1_GNBNBINITLIBV1_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Init NB set top of memory + * + * + * + * @param[in] NbPciAddress Gnb PCI address + * @param[in] StdHeader Standard Configuration Header + */ + +AGESA_STATUS +GnbSetTom ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + UINT64 MsrData; + UINT32 Value; + Status = AGESA_SUCCESS; + //Read memory size below 4G from MSR C001_001A + LibAmdMsrRead (TOP_MEM, &MsrData, StdHeader); + //Write to NB register 0x90 + Value = (UINT32)MsrData & 0xFF800000; //Keep bits 31:23 + GnbLibPciRMW ( + NbPciAddress.AddressValue | D0F0x90_ADDRESS, + AccessS3SaveWidth32, + 0x007FFFFF, + Value, + StdHeader + ); + if (Value == 0) { + Status = AGESA_WARNING; + } + + LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader); + if ((MsrData & BIT21) != 0) { + //Read memory size above 4G from MSR C001_001D + LibAmdMsrRead (TOP_MEM2, &MsrData, StdHeader); + // Write memory size[39:32] to indirect register 1A[7:0] + Value = (UINT32) ((MsrData >> 32) & 0xFF); + GnbLibPciIndirectRMW ( + NbPciAddress.AddressValue | D0F0x60_ADDRESS, + D0F0x64_x1A_ADDRESS | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + 0xFFFFFF00, + Value, + StdHeader + ); + + // Write memory size[31:23] to indirect register 19[31:23] and enable memory through bit 0 + Value = (UINT32)MsrData & 0xFF800000; //Keep bits 31:23 + Value |= BIT0; // Enable top of memory + GnbLibPciIndirectRMW ( + NbPciAddress.AddressValue | D0F0x60_ADDRESS, + D0F0x64_x19_ADDRESS | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + 0x007FFFFF, + Value, + StdHeader + ); + } + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Avoid LPC DMA transaction deadlock + * + * + * + * @param[in] NbPciAddress Gnb PCI address + * @param[in] StdHeader Standard Configuration Header + */ + +VOID +GnbLpcDmaDeadlockPrevention ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + // For GPP Link core, enable special NP memory write protocol on the processor side PCIE controller + GnbLibPciIndirectRMW ( + NbPciAddress.AddressValue | D0F0xE0_ADDRESS, + CORE_SPACE (1, D0F0xE4_CORE_0010_ADDRESS), + AccessWidth32, + 0xFFFFFFFF, + 1 << 9 , + StdHeader + ); + + //Enable special NP memory write protocol in ORB + GnbLibPciIndirectRMW ( + NbPciAddress.AddressValue | D0F0x94_ADDRESS, + D0F0x98_x06_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), + AccessS3SaveWidth32, + 0xFFFFFFFF, + 1 << D0F0x98_x06_UmiNpMemWrEn_OFFSET, + StdHeader + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * NB Dynamic Wake + * ORB_CNB_Wake signal is used to inform the CNB NCLK controller and GNB LCLK controller + * that ORB is (or will soon) push data into the synchronizer FIFO (i.e. wake is high). + * + * @param[in] NbPciAddress Gnb PCI address + * @param[in] StdHeader Standard Configuration Header + */ + +VOID +GnbOrbDynamicWake ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + ex495_STRUCT ex495 ; + + GnbLibPciIndirectRead ( + NbPciAddress.AddressValue | D0F0x94_ADDRESS, + 0x2c | (1 << D0F0x94_OrbIndWrEn_OFFSET), + AccessWidth32, + &ex495.Value, + StdHeader + ); + + // Enable Dynamic wake + // Wake Hysteresis timer value. Specifies the number of SMU pulses to count. + if (GnbBuildOptions.CfgOrbDynWakeEnable) { + ex495.Field.ex495_1 = 1; + } else { + ex495.Field.ex495_1 = 0; + } + ex495.Field.ex495_3 = 0x64; + + IDS_OPTION_HOOK (IDS_GNB_ORBDYNAMIC_WAKE, &ex495, StdHeader); + + GnbLibPciIndirectWrite ( + NbPciAddress.AddressValue | D0F0x94_ADDRESS, + 0x2c | (1 << D0F0x94_OrbIndWrEn_OFFSET), + AccessS3SaveWidth32, + &ex495.Value, + StdHeader + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Lock NB registers + * + * + * + * @param[in] NbPciAddress Gnb PCI address + * @param[in] StdHeader Standard Configuration Header + */ + +VOID +GnbLock ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GnbLibPciIndirectWriteField ( + NbPciAddress.AddressValue | D0F0x60_ADDRESS, + D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE, + D0F0x64_x00_HwInitWrLock_OFFSET, + D0F0x64_x00_HwInitWrLock_WIDTH, + 0x1, + TRUE, + StdHeader + ); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * UnitID Clumping + * + * + * @param[in] NbPciAddress Gnb PCI address + * @param[in] StdHeader Standard Configuration Header + */ + +VOID +GnbClumpUnitID ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Value; + GnbLibPciRead (MAKE_SBDFO (0, NbPciAddress.Address.Bus, 2, 0, 0), AccessWidth32, &Value, StdHeader); + if (Value != 0xFFFFFFFF) { + GnbLibPciRead (MAKE_SBDFO (0, NbPciAddress.Address.Bus, 3, 0, 0), AccessWidth32, &Value, StdHeader); + if (Value == 0xFFFFFFFF) { + GnbLibPciIndirectRMW ( + NbPciAddress.AddressValue | D0F0x94_ADDRESS, + 0x3a | (1 << D0F0x94_OrbIndWrEn_OFFSET), + AccessS3SaveWidth32, + 0xFFFFFFFF, + 1 << 3 /* D0F0x98_x3A_ClumpingEn_OFFSET*/, + StdHeader + ); + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get the index of highest SCLK VID + * + * @param[in] StdHeader Standard configuration header + * @retval NBVDD VID index + */ +UINT8 +GnbLocateHighestVidIndex ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 MaxVid; + UINT8 MaxVidIndex; + UINTN Index; + PP_FUSE_ARRAY *PpFuseArray; + + PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); + ASSERT (PpFuseArray != NULL); + if (PpFuseArray == NULL) { + IDS_HDT_CONSOLE (GNB_TRACE, " ERROR!!! Heap Location\n"); + return 0; + } + + MaxVidIndex = 0; + MaxVid = 0xff; + for (Index = 0; Index < 4; Index++) { + if (PpFuseArray->SclkVid[Index] != 0 && PpFuseArray->SclkVid[Index] < MaxVid) { + MaxVid = PpFuseArray->SclkVid[Index]; + MaxVidIndex = (UINT8) Index; + } + } + ASSERT (PpFuseArray->SclkVid[MaxVidIndex] != 0); + return MaxVidIndex; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get the index of lowest SCLK VID + * + * @param[in] StdHeader Standard configuration header + * @retval NBVDD VID index + */ +UINT8 +GnbLocateLowestVidIndex ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 MinVidIndex; + UINTN Index; + PP_FUSE_ARRAY *PpFuseArray; + + PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); + ASSERT (PpFuseArray != NULL); + if (PpFuseArray == NULL) { + IDS_HDT_CONSOLE (GNB_TRACE, " ERROR!!! Heap Location\n"); + return 0; + } + + MinVidIndex = 0; + + for (Index = 0; Index < 4; Index++) { + if (PpFuseArray->SclkVid[Index] > PpFuseArray->SclkVid[MinVidIndex]) { + MinVidIndex = (UINT8) Index; + } + } + ASSERT (PpFuseArray->SclkVid[MinVidIndex] != 0); + return MinVidIndex; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get the highest SCLK VID (high voltage) + * + * @param[in] StdHeader Standard configuration header + * @retval NBVDD VID + */ +UINT8 +GnbLocateHighestVidCode ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 MaxVidIndex; + PP_FUSE_ARRAY *PpFuseArray; + + PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); + ASSERT (PpFuseArray != NULL); + + MaxVidIndex = GnbLocateHighestVidIndex (StdHeader); + ASSERT (PpFuseArray->SclkVid[MaxVidIndex] != 0); + return PpFuseArray->SclkVid[MaxVidIndex]; + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get the lowest SCLK VID (low voltage) + * + * @param[in] StdHeader Standard configuration header + * @retval NBVDD VID + */ +UINT8 +GnbLocateLowestVidCode ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 MinVidIndex; + PP_FUSE_ARRAY *PpFuseArray; + + PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); + ASSERT (PpFuseArray != NULL); + MinVidIndex = GnbLocateLowestVidIndex (StdHeader); + ASSERT (PpFuseArray->SclkVid[MinVidIndex] != 0); + return PpFuseArray->SclkVid[MinVidIndex]; +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h new file mode 100644 index 0000000..948ee4c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h @@ -0,0 +1,126 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBNBINITLIBV1_H_ +#define _GNBNBINITLIBV1_H_ + + +AGESA_STATUS +GnbSetTom ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbLpcDmaDeadlockPrevention ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbOrbDynamicWake ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbLock ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbClumpUnitID ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +GnbLocateHighestVidIndex ( + IN AMD_CONFIG_PARAMS *StdHeader + ); +UINT8 +GnbLocateLowestVidIndex ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +GnbLocateHighestVidCode ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +GnbLocateLowestVidCode ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c new file mode 100644 index 0000000..faf7298 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c @@ -0,0 +1,620 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 64352 $ @e $Date: 2012-01-19 03:54:04 -0600 (Thu, 19 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "S3SaveState.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "GnbPcieInitLibV1.h" +#include "GnbNbInitLibV4.h" +#include "GnbRegistersTN.h" +#include "heapManager.h" +#include "GnbFamServices.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBNBINITLIBV4_GNBNBINITLIBV4_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +#define SMC_RAM_START_ADDR 0x10000ul + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +typedef struct { + GNB_PCI_SCAN_DATA ScanData; + GNB_TOPOLOGY_INFO *TopologyInfo; +} GNB_TOPOLOGY_INFO_DATA; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +GnbSmuServiceRequestV4S3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID *Context + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Check a PCIE device to see if it supports phantom functions + * + * @param[in] Device Device pci address + * @param[in] StdHeader Standard configuration header + * @return TRUE Current device supports phantom functions + */ +STATIC BOOLEAN +GnbCheckPhantomFuncSupport ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 PcieCapPtr; + UINT32 Value; + Value = 0; + + PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader); + if (PcieCapPtr != 0) { + GnbLibPciRead (Device.AddressValue | (PcieCapPtr + 4), AccessWidth32, &Value, StdHeader); + } + return ((Value & (BIT3 | BIT4)) != 0) ? TRUE : FALSE; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Evaluate device + * + * + * + * @param[in] Device PCI Address + * @param[in,out] ScanData Scan configuration data + * @retval Scan Status + */ + +SCAN_STATUS +STATIC +GnbTopologyInfoScanCallback ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ) +{ + SCAN_STATUS ScanStatus; + GNB_TOPOLOGY_INFO_DATA *GnbTopologyInfo; + PCIE_DEVICE_TYPE DeviceType; + ScanStatus = SCAN_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, " GnbIommuInfoScanCallback for Device = %d:%d:%d\n", + Device.Address.Bus, + Device.Address.Device, + Device.Address.Function + ); + GnbTopologyInfo = (GNB_TOPOLOGY_INFO_DATA *)ScanData; + ScanStatus = SCAN_SUCCESS; + DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader); + switch (DeviceType) { + case PcieDeviceRootComplex: + case PcieDeviceDownstreamPort: + GnbLibPciScanSecondaryBus (Device, &GnbTopologyInfo->ScanData); + break; + case PcieDeviceUpstreamPort: + GnbLibPciScanSecondaryBus (Device, &GnbTopologyInfo->ScanData); + ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; + break; + case PcieDevicePcieToPcix: + GnbTopologyInfo->TopologyInfo->PcieToPciexBridge = TRUE; + ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; + break; + case PcieDeviceEndPoint: + case PcieDeviceLegacyEndPoint: + if (GnbCheckPhantomFuncSupport (Device, ScanData->StdHeader)) { + GnbTopologyInfo->TopologyInfo->PhantomFunction = TRUE; + } + ScanStatus = SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; + break; + default: + break; + } + return ScanStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get IOMMU topology info + * + * + * + * @param[in] StartPciAddress Start PCI address + * @param[in] EndPciAddress End PCI address + * @param[in] TopologyInfo Topology info structure + * @param[in] StdHeader Standard Configuration Header + */ + +AGESA_STATUS +GnbGetTopologyInfoV4 ( + IN PCI_ADDR StartPciAddress, + IN PCI_ADDR EndPciAddress, + OUT GNB_TOPOLOGY_INFO *TopologyInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GNB_TOPOLOGY_INFO_DATA GnbTopologyInfo; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbGetTopologyInfoV4 Enter\n"); + GnbTopologyInfo.ScanData.GnbScanCallback = GnbTopologyInfoScanCallback; + GnbTopologyInfo.ScanData.StdHeader = StdHeader; + GnbTopologyInfo.TopologyInfo = TopologyInfo; + GnbLibPciScan (StartPciAddress, EndPciAddress, &GnbTopologyInfo.ScanData); + IDS_HDT_CONSOLE (GNB_TRACE, "GnbGetTopologyInfoV4 Exit\n"); + return AGESA_SUCCESS; +} + + + +/*----------------------------------------------------------------------------------------*/ +/** + * SMU service request + * + * + * @param[in] GnbPciAddress GNB PCI address + * @param[in] RequestId Request ID + * @param[in] AccessFlags See GNB_ACCESS_FLAGS_* definitions + * @param[in] StdHeader Standard configuration header + */ + +VOID +GnbSmuServiceRequestV4 ( + IN PCI_ADDR GnbPciAddress, + IN UINT8 RequestId, + IN UINT32 AccessFlags, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D0F0xBC_xE0003004_STRUCT D0F0xBC_xE0003004; + D0F0xBC_xE0003000_STRUCT D0F0xBC_xE0003000; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuServiceRequestV4 Enter\n"); + IDS_HDT_CONSOLE (NB_MISC, " Service Request %d\n", RequestId); + + if ((AccessFlags & GNB_REG_ACC_FLAG_S3SAVE) != 0) { + SMU_MSG_CONTEXT SmuMsgContext; + SmuMsgContext.GnbPciAddress.AddressValue = GnbPciAddress.AddressValue; + SmuMsgContext.RequestId = RequestId; + S3_SAVE_DISPATCH (StdHeader, GnbSmuServiceRequestV4S3Script_ID, sizeof (SmuMsgContext), &SmuMsgContext); + } + do { + GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0003004_ADDRESS, AccessWidth32, &D0F0xBC_xE0003004.Value, StdHeader); + } while (D0F0xBC_xE0003004.Field.IntDone == 0x0); + GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0003000_ADDRESS, AccessWidth32, &D0F0xBC_xE0003000.Value, StdHeader); + D0F0xBC_xE0003000.Field.IntToggle = ~D0F0xBC_xE0003000.Field.IntToggle; + D0F0xBC_xE0003000.Field.ServiceIndex = RequestId; + GnbLibPciIndirectWrite (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0003000_ADDRESS, AccessWidth32, &D0F0xBC_xE0003000.Value, StdHeader); + do { + GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0003004_ADDRESS, AccessWidth32, &D0F0xBC_xE0003004.Value, StdHeader); + } while (D0F0xBC_xE0003004.Field.IntAck == 0x0); + do { + GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0003004_ADDRESS, AccessWidth32, &D0F0xBC_xE0003004.Value, StdHeader); + } while (D0F0xBC_xE0003004.Field.IntDone == 0x0); + IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuServiceRequestV4 Exit\n"); +} +/*----------------------------------------------------------------------------------------*/ +/** + * SMU service request for S3 script + * + * + * @param[in] StdHeader Standard configuration header + * @param[in] ContextLength Context length + * @param[in] Context Pointer to Context + */ + +VOID +GnbSmuServiceRequestV4S3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID *Context + ) +{ + SMU_MSG_CONTEXT *SmuMsgContext; + SmuMsgContext = (SMU_MSG_CONTEXT *) Context; + GnbSmuServiceRequestV4 (SmuMsgContext->GnbPciAddress, SmuMsgContext->RequestId, 0, StdHeader); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * SMU firmware download + * + * + * @param[in] GnbPciAddress GNB Pci Address + * @param[in] Firmware Pointer tp firmware + * @param[in] StdHeader Standard configuration header + */ + +AGESA_STATUS +GnbSmuFirmwareLoadV4 ( + IN PCI_ADDR GnbPciAddress, + IN FIRMWARE_HEADER_V4 *Firmware, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + UINT32 Index; + D0F0xBC_xE00030A4_STRUCT D0F0xBC_xE00030A4; + D0F0xBC_xE0000004_STRUCT D0F0xBC_xE0000004; + D0F0xBC_xE0003088_STRUCT D0F0xBC_xE0003088; + ex1005_STRUCT ex1005 ; + D0F0xBC_x1F380_STRUCT D0F0xBC_x1F380; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuFirmwareLoadV4 Enter\n"); + IDS_HDT_CONSOLE (NB_MISC, " Firmware version 0x%x\n", Firmware->Version); + // Step 2, 10, make sure Rom firmware sequance is done + do { + GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0000004_ADDRESS, AccessWidth32, &D0F0xBC_xE0000004.Value, StdHeader); + } while (D0F0xBC_xE0000004.Field.boot_seq_done == 0); + // Step 1, check if firmware running in protected mode + GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE00030A4_ADDRESS, AccessWidth32, &D0F0xBC_xE00030A4.Value, StdHeader); + if (D0F0xBC_xE00030A4.Field.SmuProtectedMode == 0) { + // Step3, Clear firmware interrupt flags + GnbLibPciIndirectRMW ( + GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, + D0F0xBC_x1F380_ADDRESS, + AccessWidth32, + 0x0, + 0x0, + StdHeader + ); + } + //Step 4, 11, Assert LM32 reset + GnbLibPciIndirectRMW ( + GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, + 0x80000000 , + AccessWidth32, + (UINT32) ~(0x1 ), + 1 << 0 , + StdHeader + ); + // Step5, 12, Load firmware + for (Index = 0; Index < (Firmware->FirmwareLength + Firmware->HeaderLength); Index++) { + GnbLibPciIndirectWrite (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, SMC_RAM_START_ADDR + (Index * 4), AccessWidth32, &((UINT32 *) Firmware)[Index], StdHeader); + } + if (D0F0xBC_xE00030A4.Field.SmuProtectedMode == 0) { + //Step 6, Write jmp to RAM firmware + GnbLibPciIndirectRMW ( + GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, + 0x0, + AccessWidth32, + 0x0, + 0xE0000000 + ((SMC_RAM_START_ADDR + Firmware->HeaderLength * 4) >> 2), + StdHeader + ); + } else { + //Step 13, Clear autentification done + GnbLibPciIndirectRMW ( + GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, + D0F0xBC_xE0003088_ADDRESS, + AccessWidth32, + 0x0, + 0x0, + StdHeader + ); + } + // Step 7, 14 Enable LM32 clock + GnbLibPciIndirectRMW ( + GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, + 0x80000004 , + AccessWidth32, + (UINT32) ~(0x1 ), + 0 << 0 , + StdHeader + ); + + //Step 8, 15, Deassert LM32 reset + GnbLibPciIndirectRMW ( + GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, + 0x80000000 , + AccessWidth32, + (UINT32) ~(0x1 ), + 0 << 0 , + StdHeader + ); + + if (D0F0xBC_xE00030A4.Field.SmuProtectedMode == 1) { + IDS_HDT_CONSOLE (NB_MISC, " Protected mode: poll init autehtication vector\n"); + // Step 16, Wait for rom firmware init autehtication vector + do { + GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, 0x80010000 , AccessWidth32, &ex1005.Value, StdHeader); + } while (ex1005.Value != 0x400); + // Call Authentication service + GnbSmuServiceRequestV4 (GnbPciAddress, SMC_MSG_FIRMWARE_AUTH, 0, StdHeader); + IDS_HDT_CONSOLE (NB_MISC, " Protected mode: poll init autehtication done\n"); + // Wait for autehtication done + do { + GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0003088_ADDRESS, AccessWidth32, &D0F0xBC_xE0003088.Value, StdHeader); + } while (D0F0xBC_xE0003088.Field.SmuAuthDone == 0x0); + //Step 17, Check Authentication results + if (D0F0xBC_xE0003088.Field.SmuAuthPass == 0) { + IDS_HDT_CONSOLE (NB_MISC, " ERROR!!!Autehtication fail!!!\n"); + ASSERT (FALSE); + return AGESA_FATAL; + } + // Step 18, Clear firmware interrupt enable flag + GnbLibPciIndirectRMW ( + GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, + D0F0xBC_x1F380_ADDRESS, + AccessWidth32, + 0x0, + 0x0, + StdHeader + ); + //Step 19, Assert LM32 reset + GnbLibPciIndirectRMW ( + GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, + 0x80000000 , + AccessWidth32, + (UINT32) ~(0x1 ), + 1 << 0 , + StdHeader + ); + //Step 20, Deassert LM32 reset + GnbLibPciIndirectRMW ( + GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, + 0x80000000 , + AccessWidth32, + (UINT32) ~(0x1 ), + 0 << 0 , + StdHeader + ); + } +//Step 9, 21 Wait firmware to initialize + do { + GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_x1F380_ADDRESS, AccessWidth32, &D0F0xBC_x1F380.Value, StdHeader); + } while (D0F0xBC_x1F380.Field.InterruptsEnabled == 0); + IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuFirmwareLoadV4 Exit\n"); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get IOMMU PCI address + * + * + * @param[in] GnbHandle GNB handle + * @param[in] StdHeader Standard configuration header + */ + +PCI_ADDR +GnbGetIommuPciAddressV4 ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR GnbIommuPciAddress; + GnbIommuPciAddress = GnbGetHostPciAddress (GnbHandle); + GnbIommuPciAddress.Address.Function = 0x2; + return GnbIommuPciAddress; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * UnitID Clumping + * + * + * @param[in] GnbHandle GNB handle + * @param[in] StdHeader Standard configuration header + */ + +VOID +GnbClumpUnitIdV4 ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + PCIe_ENGINE_CONFIG *EngineList; + UINT32 Value; + + Value = 0; + EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetChild (DESCRIPTOR_PCIE_ENGINE, &GnbHandle->Header); + while (EngineList != NULL) { + if (EngineList->Type.Port.NumberOfUnitId != 0) { + if (!PcieConfigIsActivePcieEngine (EngineList)) { + Value |= (((1 << EngineList->Type.Port.NumberOfUnitId) - 1) << EngineList->Type.Port.UnitId); + } else { + if (EngineList->Type.Port.NumberOfUnitId > 1) { + Value |= (((1 << (EngineList->Type.Port.NumberOfUnitId - 1)) - 1) << (EngineList->Type.Port.UnitId + 1)); + } + } + } + EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (EngineList, DESCRIPTOR_TERMINATE_GNB); + } + // Set GNB + GnbLibPciIndirectRMW ( + GnbHandle->Address.AddressValue | D0F0x94_ADDRESS, + D0F0x98_x3A_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), + AccessS3SaveWidth32, + (UINT32) ~Value, + Value, + StdHeader + ); + //Set UNB + GnbLibPciRMW ( + MAKE_SBDFO (0, 0, GnbHandle->NodeId + 0x18, 0, D18F0x110_ADDRESS + GnbHandle->LinkId * 4), + AccessS3SaveWidth32, + (UINT32) ~Value, + Value, + StdHeader + ); +} + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Config GNB to prevent LPC deadlock scenario + * + * + * @param[in] GnbHandle GNB handle + * @param[in] StdHeader Standard configuration header + */ + +VOID +GnbLpcDmaDeadlockPreventionV4 ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_ENGINE_CONFIG *EngineList; + + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &GnbHandle->Header); + EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_ENGINES, &GnbHandle->Header); + while (EngineList != NULL) { + if (PcieConfigIsPcieEngine (EngineList) && PcieConfigIsSbPcieEngine (EngineList)) { + PcieRegisterRMW ( + PcieConfigGetParentWrapper (EngineList), + CORE_SPACE (EngineList->Type.Port.CoreId, D0F0xE4_CORE_0010_ADDRESS), + D0F0xE4_CORE_0010_UmiNpMemWrite_MASK, + 1 << D0F0xE4_CORE_0010_UmiNpMemWrite_OFFSET, + TRUE, + Pcie + ); + //Enable special NP memory write protocol in ORB + GnbLibPciIndirectRMW ( + GnbHandle->Address.AddressValue | D0F0x94_ADDRESS, + D0F0x98_x06_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET), + AccessS3SaveWidth32, + 0xFFFFFFFF, + 1 << D0F0x98_x06_UmiNpMemWrEn_OFFSET, + StdHeader + ); + break; + } + EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (EngineList, DESCRIPTOR_TERMINATE_GNB); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Enable IOMMU base address. (MMIO space ) + * + * + * + * @param[in] StdHeader Standard Configuration Header + * @retval AGESA_SUCCESS + * @retval AGESA_ERROR + */ + +AGESA_STATUS +GnbEnableIommuMmioV4 ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + UINT16 CapabilityOffset; + UINT64 BaseAddress; + UINT32 Value; + PCI_ADDR GnbIommuPciAddress; + + Status = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnableIommuMmio Enter\n"); + + if (GnbFmCheckIommuPresent (GnbHandle, StdHeader)) { + GnbIommuPciAddress = GnbGetIommuPciAddressV4 (GnbHandle, StdHeader); + CapabilityOffset = GnbLibFindPciCapability (GnbIommuPciAddress.AddressValue, IOMMU_CAP_ID, StdHeader); + + GnbLibPciRead (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x4), AccessWidth32, &Value, StdHeader); + BaseAddress = (UINT64) Value << 32; + GnbLibPciRead (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x8), AccessWidth32, &Value, StdHeader); + BaseAddress |= Value; + + if ((BaseAddress & 0xfffffffffffffffe) != 0x0) { + IDS_HDT_CONSOLE (GNB_TRACE, " Enable IOMMU MMIO at address %x for Socket %d Silicon %d\n", BaseAddress, GnbGetSocketId (GnbHandle) , GnbGetSiliconId (GnbHandle)); + GnbLibPciRMW (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x8), AccessS3SaveWidth32, 0xFFFFFFFF, 0x0, StdHeader); + GnbLibPciRMW (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x4), AccessS3SaveWidth32, 0xFFFFFFFE, 0x1, StdHeader); + } else { + ASSERT (FALSE); + Status = AGESA_ERROR; + } + } + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnableIommuMmio Exit\n"); + return Status; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.h new file mode 100644 index 0000000..95d97df --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.h @@ -0,0 +1,149 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 64352 $ @e $Date: 2012-01-19 03:54:04 -0600 (Thu, 19 Jan 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ +#ifndef _GNBNBINITLIBV4_H_ +#define _GNBNBINITLIBV4_H_ + +#pragma pack (push, 1) + +/// Firmware header +typedef struct { + UINT32 Version; ///< Version + UINT32 HeaderLength; ///< Header length + UINT32 FirmwareLength; ///< Firmware length + UINT32 EntryPoint; ///< Entry point + UINT32 MessageDigest[5]; ///< Message digest + UINT32 Reserved_A[3]; ///< Reserved + UINT32 CurrentSystemState; ///< Current system state + UINT32 DpmCacHistory; ///< DpmCac History + UINT32 DpmResidencyCounters; ///< DPM recidency counters + UINT32 Reserved_B[16]; ///< Reserved + UINT32 Reserved_C[16]; ///< Reserved + UINT32 Reserved_D[16]; ///< Reserved + UINT32 HeaderEnd; ///< Header end signature +} FIRMWARE_HEADER_V4; + +/// SMU service request contect +typedef struct { + PCI_ADDR GnbPciAddress; ///< PCIe address of GNB + UINT8 RequestId; ///< Request/Msg ID +} SMU_MSG_CONTEXT; + +#pragma pack (pop) + +AGESA_STATUS +GnbGetTopologyInfoV4 ( + IN PCI_ADDR StartPciAddress, + IN PCI_ADDR EndPciAddress, + OUT GNB_TOPOLOGY_INFO *TopologyInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbSmuServiceRequestV4 ( + IN PCI_ADDR GnbPciAddress, + IN UINT8 RequestId, + IN UINT32 AccessFlags, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbSmuFirmwareLoadV4 ( + IN PCI_ADDR GnbPciAddress, + IN FIRMWARE_HEADER_V4 *Firmware, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +PCI_ADDR +GnbGetIommuPciAddressV4 ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbClumpUnitIdV4 ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GnbLpcDmaDeadlockPreventionV4 ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbEnableIommuMmioV4 ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c new file mode 100644 index 0000000..1b3742d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c @@ -0,0 +1,578 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe ALIB + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + + +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "cpuLateInit.h" +#include "cpuRegisters.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbNbInitLibV1.h" +#include "GnbRegistersLN.h" +#include "OptionGnb.h" +#include "PcieAlib.h" +#include "GnbFuseTable.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEALIBV1_PCIEALIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern F_ALIB_GET *AlibGetBaseTable; +extern F_ALIB_UPDATE *AlibDispatchTable[]; + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +PcieAlibUpdatePcieMmioInfo ( + IN OUT VOID *AlibSsdtBuffer, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PcieAlibUpdateVoltageInfo ( + IN OUT VOID *AlibSsdtBuffer, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PcieAlibUpdatePcieInfo ( + IN OUT VOID *AlibSsdtBuffer, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +PcieAlibSetPortMaxSpeedCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +STATIC +PcieAlibSetPortOverrideSpeedCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +STATIC +PcieAlibSetPortInfoCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PcieAlibBuildAcpiTable ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT VOID **AlibSsdtPtr + ); + +VOID +STATIC +PcieAlibSetSclkVid ( + IN OUT VOID *Buffer, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Create ACPI ALIB SSDT table + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +PcieAlibFeature ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AMD_LATE_PARAMS *LateParamsPtr; + LateParamsPtr = (AMD_LATE_PARAMS*) StdHeader; + return PcieAlibBuildAcpiTable (StdHeader, &LateParamsPtr->AcpiAlib); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Build ALIB ACPI table + * + * + * + * @param[in] StdHeader Standard Configuration Header + * @param[in,out] AlibSsdtPtr Pointer to pointer to ALIB SSDT table + * @retval AGESA_SUCCESS + * @retval AGESA_ERROR + */ + +AGESA_STATUS +PcieAlibBuildAcpiTable ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT VOID **AlibSsdtPtr + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + UINTN Index; + VOID *AlibSsdtBuffer; + VOID *AlibSsdtTable; + UINTN AlibSsdtlength; + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibBuildAcpiTable Enter\n"); + AgesaStatus = AGESA_SUCCESS; + AlibSsdtTable = AlibGetBaseTable (StdHeader); + AlibSsdtlength = ((ACPI_TABLE_HEADER*) AlibSsdtTable)->TableLength; + if (*AlibSsdtPtr == NULL) { + AlibSsdtBuffer = GnbAllocateHeapBuffer ( + AMD_ACPI_ALIB_BUFFER_HANDLE, + AlibSsdtlength, + StdHeader + ); + ASSERT (AlibSsdtBuffer != NULL); + if (AlibSsdtBuffer == NULL) { + return AGESA_ERROR; + } + *AlibSsdtPtr = AlibSsdtBuffer; + } else { + AlibSsdtBuffer = *AlibSsdtPtr; + } + // Copy template to buffer + LibAmdMemCopy (AlibSsdtBuffer, AlibSsdtTable, AlibSsdtlength, StdHeader); + // Disaptch fucntion form table + Index = 0; + while (AlibDispatchTable[Index] != NULL) { + Status = AlibDispatchTable[Index] (AlibSsdtBuffer, StdHeader); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + Index++; + } + if (AgesaStatus != AGESA_SUCCESS) { + //Shrink table length to size of the header + ((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength = sizeof (ACPI_TABLE_HEADER); + } + ChecksumAcpiTable ((ACPI_TABLE_HEADER*) AlibSsdtBuffer, StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibBuildAcpiTable Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Update MMIO info + * + * + * + * + * @param[in] AlibSsdtBuffer Ponter to SSDT table + * @param[in] StdHeader Standard configuration header + */ + +AGESA_STATUS +PcieAlibUpdatePcieMmioInfo ( + IN OUT VOID *AlibSsdtBuffer, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 AmlObjName; + UINT32 AlibSsdtlength; + VOID *AmlObjPtr; + AGESA_STATUS Status; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdatePcieMmioInfo Enter\n"); + Status = AGESA_SUCCESS; + AlibSsdtlength = ((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength; + AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '1'); + AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr != NULL) { + UINT64 LocalMsrRegister; + LibAmdMsrRead (MSR_MMIO_Cfg_Base, &LocalMsrRegister, StdHeader); + if ((LocalMsrRegister & BIT0) != 0 && (LocalMsrRegister & 0xFFFFFFFF00000000) == 0) { + *(UINT32*)((UINT8*) AmlObjPtr + 5) = (UINT32)(LocalMsrRegister & 0xFFFFF00000); + } else { + Status = AGESA_FATAL; + } + } else { + Status = AGESA_FATAL; + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdatePcieMmioInfo Exit\n"); + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Update MMIO info + * + * + * + * + * @param[in] AlibSsdtBuffer Ponter to SSDT table + * @param[in] StdHeader Standard configuration header + */ + +AGESA_STATUS +PcieAlibUpdateVoltageInfo ( + IN OUT VOID *AlibSsdtBuffer, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 AmlObjName; + UINT32 AlibSsdtlength; + VOID *AmlObjPtr; + UINT8 BootUpVidIndex; + UINT8 Gen1VidIndex; + PP_FUSE_ARRAY *PpFuseArray; + AGESA_STATUS Status; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdateVoltageInfo Enter\n"); + Status = AGESA_SUCCESS; + AlibSsdtlength = ((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength; + PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); + ASSERT (PpFuseArray != NULL); + if (PpFuseArray != NULL) { + AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '3'); + AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr != NULL) { + *(UINT8*)((UINT8*) AmlObjPtr + 5) = PpFuseArray->PcieGen2Vid; + } else { + Status = AGESA_FATAL; + } + } else { + Status = AGESA_FATAL; + } + + Gen1VidIndex = GnbLocateLowestVidIndex (StdHeader); + AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '4'); + AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr != NULL) { + *(UINT8*)((UINT8*) AmlObjPtr + 5) = Gen1VidIndex; + } else { + Status = AGESA_FATAL; + } + + BootUpVidIndex = GnbLocateHighestVidIndex (StdHeader); + AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '5'); + AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr != NULL) { + *(UINT8*)((UINT8*) AmlObjPtr + 5) = BootUpVidIndex; + } else { + Status = AGESA_FATAL; + } + + AmlObjName = STRING_TO_UINT32 ('A', 'D', '1', '0'); + AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr != NULL) { + PcieAlibSetSclkVid ((UINT8*) ((UINT8*)AmlObjPtr + 7), StdHeader); + } else { + Status = AGESA_FATAL; + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdateVoltageInfo Exit\n"); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Update PCIe info + * + * + * + * + * @param[in] AlibSsdtBuffer Ponter to SSDT table + * @param[in] StdHeader Standard configuration header + */ + +AGESA_STATUS +PcieAlibUpdatePcieInfo ( + IN OUT VOID *AlibSsdtBuffer, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCIe_PLATFORM_CONFIG *Pcie; + UINT32 AmlObjName; + UINT32 AlibSsdtlength; + VOID *AmlObjPtr; + AGESA_STATUS Status; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdatePcieInfo Enter\n"); + Status = AGESA_SUCCESS; + AlibSsdtlength = ((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength; + if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) { + AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '2'); + AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr != NULL) { + *(UINT8*)((UINT8*) AmlObjPtr + 5) = Pcie->PsppPolicy; + } else { + Status = AGESA_FATAL; + } + AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '6'); + AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr != NULL) { + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieAlibSetPortMaxSpeedCallback, + (UINT8*)((UINT8*) AmlObjPtr + 7), + Pcie + ); + } else { + Status = AGESA_FATAL; + } + AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '8'); + AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr != NULL) { + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieAlibSetPortOverrideSpeedCallback, + (UINT8*)((UINT8*) AmlObjPtr + 7), + Pcie + ); + } else { + Status = AGESA_FATAL; + } + AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '7'); + AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr != NULL) { + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieAlibSetPortInfoCallback, + (UINT8*)((UINT8*) AmlObjPtr + 4), + Pcie + ); + } else { + Status = AGESA_FATAL; + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdatePcieInfo Exit\n"); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init max port speed capability + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieAlibSetPortMaxSpeedCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 *PsppMaxPortSpeedPackage; + PsppMaxPortSpeedPackage = (UINT8*) Buffer; + if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { + PsppMaxPortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init max port speed capability + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieAlibSetPortOverrideSpeedCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 *PsppOverridePortSpeedPackage; + PsppOverridePortSpeedPackage = (UINT8*) Buffer; + if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { + PsppOverridePortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = Engine->Type.Port.PortData.MiscControls.LinkSafeMode; + } + if (Engine->Type.Port.PortData.LinkHotplug == HotplugBasic && !PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { + PsppOverridePortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = PcieGen1; + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init port info + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieAlibSetPortInfoCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + ALIB_PORT_INFO_PACKAGE *PortInfoPackage; + UINT8 PortIndex; + PortInfoPackage = (ALIB_PORT_INFO_PACKAGE*) Buffer; + PortIndex = (UINT8) Engine->Type.Port.Address.Address.Device - 2; + PortInfoPackage->PortInfo[PortIndex].StartPhyLane = (UINT8) Engine->EngineData.StartLane; + PortInfoPackage->PortInfo[PortIndex].EndPhyLane = (UINT8) Engine->EngineData.EndLane; + PortInfoPackage->PortInfo[PortIndex].StartCoreLane = (UINT8) Engine->Type.Port.StartCoreLane; + PortInfoPackage->PortInfo[PortIndex].EndCoreLane = (UINT8) Engine->Type.Port.EndCoreLane; + PortInfoPackage->PortInfo[PortIndex].PortId = Engine->Type.Port.PortId; + PortInfoPackage->PortInfo[PortIndex].WrapperId = 0x0130 | (PcieConfigGetParentWrapper (Engine)->WrapId); + PortInfoPackage->PortInfo[PortIndex].LinkHotplug = Engine->Type.Port.PortData.LinkHotplug; + PortInfoPackage->PortInfo[PortIndex].MaxSpeedCap = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine); + PortInfoPackage->PortInfo[PortIndex].ClkPmSupport = Engine->Type.Port.PortData.MiscControls.ClkPmSupport; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init port info + * + * + * + * + * @param[in, out] Buffer Asl buffer + * @param[in] StdHeader Standard configuration header + * + */ + +VOID +STATIC +PcieAlibSetSclkVid ( + IN OUT VOID *Buffer, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 *SclkVid; + PP_FUSE_ARRAY *PpFuseArray; + UINT8 Index; + + SclkVid = (UINT8*) Buffer; + PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); + ASSERT (PpFuseArray != NULL); + if (PpFuseArray == NULL) { + IDS_HDT_CONSOLE (GNB_TRACE, " ERROR!!! Heap Location\n"); + return; + } + + for (Index = 0; Index < 4; Index++) { + SclkVid[Index * 2 + 1] = PpFuseArray->SclkVid[Index]; + } +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h new file mode 100644 index 0000000..63a06e1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h @@ -0,0 +1,109 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe ALIB + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _PCIEALIB_H_ +#define _PCIEALIB_H_ + +#pragma pack (push, 1) +///Port info asl buffer +typedef struct { + UINT8 BufferOp; ///< Opcode + UINT8 PkgLength; ///< Package length + UINT8 BufferSize; ///< Buffer size + UINT8 ByteList; ///< Byte lisy + UINT8 StartPhyLane; ///< Port Start PHY lane + UINT8 EndPhyLane; ///< Port End PHY lane + UINT8 StartCoreLane; ///< Port Start Core lane + UINT8 EndCoreLane; ///< Port End Core lane + UINT8 PortId; ///< Port ID + UINT16 WrapperId; ///< Wrapper ID + UINT8 LinkHotplug; ///< Link hotplug type + UINT8 MaxSpeedCap; ///< Max port speed capability + UINT8 ClkPmSupport; ///< ClkPmSupport +} ALIB_PORT_INFO_BUFFER; +///Ports info asl package +typedef struct { + UINT8 PackageOp; ///< Opcode + UINT8 PkgLength; ///< Package length + UINT8 NumElements; ///< number of elements + UINT8 PackageElementList; ///< package element list + ALIB_PORT_INFO_BUFFER PortInfo[7]; ///< Array of port info buffers +} ALIB_PORT_INFO_PACKAGE; + +#pragma pack (pop) + +AGESA_STATUS +PcieAlibFeature ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl new file mode 100644 index 0000000..5c53c6b --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl @@ -0,0 +1,136 @@ +/** + * @file + * + * ALIB PSPP config + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _PCIEALIBCONFIG_H_ +#define _PCIEALIBCONFIG_H_ + +//#define PCIE_PHY_LANE_POWER_GATE_SUPPORT +// #define PCIE_DISABLE_UNUSED_LANES_ON_ACTIVE_LINK + +#define DEF_OFFSET_START_CORE_LANE 2 +#define DEF_OFFSET_END_CORE_LANE 3 +#define DEF_OFFSET_START_PHY_LANE 0 +#define DEF_OFFSET_END_PHY_LANE 1 +#define DEF_OFFSET_PORT_ID 4 +#define DEF_OFFSET_WRAPPER_ID 5 +#define DEF_OFFSET_LINK_HOTPLUG 7 +#define DEF_OFFSET_GEN2_CAP 8 +#define DEF_OFFSET_CLK_PM_SUPPORT 9 + +#define DEF_BASIC_HOTPLUG 1 + +#define DEF_PSPP_POLICY_START 1 +#define DEF_PSPP_POLICY_STOP 0 +#define DEF_PSPP_POLICY_PERFORMANCE 1 +#define DEF_PSPP_POLICY_BALANCEHIGH 2 +#define DEF_PSPP_POLICY_BALANCELOW 3 +#define DEF_PSPP_POLICY_POWERSAVING 4 +#define DEF_PSPP_STATE_AC 0 +#define DEF_PSPP_STATE_DC 1 + +#define DEF_TRAINING_STATE_COMPLETE 0 +#define DEF_TRAINING_STATE_DETECT_PRESENCE 1 +#define DEF_TRAINING_STATE_PRESENCE_DETECTED 2 +#define DEF_TRAINING_GEN2_WORKAROUND 3 +#define DEF_TRAINING_STATE_NOT_PRESENT 4 +#define DEF_TRAINING_DEVICE_PRESENT 5 +#define DEF_TRAINING_STATE_RELEASE_TRAINING 6 +#define DEF_TRAINING_STATE_REQUEST_RESET 7 +#define DEF_TRAINING_STATE_EXIT 8 + +#define DEF_LINK_SPEED_GEN1 1 +#define DEF_LINK_SPEED_GEN2 2 + +#define DEF_HOTPLUG_STATUS_DEVICE_NOT_PRESENT 0 +#define DEF_HOTPLUG_STATUS_DEVICE_PRESENT 1 + +#define DEF_PORT_NOT_ALLOCATED 0 +#define DEF_PORT_ALLOCATED 1 + +#define DEF_PCIE_LANE_POWERON 1 +#define DEF_PCIE_LANE_POWEROFF 0 +#define DEF_PCIE_LANE_POWEROFFUNUSED 2 + +#define DEF_SCARTCH_PSPP_START_OFFSET 0 +#define DEF_SCARTCH_PSPP_POLICY_OFFSET 1 +#define DEF_SCARTCH_PSPP_ACDC_OFFSET 5 +#define DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET 6 +#define DEF_SCARTCH_PSPP_REQ_OFFSET 16 + +#define DEF_LINKWIDTH_ACTIVE 0 +#define DEF_LINKWIDTH_MAX_PHY 1 + +#define DEF_SB_PORT_INDEX 6 + +#define TRUE 1 +#define FALSE 0 + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl new file mode 100644 index 0000000..bc1f70d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl @@ -0,0 +1,111 @@ +/** + * @file + * + * ALIB ASL library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + + /*----------------------------------------------------------------------------------------*/ + /** + * Master control method + * + * Arg0 - Function ID + * Arg1 - Function specific data buffer + */ + Method (ALIB, 2, NotSerialized) { + If (Lequal (Arg0, 0x1)) { + return (procPsppReportAcDsState (Arg1)) + } + If (LEqual (Arg0, 0x2)) { + return (procPsppPerformanceRequest (Arg1)) + } + If (LEqual (Arg0, 0x3)) { + return (procPsppControl (Arg1)) + } + If (LEqual (Arg0, 0x4)) { + return (procPcieSetBusWidth (Arg1)) + } + If (LEqual (Arg0, 0x5)) { + return (procAlibInit ()) + } + If (LEqual (Arg0, 0x6)) { + return (procPciePortHotplug (Arg1)) + } + return (0) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Alib Init + * + * + */ + Method (procAlibInit, 0, Serialized) { + + return (0) + } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibDebugLib.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibDebugLib.esl new file mode 100644 index 0000000..e8820cf --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibDebugLib.esl @@ -0,0 +1,73 @@ +/** + * @file + * + * ALIB ASL library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 44324 $ @e $Date: 2010-12-22 01:16:51 -0800 (Wed, 22 Dec 2010) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + Name (varStringBuffer, Buffer (256) {}) + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl new file mode 100644 index 0000000..951193a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl @@ -0,0 +1,787 @@ +/** + * @file + * + * ALIB ASL library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 65976 $ @e $Date: 2012-02-27 22:24:12 -0600 (Mon, 27 Feb 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + External(_SB.ALIC, MethodObj) + External(P80H) + + Name (varStartPhyLane, 0) + Name (varEndPhyLane, 0) + Name (varStartCoreLane, 0) + Name (varEndCoreLane, 0) + Name (varWrapperId, 0) + Name (varPortId, 0) + Name (varMaxPhyLinkWidth, 0) + + Name (varNormalizeLinkWidthBuffer, Buffer () {1, 2, 4, 4, 8, 8, 8, 8, 16, 16, 16, 16, 16, 16, 16, 16}) + /*----------------------------------------------------------------------------------------*/ + /** + * Set PCIe Bus Width + * + * Arg0 - Data Buffer + */ + Method (procPcieSetBusWidth, 1, NotSerialized) { + Store ("procPcieSetBusWidth Enter", Debug) + + Name (varClientBus, 0) + Name (varArgBusWidth, 0) + Store (0, varPortIndex) + Store (Buffer (10) {}, Local7) + + //ClientId: WORD + //Bits 2-0: Function number. + //Bits 7-3: Device number. + //Bits 15-8: Bus number. + Store (DerefOf (Index (Arg0, 0x3)), varClientBus) + Store (DerefOf (Index (Arg0, 0x4)), varArgBusWidth) + Store (Concatenate (" Client Bus : ", ToHexString (varClientBus), varStringBuffer), Debug) + Store (Concatenate (" Arg Bus Width : ", ToHexString (varArgBusWidth), varStringBuffer), Debug) + + Store (3, Index (Local7, 0x0)) // Return Buffer Length + Store (0, Index (Local7, 0x1)) // Return Buffer Length + Store (varArgBusWidth, Index (Local7, 0x2)) // Return BusWidth + // disable interface + return (Local7) + + //deternime correct lane bitmap (check for reversal) gate/ungate unused lanes + + // determine port index base on "Client ID" + while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { + if (LEqual (procChecPortAllocated (varPortIndex), DEF_PORT_ALLOCATED)) { + Store (procPciDwordRead (ShiftLeft (Add( varPortIndex, 2), 3), 0x18), Local1) + And (ShiftRight (Local1, 16), 0xff, varSubordinateBusLocal2) //Local2 Port Subordinate Bus number + And (ShiftRight (Local1, 8), 0xff, varSecondaryBusLocal1) //Local1 Port Secondary Bus number + if (LAnd (LGreaterEqual (varClientBus, Local1), LLessEqual(varClientBus, Local2))) { + break + } + } + Increment (varPortIndex) + } + if (LGreater (varPortIndex, varMaxPortIndexNumber)) { + Store ("procPcieSetBusWidth Exit -- over max port index", Debug) + return (Local7) + } + + Store (Concatenate (" Pcie Set BusWidth for port index : ", ToHexString (varPortIndex), varStringBuffer), Debug) + + // Normalize link width (Num Lanes) to correct value x1, x2.x4,x8,x16, + // make sure that number of lanes requested to be powered on less or equal mx port link width + if (LLessEqual (procPcieGetLinkWidth (varPortIndex, DEF_LINKWIDTH_MAX_PHY), varArgBusWidth)) { + // Active link equal max link width, nothing needs to be done + Store ("procPcieSetBusWidth Exit -- over max lanes supported", Debug) + return (Local7) + } + Store (DeRefOf (Index (varNormalizeLinkWidthBuffer, varArgBusWidth)), Local1) + + + // call procPcieLaneControl to power on all lanes (Arg0 - port index , Arg1 - 1, Arg2 = 0) + procPcieLaneControl (varPortIndex, DEF_PCIE_LANE_POWERON, 0) + + // call procPcieLaneControl power off unused lanes (Arg0 - port index, Arg1 - 1, Arg2 = Link width) + procPcieLaneControl (varPortIndex, DEF_PCIE_LANE_POWEROFFUNUSED, Local1) + +#ifdef PHY_SPEED_REPORT_SUPPORT + procReportPhySpeedCap () +#endif + Store (Local1, Index (Local7, 0x2)) // Return BusWidth + + Store ("procPcieSetBusWidth Exit", Debug) + return (Local7) + } + + + /*----------------------------------------------------------------------------------------*/ + /** + * PCIe port hotplug + * + * Arg0 - Data Buffer + * Retval - Return buffer + */ + Method (procPciePortHotplug, 1, Serialized) { + Store ("PciePortHotplug Enter", Debug) + Store (DerefOf (Index (Arg0, 4)), varHotplugStateLocal0) + Store (DerefOf (Index (Arg0, 2)), varPortBdfLocal1) + + Subtract (ShiftRight (varPortBdfLocal1, 3), 2, varPortIndexLocal4) + if (LEqual(varHotplugStateLocal0, 1)) { + // Enable port + Store (DEF_TRAINING_STATE_RELEASE_TRAINING, Local2) + } else { + // Disable port + Store (DEF_TRAINING_STATE_NOT_PRESENT, Local2) + } + + //Disable ASPM + Store (procPciDwordRead (varPortBdfLocal1, 0x68), Local3) + procPciDwordRMW (varPortBdfLocal1, 0x68, Not (0x00000003), 0x00) + + Store (procPciePortTraining (varPortIndexLocal4, Local2), varHotplugStateLocal0) + + //Restore ASPM + procPciDwordRMW (varPortBdfLocal1, 0x68, Not (0x00000003), And (Local3, 0x3)) + +#ifdef PHY_SPEED_REPORT_SUPPORT + procReportPhySpeedCap () +#endif + + Store (Buffer (10) {}, Local7) + CreateWordField (Local7, 0x0, varReturnBufferLength) + CreateByteField (Local7, 0x2, varReturnStatus) + CreateByteField (Local7, 0x3, varReturnDeviceStatus) + Store (0x4, varReturnBufferLength) + Store (0x0, varReturnStatus) + Store (varHotplugStateLocal0, varReturnDeviceStatus) + Store ("PciePortHotplug Exit", Debug) + return (Local7) + } + + Name (varSpeedRequest, Buffer (10) {0,0,0,0,0,0,0,0,0,0}) + + /*----------------------------------------------------------------------------------------*/ + /** + * Train PCIe port + * + * + * Arg0 - Port Index + * Arg1 - Initial state + */ + Method (procPciePortTraining, 2, Serialized) { + Store ("PciePortTraining Enter", Debug) + Store (DEF_HOTPLUG_STATUS_DEVICE_NOT_PRESENT, varResultLocal4) + Store (procPcieGetPortInfo (Arg0), Local7) + // Check if port supports basic hotplug + Store (DerefOf (Index (Local7, DEF_OFFSET_LINK_HOTPLUG)), varTempLocal1) + if (LNotEqual (varTempLocal1, DEF_BASIC_HOTPLUG)) { + Store (" No action.[Hotplug type]", Debug) + Store ("procPciePortTraining Exit", Debug) + return (varResultLocal4) + } + Store (Arg1, varStateLocal2) + while (LNotEqual (varStateLocal2, DEF_TRAINING_STATE_EXIT)) { + if (LEqual (varStateLocal2, DEF_TRAINING_STATE_RELEASE_TRAINING)) { + Store (" State: Release training", Debug) + // Remove link speed override + Store (0, Index (varOverrideLinkSpeed, Arg0)) + // Enable link width upconfigure + procPciePortIndirectRegisterRMW (Arg0, 0xA2, Not (0x2000), 0x0000) + if (LAnd (LGreater (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LLess (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) { + // Request Max link speed for hotplug by going to AC state + Store (0, varPsppAcDcOverride) + procApplyPsppState () + } else { + procPcieSetLinkSpeed (Arg0, DeRefOf (Index (varMaxLinkSpeed, Arg0))) + } + // Power on/enable port lanes + procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWERON, 0) + // Release training + procPcieTrainingControl (Arg0, 0) + // Move to next state to check presence detection + Store (DEF_TRAINING_STATE_DETECT_PRESENCE, varStateLocal2) + // Initialize retry count + Store(0, varCountLocal3) + } + if (LEqual (varStateLocal2, DEF_TRAINING_STATE_DETECT_PRESENCE)) { + Store (" State: Detect presence", Debug) + And (procPciePortIndirectRegisterRead (Arg0, 0xa5), 0x3f, varTempLocal1) + if (LGreater (varTempLocal1, 0x4)) { + // device connection detected move to next state + Store (DEF_TRAINING_STATE_PRESENCE_DETECTED, varStateLocal2) + // reset retry counter + Store(0, varCountLocal3) + continue + } + if (LLess (varCountLocal3, 80)) { + Sleep (1) + Increment (varCountLocal3) + } else { + // detection time expired move to device not present state + Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2) + } + } + if (LEqual (varStateLocal2, DEF_TRAINING_STATE_PRESENCE_DETECTED)) { + Store (" State: Device detected", Debug) + Store (procPciePortIndirectRegisterRead (Arg0, 0xa5), varTempLocal1) + And (varTempLocal1, 0x3f, varTempLocal1) + if (LAnd (LGreaterEqual (varTempLocal1, 0x10), LLessEqual (varTempLocal1, 0x13))) { + Store (DEF_TRAINING_DEVICE_PRESENT, varStateLocal2) + continue + } + if (LLess (varCountLocal3, 80)) { + Sleep (1) + Increment (varCountLocal3) + continue + } + Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2) + if (LEqual (DeRefOf (Index (varOverrideLinkSpeed, Arg0)), DEF_LINK_SPEED_GEN1)) { + // GEN2 workaround already applied but device not trained successfully move device not present state + continue + } + + if (LEqual (procPcieCheckForGen2Workaround (Arg0), TRUE)) { + Store (" Request Gen2 workaround", Debug) + procPciePortIndirectRegisterRMW (Arg0, 0xA2, Not (0x2000), 0x2000) + Store (DEF_LINK_SPEED_GEN1, Index (varOverrideLinkSpeed, Arg0)) + procPcieSetLinkSpeed (Arg0, DEF_LINK_SPEED_GEN1) + Store (DEF_TRAINING_STATE_REQUEST_RESET, varStateLocal2) + } + } + if (LEqual (varStateLocal2, DEF_TRAINING_STATE_NOT_PRESENT)) { + Store (" State: Device not present", Debug) + procPcieTrainingControl (Arg0, 1) + procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWEROFF, 0) +#ifdef PCIE_MAX_PAYLOAD_SUPPORT + procPcieClearMaxPayload (Arg0) +#endif + + // Find device on secondary bus + Store (ShiftLeft (Add( Arg0, 2), 3), varTempBdfLocal0) + Store (procPciDwordRead (varTempBdfLocal0, 0x18), varTempLocal1) + And (ShiftRight (varTempLocal1, 8), 0xFF, varTempLocal1) + Store (Concatenate (" Remove device from Bus : ", ToHexString (varTempLocal1), varStringBuffer), Debug) + ShiftLeft (varTempLocal1, 8, varTempBdfLocal0) + Store (procPciDwordRead (varTempBdfLocal0, 0x0), varTempLocal0) + if (LEqual (varTempLocal0, 0xFFFFFFFF)) { + Store (" Device has been un-pluged!! ", Debug) + } + // Exclude device from PSPP managment since it is not present + Store (DEF_LINK_SPEED_GEN1, Index (varOverrideLinkSpeed, Arg0)) + Store (DEF_TRAINING_STATE_COMPLETE, varStateLocal2) + } + if (LEqual (varStateLocal2, DEF_TRAINING_STATE_REQUEST_RESET)) { + Store (" State: Request Reset", Debug) + if (CondRefOf (_SB.ALIC, Local6)) { + Store (" Call ALIC method", Debug) + //varTempLocal1 contain port BDF + Store(ShiftLeft (Add (Arg0, 2), 3), varTempLocal1) + _SB.ALIC (varTempLocal1, 0) + Sleep (2) + _SB.ALIC (varTempLocal1, 1) + Store (0, varCountLocal3) + Store (DEF_TRAINING_STATE_DETECT_PRESENCE, varStateLocal2) + continue + } + Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2) + } + if (LEqual (varStateLocal2, DEF_TRAINING_DEVICE_PRESENT)) { + Store (" State: Device present", Debug) + Store (DEF_HOTPLUG_STATUS_DEVICE_PRESENT, varResultLocal4) + Store (DEF_TRAINING_STATE_COMPLETE, varStateLocal2) +#ifdef PCIE_DISABLE_UNUSED_LANES_ON_ACTIVE_LINK + procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWEROFFUNUSED, 0) +#endif +#ifdef PCIE_MAX_PAYLOAD_SUPPORT + procPcieSetMaxPayload (Arg0) +#endif +#ifdef PCIE_CLKPM_SUPPORT + procPcieClkPmConfigure (Arg0) +#endif + } + if (LEqual (varStateLocal2, DEF_TRAINING_STATE_COMPLETE)) { + if (LAnd (LGreater (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LLess (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) { + Store (1, varPsppAcDcOverride) + procApplyPsppState () + } + Store (DEF_TRAINING_STATE_EXIT, varStateLocal2) + } + } + Store ("PciePortTraining Exit", Debug) + return (varResultLocal4) + } + + + /*----------------------------------------------------------------------------------------*/ + /** + * Lane control + * + * Arg0 - Port Index + * Arg1 - 0 - Power off all lanes / 1 - Power on all Lanes / 2 Power off unused lanes + * Arg2 - link width + */ + + Method (procPcieLaneControl, 3, Serialized) { + Store ("PcieLaneControl Enter", Debug) + Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug) + Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug) + Store (procPcieGetPortInfo (Arg0), Local7) +#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT + Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane) + Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane) +#endif + Store (DerefOf (Index (Local7, DEF_OFFSET_START_CORE_LANE)), varStartCoreLane) + Store (DerefOf (Index (Local7, DEF_OFFSET_END_CORE_LANE)), varEndCoreLane) + + Store (procPcieGetLinkWidth (Arg0, DEF_LINKWIDTH_MAX_PHY), varMaxPhyLinkWidth) + + if (LEqual (Arg1, DEF_PCIE_LANE_POWEROFF)) { + procPcieLaneEnableControl (Arg0, varStartCoreLane, Add (varStartCoreLane, Subtract(varMaxPhyLinkWidth, 1)), 1) +#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT + procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 1) +#endif + } + if (LEqual (Arg1, DEF_PCIE_LANE_POWERON)) { +#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT + procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 0) +#endif + procPcieLaneEnableControl (Arg0, varStartCoreLane, Add (varStartCoreLane, Subtract(varMaxPhyLinkWidth, 1)), 0) + } + if (LNotEqual (Arg1, DEF_PCIE_LANE_POWEROFFUNUSED)) { + return (0) + } + + // Local2 should have link width (active lanes) + // Local3 should have first non active lanes + // Local4 should have last non active lanes + + if (LEqual(Arg2, 0)) { + Store (procPcieGetLinkWidth (Arg0, DEF_LINKWIDTH_ACTIVE), varActiveLinkWidthLocal2) + } else { + Store ( Arg2 , varActiveLinkWidthLocal2) + } + // Let say Link width is x1 than local2 = 1, Local3 = 1 Local4 = 15 for non reversed case + // while for reversed case should be Local2 = 1 Local3 = 0 and Local4 = 14 + + if (LLessEqual (varMaxPhyLinkWidth, varActiveLinkWidthLocal2)) { + // Active link equal max link width, nothing needs to be done + return (0) + } + + Store (procPcieIsPortReversed (Arg0), varIsReversedLocal1) + //There is unused lanes after device plugged + if (LEqual(varIsReversedLocal1, FALSE)) { + Store (" Port Not Reversed", Debug) + // Link not reversed + Add (varStartCoreLane, varActiveLinkWidthLocal2, Local3) + Store (varEndCoreLane, Local4) + } else { + // Link reversed + Store (" Port Reversed", Debug) + Subtract (varEndCoreLane, varActiveLinkWidthLocal2, Local4) + Store (varStartCoreLane, Local3) + } + procPcieLaneEnableControl (Arg0, Local3, Local4, 1) +#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT + if (LGreater (varStartPhyLane, varEndPhyLane)) { + Store (varEndPhyLane, Local3) + Store (varStartPhyLane, Local4) + } else { + Store (varEndPhyLane, Local4) + Store (varStartPhyLane, Local3) + } + if (LEqual(varIsReversedLocal1, FALSE)) { + // Not reversed + Add (Local3, varActiveLinkWidthLocal2, Local3) + } else { + // Link reversed + Subtract (Local4, varActiveLinkWidthLocal2, Local4) + } + procPcieLanePowerControl (Local3, Local4, 1) +#endif + return (0) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Check if GEN2 workaround applicable + * + * Arg0 - Port Index + * Retval - TRUE / FALSE + */ + + Method (procPcieCheckForGen2Workaround, 1, NotSerialized) { + Store (Buffer (16) {}, Local1) + Store (0x0, Local0) + while (LLessEqual (Local0, 0x3)) { + Store (procPciePortIndirectRegisterRead (Arg0, Add (Local0, 0xA5)), Local2) + Store (Local2, Index (Local1, Multiply (Local0, 4))) + Store (ShiftRight (Local2, 8), Index (Local1, Add (Multiply (Local0, 4), 1))) + Store (ShiftRight (Local2, 16), Index (Local1, Add (Multiply (Local0, 4), 2))) + Store (ShiftRight (Local2, 24), Index (Local1, Add (Multiply (Local0, 4), 3))) + Increment (Local0) + } + Store (0, Local0) + while (LLess (Local0, 15)) { + if (LAnd (LEqual (DeRefOf (Index (Local1, Local0)), 0x2a), LEqual (DeRefOf (Index (Local1, Add (Local0, 1))), 0x9))) { + return (TRUE) + } + Increment (Local0) + } + return (FALSE) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Is port reversed + * + * Arg0 - Port Index + * Retval - 0 - Not reversed / !=0 - Reversed + */ + Method (procPcieIsPortReversed , 1, Serialized) { + Store (procPcieGetPortInfo (Arg0), Local7) + + Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane) + Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane) + Store (0, Local0) + if (LGreater (varStartPhyLane, varEndPhyLane)) { + Store (1, Local0) + } + And (procPciePortIndirectRegisterRead (Arg0, 0x50), 0x1, Local1) + return (And (Xor (Local0, Local1), 0x1)) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Training Control + * + * Arg0 - Port Index + * Arg1 - Hold Training (1) / Release Training (0) + */ + Method (procPcieTrainingControl , 2, NotSerialized) { + Store ("PcieTrainingControl Enter", Debug) + Store (procPcieGetPortInfo (Arg0), Local7) + Store (DerefOf (Index (Local7, DEF_OFFSET_PORT_ID)), varPortId) + Store ( + Or (ShiftLeft (DerefOf (Index (Local7, Add (DEF_OFFSET_WRAPPER_ID, 1))), 8), DerefOf (Index (Local7, DEF_OFFSET_WRAPPER_ID))), + varWrapperId + ) + procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), Add (0x800, Multiply (0x100, varPortId))), Not (0x1), Arg1); + Store ("PcieTrainingControl Exit", Debug) + } + + +Name (varLinkWidthBuffer, Buffer () {0, 1, 2, 4, 8, 12, 16}) + /*----------------------------------------------------------------------------------------*/ + /** + * Get actual negotiated/PHY or core link width + * + * Arg0 - Port Index + * Arg1 - 0/1 Negotiated/Phy + * Retval - Link Width + */ + Method (procPcieGetLinkWidth, 2, NotSerialized) { + Store ("PcieGetLinkWidth Enter", Debug) + Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug) + Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug) + + if (LEqual (Arg1, DEF_LINKWIDTH_ACTIVE)){ + //Get negotiated length + And (ShiftRight (procPciePortIndirectRegisterRead (Arg0, 0xA2), 4), 0x7, Local0) + Store (DeRefOf (Index (varLinkWidthBuffer, Local0)), Local1) + Store (Concatenate (" Active Link Width :", ToHexString (Local1), varStringBuffer), Debug) + } else { + //Get phy length + Store (procPcieGetPortInfo (Arg0), Local7) + Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane) + Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane) + if (LGreater (varStartPhyLane, varEndPhyLane)) { + Subtract (varStartPhyLane, varEndPhyLane, Local1) + } else { + Subtract (varEndPhyLane, varStartPhyLane, Local1) + } + Increment (Local1) + Store (Concatenate (" PHY Link Width :", ToHexString (Local1), varStringBuffer), Debug) + } + Store ("PcieGetLinkWidth Exit", Debug) + return (Local1) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * PCIe lane mux lane enable control (hotplug support) + * + * Arg0 - Port Index + * Arg1 - Start Lane + * Arg2 - End Lane + * Arg3 - Enable(0) / Disable(1) + */ + Method (procPcieLaneEnableControl, 4, Serialized) { + Store ("PcieLaneEnableControl Enter", Debug) + Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug) + Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug) + Store (Concatenate (" Arg2 : ", ToHexString (Arg2), varStringBuffer), Debug) + Store (Concatenate (" Arg3 : ", ToHexString (Arg3), varStringBuffer), Debug) + Store (procPcieGetPortInfo (Arg0), Local7) + Store (Arg1, varStartCoreLane) + Store (Arg2, varEndCoreLane) + Store ( + Or (ShiftLeft (DerefOf (Index (Local7, Add (DEF_OFFSET_WRAPPER_ID, 1))), 8), DerefOf (Index (Local7, DEF_OFFSET_WRAPPER_ID))), + varWrapperId + ) + if (LGreater (varStartCoreLane, varEndCoreLane)) { + Subtract (varStartCoreLane, varEndCoreLane, Local1) + Store (varEndCoreLane, Local2) + } else { + Subtract (varEndCoreLane, varStartCoreLane, Local1) + Store (varStartCoreLane, Local2) + } + ShiftLeft (Subtract (ShiftLeft (1, Add (Local1, 1)), 1), Local2, varLaneBitmapOrMaskLocal3) + Store (Not (varLaneBitmapOrMaskLocal3), varLaneBitmapAndMaskLocal4) + Store (Concatenate (" Lane Bitmap : ", ToHexString (varLaneBitmapOrMaskLocal3), varStringBuffer), Debug) + if (Lequal (Arg3, 1)) { + Store (0, varLaneBitmapOrMaskLocal3) + } + procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), 0x8023), varLaneBitmapAndMaskLocal4, varLaneBitmapOrMaskLocal3); + Stall (10) + Store ("PcieLaneEnableControl Exit", Debug) + } + +#ifdef PCIE_MAX_PAYLOAD_SUPPORT + + /*----------------------------------------------------------------------------------------*/ + /** + * Max_Payload_Size Blacklist + * + * Entry 1 = Vendor & Device ID + * Entry 2 = Max_Payload_Size for this device + */ + Name (varPayloadBlacklist, Package () { + Package() {0x10831969, 0} + }) + + /*----------------------------------------------------------------------------------------*/ + /** + * Set Max_Payload_Size + * + * Arg0 - Port Index + */ + Method (procPcieSetMaxPayload, 1, Serialized) { + + // Local variable usage + // varTempLocal0 - Temporary storage + // varBdfLocal1 - Address of port config space + // varCapLocal2 - Offset of port PCIe Capabilities + // varMaxPayloadLocal3 - Largest common value of Max_Payload_Size capability + // varMaxFunctionLocal4 - Max function number + // varFunctionLocal5 - Current function number + // varDeviceIDLocal6 - Root port BDF and Vendor and device ID for blacklist workaround + // varIndexLocal7 - Package index for blacklist workaround + + Store ("PcieSetMaxPayload Enter", Debug) + + // Get Port BDF from Port Index + Store (ShiftLeft (Add( Arg0, 2), 3), varDeviceIDLocal6) + Store (procFindPciCapability (varDeviceIDLocal6, 0x10), varCapLocal2) + if (LNotEqual (varCapLocal2, 0)) { + + // Find device on secondary bus + Store (procPciDwordRead (varDeviceIDLocal6, 0x18), varTempLocal0) + And (ShiftRight (varTempLocal0, 8), 0xFF, varTempLocal0) + + Store (Concatenate (" EP on SecondaryBus : ", ToHexString (varTempLocal0), varStringBuffer), Debug) + + ShiftLeft (varTempLocal0, 8, varBdfLocal1) + + Store (procPciDwordRead (varBdfLocal1, 0xC), varTempLocal0) + Store (And (ShiftRight (varTempLocal0, 16), 0xFF), varTempLocal0) + if (LNotEqual (And (varTempLocal0, 0x80), 0)) { + Store (0x7, varMaxFunctionLocal4) + } else { + Store (0x0, varMaxFunctionLocal4) + } + // Start with illegal value so we will know if a device is foudn + Store (0x08, varMaxPayloadLocal3) + // Search all functions and find smallest Max_Payload_Size + Store (0x0, varFunctionLocal5) + while (LLessEqual (varFunctionLocal5, varMaxFunctionLocal4)) { + Store (procFindPciCapability (Add (varBdfLocal1, varFunctionLocal5), 0x10), varCapLocal2) + if (LNotEqual (varCapLocal2, 0)) { + And (procPciDwordRead (Add (varBdfLocal1, varFunctionLocal5), Add (varCapLocal2, 0x04)), 0x07, varTempLocal0) + // Scan blacklist package for workaround + Store(procPciDwordRead (Add (varBdfLocal1, varFunctionLocal5), 0), varDeviceIDLocal6) + Store (0, varIndexLocal7) + while (LLess (varIndexLocal7, SizeOf (varPayloadBlacklist))) { + if (LEqual (DeRefOf (Index (DeRefOf (Index (varPayloadBlacklist, varIndexLocal7)), 0)), varDeviceIDLocal6)) { + Store (DeRefOf (Index (DeRefOf (Index (varPayloadBlacklist, varIndexLocal7)), 1)), varTempLocal0) + } + Increment (varIndexLocal7) + } + if (LLess (varTempLocal0, varMaxPayloadLocal3)) { + Store (varTempLocal0, varMaxPayloadLocal3) + } + } + Increment(varFunctionLocal5) + } + + // We will only set Max_Payload_Size if PCIe capabilties were found on the downstream side + if (LNotEqual (varMaxPayloadLocal3, 0x08)) { + // Read root port Max_Payload_Size and compare with device supported value + Store (ShiftLeft (Add( Arg0, 2), 3), varDeviceIDLocal6) + Store (procFindPciCapability (varDeviceIDLocal6, 0x10), varCapLocal2) + And (procPciDwordRead (varDeviceIDLocal6, Add (varCapLocal2, 0x04)), 0x07, varTempLocal0) + if (LLess (varTempLocal0, varMaxPayloadLocal3)) { + Store (varTempLocal0, varMaxPayloadLocal3) + } + // Search all functions and set smallest Max_Payload_Size to all functions + // Relocate Max_Payload_Size data to bits 7-5 + Store (Concatenate (" Setting Max_Payload_Size : ", ToHexString (varMaxPayloadLocal3), varStringBuffer), Debug) + ShiftLeft (varMaxPayloadLocal3, 5, varMaxPayloadLocal3) + // Set the root port Max_Payload_Size + procPciDwordRMW (varDeviceIDLocal6, Add (varCapLocal2, 0x08), Not (0x000000E0), varMaxPayloadLocal3) + //Set the Max_Payload_Size in each function that has PCIe Capabilities + Store (0x0, varFunctionLocal5) + while (LLessEqual (varFunctionLocal5, varMaxFunctionLocal4)) { + Store (procFindPciCapability (Add (varBdfLocal1, varFunctionLocal5), 0x10), varCapLocal2) + if (LNotEqual (varCapLocal2, 0)) { + procPciDwordRMW (varBdfLocal1, Add (varCapLocal2, 0x08), Not (0x000000E0), varMaxPayloadLocal3) + } + Increment(varFunctionLocal5) + } + } + } + Store ("PcieSetMaxPayload Exit", Debug) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Clear Max_Payload_Size + * + * Arg0 - Port Index + */ + Method (procPcieClearMaxPayload, 1, Serialized) { + + // Local variable usage + // varPortBdfLocal0 - Address of root port config space + // varPortCapLocal1 - Offset of root port PCIe Capabilities + + Store ("PcieClearMaxPayload Enter", Debug) + + // Get Port BDF from Port Index + Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal0) + Store (procFindPciCapability (varPortBdfLocal0, 0x10), varPortCapLocal1) + if (LNotEqual (varPortCapLocal1, 0)) { + // Set the root port Max_Payload_Size to default = 0x0 + procPciDwordRMW (varPortBdfLocal0, Add (varPortCapLocal1, 0x08), Not (0x000000E0), 0x0) + + } + Store ("PcieClearMaxPayload Exit", Debug) + } +#endif + +#ifdef PCIE_CLKPM_SUPPORT + Method (procPcieClkPmConfigure, 1, Serialized) { + Store ("PcieClkPmConfigure Enter", Debug) + Store (procPcieGetPortInfo (Arg0), Local7) + Store (DerefOf (Index (Local7, DEF_OFFSET_CLK_PM_SUPPORT)), varTempLocal0) + if (LEqual (varTempLocal0, 0)) { + Store ("PcieClkPmConfigure Exit", Debug) + return (0) + } + // Get Port PCI address + Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1) + Store (procPciDwordRead (varPortBdfLocal1, 0x18), varTempLocal0) + // Get device BDf on secondary bus + And (varTempLocal0, 0xFF00, varEndpointBdfLocal2) + + Store (procPciDwordRead (varEndpointBdfLocal2, 0xC), varTempLocal0) + Store (And (ShiftRight (varTempLocal0, 16), 0xFF), varTempLocal0) + if (LNotEqual (And (varTempLocal0, 0x80), 0)) { + Store (0x7, varMaxFunctionLocal3) + } else { + Store (0x0, varMaxFunctionLocal3) + } + Store (0, varFunctionLocal4) + Store (0, varIsClkPmSupportedLocal5) + while (LLessEqual (varFunctionLocal4, varMaxFunctionLocal3)) { + //Find PcieLinkControl register offset = PcieCapPtr + 0x10 + Store (procFindPciCapability (Or (varEndpointBdfLocal2, varFunctionLocal4), 0x10), varPcieCapabilityOffsetLocal6) + if (LEqual (varPcieCapabilityOffsetLocal6, 0)) { + Increment (varFunctionLocal4) + continue + } + // Found PCI capability + if (LNotEqual (And (procPciDwordRead (Or (varEndpointBdfLocal2, varFunctionLocal4), Add (varPcieCapabilityOffsetLocal6, 0xC)), ShiftLeft (1,18)), 0)) { + Store (1, varIsClkPmSupportedLocal5) + } else { + Store (0, varIsClkPmSupportedLocal5) + break + } + Increment (varFunctionLocal4) + } + if (LEqual (varIsClkPmSupportedLocal5, 0)) { + Store ("PcieClkPmConfigure Exit", Debug) + return (0) + } + Store (0, varFunctionLocal4) + + while (LLessEqual (varFunctionLocal4, varMaxFunctionLocal3)) { + //Find PcieLinkControl register offset = PcieCapPtr + 0x10 + Store (procFindPciCapability (Or (varEndpointBdfLocal2, varFunctionLocal4), 0x10), varPcieCapabilityOffsetLocal6) + if (LEqual (varPcieCapabilityOffsetLocal6, 0)) { + Increment (varFunctionLocal4) + continue + } + // Enable CLK PM Capability + procPciDwordRMW (Or (varEndpointBdfLocal2, varFunctionLocal4), Add (varPcieCapabilityOffsetLocal6, 0x10), 0xffffffff, ShiftLeft (1, 8)) + Increment (varFunctionLocal4) + } + Store ("PcieClkPmConfigure Exit", Debug) + } +#endif + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibMmioData.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibMmioData.esl new file mode 100644 index 0000000..abe0cdd --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibMmioData.esl @@ -0,0 +1,88 @@ +/** + * @file + * + * ALIB ASL library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 44324 $ @e $Date: 2010-12-22 01:16:51 -0800 (Wed, 22 Dec 2010) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. 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If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + + /*----------------------------------------------------------------------------------------*/ + /** + * PCIe MMIO Base address + * + */ + + Name ( + AD01, + 0xE0000000 + ) + + Alias ( + AD01, + varPcieBase + ) + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl new file mode 100644 index 0000000..378c039 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl @@ -0,0 +1,289 @@ +/** + * @file + * + * ALIB ASL library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 44324 $ @e $Date: 2010-12-22 01:16:51 -0800 (Wed, 22 Dec 2010) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + + /*----------------------------------------------------------------------------------------*/ + /** + * Read PCI config register through MMIO + * + * Arg0 - PCI address Bus/device/func + * Arg1 - Register offset + */ + Method (procPciDwordRead, 2, Serialized) { + Add (varPcieBase, ShiftLeft (Arg0, 12), Local0) + Add (Arg1, Local0, Local0) + OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) + Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) { + Offset (0x0), + varPciReg32, 32, + } + return (varPciReg32) + } + /*----------------------------------------------------------------------------------------*/ + /** + * Write PCI config register through MMIO + * + * Arg0 - PCI address Bus/device/func + * Arg1 - Register offset + * Arg2 - Value + */ + Method (procPciDwordWrite, 3, Serialized) { + Add (varPcieBase, ShiftLeft (Arg0, 12), Local0) + Add (Arg1, Local0, Local0) + OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) + Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) { + Offset (0x0), + varPciReg32, 32, + } + Store (Arg2, varPciReg32) + } + /*----------------------------------------------------------------------------------------*/ + /** + * Write PCI config register through MMIO + * + * Arg0 - PCI address Bus/device/func + * Arg1 - Register offset + * Arg2 - AND mask + * Arg3 - OR mask + */ + Method (procPciDwordRMW, 4, Serialized) { + Store (procPciDwordRead (Arg0, Arg1), Local0) + Or (And (Local0, Arg2), Arg3, Local0) + procPciDwordWrite (Arg0, Arg1, Local0) + } + + Mutex(varPciePortAccessMutex, 0) + /*----------------------------------------------------------------------------------------*/ + /** + * Read PCIe port indirect register + * + * Arg0 - Port Index + * Arg1 - Register offset + * + */ + Method (procPciePortIndirectRegisterRead, 2, NotSerialized) { + Acquire(varPciePortAccessMutex, 0xFFFF) + Store (ShiftLeft (Add( Arg0, 2), 3), Local0) + procPciDwordWrite (Local0, 0xe0, Arg1) + Store (procPciDwordRead (Local0, 0xe4), Local0) + Release (varPciePortAccessMutex) + return (Local0) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Write PCIe port indirect register + * + * Arg0 - Port Index + * Arg1 - Register offset + * Arg2 - Value + */ + Method (procPciePortIndirectRegisterWrite, 3, NotSerialized) { + Acquire(varPciePortAccessMutex, 0xFFFF) + Store (ShiftLeft (Add( Arg0, 2), 3), Local0) + procPciDwordWrite (Local0, 0xe0, Arg1) + procPciDwordWrite (Local0, 0xe4, Arg2) + Release (varPciePortAccessMutex) + } + /*----------------------------------------------------------------------------------------*/ + /** + * Read PCIe port indirect register + * + * Arg0 - Port Index + * Arg1 - Register offset + * Arg2 - AND Mask + * Arg3 - OR Mask + * + */ + Method (procPciePortIndirectRegisterRMW, 4, NotSerialized) { + Store (procPciePortIndirectRegisterRead (Arg0, Arg1), Local0) + Or (And (Local0, Arg2), Arg3, Local0) + procPciePortIndirectRegisterWrite (Arg0, Arg1, Local0) + } + Mutex(varHostAccessMutex, 0) + /*----------------------------------------------------------------------------------------*/ + /** + * Read PCIe port indirect register + * + * Arg0 - BDF + * Arg1 - Register offset + * Arg2 - Register address + * + */ + Method (procIndirectRegisterRead, 3, NotSerialized) { + Acquire(varHostAccessMutex, 0xFFFF) + procPciDwordWrite (Arg0, Arg1, Arg2) + Store (procPciDwordRead (Arg0, Add (Arg1, 4)), Local0) + Release(varHostAccessMutex) + return (Local0) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Write PCIe port indirect register + * + * Arg0 - BDF + * Arg1 - Register offset + * Arg2 - Register address + * Arg3 - Value + */ + Method (procIndirectRegisterWrite, 4, NotSerialized) { + Acquire(varHostAccessMutex, 0xFFFF) + procPciDwordWrite (Arg0, Arg1, Arg2) + procPciDwordWrite (Arg0, Add (Arg1, 4), Arg3) + Release(varHostAccessMutex) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Read Modify Write indirect registers + * + * Arg0 - BDF + * Arg1 - Register Offset + * Arg2 - Register Address + * Arg3 - AND Mask + * Arg4 - OR Mask + * + */ + Method (procIndirectRegisterRMW, 5, NotSerialized) { + Store (procIndirectRegisterRead (Arg0, Arg1, Arg2), Local0) + Or (And (Local0, Arg3), Arg4, Local0) + procIndirectRegisterWrite (Arg0, Arg1, Arg2, Local0) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Find Pci Capability + * + * Arg0 - PCI address Bus/device/func + * Arg1 - Capability id + */ + Method (procFindPciCapability, 2, NotSerialized) { + Store (0x34, Local1) + if (LEqual (procPciDwordRead (Arg0, 0x0), 0xFFFFFFFF)) { + // Device not present + return (0) + } + Store (1, Local0) + while (LEqual (Local0, 1)) { + Store (And (procPciDwordRead (Arg0, Local1), 0xFF), Local1) + if (LEqual (Local1, 0)) { + break + } + if (LEqual (And (procPciDwordRead (Arg0, Local1), 0xFF), Arg1)) { + Store (0, Local0) + } else { + Increment (Local1) + } + } + return (Local1) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * + * + * Arg0 - Aspm + * Arg1 - 0: Read, 1: Write + */ + Method (procPcieSbAspmControl, 2, Serialized) { + // Create an opregion for PM IO Registers + OperationRegion (PMIO, SystemIO, 0xCD6, 0x2) + Field (PMIO, ByteAcc, NoLock, Preserve) + { + PMRI, 8, + PMRD, 8 + } + IndexField (PMRI, PMRD, ByteAcc, NoLock, Preserve) + { + Offset(0xE0), // IO Base address of A-Link Express/ A-Link Bridge register + ABAR, 32, + } + OperationRegion (ACFG, SystemIO, ABAR, 0x8) + Field (ACFG, DWordAcc, Nolock, Preserve) //AB_INDX/AB_DATA + { + ABIX, 32, + ABDA, 32 + } + + Store (0, Local0) + if (LEqual (Arg1, 0)) { + Store (0x80000068, ABIX) + Store (ABDA, Local0) + return (Local0) + } else { + Store (0x80000068, ABIX) + Store (ABDA, Local0) + Or (And (Local0, 0xfffffffc), Arg0, Local0) + Store (Local0, ABDA) + } + } + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPortData.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPortData.esl new file mode 100644 index 0000000..228c839 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPortData.esl @@ -0,0 +1,109 @@ +/** + * @file + * + * ALIB ASL library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 44324 $ @e $Date: 2010-12-22 01:16:51 -0800 (Wed, 22 Dec 2010) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + + /*----------------------------------------------------------------------------------------*/ + /** + * PCIe port info + * + */ + + Name ( + AD07, + Package () { + Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev2 + Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev3 + Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev4 + Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev5 + Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev6 + Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev7 + Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev8 + Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev9 + } + ) + + Alias ( + AD07, + varPortInfo + ) + + + /*----------------------------------------------------------------------------------------*/ + /** + * + * + * Arg0 - Port ID + * Retval - buffer that represent port data set + */ + Method (procPcieGetPortInfo, 1, NotSerialized) { + return (DeRefOf (Index (varPortInfo, Arg0))) + } + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl new file mode 100644 index 0000000..bedd41c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl @@ -0,0 +1,825 @@ +/** +* @file +* +* ALIB PSPP ASL library +* +* +* +* @xrefitem bom "File Content Label" "Release Content" +* @e project: AGESA +* @e sub-project: GNB +* @e $Revision: 65976 $ @e $Date: 2012-02-27 22:24:12 -0600 (Mon, 27 Feb 2012) $ +* +*/ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + + /*----------------------------------------------------------------------------------------*/ + /** + * PCIe Performance Policy + * + * varPsppPolicy - 0 Disabled + * 1 Performance + * 2 Balance Hight + * 3 Balance Low + * 4 Power Saving + */ + Name ( + AD02, + 0x0 + ) + + Alias ( + AD02, + varPsppPolicy + ) + + /*----------------------------------------------------------------------------------------*/ + /** + * GEN2 VID + * + */ + + Name ( + AD03, + 0x0 + ) + + Alias ( + AD03, + varGen2Vid + ) + + /*----------------------------------------------------------------------------------------*/ + /** + * GEN1 VID + * + */ + Name ( + AD04, + 0x0 + ) + + Alias ( + AD04, + varGen1Vid + ) + + /*----------------------------------------------------------------------------------------*/ + /** + * Boot VID + * + */ + + Name ( + AD05, + 0x0 + ) + + Alias ( + AD05, + varBootVid + ) + + /*----------------------------------------------------------------------------------------*/ + /** + * Max Port link speed + * + */ + Name (AD06, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) + + Alias (AD06, varMaxLinkSpeed) + + + /*----------------------------------------------------------------------------------------*/ + /** + * Max link speed that was changed during runtime (hotplug for instance) + * + */ + + Name (AD08, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) + + Alias (AD08, varOverrideLinkSpeed) + + /*----------------------------------------------------------------------------------------*/ + /** + * Policy service status + * + * varPsppPolicyService - 0 (Stopped) + * 1 (Started) + */ + + Name (varPsppPolicyService, 0x0 ) + + /*----------------------------------------------------------------------------------------*/ + /** + * AC DC state + * + * varPsppAcDcState - 0 (AC) + * 1 (DC) + */ + + Name (varPsppAcDcState, 0x0) + Name (varPsppAcDcOverride, 0x1) + + /*----------------------------------------------------------------------------------------*/ + /** + * Client ID array + * + */ + + Name (varPsppClientIdArray, + Package () {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000} + ) + + Name (varDefaultPsppClientIdArray, + Package () {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000} + ) + /*----------------------------------------------------------------------------------------*/ + /** + * LInk speed requested by device driver + * + */ + + Name (varRequestedLinkSpeed, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) + + /*----------------------------------------------------------------------------------------*/ + /** + * Current link speed + * + */ + Name (AD09, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }) + Alias (AD09, varCurrentLinkSpeed) + /*----------------------------------------------------------------------------------------*/ + /** + * Template link speed + * + */ + Name ( + varGen1LinkSpeedTemplate, + Package () { + DEF_LINK_SPEED_GEN1, + DEF_LINK_SPEED_GEN1, + DEF_LINK_SPEED_GEN1, + DEF_LINK_SPEED_GEN1, + DEF_LINK_SPEED_GEN1, + DEF_LINK_SPEED_GEN1, + DEF_LINK_SPEED_GEN1, + DEF_LINK_SPEED_GEN1 + }) + + /*----------------------------------------------------------------------------------------*/ + /** + * Template link speed + * + */ + Name (varLowVoltageRequest, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }) + + /*----------------------------------------------------------------------------------------*/ + /** + * Global varuable + * + */ + Name (varPortIndex, 0) + + /*----------------------------------------------------------------------------------------*/ + /** + * Sclk VID that was changed during runtime + * + */ + + Name (AD10, Package () {0x00, 0x00, 0x00, 0x00}) + + Alias (AD10, varSclkVid) + + /*----------------------------------------------------------------------------------------*/ + /** + * Report AC/DC state + * + * Arg0 - Data Buffer + */ + Method (procPsppReportAcDsState, 1, Serialized) { + Store ("PsppReportAcDsState Enter", Debug) + + Store (DeRefOf (Index (Arg0, 0x2)), varArgAcDcStateLocal1) + Store (Concatenate (" AC/DC state: ", ToHexString (varArgAcDcStateLocal1), varStringBuffer), Debug) + + Store (procPsppGetAcDcState(), varCurrentAcDcStateLocal0) + Store (varArgAcDcStateLocal1, varPsppAcDcState) + + Or (ShiftLeft (1, DEF_SCARTCH_PSPP_ACDC_OFFSET), ShiftLeft (1, DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET), Local2) + Or (ShiftLeft (varPsppAcDcState, DEF_SCARTCH_PSPP_ACDC_OFFSET), ShiftLeft (varPsppAcDcOverride, DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET), Local3) + procIndirectRegisterRMW (0x0, 0x60, 0xF4, Not (Local2), And (Local2, Local3)) + + + if (LEqual (varArgAcDcStateLocal1, varCurrentAcDcStateLocal0)) { + Store (" No action. [AC/DC state not changed]", Debug) + Store ("PsppReportAcDsState Exit", Debug) + return (0) + } + + // Disable both APM (boost) and PDM flow on DC event enable it on AC. + procApmPdmActivate(varPsppAcDcState) + + // Set DPM state for Power Saving, due to this policy will not attend ApplyPsppState service. + if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING)) { + procNbLclkDpmActivate(DEF_LINK_SPEED_GEN1) +#ifdef ALTVDDNB_SUPPORT + procNbAltVddNb (DEF_LINK_SPEED_GEN1) +#endif + } + if (LOr (LLessEqual (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LGreaterEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) { + Store (" No action. [Policy type]", Debug) + Store ("PsppReportAcDsState Exit", Debug) + return (0) + } + if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) { + Store (" No action. [Policy not started]", Debug) + Store ("PsppReportAcDsState Exit", Debug) + return (0) + } + procApplyPsppState () + Store ("PsppReportAcDsState Exit", Debug) + return (0) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * PCIe Performance Request + * + * Arg0 - Data Buffer + */ + Method (procPsppPerformanceRequest, 1, NotSerialized) { + Store (procPsppProcessPerformanceRequest (Arg0), Local7) + Store (DeRefOf (Index (Local7, 2)), varReturnStatusLocal0) + if (LNotEqual (varReturnStatusLocal0, 2)) { + return (Local7) + } + procApplyPsppState () + return (Local7) + } + /*----------------------------------------------------------------------------------------*/ + /** + * PCIe Performance Request + * + * Arg0 - Data Buffer + */ + Method (procPsppProcessPerformanceRequest, 1, NotSerialized) { + Store ("PsppProcessPerformanceRequest Enter", Debug) + Name (varClientBus, 0) + Store (0, varPortIndex) + Store (Buffer (10) {}, Local7) + CreateWordField (Local7, 0x0, varReturnBufferLength) + Store (3, varReturnBufferLength) + CreateByteField (Local7, 0x2, varReturnStatus) + Store (1, varReturnStatus) + + if (LOr (LLessEqual (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LGreaterEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) { + Store (" No action. [Policy type]", Debug) + Store ("PsppPerformanceRequest Exit", Debug) + return (Local7) + } + if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) { + Store (" No action. [Policy not started]", Debug) + Store ("PsppPerformanceRequest Exit", Debug) + return (Local7) + } + CreateWordField (Arg0, 0x2, varClientId) + CreateWordField (Arg0, 0x4, varValidFlag) + CreateWordField (Arg0, 0x6, varFlag) + CreateByteField (Arg0, 0x8, varRequestType) + CreateByteField (Arg0, 0x9, varRequestData) + + Store (Concatenate (" Client ID : ", ToHexString (varClientId), varStringBuffer), Debug) + Store (Concatenate (" Valid Flags : ", ToHexString (varValidFlag), varStringBuffer), Debug) + Store (Concatenate (" Flags : ", ToHexString (varFlag), varStringBuffer), Debug) + Store (Concatenate (" Request Type: ", ToHexString (varRequestType), varStringBuffer), Debug) + Store (Concatenate (" Request Data: ", ToHexString (varRequestData), varStringBuffer), Debug) + + + And (ShiftRight (varClientId, 8), 0xff, varClientBus) + while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { + if (LEqual (procChecPortAllocated (varPortIndex), DEF_PORT_ALLOCATED)) { + Store (procPciDwordRead (ShiftLeft (Add( varPortIndex, 2), 3), 0x18), Local1) + And (ShiftRight (Local1, 16), 0xff, varSubordinateBusLocal2) //Local2 Port Subordinate Bus number + And (ShiftRight (Local1, 8), 0xff, varSecondaryBusLocal1) //Local1 Port Secondary Bus number + if (LAnd (LGreaterEqual (varClientBus, Local1), LLessEqual(varClientBus, Local2))) { + break + } + } + Increment (varPortIndex) + } + if (LGreater (varPortIndex, varMaxPortIndexNumber)) { + Store ("PsppPerformanceRequest Exit", Debug) + return (Local7) + } + + Store (Concatenate (" Performance request for port index : ", ToHexString (varPortIndex), Local6), Debug) + + if (LEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), 0x0000)) { + Store (varClientId, Index (varPsppClientIdArray, varPortIndex)) + } ElseIf (LNotEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), varClientId)) { + // We already have registered client + Store (" No action. [Unsupported request]", Debug) + Store ("PsppPerformanceRequest Exit", Debug) + return (Local7) + } + Store (0, Index (varLowVoltageRequest, varPortIndex)) + if (LEqual (varRequestData, 0)) { + Store (0x0000, Index (varPsppClientIdArray, varPortIndex)) + } + if (LEqual (varRequestData, 1)) { + Store (1, Index (varLowVoltageRequest, varPortIndex)) + } + if (LEqual (varRequestData, 2)) { + Store (DEF_LINK_SPEED_GEN1, Index (varRequestedLinkSpeed, varPortIndex)) + } + if (LEqual (varRequestData, 3)) { + Store (DEF_LINK_SPEED_GEN2, Index (varRequestedLinkSpeed, varPortIndex)) + } + if (LEqual (And (varValidFlag, varFlag), 0x1)) { + Store (DerefOf (Index (varMaxLinkSpeed, varPortIndex)), Index (varRequestedLinkSpeed, varPortIndex)) + } + Store (2, varReturnStatus) + Store ("PsppProcessPerformanceRequest Exit", Debug) + return (Local7) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * PSPP Start/Stop Management Request + * + * Arg0 - Data Buffer + */ + + Method (procChecPortAllocated, 1, Serialized) { + if (LEqual (DeRefOf (Index (varMaxLinkSpeed, Arg0)), 0)) { + return (DEF_PORT_NOT_ALLOCATED) + } + return (DEF_PORT_ALLOCATED) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * PSPP Start/Stop Management Request + * + * Arg0 - Data Buffer + */ + Method (procPsppControl, 1, Serialized) { + Store ("PsppControl Enter", Debug) + Store (Buffer (256) {}, Local7) + Store (3, Index (Local7, 0x0)) // Return Buffer Length + Store (0, Index (Local7, 0x1)) // Return Buffer Length + Store (0, Index (Local7, 0x2)) // Return Status + + Store (DerefOf (Index (Arg0, 0x2)), varPsppPolicyService) + + Store (procIndirectRegisterRead (0x0, 0x60, 0xF4), varPsppScratchLocal0) + + if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_START)) { + if (LEqual (And (varPsppScratchLocal0, 1), DEF_PSPP_POLICY_START)) { + // Policy already started + Store (" No action. [Policy already started]", Debug) + Store ("PsppControl Exit", Debug) + return (Local7) + } + Or (varPsppScratchLocal0, DEF_PSPP_POLICY_START, varPsppScratchLocal0) + } + if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) { + if (LEqual (And (varPsppScratchLocal0, 1), DEF_PSPP_POLICY_STOP)) { + // Policy already stopped + Store (" No action. [Policy already stopped]", Debug) + Store ("PsppControl Exit", Debug) + return (Local7) + } + And (varPsppScratchLocal0, Not (DEF_PSPP_POLICY_START), varPsppScratchLocal0) + } + Or (varPsppScratchLocal0, Shiftleft (varPsppPolicy, DEF_SCARTCH_PSPP_POLICY_OFFSET), varPsppScratchLocal0) + procIndirectRegisterWrite (0x0, 0x60, 0xF4, varPsppScratchLocal0) + + procCopyPackage (RefOf (varDefaultPsppClientIdArray), RefOf (varPsppClientIdArray)) + + // Reevaluate APM/PDM state here on S3 resume while staying on DC. + procApmPdmActivate(varPsppAcDcState) + + // Set DPM state for PSPP Power Saving, due to this policy will not attend ApplyPsppState service. + if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING)) { + procNbLclkDpmActivate(DEF_LINK_SPEED_GEN1) +#ifdef ALTVDDNB_SUPPORT + procNbAltVddNb (DEF_LINK_SPEED_GEN1) +#endif + } + //Reevaluate PCIe speed for all devices base on PSPP state switch to boot up voltage + if (LAnd (LGreater (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LLess (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) { + // Load default speed capability state + if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCEHIGH)) { + procCopyPackage (RefOf (varMaxLinkSpeed), RefOf (varCurrentLinkSpeed)) + Store (0, varPortIndex) + while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { + if (LNotEqual (DeRefOf (Index (varOverrideLinkSpeed, varPortIndex)), 0)) { + Store (DeRefOf (Index (varOverrideLinkSpeed, varPortIndex)), Index (varCurrentLinkSpeed, varPortIndex)) + } + Increment (varPortIndex) + } + } else { + procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varCurrentLinkSpeed)) +#ifdef SBLINK_BALANCE_LOW_GEN2_SUPPORT + Store (DeRefOf (Index (varMaxLinkSpeed, DEF_SB_PORT_INDEX)),Index (varCurrentLinkSpeed, DEF_SB_PORT_INDEX)) + //Store (DEF_LINK_SPEED_GEN2, Index (varCurrentLinkSpeed, DEF_SB_PORT_INDEX)) +#endif + + } + procApplyPsppState () + } + Store ("PsppControl Exit", Debug) + return (Local7) + } + + Name (varNewLinkSpeed, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) + + /*----------------------------------------------------------------------------------------*/ + /** + * Evaluate PCIe speed on all links according to PSPP state and client requests + * + * + * + */ + Method (procApplyPsppState, 0, Serialized) { + Store ("ApplyPsppState Enter", Debug) + Store (0, varPortIndex) + + procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varNewLinkSpeed)) + while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { + if (LEqual (procChecPortAllocated(varPortIndex), DEF_PORT_ALLOCATED)) { + Store (procGetPortRequestedCapability (varPortIndex), Index (varNewLinkSpeed, varPortIndex)) + } + Increment (varPortIndex) + } + if (LNotEqual(Match (varLowVoltageRequest, MEQ, 0x01, MTR, 0, 0), ONES)) { + procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varNewLinkSpeed)) + } + if (LNotEqual(Match (varNewLinkSpeed, MEQ, DEF_LINK_SPEED_GEN2, MTR, 0, 0), ONES)) { + // Set GEN2 voltage + Store ("Set GEN2 VID", Debug) +#ifdef ALTVDDNB_SUPPORT + procNbAltVddNb (DEF_LINK_SPEED_GEN2) +#endif + procPcieSetVoltage (DEF_LINK_SPEED_GEN2, 1) +// procPcieAdjustPll (DEF_LINK_SPEED_GEN2) + procNbLclkDpmActivate(DEF_LINK_SPEED_GEN2) + } + Store (0, varPortIndex) + while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { + if (LEqual (procChecPortAllocated(varPortIndex), DEF_PORT_NOT_ALLOCATED)) { + Increment (varPortIndex) + continue + } + Store (DerefOf (Index (varCurrentLinkSpeed, varPortIndex)), varCurrentLinkSpeedLocal0) + Store (DerefOf (Index (varNewLinkSpeed, varPortIndex)), varNewLinkSpeedLocal2) + if (LEqual (varCurrentLinkSpeedLocal0, varNewLinkSpeedLocal2)) { + Increment (varPortIndex) + continue + } + Store (varNewLinkSpeedLocal2, Index (varCurrentLinkSpeed, varPortIndex)) + procSetPortCapabilityAndSpeed (varPortIndex, varNewLinkSpeedLocal2) + Increment (varPortIndex) + } + if (LEqual(Match (varNewLinkSpeed, MEQ, DEF_LINK_SPEED_GEN2, MTR, 0, 0), ONES)) { + // Set GEN1 voltage + Store ("Set GEN1 VID", Debug) + procNbLclkDpmActivate(DEF_LINK_SPEED_GEN1) +// procPcieAdjustPll (DEF_LINK_SPEED_GEN1) + procPcieSetVoltage (DEF_LINK_SPEED_GEN1, 0) +#ifdef ALTVDDNB_SUPPORT + procNbAltVddNb (DEF_LINK_SPEED_GEN1) +#endif + } +#ifdef PHY_SPEED_REPORT_SUPPORT + procReportPhySpeedCap () +#endif + Store ("ApplyPsppState Exit", Debug) + } + /*----------------------------------------------------------------------------------------*/ + /** + * Read PCI config register + * + * Arg0 - Port Index + * + */ + Method (procGetPortRequestedCapability, 1) { + Store (DEF_LINK_SPEED_GEN2, varCurrentSpeedLocal0) + Store (procPsppGetAcDcState(), varAcDcStateLocal1) + if (LEqual (DerefOf (Index (varPsppClientIdArray, Arg0)), 0x0000)) { + if (LOr (LEqual (varAcDcStateLocal1, DEF_PSPP_STATE_DC), LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCELOW))) { + // Default policy cap to GEN1 + Store (DEF_LINK_SPEED_GEN1, varCurrentSpeedLocal0) + } +#ifdef SBLINK_BALANCE_LOW_GEN2_SUPPORT + if (LAnd (LEqual (varAcDcStateLocal1, DEF_PSPP_STATE_AC), LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCELOW))) { + if (LEqual (Arg0, DEF_SB_PORT_INDEX)) { + Store (DEF_LINK_SPEED_GEN2, varCurrentSpeedLocal0) + } + } +#endif + if (LNotEqual (DerefOf (Index (varOverrideLinkSpeed, Arg0)), 0)) { + Store (DerefOf (Index (varOverrideLinkSpeed, Arg0)), varCurrentSpeedLocal0) + } + } else { + Store (DerefOf (Index (varRequestedLinkSpeed, Arg0)), varCurrentSpeedLocal0) + } + Store (DerefOf (Index (varMaxLinkSpeed, varPortIndex)),varMaxLinkSpeedLocal2) + if (LLess (varMaxLinkSpeedLocal2, varCurrentSpeedLocal0)) { + Store (varMaxLinkSpeedLocal2, varCurrentSpeedLocal0) + } + + + return (varCurrentSpeedLocal0) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Set capability and speed + * + * Arg0 - Port Index + * Arg1 - Link speed + */ + Method (procSetPortCapabilityAndSpeed, 2, NotSerialized) { + Store ("SetPortCapabilityAndSpeed Enter", Debug) + Store (Concatenate (" Port Index : ", ToHexString (Arg0), varStringBuffer), Debug) + Store (Concatenate (" Speed : ", ToHexString (Arg1), varStringBuffer), Debug) + + //UnHide UMI port + if (LEqual (Arg0, 6)) { + procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x40); + } + + procPcieSetLinkSpeed (Arg0, Arg1) + + // Programming for LcInitSpdChgWithCsrEn + if (LNotEqual (DeRefOf (Index (varPsppClientIdArray, Arg0)), 0x0000)) { + // Registered port, LcInitSpdChgWithCsrEn = 0. + procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x0) + } else { + procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x00001000) + } + + // Determine port PCI address and check port present + Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1) + And (procPciePortIndirectRegisterRead (Arg0, 0xA5), 0x3f, varPortPresentLocal3) + procPciePortIndirectRegisterWrite (Arg0, 0x1, varPortPresentLocal3) + if (LGreaterEqual (varPortPresentLocal3, 0x10)) { + procDisableAndSaveAspm (Arg0) + Store (1, Local2) + while (Local2) { + //retrain port + procPciDwordRMW (varPortBdfLocal1, 0x68, Not (0x00000000), 0x20) + Sleep (30) + while (And (procPciDwordRead (varPortBdfLocal1, 0x68), 0x08000000)) { + Sleep (10) + } + Store (0, Local2) + if (LEqual (Arg1, DEF_LINK_SPEED_GEN1)) { + //Store (procPciePortIndirectRegisterRead (Arg0, 0xA4), varLcCurrentLinkSpeedLocal4) + if (LNotEqual (procPciePortGetCurrentLinkSpeed (Arg0), DEF_LINK_SPEED_GEN1)) { + Store (1, Local2) + } + } + } + procRestoreAspm (Arg0) + } else { + Store (" Device not present. Set capability and speed only", Debug) + } + //Hide UMI port + if (LEqual (Arg0, 6)) { + procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x00); + } + Store ("SetPortCapabilityAndSpeed Exit", Debug) + } + + Name (varPcieLinkControlArray, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}) + Name (varPcieLinkControlOffset, 0) + Name (varPcieLinkControlData, 0) + Name (varPcieRcControlData, 0) + + /*----------------------------------------------------------------------------------------*/ + /** + * Disable and save ASPM state + * + * Arg0 - Port Index + */ + Method (procDisableAndSaveAspm, 1, Serialized) { + Store (0, varPcieLinkControlOffset) + Store (0, varPcieLinkControlData) + + Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1) + if (LEqual (Arg0, 6)) { + Store (" Disable SB ASPM", Debug) + Store (procPcieSbAspmControl (0, 0), Index (varPcieLinkControlArray, 0)) + Store (Concatenate (" PcieLinkControl Data : ", ToHexString (DerefOf(Index (varPcieLinkControlArray, 0))), varStringBuffer), Debug) + procPcieSbAspmControl (0, 1) + return (0) + } + + Store (procPciDwordRead (varPortBdfLocal1, 0x18), varTempLocal3) + Store (And (ShiftRight (varTempLocal3, 8), 0xFF), varTempLocal3) + + Store (Concatenate (" Disable EP ASPM on Secondary Bus : ", ToHexString (varTempLocal3), varStringBuffer), Debug) + + Store (ShiftLeft (varTempLocal3, 8), varEndpointBdfLocal2) + Store (procPciDwordRead (varEndpointBdfLocal2, 0xC), varTempLocal3) + Store (And (ShiftRight (varTempLocal3, 16), 0xFF), varTempLocal3) + + Store (Concatenate (" EP Header type : ", ToHexString (varTempLocal3), varStringBuffer), Debug) + + if (LNotEqual (And (varTempLocal3, 0x80), 0)) { + Store (0x7, varMaxFunctionLocal0) + } else { + Store (0x0, varMaxFunctionLocal0) + } + Store (0, varFunctionLocal4) + while (LLessEqual (varFunctionLocal4, varMaxFunctionLocal0)) { + //Find PcieLinkControl register offset = PcieCapPtr + 0x10 + Store (procFindPciCapability (Add (varEndpointBdfLocal2, varFunctionLocal4), 0x10), varPcieLinkControlOffset) + if (LEqual (varPcieLinkControlOffset, 0)) { + Increment (varFunctionLocal4) + continue + } + Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset) + + Store (Concatenate (" Function number of Secondary Bus : ", ToHexString (varFunctionLocal4), varStringBuffer), Debug) + Store (Concatenate (" PcieLinkControl register offset : ", ToHexString (varPcieLinkControlOffset), varStringBuffer), Debug) + // Save ASPM on EP + Store (procPciDwordRead (Add (varEndpointBdfLocal2, varFunctionLocal4) , varPcieLinkControlOffset), varPcieLinkControlData) + Store (And (varPcieLinkControlData, 0x3), Index (varPcieLinkControlArray, varFunctionLocal4)) + + Store (Concatenate (" PcieLinkControl Data : ", ToHexString (varPcieLinkControlData), varStringBuffer), Debug) + + procPciDwordRMW (Add (varEndpointBdfLocal2, varFunctionLocal4), varPcieLinkControlOffset, Not (0x00000003), 0x00) + Store ("Disable ASPM on EP Complete!!", Debug) + Increment (varFunctionLocal4) + } + //Disable ASPM on RC + Store (procPciDwordRead (varPortBdfLocal1, 0x68), varPcieRcControlData) + procPciDwordRMW (varPortBdfLocal1, 0x68, Not (0x00000003), 0x00) + } + /*----------------------------------------------------------------------------------------*/ + /** + * Restore ASPM + * + * Arg0 - Port Index + */ + Method (procRestoreAspm, 1, Serialized) { + + Store (0, varPcieLinkControlOffset) + Store (0, varPcieLinkControlData) + + + // Restore SB ASPM + if (LEqual (Arg0, 6)) { + Store (" Restore SB ASPM", Debug) + Store (Concatenate (" PcieLinkControl Data : ", ToHexString (DerefOf(Index (varPcieLinkControlArray, 0))), varStringBuffer), Debug) + procPcieSbAspmControl (DerefOf(Index (varPcieLinkControlArray, 0)), 1) + return (0) + } + Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1) + // Restore EP ASPM + Store (procPciDwordRead (varPortBdfLocal1, 0x18), varTempLocal3) + Store (And (ShiftRight (varTempLocal3, 8), 0xFF), varTempLocal3) + // Restore ASPM on RC + procPciDwordRMW (varPortBdfLocal1, 0x68, Not (0x00000003), And (varPcieRcControlData, 0x3)) + + Store (Concatenate (" Disable EP ASPM on SecondaryBus : ", ToHexString (varTempLocal3), varStringBuffer), Debug) + + Store (ShiftLeft (varTempLocal3, 8), varEndpointBdfLocal2) + Store (procPciDwordRead (varEndpointBdfLocal2, 0xC), varTempLocal3) + Store (And (ShiftRight (varTempLocal3, 16), 0xFF), varTempLocal3) + + Store (Concatenate (" EP Header type : ", ToHexString (varTempLocal3), varStringBuffer), Debug) + + if (LNotEqual (And (varTempLocal3, 0x80), 0)) { + Store (0x7, varMaxFunctionLocal0) + } else { + Store (0x0, varMaxFunctionLocal0) + } + Store (0, varFunctionLocal4) + while (LLessEqual (varFunctionLocal4, varMaxFunctionLocal0)) { + //Find PcieLinkControl register offset = PcieCapPtr + 0x10 + Store (procFindPciCapability (Add (varEndpointBdfLocal2, varFunctionLocal4), 0x10), varPcieLinkControlOffset) + if (LEqual (varPcieLinkControlOffset, 0)) { + Increment (varFunctionLocal4) + continue + } + Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset) + + Store (Concatenate (" Restore Function number of SecondaryBus : ", ToHexString (varFunctionLocal4), varStringBuffer), Debug) + Store (Concatenate (" Restore PcieLinkControl register offset : ", ToHexString (varPcieLinkControlOffset), varStringBuffer), Debug) + Store (Concatenate (" PcieLinkControl Data : ", ToHexString (DerefOf (Index (varPcieLinkControlArray, varFunctionLocal4))), varStringBuffer), Debug) + + procPciDwordWrite (Add (varEndpointBdfLocal2, varFunctionLocal4), varPcieLinkControlOffset, DerefOf (Index (varPcieLinkControlArray, varFunctionLocal4))) + Increment (varFunctionLocal4) + } + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Request VID + * + * Arg0 - Port Index + * Arg1 - PCIe speed + */ + + Method (procPcieSetLinkSpeed, 2) { + Store (ShiftLeft (Add( Arg0, 2), 3), Local0) + if (LEqual (Arg1, DEF_LINK_SPEED_GEN1)) { + procPciDwordRMW (Local0, 0x88, Not (0x0000002f), 0x21) + procPciePortIndirectRegisterRMW (Arg0, 0xA4, Not (0x20000001), 0x0) + } else { + procPciePortIndirectRegisterRMW (Arg0, 0xA4, Not (0x20000001), 0x20000001) + procPciDwordRMW (Local0, 0x88, Not (0x0000002f), 0x2) + } + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Read PCIe port indirect register + * + * Arg0 - Ref Source Pckage + * Arg1 - Ref to Destination Package + * + */ + Method (procCopyPackage, 2, NotSerialized) { + + Store (SizeOf (Arg0), Local1) + Store (0, Local0) + While (LLess (Local0, Local1)) { + Store (DerefOf(Index(DerefOf (Arg0), Local0)), Index(DerefOf (Arg1), Local0)) + Increment (Local0) + } + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Read PCIe port indirect register + * + * Arg0 - Ref Source Pckage + * Arg1 - Ref to Destination Package + * + */ + Method (procPsppGetAcDcState, 0 , NotSerialized) { + Return (And (varPsppAcDcState, varPsppAcDcOverride)) + } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c new file mode 100644 index 0000000..a88b5d9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c @@ -0,0 +1,445 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe link ASPM + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "OptionGnb.h" +#include "GnbCommonLib.h" +#include "GnbPcieInitLibV1.h" +#include "PcieAspmBlackList.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPM_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_BUILD_OPTIONS GnbBuildOptions; +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +typedef struct { + GNB_PCI_SCAN_DATA ScanData; + PCIE_ASPM_TYPE Aspm; + PCI_ADDR DownstreamPort; +} PCIE_ASPM_DATA; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +PcieAspmInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + + +SCAN_STATUS +PcieAspmCallback ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ); + +VOID +PcieAspmEnableOnLink ( + IN PCI_ADDR Downstream, + IN PCI_ADDR Upstream, + IN PCIE_ASPM_TYPE Aspm, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +PCIE_ASPM_TYPE +PcieAspmGetPmCapability ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Enable PCIE Advance state power management + * + * + * + * @param[in] DownstreamPort PCI Address of the downstream port + * @param[in] Aspm ASPM type + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +VOID +PcieLinkAspmEnable ( + IN PCI_ADDR DownstreamPort, + IN PCIE_ASPM_TYPE Aspm, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCIE_ASPM_DATA PcieAspmData; + PcieAspmData.Aspm = Aspm; + PcieAspmData.ScanData.StdHeader = StdHeader; + PcieAspmData.ScanData.GnbScanCallback = PcieAspmCallback; + GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieAspmData.ScanData); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Evaluate device + * + * + * + * @param[in] Device PCI Address + * @param[in,out] ScanData Scan configuration data + * @retval Scan Status of 0 + */ + +SCAN_STATUS +PcieAspmCallback ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ) +{ + SCAN_STATUS ScanStatus; + PCIE_ASPM_DATA *PcieAspmData; + PCIE_DEVICE_TYPE DeviceType; + ScanStatus = SCAN_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, " PcieAspmCallback for Device = %d:%d:%d\n", + Device.Address.Bus, + Device.Address.Device, + Device.Address.Function + ); + PcieAspmData = (PCIE_ASPM_DATA *) ScanData; + ScanStatus = SCAN_SUCCESS; + DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader); + switch (DeviceType) { + case PcieDeviceRootComplex: + case PcieDeviceDownstreamPort: + PcieAspmData->DownstreamPort = Device; + //PcieExitLatencyData->LinkCount++; + GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader); + GnbLibPciScanSecondaryBus (Device, &PcieAspmData->ScanData); + //PcieExitLatencyData->LinkCount--; + break; + case PcieDeviceUpstreamPort: + PcieAspmEnableOnLink ( + PcieAspmData->DownstreamPort, + Device, + PcieAspmData->Aspm, + ScanData->StdHeader + ); + GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader); + GnbLibPciScanSecondaryBus (Device, &PcieAspmData->ScanData); + ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; + break; + case PcieDeviceEndPoint: + case PcieDeviceLegacyEndPoint: + PcieAspmEnableOnLink ( + PcieAspmData->DownstreamPort, + Device, + PcieAspmData->Aspm, + ScanData->StdHeader + ); + ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; + break; + default: + break; + } + return ScanStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set ASMP State on PCIe device function + * + * + * + * @param[in] Function PCI address of function. + * @param[in] Aspm Aspm capability to enable + * @param[in] StdHeader Standard configuration header + * + */ + /*----------------------------------------------------------------------------------------*/ +VOID +PcieAspmEnableOnFunction ( + IN PCI_ADDR Function, + IN PCIE_ASPM_TYPE Aspm, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 PcieCapPtr; + PcieCapPtr = GnbLibFindPciCapability (Function.AddressValue, PCIE_CAP_ID, StdHeader); + if (PcieCapPtr != 0) { + GnbLibPciRMW ( + Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER) , + AccessS3SaveWidth8, + (UINT32)~(BIT0 | BIT1), + Aspm, + StdHeader + ); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set ASMP State on all function of PCI device + * + * + * + * @param[in] Device PCI address of device. + * @param[in] Aspm Aspm capability to enable + * @param[in] StdHeader Standard configuration header + * + */ + /*----------------------------------------------------------------------------------------*/ +STATIC VOID +PcieAspmEnableOnDevice ( + IN PCI_ADDR Device, + IN PCIE_ASPM_TYPE Aspm, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 MaxFunc; + UINT8 CurrentFunc; + MaxFunc = GnbLibPciIsMultiFunctionDevice (Device.AddressValue, StdHeader) ? 7 : 0; + for (CurrentFunc = 0; CurrentFunc <= MaxFunc; CurrentFunc++) { + Device.Address.Function = CurrentFunc; + if (GnbLibPciIsDevicePresent (Device.AddressValue, StdHeader)) { + PcieAspmEnableOnFunction (Device, Aspm, StdHeader); + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Enable ASPM on link + * + * + * + * @param[in] Downstream PCI Address of downstrteam port + * @param[in] Upstream PCI Address of upstream port + * @param[in] Aspm Aspm capability to enable + * @param[in] StdHeader Standard configuration header + */ + +VOID +PcieAspmEnableOnLink ( + IN PCI_ADDR Downstream, + IN PCI_ADDR Upstream, + IN PCIE_ASPM_TYPE Aspm, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCIe_LINK_ASPM LinkAsmp; + PCIE_ASPM_TYPE DownstreamCap; + PCIE_ASPM_TYPE UpstreamCap; + LinkAsmp.DownstreamPort = Downstream; + DownstreamCap = PcieAspmGetPmCapability (Downstream, StdHeader); + LinkAsmp.UpstreamPort = Upstream; + UpstreamCap = PcieAspmGetPmCapability (Upstream, StdHeader); + LinkAsmp.DownstreamAspm = DownstreamCap & UpstreamCap & Aspm & AspmL1; + LinkAsmp.UpstreamAspm = LinkAsmp.DownstreamAspm; + LinkAsmp.RequestedAspm = Aspm; + if ((UpstreamCap & Aspm & AspmL0s) != 0) { + LinkAsmp.UpstreamAspm |= AspmL0s; + } + if ((DownstreamCap & Aspm & AspmL0s) != 0) { + LinkAsmp.DownstreamAspm |= AspmL0s; + } + if (GnbBuildOptions.PcieAspmBlackListEnable == 1) { + PcieAspmBlackListFeature (&LinkAsmp, StdHeader); + } + //AgesaPcieLinkAspm (&LinkAsmp, StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, " Set ASPM [%d] for Device = %d:%d:%d\n", + (LinkAsmp.UpstreamAspm) , + LinkAsmp.UpstreamPort.Address.Bus, + LinkAsmp.UpstreamPort.Address.Device, + LinkAsmp.UpstreamPort.Address.Function + ); + IDS_HDT_CONSOLE (GNB_TRACE, " Set ASPM [%d] for Device = %d:%d:%d\n", + (LinkAsmp.DownstreamAspm) , + LinkAsmp.DownstreamPort.Address.Bus, + LinkAsmp.DownstreamPort.Address.Device, + LinkAsmp.DownstreamPort.Address.Function + ); + // Disable ASPM Upstream component + PcieAspmEnableOnDevice (Upstream, AspmDisabled, StdHeader); + // Enable ASPM Donstream component + PcieAspmEnableOnFunction (Downstream, LinkAsmp.DownstreamAspm, StdHeader); + // Enable ASPM Upstream component + PcieAspmEnableOnDevice (Upstream, LinkAsmp.UpstreamAspm, StdHeader); +} + + + +/**----------------------------------------------------------------------------------------*/ +/** + * Port/Endpoint ASMP capability + * + * + * + * @param[in] Device PCI address of downstream port + * @param[in] StdHeader Standard configuration header + * + * @retval PCIE_ASPM_TYPE + */ + /*----------------------------------------------------------------------------------------*/ +PCIE_ASPM_TYPE +PcieAspmGetPmCapability ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 PcieCapPtr; + UINT32 Value; + PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader); + if (PcieCapPtr == 0) { + return 0; + } + GnbLibPciRead ( + Device.AddressValue | (PcieCapPtr + PCIE_LINK_CAP_REGISTER), + AccessWidth32, + &Value, + StdHeader + ); + return (Value >> 10) & 3; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all active ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieAspmPortInitCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + if (Engine->Type.Port.PortData.LinkAspm != AspmDisabled && + !PcieConfigIsSbPcieEngine (Engine) && + PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { + PcieLinkAspmEnable ( + Engine->Type.Port.Address, + Engine->Type.Port.PortData.LinkAspm, + GnbLibGetHeader (Pcie) + ); + } +} + + +/**----------------------------------------------------------------------------------------*/ +/** + * Interface to enable Clock Power Managment + * + * + * + * @param[in] StdHeader Standard configuration header + * + * @retval AGESA_STATUS + */ + /*----------------------------------------------------------------------------------------*/ +AGESA_STATUS +PcieAspmInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAspmInterface Enter\n"); + AgesaStatus = PcieLocateConfigurationData (StdHeader, &Pcie); + if (AgesaStatus == AGESA_SUCCESS) { + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieAspmPortInitCallback, + NULL, + Pcie + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieAspmInterface Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.h new file mode 100644 index 0000000..16bf03e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.h @@ -0,0 +1,90 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe link ASPM + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _PCIEASPM_H_ +#define _PCIEASPM_H_ + +VOID +PcieLinkAspmEnable ( + IN PCI_ADDR DownstreamPort, + IN PCIE_ASPM_TYPE Aspm, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +PcieAspmEnableOnFunction ( + IN PCI_ADDR Function, + IN PCIE_ASPM_TYPE Aspm, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c new file mode 100644 index 0000000..d268915 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c @@ -0,0 +1,353 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe Clock Power Managment + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "PcieClkPm.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIECLKPM_PCIECLKPM_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Enable Clock Power Managment on function of the device + * + * + * + * @param[in] Function PCI address of function. + * @param[in] StdHeader Standard configuration header + * + */ + /*----------------------------------------------------------------------------------------*/ +STATIC VOID +PcieClkPmEnableOnFunction ( + IN PCI_ADDR Function, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 PcieCapPtr; + PcieCapPtr = GnbLibFindPciCapability (Function.AddressValue, PCIE_CAP_ID, StdHeader); + if (PcieCapPtr != 0) { + GnbLibPciRMW ( + Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER), + AccessS3SaveWidth32, + (UINT32)~(BIT8), + BIT8, + StdHeader + ); + } +} + + +/**----------------------------------------------------------------------------------------*/ +/** + * check capability of intire device including its functions + * + * + * + * @param[in] Device PCI address of downstream port + * @param[in] StdHeader Standard configuration header + * + * @retval TRUE - Device support Clock Power Managment + */ + /*----------------------------------------------------------------------------------------*/ +STATIC BOOLEAN +PcieClkPmCheckDeviceCapability ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + UINT8 MaxFunc; + UINT8 CurrentFunc; + UINT8 PcieCapPtr; + UINT32 Value; + + MaxFunc = GnbLibPciIsMultiFunctionDevice (Device.AddressValue, StdHeader) ? 7 : 0; + + for (CurrentFunc = 0; CurrentFunc <= MaxFunc; CurrentFunc++) { + Device.Address.Function = CurrentFunc; + if (GnbLibPciIsDevicePresent (Device.AddressValue, StdHeader)) { + PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader); + if (PcieCapPtr == 0) { + return FALSE; + } + GnbLibPciRead ( + Device.AddressValue | (PcieCapPtr + PCIE_LINK_CAP_REGISTER), + AccessWidth32, + &Value, + StdHeader + ); + if ((Value & BIT18) == 0) { + return FALSE; + } + } + } + return TRUE; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Set Clock power managment on device + * + * + * + * @param[in] Device PCI address of device. + * @param[in] StdHeader Standard configuration header + * + */ + /*----------------------------------------------------------------------------------------*/ +STATIC VOID +PcieClkPmEnableOnDevice ( + IN PCI_ADDR Device, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 MaxFunc; + UINT8 CurrentFunc; + if (PcieClkPmCheckDeviceCapability (Device, StdHeader)) { + MaxFunc = GnbLibPciIsMultiFunctionDevice (Device.AddressValue, StdHeader) ? 7 : 0; + for (CurrentFunc = 0; CurrentFunc <= MaxFunc; CurrentFunc++) { + Device.Address.Function = CurrentFunc; + if (GnbLibPciIsDevicePresent (Device.AddressValue, StdHeader)) { + IDS_HDT_CONSOLE (GNB_TRACE, " Enable Clock Power Managment for Device = %d:%d:%d\n", + Device.Address.Bus, + Device.Address.Device, + Device.Address.Function + ); + PcieClkPmEnableOnFunction (Device, StdHeader); + } + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Evaluate device + * + * + * + * @param[in] Device PCI Address + * @param[in,out] ScanData Scan configuration data + * @retval Scan Status of 0 + */ + +STATIC SCAN_STATUS +PcieClkPmCallback ( + IN PCI_ADDR Device, + IN OUT GNB_PCI_SCAN_DATA *ScanData + ) +{ + SCAN_STATUS ScanStatus; + PCIE_DEVICE_TYPE DeviceType; + ScanStatus = SCAN_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, " PcieClkPmCallback for Device = %d:%d:%d\n", + Device.Address.Bus, + Device.Address.Device, + Device.Address.Function + ); + ScanStatus = SCAN_SUCCESS; + DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader); + switch (DeviceType) { + case PcieDeviceRootComplex: + case PcieDeviceDownstreamPort: + GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader); + GnbLibPciScanSecondaryBus (Device, ScanData); + break; + case PcieDeviceUpstreamPort: + PcieClkPmEnableOnDevice (Device, ScanData->StdHeader); + GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader); + GnbLibPciScanSecondaryBus (Device, ScanData); + ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; + break; + case PcieDeviceEndPoint: + case PcieDeviceLegacyEndPoint: + PcieClkPmEnableOnDevice (Device, ScanData->StdHeader); + ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; + break; + default: + break; + } + return ScanStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Confiugure Clock Power Managment + * + * + * + * + * @param[in] DownstreamPort Downstream port PCI address + * @param[in] StdHeader Standard configuration header + * + */ + +VOID +STATIC +PcieClkPmPortInitConfigure ( + IN PCI_ADDR DownstreamPort, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GNB_PCI_SCAN_DATA ScanData; + ScanData.StdHeader = StdHeader; + ScanData.GnbScanCallback = PcieClkPmCallback; + GnbLibPciScan (DownstreamPort, DownstreamPort, &ScanData); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all active ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieClkPmPortInitCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + if (Engine->Type.Port.PortData.MiscControls.ClkPmSupport == 0x1 && + !PcieConfigIsSbPcieEngine (Engine) && + PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { + PcieClkPmPortInitConfigure ( + Engine->Type.Port.Address, + GnbLibGetHeader (Pcie) + ); + } +} + +/**----------------------------------------------------------------------------------------*/ +/** + * Interface to enable Clock Power Managment + * + * + * + * @param[in] StdHeader Standard configuration header + * + * @retval AGESA_STATUS + */ + /*----------------------------------------------------------------------------------------*/ +AGESA_STATUS +PcieClkPmInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieClkPmInterface Enter\n"); + AgesaStatus = PcieLocateConfigurationData (StdHeader, &Pcie); + if (AgesaStatus == AGESA_SUCCESS) { + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieClkPmPortInitCallback, + NULL, + Pcie + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieClkPmInterface Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.h new file mode 100644 index 0000000..3d14ac8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.h @@ -0,0 +1,81 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe link ASPM + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _PCIECLKPM_H_ +#define _PCIECLKPM_H_ + +AGESA_STATUS +PcieClkPmInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c new file mode 100644 index 0000000..4b354ca --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c @@ -0,0 +1,162 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB function to create/locate PCIe configuration data area + * + * Contain code that create/locate/manes GNB/PCIe configuration + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_GNBHANDLELIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get GNB handle + * + * + * @param[in] StdHeader Standard configuration header + */ +GNB_HANDLE * +GnbGetHandle ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCIe_PLATFORM_CONFIG *Pcie; + GNB_HANDLE *GnbHandle; + AGESA_STATUS Status; + GnbHandle = NULL; + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + GnbHandle = (GNB_HANDLE *) PcieConfigGetChild (DESCRIPTOR_SILICON, &Pcie->Header); + } + return GnbHandle; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get GNB socket ID + * + * + * @param[in] GnbHandle Gnb handle + */ +UINT8 +GnbGetSocketId ( + IN GNB_HANDLE *GnbHandle + ) +{ + return PcieConfigGetParentComplex (GnbHandle)->SocketId; +} + +/*----------------------------------------------------------------------------------------*/ +/* + * Get PCI_ADDR of GNB + * + * + * @param[in] Handle Pointer to GNB_HANDLE + * @retval PCI_ADDR PCI_ADDR of device + */ + +PCI_ADDR +GnbGetHostPciAddress ( + IN GNB_HANDLE *Handle + ) +{ + ASSERT (Handle != NULL); + return Handle->Address; +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.h new file mode 100644 index 0000000..affaa8c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.h @@ -0,0 +1,101 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB function to create/locate PCIe configuration data area + * + * Contain code that create/locate and rebase configuration data area. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _GNBHANDLELIB_H_ +#define _GNBHANDLELIB_H_ + + +GNB_HANDLE * +GnbGetHandle ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +GnbGetSocketId ( + IN GNB_HANDLE *GnbHandle + ); + +PCI_ADDR +GnbGetHostPciAddress ( + IN GNB_HANDLE *Handle + ); + + +#define GnbGetNextHandle(Descriptor) (GNB_HANDLE *) PcieConfigGetNextTopologyDescriptor (Descriptor, DESCRIPTOR_TERMINATE_TOPOLOGY) + +#define GnbGetSiliconId(Handle) (Handle != NULL ? (Handle)->SiliconId : 0) +#define GnbGetNodeId(Handle) (Handle != NULL ? (Handle)->NodeId : 0) + +#define GnbIsGnbConnectedToSb(Handle) (Handle != NULL ? ((Handle)->Address.AddressValue == 0x0) : FALSE) + +#endif + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h new file mode 100644 index 0000000..9074aba --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h @@ -0,0 +1,81 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe configuration + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _GNBPCIECONFIG_H_ +#define _GNBPCIECONFIG_H_ + +#include "GnbPcie.h" +#include "PcieConfigData.h" +#include "PcieConfigLib.h" +#include "GnbHandleLib.h" + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c new file mode 100644 index 0000000..febae7f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c @@ -0,0 +1,561 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB function to create/locate PCIe configuration data area + * + * Contain code that create/locate and rebase configuration data area. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "OptionGnb.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbFamServices.h" +#include "cpuServices.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "PcieMapTopology.h" +#include "PcieInputParser.h" +#include "PcieConfigLib.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; +extern GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +#define PcieConfigAttachChild(P, C) (P)->Child = (UINT16) ((UINT8 *) C - (UINT8 *) P); +#define PcieConfigAttachParent(P, C) (C)->Parent = (UINT16) ((UINT8 *) C - (UINT8 *) P); + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +STATIC +PcieConfigAttachComplexes ( + IN OUT PCIe_COMPLEX_CONFIG *Base, + IN OUT PCIe_COMPLEX_CONFIG *New + ); + +AGESA_STATUS +PcieUpdateConfigurationData ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +PCIe_COMPLEX_DESCRIPTOR * +PcieConfigProcessUserConfig ( + IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PcieConfigurationInit ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PcieConfigurationMap ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Create internal PCIe configuration topology + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_SUCCESS Configuration data successfully allocated. + * @retval AGESA_FATAL Configuration data allocation failed. + */ + +AGESA_STATUS +PcieConfigurationInit ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_SILICON_CONFIG *Silicon; + UINT8 SocketId; + UINTN CurrentComplexesDataLength; + UINTN ComplexesDataLength; + UINT8 ComplexIndex; + VOID *Buffer; + ComplexesDataLength = 0; + Status = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationInit Enter\n"); + for (SocketId = 0; SocketId < GetPlatformNumberOfSockets (); SocketId++) { + if (IsProcessorPresent (SocketId, StdHeader)) { + Status = PcieFmGetComplexDataLength (SocketId, &CurrentComplexesDataLength, StdHeader); + ASSERT (Status == AGESA_SUCCESS); + ComplexesDataLength += CurrentComplexesDataLength; + } + } + ComplexIndex = 0; + Pcie = GnbAllocateHeapBufferAndClear (AMD_PCIE_COMPLEX_DATA_HANDLE, sizeof (PCIe_PLATFORM_CONFIG) + ComplexesDataLength, StdHeader); + ASSERT (Pcie != NULL); + if (Pcie != NULL) { + PcieConfigAttachChild (&Pcie->Header, &Pcie->ComplexList[ComplexIndex].Header); + PcieConfigSetDescriptorFlags (Pcie, DESCRIPTOR_PLATFORM | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_TOPOLOGY); + Buffer = (UINT8 *) (Pcie) + sizeof (PCIe_PLATFORM_CONFIG); + for (SocketId = 0; SocketId < GetPlatformNumberOfSockets (); SocketId++) { + if (IsProcessorPresent (SocketId, StdHeader)) { + Pcie->ComplexList[ComplexIndex].SocketId = SocketId; + //Attache Comples to Silicon which will be created by PcieFmBuildComplexConfiguration + PcieConfigAttachChild (&Pcie->ComplexList[ComplexIndex].Header, &((PCIe_SILICON_CONFIG *) Buffer)->Header); + //Attach Comples to Pcie + PcieConfigAttachParent (&Pcie->Header, &Pcie->ComplexList[ComplexIndex].Header); + PcieConfigSetDescriptorFlags (&Pcie->ComplexList[ComplexIndex], DESCRIPTOR_COMPLEX | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY); + PcieFmBuildComplexConfiguration (SocketId, Buffer, StdHeader); + Silicon = PcieConfigGetChildSilicon (&Pcie->ComplexList[ComplexIndex]); + while (Silicon != NULL) { + PcieConfigAttachParent (&Pcie->ComplexList[ComplexIndex].Header, &Silicon->Header); + GetNodeId (SocketId, Silicon->SiliconId, &Silicon->NodeId, StdHeader); + GnbFmGetLinkId ((GNB_HANDLE*) Silicon, &Silicon->LinkId, StdHeader); + Silicon = (PCIe_SILICON_CONFIG *) PcieConfigGetNextTopologyDescriptor (Silicon, DESCRIPTOR_TERMINATE_TOPOLOGY); + } + + if (ComplexIndex > 0) { + PcieConfigAttachComplexes (&Pcie->ComplexList[ComplexIndex - 1], &Pcie->ComplexList[ComplexIndex]); + } + PcieFmGetComplexDataLength (SocketId, &CurrentComplexesDataLength, StdHeader); + Buffer = (VOID *) ((UINT8 *) Buffer + CurrentComplexesDataLength); + ComplexIndex++; + } + } + } else { + Status = AGESA_FATAL; + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationInit Exit [0x%x]\n", Status); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Create internal PCIe configuration topology + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_SUCCESS Configuration data successfully allocated. + * @retval AGESA_FATAL Configuration data allocation failed. + */ + +AGESA_STATUS +PcieConfigurationMap ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AMD_EARLY_PARAMS *EarlyParamsPtr; + PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; + PCIe_PLATFORM_CONFIG *Pcie; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor; + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + UINTN Index; + UINTN NumberOfComplexes; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationMap Enter\n"); + AgesaStatus = AGESA_SUCCESS; + EarlyParamsPtr = (AMD_EARLY_PARAMS *) StdHeader; + PcieComplexList = PcieConfigProcessUserConfig (EarlyParamsPtr->GnbConfig.PcieComplexList, StdHeader); + GNB_DEBUG_CODE ( + if (PcieComplexList != NULL) { + PcieUserConfigConfigDump (PcieComplexList); + } + ); + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetChild (DESCRIPTOR_COMPLEX, &Pcie->Header); + NumberOfComplexes = PcieInputParserGetNumberOfComplexes (PcieComplexList); + while (Complex != NULL) { + for (Index = 0; Index < NumberOfComplexes; Index++) { + ComplexDescriptor = PcieInputParserGetComplexDescriptor (PcieComplexList, Index); + if (ComplexDescriptor->SocketId == Complex->SocketId) { + Status = PcieMapTopologyOnComplex (ComplexDescriptor, Complex, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } + } + Complex = PcieLibGetNextDescriptor (Complex); + } + } + Pcie->LinkReceiverDetectionPooling = GnbBuildOptions.CfgGnbLinkReceiverDetectionPooling; + Pcie->LinkL0Pooling = GnbBuildOptions.CfgGnbLinkL0Pooling; + Pcie->LinkGpioResetAssertionTime = GnbBuildOptions.CfgGnbLinkGpioResetAssertionTime; + Pcie->LinkResetToTrainingTime = GnbBuildOptions.CfgGnbLinkResetToTrainingTime; + Pcie->GfxCardWorkaround = GfxWorkaroundEnable; + Pcie->TrainingExitState = LinkStateTrainingCompleted; + Pcie->TrainingAlgorithm = GnbBuildOptions.CfgGnbTrainingAlgorithm; + if ((UserOptions.CfgAmdPlatformType & AMD_PLATFORM_MOBILE) != 0) { + Pcie->GfxCardWorkaround = GfxWorkaroundDisable; + } + Pcie->PsppPolicy = EarlyParamsPtr->GnbConfig.PsppPolicy; + IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_PLATFORM_CONFIG, Pcie, StdHeader); + GNB_DEBUG_CODE ( + PcieConfigDebugDump (Pcie); + ); + HeapDeallocateBuffer (AMD_GNB_TEMP_DATA_HANDLE, StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationInit Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Locate global PCIe configuration data + * + * + * + * @param[in] PcieComplexList User PCIe topology configuration + * @param[out] StdHeader Standard configuration header + * @retval Updated topology configuration + */ +PCIe_COMPLEX_DESCRIPTOR * +PcieConfigProcessUserConfig ( + IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Node0SocketId; + UINT32 Node0SiliconId; + UINTN NumberOfComplexes; + UINTN NumberOfPorts; + UINTN Index; + UINT16 DescriptorLoLane; + UINT16 DescriptorHiLane; + PCIe_COMPLEX_DESCRIPTOR *ResultComplexConfig; + PCIe_COMPLEX_DESCRIPTOR *SbComplexDescriptor; + PCIe_PORT_DESCRIPTOR *SbPortDescriptor; + PCIe_PORT_DESCRIPTOR DefaultSbPortDescriptor; + PCIe_ENGINE_DESCRIPTOR *EngineDescriptor; + AGESA_STATUS Status; + SbPortDescriptor = NULL; + GetSocketModuleOfNode (0, &Node0SocketId, &Node0SiliconId, StdHeader); + Status = PcieFmGetSbConfigInfo ((UINT8) Node0SocketId, &DefaultSbPortDescriptor, StdHeader); + if (Status == AGESA_UNSUPPORTED) { + return PcieComplexList; + } + if (PcieComplexList == NULL) { + // No complex descriptor for any silicon was provided + // 1. Create complex descriptor + // 2. Create SB port descriptor + // 3. Attach SB descriptor to complex descriptor created in step #1 + ResultComplexConfig = (PCIe_COMPLEX_DESCRIPTOR *) GnbAllocateHeapBufferAndClear ( + AMD_GNB_TEMP_DATA_HANDLE, + sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR), + StdHeader + ); + SbComplexDescriptor = ResultComplexConfig; + SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8 *) ResultComplexConfig + sizeof (PCIe_COMPLEX_DESCRIPTOR)); + LibAmdMemCopy (SbPortDescriptor, &DefaultSbPortDescriptor, sizeof (PCIe_PORT_DESCRIPTOR), StdHeader); + SbPortDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST; + // Attach post array to complex descriptor + SbComplexDescriptor->PciePortList = SbPortDescriptor; + SbComplexDescriptor->SocketId = Node0SocketId; + SbComplexDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST; + } else { + NumberOfComplexes = PcieInputParserGetNumberOfComplexes (PcieComplexList); + SbComplexDescriptor = PcieInputParserGetComplexDescriptorOfSocket (PcieComplexList, Node0SocketId); + if (SbComplexDescriptor == NULL) { + // No complex descriptor for silicon that have SB attached. + // 1. Create complex descriptor. Will be first one in the list + // 2. Create SB port descriptor + // 3. Attach SB descriptor to complex descriptor created in step #1 + ResultComplexConfig = (PCIe_COMPLEX_DESCRIPTOR *) GnbAllocateHeapBufferAndClear ( + AMD_GNB_TEMP_DATA_HANDLE, + (NumberOfComplexes + 1) * sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR), + StdHeader + ); + SbComplexDescriptor = ResultComplexConfig; + SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8 *) ResultComplexConfig + (NumberOfComplexes + 1) * sizeof (PCIe_COMPLEX_DESCRIPTOR)); + LibAmdMemCopy (SbPortDescriptor, &DefaultSbPortDescriptor, sizeof (PCIe_PORT_DESCRIPTOR), StdHeader); + SbPortDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST; + // Attach post array to complex descriptor + SbComplexDescriptor->PciePortList = SbPortDescriptor; + SbComplexDescriptor->SocketId = Node0SocketId; + SbComplexDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST; + LibAmdMemCopy ( + (UINT8 *) ResultComplexConfig + sizeof (PCIe_COMPLEX_DESCRIPTOR), + PcieComplexList, + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR), + StdHeader + ); + + } else { + // Complex descriptor that represent silicon that have SB attached exist + // 1. Determine if complex have descriptor for SB + // 2. Create new descriptor for SB if needed + NumberOfPorts = PcieInputParserGetLengthOfPcieEnginesList (SbComplexDescriptor); + ResultComplexConfig = (PCIe_COMPLEX_DESCRIPTOR *) GnbAllocateHeapBuffer ( + AMD_GNB_TEMP_DATA_HANDLE, + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR) + (NumberOfPorts + 1) * sizeof (PCIe_PORT_DESCRIPTOR), + StdHeader + ); + // Copy complex descriptor array + LibAmdMemCopy ( + ResultComplexConfig, + PcieComplexList, + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR), + StdHeader + ); + if (NumberOfPorts != 0) { + // Copy port descriptor array associated with complex with SB attached + LibAmdMemCopy ( + (UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR), + SbComplexDescriptor->PciePortList, + NumberOfPorts * sizeof (PCIe_PORT_DESCRIPTOR), + StdHeader + ); + // Update SB complex pointer on in memory list + SbComplexDescriptor = PcieInputParserGetComplexDescriptorOfSocket ((PCIe_COMPLEX_DESCRIPTOR *) ResultComplexConfig, Node0SocketId); + // Attach port descriptor array to complex + SbComplexDescriptor->PciePortList = (PCIe_PORT_DESCRIPTOR *) ((UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR)); + for (Index = 0; Index < NumberOfPorts; ++Index) { + EngineDescriptor = PcieInputParserGetEngineDescriptor (SbComplexDescriptor, Index); + if (EngineDescriptor->EngineData.EngineType == PciePortEngine) { + DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); + DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane); + if (DescriptorLoLane >= DefaultSbPortDescriptor.EngineData.StartLane && DescriptorLoLane <= DefaultSbPortDescriptor.EngineData.EndLane) { + SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) EngineDescriptor; + } + } + } + } + if (SbPortDescriptor == NULL) { + // No descriptor that represent SB where found, create new one, will be first one in list + SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR)); + // Copy default config info + LibAmdMemCopy (SbPortDescriptor, &DefaultSbPortDescriptor, sizeof (PCIe_PORT_DESCRIPTOR), StdHeader); + // Reattach descriptor list to complex + SbComplexDescriptor->PciePortList = SbPortDescriptor; + } else { + // Move SB descriptor to be first one in array + LibAmdMemCopy ( + (UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR), + SbPortDescriptor, + sizeof (PCIe_PORT_DESCRIPTOR), + StdHeader + ); + // Disable original SB descriptor + SbPortDescriptor->EngineData.EngineType = PcieUnusedEngine; + //Update pointer to new SB descriptor + SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR)); + //It is no longer a descriptor that terminates list + SbPortDescriptor->Flags &= (~ DESCRIPTOR_TERMINATE_LIST); + // Reattach descriptor list to complex + SbComplexDescriptor->PciePortList = SbPortDescriptor; + } + } + } + // Mark descriptor as SB link + SbPortDescriptor->Port.MiscControls.SbLink = 0x1; + return ResultComplexConfig; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Locate global PCIe configuration data + * + * + * + * @param[in] StdHeader Standard configuration header + * @param[out] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Configuration data successfully located + * @retval AGESA_FATAL Configuration can not be located. + */ +AGESA_STATUS +PcieLocateConfigurationData ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT PCIe_PLATFORM_CONFIG **Pcie + ) +{ + *Pcie = GnbLocateHeapBuffer (AMD_PCIE_COMPLEX_DATA_HANDLE, StdHeader); + if (*Pcie == NULL) { + IDS_ERROR_TRAP; + return AGESA_FATAL; + } + (*Pcie)->StdHeader = /* (PVOID) */ (UINT32)StdHeader; + PcieUpdateConfigurationData (*Pcie); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Attache descriptors + * + * + * @param[in] Type Descriptor type + * @param[in,out] Base Base descriptor + * @param[in,out] New New descriptor + */ +VOID +STATIC +PcieConfigAttachDescriptors ( + IN UINT32 Type, + IN OUT PCIe_DESCRIPTOR_HEADER *Base, + IN OUT PCIe_DESCRIPTOR_HEADER *New + ) +{ + PCIe_DESCRIPTOR_HEADER *Left; + PCIe_DESCRIPTOR_HEADER *Right; + + Left = PcieConfigGetPeer (DESCRIPTOR_TERMINATE_GNB, PcieConfigGetChild (Type, Base)); + ASSERT (Left != NULL); + Right = PcieConfigGetChild (Type, New); + Left->Peer = (UINT16) ((UINT8 *) Right - (UINT8 *) Left); + PcieConfigResetDescriptorFlags (Left, DESCRIPTOR_TERMINATE_TOPOLOGY); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Attach configurations of two GNB to each other. + * + * Function will link all data structure to linked lists + * + * @param[in,out] Base Base complex descriptor + * @param[in,out] New New complex descriptor + */ +VOID +STATIC +PcieConfigAttachComplexes ( + IN OUT PCIe_COMPLEX_CONFIG *Base, + IN OUT PCIe_COMPLEX_CONFIG *New + ) +{ + // Connect Complex + Base->Header.Peer = (UINT16) ((UINT8 *) New - (UINT8 *) Base); + PcieConfigResetDescriptorFlags (Base, DESCRIPTOR_TERMINATE_TOPOLOGY); + // Connect Silicon + PcieConfigAttachDescriptors (DESCRIPTOR_SILICON, &Base->Header, &New->Header); + // Connect Wrappers + PcieConfigAttachDescriptors (DESCRIPTOR_PCIE_WRAPPER | DESCRIPTOR_DDI_WRAPPER, &Base->Header, &New->Header); + // Connect Engines + PcieConfigAttachDescriptors (DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_DDI_ENGINE, &Base->Header, &New->Header); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Update configuration data + * + * Puprouse of this structure to update config data that base on programming of + * other silicon compoments. For instance PCI address of GNB and PCIe ports + * can change by AGESA or external agent + * + * + * @param[in,out] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Configuration data successfully update + * @retval AGESA_FATAL Failt to update configuration + */ +AGESA_STATUS +PcieUpdateConfigurationData ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_SILICON_CONFIG *Silicon; + PCIe_ENGINE_CONFIG *Engine; + PCI_ADDR NewAddress; + // Update silicon configuration + Silicon = PcieConfigGetChildSilicon (Pcie); + while (Silicon != NULL) { + NewAddress = GnbFmGetPciAddress ((GNB_HANDLE *) PcieConfigGetParentComplex (Silicon), GnbLibGetHeader (Pcie)); + if (Silicon->Address.AddressValue != NewAddress.AddressValue) { + Silicon->Address.AddressValue = NewAddress.AddressValue; + Engine = PcieConfigGetChildEngine (Silicon); + while (Engine != NULL) { + if (PcieConfigIsPcieEngine (Engine)) { + Engine->Type.Port.Address.Address.Bus = Silicon->Address.Address.Bus; + } + Engine = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (Engine, DESCRIPTOR_TERMINATE_GNB); + } + } + Silicon = (PCIe_SILICON_CONFIG *) PcieConfigGetNextTopologyDescriptor (Silicon, DESCRIPTOR_TERMINATE_TOPOLOGY); + } + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h new file mode 100644 index 0000000..063d408 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h @@ -0,0 +1,84 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB function to create/locate PCIe configuration data area + * + * Contain code that create/locate and rebase configuration data area. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 63425 $ @e $Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +#ifndef _PCIECONFIGDATA_H_ +#define _PCIECONFIGDATA_H_ + + +AGESA_STATUS +PcieLocateConfigurationData ( + IN AMD_CONFIG_PARAMS *StdHeader, + OUT PCIe_PLATFORM_CONFIG **Pcie + ); + +#endif + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c new file mode 100644 index 0000000..0083e80 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c @@ -0,0 +1,827 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB function to create/locate PCIe configuration data area + * + * Contain code that create/locate and rebase configuration data area. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision: 65589 $ @e $Date: 2012-02-19 20:32:29 -0600 (Sun, 19 Feb 2012) $ + * + */ +/* +***************************************************************************** +* +* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* AMD is granting you permission to use this software (the Materials) +* pursuant to the terms and conditions of your Software License Agreement +* with AMD. This header does *NOT* give you permission to use the Materials +* or any rights under AMD's intellectual property. Your use of any portion +* of these Materials shall constitute your acceptance of those terms and +* conditions. If you do not agree to the terms and conditions of the Software +* License Agreement, please do not use any portion of these Materials. +* +* CONFIDENTIALITY: The Materials and all other information, identified as +* confidential and provided to you by AMD shall be kept confidential in +* accordance with the terms and conditions of the Software License Agreement. +* +* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +* THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +* THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +* +* AMD does not assume any responsibility for any errors which may appear in +* the Materials or any other related information provided to you by AMD, or +* result from use of the Materials or any related information. +* +* You agree that you will not reverse engineer or decompile the Materials. +* +* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +* further information, software, technical information, know-how, or show-how +* available to you. Additionally, AMD retains the right to modify the +* Materials at any time, without notice, and is not obligated to provide such +* modified Materials to you. +* +* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +* subject to the restrictions as set forth in FAR 52.227-14 and +* DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +* Government constitutes acknowledgement of AMD's proprietary rights in them. +* +* EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +* direct product thereof will be exported directly or indirectly, into any +* country prohibited by the United States Export Administration Act and the +* regulations thereunder, without the required authorization from the U.S. +* government nor will be used for any purpose prohibited by the same. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "PcieMapTopology.h" +#include "PcieInputParser.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * get Master Lane of PCIe port engine + * + * + * + * @param[in] Engine Pointer to engine descriptor + * @retval Master Engine Lane Number + */ +UINT8 +PcieConfigGetPcieEngineMasterLane ( + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + UINT8 MasterLane; + PCIe_WRAPPER_CONFIG *Wrapper; + ASSERT (PcieConfigIsPcieEngine (Engine)); + + Wrapper = PcieConfigGetParentWrapper (Engine); + if (Engine->EngineData.StartLane <= Engine->EngineData.EndLane) { + MasterLane = (UINT8) (Engine->EngineData.StartLane - Wrapper->StartPhyLane); + } else { + MasterLane = (UINT8) (Engine->EngineData.EndLane - Wrapper->StartPhyLane); + } + return MasterLane; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get number of core lanes + * + * + * + * @param[in] Engine Pointer to engine descriptor + * @retval Number of core lane + */ +UINT8 +PcieConfigGetNumberOfCoreLane ( + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + if (Engine->Type.Port.StartCoreLane >= UNUSED_LANE_ID || Engine->Type.Port.EndCoreLane >= UNUSED_LANE_ID) { + return 0; + } + return (UINT8) (Engine->Type.Port.EndCoreLane - Engine->Type.Port.StartCoreLane + 1); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Disable engine + * + * + * + * @param[in] Engine Pointer to engine config descriptor + */ +VOID +PcieConfigDisableEngine ( + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + if (PcieConfigIsSbPcieEngine (Engine)) { + return; + } + PcieConfigResetDescriptorFlags (Engine, DESCRIPTOR_ALLOCATED); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Disable all engines on wrapper + * + * + * + * @param[in] EngineTypeMask Engine type bitmap. + * @param[in] Wrapper Pointer to wrapper config descriptor + */ +VOID +PcieConfigDisableAllEngines ( + IN UINTN EngineTypeMask, + IN PCIe_WRAPPER_CONFIG *Wrapper + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + EngineList = PcieConfigGetChildEngine (Wrapper); + while (EngineList != NULL) { + if ((EngineList->EngineData.EngineType & EngineTypeMask) != 0) { + PcieConfigDisableEngine (EngineList); + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get engine PHY lanes bitmap + * + * + * + * @param[in] Engine Pointer to engine config descriptor + */ +UINT32 +PcieConfigGetEnginePhyLaneBitMap ( + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + UINT32 LaneBitMap; + LaneBitMap = 0; + if (PcieLibIsEngineAllocated (Engine)) { + LaneBitMap = ((1 << PcieConfigGetNumberOfPhyLane (Engine)) - 1) << (PcieLibGetLoPhyLane (Engine) - PcieConfigGetParentWrapper (Engine)->StartPhyLane); + } + return LaneBitMap; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get number of phy lanes + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @retval Number of Phy lane + */ +UINT8 +PcieConfigGetNumberOfPhyLane ( + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.StartLane >= UNUSED_LANE_ID) { + return 0; + } + if (Engine->EngineData.StartLane > Engine->EngineData.EndLane) { + return (UINT8) (Engine->EngineData.StartLane - Engine->EngineData.EndLane + 1); + } else { + return (UINT8) (Engine->EngineData.EndLane - Engine->EngineData.StartLane + 1); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get port configuration signature for given wrapper and core + * + * Support for unify register access through index/data pair on GNB + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] CoreId Core ID + * @retval Configuration Signature + */ +UINT64 +PcieConfigGetConfigurationSignature ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 CoreId + ) +{ + UINT64 ConfigurationSignature; + PCIe_ENGINE_CONFIG *EngineList; + ConfigurationSignature = 0; + EngineList = PcieConfigGetChildEngine (Wrapper); + while (EngineList != NULL) { + if (PcieConfigIsPcieEngine (EngineList) && EngineList->Type.Port.CoreId == CoreId) { + ConfigurationSignature = (ConfigurationSignature << 8) | PcieConfigGetNumberOfCoreLane (EngineList); + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + return ConfigurationSignature; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Check Port Status + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in] PortStatus Check if status asserted for port + * @retval TRUE if status asserted + */ +BOOLEAN +PcieConfigCheckPortStatus ( + IN PCIe_ENGINE_CONFIG *Engine, + IN UINT32 PortStatus + ) +{ + return (Engine->InitStatus & PortStatus) == 0 ? FALSE : TRUE; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set/Reset port status + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in] SetStatus SetStatus + * @param[in] ResetStatus ResetStatus + * + */ +UINT16 +PcieConfigUpdatePortStatus ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_ENGINE_INIT_STATUS SetStatus, + IN PCIe_ENGINE_INIT_STATUS ResetStatus + ) +{ + Engine->InitStatus |= SetStatus; + Engine->InitStatus &= (~ResetStatus); + return Engine->InitStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Execute callback on all descriptor of specific type + * + * + * @param[in] InDescriptorFlags Include descriptor flags + * @param[in] OutDescriptorFlags Exlude descriptor flags + * @param[in] TerminationFlags Termination flags + * @param[in] Callback Pointer to callback function + * @param[in, out] Buffer Pointer to buffer to pass information to callback + * @param[in] Pcie Pointer to global PCIe configuration + */ + +AGESA_STATUS +PcieConfigRunProcForAllDescriptors ( + IN UINT32 InDescriptorFlags, + IN UINT32 OutDescriptorFlags, + IN UINT32 TerminationFlags, + IN PCIe_RUN_ON_DESCRIPTOR_CALLBACK Callback, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_DESCRIPTOR_HEADER *Descriptor; + + AgesaStatus = AGESA_SUCCESS; + Descriptor = PcieConfigGetChild (InDescriptorFlags & DESCRIPTOR_ALL_TYPES, &Pcie->Header); + while (Descriptor != NULL) { + if ((InDescriptorFlags & Descriptor->DescriptorFlags) != 0 && (OutDescriptorFlags && Descriptor->DescriptorFlags) == 0) { + Status = Callback (Descriptor, Buffer, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } + Descriptor = (PCIe_DESCRIPTOR_HEADER *) PcieConfigGetNextTopologyDescriptor (Descriptor, TerminationFlags); + } + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Execute callback on all wrappers in topology + * + * + * @param[in] DescriptorFlags Wrapper Flags + * @param[in] Callback Pointer to callback function + * @param[in, out] Buffer Pointer to buffer to pass information to callback + * @param[in] Pcie Pointer to global PCIe configuration + */ + +AGESA_STATUS +PcieConfigRunProcForAllWrappers ( + IN UINT32 DescriptorFlags, + IN PCIe_RUN_ON_WRAPPER_CALLBACK Callback, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_WRAPPER_CONFIG *Wrapper; + + AgesaStatus = AGESA_SUCCESS; + Wrapper = (PCIe_WRAPPER_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_WRAPPERS, &Pcie->Header); + while (Wrapper != NULL) { + if (!(PcieLibIsVirtualDesciptor (Wrapper) && (DescriptorFlags & DESCRIPTOR_VIRTUAL) == 0)) { + if ((DescriptorFlags & DESCRIPTOR_ALL_WRAPPERS & Wrapper->Header.DescriptorFlags) != 0) { + Status = Callback (Wrapper, Buffer, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } + } + Wrapper = (PCIe_WRAPPER_CONFIG *) PcieConfigGetNextTopologyDescriptor (Wrapper, DESCRIPTOR_TERMINATE_TOPOLOGY); + } + return AgesaStatus; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Execute callback on all engine in topology + * + * + * @param[in] DescriptorFlags Engine flags. + * @param[in] Callback Pointer to callback function + * @param[in, out] Buffer Pointer to buffer to pass information to callback + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PcieConfigRunProcForAllEngines ( + IN UINT32 DescriptorFlags, + IN PCIe_RUN_ON_ENGINE_CALLBACK Callback, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + + PCIe_ENGINE_CONFIG *Engine; + Engine = (PCIe_ENGINE_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_ENGINES, &Pcie->Header); + while (Engine != NULL) { + if (!(PcieLibIsVirtualDesciptor (Engine) && (DescriptorFlags & DESCRIPTOR_VIRTUAL) == 0)) { + if (!((DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0 && !PcieLibIsEngineAllocated (Engine))) { + if ((Engine->Header.DescriptorFlags & DESCRIPTOR_ALL_ENGINES & DescriptorFlags) != 0) { + Callback (Engine, Buffer, Pcie); + } + } + } + Engine = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (Engine, DESCRIPTOR_TERMINATE_TOPOLOGY); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get parent descriptor of specific type + * + * + * @param[in] Type Descriptor type + * @param[in] Descriptor Pointer to buffer to pass information to callback + */ +PCIe_DESCRIPTOR_HEADER * +PcieConfigGetParent ( + IN UINT32 Type, + IN PCIe_DESCRIPTOR_HEADER *Descriptor + ) +{ + while ((Descriptor->DescriptorFlags & Type) == 0) { + if (Descriptor->Parent != 0) { + Descriptor = (PCIe_DESCRIPTOR_HEADER *) ((UINT8 *) Descriptor - Descriptor->Parent); + } else { + return NULL; + } + } + return Descriptor; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get child descriptor of specific type + * + * + * @param[in] Type Descriptor type + * @param[in] Descriptor Pointer to buffer to pass information to callback + */ +PCIe_DESCRIPTOR_HEADER * +PcieConfigGetChild ( + IN UINT32 Type, + IN PCIe_DESCRIPTOR_HEADER *Descriptor + ) +{ + while ((Descriptor->DescriptorFlags & Type) == 0) { + if (Descriptor->Child != 0) { + Descriptor = (PCIe_DESCRIPTOR_HEADER *) ((UINT8 *) Descriptor + Descriptor->Child); + } else { + return NULL; + } + } + return Descriptor; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get peer descriptor of specific type + * + * + * @param[in] Type Descriptor type + * @param[in] Descriptor Pointer to buffer to pass information to callback + */ +PCIe_DESCRIPTOR_HEADER * +PcieConfigGetPeer ( + IN UINT32 Type, + IN PCIe_DESCRIPTOR_HEADER *Descriptor + ) +{ + ASSERT (Descriptor != NULL); + while ((Descriptor->DescriptorFlags & Type) == 0) { + if (Descriptor->Peer != 0) { + Descriptor = (PCIe_DESCRIPTOR_HEADER *) ((UINT8 *) Descriptor + Descriptor->Peer); + } else { + return NULL; + } + } + return Descriptor; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Check is engine is active or potentially active + * + * + * + * @param[in] Engine Pointer to engine descriptor + * @retval TRUE - engine active + * @retval FALSE - engine not active + */ +BOOLEAN +PcieConfigIsActivePcieEngine ( + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + BOOLEAN Result; + ASSERT (PcieConfigIsPcieEngine (Engine)); + Result = FALSE; + if (PcieConfigIsEngineAllocated (Engine)) { + if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || + (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled && Engine->Type.Port.PortData.LinkHotplug != HotplugInboard)) { + Result = TRUE; + } + } + return Result; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Locate SB engine on wrapper + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @retval SB engine pointer or NULL + */ +PCIe_ENGINE_CONFIG * +PcieConfigLocateSbEngine ( + IN PCIe_WRAPPER_CONFIG *Wrapper + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + EngineList = PcieConfigGetChildEngine (Wrapper); + while (EngineList != NULL) { + if (PcieConfigIsSbPcieEngine (EngineList)) { + return EngineList; + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + return NULL; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Helper function to dump engine configuration + * + * + * @param[in] EngineList Engine Configuration + */ +VOID +PcieConfigEngineDebugDump ( + IN PCIe_ENGINE_CONFIG *EngineList + ) +{ + IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", EngineList->Header.DescriptorFlags); + IDS_HDT_CONSOLE (PCIE_MISC, " Engine Type - %s\n Start Phy Lane - %d\n End Phy Lane - %d\n", + ((EngineList->EngineData.EngineType == PciePortEngine) ? "PCIe Port" : "DDI Link"), + EngineList->EngineData.StartLane, + EngineList->EngineData.EndLane + ); + IDS_HDT_CONSOLE (PCIE_MISC, " Scrath - %d\n", EngineList->Scratch); + IDS_HDT_CONSOLE (PCIE_MISC, " Init Status - 0x%08x\n", EngineList->InitStatus); + if (PcieLibIsPcieEngine (EngineList)) { + IDS_HDT_CONSOLE (PCIE_MISC, " PCIe port configuration:\n"); + IDS_HDT_CONSOLE (PCIE_MISC, " Port Training - %s\n", + (EngineList->Type.Port.PortData.PortPresent == PortDisabled) ? "Disable" : "Enabled" + ); + IDS_HDT_CONSOLE (PCIE_MISC, " Start Core Lane - %d\n", EngineList->Type.Port.StartCoreLane); + IDS_HDT_CONSOLE (PCIE_MISC, " End Core Lane - %d\n", EngineList->Type.Port.EndCoreLane); + IDS_HDT_CONSOLE (PCIE_MISC, " Requested PCI Dev Number - %d\n",EngineList->Type.Port.PortData.DeviceNumber); + IDS_HDT_CONSOLE (PCIE_MISC, " Requested PCI Func Number - %d\n",EngineList->Type.Port.PortData.FunctionNumber); + IDS_HDT_CONSOLE (PCIE_MISC, " PCI Address - %d:%d:%d\n", + EngineList->Type.Port.Address.Address.Bus, + EngineList->Type.Port.Address.Address.Device, + EngineList->Type.Port.Address.Address.Function + ); + IDS_HDT_CONSOLE (PCIE_MISC, " Misc Control - 0x%02x\n", EngineList->Type.Port.PortData.MiscControls); + IDS_HDT_CONSOLE (PCIE_MISC, " Native PCI Dev Number - %d\n", EngineList->Type.Port.NativeDevNumber); + IDS_HDT_CONSOLE (PCIE_MISC, " Native PCI Func Number - %d\n", EngineList->Type.Port.NativeFunNumber); + IDS_HDT_CONSOLE (PCIE_MISC, " Hotplug - %s\n", + (EngineList->Type.Port.PortData.LinkHotplug == HotplugDisabled) ? "Disabled" : ( + (EngineList->Type.Port.PortData.LinkHotplug == HotplugBasic) ? "Basic" : ( + (EngineList->Type.Port.PortData.LinkHotplug == HotplugServer) ? "Server" : ( + (EngineList->Type.Port.PortData.LinkHotplug == HotplugEnhanced) ? "Enhanced" : ( + (EngineList->Type.Port.PortData.LinkHotplug == HotplugInboard) ? "Inboard" : "Unknown")))) + ); + ASSERT (EngineList->Type.Port.PortData.LinkHotplug < MaxHotplug); + IDS_HDT_CONSOLE (PCIE_MISC, " ASPM - %s\n", + (EngineList->Type.Port.PortData.LinkAspm == AspmDisabled) ? "Disabled" : ( + (EngineList->Type.Port.PortData.LinkAspm == AspmL0s) ? "L0s" : ( + (EngineList->Type.Port.PortData.LinkAspm == AspmL1) ? "L1" : ( + (EngineList->Type.Port.PortData.LinkAspm == AspmL0sL1) ? "L0s & L1" : "Unknown"))) + ); + ASSERT (EngineList->Type.Port.PortData.LinkAspm < MaxAspm); + IDS_HDT_CONSOLE (PCIE_MISC, " Speed - %d\n", + EngineList->Type.Port.PortData.LinkSpeedCapability + ); + } else { + IDS_HDT_CONSOLE (PCIE_MISC, " DDI configuration:\n"); + IDS_HDT_CONSOLE (PCIE_MISC, " Connector - %s\n", + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDP) ? "DP" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDP) ? "eDP" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeSingleLinkDVI) ? "Single Link DVI" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDualLinkDVI) ? "Dual Link DVI" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeHDMI) ? "HDMI" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeTravisDpToVga) ? "Travis DP-to-VGA" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeTravisDpToLvds) ? "Travis DP-to-LVDS" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeLvds) ? "LVDS" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeNutmegDpToVga) ? "Hudson-2 Nutmeg DP-to-VGA" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeSingleLinkDviI) ? "Single Link DVI-I" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeCrt) ? "CRT" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDPToLvds) ? "eDP To Lvds" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDPToRealtecLvds) ? "Realtec eDP To Lvds" : ( + (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeAutoDetect) ? "Autodetect" : "Unknown"))))))))))))) + ); + ASSERT (EngineList->Type.Ddi.DdiData.ConnectorType < MaxConnectorType); + IDS_HDT_CONSOLE (PCIE_MISC, " Aux - Aux%d\n", EngineList->Type.Ddi.DdiData.AuxIndex + 1); + ASSERT (EngineList->Type.Ddi.DdiData.AuxIndex < MaxAux); + IDS_HDT_CONSOLE (PCIE_MISC, " Hdp - Hdp%d\n", EngineList->Type.Ddi.DdiData.HdpIndex + 1); + ASSERT (EngineList->Type.Ddi.DdiData.HdpIndex < MaxHdp); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Helper function to dump wrapper configuration + * + * + * @param[in] WrapperList Wrapper Configuration + */ +VOID +PcieConfigWrapperDebugDump ( + IN PCIe_WRAPPER_CONFIG *WrapperList + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + IDS_HDT_CONSOLE (PCIE_MISC, " <---------Wrapper - %s Config -------->\n", + PcieFmDebugGetWrapperNameString (WrapperList) + ); + IDS_HDT_CONSOLE (PCIE_MISC, " Start PHY lane - %02d\n", WrapperList->StartPhyLane); + IDS_HDT_CONSOLE (PCIE_MISC, " End PHY lane - %02d\n", WrapperList->EndPhyLane); + IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", WrapperList->