[coreboot] suspend/resume in v3

[Peter Stuge]

Discussing on IRC, ruik pointed out that we of course have to
consider suspend and resume in v3.

He wrote some great pointers on the topic today and I'm pasting here
for archival and as food for thought.

<ruik> CareBear: the S3 works this way:
<ruik> 1) get the wakeup info from chipset
<ruik> 2) in intraphase ask the memory to go out of self refresh (skip train)
<ruik> 3) do coreboot chipset init as usual
<ruik> 4) when creating ACPI tables look to that place, in one table there will be OS waking vector
<ruik> 5) after all done, jump to OS instead of payload, switch A20 on go to real mode and jump
<ruik> 6) do this all steps in reserved memory, do not corrupt system memory used by OS
<ruik> 7) minor fix for ACPI dsdt is needed, just one line ;)
<ruik> CareBear: just add one line to SLP
<ruik> similar to bit for S5 and S0
<ruik> one more caveat
<ruik> make sure that suspend signal clock from SB is understood by superIO
<ruik> so superIO wont cut RAM power

I think 6) in particular deserves some consideration.

//Peter