On 6/6/10 6:29 PM, Rudolf Marek wrote:
Afaik it's "ECC clearing" which is implemented several times in the tree, including stage2.
Nope, the APs can init the memory controller too. Check CONFIG_MEM_TRAIN_SEQ 0 for BSP only 1 = train_ram_on_node is called from init_cpus 2 = dunno - looks like it is also done in parallel but I could not find how it works.
Lot of boards sets it up for 2 a think only one to 1
I think 2 is for calling it from CAR..
Still wondering how much time we save by parallelizing this... Did anyone take a measurement?