Quoting joe@smittys.pointclark.net:
Quoting joe@smittys.pointclark.net:
OK, I have a new booting problem. LB dies on the i82801xx_enable_ioapic() function in 82801xx_lpc.c:
void i82801xx_enable_ioapic(struct device *dev) { uint32_t reg32; volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000; volatile uint32_t *ioapic_data = (volatile uint32_t *)0xfec00010;
reg32 = pci_read_config32(dev, GEN_CNTL); reg32 |= (3 << 7); /* Enable IOAPIC */ reg32 |= (1 << 13); /* Coprocessor error enable */ reg32 |= (1 << 1); /* Delayed transaction enable */ reg32 |= (1 << 2); /* DMA collection buffer enable */ pci_write_config32(dev, GEN_CNTL, reg32); printk_debug("IOAPIC Southbridge enabled %x\n", reg32);
*ioapic_index = 0; *ioapic_data = (1 << 25);
*ioapic_index = 0; reg32 = *ioapic_data; printk_debug("Southbridge APIC ID = %x\n", reg32); if (reg32 != (1 << 25)) die("APIC Error\n");
/* TODO: From i82801ca, needed/useful on other ICH? */ *ioapic_index = 3; // Select Boot Configuration register *ioapic_data = 1; // Use Processor System Bus to deliver interrupts }
Initializing devices... Root Device init PCI: 00:00.0 init Northbridge init PCI: 00:1d.0 init PCI: 00:1d.1 init PCI: 00:1d.2 init PCI: 00:1d.7 init EHCI: Setting up controller.. done. PCI: 00:1e.0 init PCI: 00:1f.0 init IOAPIC Southbridge enabled 2186 Southbridge APIC ID = 0 APIC Error
What is going on here? Why is *ioapic_data coming back as 0x0 after it has been set to 0x2000000 (1 << 25)? Help?
Hmm. Could this be because *ioapic_data is not able to use the memory space at 0xfec00010?? I also noticed in the bootlog the AC'97 Audio Controller is using this memory space:
PCI: 00:1f.0 assign_resources, bus 0 link: 0 PCI: 00:1f.5 1c <- [0x00fec00000 - 0x00fec000ff] mem
Could this be causing the issue? If so how would I tell the AC'97 Audio Controller to use a different memory space?
Yup I was right, I disabled the AC'97 Audio Controller and it booted right up. Now I just have to figure out why the ac'97 audio is using this memory space and how to chage it. Anyone....Help?
Thanks - Joe
Initializing devices... Root Device init PCI: 00:00.0 init Northbridge init PCI: 00:1d.0 init PCI: 00:1d.1 init PCI: 00:1d.2 init PCI: 00:1d.7 init EHCI: Setting up controller.. done. PCI: 00:1e.0 init PCI: 00:1f.0 init IOAPIC Southbridge enabled 2186 Southbridge APIC ID = 2000000 Set power on if power fails RTC Init PNP: 002e.4 init PNP: 002e.7 init PCI: 00:1f.1 init IDE0 IDE1 PCI: 00:1f.3 init Devices initialized Copying IRQ routing tables to 0xf0000...done. Verifing copy of IRQ routing tables at 0xf0000...done Checking IRQ routing table consistency... check_pirq_routing_table() - irq_routing_table located at: 0x000f0000 done. Moving GDT to 0x500...ok Adjust low_table_end from 0x00000530 to 0x00001000 Adjust rom_table_end from 0x000f0400 to 0x00100000 Wrote linuxbios table at: 00000530 - 000006d8 checksum 7e74
Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3