David Hendricks (dhendrix@chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2351
-gerrit
commit 8421155b4dfc076339bee9405bd68f4a73bc4a1e Author: David Hendricks dhendrix@chromium.org Date: Sun Feb 10 15:50:20 2013 -0800
armv7/exynos5250/snow: deprecate CONFIG_{RAMBASE,RAMTOP}
RAMBASE and RAMTOP are leftovers from the x86 port and do not apply the same way on ARM platforms. On x86 they refer to the low memory region where coreboot tables reside.
However on ARM we don't have such a region which is architecturally defined. So instead we'll use the CPU-defined DRAM base address and the mainboard-defined DRAM size.
This also has the pleasant side-effect of fixing the coreboot tables to not clobber ramstage code...
Change-Id: I5548ecf05e82f9d9ecec8548fabdd99cc1e39c3b Signed-off-by: David Hendricks dhendrix@chromium.org --- src/arch/armv7/coreboot_ram.ld | 7 +------ src/cpu/samsung/exynos5250/Kconfig | 9 ++------- src/mainboard/google/snow/ramstage.c | 8 +++++--- 3 files changed, 8 insertions(+), 16 deletions(-)
diff --git a/src/arch/armv7/coreboot_ram.ld b/src/arch/armv7/coreboot_ram.ld index c69499c..0644e36 100644 --- a/src/arch/armv7/coreboot_ram.ld +++ b/src/arch/armv7/coreboot_ram.ld @@ -26,7 +26,7 @@ ENTRY(_start)
SECTIONS { - . = CONFIG_RAMBASE; + . = CONFIG_SYS_SDRAM_BASE; /* First we place the code and read only data (typically const declared). * This could theoretically be placed in rom. */ @@ -123,11 +123,6 @@ SECTIONS _ram_seg = _text; _eram_seg = _eheap;
- /* CONFIG_RAMTOP is the upper address of cached memory (among other - * things). We must not exceed beyond that address, there be dragons. - */ - _bogus = ASSERT( ( _eram_seg < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP"); - /* Discard the sections we don't need/want */
/DISCARD/ : { diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index f62195a..2869d76 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -90,11 +90,6 @@ config SYS_TEXT_BASE hex "Executable code section" default 0x43e00000
-config RAMBASE +config COREBOOT_TABLES_SIZE hex - default SYS_SDRAM_BASE -# according to stefan, this is RAMBASE + 1M. -config RAMTOP - hex - default 0x40100000 - + default 0x100000 diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index d280dbe..b779999 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -30,9 +30,11 @@ void main(void) printk(BIOS_INFO, "hello from ramstage\n");
#if CONFIG_WRITE_HIGH_TABLES - /* Leave some space for ACPI tables */ - high_tables_base = CONFIG_RAMBASE; - high_tables_size = CONFIG_RAMBASE + 0x100000; + /* place at top of physical memory */ + high_tables_size = CONFIG_COREBOOT_TABLES_SIZE; + high_tables_base = CONFIG_SYS_SDRAM_BASE + + ((CONFIG_DRAM_SIZE_MB * 1024) * CONFIG_NR_DRAM_BANKS) - + CONFIG_COREBOOT_TABLES_SIZE; #endif
hardwaremain(0);