On Mon, Sep 2, 2019 at 1:31 PM Patrick Georgi via coreboot email@example.com wrote:
On Mon, Sep 02, 2019 at 02:50:15PM +1000, Benjamin Doron wrote:
c) The fans spin up to high and then it stays that way. It does nothing else. The display is dark too.
The display is approximately the last thing you'll get to work. Find yourself some serial console connection to use (I think RasPis can be used as EHCI debug port device) or use our flash console feature (which might be less reliable, so this should be a backup or last resort option) to figure out how far coreboot gets.
coreboot can also use a FTDI FT232H or FT2232H USB board to output debug logs via usbdebug. Note that they must be FT232*H*, and not FT232*R*, for it to work. You would also need an USB to UART (not RS232) adapter to connect the FTDI board to a computer to actually read the log.
Now, in all honesty I should have tried first without cleaning Intel ME but I find it so much more likely that I did something wrong than that cleaning ME was the sole problem.
Tampering with the ME firmware certainly won't help ;-)
Indeed. This can cause bugs that nobody knows why they would happen. For instance, the ME configures clocking-related parameters, which it might not do when its firmware is crippled by e.g. me_cleaner. This can cause lots of weird bugs, such as the LPC bus not working.
Can anyone advise me on how to continue? My code is here: https://github.com/benjamindoron/coreboot
I don't have more to add, except wishing you good luck with your endeavour :-)
I see this is a Skylake laptop... Laptops are usually harder to port because of the limited debug capabilities and the custom and usually undocumented embedded controller (referred to as EC). I would suggest trying to find documentation for your mainboard (schematics and boardviews are the most useful resources) on the Internet.
You should know that coreboot on Skylake uses a FSP binary. I see you're using the older FSP 1.1, I would suggest using the Kaby Lake FSP 2.0 (compatible with Skylake) since more people know about / use it (harder to run into unknown bugs).
I would recommend using coreboot's Gerrit code collaboration tool  to work on your board port, as it's much easier (at least for me) to suggest modifications on there. Plus, changes get merged through Gerrit, so having your change there is already a step forward :)
You are now probably wondering how to do that. It should be explained in .
PS: Your follow-up email with a coreboot binary ended up in the moderation queue and I rejected it: Please be mindful about user's mailboxes before broadcasting a multi-megabytes image to the world :-)
I think it's easier to review coreboot source code than binary coreboot images :D