joe@smittys.pointclark.net wrote:
OK, I have a new booting problem. LB dies on the i82801xx_enable_ioapic() function in 82801xx_lpc.c:
void i82801xx_enable_ioapic(struct device *dev) { uint32_t reg32; volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000; volatile uint32_t *ioapic_data = (volatile uint32_t *)0xfec00010;
reg32 = pci_read_config32(dev, GEN_CNTL); reg32 |= (3 << 7); /* Enable IOAPIC */ reg32 |= (1 << 13); /* Coprocessor error enable */ reg32 |= (1 << 1); /* Delayed transaction enable */ reg32 |= (1 << 2); /* DMA collection buffer enable */ pci_write_config32(dev, GEN_CNTL, reg32); printk_debug("IOAPIC Southbridge enabled %x\n", reg32);
*ioapic_index = 0; *ioapic_data = (1 << 25);
*ioapic_index = 0; reg32 = *ioapic_data; printk_debug("Southbridge APIC ID = %x\n", reg32); if (reg32 != (1 << 25)) die("APIC Error\n");
/* TODO: From i82801ca, needed/useful on other ICH? */ *ioapic_index = 3; // Select Boot Configuration register *ioapic_data = 1; // Use Processor System Bus to deliver interrupts }
Initializing devices... Root Device init PCI: 00:00.0 init Northbridge init PCI: 00:1d.0 init PCI: 00:1d.1 init PCI: 00:1d.2 init PCI: 00:1d.7 init EHCI: Setting up controller.. done. PCI: 00:1e.0 init PCI: 00:1f.0 init IOAPIC Southbridge enabled 2186 Southbridge APIC ID = 0 APIC Error
What is going on here? Why is *ioapic_data coming back as 0x0 after it has been set to 0x2000000 (1 << 25)? Help?
Thanks - Joe
I'm headed to bed, but check the datasheets and make sure that register isn't set to read only unless some other bit is set (does reading it back confirm that it gets set correctly?). Also make sure you have enable_lapic() somewhere, and CONFIG_IOAPIC in mainboard Options.lb. Coprocessor error enable should also be commented out or controlled by #if CONFIG_SMP.
-Corey