Zheng Bao (zheng.bao@amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1880
-gerrit
commit e833ee21e8371aec8d788bd586cb632da5d707cd Author: Zheng Bao fishbaozi@gmail.com Date: Fri Dec 14 15:58:15 2012 +0800
USBDEBUG: Enable the EHCI in AMD Southbridge
Since SB800, USB2.0 debug port is dev 0x12, func 2.
Change-Id: Ie0e33cb2f0833b0baeef81323e1a0634242fbe55 Signed-off-by: Zheng Bao zheng.bao@amd.com Signed-off-by: zbao fishbaozi@gmail.com --- src/southbridge/amd/agesa/hudson/Makefile.inc | 3 ++- src/southbridge/amd/agesa/hudson/enable_usbdebug.c | 8 ++++++-- src/southbridge/amd/cimx/sb800/Makefile.inc | 3 +++ src/southbridge/amd/sb800/enable_usbdebug.c | 8 ++++++-- 4 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 0d4b739..c9a1731 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -9,7 +9,8 @@ ramstage-y += pci.c ramstage-y += pcie.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c ramstage-y += reset.c -romstage-y += enable_usbdebug.c +romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c +ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_setup.c
ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c index c558a26..85ac8d7 100644 --- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c @@ -45,8 +45,12 @@ void set_debug_port(unsigned int port)
void enable_usbdebug(unsigned int port) { - pci_write_config32(PCI_DEV(0, HUDSON_DEVN_BASE + 0x13, 5), + /* Enable all of the USB controllers */ + outb(0xEF, PM_INDEX); + outb(0x7F, PM_DATA); + + pci_write_config32(PCI_DEV(0, HUDSON_DEVN_BASE + 0x12, 2), EHCI_BAR_INDEX, CONFIG_EHCI_BAR); - pci_write_config8(PCI_DEV(0, HUDSON_DEVN_BASE + 0x13, 5), 0x04, 0x2); /* mem space enabe */ + pci_write_config8(PCI_DEV(0, HUDSON_DEVN_BASE + 0x12, 2), 0x04, 0x6); /* mem space enabe */ set_debug_port(port); } diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 064cbc7..de9b979 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -32,6 +32,9 @@ ramstage-$(CONFIG_SB800_IMC_FAN_CONTROL) += fan.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c
+romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c +ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c + ramstage-y += smbus.c ramstage-y += lpc.c
diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c index 174b0f2..158032e 100644 --- a/src/southbridge/amd/sb800/enable_usbdebug.c +++ b/src/southbridge/amd/sb800/enable_usbdebug.c @@ -45,8 +45,12 @@ void set_debug_port(unsigned int port)
void enable_usbdebug(unsigned int port) { - pci_write_config32(PCI_DEV(0, SB800_DEVN_BASE + 0x13, 5), + /* Enable all of the USB controllers */ + outb(0xEF, PM_INDEX); + outb(0x7F, PM_DATA); + + pci_write_config32(PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2), EHCI_BAR_INDEX, CONFIG_EHCI_BAR); - pci_write_config8(PCI_DEV(0, SB800_DEVN_BASE + 0x13, 5), 0x04, 0x2); /* mem space enabe */ + pci_write_config8(PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2), 0x04, 0x6); /* mem space enabe */ set_debug_port(port); }