Re: Level 2 cache activation code?

[Svante Signell]

On Mon, 2003-12-01 at 00:47, Denis Dowling wrote:
> Hi Svante,
>
> ----- Original Message ----- 
> From: "Svante Signell" 
> To: "ron minnich" 
> Cc: "Takeshi Sone" ; 
> Sent: Monday, December 01, 2003 10:14 AM
> Subject: Re: Level 2 cache activation code?
> > The processor is an 1.3GHz Celeron Tualatin, with CPUID: 6b0. According
> > to the code in l2_cache.c newer CPUs than Coppermine (680) does not need
> > the L2 setup code. Is this the case?
>
> This was based on the assumption that all CPU from the coppermine forward
> had the cache integrated onto the CPU die. Is this the case with your CPU.
> Is it just a single large CPU on the slot1 pcb or does there look to be
> cache chips mounted on the board as well?

The CPU is placed on a socket 370 to slot 1 adapter (SLOT-T) from Upgradeware. 
No, there are no external cache chips on the MOBO. BTW, the MOBO is a dual CPU 82443BX 
board (MSI-6120). It runs perfectly well with dual Celerons (Mendocino). Also, the CPU 
placed on the SLOT-T adapter works perfectly well with other (single CPU) boards.
> > if (signature < 0x630 || signature >= 0x680) {
> >   printk_debug("CPU signature of %x so no L2 cache configuration\n",
> > signature);
> >   goto done;
>
> You could always just drop this test and see what happens later. If the CPU
> does have external cache chips then this code might just work in
> initiallising the cache.

I have disabled the test and it seems the cache activation seem to work,
see below. The slowness remains however :-(

Dec  4 14:39:56 cl-dual kernel: Configuring L2 cache...Disable Cache
Dec  4 14:39:56 cl-dual kernel: rdmsr(0x17) = 0, 84320000
Dec  4 14:39:56 cl-dual kernel: L2 Cache latency is 1
Dec  4 14:39:56 cl-dual kernel: Sending 0 to set_l2_register4
Dec  4 14:39:56 cl-dual kernel: L2 ECC Checking is enabled
Dec  4 14:39:56 cl-dual kernel: L2 Physical Address Range is 512M
Dec  4 14:39:56 cl-dual kernel: Maximum cache mask is 2000
Dec  4 14:39:56 cl-dual kernel: L2 Cache Mask is 0
Dec  4 14:39:56 cl-dual kernel: read_l2(2) = 0
Dec  4 14:39:56 cl-dual kernel: write_l2(2) = 0
Dec  4 14:39:56 cl-dual kernel: Enable Cache
Dec  4 14:39:56 cl-dual kernel: L2 Cache size is 256K
Dec  4 14:39:56 cl-dual kernel: L2 Cache lines initialized
Dec  4 14:39:56 cl-dual kernel: Disable Cache
Dec  4 14:39:56 cl-dual kernel: Enable Cache
Dec  4 14:39:56 cl-dual kernel: done.
Dec  4 14:39:56 cl-dual kernel:  cache_on  installed
> Looks fine. Turn on as much debugging in the l2_cache code as possible and
> post to me and I will decode. Need to be able to see all of the printk_debug
> messages.
>
> Regards,
> Denis

What is wrong here:
Not caches
Not mtrr
microcode??
anything else??
HW fault, i.e. the VRM does not work as expected, even though lm-sensors
are reporting correct voltages.
The BIOS is not supporting Coppermine and later CPUs. AMI BIOS V2.0 from
(MSI)

Soon giving up...