On 10/27/07, Corey Osgood corey.osgood@gmail.com wrote:
Hmm, I have no geode (except an NX kicking around somewhere), but I'm looking at the c7, cn700, and vt8237r. I've ported most of the northbridge and superio code, next comes the southbridge.
Let's start getting your patches in the tree in small doses, then. can we start with the superio?
A couple questions, if you don't mind too much:
In the dts: pcipath = "x,y";
x and y are device and function, correct? (only ask because it looks odd on some of them). How do we handle devices on another bus?
Remember this is hierarchical. So the intent is that this pcipath for a device would be contained in the scope of a bus. It's not been tested in real life yet.
Where should/is serial init done? For a separate superio should it be in the initram main(), or is it handled by dts/Kconfig magic? Is calling uart/console init still necessary?
serial init is done in the stage 0 C code, as early as possible.
What's needed for cache as ram (on via c3/7)? Should the generic stage0_i586.S do the trick (or be made to do the trick)? And will/should each cpu have its own folder like in v2, or is there some better and more generic plan?
The generic ought to do the trick for the C3/7. The cpu support is in arch/x86/cpu-name, as in geodelx.
Read my document, and tell me what's missing, and I will update the document. The intent is that the document should have ALL information for a port.
ron