Re: [coreboot] [v2] r4698 - trunk/coreboot-v2/src/mainboard/dell/s1850

[Ed Swierk]

On Wed, Sep 30, 2009 at 5:02 PM,   wrote:
> /* using SerialICE, we've seen this basic reset sequence on the dell.
> * we don't understand it as it uses undocumented registers, but
> * we're going to clone it.
> */
> /* enable a hidden device. */
> b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
> b |= 0x8;
> pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
> /* read-write lock in CMOS on LPC bridge on ICH5 */
> pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, 4);
> /* operate on undocumented device */
> l = pci_read_config32(PCI_DEV(0, 0, 2), 0xa4);
> l |= 0x1000;
> pci_write_config32(PCI_DEV(0, 0, 2), 0xa4, l);
> l = pci_read_config32(PCI_DEV(0, 0, 2), 0x9c);
> l |= 0x8000;
> pci_write_config32(PCI_DEV(0, 0, 2), 0x9c, l);
> /* disable undocumented device */
> b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
> b &= ~0x8;
> pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);

http://downloadmirror.intel.com/8815/ENG/README.TXT offers a hint
about what this is doing, but doesn't really explain why:

"According MCH BSU 0.82, document#64:Required Register Settings. To
take full advantage of the changes in the MCH Silicon, for stability
on MCH B0 stepping and above, Intel recommends that BIOS clear bit 12
of D0:F2:R0A4h and set bit 15 of D0:F2:R09Ch very early during boot."

--Ed