I've tried this for tyan/s1846 (adding to intel/440bx/raminit.c) and I see no change after a diff of my before/after console output log files.
Is there another function I need to add to get output?
Here's a similar section of my console output:
RAM Enable 1: Apply NOP Sending RAM command 0x0020 to 0x00000000 RAM Enable 2: Precharge all Sending RAM command 0x0040 to 0x00000000 RAM Enable 3: CBR Sending RAM command 0x0080 to 0x00000000 Sending RAM command 0x0080 to 0x00000000 Sending RAM command 0x0080 to 0x00000000 Sending RAM command 0x0080 to 0x00000000 Sending RAM command 0x0080 to 0x00000000 Sending RAM command 0x0080 to 0x00000000 Sending RAM command 0x0080 to 0x00000000 Sending RAM command 0x0080 to 0x00000000 RAM Enable 4: Mode register set Sending RAM command 0x0060 to 0x000001d0 RAM Enable 5: Normal operation Sending RAM command 0x0000 to 0x00000000 RAM Enable 6: Enable refresh Enabling refresh (DRAMC = 0x09) for DIMM 00 Enabling refresh (DRAMC = 0x09) for DIMM 01 Enabling refresh (DRAMC = 0x09) for DIMM 02 Enabling refresh (DRAMC = 0x09) for DIMM 03 Northbridge following SDRAM init: PCI: 00:00.00
On Mon, 2007-04-02 at 09:40 -0400, Corey Osgood wrote:
I'm trying to port the sdram reading functions from LBv1 up to v2 (for use with the raminit.c that Uwe just committed), but so far haven't gotten it to work, so I'm hoping maybe someone can spot my problem (I think this is where a problem is). For anyone not familiar with v1, ASSERT_RAM_COMMAND() is called by generic_sdram_enable.inc, and is supposed to read from an address on the dimms. Here's the code for just
...
And here's what I've ported it to. Anyone see anything that sticks out as a problem? (offset = 0x0400, except when setting MRS it's 0x01d0)
static void dimms_read(unsigned long offset) { int slot; //DIMM0_READ unsigned long addr = 0; addr += offset; PRINT_DEBUG("addr = "); PRINT_DEBUG_HEX32(addr); // FIXME PRINT_DEBUG("\r\n"); //DIMM_READ read32(addr); addr ^= 0xdff8; // xorl $0xdff8, %eax read32(addr);
/* All this should be unnecessary for a single sided single dimm and may even screw things up a bit */for(slot = 0; slot < 7; slot++) { //DIMM_BASE(n) /* Compute DIMM_BASE */ addr = pci_read_config8(0, (0x60 + slot ));//count starts at 0, so slot-1 not necessary /* NOTE: We should probably check if we already read this addr (ie if all dimm slots aren't populated), but easier not to */ addr &= 0xFF; addr = (addr << 23); //DIMM_READ addr += offset; PRINT_DEBUG(" to 0x"); PRINT_DEBUG_HEX32(addr); // FIXME read32(addr); /* This was pulled from v1, I think it's right */ addr ^= 0xdff8; PRINT_DEBUG(" and 0x"); PRINT_DEBUG_HEX32(addr); // FIXME PRINT_DEBUG("\r\n"); read32(addr); } }
Here's some of my minicom.cap, showing what addresses this comes up with:
<any non-MRS command> to 0x00000000 and 0x0000dff8 to 0x04000000 and 0x0400dff8 to 0x04000000 and 0x0400dff8 to 0x04000000 and 0x0400dff8 to 0x04000000 and 0x0400dff8 to 0x04000000 and 0x0400dff8 to 0x04000000 and 0x0400dff8 RAM Enable 4: Mode register set Computed cas value = 0x01d0 Sending RAM command 0x03addr = 000001d0 to 0x000001d0 and 0x0000de28 to 0x040001d0 and 0x0400de28 etc
-- Roger http://www.eskimo.com/~roger/index.html Key fingerprint = 8977 A252 2623 F567 70CD 1261 640F C963 1005 1D61
Fri Apr 27 17:33:26 PDT 2007