Re: [coreboot] patch: dbe62

[Peter Stuge]

You got it with code vs. data, Carl-Daniel. This is a nice good step
towards what I meant! :)

I'll try to think a bit about how to express interrupt routing, but
there is no point in a different syntax if it isn't more flexible.
I think this will crystallize for k8.

On Sat, Mar 01, 2008 at 04:16:30PM +0100, Carl-Daniel Hailfinger wrote:
> Ron: The patch is also attached to reduce your gmail pain.
>
> Factor out write_pirq_routing_table() for all GeodeLX targets.
> Compile tested on norwich, alix1c and dbe62. msm800sev is not affected 
> and dbe61 is broken anyway.
>
> svn is unable to create a valid patch for what I did, so I'll have to 
> commit this myself. To reproduce, perform the following commands, then 
> apply the patch:
>
> svn mv mainboard/amd/norwich/irq_tables.c mainboard/amd/norwich/irq_tables.h
> svn mv mainboard/pcengines/alix1c/irq_tables.c 
> mainboard/pcengines/alix1c/irq_tables.h
> svn mv mainboard/artecgroup/dbe61/irq_tables.c 
> mainboard/artecgroup/dbe61/irq_tables.h
> svn mv mainboard/artecgroup/dbe62/irq_tables.c 
> mainboard/artecgroup/dbe62/irq_tables.h
>
> Signed-off-by: Carl-Daniel Hailfinger

Acked-by: Peter Stuge

(but let's have some more comments)
> Index: LinuxBIOSv3-pirq/southbridge/amd/cs5536/irq_tables.c
>
> --- LinuxBIOSv3-pirq/southbridge/amd/cs5536/irq_tables.c	(Revision 0)
> +++ LinuxBIOSv3-pirq/southbridge/amd/cs5536/irq_tables.c	(Revision 0)
> @@ -0,0 +1,77 @@
> +/*
> +* This file is part of the coreboot project.
> +*
> +* Copyright (C) 2007 Advanced Micro Devices, Inc.
> +*
> +* This program is free software; you can redistribute it and/or modify
> +* it under the terms of the GNU General Public License version 2 as
> +* published by the Free Software Foundation.
> +*
> +* This program is distributed in the hope that it will be useful,
> +* but WITHOUT ANY WARRANTY; without even the implied warranty of
> +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +* GNU General Public License for more details.
> +*
> +* You should have received a copy of the GNU General Public License
> +* along with this program; if not, write to the Free Software
> +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> +*/
>
> +#include <types.h>
> +#include <lib.h>
> +#include <console.h>
> +#include <device/device.h>
> +#include <device/pci.h>
> +#include <string.h>
> +#include <msr.h>
> +#include <io.h>
> +#include <pirq_routing.h>
> +#include <amd_geodelx.h>
> +#include <irq_tables.h>
> +#include "cs5536.h"
>
> +unsigned long write_pirq_routing_table(unsigned long addr)
> +{
> int i, j, k, num_entries;
> unsigned char pirq[4];
> u16 chipset_irq_map;
> u32 pciAddr, pirtable_end;
> struct irq_routing_table *pirq_tbl;
> pirtable_end = copy_pirq_routing_table(addr);
> /* Set up chipset IRQ steering. */
> pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
> chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
> printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
>      chipset_irq_map);
> outl(pciAddr & ~3, 0xCF8);
> outl(chipset_irq_map, 0xCFC);
> pirq_tbl = (struct irq_routing_table *) (addr);
> num_entries = (pirq_tbl->size - 32) / 16;
> /* Set PCI IRQs. */
> for (i = 0; i < num_entries; i++) {
> printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
> 	     pirq_tbl->slots[i].devfn, 
>
> pirq_tbl->slots[i].slot);
> for (j = 0; j < 4; j++) {
> 	printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j,
> 		     pirq_tbl->slots[i].irq[j].bitmap);
> 	/* Finds lsb in bitmap to IRQ#. */
> 	for (k = 0; 
> 	     (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 
>
> 1)) +				     && (pirq_tbl->slots[i].irq[j].bitmap != 
> 0);
> 	     k++);
> 	pirq[j] = k;
> 	printk(BIOS_DEBUG, "PIRQ: %d\n", k);
> }
> /* Bus, device, slots IRQs for {A,B,C,D}. */
> pci_assign_irqs(pirq_tbl->slots[i].bus,
> 		pirq_tbl->slots[i].devfn >> 3, pirq);
> }
> /* Put the PIR table in memory and checksum. */
> return pirtable_end;
>
> +}
> Index: LinuxBIOSv3-pirq/southbridge/amd/cs5536/Makefile
> ===================================================================
> --- LinuxBIOSv3-pirq/southbridge/amd/cs5536/Makefile	(Revision 626)
> +++ LinuxBIOSv3-pirq/southbridge/amd/cs5536/Makefile	(Arbeitskopie)
> @@ -23,6 +23,10 @@
>
> STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/cs5536.o
>
> +ifeq ($(CONFIG_PIRQ_TABLE),y)
> +STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/irq_tables.o 
> +endif
>
> STAGE0_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/stage1.o
>
> endif
> Index: LinuxBIOSv3-pirq/mainboard/amd/norwich/irq_tables.h
> ===================================================================
> --- LinuxBIOSv3-pirq/mainboard/amd/norwich/irq_tables.h	(Revision 
> 626)
> +++ LinuxBIOSv3-pirq/mainboard/amd/norwich/irq_tables.h (Arbeitskopie)
> @@ -93,49 +93,3 @@
>     {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, 
>     {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0},	/* slot4 */
>     }
> };
>
> -unsigned long write_pirq_routing_table(unsigned long addr)
> -{
> int i, j, k, num_entries;
> unsigned char pirq[4];
> u16 chipset_irq_map;
> u32 pciAddr, pirtable_end;
> struct irq_routing_table *pirq_tbl;
> pirtable_end = copy_pirq_routing_table(addr);
> /* Set up chipset IRQ steering. */
> pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
> chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
> printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
>      chipset_irq_map);
> outl(pciAddr & ~3, 0xCF8);
> outl(chipset_irq_map, 0xCFC);
> pirq_tbl = (struct irq_routing_table *) (addr);
> num_entries = (pirq_tbl->size - 32) / 16;
> /* Set PCI IRQs. */
> for (i = 0; i < num_entries; i++) {
> printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
> 	     pirq_tbl->slots[i].devfn, 
>
> pirq_tbl->slots[i].slot);
> for (j = 0; j < 4; j++) {
> 	printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j,
> 		     pirq_tbl->slots[i].irq[j].bitmap);
> 	/* Finds lsb in bitmap to IRQ#. */
> 	for (k = 0;
> 	     (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1))
> 		     && (pirq_tbl->slots[i].irq[j].bitmap != 
>
> 0);
> 	     k++);
> 	pirq[j] = k;
> 	printk(BIOS_DEBUG, "PIRQ: %d\n", k);
> }
> /* Bus, device, slots IRQs for {A,B,C,D}. */
> pci_assign_irqs(pirq_tbl->slots[i].bus,
> 		pirq_tbl->slots[i].devfn >> 3, pirq);
> }
> /* Put the PIR table in memory and checksum. */
> return pirtable_end;
>
> -}
> Index: LinuxBIOSv3-pirq/mainboard/amd/norwich/Makefile
> ===================================================================
> --- LinuxBIOSv3-pirq/mainboard/amd/norwich/Makefile	(Revision 626)
> +++ LinuxBIOSv3-pirq/mainboard/amd/norwich/Makefile	(Arbeitskopie)
> @@ -26,7 +26,7 @@
>    	$(src)/southbridge/amd/cs5536/smbus_initram.c \
>    	$(src)/arch/x86/geodelx/geodelx.c
>
> -STAGE2_MAINBOARD_OBJ = irq_tables.o
> +STAGE2_MAINBOARD_OBJ =
>
> $(obj)/coreboot.vpd:
>    $(Q)printf "  BUILD   DUMMY VPD\n"
> Index: LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/irq_tables.h
> ===================================================================
> --- LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/irq_tables.h	(Revision 
> 626)
> +++ LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/irq_tables.h (Arbeitskopie)
> @@ -68,49 +68,3 @@
>     {0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 
>     0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* ethernet */
>    }
> };
>
> -unsigned long write_pirq_routing_table(unsigned long addr)
> -{
> int i, j, k, num_entries;
> unsigned char pirq[4];
> u16 chipset_irq_map;
> u32 pciAddr, pirtable_end;
> struct irq_routing_table *pirq_tbl;
> pirtable_end = copy_pirq_routing_table(addr);
> /* Set up chipset IRQ steering. */
> pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
> chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
> printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
>      chipset_irq_map);
> outl(pciAddr & ~3, 0xCF8);
> outl(chipset_irq_map, 0xCFC);
> pirq_tbl = (struct irq_routing_table *) (addr);
> num_entries = (pirq_tbl->size - 32) / 16;
> /* Set PCI IRQs. */
> for (i = 0; i < num_entries; i++) {
> printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
> 	     pirq_tbl->slots[i].devfn, 
>
> pirq_tbl->slots[i].slot);
> for (j = 0; j < 4; j++) {
> 	printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j,
> 		     pirq_tbl->slots[i].irq[j].bitmap);
> 	/* Finds lsb in bitmap to IRQ#. */
> 	for (k = 0; 
> 	     (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 
>
> 1)) -				     && (pirq_tbl->slots[i].irq[j].bitmap != 
> 0);
> 	     k++);
> 	pirq[j] = k;
> 	printk(BIOS_DEBUG, "PIRQ: %d\n", k);
> }
> /* Bus, device, slots IRQs for {A,B,C,D}. */
> pci_assign_irqs(pirq_tbl->slots[i].bus,
> 		pirq_tbl->slots[i].devfn >> 3, pirq);
> }
> /* Put the PIR table in memory and checksum. */
> return pirtable_end;
>
> -}
> Index: LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/Makefile
> ===================================================================
> --- LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/Makefile	(Revision 
> 626)
> +++ LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/Makefile (Arbeitskopie)
> @@ -25,7 +25,7 @@
>    	$(src)/northbridge/amd/geodelx/raminit.c \
>    	$(src)/arch/x86/geodelx/geodelx.c
>
> -STAGE2_MAINBOARD_OBJ = irq_tables.o 
> +STAGE2_MAINBOARD_OBJ =
>
> $(obj)/coreboot.vpd:
>    $(Q)printf "  BUILD   DUMMY VPD\n"
> Index: LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/irq_tables.h
> ===================================================================
> --- LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/irq_tables.h	(Revision 
> 626)
> +++ LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/irq_tables.h (Arbeitskopie)
> @@ -17,20 +17,9 @@
> Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
>
> */
>
> -#include <types.h>
> -#include <lib.h>
> -#include <console.h>
> -#include <device/device.h>
> -#include <device/pci.h>
> -#include <string.h>
> -#include <msr.h>
> -#include <io.h>
> #include <pirq_routing.h>
> -#include <amd_geodelx.h>
> -#include "../../../southbridge/amd/cs5536/cs5536.h"
>
> /* Platform IRQs */
> #define PIRQA 11
> #define PIRQB 10
> @@ -112,49 +101,3 @@
>    	{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, 
>    	M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
>    }
> };
>
> -unsigned long write_pirq_routing_table(unsigned long addr)
> -{
> int i, j, k, num_entries;
> unsigned char pirq[4];
> u16 chipset_irq_map;
> u32 pciAddr, pirtable_end;
> struct irq_routing_table *pirq_tbl;
> pirtable_end = copy_pirq_routing_table(addr);
> /* Set up chipset IRQ steering. */
> pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
> chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
> printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
>      chipset_irq_map);
> outl(pciAddr & ~3, 0xCF8);
> outl(chipset_irq_map, 0xCFC);
> pirq_tbl = (struct irq_routing_table *) (addr);
> num_entries = (pirq_tbl->size - 32) / 16;
> /* Set PCI IRQs. */
> for (i = 0; i < num_entries; i++) {
> printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
> 	     pirq_tbl->slots[i].devfn, 
>
> pirq_tbl->slots[i].slot);
> for (j = 0; j < 4; j++) {
> 	printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j,
> 		     pirq_tbl->slots[i].irq[j].bitmap);
> 	/* Finds lsb in bitmap to IRQ#. */
> 	for (k = 0; 
> 	     (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 
>
> 1)) -				     && (pirq_tbl->slots[i].irq[j].bitmap != 
> 0);
> 	     k++);
> 	pirq[j] = k;
> 	printk(BIOS_DEBUG, "PIRQ: %d\n", k);
> }
> /* Bus, device, slots IRQs for {A,B,C,D}. */
> pci_assign_irqs(pirq_tbl->slots[i].bus,
> 		pirq_tbl->slots[i].devfn >> 3, pirq);
> }
> /* Put the PIR table in memory and checksum. */
> return pirtable_end;
>
> -}
> Index: LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/Makefile
> ===================================================================
> --- LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/Makefile	(Revision 
> 626)
> +++ LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/Makefile (Arbeitskopie)
> @@ -25,7 +25,7 @@
>    	$(src)/northbridge/amd/geodelx/raminit.c \
>    	$(src)/arch/x86/geodelx/geodelx.c
>
> -STAGE2_MAINBOARD_OBJ = irq_tables.o 
> +STAGE2_MAINBOARD_OBJ =
>
> $(obj)/coreboot.vpd:
>    $(Q)printf "  BUILD   DUMMY VPD\n"
> Index: LinuxBIOSv3-pirq/Makefile
> ===================================================================
> --- LinuxBIOSv3-pirq/Makefile	(Revision 626)
> +++ LinuxBIOSv3-pirq/Makefile	(Arbeitskopie)
> @@ -85,6 +85,7 @@
> COREBOOTINCLUDE    :=   -I$(src) -Iinclude \
>    		-I$(src)/include \
>    		-I$(src)/include/arch/$(ARCH)/ \
> 	-I$(src)/mainboard/$(MAINBOARDDIR)/ \
> -include $(obj)/config.h \
> -include $(obj)/build.h
> Index: LinuxBIOSv3-pirq/southbridge/amd/cs5536/irq_tables.c
>
> --- LinuxBIOSv3-pirq/southbridge/amd/cs5536/irq_tables.c	(Revision 0)
> +++ LinuxBIOSv3-pirq/southbridge/amd/cs5536/irq_tables.c	(Revision 0)
> @@ -0,0 +1,77 @@
> +/*
> +* This file is part of the coreboot project.
> +*
> +* Copyright (C) 2007 Advanced Micro Devices, Inc.
> +*
> +* This program is free software; you can redistribute it and/or modify
> +* it under the terms of the GNU General Public License version 2 as
> +* published by the Free Software Foundation.
> +*
> +* This program is distributed in the hope that it will be useful,
> +* but WITHOUT ANY WARRANTY; without even the implied warranty of
> +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +* GNU General Public License for more details.
> +*
> +* You should have received a copy of the GNU General Public License
> +* along with this program; if not, write to the Free Software
> +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> +*/
>
> +#include <types.h>
> +#include <lib.h>
> +#include <console.h>
> +#include <device/device.h>
> +#include <device/pci.h>
> +#include <string.h>
> +#include <msr.h>
> +#include <io.h>
> +#include <pirq_routing.h>
> +#include <amd_geodelx.h>
> +#include <irq_tables.h>
> +#include "cs5536.h"
>
> +unsigned long write_pirq_routing_table(unsigned long addr)
> +{
> int i, j, k, num_entries;
> unsigned char pirq[4];
> u16 chipset_irq_map;
> u32 pciAddr, pirtable_end;
> struct irq_routing_table *pirq_tbl;
> pirtable_end = copy_pirq_routing_table(addr);
> /* Set up chipset IRQ steering. */
> pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
> chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
> printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
>      chipset_irq_map);
> outl(pciAddr & ~3, 0xCF8);
> outl(chipset_irq_map, 0xCFC);
> pirq_tbl = (struct irq_routing_table *) (addr);
> num_entries = (pirq_tbl->size - 32) / 16;
> /* Set PCI IRQs. */
> for (i = 0; i < num_entries; i++) {
> printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
> 	     pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
> for (j = 0; j < 4; j++) {
> 	printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j,
> 		     pirq_tbl->slots[i].irq[j].bitmap);
> 	/* Finds lsb in bitmap to IRQ#. */
> 	for (k = 0; 
> 	     (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) 
> 		     && (pirq_tbl->slots[i].irq[j].bitmap != 0);
> 	     k++);
> 	pirq[j] = k;
> 	printk(BIOS_DEBUG, "PIRQ: %d\n", k);
> }
> /* Bus, device, slots IRQs for {A,B,C,D}. */
> pci_assign_irqs(pirq_tbl->slots[i].bus,
> 		pirq_tbl->slots[i].devfn >> 3, pirq);
> }
> /* Put the PIR table in memory and checksum. */
> return pirtable_end;
>
> +}
> Index: LinuxBIOSv3-pirq/southbridge/amd/cs5536/Makefile
> ===================================================================
> --- LinuxBIOSv3-pirq/southbridge/amd/cs5536/Makefile	(Revision 626)
> +++ LinuxBIOSv3-pirq/southbridge/amd/cs5536/Makefile	(Arbeitskopie)
> @@ -23,6 +23,10 @@
>
> STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/cs5536.o
>
> +ifeq ($(CONFIG_PIRQ_TABLE),y)
> +STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/irq_tables.o 
> +endif
>
> STAGE0_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/stage1.o
>
> endif
> Index: LinuxBIOSv3-pirq/mainboard/amd/norwich/irq_tables.h
> ===================================================================
> --- LinuxBIOSv3-pirq/mainboard/amd/norwich/irq_tables.h	(Revision 626)
> +++ LinuxBIOSv3-pirq/mainboard/amd/norwich/irq_tables.h	(Arbeitskopie)
> @@ -93,49 +93,3 @@
>     {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0},	/* slot4 */
>     }
>  };
>
> -unsigned long write_pirq_routing_table(unsigned long addr)
> -{
> int i, j, k, num_entries;
> unsigned char pirq[4];
> u16 chipset_irq_map;
> u32 pciAddr, pirtable_end;
> struct irq_routing_table *pirq_tbl;
> pirtable_end = copy_pirq_routing_table(addr);
> /* Set up chipset IRQ steering. */
> pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
> chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
> printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
>      chipset_irq_map);
> outl(pciAddr & ~3, 0xCF8);
> outl(chipset_irq_map, 0xCFC);
> pirq_tbl = (struct irq_routing_table *) (addr);
> num_entries = (pirq_tbl->size - 32) / 16;
> /* Set PCI IRQs. */
> for (i = 0; i < num_entries; i++) {
> printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
> 	     pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
> for (j = 0; j < 4; j++) {
> 	printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j,
> 		     pirq_tbl->slots[i].irq[j].bitmap);
> 	/* Finds lsb in bitmap to IRQ#. */
> 	for (k = 0;
> 	     (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1))
> 		     && (pirq_tbl->slots[i].irq[j].bitmap != 0);
> 	     k++);
> 	pirq[j] = k;
> 	printk(BIOS_DEBUG, "PIRQ: %d\n", k);
> }
> /* Bus, device, slots IRQs for {A,B,C,D}. */
> pci_assign_irqs(pirq_tbl->slots[i].bus,
> 		pirq_tbl->slots[i].devfn >> 3, pirq);
> }
> /* Put the PIR table in memory and checksum. */
> return pirtable_end;
>
> -}
> Index: LinuxBIOSv3-pirq/mainboard/amd/norwich/Makefile
> ===================================================================
> --- LinuxBIOSv3-pirq/mainboard/amd/norwich/Makefile	(Revision 626)
> +++ LinuxBIOSv3-pirq/mainboard/amd/norwich/Makefile	(Arbeitskopie)
> @@ -26,7 +26,7 @@
>    	$(src)/southbridge/amd/cs5536/smbus_initram.c \
>    	$(src)/arch/x86/geodelx/geodelx.c
>
> -STAGE2_MAINBOARD_OBJ = irq_tables.o
> +STAGE2_MAINBOARD_OBJ =
>
> $(obj)/coreboot.vpd:
>    $(Q)printf "  BUILD   DUMMY VPD\n"
> Index: LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/irq_tables.h
> ===================================================================
> --- LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/irq_tables.h	(Revision 626)
> +++ LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/irq_tables.h	(Arbeitskopie)
> @@ -68,49 +68,3 @@
>     {0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* ethernet */
>    }
>  };
>
> -unsigned long write_pirq_routing_table(unsigned long addr)
> -{
> int i, j, k, num_entries;
> unsigned char pirq[4];
> u16 chipset_irq_map;
> u32 pciAddr, pirtable_end;
> struct irq_routing_table *pirq_tbl;
> pirtable_end = copy_pirq_routing_table(addr);
> /* Set up chipset IRQ steering. */
> pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
> chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
> printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
>      chipset_irq_map);
> outl(pciAddr & ~3, 0xCF8);
> outl(chipset_irq_map, 0xCFC);
> pirq_tbl = (struct irq_routing_table *) (addr);
> num_entries = (pirq_tbl->size - 32) / 16;
> /* Set PCI IRQs. */
> for (i = 0; i < num_entries; i++) {
> printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
> 	     pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
> for (j = 0; j < 4; j++) {
> 	printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j,
> 		     pirq_tbl->slots[i].irq[j].bitmap);
> 	/* Finds lsb in bitmap to IRQ#. */
> 	for (k = 0; 
> 	     (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) 
> 		     && (pirq_tbl->slots[i].irq[j].bitmap != 0);
> 	     k++);
> 	pirq[j] = k;
> 	printk(BIOS_DEBUG, "PIRQ: %d\n", k);
> }
> /* Bus, device, slots IRQs for {A,B,C,D}. */
> pci_assign_irqs(pirq_tbl->slots[i].bus,
> 		pirq_tbl->slots[i].devfn >> 3, pirq);
> }
> /* Put the PIR table in memory and checksum. */
> return pirtable_end;
>
> -}
> Index: LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/Makefile
> ===================================================================
> --- LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/Makefile	(Revision 626)
> +++ LinuxBIOSv3-pirq/mainboard/artecgroup/dbe62/Makefile	(Arbeitskopie)
> @@ -25,7 +25,7 @@
>    	$(src)/northbridge/amd/geodelx/raminit.c \
>    	$(src)/arch/x86/geodelx/geodelx.c
>
> -STAGE2_MAINBOARD_OBJ = irq_tables.o 
> +STAGE2_MAINBOARD_OBJ =
>
> $(obj)/coreboot.vpd:
>    $(Q)printf "  BUILD   DUMMY VPD\n"
> Index: LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/irq_tables.h
> ===================================================================
> --- LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/irq_tables.h	(Revision 626)
> +++ LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/irq_tables.h	(Arbeitskopie)
> @@ -17,20 +17,9 @@
> Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
>
> */
>
> -#include <types.h>
> -#include <lib.h>
> -#include <console.h>
> -#include <device/device.h>
> -#include <device/pci.h>
> -#include <string.h>
> -#include <msr.h>
> -#include <io.h>
>  #include <pirq_routing.h>
> -#include <amd_geodelx.h>
> -#include "../../../southbridge/amd/cs5536/cs5536.h"
>
> /* Platform IRQs */
>  #define PIRQA 11
>  #define PIRQB 10
> @@ -112,49 +101,3 @@
>    	{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
>    }
>  };
>
> -unsigned long write_pirq_routing_table(unsigned long addr)
> -{
> int i, j, k, num_entries;
> unsigned char pirq[4];
> u16 chipset_irq_map;
> u32 pciAddr, pirtable_end;
> struct irq_routing_table *pirq_tbl;
> pirtable_end = copy_pirq_routing_table(addr);
> /* Set up chipset IRQ steering. */
> pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
> chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
> printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
>      chipset_irq_map);
> outl(pciAddr & ~3, 0xCF8);
> outl(chipset_irq_map, 0xCFC);
> pirq_tbl = (struct irq_routing_table *) (addr);
> num_entries = (pirq_tbl->size - 32) / 16;
> /* Set PCI IRQs. */
> for (i = 0; i < num_entries; i++) {
> printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
> 	     pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
> for (j = 0; j < 4; j++) {
> 	printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j,
> 		     pirq_tbl->slots[i].irq[j].bitmap);
> 	/* Finds lsb in bitmap to IRQ#. */
> 	for (k = 0; 
> 	     (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) 
> 		     && (pirq_tbl->slots[i].irq[j].bitmap != 0);
> 	     k++);
> 	pirq[j] = k;
> 	printk(BIOS_DEBUG, "PIRQ: %d\n", k);
> }
> /* Bus, device, slots IRQs for {A,B,C,D}. */
> pci_assign_irqs(pirq_tbl->slots[i].bus,
> 		pirq_tbl->slots[i].devfn >> 3, pirq);
> }
> /* Put the PIR table in memory and checksum. */
> return pirtable_end;
>
> -}
> Index: LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/Makefile
> ===================================================================
> --- LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/Makefile	(Revision 626)
> +++ LinuxBIOSv3-pirq/mainboard/pcengines/alix1c/Makefile	(Arbeitskopie)
> @@ -25,7 +25,7 @@
>    	$(src)/northbridge/amd/geodelx/raminit.c \
>    	$(src)/arch/x86/geodelx/geodelx.c
>
> -STAGE2_MAINBOARD_OBJ = irq_tables.o 
> +STAGE2_MAINBOARD_OBJ =
>
> $(obj)/coreboot.vpd:
>    $(Q)printf "  BUILD   DUMMY VPD\n"
> Index: LinuxBIOSv3-pirq/Makefile
> ===================================================================
> --- LinuxBIOSv3-pirq/Makefile	(Revision 626)
> +++ LinuxBIOSv3-pirq/Makefile	(Arbeitskopie)
> @@ -85,6 +85,7 @@
>  COREBOOTINCLUDE    :=   -I$(src) -Iinclude \
>    		-I$(src)/include \
>    		-I$(src)/include/arch/$(ARCH)/ \
> 	-I$(src)/mainboard/$(MAINBOARDDIR)/ \
> -include $(obj)/config.h \
> -include $(obj)/build.h