[coreboot] Re: PCIe hotplug support with Intel FSP 2.0

[Jay Talbott]

The behavior of the FSP is that if PCIe hot plug is not enabled for a root port and nothing is connected to that root port at boot time, the root port is automatically disabled. The root port disappears and therefore is not enumerated during the PCI bus scan or assigned any PCI resources.

Enabling PCIe hot plug results in the root port remaining enabled even if nothing is connected to it at boot time. In this case the root port is enumerated and assigned resources, but obviously nothing is detected connected to it, and thus no PCI resources are reserved by coreboot for any device that connects to the root port after boot.

No further infrastructure is needed in coreboot, as handling of hot plug events should be handled at the OS level after the system is booted. Obviously this would include needing to do a PCI bus rescan and resource reallocation after the newly attached device is detected.

So the whole purpose of the PCIe hot plug settings in the FSP are simply to keep the root port from being automatically disabled if no device is connected to it at boot time. That’s all it does.

- Jay

Jay Talbott
Principal Consulting Engineer
SysPro Consulting, LLC
3057 E. Muirfield St.
Gilbert, AZ 85298
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> On Apr 30, 2020, at 2:35 AM, Michal Zygowski  wrote:
>
> Dear coreboot community,
>
> What are the requirements for working PCIe hotplug support on
> Intel-based platforms using FSP 2.0?
>
> I see there are FSP configuration options for PCIe root ports hotplug,
> but setting the bit alone and enabling PCIe hotplug in coreboot is
> sufficient?
> Typically there should be an ACPI code or SMI handler to train the link
> when the device is detected in the slot if I am not mistaken.
>
> Anyone with PCIe hotplug experience could advise and clarify my doubts?
>
> Thanks in advance.
>
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