[coreboot] r849 - coreboot-v3/arch/x86/amd/model_fxx

Author: rminnich
Date: 2008-08-30 06:20:03 +0200 (Sat, 30 Aug 2008)
New Revision: 849

Modified:
   coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c
Log:
Hacks to get us trying to read the smbus.

There is really strange logic in the init_cpus, and it needs cleanup.

Signed-off-by: Ronald G. Minnich 
Acked-by: Ronald G. Minnich

Modified: coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c
===================================================================
--- coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c	2008-08-30 03:42:01 UTC (rev 848)
+++ coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c	2008-08-30 04:20:03 UTC (rev 849)
@@ -69,8 +69,8 @@
    nodes = get_nodes();

/* if the get_option fails siblings remain disabled. */
-	disable_siblings = !CONFIG_LOGICAL_CPUS;
-	get_option(&disable_siblings, "dual_core");
+	// This sound not be a config option. 	disable_siblings = !CONFIG_LOGICAL_CPUS;
+	//get_option(&disable_siblings, "dual_core");

/* There is an interesting problem in different steppings. See page 373. The interpretation of the 
     * APIC ID bits is different. To determine which order is used, check bit 54 of the programmers' guide
@@ -79,7 +79,7 @@
     */
    nb_cfg_54 = read_nb_cfg_54();

-
+	printk(BIOS_SPEW, "for_each_ap: nodes is %d\n", nodes);
    for (i = 0; i < nodes; i++) {
    	e0_later_single_core = 0;
    	/* Page 166. This field indicates the number of cores, with 0 meaning 1, 1 meaning 2, and all else reserved */
@@ -93,6 +93,7 @@
    	}
    	siblings = j;

+		printk(BIOS_SPEW, "Node %d: siblings is %d\n", i, siblings);
    	unsigned jstart, jend;

if (core_range == 2) {
@@ -109,7 +110,7 @@

for (j = jstart; j <= jend; j++) {
-
+			printk(BIOS_SPEW, "Node %d: Start %d\n", i, j);
    		ap_apicid =
    		    i * (nb_cfg_54 ? (siblings + 1) : 1) +
    		    j * (nb_cfg_54 ? 1 : 8);
@@ -327,6 +328,8 @@
     */
    void soft_reset(void);

+#warning ignore init_detectedx
+cpu_init_detectedx = 0;
    /* 
     * MTRR must be set by this point.
     */