Dear Marshall, dear Felix, dear coreboot folks,
As documented in *AMD Family 17h in coreboot* [1][2], the AMD Secure Processor [3], formerly known as Platform Security Processor [4], now discovers, enables and trains DRAM [5].
Ron compared it to the QEMU Q35 target in his OSFC 2020 talk *pure open source on an AMD Zen* [6].
My question is, why is the AGESA proprietary blob still integrated into coreboot (using the FSP driver)? I thought, the blobs were only needed for memory initialization, and the rest could be done in coreboot.
From *AMD Family 17h in coreboot* [1]:
Support in coreboot for modern AMD products is based on AMD’s reference code: AMD Generic Encapsulated Software Architecture (AGESA™). AGESA contains the technology for enabling DRAM, configuring proprietary core logic, assistance with generating ACPI tables, and other features.
Could this be done in coreboot?
Shouldn’t Ron’s approach be the way forward for future devices seeing to depend on as few blobs as necessary?
Kind regards,
Paul
[1]: https://doc.coreboot.org/soc/amd/family17h.html [2]: https://review.coreboot.org/cgit/coreboot.git/tree/Documentation/soc/amd/fam... [3]: https://www.amd.com/en/technologies/pro-security [4]: https://en.wikipedia.org/wiki/AMD_Platform_Security_Processor [5]: https://doc.coreboot.org/soc/amd/family17h.html#problem-statements [6]: https://cfp.osfc.io/osfc2020/talk/TBSHA8/