On Wed, Jun 8, 2011 at 5:57 PM, Thomas Rohloff v10lator@myway.de wrote:
Am Fri, 3 Jun 2011 20:43:17 +0200 schrieb Stefan Reinauer stefan.reinauer@coreboot.org:
If someone with the hardware steps up to do a port there is a chance indeed.
I googled a bit and found somebody called "Jonathan A. Kollasch". He wrote that he has a board with the same north- and southbridge. This message was from 12.04. at 23:06. If anybody has his message (subject: "SB850 SERR# routinh (almost off-topic)") please re-send it to me because his e-mail isn't shown in the mailing list archives found by google but I would like to speak to him. :)
He hangs out on #coreboot on freenode using the name "jakllsch".
On Wed, Jun 8, 2011 at 5:57 PM, Thomas Rohloff v10lator@myway.de wrote:
That someone could be you! :-)
I don't think so. I know all the documentation is there but my coding skills are extreme poor.
That's fine. It sounds like your board is like 95% done thanks to Jonathan's efforts (assuming he's been successful) and AMD. If you can copy some files and make some minor tweaks to config files, that might be enough to get you up and running without actually doing any coding.
On Wed, Jun 8, 2011 at 5:57 PM, Thomas Rohloff v10lator@myway.de wrote:
Also be sure that you have any means of recovery. A second flash chip if yours is socketed, or an external eeprom burner for instance.
I would buy a secound chip if I could help with it, but I don't think I could do more then testing.
Have not looked into it, but I believe I read that the 3core/4core
switch is done by some code running on the EC, so it might not be a lot of work on the bios side.
What is EC? Is this a chip called "UCC" by AsRock?
EC is sort of a SuperIO chip, but with more functions commonly used in laptops. I think you have a normal SuperIO chip. "UCC" seems to be a marketing name from AsRock that means "Unlock CPU Core".