Quoting ron minnich rminnich@gmail.com:
On Fri, Feb 22, 2008 at 8:15 AM, joe@smittys.pointclark.net wrote:
For coreboot to automate this it would have to a IDENTIFY_DRIVE command query to the drive and then set IDE pci configuration register. Would this be possible to do pre payload or is this something that would have to be set manually. If manual could we impliment a global setting??
I hate to say this, but I think we need to do this in the code for that chip. Whicdh chipset is this again?
ron
It is the Intel 82801DB ICH4 chipset. I think most of the ICH's are the same on this. So are you saying this can be set in filo, or coreboot?
IDE_CONFIG?IDE I/O Configuration Register(IDE?D31:F1) Address Offset: 54h Attribute: R/W Default Value: 00h Size: 32 bits
Bit 7 Secondary Slave Channel Cable Reporting ? R/W. BIOS should program this bit to tell the IDE driver which cable is plugged into the channel. 0 = 40 conductor cable is present. 1 = 80 conductor cable is present. Bit 6 Secondary Master Channel Cable Reporting ? R/W. Same description as bit 7 Bit 5 Primary Slave Channel Cable Reporting ? R/W. Same description as bit 7 Bit 4 Primary Master Channel Cable Reporting ? R/W. Same description as bit 7
Thanks - Joe