Author: hailfinger Date: 2008-03-07 02:20:36 +0100 (Fri, 07 Mar 2008) New Revision: 637
Modified: coreboot-v3/arch/x86/pirq_routing.c coreboot-v3/mainboard/amd/norwich/irq_tables.h coreboot-v3/mainboard/artecgroup/dbe61/irq_tables.h coreboot-v3/mainboard/artecgroup/dbe62/irq_tables.h coreboot-v3/mainboard/pcengines/alix1c/irq_tables.h Log: PIRQ table cosmetics/cleanup. Bugfixes and #error for uninitialized memory accesses.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net Acked-by: Uwe Hermann uwe@hermann-uwe.de
Modified: coreboot-v3/arch/x86/pirq_routing.c =================================================================== --- coreboot-v3/arch/x86/pirq_routing.c 2008-03-06 23:33:59 UTC (rev 636) +++ coreboot-v3/arch/x86/pirq_routing.c 2008-03-07 01:20:36 UTC (rev 637) @@ -37,16 +37,6 @@
printk(BIOS_INFO, "Checking IRQ routing table consistency...\n");
-#if defined(IRQ_SLOT_COUNT) - if (sizeof(struct irq_routing_table) != rt->size) { - printk_warning("Inconsistent IRQ routing table size (0x%x/0x%x)\n", - sizeof(struct irq_routing_table), - rt->size - ); - rt->size=sizeof(struct irq_routing_table); - } -#endif - for (i = 0; i < rt->size; i++) sum += addr[i];
Modified: coreboot-v3/mainboard/amd/norwich/irq_tables.h =================================================================== --- coreboot-v3/mainboard/amd/norwich/irq_tables.h 2008-03-06 23:33:59 UTC (rev 636) +++ coreboot-v3/mainboard/amd/norwich/irq_tables.h 2008-03-07 01:20:36 UTC (rev 637) @@ -17,20 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <types.h> -#include <lib.h> -#include <console.h> -#include <device/device.h> -#include <device/pci.h> -#include <string.h> -#include <msr.h> -#include <io.h> #include <pirq_routing.h> -#include <amd_geodelx.h> -#include "../../../southbridge/amd/cs5536/cs5536.h"
/* Number of slots and devices in the PIR table */ -#define SLOT_COUNT 6 +#define IRQ_SLOT_COUNT 6
/* Platform IRQs */ #define PIRQA 11 @@ -73,7 +63,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * SLOT_COUNT, /* Max. number of devices on the bus */ + 32 + 16 * IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ @@ -83,13 +73,19 @@ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ 0x00, /* Checksum */ { - /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ - {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ - {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0}, /* slot1 */ - {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0}, /* slot2 */ - {0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x3, 0x0}, /* slot3 */ - {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, /* slot4 */ + /* If you change the number of entries, change IRQ_SLOT_COUNT above! */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* CPU */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, + /* chipset */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, + /* slot1 */ + {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0}, + /* slot2 */ + {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0}, + /* slot3 */ + {0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x3, 0x0}, + /* slot4 */ + {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, } };
Modified: coreboot-v3/mainboard/artecgroup/dbe61/irq_tables.h =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe61/irq_tables.h 2008-03-06 23:33:59 UTC (rev 636) +++ coreboot-v3/mainboard/artecgroup/dbe61/irq_tables.h 2008-03-07 01:20:36 UTC (rev 637) @@ -5,7 +5,7 @@ * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM */
-#include <arch/pirq_routing.h> +#include <pirq_routing.h>
#define ID_SLOT_PCI_NET 1 // ThinCan ethernet #define ID_SLOT_PCI_RSVD1 2 // reserved entry 1
Modified: coreboot-v3/mainboard/artecgroup/dbe62/irq_tables.h =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/irq_tables.h 2008-03-06 23:33:59 UTC (rev 636) +++ coreboot-v3/mainboard/artecgroup/dbe62/irq_tables.h 2008-03-07 01:20:36 UTC (rev 637) @@ -17,20 +17,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <types.h> -#include <lib.h> -#include <console.h> -#include <device/device.h> -#include <device/pci.h> -#include <string.h> -#include <msr.h> -#include <io.h> #include <pirq_routing.h> -#include <amd_geodelx.h> -#include "../../../southbridge/amd/cs5536/cs5536.h"
+/* Number of slots and devices in the PIR table */ +#error IRQ_SLOT_COUNT does not match PIR table contents, IRQ routing setup will access uninitialied memory +#define IRQ_SLOT_COUNT 5
- /* Platform IRQs */ #define PIRQA 10 #define PIRQB 11 @@ -52,7 +44,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * 5, /* Max. number of devices on the bus */ + 32 + 16 * IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ @@ -62,9 +54,13 @@ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ 0x00, /* Checksum */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ - {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ - {0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ + /* If you change the number of entries, change IRQ_SLOT_COUNT above! */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* CPU */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, + /* chipset */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, + /* ethernet */ + {0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, } };
Modified: coreboot-v3/mainboard/pcengines/alix1c/irq_tables.h =================================================================== --- coreboot-v3/mainboard/pcengines/alix1c/irq_tables.h 2008-03-06 23:33:59 UTC (rev 636) +++ coreboot-v3/mainboard/pcengines/alix1c/irq_tables.h 2008-03-07 01:20:36 UTC (rev 637) @@ -19,6 +19,8 @@
#include <pirq_routing.h>
+/* Number of slots and devices in the PIR table */ +#define IRQ_SLOT_COUNT 5
/* Platform IRQs */ #define PIRQA 11 @@ -71,7 +73,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * 5, /* Max. number of devices on the bus */ + 32 + 16 * IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */