Author: stepan Date: Wed Jan 19 07:32:35 2011 New Revision: 6272 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6272
Log: Now that the VIA code is run above 1Meg (like other boards), it should cache that range instead of the first 1Meg. This reduces boot time by about 1 second on epia-cn.
This patch also adds a MTRRphysMaskValid bit definition.
Signed-off-by: Kevin O'Connor kevin@koconnor.net Acked-by: Stefan Reinauer stepan@coreboot.org
Modified: trunk/src/cpu/via/car/cache_as_ram.inc trunk/src/cpu/x86/mtrr/mtrr.c trunk/src/include/cpu/x86/mtrr.h
Modified: trunk/src/cpu/via/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/via/car/cache_as_ram.inc Wed Jan 19 07:31:24 2011 (r6271) +++ trunk/src/cpu/via/car/cache_as_ram.inc Wed Jan 19 07:32:35 2011 (r6272) @@ -103,7 +103,7 @@ movl $MTRRphysMask_MSR(0), %ecx /* This assumes we never access addresses above 2^36 in CAR. */ movl $0x0000000f, %edx - movl $(~(CacheSize - 1) | 0x800), %eax + movl $(~(CacheSize - 1) | MTRRphysMaskValid), %eax wrmsr
#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK @@ -129,7 +129,7 @@
movl $MTRRphysMask_MSR(1), %ecx movl $0x0000000f, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr
/* Set the default memory type and enable fixed and variable MTRRs. */ @@ -219,54 +219,27 @@ movl $(MTRRdefTypeEn), %eax wrmsr
- /* Enable caching for first 1M using variable MTRR. */ + /* Enable caching for CONFIG_RAMBASE..CONFIG_RAMTOP. */ movl $MTRRphysBase_MSR(0), %ecx xorl %edx, %edx - movl $(0 | MTRR_TYPE_WRBACK), %eax + movl $(CONFIG_RAMBASE | MTRR_TYPE_WRBACK), %eax wrmsr
- /* - * Enable cache for 0-7ffff, 80000-9ffff, e0000-fffff; - * If 1M cacheable, then when S3 resume, there is stange color on - * screen for 2 sec. Suppose problem of a0000-dfffff and cache. - * And in x86_setup_fixed_mtrrs()(mtrr.c), 0-256M is set cacheable. - */ - movl $MTRRphysMask_MSR(0), %ecx movl $0x0000000f, %edx /* AMD 40 bit 0xff */ - movl $((~((0 + 0x80000) - 1)) | 0x800), %eax - wrmsr - - movl $MTRRphysBase_MSR(1), %ecx - xorl %edx, %edx - movl $(0x80000 | MTRR_TYPE_WRBACK), %eax - wrmsr - - movl $MTRRphysMask_MSR(1), %ecx - movl $0x0000000f, %edx /* AMD 40 bit 0xff */ - movl $((~((0 + 0x20000) - 1)) | 0x800), %eax - wrmsr - - movl $MTRRphysBase_MSR(2), %ecx - xorl %edx, %edx - movl $(0xc0000 | MTRR_TYPE_WRBACK), %eax - wrmsr - - movl $MTRRphysMask_MSR(2), %ecx - movl $0x0000000f, %edx /* AMD 40 bit 0xff */ - movl $((~(( 0 + 0x40000) - 1)) | 0x800), %eax + movl $(~(CONFIG_RAMTOP - CONFIG_RAMBASE - 1) | MTRRphysMaskValid), %eax wrmsr
/* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */ - movl $MTRRphysBase_MSR(3), %ecx + movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx movl $REAL_XIP_ROM_BASE, %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr
- movl $MTRRphysMask_MSR(3), %ecx + movl $MTRRphysMask_MSR(1), %ecx xorl %edx, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr
enable_cache()
Modified: trunk/src/cpu/x86/mtrr/mtrr.c ============================================================================== --- trunk/src/cpu/x86/mtrr/mtrr.c Wed Jan 19 07:31:24 2011 (r6271) +++ trunk/src/cpu/x86/mtrr/mtrr.c Wed Jan 19 07:32:35 2011 (r6272) @@ -62,7 +62,7 @@ msr_t msr;
msr = rdmsr(MTRRdefType_MSR); - msr.lo |= 0x800; + msr.lo |= MTRRdefTypeEn; wrmsr(MTRRdefType_MSR, msr); }
@@ -115,7 +115,7 @@
/* Bit 32-35 of MTRRphysMask should be set to 1 */ base.lo |= type; - mask.lo |= 0x800; + mask.lo |= MTRRphysMaskValid; wrmsr (MTRRphysBase_MSR(reg), base); wrmsr (MTRRphysMask_MSR(reg), mask);
Modified: trunk/src/include/cpu/x86/mtrr.h ============================================================================== --- trunk/src/include/cpu/x86/mtrr.h Wed Jan 19 07:31:24 2011 (r6271) +++ trunk/src/include/cpu/x86/mtrr.h Wed Jan 19 07:32:35 2011 (r6272) @@ -21,6 +21,8 @@ #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
+#define MTRRphysMaskValid (1 << 11) + #define NUM_FIXED_RANGES 88 #define MTRRfix64K_00000_MSR 0x250 #define MTRRfix16K_80000_MSR 0x258