Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1771
-gerrit
commit 508e0aa9ff5f7ab76ad48f0863ab56e7a181919c Author: Stefan Reinauer reinauer@chromium.org Date: Thu Aug 16 14:05:42 2012 -0700
SandyBridge/IvyBridge: Add IFD and ME firmware automatically
right now coreboot's build process produces images that are not booting on actual hardware because they are smaller than the actual flash device and also don't have an IFD nor an ME firmware in them. In order to produce bootable images, you needed a wrapper script / extra step until now. With this change, the resulting coreboot.rom is actually bootable.
Change-Id: I82714069fb004d4badc41698747a704bd9fed4da Signed-off-by: Stefan Reinauer reinauer@google.com --- Makefile.inc | 7 ++++++- src/arch/x86/Makefile.inc | 2 +- src/southbridge/intel/bd82x6x/Makefile.inc | 16 ++++++++++++++++ 3 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/Makefile.inc b/Makefile.inc index e499bac..b1fbbee 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -166,7 +166,7 @@ CFLAGS += -Werror endif CFLAGS += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
-additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/options +additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/ifdtool $(objutil)/options
####################################################################### # generate build support files @@ -224,6 +224,11 @@ $(ROMCC): $(top)/util/romcc/romcc.c @# http://www.coreboot.org/pipermail/coreboot/2010-February/055825.html $(HOSTCC) -g $(STACK) -Wall -o $@ $<
+IFDTOOL:=$(objutil)/ifdtool/ifdtool +$(IFDTOOL): $(top)/util/ifdtool/ifdtool.c + @printf " HOSTCC $(subst $(obj)/,,$(@))\n" + $(HOSTCC) $(HOSTCFLAGS) -o $@ $< + ####################################################################### # needed objects that every mainboard uses # Creation of these is architecture and mainboard independent diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 868f159..b823db0 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -74,7 +74,7 @@ $(obj)/coreboot.pre1: $(CBFSTOOL) mv $(obj)/coreboot.rom $@ endif
-$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) +$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) @printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre $@.tmp if [ -f $(objcbfs)/coreboot_ap.elf ]; \ diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index c588341..7abf4f2 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -17,6 +17,11 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
+# Run an intermediate step when producing coreboot.rom +# that adds additional components to the final firmware +# image outside of CBFS +INTERMEDIATE:=bd82x6x_add_me + driver-y += pch.c driver-y += azalia.c driver-y += lpc.c @@ -45,3 +50,14 @@ ramstage-$(CONFIG_USBDEBUG) += usb_debug.c smm-$(CONFIG_USBDEBUG) += usb_debug.c romstage-y += reset.c
+$(INTERMEDIATE): $(obj)/coreboot.pre $(IFDTOOL) + printf " DD Adding Intel Firmware Descriptor\n" + dd if=3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin \ + of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 + printf " IFDTOOL me.bin -> coreboot.pre\n" + $(objutil)/ifdtool/ifdtool \ + -i ME:3rdparty/mainboard/$(MAINBOARDDIR)/me.bin \ + $(obj)/coreboot.pre + mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre + +PHONY += $$(INTERMEDIATE)