Dell - Internal Use - Confidential
Hi Matt, Thanks for the prompt response. I am using Rangeley FSP in my coreboot environment and I don’t see mrc cache in the coreboot region even though I chose to use MRC Cache in the config. Performing operation on 'COREBOOT' region... Name Offset Type Size cbfs master header 0x0 cbfs header 32 fallback/romstage 0x80 stage 27612 cpu_microcode_blob.bin 0x6cc0 microcode 167936 fallback/ramstage 0x2fd40 stage 121204 config 0x4d700 raw 539 revision 0x4d980 raw 588 cmos_layout.bin 0x4dc40 cmos_layout 1320 fallback/dsdt.aml 0x4e1c0 raw 8074 fallback/payload 0x501c0 payload 648600 img/memtest 0xee7c0 payload 180268 (empty) 0x11a840 null 415320 fsp.bin 0x17fec0 fsp 389120 (empty) 0x1def00 null 132504 bootblock 0x1ff4c0 bootblock 2560
I had built the tianocore long before(may be 6 months back) and I am pretty sure I chose release payload.
Thanks, Sibi From: Matt DeVillier [mailto:matt.devillier@gmail.com] Sent: Friday, March 24, 2017 2:23 PM To: Rajasekaran, Sibi Sibi_Rajasekaran@Dell.com Cc: Zoran Stojsavljevic zoran.stojsavljevic@gmail.com; coreboot coreboot@coreboot.org Subject: Re: [coreboot] Maintain boot order for multiple EFI based OS
On Fri, Mar 24, 2017 at 6:26 PM, <Sibi.Rajasekaran@dell.commailto:Sibi.Rajasekaran@dell.com> wrote:
For your question, takes around 26 seconds from power On till Tianocore execute completion. Looking at reducing this boot time.
Sibi, if you're not using mrc cache for RAM training, that's likely contributing 10s or so at least. Have you enabled coreboot timestamps and used cbmem to examine time to payload execute? Also, building Tianocore in debug (vs release) mode adds a bit of time as well due to the volume of serial output. I use coreboot + Tianocore on Baytrail N28xx/29xx (though not with FSP) and normal boot (after RAM training) with a release payload is on the order of 2s, with coreboot taking about 6-700ms of that.