Marc Jones (marcj303@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/94
-gerrit
commit d9b19420728cf7bab913bd8f88d5fe34125b5664 Author: Marc Jones marcj303@gmail.com Date: Tue Jul 12 23:02:03 2011 -0600
Set SB800 ROM decode size based on kconfig.
Change-Id: I46ea26b5534064fe1c7e2ce2b2f12cacf18a4d4d Signed-off-by: Marc Jones marcj303@gmail.com --- src/southbridge/amd/cimx/sb800/bootblock.c | 5 ++--- src/southbridge/amd/sb800/bootblock.c | 2 +- 2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index aaec03c..170276a 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -49,10 +49,9 @@ static void enable_rom(void) dword |= (1 << 0) | (1 << 1) | (1 << 4) | (1 << 6) | (1 << 21); pci_io_write_config32(dev, 0x48, dword);
- /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */ - /* Set the 4MB enable bits */ + /* Enable rom access */ word = pci_io_read_config16(dev, 0x6c); - word = 0xFFC0; + word = 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6); pci_io_write_config16(dev, 0x6c, word); }
diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c index 82d80f0..18eae24 100644 --- a/src/southbridge/amd/sb800/bootblock.c +++ b/src/southbridge/amd/sb800/bootblock.c @@ -57,7 +57,7 @@ static void sb800_enable_rom(void) * 0xffe0(0000): 2MB * 0xffc0(0000): 4MB */ - pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */ + pci_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); /* Enable LPC ROM range end at 0xffff(ffff). */ pci_write_config16(dev, 0x6e, 0xffff); }