Hello, everyone.
First of all, I would like to thanks and to congratulate all the community who helps to develop and to optimize this great project. Keep it up :)
I would appreciate if you can give me some opinions or point me to someone who will, regarding the Open Issues I present below (3.1 and 3.2). Trying to give you a brief contextualization of my status before and after Coreboot.
*1) Init:* -------- Recently I bought a refurbished x220 and flashed it with a custom BIOS (Lenovo ThinkPad x220_1.40-(8DET70WW)-8duj26us_NWL_ADV_AES_PM_Speedo) because I wanted to unlock the RAM speed to be 1866MHz (max RAM speed is locked to 1333Mhz in official BIOS), white-list some Wi-Fi cards, Advanced Chipset Config menu, etc.
This custom BIOS worked perfectly until I changed some settings related with Intel VT-x. If I recall correctly, I activated SR-IOV for PCI-E, saved and exited and after that x220 = BRICKED.
I tried every typical troubleshooting/workaround (Removing as much HW as possible, unplug BIOS battery for hours, etc), nothing worked. x220 BIOS never booted again and the machine was in a constant boot loop. Don't know why/how this happened in the first place, but since it is a custom BIOS and it is very hard to reach the developer, I knew I could never get it to work without an intrusive method...
*2) Coreboot as Salvation:* ------------------------- I started to look for alternatives, and luckily, Coreboot supports x220 since a couple of months ago :) After dealing with all the learning curve to understand the minimal requirements to compile and install Coreboot (tricky part is basically the need for HW flashing) I managed to get a working BIOS and x220 is now (almost 100%) operational :) I've read and used the blobs from the "damaged" custom BIOS. I'm not sure if this can affect the functionality of Coreboot. Apparently, it does not.
*(Let me know if anyone of you need details/help about/with the HW flashing in this type of chip (MX25L6406E/MX25L6408E)).* *3) Coreboot rocks but... Current Open issues:* --------------------------------------------- I decided to use coreboot-4.4 release instead of git-master. As payload I'm using SeaBIOS (booting Archlinux with Syslinux as bootloader).
*3.1) RAM speed:* --------------- I've 2 x 8GB DRR3-1866MHz installed. The 16GB are detected but the speed reported is just 667MHz. With the official BIOS, the max speed was 1333Mhz. Don't know how Coreboot is handling this subject in this particular main-board... DDR timings are a little bit confusing to me, I guess...
Before, with dmidecode -t 17 the speed was 1333Mhz and now it is just 667Mhz... This 667MHz speed I get with coreboot is 2x667=1333Mhz or in reality is 2x333MHz? In "northbridge/intel/sandybridge/raminit.c" we can see the following statement:
/* Maximum supported DDR3 frequency is 1066MHz (DDR3 2133) so make sure * we cap it if we have faster DIMMs. * Then, align it to the closest JEDEC standard frequency */
*=> So, if I'm understanding it correctly, current 667 Mhz is not the maximum * *speed supported.Any idea on how I can get higher speeds?*
*3.2) TP-SMAPI: * -------------- Looks like tp-smapi is not available using Coreboot. It was OK with the official and custom BIOS before.
From what I've read, this is not a Coreboot limitation... Not sure if the
blobs/EC are not ok for tp-smapi now... I use tp-smapi for battery threshold, etc. TLP http://linrunner.de/en/tlp/tlp.htmlalso uses tp-smapi. So it is kinda of important to me.
*=> Anyone using tp-smapi with no problems out there?*
*3.3) Config files:* ------------------ coreboot - http://pastebin.com/9ymtxLBW seabios - http://pastebin.com/rUU7ajRH cmos.default - http://pastebin.com/Pm5vS15R
Thanks in advance, guys. All the best \o
--sigkill